Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2009 |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, |
| 20 | * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 21 | * SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Daniel Vetter <daniel@ffwll.ch> |
| 25 | * |
| 26 | * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c |
| 27 | */ |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 28 | #include <drm/drmP.h> |
| 29 | #include <drm/i915_drm.h> |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 30 | #include "i915_drv.h" |
| 31 | #include "i915_reg.h" |
| 32 | #include "intel_drv.h" |
| 33 | |
| 34 | /* Limits for overlay size. According to intel doc, the real limits are: |
| 35 | * Y width: 4095, UV width (planar): 2047, Y height: 2047, |
| 36 | * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use |
| 37 | * the mininum of both. */ |
| 38 | #define IMAGE_MAX_WIDTH 2048 |
| 39 | #define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */ |
| 40 | /* on 830 and 845 these large limits result in the card hanging */ |
| 41 | #define IMAGE_MAX_WIDTH_LEGACY 1024 |
| 42 | #define IMAGE_MAX_HEIGHT_LEGACY 1088 |
| 43 | |
| 44 | /* overlay register definitions */ |
| 45 | /* OCMD register */ |
| 46 | #define OCMD_TILED_SURFACE (0x1<<19) |
| 47 | #define OCMD_MIRROR_MASK (0x3<<17) |
| 48 | #define OCMD_MIRROR_MODE (0x3<<17) |
| 49 | #define OCMD_MIRROR_HORIZONTAL (0x1<<17) |
| 50 | #define OCMD_MIRROR_VERTICAL (0x2<<17) |
| 51 | #define OCMD_MIRROR_BOTH (0x3<<17) |
| 52 | #define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */ |
| 53 | #define OCMD_UV_SWAP (0x1<<14) /* YVYU */ |
| 54 | #define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */ |
| 55 | #define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */ |
| 56 | #define OCMD_SOURCE_FORMAT_MASK (0xf<<10) |
| 57 | #define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */ |
| 58 | #define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */ |
| 59 | #define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */ |
| 60 | #define OCMD_YUV_422_PACKED (0x8<<10) |
| 61 | #define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */ |
| 62 | #define OCMD_YUV_420_PLANAR (0xc<<10) |
| 63 | #define OCMD_YUV_422_PLANAR (0xd<<10) |
| 64 | #define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */ |
| 65 | #define OCMD_TVSYNCFLIP_PARITY (0x1<<9) |
| 66 | #define OCMD_TVSYNCFLIP_ENABLE (0x1<<7) |
Chris Wilson | d796136 | 2010-07-13 13:52:17 +0100 | [diff] [blame] | 67 | #define OCMD_BUF_TYPE_MASK (0x1<<5) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 68 | #define OCMD_BUF_TYPE_FRAME (0x0<<5) |
| 69 | #define OCMD_BUF_TYPE_FIELD (0x1<<5) |
| 70 | #define OCMD_TEST_MODE (0x1<<4) |
| 71 | #define OCMD_BUFFER_SELECT (0x3<<2) |
| 72 | #define OCMD_BUFFER0 (0x0<<2) |
| 73 | #define OCMD_BUFFER1 (0x1<<2) |
| 74 | #define OCMD_FIELD_SELECT (0x1<<2) |
| 75 | #define OCMD_FIELD0 (0x0<<1) |
| 76 | #define OCMD_FIELD1 (0x1<<1) |
| 77 | #define OCMD_ENABLE (0x1<<0) |
| 78 | |
| 79 | /* OCONFIG register */ |
| 80 | #define OCONF_PIPE_MASK (0x1<<18) |
| 81 | #define OCONF_PIPE_A (0x0<<18) |
| 82 | #define OCONF_PIPE_B (0x1<<18) |
| 83 | #define OCONF_GAMMA2_ENABLE (0x1<<16) |
| 84 | #define OCONF_CSC_MODE_BT601 (0x0<<5) |
| 85 | #define OCONF_CSC_MODE_BT709 (0x1<<5) |
| 86 | #define OCONF_CSC_BYPASS (0x1<<4) |
| 87 | #define OCONF_CC_OUT_8BIT (0x1<<3) |
| 88 | #define OCONF_TEST_MODE (0x1<<2) |
| 89 | #define OCONF_THREE_LINE_BUFFER (0x1<<0) |
| 90 | #define OCONF_TWO_LINE_BUFFER (0x0<<0) |
| 91 | |
| 92 | /* DCLRKM (dst-key) register */ |
| 93 | #define DST_KEY_ENABLE (0x1<<31) |
| 94 | #define CLK_RGB24_MASK 0x0 |
| 95 | #define CLK_RGB16_MASK 0x070307 |
| 96 | #define CLK_RGB15_MASK 0x070707 |
| 97 | #define CLK_RGB8I_MASK 0xffffff |
| 98 | |
| 99 | #define RGB16_TO_COLORKEY(c) \ |
| 100 | (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3)) |
| 101 | #define RGB15_TO_COLORKEY(c) \ |
| 102 | (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3)) |
| 103 | |
| 104 | /* overlay flip addr flag */ |
| 105 | #define OFC_UPDATE 0x1 |
| 106 | |
| 107 | /* polyphase filter coefficients */ |
| 108 | #define N_HORIZ_Y_TAPS 5 |
| 109 | #define N_VERT_Y_TAPS 3 |
| 110 | #define N_HORIZ_UV_TAPS 3 |
| 111 | #define N_VERT_UV_TAPS 3 |
| 112 | #define N_PHASES 17 |
| 113 | #define MAX_TAPS 5 |
| 114 | |
| 115 | /* memory bufferd overlay registers */ |
| 116 | struct overlay_registers { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 117 | u32 OBUF_0Y; |
| 118 | u32 OBUF_1Y; |
| 119 | u32 OBUF_0U; |
| 120 | u32 OBUF_0V; |
| 121 | u32 OBUF_1U; |
| 122 | u32 OBUF_1V; |
| 123 | u32 OSTRIDE; |
| 124 | u32 YRGB_VPH; |
| 125 | u32 UV_VPH; |
| 126 | u32 HORZ_PH; |
| 127 | u32 INIT_PHS; |
| 128 | u32 DWINPOS; |
| 129 | u32 DWINSZ; |
| 130 | u32 SWIDTH; |
| 131 | u32 SWIDTHSW; |
| 132 | u32 SHEIGHT; |
| 133 | u32 YRGBSCALE; |
| 134 | u32 UVSCALE; |
| 135 | u32 OCLRC0; |
| 136 | u32 OCLRC1; |
| 137 | u32 DCLRKV; |
| 138 | u32 DCLRKM; |
| 139 | u32 SCLRKVH; |
| 140 | u32 SCLRKVL; |
| 141 | u32 SCLRKEN; |
| 142 | u32 OCONFIG; |
| 143 | u32 OCMD; |
| 144 | u32 RESERVED1; /* 0x6C */ |
| 145 | u32 OSTART_0Y; |
| 146 | u32 OSTART_1Y; |
| 147 | u32 OSTART_0U; |
| 148 | u32 OSTART_0V; |
| 149 | u32 OSTART_1U; |
| 150 | u32 OSTART_1V; |
| 151 | u32 OTILEOFF_0Y; |
| 152 | u32 OTILEOFF_1Y; |
| 153 | u32 OTILEOFF_0U; |
| 154 | u32 OTILEOFF_0V; |
| 155 | u32 OTILEOFF_1U; |
| 156 | u32 OTILEOFF_1V; |
| 157 | u32 FASTHSCALE; /* 0xA0 */ |
| 158 | u32 UVSCALEV; /* 0xA4 */ |
| 159 | u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */ |
| 160 | u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */ |
| 161 | u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES]; |
| 162 | u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */ |
| 163 | u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES]; |
| 164 | u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */ |
| 165 | u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES]; |
| 166 | u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */ |
| 167 | u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES]; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 168 | }; |
| 169 | |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 170 | struct intel_overlay { |
| 171 | struct drm_device *dev; |
| 172 | struct intel_crtc *crtc; |
| 173 | struct drm_i915_gem_object *vid_bo; |
| 174 | struct drm_i915_gem_object *old_vid_bo; |
| 175 | int active; |
| 176 | int pfit_active; |
| 177 | u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */ |
| 178 | u32 color_key; |
| 179 | u32 brightness, contrast, saturation; |
| 180 | u32 old_xscale, old_yscale; |
| 181 | /* register access */ |
| 182 | u32 flip_addr; |
| 183 | struct drm_i915_gem_object *reg_bo; |
| 184 | /* flip handling */ |
| 185 | uint32_t last_flip_req; |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 186 | void (*flip_tail)(struct intel_overlay *); |
Chris Wilson | 23f09ce | 2010-08-12 13:53:37 +0100 | [diff] [blame] | 187 | }; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 188 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 189 | static struct overlay_registers __iomem * |
Chris Wilson | 8d74f65 | 2010-08-12 10:35:26 +0100 | [diff] [blame] | 190 | intel_overlay_map_regs(struct intel_overlay *overlay) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 191 | { |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 192 | struct drm_i915_private *dev_priv = overlay->dev->dev_private; |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 193 | struct overlay_registers __iomem *regs; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 194 | |
Chris Wilson | 9bb2ff7 | 2010-08-12 12:02:11 +0100 | [diff] [blame] | 195 | if (OVERLAY_NEEDS_PHYSICAL(overlay->dev)) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 196 | regs = (struct overlay_registers __iomem *)overlay->reg_bo->phys_handle->vaddr; |
Chris Wilson | 9bb2ff7 | 2010-08-12 12:02:11 +0100 | [diff] [blame] | 197 | else |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 198 | regs = io_mapping_map_wc(dev_priv->gtt.mappable, |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 199 | i915_gem_obj_ggtt_offset(overlay->reg_bo)); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 200 | |
Chris Wilson | 9bb2ff7 | 2010-08-12 12:02:11 +0100 | [diff] [blame] | 201 | return regs; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 202 | } |
| 203 | |
Chris Wilson | 9bb2ff7 | 2010-08-12 12:02:11 +0100 | [diff] [blame] | 204 | static void intel_overlay_unmap_regs(struct intel_overlay *overlay, |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 205 | struct overlay_registers __iomem *regs) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 206 | { |
Chris Wilson | 8d74f65 | 2010-08-12 10:35:26 +0100 | [diff] [blame] | 207 | if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev)) |
Chris Wilson | 9bb2ff7 | 2010-08-12 12:02:11 +0100 | [diff] [blame] | 208 | io_mapping_unmap(regs); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 209 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 210 | |
Chris Wilson | b6c028e | 2010-08-12 11:55:08 +0100 | [diff] [blame] | 211 | static int intel_overlay_do_wait_request(struct intel_overlay *overlay, |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 212 | void (*tail)(struct intel_overlay *)) |
Chris Wilson | b6c028e | 2010-08-12 11:55:08 +0100 | [diff] [blame] | 213 | { |
| 214 | struct drm_device *dev = overlay->dev; |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 215 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 216 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Chris Wilson | b6c028e | 2010-08-12 11:55:08 +0100 | [diff] [blame] | 217 | int ret; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 218 | |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 219 | BUG_ON(overlay->last_flip_req); |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 220 | ret = i915_add_request(ring, &overlay->last_flip_req); |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 221 | if (ret) |
| 222 | return ret; |
| 223 | |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 224 | overlay->flip_tail = tail; |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 225 | ret = i915_wait_seqno(ring, overlay->last_flip_req); |
Chris Wilson | b6c028e | 2010-08-12 11:55:08 +0100 | [diff] [blame] | 226 | if (ret) |
| 227 | return ret; |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 228 | i915_gem_retire_requests(dev); |
Chris Wilson | b6c028e | 2010-08-12 11:55:08 +0100 | [diff] [blame] | 229 | |
Chris Wilson | b6c028e | 2010-08-12 11:55:08 +0100 | [diff] [blame] | 230 | overlay->last_flip_req = 0; |
| 231 | return 0; |
| 232 | } |
| 233 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 234 | /* overlay needs to be disable in OCMD reg */ |
| 235 | static int intel_overlay_on(struct intel_overlay *overlay) |
| 236 | { |
| 237 | struct drm_device *dev = overlay->dev; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 238 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 239 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 240 | int ret; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 241 | |
| 242 | BUG_ON(overlay->active); |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 243 | overlay->active = 1; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 244 | |
Daniel Vetter | 6306cb4 | 2012-08-12 19:27:10 +0200 | [diff] [blame] | 245 | WARN_ON(IS_I830(dev) && !(dev_priv->quirks & QUIRK_PIPEA_FORCE)); |
Chris Wilson | 106dada | 2010-07-16 17:13:01 +0100 | [diff] [blame] | 246 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 247 | ret = intel_ring_begin(ring, 4); |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 248 | if (ret) |
| 249 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 250 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 251 | intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_ON); |
| 252 | intel_ring_emit(ring, overlay->flip_addr | OFC_UPDATE); |
| 253 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); |
| 254 | intel_ring_emit(ring, MI_NOOP); |
| 255 | intel_ring_advance(ring); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 256 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 257 | return intel_overlay_do_wait_request(overlay, NULL); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 258 | } |
| 259 | |
| 260 | /* overlay needs to be enabled in OCMD reg */ |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 261 | static int intel_overlay_continue(struct intel_overlay *overlay, |
| 262 | bool load_polyphase_filter) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 263 | { |
| 264 | struct drm_device *dev = overlay->dev; |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 265 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 266 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 267 | u32 flip_addr = overlay->flip_addr; |
| 268 | u32 tmp; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 269 | int ret; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 270 | |
| 271 | BUG_ON(!overlay->active); |
| 272 | |
| 273 | if (load_polyphase_filter) |
| 274 | flip_addr |= OFC_UPDATE; |
| 275 | |
| 276 | /* check for underruns */ |
| 277 | tmp = I915_READ(DOVSTA); |
| 278 | if (tmp & (1 << 17)) |
| 279 | DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp); |
| 280 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 281 | ret = intel_ring_begin(ring, 2); |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 282 | if (ret) |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 283 | return ret; |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 284 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 285 | intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); |
| 286 | intel_ring_emit(ring, flip_addr); |
| 287 | intel_ring_advance(ring); |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 288 | |
Mika Kuoppala | 0025c07 | 2013-06-12 12:35:30 +0300 | [diff] [blame] | 289 | return i915_add_request(ring, &overlay->last_flip_req); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 290 | } |
| 291 | |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 292 | static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 293 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 294 | struct drm_i915_gem_object *obj = overlay->old_vid_bo; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 295 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 296 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 297 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 298 | |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 299 | overlay->old_vid_bo = NULL; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 300 | } |
| 301 | |
Daniel Vetter | 12ca45f | 2037-04-25 10:08:26 +0200 | [diff] [blame] | 302 | static void intel_overlay_off_tail(struct intel_overlay *overlay) |
| 303 | { |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 304 | struct drm_i915_gem_object *obj = overlay->vid_bo; |
Daniel Vetter | 12ca45f | 2037-04-25 10:08:26 +0200 | [diff] [blame] | 305 | |
| 306 | /* never have the overlay hw on without showing a frame */ |
| 307 | BUG_ON(!overlay->vid_bo); |
Daniel Vetter | 12ca45f | 2037-04-25 10:08:26 +0200 | [diff] [blame] | 308 | |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 309 | i915_gem_object_ggtt_unpin(obj); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 310 | drm_gem_object_unreference(&obj->base); |
Daniel Vetter | 12ca45f | 2037-04-25 10:08:26 +0200 | [diff] [blame] | 311 | overlay->vid_bo = NULL; |
| 312 | |
| 313 | overlay->crtc->overlay = NULL; |
| 314 | overlay->crtc = NULL; |
| 315 | overlay->active = 0; |
| 316 | } |
| 317 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 318 | /* overlay needs to be disabled in OCMD reg */ |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 319 | static int intel_overlay_off(struct intel_overlay *overlay) |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 320 | { |
| 321 | struct drm_device *dev = overlay->dev; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 322 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 323 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 324 | u32 flip_addr = overlay->flip_addr; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 325 | int ret; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 326 | |
| 327 | BUG_ON(!overlay->active); |
| 328 | |
| 329 | /* According to intel docs the overlay hw may hang (when switching |
| 330 | * off) without loading the filter coeffs. It is however unclear whether |
| 331 | * this applies to the disabling of the overlay or to the switching off |
| 332 | * of the hw. Do it in both cases */ |
| 333 | flip_addr |= OFC_UPDATE; |
| 334 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 335 | ret = intel_ring_begin(ring, 6); |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 336 | if (ret) |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 337 | return ret; |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 338 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 339 | /* wait for overlay to go idle */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 340 | intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE); |
| 341 | intel_ring_emit(ring, flip_addr); |
| 342 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 343 | /* turn overlay off */ |
Daniel Vetter | a919398 | 2012-10-22 12:55:55 +0200 | [diff] [blame] | 344 | if (IS_I830(dev)) { |
| 345 | /* Workaround: Don't disable the overlay fully, since otherwise |
| 346 | * it dies on the next OVERLAY_ON cmd. */ |
| 347 | intel_ring_emit(ring, MI_NOOP); |
| 348 | intel_ring_emit(ring, MI_NOOP); |
| 349 | intel_ring_emit(ring, MI_NOOP); |
| 350 | } else { |
| 351 | intel_ring_emit(ring, MI_OVERLAY_FLIP | MI_OVERLAY_OFF); |
| 352 | intel_ring_emit(ring, flip_addr); |
| 353 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); |
| 354 | } |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 355 | intel_ring_advance(ring); |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 356 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 357 | return intel_overlay_do_wait_request(overlay, intel_overlay_off_tail); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 358 | } |
| 359 | |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 360 | /* recover from an interruption due to a signal |
| 361 | * We have to be careful not to repeat work forever an make forward progess. */ |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 362 | static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay) |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 363 | { |
| 364 | struct drm_device *dev = overlay->dev; |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 365 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 366 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 367 | int ret; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 368 | |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 369 | if (overlay->last_flip_req == 0) |
| 370 | return 0; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 371 | |
Ben Widawsky | 199b2bc | 2012-05-24 15:03:11 -0700 | [diff] [blame] | 372 | ret = i915_wait_seqno(ring, overlay->last_flip_req); |
Chris Wilson | b6c028e | 2010-08-12 11:55:08 +0100 | [diff] [blame] | 373 | if (ret) |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 374 | return ret; |
Ben Widawsky | b2da9fe | 2012-04-26 16:02:58 -0700 | [diff] [blame] | 375 | i915_gem_retire_requests(dev); |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 376 | |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 377 | if (overlay->flip_tail) |
| 378 | overlay->flip_tail(overlay); |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 379 | |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 380 | overlay->last_flip_req = 0; |
| 381 | return 0; |
| 382 | } |
| 383 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 384 | /* Wait for pending overlay flip and release old frame. |
| 385 | * Needs to be called before the overlay register are changed |
Chris Wilson | 8d74f65 | 2010-08-12 10:35:26 +0100 | [diff] [blame] | 386 | * via intel_overlay_(un)map_regs |
| 387 | */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 388 | static int intel_overlay_release_old_vid(struct intel_overlay *overlay) |
| 389 | { |
Chris Wilson | 5cd68c9 | 2010-08-12 12:21:54 +0100 | [diff] [blame] | 390 | struct drm_device *dev = overlay->dev; |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 391 | struct drm_i915_private *dev_priv = dev->dev_private; |
Oscar Mateo | a4872ba | 2014-05-22 14:13:33 +0100 | [diff] [blame] | 392 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 393 | int ret; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 394 | |
Chris Wilson | 5cd68c9 | 2010-08-12 12:21:54 +0100 | [diff] [blame] | 395 | /* Only wait if there is actually an old frame to release to |
| 396 | * guarantee forward progress. |
| 397 | */ |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 398 | if (!overlay->old_vid_bo) |
| 399 | return 0; |
| 400 | |
Chris Wilson | 5cd68c9 | 2010-08-12 12:21:54 +0100 | [diff] [blame] | 401 | if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) { |
| 402 | /* synchronous slowpath */ |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 403 | ret = intel_ring_begin(ring, 2); |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 404 | if (ret) |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 405 | return ret; |
Chris Wilson | e1f99ce | 2010-10-27 12:45:26 +0100 | [diff] [blame] | 406 | |
Daniel Vetter | 6d90c95 | 2012-04-26 23:28:05 +0200 | [diff] [blame] | 407 | intel_ring_emit(ring, MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP); |
| 408 | intel_ring_emit(ring, MI_NOOP); |
| 409 | intel_ring_advance(ring); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 410 | |
Chris Wilson | acb868d | 2012-09-26 13:47:30 +0100 | [diff] [blame] | 411 | ret = intel_overlay_do_wait_request(overlay, |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 412 | intel_overlay_release_old_vid_tail); |
Chris Wilson | 5cd68c9 | 2010-08-12 12:21:54 +0100 | [diff] [blame] | 413 | if (ret) |
| 414 | return ret; |
| 415 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 416 | |
Chris Wilson | 5cd68c9 | 2010-08-12 12:21:54 +0100 | [diff] [blame] | 417 | intel_overlay_release_old_vid_tail(overlay); |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 418 | |
| 419 | |
| 420 | i915_gem_track_fb(overlay->old_vid_bo, NULL, |
| 421 | INTEL_FRONTBUFFER_OVERLAY(overlay->crtc->pipe)); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 422 | return 0; |
| 423 | } |
| 424 | |
| 425 | struct put_image_params { |
| 426 | int format; |
| 427 | short dst_x; |
| 428 | short dst_y; |
| 429 | short dst_w; |
| 430 | short dst_h; |
| 431 | short src_w; |
| 432 | short src_scan_h; |
| 433 | short src_scan_w; |
| 434 | short src_h; |
| 435 | short stride_Y; |
| 436 | short stride_UV; |
| 437 | int offset_Y; |
| 438 | int offset_U; |
| 439 | int offset_V; |
| 440 | }; |
| 441 | |
| 442 | static int packed_depth_bytes(u32 format) |
| 443 | { |
| 444 | switch (format & I915_OVERLAY_DEPTH_MASK) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 445 | case I915_OVERLAY_YUV422: |
| 446 | return 4; |
| 447 | case I915_OVERLAY_YUV411: |
| 448 | /* return 6; not implemented */ |
| 449 | default: |
| 450 | return -EINVAL; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 451 | } |
| 452 | } |
| 453 | |
| 454 | static int packed_width_bytes(u32 format, short width) |
| 455 | { |
| 456 | switch (format & I915_OVERLAY_DEPTH_MASK) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 457 | case I915_OVERLAY_YUV422: |
| 458 | return width << 1; |
| 459 | default: |
| 460 | return -EINVAL; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 461 | } |
| 462 | } |
| 463 | |
| 464 | static int uv_hsubsampling(u32 format) |
| 465 | { |
| 466 | switch (format & I915_OVERLAY_DEPTH_MASK) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 467 | case I915_OVERLAY_YUV422: |
| 468 | case I915_OVERLAY_YUV420: |
| 469 | return 2; |
| 470 | case I915_OVERLAY_YUV411: |
| 471 | case I915_OVERLAY_YUV410: |
| 472 | return 4; |
| 473 | default: |
| 474 | return -EINVAL; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 475 | } |
| 476 | } |
| 477 | |
| 478 | static int uv_vsubsampling(u32 format) |
| 479 | { |
| 480 | switch (format & I915_OVERLAY_DEPTH_MASK) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 481 | case I915_OVERLAY_YUV420: |
| 482 | case I915_OVERLAY_YUV410: |
| 483 | return 2; |
| 484 | case I915_OVERLAY_YUV422: |
| 485 | case I915_OVERLAY_YUV411: |
| 486 | return 1; |
| 487 | default: |
| 488 | return -EINVAL; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 489 | } |
| 490 | } |
| 491 | |
| 492 | static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width) |
| 493 | { |
| 494 | u32 mask, shift, ret; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 495 | if (IS_GEN2(dev)) { |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 496 | mask = 0x1f; |
| 497 | shift = 5; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 498 | } else { |
| 499 | mask = 0x3f; |
| 500 | shift = 6; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 501 | } |
| 502 | ret = ((offset + width + mask) >> shift) - (offset >> shift); |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 503 | if (!IS_GEN2(dev)) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 504 | ret <<= 1; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 505 | ret -= 1; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 506 | return ret << 2; |
| 507 | } |
| 508 | |
| 509 | static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = { |
| 510 | 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0, |
| 511 | 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440, |
| 512 | 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0, |
| 513 | 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380, |
| 514 | 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320, |
| 515 | 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0, |
| 516 | 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260, |
| 517 | 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200, |
| 518 | 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0, |
| 519 | 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160, |
| 520 | 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120, |
| 521 | 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0, |
| 522 | 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0, |
| 523 | 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060, |
| 524 | 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040, |
| 525 | 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020, |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 526 | 0xb000, 0x3000, 0x0800, 0x3000, 0xb000 |
| 527 | }; |
| 528 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 529 | static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = { |
| 530 | 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60, |
| 531 | 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40, |
| 532 | 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880, |
| 533 | 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00, |
| 534 | 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0, |
| 535 | 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0, |
| 536 | 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240, |
| 537 | 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0, |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 538 | 0x3000, 0x0800, 0x3000 |
| 539 | }; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 540 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 541 | static void update_polyphase_filter(struct overlay_registers __iomem *regs) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 542 | { |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 543 | memcpy_toio(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs)); |
| 544 | memcpy_toio(regs->UV_HCOEFS, uv_static_hcoeffs, |
| 545 | sizeof(uv_static_hcoeffs)); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 546 | } |
| 547 | |
| 548 | static bool update_scaling_factors(struct intel_overlay *overlay, |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 549 | struct overlay_registers __iomem *regs, |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 550 | struct put_image_params *params) |
| 551 | { |
| 552 | /* fixed point with a 12 bit shift */ |
| 553 | u32 xscale, yscale, xscale_UV, yscale_UV; |
| 554 | #define FP_SHIFT 12 |
| 555 | #define FRACT_MASK 0xfff |
| 556 | bool scale_changed = false; |
| 557 | int uv_hscale = uv_hsubsampling(params->format); |
| 558 | int uv_vscale = uv_vsubsampling(params->format); |
| 559 | |
| 560 | if (params->dst_w > 1) |
| 561 | xscale = ((params->src_scan_w - 1) << FP_SHIFT) |
| 562 | /(params->dst_w); |
| 563 | else |
| 564 | xscale = 1 << FP_SHIFT; |
| 565 | |
| 566 | if (params->dst_h > 1) |
| 567 | yscale = ((params->src_scan_h - 1) << FP_SHIFT) |
| 568 | /(params->dst_h); |
| 569 | else |
| 570 | yscale = 1 << FP_SHIFT; |
| 571 | |
| 572 | /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/ |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 573 | xscale_UV = xscale/uv_hscale; |
| 574 | yscale_UV = yscale/uv_vscale; |
| 575 | /* make the Y scale to UV scale ratio an exact multiply */ |
| 576 | xscale = xscale_UV * uv_hscale; |
| 577 | yscale = yscale_UV * uv_vscale; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 578 | /*} else { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 579 | xscale_UV = 0; |
| 580 | yscale_UV = 0; |
| 581 | }*/ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 582 | |
| 583 | if (xscale != overlay->old_xscale || yscale != overlay->old_yscale) |
| 584 | scale_changed = true; |
| 585 | overlay->old_xscale = xscale; |
| 586 | overlay->old_yscale = yscale; |
| 587 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 588 | iowrite32(((yscale & FRACT_MASK) << 20) | |
| 589 | ((xscale >> FP_SHIFT) << 16) | |
| 590 | ((xscale & FRACT_MASK) << 3), |
| 591 | ®s->YRGBSCALE); |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 592 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 593 | iowrite32(((yscale_UV & FRACT_MASK) << 20) | |
| 594 | ((xscale_UV >> FP_SHIFT) << 16) | |
| 595 | ((xscale_UV & FRACT_MASK) << 3), |
| 596 | ®s->UVSCALE); |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 597 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 598 | iowrite32((((yscale >> FP_SHIFT) << 16) | |
| 599 | ((yscale_UV >> FP_SHIFT) << 0)), |
| 600 | ®s->UVSCALEV); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 601 | |
| 602 | if (scale_changed) |
| 603 | update_polyphase_filter(regs); |
| 604 | |
| 605 | return scale_changed; |
| 606 | } |
| 607 | |
| 608 | static void update_colorkey(struct intel_overlay *overlay, |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 609 | struct overlay_registers __iomem *regs) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 610 | { |
| 611 | u32 key = overlay->color_key; |
Chris Wilson | 6ba3ddd | 2010-08-12 09:30:58 +0100 | [diff] [blame] | 612 | |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 613 | switch (overlay->crtc->base.primary->fb->bits_per_pixel) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 614 | case 8: |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 615 | iowrite32(0, ®s->DCLRKV); |
| 616 | iowrite32(CLK_RGB8I_MASK | DST_KEY_ENABLE, ®s->DCLRKM); |
Chris Wilson | 6ba3ddd | 2010-08-12 09:30:58 +0100 | [diff] [blame] | 617 | break; |
| 618 | |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 619 | case 16: |
Matt Roper | f4510a2 | 2014-04-01 15:22:40 -0700 | [diff] [blame] | 620 | if (overlay->crtc->base.primary->fb->depth == 15) { |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 621 | iowrite32(RGB15_TO_COLORKEY(key), ®s->DCLRKV); |
| 622 | iowrite32(CLK_RGB15_MASK | DST_KEY_ENABLE, |
| 623 | ®s->DCLRKM); |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 624 | } else { |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 625 | iowrite32(RGB16_TO_COLORKEY(key), ®s->DCLRKV); |
| 626 | iowrite32(CLK_RGB16_MASK | DST_KEY_ENABLE, |
| 627 | ®s->DCLRKM); |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 628 | } |
Chris Wilson | 6ba3ddd | 2010-08-12 09:30:58 +0100 | [diff] [blame] | 629 | break; |
| 630 | |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 631 | case 24: |
| 632 | case 32: |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 633 | iowrite32(key, ®s->DCLRKV); |
| 634 | iowrite32(CLK_RGB24_MASK | DST_KEY_ENABLE, ®s->DCLRKM); |
Chris Wilson | 6ba3ddd | 2010-08-12 09:30:58 +0100 | [diff] [blame] | 635 | break; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 636 | } |
| 637 | } |
| 638 | |
| 639 | static u32 overlay_cmd_reg(struct put_image_params *params) |
| 640 | { |
| 641 | u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0; |
| 642 | |
| 643 | if (params->format & I915_OVERLAY_YUV_PLANAR) { |
| 644 | switch (params->format & I915_OVERLAY_DEPTH_MASK) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 645 | case I915_OVERLAY_YUV422: |
| 646 | cmd |= OCMD_YUV_422_PLANAR; |
| 647 | break; |
| 648 | case I915_OVERLAY_YUV420: |
| 649 | cmd |= OCMD_YUV_420_PLANAR; |
| 650 | break; |
| 651 | case I915_OVERLAY_YUV411: |
| 652 | case I915_OVERLAY_YUV410: |
| 653 | cmd |= OCMD_YUV_410_PLANAR; |
| 654 | break; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 655 | } |
| 656 | } else { /* YUV packed */ |
| 657 | switch (params->format & I915_OVERLAY_DEPTH_MASK) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 658 | case I915_OVERLAY_YUV422: |
| 659 | cmd |= OCMD_YUV_422_PACKED; |
| 660 | break; |
| 661 | case I915_OVERLAY_YUV411: |
| 662 | cmd |= OCMD_YUV_411_PACKED; |
| 663 | break; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 664 | } |
| 665 | |
| 666 | switch (params->format & I915_OVERLAY_SWAP_MASK) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 667 | case I915_OVERLAY_NO_SWAP: |
| 668 | break; |
| 669 | case I915_OVERLAY_UV_SWAP: |
| 670 | cmd |= OCMD_UV_SWAP; |
| 671 | break; |
| 672 | case I915_OVERLAY_Y_SWAP: |
| 673 | cmd |= OCMD_Y_SWAP; |
| 674 | break; |
| 675 | case I915_OVERLAY_Y_AND_UV_SWAP: |
| 676 | cmd |= OCMD_Y_AND_UV_SWAP; |
| 677 | break; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 678 | } |
| 679 | } |
| 680 | |
| 681 | return cmd; |
| 682 | } |
| 683 | |
Chris Wilson | 5fe82c5 | 2010-08-12 12:38:21 +0100 | [diff] [blame] | 684 | static int intel_overlay_do_put_image(struct intel_overlay *overlay, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 685 | struct drm_i915_gem_object *new_bo, |
Chris Wilson | 5fe82c5 | 2010-08-12 12:38:21 +0100 | [diff] [blame] | 686 | struct put_image_params *params) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 687 | { |
| 688 | int ret, tmp_width; |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 689 | struct overlay_registers __iomem *regs; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 690 | bool scale_changed = false; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 691 | struct drm_device *dev = overlay->dev; |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 692 | u32 swidth, swidthsw, sheight, ostride; |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 693 | enum pipe pipe = overlay->crtc->pipe; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 694 | |
| 695 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 696 | BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 697 | BUG_ON(!overlay); |
| 698 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 699 | ret = intel_overlay_release_old_vid(overlay); |
| 700 | if (ret != 0) |
| 701 | return ret; |
| 702 | |
Chris Wilson | 2da3b9b | 2011-04-14 09:41:17 +0100 | [diff] [blame] | 703 | ret = i915_gem_object_pin_to_display_plane(new_bo, 0, NULL); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 704 | if (ret != 0) |
| 705 | return ret; |
| 706 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 707 | ret = i915_gem_object_put_fence(new_bo); |
| 708 | if (ret) |
| 709 | goto out_unpin; |
| 710 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 711 | if (!overlay->active) { |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 712 | u32 oconfig; |
Chris Wilson | 8d74f65 | 2010-08-12 10:35:26 +0100 | [diff] [blame] | 713 | regs = intel_overlay_map_regs(overlay); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 714 | if (!regs) { |
| 715 | ret = -ENOMEM; |
| 716 | goto out_unpin; |
| 717 | } |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 718 | oconfig = OCONF_CC_OUT_8BIT; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 719 | if (IS_GEN4(overlay->dev)) |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 720 | oconfig |= OCONF_CSC_MODE_BT709; |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 721 | oconfig |= pipe == 0 ? |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 722 | OCONF_PIPE_A : OCONF_PIPE_B; |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 723 | iowrite32(oconfig, ®s->OCONFIG); |
Chris Wilson | 9bb2ff7 | 2010-08-12 12:02:11 +0100 | [diff] [blame] | 724 | intel_overlay_unmap_regs(overlay, regs); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 725 | |
| 726 | ret = intel_overlay_on(overlay); |
| 727 | if (ret != 0) |
| 728 | goto out_unpin; |
| 729 | } |
| 730 | |
Chris Wilson | 8d74f65 | 2010-08-12 10:35:26 +0100 | [diff] [blame] | 731 | regs = intel_overlay_map_regs(overlay); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 732 | if (!regs) { |
| 733 | ret = -ENOMEM; |
| 734 | goto out_unpin; |
| 735 | } |
| 736 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 737 | iowrite32((params->dst_y << 16) | params->dst_x, ®s->DWINPOS); |
| 738 | iowrite32((params->dst_h << 16) | params->dst_w, ®s->DWINSZ); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 739 | |
| 740 | if (params->format & I915_OVERLAY_YUV_PACKED) |
| 741 | tmp_width = packed_width_bytes(params->format, params->src_w); |
| 742 | else |
| 743 | tmp_width = params->src_w; |
| 744 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 745 | swidth = params->src_w; |
| 746 | swidthsw = calc_swidthsw(overlay->dev, params->offset_Y, tmp_width); |
| 747 | sheight = params->src_h; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 748 | iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_Y, ®s->OBUF_0Y); |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 749 | ostride = params->stride_Y; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 750 | |
| 751 | if (params->format & I915_OVERLAY_YUV_PLANAR) { |
| 752 | int uv_hscale = uv_hsubsampling(params->format); |
| 753 | int uv_vscale = uv_vsubsampling(params->format); |
| 754 | u32 tmp_U, tmp_V; |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 755 | swidth |= (params->src_w/uv_hscale) << 16; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 756 | tmp_U = calc_swidthsw(overlay->dev, params->offset_U, |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 757 | params->src_w/uv_hscale); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 758 | tmp_V = calc_swidthsw(overlay->dev, params->offset_V, |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 759 | params->src_w/uv_hscale); |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 760 | swidthsw |= max_t(u32, tmp_U, tmp_V) << 16; |
| 761 | sheight |= (params->src_h/uv_vscale) << 16; |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 762 | iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_U, ®s->OBUF_0U); |
| 763 | iowrite32(i915_gem_obj_ggtt_offset(new_bo) + params->offset_V, ®s->OBUF_0V); |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 764 | ostride |= params->stride_UV << 16; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 765 | } |
| 766 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 767 | iowrite32(swidth, ®s->SWIDTH); |
| 768 | iowrite32(swidthsw, ®s->SWIDTHSW); |
| 769 | iowrite32(sheight, ®s->SHEIGHT); |
| 770 | iowrite32(ostride, ®s->OSTRIDE); |
| 771 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 772 | scale_changed = update_scaling_factors(overlay, regs, params); |
| 773 | |
| 774 | update_colorkey(overlay, regs); |
| 775 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 776 | iowrite32(overlay_cmd_reg(params), ®s->OCMD); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 777 | |
Chris Wilson | 9bb2ff7 | 2010-08-12 12:02:11 +0100 | [diff] [blame] | 778 | intel_overlay_unmap_regs(overlay, regs); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 779 | |
Chris Wilson | 8dc5d14 | 2010-08-12 12:36:12 +0100 | [diff] [blame] | 780 | ret = intel_overlay_continue(overlay, scale_changed); |
| 781 | if (ret) |
| 782 | goto out_unpin; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 783 | |
Daniel Vetter | a071fa0 | 2014-06-18 23:28:09 +0200 | [diff] [blame] | 784 | i915_gem_track_fb(overlay->vid_bo, new_bo, |
| 785 | INTEL_FRONTBUFFER_OVERLAY(pipe)); |
| 786 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 787 | overlay->old_vid_bo = overlay->vid_bo; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 788 | overlay->vid_bo = new_bo; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 789 | |
Daniel Vetter | f99d706 | 2014-06-19 16:01:59 +0200 | [diff] [blame] | 790 | intel_frontbuffer_flip(dev, |
| 791 | INTEL_FRONTBUFFER_OVERLAY(pipe)); |
| 792 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 793 | return 0; |
| 794 | |
| 795 | out_unpin: |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 796 | i915_gem_object_ggtt_unpin(new_bo); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 797 | return ret; |
| 798 | } |
| 799 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 800 | int intel_overlay_switch_off(struct intel_overlay *overlay) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 801 | { |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 802 | struct overlay_registers __iomem *regs; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 803 | struct drm_device *dev = overlay->dev; |
Chris Wilson | 5dcdbcb | 2010-08-12 13:50:28 +0100 | [diff] [blame] | 804 | int ret; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 805 | |
| 806 | BUG_ON(!mutex_is_locked(&dev->struct_mutex)); |
Rob Clark | 51fd371 | 2013-11-19 12:10:12 -0500 | [diff] [blame] | 807 | BUG_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex)); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 808 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 809 | ret = intel_overlay_recover_from_interrupt(overlay); |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 810 | if (ret != 0) |
| 811 | return ret; |
Daniel Vetter | 9bedb97 | 2009-11-30 15:55:49 +0100 | [diff] [blame] | 812 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 813 | if (!overlay->active) |
| 814 | return 0; |
| 815 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 816 | ret = intel_overlay_release_old_vid(overlay); |
| 817 | if (ret != 0) |
| 818 | return ret; |
| 819 | |
Chris Wilson | 8d74f65 | 2010-08-12 10:35:26 +0100 | [diff] [blame] | 820 | regs = intel_overlay_map_regs(overlay); |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 821 | iowrite32(0, ®s->OCMD); |
Chris Wilson | 9bb2ff7 | 2010-08-12 12:02:11 +0100 | [diff] [blame] | 822 | intel_overlay_unmap_regs(overlay, regs); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 823 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 824 | ret = intel_overlay_off(overlay); |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 825 | if (ret != 0) |
| 826 | return ret; |
| 827 | |
Daniel Vetter | 12ca45f | 2037-04-25 10:08:26 +0200 | [diff] [blame] | 828 | intel_overlay_off_tail(overlay); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 829 | return 0; |
| 830 | } |
| 831 | |
| 832 | static int check_overlay_possible_on_crtc(struct intel_overlay *overlay, |
| 833 | struct intel_crtc *crtc) |
| 834 | { |
Chris Wilson | f7abfe8 | 2010-09-13 14:19:16 +0100 | [diff] [blame] | 835 | if (!crtc->active) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 836 | return -EINVAL; |
| 837 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 838 | /* can't use the overlay with double wide pipe */ |
Ville Syrjälä | 4926cb7 | 2013-09-04 18:30:07 +0300 | [diff] [blame] | 839 | if (crtc->config.double_wide) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 840 | return -EINVAL; |
| 841 | |
| 842 | return 0; |
| 843 | } |
| 844 | |
| 845 | static void update_pfit_vscale_ratio(struct intel_overlay *overlay) |
| 846 | { |
| 847 | struct drm_device *dev = overlay->dev; |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 848 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 849 | u32 pfit_control = I915_READ(PFIT_CONTROL); |
Chris Wilson | 446d218 | 2010-08-12 11:15:58 +0100 | [diff] [blame] | 850 | u32 ratio; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 851 | |
| 852 | /* XXX: This is not the same logic as in the xorg driver, but more in |
Chris Wilson | 446d218 | 2010-08-12 11:15:58 +0100 | [diff] [blame] | 853 | * line with the intel documentation for the i965 |
| 854 | */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 855 | if (INTEL_INFO(dev)->gen >= 4) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 856 | /* on i965 use the PGM reg to read out the autoscaler values */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 857 | ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965; |
| 858 | } else { |
Chris Wilson | 446d218 | 2010-08-12 11:15:58 +0100 | [diff] [blame] | 859 | if (pfit_control & VERT_AUTO_SCALE) |
| 860 | ratio = I915_READ(PFIT_AUTO_RATIOS); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 861 | else |
Chris Wilson | 446d218 | 2010-08-12 11:15:58 +0100 | [diff] [blame] | 862 | ratio = I915_READ(PFIT_PGM_RATIOS); |
| 863 | ratio >>= PFIT_VERT_SCALE_SHIFT; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 864 | } |
| 865 | |
| 866 | overlay->pfit_vscale_ratio = ratio; |
| 867 | } |
| 868 | |
| 869 | static int check_overlay_dst(struct intel_overlay *overlay, |
| 870 | struct drm_intel_overlay_put_image *rec) |
| 871 | { |
| 872 | struct drm_display_mode *mode = &overlay->crtc->base.mode; |
| 873 | |
Daniel Vetter | 75c1399 | 2012-01-28 23:48:46 +0100 | [diff] [blame] | 874 | if (rec->dst_x < mode->hdisplay && |
| 875 | rec->dst_x + rec->dst_width <= mode->hdisplay && |
| 876 | rec->dst_y < mode->vdisplay && |
| 877 | rec->dst_y + rec->dst_height <= mode->vdisplay) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 878 | return 0; |
| 879 | else |
| 880 | return -EINVAL; |
| 881 | } |
| 882 | |
| 883 | static int check_overlay_scaling(struct put_image_params *rec) |
| 884 | { |
| 885 | u32 tmp; |
| 886 | |
| 887 | /* downscaling limit is 8.0 */ |
| 888 | tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16; |
| 889 | if (tmp > 7) |
| 890 | return -EINVAL; |
| 891 | tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16; |
| 892 | if (tmp > 7) |
| 893 | return -EINVAL; |
| 894 | |
| 895 | return 0; |
| 896 | } |
| 897 | |
| 898 | static int check_overlay_src(struct drm_device *dev, |
| 899 | struct drm_intel_overlay_put_image *rec, |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 900 | struct drm_i915_gem_object *new_bo) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 901 | { |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 902 | int uv_hscale = uv_hsubsampling(rec->flags); |
| 903 | int uv_vscale = uv_vsubsampling(rec->flags); |
Dan Carpenter | 8f28f54 | 2010-10-27 23:17:25 +0200 | [diff] [blame] | 904 | u32 stride_mask; |
| 905 | int depth; |
| 906 | u32 tmp; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 907 | |
| 908 | /* check src dimensions */ |
| 909 | if (IS_845G(dev) || IS_I830(dev)) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 910 | if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY || |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 911 | rec->src_width > IMAGE_MAX_WIDTH_LEGACY) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 912 | return -EINVAL; |
| 913 | } else { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 914 | if (rec->src_height > IMAGE_MAX_HEIGHT || |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 915 | rec->src_width > IMAGE_MAX_WIDTH) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 916 | return -EINVAL; |
| 917 | } |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 918 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 919 | /* better safe than sorry, use 4 as the maximal subsampling ratio */ |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 920 | if (rec->src_height < N_VERT_Y_TAPS*4 || |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 921 | rec->src_width < N_HORIZ_Y_TAPS*4) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 922 | return -EINVAL; |
| 923 | |
Chris Wilson | a1efd14 | 2010-07-12 19:35:38 +0100 | [diff] [blame] | 924 | /* check alignment constraints */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 925 | switch (rec->flags & I915_OVERLAY_TYPE_MASK) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 926 | case I915_OVERLAY_RGB: |
| 927 | /* not implemented */ |
| 928 | return -EINVAL; |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 929 | |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 930 | case I915_OVERLAY_YUV_PACKED: |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 931 | if (uv_vscale != 1) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 932 | return -EINVAL; |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 933 | |
| 934 | depth = packed_depth_bytes(rec->flags); |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 935 | if (depth < 0) |
| 936 | return depth; |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 937 | |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 938 | /* ignore UV planes */ |
| 939 | rec->stride_UV = 0; |
| 940 | rec->offset_U = 0; |
| 941 | rec->offset_V = 0; |
| 942 | /* check pixel alignment */ |
| 943 | if (rec->offset_Y % depth) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 944 | return -EINVAL; |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 945 | break; |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 946 | |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 947 | case I915_OVERLAY_YUV_PLANAR: |
| 948 | if (uv_vscale < 0 || uv_hscale < 0) |
| 949 | return -EINVAL; |
| 950 | /* no offset restrictions for planar formats */ |
| 951 | break; |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 952 | |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 953 | default: |
| 954 | return -EINVAL; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 955 | } |
| 956 | |
| 957 | if (rec->src_width % uv_hscale) |
| 958 | return -EINVAL; |
| 959 | |
| 960 | /* stride checking */ |
Chris Wilson | a1efd14 | 2010-07-12 19:35:38 +0100 | [diff] [blame] | 961 | if (IS_I830(dev) || IS_845G(dev)) |
| 962 | stride_mask = 255; |
| 963 | else |
| 964 | stride_mask = 63; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 965 | |
| 966 | if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask) |
| 967 | return -EINVAL; |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 968 | if (IS_GEN4(dev) && rec->stride_Y < 512) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 969 | return -EINVAL; |
| 970 | |
| 971 | tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ? |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 972 | 4096 : 8192; |
| 973 | if (rec->stride_Y > tmp || rec->stride_UV > 2*1024) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 974 | return -EINVAL; |
| 975 | |
| 976 | /* check buffer dimensions */ |
| 977 | switch (rec->flags & I915_OVERLAY_TYPE_MASK) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 978 | case I915_OVERLAY_RGB: |
| 979 | case I915_OVERLAY_YUV_PACKED: |
| 980 | /* always 4 Y values per depth pixels */ |
| 981 | if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y) |
| 982 | return -EINVAL; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 983 | |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 984 | tmp = rec->stride_Y*rec->src_height; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 985 | if (rec->offset_Y + tmp > new_bo->base.size) |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 986 | return -EINVAL; |
| 987 | break; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 988 | |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 989 | case I915_OVERLAY_YUV_PLANAR: |
| 990 | if (rec->src_width > rec->stride_Y) |
| 991 | return -EINVAL; |
| 992 | if (rec->src_width/uv_hscale > rec->stride_UV) |
| 993 | return -EINVAL; |
| 994 | |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 995 | tmp = rec->stride_Y * rec->src_height; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 996 | if (rec->offset_Y + tmp > new_bo->base.size) |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 997 | return -EINVAL; |
Chris Wilson | 9f7c3f4 | 2010-08-12 11:29:34 +0100 | [diff] [blame] | 998 | |
| 999 | tmp = rec->stride_UV * (rec->src_height / uv_vscale); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1000 | if (rec->offset_U + tmp > new_bo->base.size || |
| 1001 | rec->offset_V + tmp > new_bo->base.size) |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 1002 | return -EINVAL; |
| 1003 | break; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1004 | } |
| 1005 | |
| 1006 | return 0; |
| 1007 | } |
| 1008 | |
Chris Wilson | e9e331a | 2010-09-13 01:16:10 +0100 | [diff] [blame] | 1009 | /** |
| 1010 | * Return the pipe currently connected to the panel fitter, |
| 1011 | * or -1 if the panel fitter is not present or not in use |
| 1012 | */ |
| 1013 | static int intel_panel_fitter_pipe(struct drm_device *dev) |
| 1014 | { |
| 1015 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1016 | u32 pfit_control; |
| 1017 | |
| 1018 | /* i830 doesn't have a panel fitter */ |
Ville Syrjälä | dc9e7dec | 2014-01-10 14:06:45 +0200 | [diff] [blame] | 1019 | if (INTEL_INFO(dev)->gen <= 3 && (IS_I830(dev) || !IS_MOBILE(dev))) |
Chris Wilson | e9e331a | 2010-09-13 01:16:10 +0100 | [diff] [blame] | 1020 | return -1; |
| 1021 | |
| 1022 | pfit_control = I915_READ(PFIT_CONTROL); |
| 1023 | |
| 1024 | /* See if the panel fitter is in use */ |
| 1025 | if ((pfit_control & PFIT_ENABLE) == 0) |
| 1026 | return -1; |
| 1027 | |
| 1028 | /* 965 can place panel fitter on either pipe */ |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1029 | if (IS_GEN4(dev)) |
Chris Wilson | e9e331a | 2010-09-13 01:16:10 +0100 | [diff] [blame] | 1030 | return (pfit_control >> 29) & 0x3; |
| 1031 | |
| 1032 | /* older chips can only use pipe 1 */ |
| 1033 | return 1; |
| 1034 | } |
| 1035 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1036 | int intel_overlay_put_image(struct drm_device *dev, void *data, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1037 | struct drm_file *file_priv) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1038 | { |
| 1039 | struct drm_intel_overlay_put_image *put_image_rec = data; |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 1040 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1041 | struct intel_overlay *overlay; |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 1042 | struct drm_crtc *drmmode_crtc; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1043 | struct intel_crtc *crtc; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1044 | struct drm_i915_gem_object *new_bo; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1045 | struct put_image_params *params; |
| 1046 | int ret; |
| 1047 | |
Daniel Vetter | 1cff8f6 | 2012-04-24 09:55:08 +0200 | [diff] [blame] | 1048 | /* No need to check for DRIVER_MODESET - we don't set it up then. */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1049 | overlay = dev_priv->overlay; |
| 1050 | if (!overlay) { |
| 1051 | DRM_DEBUG("userspace bug: no overlay\n"); |
| 1052 | return -ENODEV; |
| 1053 | } |
| 1054 | |
| 1055 | if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) { |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1056 | drm_modeset_lock_all(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1057 | mutex_lock(&dev->struct_mutex); |
| 1058 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1059 | ret = intel_overlay_switch_off(overlay); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1060 | |
| 1061 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1062 | drm_modeset_unlock_all(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1063 | |
| 1064 | return ret; |
| 1065 | } |
| 1066 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 1067 | params = kmalloc(sizeof(*params), GFP_KERNEL); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1068 | if (!params) |
| 1069 | return -ENOMEM; |
| 1070 | |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 1071 | drmmode_crtc = drm_crtc_find(dev, put_image_rec->crtc_id); |
| 1072 | if (!drmmode_crtc) { |
Dan Carpenter | 915a428 | 2010-03-06 14:05:39 +0300 | [diff] [blame] | 1073 | ret = -ENOENT; |
| 1074 | goto out_free; |
| 1075 | } |
Rob Clark | 7707e65 | 2014-07-17 23:30:04 -0400 | [diff] [blame] | 1076 | crtc = to_intel_crtc(drmmode_crtc); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1077 | |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1078 | new_bo = to_intel_bo(drm_gem_object_lookup(dev, file_priv, |
| 1079 | put_image_rec->bo_handle)); |
Chris Wilson | c872522 | 2011-02-19 11:31:06 +0000 | [diff] [blame] | 1080 | if (&new_bo->base == NULL) { |
Dan Carpenter | 915a428 | 2010-03-06 14:05:39 +0300 | [diff] [blame] | 1081 | ret = -ENOENT; |
| 1082 | goto out_free; |
| 1083 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1084 | |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1085 | drm_modeset_lock_all(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1086 | mutex_lock(&dev->struct_mutex); |
| 1087 | |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1088 | if (new_bo->tiling_mode) { |
Daniel Vetter | 3b25b31 | 2014-02-14 14:06:06 +0100 | [diff] [blame] | 1089 | DRM_DEBUG_KMS("buffer used for overlay image can not be tiled\n"); |
Chris Wilson | d9e86c0 | 2010-11-10 16:40:20 +0000 | [diff] [blame] | 1090 | ret = -EINVAL; |
| 1091 | goto out_unlock; |
| 1092 | } |
| 1093 | |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1094 | ret = intel_overlay_recover_from_interrupt(overlay); |
Chris Wilson | b303cf9 | 2010-08-12 14:03:48 +0100 | [diff] [blame] | 1095 | if (ret != 0) |
| 1096 | goto out_unlock; |
Daniel Vetter | 03f77ea | 2009-09-15 22:57:37 +0200 | [diff] [blame] | 1097 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1098 | if (overlay->crtc != crtc) { |
| 1099 | struct drm_display_mode *mode = &crtc->base.mode; |
Chris Wilson | ce453d8 | 2011-02-21 14:43:56 +0000 | [diff] [blame] | 1100 | ret = intel_overlay_switch_off(overlay); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1101 | if (ret != 0) |
| 1102 | goto out_unlock; |
| 1103 | |
| 1104 | ret = check_overlay_possible_on_crtc(overlay, crtc); |
| 1105 | if (ret != 0) |
| 1106 | goto out_unlock; |
| 1107 | |
| 1108 | overlay->crtc = crtc; |
| 1109 | crtc->overlay = overlay; |
| 1110 | |
Chris Wilson | e9e331a | 2010-09-13 01:16:10 +0100 | [diff] [blame] | 1111 | /* line too wide, i.e. one-line-mode */ |
| 1112 | if (mode->hdisplay > 1024 && |
| 1113 | intel_panel_fitter_pipe(dev) == crtc->pipe) { |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1114 | overlay->pfit_active = 1; |
| 1115 | update_pfit_vscale_ratio(overlay); |
| 1116 | } else |
| 1117 | overlay->pfit_active = 0; |
| 1118 | } |
| 1119 | |
| 1120 | ret = check_overlay_dst(overlay, put_image_rec); |
| 1121 | if (ret != 0) |
| 1122 | goto out_unlock; |
| 1123 | |
| 1124 | if (overlay->pfit_active) { |
| 1125 | params->dst_y = ((((u32)put_image_rec->dst_y) << 12) / |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 1126 | overlay->pfit_vscale_ratio); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1127 | /* shifting right rounds downwards, so add 1 */ |
| 1128 | params->dst_h = ((((u32)put_image_rec->dst_height) << 12) / |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 1129 | overlay->pfit_vscale_ratio) + 1; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1130 | } else { |
| 1131 | params->dst_y = put_image_rec->dst_y; |
| 1132 | params->dst_h = put_image_rec->dst_height; |
| 1133 | } |
| 1134 | params->dst_x = put_image_rec->dst_x; |
| 1135 | params->dst_w = put_image_rec->dst_width; |
| 1136 | |
| 1137 | params->src_w = put_image_rec->src_width; |
| 1138 | params->src_h = put_image_rec->src_height; |
| 1139 | params->src_scan_w = put_image_rec->src_scan_width; |
| 1140 | params->src_scan_h = put_image_rec->src_scan_height; |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 1141 | if (params->src_scan_h > params->src_h || |
| 1142 | params->src_scan_w > params->src_w) { |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1143 | ret = -EINVAL; |
| 1144 | goto out_unlock; |
| 1145 | } |
| 1146 | |
| 1147 | ret = check_overlay_src(dev, put_image_rec, new_bo); |
| 1148 | if (ret != 0) |
| 1149 | goto out_unlock; |
| 1150 | params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK; |
| 1151 | params->stride_Y = put_image_rec->stride_Y; |
| 1152 | params->stride_UV = put_image_rec->stride_UV; |
| 1153 | params->offset_Y = put_image_rec->offset_Y; |
| 1154 | params->offset_U = put_image_rec->offset_U; |
| 1155 | params->offset_V = put_image_rec->offset_V; |
| 1156 | |
| 1157 | /* Check scaling after src size to prevent a divide-by-zero. */ |
| 1158 | ret = check_overlay_scaling(params); |
| 1159 | if (ret != 0) |
| 1160 | goto out_unlock; |
| 1161 | |
| 1162 | ret = intel_overlay_do_put_image(overlay, new_bo, params); |
| 1163 | if (ret != 0) |
| 1164 | goto out_unlock; |
| 1165 | |
| 1166 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1167 | drm_modeset_unlock_all(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1168 | |
| 1169 | kfree(params); |
| 1170 | |
| 1171 | return 0; |
| 1172 | |
| 1173 | out_unlock: |
| 1174 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1175 | drm_modeset_unlock_all(dev); |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1176 | drm_gem_object_unreference_unlocked(&new_bo->base); |
Dan Carpenter | 915a428 | 2010-03-06 14:05:39 +0300 | [diff] [blame] | 1177 | out_free: |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1178 | kfree(params); |
| 1179 | |
| 1180 | return ret; |
| 1181 | } |
| 1182 | |
| 1183 | static void update_reg_attrs(struct intel_overlay *overlay, |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 1184 | struct overlay_registers __iomem *regs) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1185 | { |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 1186 | iowrite32((overlay->contrast << 18) | (overlay->brightness & 0xff), |
| 1187 | ®s->OCLRC0); |
| 1188 | iowrite32(overlay->saturation, ®s->OCLRC1); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1189 | } |
| 1190 | |
| 1191 | static bool check_gamma_bounds(u32 gamma1, u32 gamma2) |
| 1192 | { |
| 1193 | int i; |
| 1194 | |
| 1195 | if (gamma1 & 0xff000000 || gamma2 & 0xff000000) |
| 1196 | return false; |
| 1197 | |
| 1198 | for (i = 0; i < 3; i++) { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 1199 | if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff)) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1200 | return false; |
| 1201 | } |
| 1202 | |
| 1203 | return true; |
| 1204 | } |
| 1205 | |
| 1206 | static bool check_gamma5_errata(u32 gamma5) |
| 1207 | { |
| 1208 | int i; |
| 1209 | |
| 1210 | for (i = 0; i < 3; i++) { |
| 1211 | if (((gamma5 >> i*8) & 0xff) == 0x80) |
| 1212 | return false; |
| 1213 | } |
| 1214 | |
| 1215 | return true; |
| 1216 | } |
| 1217 | |
| 1218 | static int check_gamma(struct drm_intel_overlay_attrs *attrs) |
| 1219 | { |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 1220 | if (!check_gamma_bounds(0, attrs->gamma0) || |
| 1221 | !check_gamma_bounds(attrs->gamma0, attrs->gamma1) || |
| 1222 | !check_gamma_bounds(attrs->gamma1, attrs->gamma2) || |
| 1223 | !check_gamma_bounds(attrs->gamma2, attrs->gamma3) || |
| 1224 | !check_gamma_bounds(attrs->gamma3, attrs->gamma4) || |
| 1225 | !check_gamma_bounds(attrs->gamma4, attrs->gamma5) || |
| 1226 | !check_gamma_bounds(attrs->gamma5, 0x00ffffff)) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1227 | return -EINVAL; |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 1228 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1229 | if (!check_gamma5_errata(attrs->gamma5)) |
| 1230 | return -EINVAL; |
Chris Wilson | 722506f | 2010-08-12 09:28:50 +0100 | [diff] [blame] | 1231 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1232 | return 0; |
| 1233 | } |
| 1234 | |
| 1235 | int intel_overlay_attrs(struct drm_device *dev, void *data, |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1236 | struct drm_file *file_priv) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1237 | { |
| 1238 | struct drm_intel_overlay_attrs *attrs = data; |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 1239 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1240 | struct intel_overlay *overlay; |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 1241 | struct overlay_registers __iomem *regs; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1242 | int ret; |
| 1243 | |
Daniel Vetter | 1cff8f6 | 2012-04-24 09:55:08 +0200 | [diff] [blame] | 1244 | /* No need to check for DRIVER_MODESET - we don't set it up then. */ |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1245 | overlay = dev_priv->overlay; |
| 1246 | if (!overlay) { |
| 1247 | DRM_DEBUG("userspace bug: no overlay\n"); |
| 1248 | return -ENODEV; |
| 1249 | } |
| 1250 | |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1251 | drm_modeset_lock_all(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1252 | mutex_lock(&dev->struct_mutex); |
| 1253 | |
Chris Wilson | 60fc332 | 2010-08-12 10:44:45 +0100 | [diff] [blame] | 1254 | ret = -EINVAL; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1255 | if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) { |
Chris Wilson | 60fc332 | 2010-08-12 10:44:45 +0100 | [diff] [blame] | 1256 | attrs->color_key = overlay->color_key; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1257 | attrs->brightness = overlay->brightness; |
Chris Wilson | 60fc332 | 2010-08-12 10:44:45 +0100 | [diff] [blame] | 1258 | attrs->contrast = overlay->contrast; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1259 | attrs->saturation = overlay->saturation; |
| 1260 | |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1261 | if (!IS_GEN2(dev)) { |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1262 | attrs->gamma0 = I915_READ(OGAMC0); |
| 1263 | attrs->gamma1 = I915_READ(OGAMC1); |
| 1264 | attrs->gamma2 = I915_READ(OGAMC2); |
| 1265 | attrs->gamma3 = I915_READ(OGAMC3); |
| 1266 | attrs->gamma4 = I915_READ(OGAMC4); |
| 1267 | attrs->gamma5 = I915_READ(OGAMC5); |
| 1268 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1269 | } else { |
Chris Wilson | 60fc332 | 2010-08-12 10:44:45 +0100 | [diff] [blame] | 1270 | if (attrs->brightness < -128 || attrs->brightness > 127) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1271 | goto out_unlock; |
Chris Wilson | 60fc332 | 2010-08-12 10:44:45 +0100 | [diff] [blame] | 1272 | if (attrs->contrast > 255) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1273 | goto out_unlock; |
Chris Wilson | 60fc332 | 2010-08-12 10:44:45 +0100 | [diff] [blame] | 1274 | if (attrs->saturation > 1023) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1275 | goto out_unlock; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1276 | |
Chris Wilson | 60fc332 | 2010-08-12 10:44:45 +0100 | [diff] [blame] | 1277 | overlay->color_key = attrs->color_key; |
| 1278 | overlay->brightness = attrs->brightness; |
| 1279 | overlay->contrast = attrs->contrast; |
| 1280 | overlay->saturation = attrs->saturation; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1281 | |
Chris Wilson | 8d74f65 | 2010-08-12 10:35:26 +0100 | [diff] [blame] | 1282 | regs = intel_overlay_map_regs(overlay); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1283 | if (!regs) { |
| 1284 | ret = -ENOMEM; |
| 1285 | goto out_unlock; |
| 1286 | } |
| 1287 | |
| 1288 | update_reg_attrs(overlay, regs); |
| 1289 | |
Chris Wilson | 9bb2ff7 | 2010-08-12 12:02:11 +0100 | [diff] [blame] | 1290 | intel_overlay_unmap_regs(overlay, regs); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1291 | |
| 1292 | if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) { |
Chris Wilson | a6c45cf | 2010-09-17 00:32:17 +0100 | [diff] [blame] | 1293 | if (IS_GEN2(dev)) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1294 | goto out_unlock; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1295 | |
| 1296 | if (overlay->active) { |
| 1297 | ret = -EBUSY; |
| 1298 | goto out_unlock; |
| 1299 | } |
| 1300 | |
| 1301 | ret = check_gamma(attrs); |
Chris Wilson | 60fc332 | 2010-08-12 10:44:45 +0100 | [diff] [blame] | 1302 | if (ret) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1303 | goto out_unlock; |
| 1304 | |
| 1305 | I915_WRITE(OGAMC0, attrs->gamma0); |
| 1306 | I915_WRITE(OGAMC1, attrs->gamma1); |
| 1307 | I915_WRITE(OGAMC2, attrs->gamma2); |
| 1308 | I915_WRITE(OGAMC3, attrs->gamma3); |
| 1309 | I915_WRITE(OGAMC4, attrs->gamma4); |
| 1310 | I915_WRITE(OGAMC5, attrs->gamma5); |
| 1311 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1312 | } |
| 1313 | |
Chris Wilson | 60fc332 | 2010-08-12 10:44:45 +0100 | [diff] [blame] | 1314 | ret = 0; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1315 | out_unlock: |
| 1316 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | a0e99e6 | 2012-12-02 01:05:46 +0100 | [diff] [blame] | 1317 | drm_modeset_unlock_all(dev); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1318 | |
| 1319 | return ret; |
| 1320 | } |
| 1321 | |
| 1322 | void intel_setup_overlay(struct drm_device *dev) |
| 1323 | { |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 1324 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1325 | struct intel_overlay *overlay; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1326 | struct drm_i915_gem_object *reg_bo; |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 1327 | struct overlay_registers __iomem *regs; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1328 | int ret; |
| 1329 | |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 1330 | if (!HAS_OVERLAY(dev)) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1331 | return; |
| 1332 | |
Daniel Vetter | b14c567 | 2013-09-19 12:18:32 +0200 | [diff] [blame] | 1333 | overlay = kzalloc(sizeof(*overlay), GFP_KERNEL); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1334 | if (!overlay) |
| 1335 | return; |
Chris Wilson | 79d2427 | 2011-06-28 11:27:47 +0100 | [diff] [blame] | 1336 | |
| 1337 | mutex_lock(&dev->struct_mutex); |
| 1338 | if (WARN_ON(dev_priv->overlay)) |
| 1339 | goto out_free; |
| 1340 | |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1341 | overlay->dev = dev; |
| 1342 | |
Daniel Vetter | f63a484 | 2013-07-23 19:24:38 +0200 | [diff] [blame] | 1343 | reg_bo = NULL; |
| 1344 | if (!OVERLAY_NEEDS_PHYSICAL(dev)) |
| 1345 | reg_bo = i915_gem_object_create_stolen(dev, PAGE_SIZE); |
Chris Wilson | 8040513 | 2012-11-15 11:32:29 +0000 | [diff] [blame] | 1346 | if (reg_bo == NULL) |
| 1347 | reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE); |
| 1348 | if (reg_bo == NULL) |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1349 | goto out_free; |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1350 | overlay->reg_bo = reg_bo; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1351 | |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 1352 | if (OVERLAY_NEEDS_PHYSICAL(dev)) { |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 1353 | ret = i915_gem_object_attach_phys(reg_bo, PAGE_SIZE); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1354 | if (ret) { |
| 1355 | DRM_ERROR("failed to attach phys overlay regs\n"); |
| 1356 | goto out_free_bo; |
| 1357 | } |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 1358 | overlay->flip_addr = reg_bo->phys_handle->busaddr; |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 1359 | } else { |
Daniel Vetter | 1ec9e26 | 2014-02-14 14:01:11 +0100 | [diff] [blame] | 1360 | ret = i915_gem_obj_ggtt_pin(reg_bo, PAGE_SIZE, PIN_MAPPABLE); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1361 | if (ret) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1362 | DRM_ERROR("failed to pin overlay register bo\n"); |
| 1363 | goto out_free_bo; |
| 1364 | } |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1365 | overlay->flip_addr = i915_gem_obj_ggtt_offset(reg_bo); |
Chris Wilson | 0ddc128 | 2010-08-12 09:35:00 +0100 | [diff] [blame] | 1366 | |
| 1367 | ret = i915_gem_object_set_to_gtt_domain(reg_bo, true); |
| 1368 | if (ret) { |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 1369 | DRM_ERROR("failed to move overlay register bo into the GTT\n"); |
| 1370 | goto out_unpin_bo; |
| 1371 | } |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1372 | } |
| 1373 | |
| 1374 | /* init all values */ |
| 1375 | overlay->color_key = 0x0101fe; |
| 1376 | overlay->brightness = -19; |
| 1377 | overlay->contrast = 75; |
| 1378 | overlay->saturation = 146; |
| 1379 | |
Chris Wilson | 8d74f65 | 2010-08-12 10:35:26 +0100 | [diff] [blame] | 1380 | regs = intel_overlay_map_regs(overlay); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1381 | if (!regs) |
Chris Wilson | 79d2427 | 2011-06-28 11:27:47 +0100 | [diff] [blame] | 1382 | goto out_unpin_bo; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1383 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 1384 | memset_io(regs, 0, sizeof(struct overlay_registers)); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1385 | update_polyphase_filter(regs); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1386 | update_reg_attrs(overlay, regs); |
| 1387 | |
Chris Wilson | 9bb2ff7 | 2010-08-12 12:02:11 +0100 | [diff] [blame] | 1388 | intel_overlay_unmap_regs(overlay, regs); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1389 | |
| 1390 | dev_priv->overlay = overlay; |
Chris Wilson | 79d2427 | 2011-06-28 11:27:47 +0100 | [diff] [blame] | 1391 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1392 | DRM_INFO("initialized overlay support\n"); |
| 1393 | return; |
| 1394 | |
Chris Wilson | 0ddc128 | 2010-08-12 09:35:00 +0100 | [diff] [blame] | 1395 | out_unpin_bo: |
Chris Wilson | 79d2427 | 2011-06-28 11:27:47 +0100 | [diff] [blame] | 1396 | if (!OVERLAY_NEEDS_PHYSICAL(dev)) |
Ben Widawsky | d7f46fc | 2013-12-06 14:10:55 -0800 | [diff] [blame] | 1397 | i915_gem_object_ggtt_unpin(reg_bo); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1398 | out_free_bo: |
Chris Wilson | 05394f3 | 2010-11-08 19:18:58 +0000 | [diff] [blame] | 1399 | drm_gem_object_unreference(®_bo->base); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1400 | out_free: |
Chris Wilson | 79d2427 | 2011-06-28 11:27:47 +0100 | [diff] [blame] | 1401 | mutex_unlock(&dev->struct_mutex); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1402 | kfree(overlay); |
| 1403 | return; |
| 1404 | } |
| 1405 | |
| 1406 | void intel_cleanup_overlay(struct drm_device *dev) |
| 1407 | { |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 1408 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1409 | |
Chris Wilson | 62cf4e6 | 2010-08-12 10:50:36 +0100 | [diff] [blame] | 1410 | if (!dev_priv->overlay) |
| 1411 | return; |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1412 | |
Chris Wilson | 62cf4e6 | 2010-08-12 10:50:36 +0100 | [diff] [blame] | 1413 | /* The bo's should be free'd by the generic code already. |
| 1414 | * Furthermore modesetting teardown happens beforehand so the |
| 1415 | * hardware should be off already */ |
| 1416 | BUG_ON(dev_priv->overlay->active); |
| 1417 | |
| 1418 | drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base); |
| 1419 | kfree(dev_priv->overlay); |
Daniel Vetter | 02e792f | 2009-09-15 22:57:34 +0200 | [diff] [blame] | 1420 | } |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1421 | |
| 1422 | struct intel_overlay_error_state { |
| 1423 | struct overlay_registers regs; |
| 1424 | unsigned long base; |
| 1425 | u32 dovsta; |
| 1426 | u32 isr; |
| 1427 | }; |
| 1428 | |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 1429 | static struct overlay_registers __iomem * |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 1430 | intel_overlay_map_regs_atomic(struct intel_overlay *overlay) |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1431 | { |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 1432 | struct drm_i915_private *dev_priv = overlay->dev->dev_private; |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 1433 | struct overlay_registers __iomem *regs; |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1434 | |
| 1435 | if (OVERLAY_NEEDS_PHYSICAL(overlay->dev)) |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 1436 | /* Cast to make sparse happy, but it's wc memory anyway, so |
| 1437 | * equivalent to the wc io mapping on X86. */ |
| 1438 | regs = (struct overlay_registers __iomem *) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 1439 | overlay->reg_bo->phys_handle->vaddr; |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1440 | else |
Ben Widawsky | 5d4545a | 2013-01-17 12:45:15 -0800 | [diff] [blame] | 1441 | regs = io_mapping_map_atomic_wc(dev_priv->gtt.mappable, |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1442 | i915_gem_obj_ggtt_offset(overlay->reg_bo)); |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1443 | |
| 1444 | return regs; |
| 1445 | } |
| 1446 | |
| 1447 | static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay, |
Ben Widawsky | 75020bc | 2012-04-16 14:07:43 -0700 | [diff] [blame] | 1448 | struct overlay_registers __iomem *regs) |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1449 | { |
| 1450 | if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev)) |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 1451 | io_mapping_unmap_atomic(regs); |
Chris Wilson | 3bd3c93 | 2010-08-19 08:19:30 +0100 | [diff] [blame] | 1452 | } |
| 1453 | |
| 1454 | |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1455 | struct intel_overlay_error_state * |
| 1456 | intel_overlay_capture_error_state(struct drm_device *dev) |
| 1457 | { |
Jani Nikula | d5d45cc | 2014-03-31 14:27:20 +0300 | [diff] [blame] | 1458 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1459 | struct intel_overlay *overlay = dev_priv->overlay; |
| 1460 | struct intel_overlay_error_state *error; |
| 1461 | struct overlay_registers __iomem *regs; |
| 1462 | |
| 1463 | if (!overlay || !overlay->active) |
| 1464 | return NULL; |
| 1465 | |
| 1466 | error = kmalloc(sizeof(*error), GFP_ATOMIC); |
| 1467 | if (error == NULL) |
| 1468 | return NULL; |
| 1469 | |
| 1470 | error->dovsta = I915_READ(DOVSTA); |
| 1471 | error->isr = I915_READ(ISR); |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 1472 | if (OVERLAY_NEEDS_PHYSICAL(overlay->dev)) |
Chris Wilson | 0073115 | 2014-05-21 12:42:56 +0100 | [diff] [blame] | 1473 | error->base = (__force long)overlay->reg_bo->phys_handle->vaddr; |
Chris Wilson | 31578148 | 2010-08-12 09:42:51 +0100 | [diff] [blame] | 1474 | else |
Ben Widawsky | f343c5f | 2013-07-05 14:41:04 -0700 | [diff] [blame] | 1475 | error->base = i915_gem_obj_ggtt_offset(overlay->reg_bo); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1476 | |
| 1477 | regs = intel_overlay_map_regs_atomic(overlay); |
| 1478 | if (!regs) |
| 1479 | goto err; |
| 1480 | |
| 1481 | memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers)); |
Linus Torvalds | c48c43e | 2010-10-26 18:57:59 -0700 | [diff] [blame] | 1482 | intel_overlay_unmap_regs_atomic(overlay, regs); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1483 | |
| 1484 | return error; |
| 1485 | |
| 1486 | err: |
| 1487 | kfree(error); |
| 1488 | return NULL; |
| 1489 | } |
| 1490 | |
| 1491 | void |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1492 | intel_overlay_print_error_state(struct drm_i915_error_state_buf *m, |
| 1493 | struct intel_overlay_error_state *error) |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1494 | { |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1495 | i915_error_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n", |
| 1496 | error->dovsta, error->isr); |
| 1497 | i915_error_printf(m, " Register file at 0x%08lx:\n", |
| 1498 | error->base); |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1499 | |
Mika Kuoppala | edc3d88 | 2013-05-23 13:55:35 +0300 | [diff] [blame] | 1500 | #define P(x) i915_error_printf(m, " " #x ": 0x%08x\n", error->regs.x) |
Chris Wilson | 6ef3d42 | 2010-08-04 20:26:07 +0100 | [diff] [blame] | 1501 | P(OBUF_0Y); |
| 1502 | P(OBUF_1Y); |
| 1503 | P(OBUF_0U); |
| 1504 | P(OBUF_0V); |
| 1505 | P(OBUF_1U); |
| 1506 | P(OBUF_1V); |
| 1507 | P(OSTRIDE); |
| 1508 | P(YRGB_VPH); |
| 1509 | P(UV_VPH); |
| 1510 | P(HORZ_PH); |
| 1511 | P(INIT_PHS); |
| 1512 | P(DWINPOS); |
| 1513 | P(DWINSZ); |
| 1514 | P(SWIDTH); |
| 1515 | P(SWIDTHSW); |
| 1516 | P(SHEIGHT); |
| 1517 | P(YRGBSCALE); |
| 1518 | P(UVSCALE); |
| 1519 | P(OCLRC0); |
| 1520 | P(OCLRC1); |
| 1521 | P(DCLRKV); |
| 1522 | P(DCLRKM); |
| 1523 | P(SCLRKVH); |
| 1524 | P(SCLRKVL); |
| 1525 | P(SCLRKEN); |
| 1526 | P(OCONFIG); |
| 1527 | P(OCMD); |
| 1528 | P(OSTART_0Y); |
| 1529 | P(OSTART_1Y); |
| 1530 | P(OSTART_0U); |
| 1531 | P(OSTART_0V); |
| 1532 | P(OSTART_1U); |
| 1533 | P(OSTART_1V); |
| 1534 | P(OTILEOFF_0Y); |
| 1535 | P(OTILEOFF_1Y); |
| 1536 | P(OTILEOFF_0U); |
| 1537 | P(OTILEOFF_0V); |
| 1538 | P(OTILEOFF_1U); |
| 1539 | P(OTILEOFF_1V); |
| 1540 | P(FASTHSCALE); |
| 1541 | P(UVSCALEV); |
| 1542 | #undef P |
| 1543 | } |