Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2013 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | */ |
| 23 | |
| 24 | #include "i915_drv.h" |
| 25 | #include "intel_drv.h" |
| 26 | |
| 27 | #define FORCEWAKE_ACK_TIMEOUT_MS 2 |
| 28 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 29 | #define __raw_i915_read8(dev_priv__, reg__) readb((dev_priv__)->regs + (reg__)) |
| 30 | #define __raw_i915_write8(dev_priv__, reg__, val__) writeb(val__, (dev_priv__)->regs + (reg__)) |
| 31 | |
| 32 | #define __raw_i915_read16(dev_priv__, reg__) readw((dev_priv__)->regs + (reg__)) |
| 33 | #define __raw_i915_write16(dev_priv__, reg__, val__) writew(val__, (dev_priv__)->regs + (reg__)) |
| 34 | |
| 35 | #define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__)) |
| 36 | #define __raw_i915_write32(dev_priv__, reg__, val__) writel(val__, (dev_priv__)->regs + (reg__)) |
| 37 | |
| 38 | #define __raw_i915_read64(dev_priv__, reg__) readq((dev_priv__)->regs + (reg__)) |
| 39 | #define __raw_i915_write64(dev_priv__, reg__, val__) writeq(val__, (dev_priv__)->regs + (reg__)) |
| 40 | |
| 41 | #define __raw_posting_read(dev_priv__, reg__) (void)__raw_i915_read32(dev_priv__, reg__) |
| 42 | |
Paulo Zanoni | b2ec142 | 2014-02-21 13:52:25 -0300 | [diff] [blame] | 43 | static void |
| 44 | assert_device_not_suspended(struct drm_i915_private *dev_priv) |
| 45 | { |
| 46 | WARN(HAS_RUNTIME_PM(dev_priv->dev) && dev_priv->pm.suspended, |
| 47 | "Device suspended\n"); |
| 48 | } |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 49 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 50 | static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv) |
| 51 | { |
| 52 | u32 gt_thread_status_mask; |
| 53 | |
| 54 | if (IS_HASWELL(dev_priv->dev)) |
| 55 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW; |
| 56 | else |
| 57 | gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK; |
| 58 | |
| 59 | /* w/a for a sporadic read returning 0 by waiting for the GT |
| 60 | * thread to wake up. |
| 61 | */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 62 | if (wait_for_atomic_us((__raw_i915_read32(dev_priv, GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500)) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 63 | DRM_ERROR("GT thread status wait timed out\n"); |
| 64 | } |
| 65 | |
| 66 | static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv) |
| 67 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 68 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
| 69 | /* something from same cacheline, but !FORCEWAKE */ |
| 70 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 71 | } |
| 72 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 73 | static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, |
| 74 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 75 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 76 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 77 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 78 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 79 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 80 | __raw_i915_write32(dev_priv, FORCEWAKE, 1); |
| 81 | /* something from same cacheline, but !FORCEWAKE */ |
| 82 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 83 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 84 | if (wait_for_atomic((__raw_i915_read32(dev_priv, FORCEWAKE_ACK) & 1), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 85 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 86 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 87 | |
| 88 | /* WaRsForcewakeWaitTC0:snb */ |
| 89 | __gen6_gt_wait_for_thread_c0(dev_priv); |
| 90 | } |
| 91 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 92 | static void __gen7_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 93 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 94 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 95 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 96 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 97 | } |
| 98 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 99 | static void __gen7_gt_force_wake_mt_get(struct drm_i915_private *dev_priv, |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 100 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 101 | { |
| 102 | u32 forcewake_ack; |
| 103 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 104 | if (IS_HASWELL(dev_priv->dev) || IS_GEN8(dev_priv->dev)) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 105 | forcewake_ack = FORCEWAKE_ACK_HSW; |
| 106 | else |
| 107 | forcewake_ack = FORCEWAKE_MT_ACK; |
| 108 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 109 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL) == 0, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 110 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 111 | DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n"); |
| 112 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 113 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 114 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 115 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 116 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 117 | |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 118 | if (wait_for_atomic((__raw_i915_read32(dev_priv, forcewake_ack) & FORCEWAKE_KERNEL), |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 119 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 120 | DRM_ERROR("Timed out waiting for forcewake to ack request.\n"); |
| 121 | |
| 122 | /* WaRsForcewakeWaitTC0:ivb,hsw */ |
Ben Widawsky | 0f161f7 | 2013-11-02 21:07:50 -0700 | [diff] [blame] | 123 | if (INTEL_INFO(dev_priv->dev)->gen < 8) |
| 124 | __gen6_gt_wait_for_thread_c0(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 125 | } |
| 126 | |
| 127 | static void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv) |
| 128 | { |
| 129 | u32 gtfifodbg; |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 130 | |
| 131 | gtfifodbg = __raw_i915_read32(dev_priv, GTFIFODBG); |
Ville Syrjälä | 90f256b | 2013-11-14 01:59:59 +0200 | [diff] [blame] | 132 | if (WARN(gtfifodbg, "GT wake FIFO error 0x%x\n", gtfifodbg)) |
| 133 | __raw_i915_write32(dev_priv, GTFIFODBG, gtfifodbg); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 134 | } |
| 135 | |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 136 | static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, |
| 137 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 138 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 139 | __raw_i915_write32(dev_priv, FORCEWAKE, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 140 | /* something from same cacheline, but !FORCEWAKE */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 141 | __raw_posting_read(dev_priv, ECOBUS); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 142 | gen6_gt_check_fifodbg(dev_priv); |
| 143 | } |
| 144 | |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 145 | static void __gen7_gt_force_wake_mt_put(struct drm_i915_private *dev_priv, |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 146 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 147 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 148 | __raw_i915_write32(dev_priv, FORCEWAKE_MT, |
| 149 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 150 | /* something from same cacheline, but !FORCEWAKE_MT */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 151 | __raw_posting_read(dev_priv, ECOBUS); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 152 | |
| 153 | if (IS_GEN7(dev_priv->dev)) |
| 154 | gen6_gt_check_fifodbg(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | static int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv) |
| 158 | { |
| 159 | int ret = 0; |
| 160 | |
Deepak S | 5135d64 | 2013-11-29 15:56:30 +0530 | [diff] [blame] | 161 | /* On VLV, FIFO will be shared by both SW and HW. |
| 162 | * So, we need to read the FREE_ENTRIES everytime */ |
| 163 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 164 | dev_priv->uncore.fifo_count = |
| 165 | __raw_i915_read32(dev_priv, GTFIFOCTL) & |
| 166 | GT_FIFO_FREE_ENTRIES_MASK; |
| 167 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 168 | if (dev_priv->uncore.fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) { |
| 169 | int loop = 500; |
Ville Syrjälä | 46520e2 | 2013-11-14 02:00:00 +0200 | [diff] [blame] | 170 | u32 fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 171 | while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) { |
| 172 | udelay(10); |
Ville Syrjälä | 46520e2 | 2013-11-14 02:00:00 +0200 | [diff] [blame] | 173 | fifo = __raw_i915_read32(dev_priv, GTFIFOCTL) & GT_FIFO_FREE_ENTRIES_MASK; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 174 | } |
| 175 | if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES)) |
| 176 | ++ret; |
| 177 | dev_priv->uncore.fifo_count = fifo; |
| 178 | } |
| 179 | dev_priv->uncore.fifo_count--; |
| 180 | |
| 181 | return ret; |
| 182 | } |
| 183 | |
| 184 | static void vlv_force_wake_reset(struct drm_i915_private *dev_priv) |
| 185 | { |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 186 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 187 | _MASKED_BIT_DISABLE(0xffff)); |
Jani Nikula | 05adaf1 | 2014-05-09 14:52:34 +0300 | [diff] [blame] | 188 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 189 | _MASKED_BIT_DISABLE(0xffff)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 190 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 191 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 192 | } |
| 193 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 194 | static void __vlv_force_wake_get(struct drm_i915_private *dev_priv, |
| 195 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 196 | { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 197 | /* Check for Render Engine */ |
| 198 | if (FORCEWAKE_RENDER & fw_engine) { |
| 199 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 200 | FORCEWAKE_ACK_VLV) & |
| 201 | FORCEWAKE_KERNEL) == 0, |
| 202 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 203 | DRM_ERROR("Timed out: Render forcewake old ack to clear.\n"); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 204 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 205 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 206 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 207 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 208 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 209 | FORCEWAKE_ACK_VLV) & |
| 210 | FORCEWAKE_KERNEL), |
| 211 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 212 | DRM_ERROR("Timed out: waiting for Render to ack.\n"); |
| 213 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 214 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 215 | /* Check for Media Engine */ |
| 216 | if (FORCEWAKE_MEDIA & fw_engine) { |
| 217 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 218 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 219 | FORCEWAKE_KERNEL) == 0, |
| 220 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 221 | DRM_ERROR("Timed out: Media forcewake old ack to clear.\n"); |
| 222 | |
| 223 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 224 | _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL)); |
| 225 | |
| 226 | if (wait_for_atomic((__raw_i915_read32(dev_priv, |
| 227 | FORCEWAKE_ACK_MEDIA_VLV) & |
| 228 | FORCEWAKE_KERNEL), |
| 229 | FORCEWAKE_ACK_TIMEOUT_MS)) |
| 230 | DRM_ERROR("Timed out: waiting for media to ack.\n"); |
| 231 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 232 | |
| 233 | /* WaRsForcewakeWaitTC0:vlv */ |
Ville Syrjälä | 3f4e349 | 2014-05-23 21:00:18 +0530 | [diff] [blame] | 234 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
| 235 | __gen6_gt_wait_for_thread_c0(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 236 | } |
| 237 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 238 | static void __vlv_force_wake_put(struct drm_i915_private *dev_priv, |
| 239 | int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 240 | { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 241 | |
| 242 | /* Check for Render Engine */ |
| 243 | if (FORCEWAKE_RENDER & fw_engine) |
| 244 | __raw_i915_write32(dev_priv, FORCEWAKE_VLV, |
| 245 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 246 | |
| 247 | |
| 248 | /* Check for Media Engine */ |
| 249 | if (FORCEWAKE_MEDIA & fw_engine) |
| 250 | __raw_i915_write32(dev_priv, FORCEWAKE_MEDIA_VLV, |
| 251 | _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL)); |
| 252 | |
Ville Syrjälä | ab53c26 | 2014-05-23 21:00:19 +0530 | [diff] [blame] | 253 | /* something from same cacheline, but !FORCEWAKE_VLV */ |
| 254 | __raw_posting_read(dev_priv, FORCEWAKE_ACK_VLV); |
| 255 | if (!IS_CHERRYVIEW(dev_priv->dev)) |
| 256 | gen6_gt_check_fifodbg(dev_priv); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 257 | } |
| 258 | |
Damien Lespiau | b88b23d | 2014-03-28 16:54:25 +0000 | [diff] [blame] | 259 | static void vlv_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 260 | { |
| 261 | unsigned long irqflags; |
| 262 | |
| 263 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 264 | |
| 265 | if (fw_engine & FORCEWAKE_RENDER && |
| 266 | dev_priv->uncore.fw_rendercount++ != 0) |
| 267 | fw_engine &= ~FORCEWAKE_RENDER; |
| 268 | if (fw_engine & FORCEWAKE_MEDIA && |
| 269 | dev_priv->uncore.fw_mediacount++ != 0) |
| 270 | fw_engine &= ~FORCEWAKE_MEDIA; |
| 271 | |
| 272 | if (fw_engine) |
| 273 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw_engine); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 274 | |
| 275 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 276 | } |
| 277 | |
Damien Lespiau | b88b23d | 2014-03-28 16:54:25 +0000 | [diff] [blame] | 278 | static void vlv_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 279 | { |
| 280 | unsigned long irqflags; |
| 281 | |
| 282 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 283 | |
Daniel Vetter | 3123fca | 2014-03-15 20:20:29 +0100 | [diff] [blame] | 284 | if (fw_engine & FORCEWAKE_RENDER) { |
| 285 | WARN_ON(!dev_priv->uncore.fw_rendercount); |
| 286 | if (--dev_priv->uncore.fw_rendercount != 0) |
| 287 | fw_engine &= ~FORCEWAKE_RENDER; |
| 288 | } |
| 289 | |
| 290 | if (fw_engine & FORCEWAKE_MEDIA) { |
| 291 | WARN_ON(!dev_priv->uncore.fw_mediacount); |
| 292 | if (--dev_priv->uncore.fw_mediacount != 0) |
| 293 | fw_engine &= ~FORCEWAKE_MEDIA; |
| 294 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 295 | |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 296 | if (fw_engine) |
| 297 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fw_engine); |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 298 | |
| 299 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 300 | } |
| 301 | |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 302 | static void gen6_force_wake_timer(unsigned long arg) |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 303 | { |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 304 | struct drm_i915_private *dev_priv = (void *)arg; |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 305 | unsigned long irqflags; |
| 306 | |
Paulo Zanoni | b2ec142 | 2014-02-21 13:52:25 -0300 | [diff] [blame] | 307 | assert_device_not_suspended(dev_priv); |
| 308 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 309 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | 3123fca | 2014-03-15 20:20:29 +0100 | [diff] [blame] | 310 | WARN_ON(!dev_priv->uncore.forcewake_count); |
| 311 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 312 | if (--dev_priv->uncore.forcewake_count == 0) |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 313 | dev_priv->uncore.funcs.force_wake_put(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 314 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 315 | |
| 316 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 317 | } |
| 318 | |
Jesse Barnes | 156c7ca | 2014-06-12 08:35:45 -0700 | [diff] [blame] | 319 | void intel_uncore_forcewake_reset(struct drm_device *dev, bool restore) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 320 | { |
| 321 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 322 | unsigned long irqflags; |
| 323 | |
Imre Deak | 9e31c2a5 | 2014-06-06 14:04:37 +0300 | [diff] [blame] | 324 | if (del_timer_sync(&dev_priv->uncore.force_wake_timer)) |
| 325 | gen6_force_wake_timer((unsigned long)dev_priv); |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 326 | |
| 327 | /* Hold uncore.lock across reset to prevent any register access |
| 328 | * with forcewake not set correctly |
| 329 | */ |
| 330 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 331 | |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 332 | if (IS_VALLEYVIEW(dev)) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 333 | vlv_force_wake_reset(dev_priv); |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 334 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 335 | __gen6_gt_force_wake_reset(dev_priv); |
Mika Kuoppala | 0a089e3 | 2014-02-21 17:32:00 +0200 | [diff] [blame] | 336 | |
| 337 | if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev) || IS_GEN8(dev)) |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 338 | __gen7_gt_force_wake_mt_reset(dev_priv); |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 339 | |
| 340 | if (restore) { /* If reset with a user forcewake, try to restore */ |
| 341 | unsigned fw = 0; |
| 342 | |
| 343 | if (IS_VALLEYVIEW(dev)) { |
| 344 | if (dev_priv->uncore.fw_rendercount) |
| 345 | fw |= FORCEWAKE_RENDER; |
| 346 | |
| 347 | if (dev_priv->uncore.fw_mediacount) |
| 348 | fw |= FORCEWAKE_MEDIA; |
| 349 | } else { |
| 350 | if (dev_priv->uncore.forcewake_count) |
| 351 | fw = FORCEWAKE_ALL; |
| 352 | } |
| 353 | |
| 354 | if (fw) |
| 355 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fw); |
| 356 | |
| 357 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 358 | dev_priv->uncore.fifo_count = |
| 359 | __raw_i915_read32(dev_priv, GTFIFOCTL) & |
| 360 | GT_FIFO_FREE_ENTRIES_MASK; |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 361 | } |
| 362 | |
| 363 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | ef46e0d | 2013-11-16 16:00:09 +0100 | [diff] [blame] | 364 | } |
| 365 | |
Imre Deak | 1001860 | 2014-06-06 12:59:39 +0300 | [diff] [blame] | 366 | void intel_uncore_early_sanitize(struct drm_device *dev, bool restore_forcewake) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 367 | { |
| 368 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 369 | |
| 370 | if (HAS_FPGA_DBG_UNCLAIMED(dev)) |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 371 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Ben Widawsky | 18ce399 | 2013-10-04 21:22:50 -0700 | [diff] [blame] | 372 | |
Ben Widawsky | 1d2866b | 2014-04-18 18:04:28 -0300 | [diff] [blame] | 373 | if ((IS_HASWELL(dev) || IS_BROADWELL(dev)) && |
Ben Widawsky | 18ce399 | 2013-10-04 21:22:50 -0700 | [diff] [blame] | 374 | (__raw_i915_read32(dev_priv, HSW_EDRAM_PRESENT) == 1)) { |
| 375 | /* The docs do not explain exactly how the calculation can be |
| 376 | * made. It is somewhat guessable, but for now, it's always |
| 377 | * 128MB. |
| 378 | * NB: We can't write IDICR yet because we do not have gt funcs |
| 379 | * set up */ |
| 380 | dev_priv->ellc_size = 128; |
| 381 | DRM_INFO("Found %zuMB of eLLC\n", dev_priv->ellc_size); |
| 382 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 383 | |
Ville Syrjälä | 9705887 | 2013-12-03 11:30:09 +0200 | [diff] [blame] | 384 | /* clear out old GT FIFO errors */ |
| 385 | if (IS_GEN6(dev) || IS_GEN7(dev)) |
| 386 | __raw_i915_write32(dev_priv, GTFIFODBG, |
| 387 | __raw_i915_read32(dev_priv, GTFIFODBG)); |
| 388 | |
Imre Deak | 1001860 | 2014-06-06 12:59:39 +0300 | [diff] [blame] | 389 | intel_uncore_forcewake_reset(dev, restore_forcewake); |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 390 | } |
| 391 | |
| 392 | void intel_uncore_sanitize(struct drm_device *dev) |
| 393 | { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 394 | /* BIOS often leaves RC6 enabled, but disable it for hw init */ |
| 395 | intel_disable_gt_powersave(dev); |
| 396 | } |
| 397 | |
| 398 | /* |
| 399 | * Generally this is called implicitly by the register read function. However, |
| 400 | * if some sequence requires the GT to not power down then this function should |
| 401 | * be called at the beginning of the sequence followed by a call to |
| 402 | * gen6_gt_force_wake_put() at the end of the sequence. |
| 403 | */ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 404 | void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 405 | { |
| 406 | unsigned long irqflags; |
| 407 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 408 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 409 | return; |
| 410 | |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 411 | intel_runtime_pm_get(dev_priv); |
| 412 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 413 | /* Redirect to VLV specific routine */ |
| 414 | if (IS_VALLEYVIEW(dev_priv->dev)) |
| 415 | return vlv_force_wake_get(dev_priv, fw_engine); |
| 416 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 417 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
| 418 | if (dev_priv->uncore.forcewake_count++ == 0) |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 419 | dev_priv->uncore.funcs.force_wake_get(dev_priv, FORCEWAKE_ALL); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 420 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
| 421 | } |
| 422 | |
| 423 | /* |
| 424 | * see gen6_gt_force_wake_get() |
| 425 | */ |
Deepak S | c8d9a59 | 2013-11-23 14:55:42 +0530 | [diff] [blame] | 426 | void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 427 | { |
| 428 | unsigned long irqflags; |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 429 | bool delayed = false; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 430 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 431 | if (!dev_priv->uncore.funcs.force_wake_put) |
| 432 | return; |
| 433 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 434 | /* Redirect to VLV specific routine */ |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 435 | if (IS_VALLEYVIEW(dev_priv->dev)) { |
| 436 | vlv_force_wake_put(dev_priv, fw_engine); |
| 437 | goto out; |
| 438 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 439 | |
| 440 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 441 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags); |
Daniel Vetter | 3123fca | 2014-03-15 20:20:29 +0100 | [diff] [blame] | 442 | WARN_ON(!dev_priv->uncore.forcewake_count); |
| 443 | |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 444 | if (--dev_priv->uncore.forcewake_count == 0) { |
| 445 | dev_priv->uncore.forcewake_count++; |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 446 | delayed = true; |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 447 | mod_timer_pinned(&dev_priv->uncore.force_wake_timer, |
| 448 | jiffies + 1); |
Chris Wilson | aec347a | 2013-08-26 13:46:09 +0100 | [diff] [blame] | 449 | } |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 450 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); |
Paulo Zanoni | c8c8fb3 | 2013-11-27 18:21:54 -0200 | [diff] [blame] | 451 | |
Paulo Zanoni | 6d88064 | 2014-02-21 17:58:29 -0300 | [diff] [blame] | 452 | out: |
| 453 | if (!delayed) |
| 454 | intel_runtime_pm_put(dev_priv); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 455 | } |
| 456 | |
Paulo Zanoni | e998c40 | 2014-02-21 13:52:26 -0300 | [diff] [blame] | 457 | void assert_force_wake_inactive(struct drm_i915_private *dev_priv) |
| 458 | { |
| 459 | if (!dev_priv->uncore.funcs.force_wake_get) |
| 460 | return; |
| 461 | |
| 462 | WARN_ON(dev_priv->uncore.forcewake_count > 0); |
| 463 | } |
| 464 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 465 | /* We give fast paths for the really cool registers */ |
| 466 | #define NEEDS_FORCE_WAKE(dev_priv, reg) \ |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 467 | ((reg) < 0x40000 && (reg) != FORCEWAKE) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 468 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 469 | #define REG_RANGE(reg, start, end) ((reg) >= (start) && (reg) < (end)) |
Damien Lespiau | 38fb6a4 | 2014-03-28 16:54:26 +0000 | [diff] [blame] | 470 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 471 | #define FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg) \ |
| 472 | (REG_RANGE((reg), 0x2000, 0x4000) || \ |
| 473 | REG_RANGE((reg), 0x5000, 0x8000) || \ |
| 474 | REG_RANGE((reg), 0xB000, 0x12000) || \ |
| 475 | REG_RANGE((reg), 0x2E000, 0x30000)) |
| 476 | |
| 477 | #define FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg) \ |
| 478 | (REG_RANGE((reg), 0x12000, 0x14000) || \ |
| 479 | REG_RANGE((reg), 0x22000, 0x24000) || \ |
| 480 | REG_RANGE((reg), 0x30000, 0x40000)) |
| 481 | |
| 482 | #define FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg) \ |
| 483 | (REG_RANGE((reg), 0x2000, 0x4000) || \ |
| 484 | REG_RANGE((reg), 0x5000, 0x8000) || \ |
| 485 | REG_RANGE((reg), 0x8300, 0x8500) || \ |
| 486 | REG_RANGE((reg), 0xB000, 0xC000) || \ |
| 487 | REG_RANGE((reg), 0xE000, 0xE800)) |
| 488 | |
| 489 | #define FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg) \ |
| 490 | (REG_RANGE((reg), 0x8800, 0x8900) || \ |
| 491 | REG_RANGE((reg), 0xD000, 0xD800) || \ |
| 492 | REG_RANGE((reg), 0x12000, 0x14000) || \ |
| 493 | REG_RANGE((reg), 0x1A000, 0x1C000) || \ |
| 494 | REG_RANGE((reg), 0x1E800, 0x1EA00) || \ |
| 495 | REG_RANGE((reg), 0x30000, 0x40000)) |
| 496 | |
| 497 | #define FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg) \ |
| 498 | (REG_RANGE((reg), 0x4000, 0x5000) || \ |
| 499 | REG_RANGE((reg), 0x8000, 0x8300) || \ |
| 500 | REG_RANGE((reg), 0x8500, 0x8600) || \ |
| 501 | REG_RANGE((reg), 0x9000, 0xB000) || \ |
| 502 | REG_RANGE((reg), 0xC000, 0xC800) || \ |
| 503 | REG_RANGE((reg), 0xF000, 0x10000) || \ |
| 504 | REG_RANGE((reg), 0x14000, 0x14400) || \ |
| 505 | REG_RANGE((reg), 0x22000, 0x24000)) |
Damien Lespiau | 38fb6a4 | 2014-03-28 16:54:26 +0000 | [diff] [blame] | 506 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 507 | static void |
| 508 | ilk_dummy_write(struct drm_i915_private *dev_priv) |
| 509 | { |
| 510 | /* WaIssueDummyWriteToWakeupFromRC6:ilk Issue a dummy write to wake up |
| 511 | * the chip from rc6 before touching it for real. MI_MODE is masked, |
| 512 | * hence harmless to write 0 into. */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 513 | __raw_i915_write32(dev_priv, MI_MODE, 0); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 514 | } |
| 515 | |
| 516 | static void |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 517 | hsw_unclaimed_reg_debug(struct drm_i915_private *dev_priv, u32 reg, bool read, |
| 518 | bool before) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 519 | { |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 520 | const char *op = read ? "reading" : "writing to"; |
| 521 | const char *when = before ? "before" : "after"; |
| 522 | |
| 523 | if (!i915.mmio_debug) |
| 524 | return; |
| 525 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 526 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 527 | WARN(1, "Unclaimed register detected %s %s register 0x%x\n", |
| 528 | when, op, reg); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 529 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 530 | } |
| 531 | } |
| 532 | |
| 533 | static void |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 534 | hsw_unclaimed_reg_detect(struct drm_i915_private *dev_priv) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 535 | { |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 536 | if (i915.mmio_debug) |
| 537 | return; |
| 538 | |
Ben Widawsky | ab484f8 | 2013-10-05 17:57:11 -0700 | [diff] [blame] | 539 | if (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM) { |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 540 | DRM_ERROR("Unclaimed register detected. Please use the i915.mmio_debug=1 to debug this problem."); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 541 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 542 | } |
| 543 | } |
| 544 | |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 545 | #define REG_READ_HEADER(x) \ |
| 546 | unsigned long irqflags; \ |
| 547 | u##x val = 0; \ |
Paulo Zanoni | 6f0ea9e | 2014-02-21 13:52:28 -0300 | [diff] [blame] | 548 | assert_device_not_suspended(dev_priv); \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 549 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
| 550 | |
| 551 | #define REG_READ_FOOTER \ |
| 552 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags); \ |
| 553 | trace_i915_reg_rw(false, reg, val, sizeof(val), trace); \ |
| 554 | return val |
| 555 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 556 | #define __gen4_read(x) \ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 557 | static u##x \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 558 | gen4_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 559 | REG_READ_HEADER(x); \ |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 560 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 561 | REG_READ_FOOTER; \ |
| 562 | } |
| 563 | |
| 564 | #define __gen5_read(x) \ |
| 565 | static u##x \ |
| 566 | gen5_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 567 | REG_READ_HEADER(x); \ |
| 568 | ilk_dummy_write(dev_priv); \ |
| 569 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 570 | REG_READ_FOOTER; \ |
| 571 | } |
| 572 | |
| 573 | #define __gen6_read(x) \ |
| 574 | static u##x \ |
| 575 | gen6_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 576 | REG_READ_HEADER(x); \ |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 577 | hsw_unclaimed_reg_debug(dev_priv, reg, true, true); \ |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 578 | if (dev_priv->uncore.forcewake_count == 0 && \ |
| 579 | NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 580 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 581 | FORCEWAKE_ALL); \ |
Paulo Zanoni | aa0b3b5 | 2014-04-01 14:55:07 -0300 | [diff] [blame] | 582 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 583 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
| 584 | FORCEWAKE_ALL); \ |
| 585 | } else { \ |
| 586 | val = __raw_i915_read##x(dev_priv, reg); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 587 | } \ |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 588 | hsw_unclaimed_reg_debug(dev_priv, reg, true, false); \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 589 | REG_READ_FOOTER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 590 | } |
| 591 | |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 592 | #define __vlv_read(x) \ |
| 593 | static u##x \ |
| 594 | vlv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 595 | unsigned fwengine = 0; \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 596 | REG_READ_HEADER(x); \ |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 597 | if (FORCEWAKE_VLV_RENDER_RANGE_OFFSET(reg)) { \ |
| 598 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 599 | fwengine = FORCEWAKE_RENDER; \ |
| 600 | } else if (FORCEWAKE_VLV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 601 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 602 | fwengine = FORCEWAKE_MEDIA; \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 603 | } \ |
Ville Syrjälä | 6fe7286 | 2014-02-27 22:07:21 +0200 | [diff] [blame] | 604 | if (fwengine) \ |
| 605 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 606 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 607 | if (fwengine) \ |
| 608 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 609 | REG_READ_FOOTER; \ |
| 610 | } |
| 611 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 612 | #define __chv_read(x) \ |
| 613 | static u##x \ |
| 614 | chv_read##x(struct drm_i915_private *dev_priv, off_t reg, bool trace) { \ |
| 615 | unsigned fwengine = 0; \ |
| 616 | REG_READ_HEADER(x); \ |
| 617 | if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ |
| 618 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 619 | fwengine = FORCEWAKE_RENDER; \ |
| 620 | } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 621 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 622 | fwengine = FORCEWAKE_MEDIA; \ |
| 623 | } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ |
| 624 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 625 | fwengine |= FORCEWAKE_RENDER; \ |
| 626 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 627 | fwengine |= FORCEWAKE_MEDIA; \ |
| 628 | } \ |
| 629 | if (fwengine) \ |
| 630 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 631 | val = __raw_i915_read##x(dev_priv, reg); \ |
| 632 | if (fwengine) \ |
| 633 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 634 | REG_READ_FOOTER; \ |
| 635 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 636 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 637 | __chv_read(8) |
| 638 | __chv_read(16) |
| 639 | __chv_read(32) |
| 640 | __chv_read(64) |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 641 | __vlv_read(8) |
| 642 | __vlv_read(16) |
| 643 | __vlv_read(32) |
| 644 | __vlv_read(64) |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 645 | __gen6_read(8) |
| 646 | __gen6_read(16) |
| 647 | __gen6_read(32) |
| 648 | __gen6_read(64) |
| 649 | __gen5_read(8) |
| 650 | __gen5_read(16) |
| 651 | __gen5_read(32) |
| 652 | __gen5_read(64) |
| 653 | __gen4_read(8) |
| 654 | __gen4_read(16) |
| 655 | __gen4_read(32) |
| 656 | __gen4_read(64) |
| 657 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 658 | #undef __chv_read |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 659 | #undef __vlv_read |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 660 | #undef __gen6_read |
| 661 | #undef __gen5_read |
| 662 | #undef __gen4_read |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 663 | #undef REG_READ_FOOTER |
| 664 | #undef REG_READ_HEADER |
| 665 | |
| 666 | #define REG_WRITE_HEADER \ |
| 667 | unsigned long irqflags; \ |
| 668 | trace_i915_reg_rw(true, reg, val, sizeof(val), trace); \ |
Paulo Zanoni | 6f0ea9e | 2014-02-21 13:52:28 -0300 | [diff] [blame] | 669 | assert_device_not_suspended(dev_priv); \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 670 | spin_lock_irqsave(&dev_priv->uncore.lock, irqflags) |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 671 | |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 672 | #define REG_WRITE_FOOTER \ |
| 673 | spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags) |
| 674 | |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 675 | #define __gen4_write(x) \ |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 676 | static void \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 677 | gen4_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 678 | REG_WRITE_HEADER; \ |
| 679 | __raw_i915_write##x(dev_priv, reg, val); \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 680 | REG_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 681 | } |
| 682 | |
| 683 | #define __gen5_write(x) \ |
| 684 | static void \ |
| 685 | gen5_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 686 | REG_WRITE_HEADER; \ |
| 687 | ilk_dummy_write(dev_priv); \ |
| 688 | __raw_i915_write##x(dev_priv, reg, val); \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 689 | REG_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 690 | } |
| 691 | |
| 692 | #define __gen6_write(x) \ |
| 693 | static void \ |
| 694 | gen6_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 695 | u32 __fifo_ret = 0; \ |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 696 | REG_WRITE_HEADER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 697 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 698 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 699 | } \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 700 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 701 | if (unlikely(__fifo_ret)) { \ |
| 702 | gen6_gt_check_fifodbg(dev_priv); \ |
| 703 | } \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 704 | REG_WRITE_FOOTER; \ |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 705 | } |
| 706 | |
| 707 | #define __hsw_write(x) \ |
| 708 | static void \ |
| 709 | hsw_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 710 | u32 __fifo_ret = 0; \ |
| 711 | REG_WRITE_HEADER; \ |
| 712 | if (NEEDS_FORCE_WAKE((dev_priv), (reg))) { \ |
| 713 | __fifo_ret = __gen6_gt_wait_for_fifo(dev_priv); \ |
| 714 | } \ |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 715 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 716 | __raw_i915_write##x(dev_priv, reg, val); \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 717 | if (unlikely(__fifo_ret)) { \ |
| 718 | gen6_gt_check_fifodbg(dev_priv); \ |
| 719 | } \ |
Paulo Zanoni | 5978118 | 2014-07-16 17:49:29 -0300 | [diff] [blame] | 720 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
| 721 | hsw_unclaimed_reg_detect(dev_priv); \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 722 | REG_WRITE_FOOTER; \ |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 723 | } |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 724 | |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 725 | static const u32 gen8_shadowed_regs[] = { |
| 726 | FORCEWAKE_MT, |
| 727 | GEN6_RPNSWREQ, |
| 728 | GEN6_RC_VIDEO_FREQ, |
| 729 | RING_TAIL(RENDER_RING_BASE), |
| 730 | RING_TAIL(GEN6_BSD_RING_BASE), |
| 731 | RING_TAIL(VEBOX_RING_BASE), |
| 732 | RING_TAIL(BLT_RING_BASE), |
| 733 | /* TODO: Other registers are not yet used */ |
| 734 | }; |
| 735 | |
| 736 | static bool is_gen8_shadowed(struct drm_i915_private *dev_priv, u32 reg) |
| 737 | { |
| 738 | int i; |
| 739 | for (i = 0; i < ARRAY_SIZE(gen8_shadowed_regs); i++) |
| 740 | if (reg == gen8_shadowed_regs[i]) |
| 741 | return true; |
| 742 | |
| 743 | return false; |
| 744 | } |
| 745 | |
| 746 | #define __gen8_write(x) \ |
| 747 | static void \ |
| 748 | gen8_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 749 | REG_WRITE_HEADER; \ |
Paulo Zanoni | 66bc2ca | 2014-07-16 17:49:30 -0300 | [diff] [blame] | 750 | hsw_unclaimed_reg_debug(dev_priv, reg, false, true); \ |
Mika Kuoppala | e9dbd2b | 2014-02-18 19:10:24 +0200 | [diff] [blame] | 751 | if (reg < 0x40000 && !is_gen8_shadowed(dev_priv, reg)) { \ |
| 752 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 753 | dev_priv->uncore.funcs.force_wake_get(dev_priv, \ |
| 754 | FORCEWAKE_ALL); \ |
| 755 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 756 | if (dev_priv->uncore.forcewake_count == 0) \ |
| 757 | dev_priv->uncore.funcs.force_wake_put(dev_priv, \ |
| 758 | FORCEWAKE_ALL); \ |
| 759 | } else { \ |
| 760 | __raw_i915_write##x(dev_priv, reg, val); \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 761 | } \ |
Paulo Zanoni | 66bc2ca | 2014-07-16 17:49:30 -0300 | [diff] [blame] | 762 | hsw_unclaimed_reg_debug(dev_priv, reg, false, false); \ |
| 763 | hsw_unclaimed_reg_detect(dev_priv); \ |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 764 | REG_WRITE_FOOTER; \ |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 765 | } |
| 766 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 767 | #define __chv_write(x) \ |
| 768 | static void \ |
| 769 | chv_write##x(struct drm_i915_private *dev_priv, off_t reg, u##x val, bool trace) { \ |
| 770 | unsigned fwengine = 0; \ |
| 771 | bool shadowed = is_gen8_shadowed(dev_priv, reg); \ |
| 772 | REG_WRITE_HEADER; \ |
| 773 | if (!shadowed) { \ |
| 774 | if (FORCEWAKE_CHV_RENDER_RANGE_OFFSET(reg)) { \ |
| 775 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 776 | fwengine = FORCEWAKE_RENDER; \ |
| 777 | } else if (FORCEWAKE_CHV_MEDIA_RANGE_OFFSET(reg)) { \ |
| 778 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 779 | fwengine = FORCEWAKE_MEDIA; \ |
| 780 | } else if (FORCEWAKE_CHV_COMMON_RANGE_OFFSET(reg)) { \ |
| 781 | if (dev_priv->uncore.fw_rendercount == 0) \ |
| 782 | fwengine |= FORCEWAKE_RENDER; \ |
| 783 | if (dev_priv->uncore.fw_mediacount == 0) \ |
| 784 | fwengine |= FORCEWAKE_MEDIA; \ |
| 785 | } \ |
| 786 | } \ |
| 787 | if (fwengine) \ |
| 788 | dev_priv->uncore.funcs.force_wake_get(dev_priv, fwengine); \ |
| 789 | __raw_i915_write##x(dev_priv, reg, val); \ |
| 790 | if (fwengine) \ |
| 791 | dev_priv->uncore.funcs.force_wake_put(dev_priv, fwengine); \ |
| 792 | REG_WRITE_FOOTER; \ |
| 793 | } |
| 794 | |
| 795 | __chv_write(8) |
| 796 | __chv_write(16) |
| 797 | __chv_write(32) |
| 798 | __chv_write(64) |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 799 | __gen8_write(8) |
| 800 | __gen8_write(16) |
| 801 | __gen8_write(32) |
| 802 | __gen8_write(64) |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 803 | __hsw_write(8) |
| 804 | __hsw_write(16) |
| 805 | __hsw_write(32) |
| 806 | __hsw_write(64) |
| 807 | __gen6_write(8) |
| 808 | __gen6_write(16) |
| 809 | __gen6_write(32) |
| 810 | __gen6_write(64) |
| 811 | __gen5_write(8) |
| 812 | __gen5_write(16) |
| 813 | __gen5_write(32) |
| 814 | __gen5_write(64) |
| 815 | __gen4_write(8) |
| 816 | __gen4_write(16) |
| 817 | __gen4_write(32) |
| 818 | __gen4_write(64) |
| 819 | |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 820 | #undef __chv_write |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 821 | #undef __gen8_write |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 822 | #undef __hsw_write |
| 823 | #undef __gen6_write |
| 824 | #undef __gen5_write |
| 825 | #undef __gen4_write |
Ville Syrjälä | 0d96530 | 2013-12-02 14:23:02 +0200 | [diff] [blame] | 826 | #undef REG_WRITE_FOOTER |
Ben Widawsky | 5d73879 | 2013-10-04 21:24:53 -0700 | [diff] [blame] | 827 | #undef REG_WRITE_HEADER |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 828 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 829 | void intel_uncore_init(struct drm_device *dev) |
| 830 | { |
| 831 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 832 | |
Chris Wilson | 8232644 | 2014-03-05 12:00:39 +0000 | [diff] [blame] | 833 | setup_timer(&dev_priv->uncore.force_wake_timer, |
| 834 | gen6_force_wake_timer, (unsigned long)dev_priv); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 835 | |
Imre Deak | 1001860 | 2014-06-06 12:59:39 +0300 | [diff] [blame] | 836 | intel_uncore_early_sanitize(dev, false); |
Daniel Vetter | 05efeebd | 2014-03-18 16:26:25 +0100 | [diff] [blame] | 837 | |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 838 | if (IS_VALLEYVIEW(dev)) { |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 839 | dev_priv->uncore.funcs.force_wake_get = __vlv_force_wake_get; |
| 840 | dev_priv->uncore.funcs.force_wake_put = __vlv_force_wake_put; |
Ben Widawsky | 43d1b64 | 2013-11-07 16:24:31 -0800 | [diff] [blame] | 841 | } else if (IS_HASWELL(dev) || IS_GEN8(dev)) { |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 842 | dev_priv->uncore.funcs.force_wake_get = __gen7_gt_force_wake_mt_get; |
| 843 | dev_priv->uncore.funcs.force_wake_put = __gen7_gt_force_wake_mt_put; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 844 | } else if (IS_IVYBRIDGE(dev)) { |
| 845 | u32 ecobus; |
| 846 | |
| 847 | /* IVB configs may use multi-threaded forcewake */ |
| 848 | |
| 849 | /* A small trick here - if the bios hasn't configured |
| 850 | * MT forcewake, and if the device is in RC6, then |
| 851 | * force_wake_mt_get will not wake the device and the |
| 852 | * ECOBUS read will return zero. Which will be |
| 853 | * (correctly) interpreted by the test below as MT |
| 854 | * forcewake being disabled. |
| 855 | */ |
| 856 | mutex_lock(&dev->struct_mutex); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 857 | __gen7_gt_force_wake_mt_get(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 858 | ecobus = __raw_i915_read32(dev_priv, ECOBUS); |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 859 | __gen7_gt_force_wake_mt_put(dev_priv, FORCEWAKE_ALL); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 860 | mutex_unlock(&dev->struct_mutex); |
| 861 | |
| 862 | if (ecobus & FORCEWAKE_MT_ENABLE) { |
| 863 | dev_priv->uncore.funcs.force_wake_get = |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 864 | __gen7_gt_force_wake_mt_get; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 865 | dev_priv->uncore.funcs.force_wake_put = |
Mika Kuoppala | 6a68735 | 2014-02-21 18:47:36 +0200 | [diff] [blame] | 866 | __gen7_gt_force_wake_mt_put; |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 867 | } else { |
| 868 | DRM_INFO("No MT forcewake available on Ivybridge, this can result in issues\n"); |
| 869 | DRM_INFO("when using vblank-synced partial screen updates.\n"); |
| 870 | dev_priv->uncore.funcs.force_wake_get = |
| 871 | __gen6_gt_force_wake_get; |
| 872 | dev_priv->uncore.funcs.force_wake_put = |
| 873 | __gen6_gt_force_wake_put; |
| 874 | } |
| 875 | } else if (IS_GEN6(dev)) { |
| 876 | dev_priv->uncore.funcs.force_wake_get = |
| 877 | __gen6_gt_force_wake_get; |
| 878 | dev_priv->uncore.funcs.force_wake_put = |
| 879 | __gen6_gt_force_wake_put; |
| 880 | } |
| 881 | |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 882 | switch (INTEL_INFO(dev)->gen) { |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 883 | default: |
Deepak S | 1938e59 | 2014-05-23 21:00:16 +0530 | [diff] [blame] | 884 | if (IS_CHERRYVIEW(dev)) { |
| 885 | dev_priv->uncore.funcs.mmio_writeb = chv_write8; |
| 886 | dev_priv->uncore.funcs.mmio_writew = chv_write16; |
| 887 | dev_priv->uncore.funcs.mmio_writel = chv_write32; |
| 888 | dev_priv->uncore.funcs.mmio_writeq = chv_write64; |
| 889 | dev_priv->uncore.funcs.mmio_readb = chv_read8; |
| 890 | dev_priv->uncore.funcs.mmio_readw = chv_read16; |
| 891 | dev_priv->uncore.funcs.mmio_readl = chv_read32; |
| 892 | dev_priv->uncore.funcs.mmio_readq = chv_read64; |
| 893 | |
| 894 | } else { |
| 895 | dev_priv->uncore.funcs.mmio_writeb = gen8_write8; |
| 896 | dev_priv->uncore.funcs.mmio_writew = gen8_write16; |
| 897 | dev_priv->uncore.funcs.mmio_writel = gen8_write32; |
| 898 | dev_priv->uncore.funcs.mmio_writeq = gen8_write64; |
| 899 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
| 900 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; |
| 901 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; |
| 902 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; |
| 903 | } |
Ben Widawsky | ab2aa47 | 2013-11-02 21:07:00 -0700 | [diff] [blame] | 904 | break; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 905 | case 7: |
| 906 | case 6: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 907 | if (IS_HASWELL(dev)) { |
| 908 | dev_priv->uncore.funcs.mmio_writeb = hsw_write8; |
| 909 | dev_priv->uncore.funcs.mmio_writew = hsw_write16; |
| 910 | dev_priv->uncore.funcs.mmio_writel = hsw_write32; |
| 911 | dev_priv->uncore.funcs.mmio_writeq = hsw_write64; |
| 912 | } else { |
| 913 | dev_priv->uncore.funcs.mmio_writeb = gen6_write8; |
| 914 | dev_priv->uncore.funcs.mmio_writew = gen6_write16; |
| 915 | dev_priv->uncore.funcs.mmio_writel = gen6_write32; |
| 916 | dev_priv->uncore.funcs.mmio_writeq = gen6_write64; |
| 917 | } |
Deepak S | 940aece | 2013-11-23 14:55:43 +0530 | [diff] [blame] | 918 | |
| 919 | if (IS_VALLEYVIEW(dev)) { |
| 920 | dev_priv->uncore.funcs.mmio_readb = vlv_read8; |
| 921 | dev_priv->uncore.funcs.mmio_readw = vlv_read16; |
| 922 | dev_priv->uncore.funcs.mmio_readl = vlv_read32; |
| 923 | dev_priv->uncore.funcs.mmio_readq = vlv_read64; |
| 924 | } else { |
| 925 | dev_priv->uncore.funcs.mmio_readb = gen6_read8; |
| 926 | dev_priv->uncore.funcs.mmio_readw = gen6_read16; |
| 927 | dev_priv->uncore.funcs.mmio_readl = gen6_read32; |
| 928 | dev_priv->uncore.funcs.mmio_readq = gen6_read64; |
| 929 | } |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 930 | break; |
| 931 | case 5: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 932 | dev_priv->uncore.funcs.mmio_writeb = gen5_write8; |
| 933 | dev_priv->uncore.funcs.mmio_writew = gen5_write16; |
| 934 | dev_priv->uncore.funcs.mmio_writel = gen5_write32; |
| 935 | dev_priv->uncore.funcs.mmio_writeq = gen5_write64; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 936 | dev_priv->uncore.funcs.mmio_readb = gen5_read8; |
| 937 | dev_priv->uncore.funcs.mmio_readw = gen5_read16; |
| 938 | dev_priv->uncore.funcs.mmio_readl = gen5_read32; |
| 939 | dev_priv->uncore.funcs.mmio_readq = gen5_read64; |
| 940 | break; |
| 941 | case 4: |
| 942 | case 3: |
| 943 | case 2: |
Ben Widawsky | 4032ef4 | 2013-10-04 21:22:54 -0700 | [diff] [blame] | 944 | dev_priv->uncore.funcs.mmio_writeb = gen4_write8; |
| 945 | dev_priv->uncore.funcs.mmio_writew = gen4_write16; |
| 946 | dev_priv->uncore.funcs.mmio_writel = gen4_write32; |
| 947 | dev_priv->uncore.funcs.mmio_writeq = gen4_write64; |
Ben Widawsky | 3967018 | 2013-10-04 21:22:53 -0700 | [diff] [blame] | 948 | dev_priv->uncore.funcs.mmio_readb = gen4_read8; |
| 949 | dev_priv->uncore.funcs.mmio_readw = gen4_read16; |
| 950 | dev_priv->uncore.funcs.mmio_readl = gen4_read32; |
| 951 | dev_priv->uncore.funcs.mmio_readq = gen4_read64; |
| 952 | break; |
| 953 | } |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 954 | } |
| 955 | |
| 956 | void intel_uncore_fini(struct drm_device *dev) |
| 957 | { |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 958 | /* Paranoia: make sure we have disabled everything before we exit. */ |
| 959 | intel_uncore_sanitize(dev); |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 960 | intel_uncore_forcewake_reset(dev, false); |
Ben Widawsky | 0b27448 | 2013-10-04 21:22:51 -0700 | [diff] [blame] | 961 | } |
| 962 | |
Damien Lespiau | af76ae44 | 2014-03-31 11:24:08 +0100 | [diff] [blame] | 963 | #define GEN_RANGE(l, h) GENMASK(h, l) |
| 964 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 965 | static const struct register_whitelist { |
| 966 | uint64_t offset; |
| 967 | uint32_t size; |
Damien Lespiau | af76ae44 | 2014-03-31 11:24:08 +0100 | [diff] [blame] | 968 | /* supported gens, 0x10 for 4, 0x30 for 4 and 5, etc. */ |
| 969 | uint32_t gen_bitmask; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 970 | } whitelist[] = { |
Damien Lespiau | af76ae44 | 2014-03-31 11:24:08 +0100 | [diff] [blame] | 971 | { RING_TIMESTAMP(RENDER_RING_BASE), 8, GEN_RANGE(4, 8) }, |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 972 | }; |
| 973 | |
| 974 | int i915_reg_read_ioctl(struct drm_device *dev, |
| 975 | void *data, struct drm_file *file) |
| 976 | { |
| 977 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 978 | struct drm_i915_reg_read *reg = data; |
| 979 | struct register_whitelist const *entry = whitelist; |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 980 | int i, ret = 0; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 981 | |
| 982 | for (i = 0; i < ARRAY_SIZE(whitelist); i++, entry++) { |
| 983 | if (entry->offset == reg->offset && |
| 984 | (1 << INTEL_INFO(dev)->gen & entry->gen_bitmask)) |
| 985 | break; |
| 986 | } |
| 987 | |
| 988 | if (i == ARRAY_SIZE(whitelist)) |
| 989 | return -EINVAL; |
| 990 | |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 991 | intel_runtime_pm_get(dev_priv); |
| 992 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 993 | switch (entry->size) { |
| 994 | case 8: |
| 995 | reg->val = I915_READ64(reg->offset); |
| 996 | break; |
| 997 | case 4: |
| 998 | reg->val = I915_READ(reg->offset); |
| 999 | break; |
| 1000 | case 2: |
| 1001 | reg->val = I915_READ16(reg->offset); |
| 1002 | break; |
| 1003 | case 1: |
| 1004 | reg->val = I915_READ8(reg->offset); |
| 1005 | break; |
| 1006 | default: |
| 1007 | WARN_ON(1); |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 1008 | ret = -EINVAL; |
| 1009 | goto out; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1010 | } |
| 1011 | |
Paulo Zanoni | cf67c70 | 2014-04-01 14:55:08 -0300 | [diff] [blame] | 1012 | out: |
| 1013 | intel_runtime_pm_put(dev_priv); |
| 1014 | return ret; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1015 | } |
| 1016 | |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1017 | int i915_get_reset_stats_ioctl(struct drm_device *dev, |
| 1018 | void *data, struct drm_file *file) |
| 1019 | { |
| 1020 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1021 | struct drm_i915_reset_stats *args = data; |
| 1022 | struct i915_ctx_hang_stats *hs; |
Oscar Mateo | 273497e | 2014-05-22 14:13:37 +0100 | [diff] [blame] | 1023 | struct intel_context *ctx; |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1024 | int ret; |
| 1025 | |
Mika Kuoppala | 661df04 | 2013-11-12 19:49:35 +0200 | [diff] [blame] | 1026 | if (args->flags || args->pad) |
| 1027 | return -EINVAL; |
| 1028 | |
Oscar Mateo | 821d66d | 2014-07-03 16:28:00 +0100 | [diff] [blame] | 1029 | if (args->ctx_id == DEFAULT_CONTEXT_HANDLE && !capable(CAP_SYS_ADMIN)) |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1030 | return -EPERM; |
| 1031 | |
| 1032 | ret = mutex_lock_interruptible(&dev->struct_mutex); |
| 1033 | if (ret) |
| 1034 | return ret; |
| 1035 | |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 1036 | ctx = i915_gem_context_get(file->driver_priv, args->ctx_id); |
| 1037 | if (IS_ERR(ctx)) { |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1038 | mutex_unlock(&dev->struct_mutex); |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 1039 | return PTR_ERR(ctx); |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1040 | } |
Ben Widawsky | 41bde55 | 2013-12-06 14:11:21 -0800 | [diff] [blame] | 1041 | hs = &ctx->hang_stats; |
Mika Kuoppala | b635991 | 2013-10-30 15:44:16 +0200 | [diff] [blame] | 1042 | |
| 1043 | if (capable(CAP_SYS_ADMIN)) |
| 1044 | args->reset_count = i915_reset_count(&dev_priv->gpu_error); |
| 1045 | else |
| 1046 | args->reset_count = 0; |
| 1047 | |
| 1048 | args->batch_active = hs->batch_active; |
| 1049 | args->batch_pending = hs->batch_pending; |
| 1050 | |
| 1051 | mutex_unlock(&dev->struct_mutex); |
| 1052 | |
| 1053 | return 0; |
| 1054 | } |
| 1055 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1056 | static int i965_reset_complete(struct drm_device *dev) |
| 1057 | { |
| 1058 | u8 gdrst; |
| 1059 | pci_read_config_byte(dev->pdev, I965_GDRST, &gdrst); |
| 1060 | return (gdrst & GRDOM_RESET_ENABLE) == 0; |
| 1061 | } |
| 1062 | |
| 1063 | static int i965_do_reset(struct drm_device *dev) |
| 1064 | { |
| 1065 | int ret; |
| 1066 | |
Daniel Vetter | 85ab399 | 2014-05-22 17:56:33 +0200 | [diff] [blame] | 1067 | /* FIXME: i965g/gm need a display save/restore for gpu reset. */ |
| 1068 | return -ENODEV; |
| 1069 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1070 | /* |
| 1071 | * Set the domains we want to reset (GRDOM/bits 2 and 3) as |
| 1072 | * well as the reset bit (GR/bit 0). Setting the GR bit |
| 1073 | * triggers the reset; when done, the hardware will clear it. |
| 1074 | */ |
| 1075 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1076 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 1077 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1078 | if (ret) |
| 1079 | return ret; |
| 1080 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1081 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1082 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 1083 | |
| 1084 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1085 | if (ret) |
| 1086 | return ret; |
| 1087 | |
| 1088 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
| 1089 | |
| 1090 | return 0; |
| 1091 | } |
| 1092 | |
Ville Syrjälä | fa4f53c | 2014-05-19 19:23:27 +0300 | [diff] [blame] | 1093 | static int g4x_do_reset(struct drm_device *dev) |
| 1094 | { |
| 1095 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1096 | int ret; |
| 1097 | |
| 1098 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1099 | GRDOM_RENDER | GRDOM_RESET_ENABLE); |
| 1100 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1101 | if (ret) |
| 1102 | return ret; |
| 1103 | |
| 1104 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ |
| 1105 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) | VCP_UNIT_CLOCK_GATE_DISABLE); |
| 1106 | POSTING_READ(VDECCLK_GATE_D); |
| 1107 | |
| 1108 | pci_write_config_byte(dev->pdev, I965_GDRST, |
| 1109 | GRDOM_MEDIA | GRDOM_RESET_ENABLE); |
| 1110 | ret = wait_for(i965_reset_complete(dev), 500); |
| 1111 | if (ret) |
| 1112 | return ret; |
| 1113 | |
| 1114 | /* WaVcpClkGateDisableForMediaReset:ctg,elk */ |
| 1115 | I915_WRITE(VDECCLK_GATE_D, I915_READ(VDECCLK_GATE_D) & ~VCP_UNIT_CLOCK_GATE_DISABLE); |
| 1116 | POSTING_READ(VDECCLK_GATE_D); |
| 1117 | |
| 1118 | pci_write_config_byte(dev->pdev, I965_GDRST, 0); |
| 1119 | |
| 1120 | return 0; |
| 1121 | } |
| 1122 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1123 | static int ironlake_do_reset(struct drm_device *dev) |
| 1124 | { |
| 1125 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1126 | int ret; |
| 1127 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1128 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
Ville Syrjälä | 0f08ffd | 2014-05-19 19:23:25 +0300 | [diff] [blame] | 1129 | ILK_GRDOM_RENDER | ILK_GRDOM_RESET_ENABLE); |
Ville Syrjälä | f67deb7 | 2014-05-19 19:23:23 +0300 | [diff] [blame] | 1130 | ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & |
Ville Syrjälä | b3a3f03 | 2014-05-19 19:23:24 +0300 | [diff] [blame] | 1131 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1132 | if (ret) |
| 1133 | return ret; |
| 1134 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1135 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, |
Ville Syrjälä | 0f08ffd | 2014-05-19 19:23:25 +0300 | [diff] [blame] | 1136 | ILK_GRDOM_MEDIA | ILK_GRDOM_RESET_ENABLE); |
Ville Syrjälä | 9aa7250 | 2014-05-19 19:23:26 +0300 | [diff] [blame] | 1137 | ret = wait_for((I915_READ(MCHBAR_MIRROR_BASE + ILK_GDSR) & |
| 1138 | ILK_GRDOM_RESET_ENABLE) == 0, 500); |
| 1139 | if (ret) |
| 1140 | return ret; |
| 1141 | |
| 1142 | I915_WRITE(MCHBAR_MIRROR_BASE + ILK_GDSR, 0); |
| 1143 | |
| 1144 | return 0; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1145 | } |
| 1146 | |
| 1147 | static int gen6_do_reset(struct drm_device *dev) |
| 1148 | { |
| 1149 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1150 | int ret; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1151 | |
| 1152 | /* Reset the chip */ |
| 1153 | |
| 1154 | /* GEN6_GDRST is not in the gt power well, no need to check |
| 1155 | * for fifo space for the write or forcewake the chip for |
| 1156 | * the read |
| 1157 | */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1158 | __raw_i915_write32(dev_priv, GEN6_GDRST, GEN6_GRDOM_FULL); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1159 | |
| 1160 | /* Spin waiting for the device to ack the reset request */ |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1161 | ret = wait_for((__raw_i915_read32(dev_priv, GEN6_GDRST) & GEN6_GRDOM_FULL) == 0, 500); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1162 | |
Chris Wilson | 0294ae7 | 2014-03-13 12:00:29 +0000 | [diff] [blame] | 1163 | intel_uncore_forcewake_reset(dev, true); |
Mika Kuoppala | 521198a | 2013-08-23 16:52:30 +0300 | [diff] [blame] | 1164 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1165 | return ret; |
| 1166 | } |
| 1167 | |
| 1168 | int intel_gpu_reset(struct drm_device *dev) |
| 1169 | { |
Robert Beckett | 542c184 | 2014-06-03 10:08:26 +0200 | [diff] [blame] | 1170 | if (INTEL_INFO(dev)->gen >= 6) |
| 1171 | return gen6_do_reset(dev); |
| 1172 | else if (IS_GEN5(dev)) |
| 1173 | return ironlake_do_reset(dev); |
| 1174 | else if (IS_G4X(dev)) |
| 1175 | return g4x_do_reset(dev); |
| 1176 | else if (IS_GEN4(dev)) |
| 1177 | return i965_do_reset(dev); |
| 1178 | else |
| 1179 | return -ENODEV; |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1180 | } |
| 1181 | |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1182 | void intel_uncore_check_errors(struct drm_device *dev) |
| 1183 | { |
| 1184 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1185 | |
| 1186 | if (HAS_FPGA_DBG_UNCLAIMED(dev) && |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1187 | (__raw_i915_read32(dev_priv, FPGA_DBG) & FPGA_DBG_RM_NOCLAIM)) { |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1188 | DRM_ERROR("Unclaimed register before interrupt\n"); |
Chris Wilson | 6af5d92 | 2013-07-19 20:36:53 +0100 | [diff] [blame] | 1189 | __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); |
Chris Wilson | 907b28c | 2013-07-19 20:36:52 +0100 | [diff] [blame] | 1190 | } |
| 1191 | } |