Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Keith Packard <keithp@keithp.com> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include <linux/i2c.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 29 | #include <linux/slab.h> |
Paul Gortmaker | 2d1a8a4 | 2011-08-30 18:16:33 -0400 | [diff] [blame] | 30 | #include <linux/export.h> |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 31 | #include <drm/drmP.h> |
| 32 | #include <drm/drm_crtc.h> |
| 33 | #include <drm/drm_crtc_helper.h> |
| 34 | #include <drm/drm_edid.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 35 | #include "intel_drv.h" |
David Howells | 760285e | 2012-10-02 18:01:07 +0100 | [diff] [blame] | 36 | #include <drm/i915_drm.h> |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 37 | #include "i915_drv.h" |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 38 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 39 | #define DP_LINK_CHECK_TIMEOUT (10 * 1000) |
| 40 | |
Jesse Barnes | cfcb0fc | 2010-10-07 16:01:06 -0700 | [diff] [blame] | 41 | /** |
| 42 | * is_edp - is the given port attached to an eDP panel (either CPU or PCH) |
| 43 | * @intel_dp: DP struct |
| 44 | * |
| 45 | * If a CPU or PCH DP output is attached to an eDP panel, this function |
| 46 | * will return true, and false otherwise. |
| 47 | */ |
| 48 | static bool is_edp(struct intel_dp *intel_dp) |
| 49 | { |
| 50 | return intel_dp->base.type == INTEL_OUTPUT_EDP; |
| 51 | } |
| 52 | |
| 53 | /** |
| 54 | * is_pch_edp - is the port on the PCH and attached to an eDP panel? |
| 55 | * @intel_dp: DP struct |
| 56 | * |
| 57 | * Returns true if the given DP struct corresponds to a PCH DP port attached |
| 58 | * to an eDP panel, false otherwise. Helpful for determining whether we |
| 59 | * may need FDI resources for a given DP output or not. |
| 60 | */ |
| 61 | static bool is_pch_edp(struct intel_dp *intel_dp) |
| 62 | { |
| 63 | return intel_dp->is_pch_edp; |
| 64 | } |
| 65 | |
Adam Jackson | 1c95822 | 2011-10-14 17:22:25 -0400 | [diff] [blame] | 66 | /** |
| 67 | * is_cpu_edp - is the port on the CPU and attached to an eDP panel? |
| 68 | * @intel_dp: DP struct |
| 69 | * |
| 70 | * Returns true if the given DP struct corresponds to a CPU eDP port. |
| 71 | */ |
| 72 | static bool is_cpu_edp(struct intel_dp *intel_dp) |
| 73 | { |
| 74 | return is_edp(intel_dp) && !is_pch_edp(intel_dp); |
| 75 | } |
| 76 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 77 | static struct intel_dp *intel_attached_dp(struct drm_connector *connector) |
| 78 | { |
| 79 | return container_of(intel_attached_encoder(connector), |
| 80 | struct intel_dp, base); |
| 81 | } |
| 82 | |
Jesse Barnes | 814948a | 2010-10-07 16:01:09 -0700 | [diff] [blame] | 83 | /** |
| 84 | * intel_encoder_is_pch_edp - is the given encoder a PCH attached eDP? |
| 85 | * @encoder: DRM encoder |
| 86 | * |
| 87 | * Return true if @encoder corresponds to a PCH attached eDP panel. Needed |
| 88 | * by intel_display.c. |
| 89 | */ |
| 90 | bool intel_encoder_is_pch_edp(struct drm_encoder *encoder) |
| 91 | { |
| 92 | struct intel_dp *intel_dp; |
| 93 | |
| 94 | if (!encoder) |
| 95 | return false; |
| 96 | |
| 97 | intel_dp = enc_to_intel_dp(encoder); |
| 98 | |
| 99 | return is_pch_edp(intel_dp); |
| 100 | } |
| 101 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 102 | static void intel_dp_link_down(struct intel_dp *intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 103 | |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 104 | void |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 105 | intel_edp_link_config(struct intel_encoder *intel_encoder, |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 106 | int *lane_num, int *link_bw) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 107 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 108 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 109 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 110 | *lane_num = intel_dp->lane_count; |
Daniel Vetter | 3b5c662 | 2012-10-18 10:15:31 +0200 | [diff] [blame] | 111 | *link_bw = drm_dp_bw_code_to_link_rate(intel_dp->link_bw); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 112 | } |
| 113 | |
Daniel Vetter | 94bf2ce | 2012-06-04 18:39:19 +0200 | [diff] [blame] | 114 | int |
| 115 | intel_edp_target_clock(struct intel_encoder *intel_encoder, |
| 116 | struct drm_display_mode *mode) |
| 117 | { |
| 118 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 119 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Daniel Vetter | 94bf2ce | 2012-06-04 18:39:19 +0200 | [diff] [blame] | 120 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 121 | if (intel_connector->panel.fixed_mode) |
| 122 | return intel_connector->panel.fixed_mode->clock; |
Daniel Vetter | 94bf2ce | 2012-06-04 18:39:19 +0200 | [diff] [blame] | 123 | else |
| 124 | return mode->clock; |
| 125 | } |
| 126 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 127 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 128 | intel_dp_max_link_bw(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 129 | { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 130 | int max_link_bw = intel_dp->dpcd[DP_MAX_LINK_RATE]; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 131 | |
| 132 | switch (max_link_bw) { |
| 133 | case DP_LINK_BW_1_62: |
| 134 | case DP_LINK_BW_2_7: |
| 135 | break; |
| 136 | default: |
| 137 | max_link_bw = DP_LINK_BW_1_62; |
| 138 | break; |
| 139 | } |
| 140 | return max_link_bw; |
| 141 | } |
| 142 | |
| 143 | static int |
| 144 | intel_dp_link_clock(uint8_t link_bw) |
| 145 | { |
| 146 | if (link_bw == DP_LINK_BW_2_7) |
| 147 | return 270000; |
| 148 | else |
| 149 | return 162000; |
| 150 | } |
| 151 | |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 152 | /* |
| 153 | * The units on the numbers in the next two are... bizarre. Examples will |
| 154 | * make it clearer; this one parallels an example in the eDP spec. |
| 155 | * |
| 156 | * intel_dp_max_data_rate for one lane of 2.7GHz evaluates as: |
| 157 | * |
| 158 | * 270000 * 1 * 8 / 10 == 216000 |
| 159 | * |
| 160 | * The actual data capacity of that configuration is 2.16Gbit/s, so the |
| 161 | * units are decakilobits. ->clock in a drm_display_mode is in kilohertz - |
| 162 | * or equivalently, kilopixels per second - so for 1680x1050R it'd be |
| 163 | * 119000. At 18bpp that's 2142000 kilobits per second. |
| 164 | * |
| 165 | * Thus the strange-looking division by 10 in intel_dp_link_required, to |
| 166 | * get the result in decakilobits instead of kilobits. |
| 167 | */ |
| 168 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 169 | static int |
Keith Packard | c898261 | 2012-01-25 08:16:25 -0800 | [diff] [blame] | 170 | intel_dp_link_required(int pixel_clock, int bpp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 171 | { |
Adam Jackson | cd9dde4 | 2011-10-14 12:43:49 -0400 | [diff] [blame] | 172 | return (pixel_clock * bpp + 9) / 10; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 173 | } |
| 174 | |
| 175 | static int |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 176 | intel_dp_max_data_rate(int max_link_clock, int max_lanes) |
| 177 | { |
| 178 | return (max_link_clock * max_lanes * 8) / 10; |
| 179 | } |
| 180 | |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 181 | static bool |
| 182 | intel_dp_adjust_dithering(struct intel_dp *intel_dp, |
| 183 | struct drm_display_mode *mode, |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 184 | bool adjust_mode) |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 185 | { |
| 186 | int max_link_clock = intel_dp_link_clock(intel_dp_max_link_bw(intel_dp)); |
Daniel Vetter | 397fe15 | 2012-10-22 22:56:43 +0200 | [diff] [blame] | 187 | int max_lanes = drm_dp_max_lane_count(intel_dp->dpcd); |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 188 | int max_rate, mode_rate; |
| 189 | |
| 190 | mode_rate = intel_dp_link_required(mode->clock, 24); |
| 191 | max_rate = intel_dp_max_data_rate(max_link_clock, max_lanes); |
| 192 | |
| 193 | if (mode_rate > max_rate) { |
| 194 | mode_rate = intel_dp_link_required(mode->clock, 18); |
| 195 | if (mode_rate > max_rate) |
| 196 | return false; |
| 197 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 198 | if (adjust_mode) |
| 199 | mode->private_flags |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 200 | |= INTEL_MODE_DP_FORCE_6BPC; |
| 201 | |
| 202 | return true; |
| 203 | } |
| 204 | |
| 205 | return true; |
| 206 | } |
| 207 | |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 208 | static int |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 209 | intel_dp_mode_valid(struct drm_connector *connector, |
| 210 | struct drm_display_mode *mode) |
| 211 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 212 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 213 | struct intel_connector *intel_connector = to_intel_connector(connector); |
| 214 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 215 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 216 | if (is_edp(intel_dp) && fixed_mode) { |
| 217 | if (mode->hdisplay > fixed_mode->hdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 218 | return MODE_PANEL; |
| 219 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 220 | if (mode->vdisplay > fixed_mode->vdisplay) |
Zhao Yakui | 7de56f4 | 2010-07-19 09:43:14 +0100 | [diff] [blame] | 221 | return MODE_PANEL; |
| 222 | } |
| 223 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 224 | if (!intel_dp_adjust_dithering(intel_dp, mode, false)) |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 225 | return MODE_CLOCK_HIGH; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 226 | |
| 227 | if (mode->clock < 10000) |
| 228 | return MODE_CLOCK_LOW; |
| 229 | |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 230 | if (mode->flags & DRM_MODE_FLAG_DBLCLK) |
| 231 | return MODE_H_ILLEGAL; |
| 232 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 233 | return MODE_OK; |
| 234 | } |
| 235 | |
| 236 | static uint32_t |
| 237 | pack_aux(uint8_t *src, int src_bytes) |
| 238 | { |
| 239 | int i; |
| 240 | uint32_t v = 0; |
| 241 | |
| 242 | if (src_bytes > 4) |
| 243 | src_bytes = 4; |
| 244 | for (i = 0; i < src_bytes; i++) |
| 245 | v |= ((uint32_t) src[i]) << ((3-i) * 8); |
| 246 | return v; |
| 247 | } |
| 248 | |
| 249 | static void |
| 250 | unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes) |
| 251 | { |
| 252 | int i; |
| 253 | if (dst_bytes > 4) |
| 254 | dst_bytes = 4; |
| 255 | for (i = 0; i < dst_bytes; i++) |
| 256 | dst[i] = src >> ((3-i) * 8); |
| 257 | } |
| 258 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 259 | /* hrawclock is 1/4 the FSB frequency */ |
| 260 | static int |
| 261 | intel_hrawclk(struct drm_device *dev) |
| 262 | { |
| 263 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 264 | uint32_t clkcfg; |
| 265 | |
Vijay Purushothaman | 9473c8f | 2012-09-27 19:13:01 +0530 | [diff] [blame] | 266 | /* There is no CLKCFG reg in Valleyview. VLV hrawclk is 200 MHz */ |
| 267 | if (IS_VALLEYVIEW(dev)) |
| 268 | return 200; |
| 269 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 270 | clkcfg = I915_READ(CLKCFG); |
| 271 | switch (clkcfg & CLKCFG_FSB_MASK) { |
| 272 | case CLKCFG_FSB_400: |
| 273 | return 100; |
| 274 | case CLKCFG_FSB_533: |
| 275 | return 133; |
| 276 | case CLKCFG_FSB_667: |
| 277 | return 166; |
| 278 | case CLKCFG_FSB_800: |
| 279 | return 200; |
| 280 | case CLKCFG_FSB_1067: |
| 281 | return 266; |
| 282 | case CLKCFG_FSB_1333: |
| 283 | return 333; |
| 284 | /* these two are just a guess; one of them might be right */ |
| 285 | case CLKCFG_FSB_1600: |
| 286 | case CLKCFG_FSB_1600_ALT: |
| 287 | return 400; |
| 288 | default: |
| 289 | return 133; |
| 290 | } |
| 291 | } |
| 292 | |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 293 | static bool ironlake_edp_have_panel_power(struct intel_dp *intel_dp) |
| 294 | { |
| 295 | struct drm_device *dev = intel_dp->base.base.dev; |
| 296 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 297 | |
| 298 | return (I915_READ(PCH_PP_STATUS) & PP_ON) != 0; |
| 299 | } |
| 300 | |
| 301 | static bool ironlake_edp_have_panel_vdd(struct intel_dp *intel_dp) |
| 302 | { |
| 303 | struct drm_device *dev = intel_dp->base.base.dev; |
| 304 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 305 | |
| 306 | return (I915_READ(PCH_PP_CONTROL) & EDP_FORCE_VDD) != 0; |
| 307 | } |
| 308 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 309 | static void |
| 310 | intel_dp_check_edp(struct intel_dp *intel_dp) |
| 311 | { |
| 312 | struct drm_device *dev = intel_dp->base.base.dev; |
| 313 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 314 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 315 | if (!is_edp(intel_dp)) |
| 316 | return; |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 317 | if (!ironlake_edp_have_panel_power(intel_dp) && !ironlake_edp_have_panel_vdd(intel_dp)) { |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 318 | WARN(1, "eDP powered off while attempting aux channel communication.\n"); |
| 319 | DRM_DEBUG_KMS("Status 0x%08x Control 0x%08x\n", |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 320 | I915_READ(PCH_PP_STATUS), |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 321 | I915_READ(PCH_PP_CONTROL)); |
| 322 | } |
| 323 | } |
| 324 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 325 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 326 | intel_dp_aux_ch(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 327 | uint8_t *send, int send_bytes, |
| 328 | uint8_t *recv, int recv_size) |
| 329 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 330 | uint32_t output_reg = intel_dp->output_reg; |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 331 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 332 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 333 | uint32_t ch_ctl = output_reg + 0x10; |
| 334 | uint32_t ch_data = ch_ctl + 4; |
| 335 | int i; |
| 336 | int recv_bytes; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 337 | uint32_t status; |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 338 | uint32_t aux_clock_divider; |
Daniel Vetter | 6b4e0a9 | 2012-06-14 22:15:00 +0200 | [diff] [blame] | 339 | int try, precharge; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 340 | |
Paulo Zanoni | 750eb99 | 2012-10-18 16:25:08 +0200 | [diff] [blame] | 341 | if (IS_HASWELL(dev)) { |
| 342 | switch (intel_dp->port) { |
| 343 | case PORT_A: |
| 344 | ch_ctl = DPA_AUX_CH_CTL; |
| 345 | ch_data = DPA_AUX_CH_DATA1; |
| 346 | break; |
| 347 | case PORT_B: |
| 348 | ch_ctl = PCH_DPB_AUX_CH_CTL; |
| 349 | ch_data = PCH_DPB_AUX_CH_DATA1; |
| 350 | break; |
| 351 | case PORT_C: |
| 352 | ch_ctl = PCH_DPC_AUX_CH_CTL; |
| 353 | ch_data = PCH_DPC_AUX_CH_DATA1; |
| 354 | break; |
| 355 | case PORT_D: |
| 356 | ch_ctl = PCH_DPD_AUX_CH_CTL; |
| 357 | ch_data = PCH_DPD_AUX_CH_DATA1; |
| 358 | break; |
| 359 | default: |
| 360 | BUG(); |
| 361 | } |
| 362 | } |
| 363 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 364 | intel_dp_check_edp(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 365 | /* The clock divider is based off the hrawclk, |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 366 | * and would like to run at 2MHz. So, take the |
| 367 | * hrawclk value and divide by 2 and use that |
Jesse Barnes | 6176b8f | 2010-09-08 12:42:00 -0700 | [diff] [blame] | 368 | * |
| 369 | * Note that PCH attached eDP panels should use a 125MHz input |
| 370 | * clock divider. |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 371 | */ |
Adam Jackson | 1c95822 | 2011-10-14 17:22:25 -0400 | [diff] [blame] | 372 | if (is_cpu_edp(intel_dp)) { |
Vijay Purushothaman | 9473c8f | 2012-09-27 19:13:01 +0530 | [diff] [blame] | 373 | if (IS_VALLEYVIEW(dev)) |
| 374 | aux_clock_divider = 100; |
| 375 | else if (IS_GEN6(dev) || IS_GEN7(dev)) |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 376 | aux_clock_divider = 200; /* SNB & IVB eDP input clock at 400Mhz */ |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 377 | else |
| 378 | aux_clock_divider = 225; /* eDP input clock at 450Mhz */ |
| 379 | } else if (HAS_PCH_SPLIT(dev)) |
Adam Jackson | 6919132 | 2011-07-26 15:39:44 -0400 | [diff] [blame] | 380 | aux_clock_divider = 63; /* IRL input clock fixed at 125Mhz */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 381 | else |
| 382 | aux_clock_divider = intel_hrawclk(dev) / 2; |
| 383 | |
Daniel Vetter | 6b4e0a9 | 2012-06-14 22:15:00 +0200 | [diff] [blame] | 384 | if (IS_GEN6(dev)) |
| 385 | precharge = 3; |
| 386 | else |
| 387 | precharge = 5; |
| 388 | |
Jesse Barnes | 11bee43 | 2011-08-01 15:02:20 -0700 | [diff] [blame] | 389 | /* Try to wait for any previous AUX channel activity */ |
| 390 | for (try = 0; try < 3; try++) { |
| 391 | status = I915_READ(ch_ctl); |
| 392 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 393 | break; |
| 394 | msleep(1); |
| 395 | } |
| 396 | |
| 397 | if (try == 3) { |
| 398 | WARN(1, "dp_aux_ch not started status 0x%08x\n", |
| 399 | I915_READ(ch_ctl)); |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 400 | return -EBUSY; |
| 401 | } |
| 402 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 403 | /* Must try at least 3 times according to DP spec */ |
| 404 | for (try = 0; try < 5; try++) { |
| 405 | /* Load the send data into the aux channel data registers */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 406 | for (i = 0; i < send_bytes; i += 4) |
| 407 | I915_WRITE(ch_data + i, |
| 408 | pack_aux(send + i, send_bytes - i)); |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 409 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 410 | /* Send the command and wait for it to complete */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 411 | I915_WRITE(ch_ctl, |
| 412 | DP_AUX_CH_CTL_SEND_BUSY | |
| 413 | DP_AUX_CH_CTL_TIME_OUT_400us | |
| 414 | (send_bytes << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) | |
| 415 | (precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) | |
| 416 | (aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT) | |
| 417 | DP_AUX_CH_CTL_DONE | |
| 418 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 419 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 420 | for (;;) { |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 421 | status = I915_READ(ch_ctl); |
| 422 | if ((status & DP_AUX_CH_CTL_SEND_BUSY) == 0) |
| 423 | break; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 424 | udelay(100); |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 425 | } |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 426 | |
Keith Packard | fb0f8fb | 2009-06-11 22:31:31 -0700 | [diff] [blame] | 427 | /* Clear done status and any errors */ |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 428 | I915_WRITE(ch_ctl, |
| 429 | status | |
| 430 | DP_AUX_CH_CTL_DONE | |
| 431 | DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 432 | DP_AUX_CH_CTL_RECEIVE_ERROR); |
Adam Jackson | d7e96fe | 2011-07-26 15:39:46 -0400 | [diff] [blame] | 433 | |
| 434 | if (status & (DP_AUX_CH_CTL_TIME_OUT_ERROR | |
| 435 | DP_AUX_CH_CTL_RECEIVE_ERROR)) |
| 436 | continue; |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 437 | if (status & DP_AUX_CH_CTL_DONE) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 438 | break; |
| 439 | } |
| 440 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 441 | if ((status & DP_AUX_CH_CTL_DONE) == 0) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 442 | DRM_ERROR("dp_aux_ch not done status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 443 | return -EBUSY; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 444 | } |
| 445 | |
| 446 | /* Check for timeout or receive error. |
| 447 | * Timeouts occur when the sink is not connected |
| 448 | */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 449 | if (status & DP_AUX_CH_CTL_RECEIVE_ERROR) { |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 450 | DRM_ERROR("dp_aux_ch receive error status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 451 | return -EIO; |
| 452 | } |
Keith Packard | 1ae8c0a | 2009-06-28 15:42:17 -0700 | [diff] [blame] | 453 | |
| 454 | /* Timeouts occur when the device isn't connected, so they're |
| 455 | * "normal" -- don't fill the kernel log with these */ |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 456 | if (status & DP_AUX_CH_CTL_TIME_OUT_ERROR) { |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 457 | DRM_DEBUG_KMS("dp_aux_ch timeout status 0x%08x\n", status); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 458 | return -ETIMEDOUT; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 459 | } |
| 460 | |
| 461 | /* Unload any bytes sent back from the other side */ |
| 462 | recv_bytes = ((status & DP_AUX_CH_CTL_MESSAGE_SIZE_MASK) >> |
| 463 | DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 464 | if (recv_bytes > recv_size) |
| 465 | recv_bytes = recv_size; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 466 | |
Chris Wilson | 4f7f7b7 | 2010-08-18 18:12:56 +0100 | [diff] [blame] | 467 | for (i = 0; i < recv_bytes; i += 4) |
| 468 | unpack_aux(I915_READ(ch_data + i), |
| 469 | recv + i, recv_bytes - i); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 470 | |
| 471 | return recv_bytes; |
| 472 | } |
| 473 | |
| 474 | /* Write data to the aux channel in native mode */ |
| 475 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 476 | intel_dp_aux_native_write(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 477 | uint16_t address, uint8_t *send, int send_bytes) |
| 478 | { |
| 479 | int ret; |
| 480 | uint8_t msg[20]; |
| 481 | int msg_bytes; |
| 482 | uint8_t ack; |
| 483 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 484 | intel_dp_check_edp(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 485 | if (send_bytes > 16) |
| 486 | return -1; |
| 487 | msg[0] = AUX_NATIVE_WRITE << 4; |
| 488 | msg[1] = address >> 8; |
Zhenyu Wang | eebc863 | 2009-07-24 01:00:30 +0800 | [diff] [blame] | 489 | msg[2] = address & 0xff; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 490 | msg[3] = send_bytes - 1; |
| 491 | memcpy(&msg[4], send, send_bytes); |
| 492 | msg_bytes = send_bytes + 4; |
| 493 | for (;;) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 494 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, &ack, 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 495 | if (ret < 0) |
| 496 | return ret; |
| 497 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) |
| 498 | break; |
| 499 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 500 | udelay(100); |
| 501 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 502 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 503 | } |
| 504 | return send_bytes; |
| 505 | } |
| 506 | |
| 507 | /* Write a single byte to the aux channel in native mode */ |
| 508 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 509 | intel_dp_aux_native_write_1(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 510 | uint16_t address, uint8_t byte) |
| 511 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 512 | return intel_dp_aux_native_write(intel_dp, address, &byte, 1); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 513 | } |
| 514 | |
| 515 | /* read bytes from a native aux channel */ |
| 516 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 517 | intel_dp_aux_native_read(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 518 | uint16_t address, uint8_t *recv, int recv_bytes) |
| 519 | { |
| 520 | uint8_t msg[4]; |
| 521 | int msg_bytes; |
| 522 | uint8_t reply[20]; |
| 523 | int reply_bytes; |
| 524 | uint8_t ack; |
| 525 | int ret; |
| 526 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 527 | intel_dp_check_edp(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 528 | msg[0] = AUX_NATIVE_READ << 4; |
| 529 | msg[1] = address >> 8; |
| 530 | msg[2] = address & 0xff; |
| 531 | msg[3] = recv_bytes - 1; |
| 532 | |
| 533 | msg_bytes = 4; |
| 534 | reply_bytes = recv_bytes + 1; |
| 535 | |
| 536 | for (;;) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 537 | ret = intel_dp_aux_ch(intel_dp, msg, msg_bytes, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 538 | reply, reply_bytes); |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 539 | if (ret == 0) |
| 540 | return -EPROTO; |
| 541 | if (ret < 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 542 | return ret; |
| 543 | ack = reply[0]; |
| 544 | if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_ACK) { |
| 545 | memcpy(recv, reply + 1, ret - 1); |
| 546 | return ret - 1; |
| 547 | } |
| 548 | else if ((ack & AUX_NATIVE_REPLY_MASK) == AUX_NATIVE_REPLY_DEFER) |
| 549 | udelay(100); |
| 550 | else |
Keith Packard | a5b3da5 | 2009-06-11 22:30:32 -0700 | [diff] [blame] | 551 | return -EIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 552 | } |
| 553 | } |
| 554 | |
| 555 | static int |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 556 | intel_dp_i2c_aux_ch(struct i2c_adapter *adapter, int mode, |
| 557 | uint8_t write_byte, uint8_t *read_byte) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 558 | { |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 559 | struct i2c_algo_dp_aux_data *algo_data = adapter->algo_data; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 560 | struct intel_dp *intel_dp = container_of(adapter, |
| 561 | struct intel_dp, |
| 562 | adapter); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 563 | uint16_t address = algo_data->address; |
| 564 | uint8_t msg[5]; |
| 565 | uint8_t reply[2]; |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 566 | unsigned retry; |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 567 | int msg_bytes; |
| 568 | int reply_bytes; |
| 569 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 570 | |
Keith Packard | 9b984da | 2011-09-19 13:54:47 -0700 | [diff] [blame] | 571 | intel_dp_check_edp(intel_dp); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 572 | /* Set up the command byte */ |
| 573 | if (mode & MODE_I2C_READ) |
| 574 | msg[0] = AUX_I2C_READ << 4; |
| 575 | else |
| 576 | msg[0] = AUX_I2C_WRITE << 4; |
| 577 | |
| 578 | if (!(mode & MODE_I2C_STOP)) |
| 579 | msg[0] |= AUX_I2C_MOT << 4; |
| 580 | |
| 581 | msg[1] = address >> 8; |
| 582 | msg[2] = address; |
| 583 | |
| 584 | switch (mode) { |
| 585 | case MODE_I2C_WRITE: |
| 586 | msg[3] = 0; |
| 587 | msg[4] = write_byte; |
| 588 | msg_bytes = 5; |
| 589 | reply_bytes = 1; |
| 590 | break; |
| 591 | case MODE_I2C_READ: |
| 592 | msg[3] = 0; |
| 593 | msg_bytes = 4; |
| 594 | reply_bytes = 2; |
| 595 | break; |
| 596 | default: |
| 597 | msg_bytes = 3; |
| 598 | reply_bytes = 1; |
| 599 | break; |
| 600 | } |
| 601 | |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 602 | for (retry = 0; retry < 5; retry++) { |
| 603 | ret = intel_dp_aux_ch(intel_dp, |
| 604 | msg, msg_bytes, |
| 605 | reply, reply_bytes); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 606 | if (ret < 0) { |
Dave Airlie | 3ff9916 | 2009-12-08 14:03:47 +1000 | [diff] [blame] | 607 | DRM_DEBUG_KMS("aux_ch failed %d\n", ret); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 608 | return ret; |
| 609 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 610 | |
| 611 | switch (reply[0] & AUX_NATIVE_REPLY_MASK) { |
| 612 | case AUX_NATIVE_REPLY_ACK: |
| 613 | /* I2C-over-AUX Reply field is only valid |
| 614 | * when paired with AUX ACK. |
| 615 | */ |
| 616 | break; |
| 617 | case AUX_NATIVE_REPLY_NACK: |
| 618 | DRM_DEBUG_KMS("aux_ch native nack\n"); |
| 619 | return -EREMOTEIO; |
| 620 | case AUX_NATIVE_REPLY_DEFER: |
| 621 | udelay(100); |
| 622 | continue; |
| 623 | default: |
| 624 | DRM_ERROR("aux_ch invalid native reply 0x%02x\n", |
| 625 | reply[0]); |
| 626 | return -EREMOTEIO; |
| 627 | } |
| 628 | |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 629 | switch (reply[0] & AUX_I2C_REPLY_MASK) { |
| 630 | case AUX_I2C_REPLY_ACK: |
| 631 | if (mode == MODE_I2C_READ) { |
| 632 | *read_byte = reply[1]; |
| 633 | } |
| 634 | return reply_bytes - 1; |
| 635 | case AUX_I2C_REPLY_NACK: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 636 | DRM_DEBUG_KMS("aux_i2c nack\n"); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 637 | return -EREMOTEIO; |
| 638 | case AUX_I2C_REPLY_DEFER: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 639 | DRM_DEBUG_KMS("aux_i2c defer\n"); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 640 | udelay(100); |
| 641 | break; |
| 642 | default: |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 643 | DRM_ERROR("aux_i2c invalid reply 0x%02x\n", reply[0]); |
Dave Airlie | ab2c067 | 2009-12-04 10:55:24 +1000 | [diff] [blame] | 644 | return -EREMOTEIO; |
| 645 | } |
| 646 | } |
David Flynn | 8316f33 | 2010-12-08 16:10:21 +0000 | [diff] [blame] | 647 | |
| 648 | DRM_ERROR("too many retries, giving up\n"); |
| 649 | return -EREMOTEIO; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 650 | } |
| 651 | |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 652 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 653 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync); |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 654 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 655 | static int |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 656 | intel_dp_i2c_init(struct intel_dp *intel_dp, |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 657 | struct intel_connector *intel_connector, const char *name) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 658 | { |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 659 | int ret; |
| 660 | |
Zhenyu Wang | d54e9d2 | 2009-10-19 15:43:51 +0800 | [diff] [blame] | 661 | DRM_DEBUG_KMS("i2c_init %s\n", name); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 662 | intel_dp->algo.running = false; |
| 663 | intel_dp->algo.address = 0; |
| 664 | intel_dp->algo.aux_ch = intel_dp_i2c_aux_ch; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 665 | |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 666 | memset(&intel_dp->adapter, '\0', sizeof(intel_dp->adapter)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 667 | intel_dp->adapter.owner = THIS_MODULE; |
| 668 | intel_dp->adapter.class = I2C_CLASS_DDC; |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 669 | strncpy(intel_dp->adapter.name, name, sizeof(intel_dp->adapter.name) - 1); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 670 | intel_dp->adapter.name[sizeof(intel_dp->adapter.name) - 1] = '\0'; |
| 671 | intel_dp->adapter.algo_data = &intel_dp->algo; |
| 672 | intel_dp->adapter.dev.parent = &intel_connector->base.kdev; |
| 673 | |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 674 | ironlake_edp_panel_vdd_on(intel_dp); |
| 675 | ret = i2c_dp_aux_add_bus(&intel_dp->adapter); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 676 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Keith Packard | 0b5c541 | 2011-09-28 16:41:05 -0700 | [diff] [blame] | 677 | return ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 678 | } |
| 679 | |
| 680 | static bool |
Laurent Pinchart | e811f5a | 2012-07-17 17:56:50 +0200 | [diff] [blame] | 681 | intel_dp_mode_fixup(struct drm_encoder *encoder, |
| 682 | const struct drm_display_mode *mode, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 683 | struct drm_display_mode *adjusted_mode) |
| 684 | { |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 685 | struct drm_device *dev = encoder->dev; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 686 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 687 | struct intel_connector *intel_connector = intel_dp->attached_connector; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 688 | int lane_count, clock; |
Daniel Vetter | 397fe15 | 2012-10-22 22:56:43 +0200 | [diff] [blame] | 689 | int max_lane_count = drm_dp_max_lane_count(intel_dp->dpcd); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 690 | int max_clock = intel_dp_max_link_bw(intel_dp) == DP_LINK_BW_2_7 ? 1 : 0; |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 691 | int bpp, mode_rate; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 692 | static int bws[2] = { DP_LINK_BW_1_62, DP_LINK_BW_2_7 }; |
| 693 | |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 694 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
| 695 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
| 696 | adjusted_mode); |
Chris Wilson | 1d8e1c7 | 2010-08-07 11:01:28 +0100 | [diff] [blame] | 697 | intel_pch_panel_fitting(dev, DRM_MODE_SCALE_FULLSCREEN, |
| 698 | mode, adjusted_mode); |
Zhao Yakui | 0d3a1be | 2010-07-19 09:43:13 +0100 | [diff] [blame] | 699 | } |
| 700 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 701 | if (adjusted_mode->flags & DRM_MODE_FLAG_DBLCLK) |
Daniel Vetter | 0af78a2 | 2012-05-23 11:30:55 +0200 | [diff] [blame] | 702 | return false; |
| 703 | |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 704 | DRM_DEBUG_KMS("DP link computation with max lane count %i " |
| 705 | "max bw %02x pixel clock %iKHz\n", |
Daniel Vetter | 7124465 | 2012-06-04 18:39:20 +0200 | [diff] [blame] | 706 | max_lane_count, bws[max_clock], adjusted_mode->clock); |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 707 | |
Daniel Vetter | cb1793c | 2012-06-04 18:39:21 +0200 | [diff] [blame] | 708 | if (!intel_dp_adjust_dithering(intel_dp, adjusted_mode, true)) |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 709 | return false; |
| 710 | |
| 711 | bpp = adjusted_mode->private_flags & INTEL_MODE_DP_FORCE_6BPC ? 18 : 24; |
Daniel Vetter | 7124465 | 2012-06-04 18:39:20 +0200 | [diff] [blame] | 712 | mode_rate = intel_dp_link_required(adjusted_mode->clock, bpp); |
Daniel Vetter | c486793 | 2012-04-10 10:42:36 +0200 | [diff] [blame] | 713 | |
Jesse Barnes | 2514bc5 | 2012-06-21 15:13:50 -0700 | [diff] [blame] | 714 | for (clock = 0; clock <= max_clock; clock++) { |
| 715 | for (lane_count = 1; lane_count <= max_lane_count; lane_count <<= 1) { |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 716 | int link_avail = intel_dp_max_data_rate(intel_dp_link_clock(bws[clock]), lane_count); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 717 | |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 718 | if (mode_rate <= link_avail) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 719 | intel_dp->link_bw = bws[clock]; |
| 720 | intel_dp->lane_count = lane_count; |
| 721 | adjusted_mode->clock = intel_dp_link_clock(intel_dp->link_bw); |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 722 | DRM_DEBUG_KMS("DP link bw %02x lane " |
| 723 | "count %d clock %d bpp %d\n", |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 724 | intel_dp->link_bw, intel_dp->lane_count, |
Daniel Vetter | 083f956 | 2012-04-20 20:23:49 +0200 | [diff] [blame] | 725 | adjusted_mode->clock, bpp); |
| 726 | DRM_DEBUG_KMS("DP link bw required %i available %i\n", |
| 727 | mode_rate, link_avail); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 728 | return true; |
| 729 | } |
| 730 | } |
| 731 | } |
Dave Airlie | fe27d53 | 2010-06-30 11:46:17 +1000 | [diff] [blame] | 732 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 733 | return false; |
| 734 | } |
| 735 | |
| 736 | struct intel_dp_m_n { |
| 737 | uint32_t tu; |
| 738 | uint32_t gmch_m; |
| 739 | uint32_t gmch_n; |
| 740 | uint32_t link_m; |
| 741 | uint32_t link_n; |
| 742 | }; |
| 743 | |
| 744 | static void |
| 745 | intel_reduce_ratio(uint32_t *num, uint32_t *den) |
| 746 | { |
| 747 | while (*num > 0xffffff || *den > 0xffffff) { |
| 748 | *num >>= 1; |
| 749 | *den >>= 1; |
| 750 | } |
| 751 | } |
| 752 | |
| 753 | static void |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 754 | intel_dp_compute_m_n(int bpp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 755 | int nlanes, |
| 756 | int pixel_clock, |
| 757 | int link_clock, |
| 758 | struct intel_dp_m_n *m_n) |
| 759 | { |
| 760 | m_n->tu = 64; |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 761 | m_n->gmch_m = (pixel_clock * bpp) >> 3; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 762 | m_n->gmch_n = link_clock * nlanes; |
| 763 | intel_reduce_ratio(&m_n->gmch_m, &m_n->gmch_n); |
| 764 | m_n->link_m = pixel_clock; |
| 765 | m_n->link_n = link_clock; |
| 766 | intel_reduce_ratio(&m_n->link_m, &m_n->link_n); |
| 767 | } |
| 768 | |
| 769 | void |
| 770 | intel_dp_set_m_n(struct drm_crtc *crtc, struct drm_display_mode *mode, |
| 771 | struct drm_display_mode *adjusted_mode) |
| 772 | { |
| 773 | struct drm_device *dev = crtc->dev; |
Daniel Vetter | 6c2b7c12 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 774 | struct intel_encoder *encoder; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 775 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 776 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
Jesse Barnes | 858fa035 | 2011-06-24 12:19:24 -0700 | [diff] [blame] | 777 | int lane_count = 4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 778 | struct intel_dp_m_n m_n; |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 779 | int pipe = intel_crtc->pipe; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 780 | |
| 781 | /* |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 782 | * Find the lane count in the intel_encoder private |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 783 | */ |
Daniel Vetter | 6c2b7c12 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 784 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 785 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 786 | |
Keith Packard | 9a10f40 | 2011-11-02 13:03:47 -0700 | [diff] [blame] | 787 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || |
| 788 | intel_dp->base.type == INTEL_OUTPUT_EDP) |
| 789 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 790 | lane_count = intel_dp->lane_count; |
Jesse Barnes | 5119066 | 2010-10-07 16:01:08 -0700 | [diff] [blame] | 791 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 792 | } |
| 793 | } |
| 794 | |
| 795 | /* |
| 796 | * Compute the GMCH and Link ratios. The '3' here is |
| 797 | * the number of bytes_per_pixel post-LUT, which we always |
| 798 | * set up for 8-bits of R/G/B, or 3 bytes total. |
| 799 | */ |
Jesse Barnes | 858fa035 | 2011-06-24 12:19:24 -0700 | [diff] [blame] | 800 | intel_dp_compute_m_n(intel_crtc->bpp, lane_count, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 801 | mode->clock, adjusted_mode->clock, &m_n); |
| 802 | |
Paulo Zanoni | 1eb8dfe | 2012-10-18 12:42:10 -0300 | [diff] [blame] | 803 | if (IS_HASWELL(dev)) { |
| 804 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
| 805 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
| 806 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
| 807 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
| 808 | } else if (HAS_PCH_SPLIT(dev)) { |
Paulo Zanoni | 7346bfa | 2012-10-15 15:51:35 -0300 | [diff] [blame] | 809 | I915_WRITE(TRANSDATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 810 | I915_WRITE(TRANSDATA_N1(pipe), m_n.gmch_n); |
| 811 | I915_WRITE(TRANSDPLINK_M1(pipe), m_n.link_m); |
| 812 | I915_WRITE(TRANSDPLINK_N1(pipe), m_n.link_n); |
Vijay Purushothaman | 74a4dd2 | 2012-09-27 19:13:04 +0530 | [diff] [blame] | 813 | } else if (IS_VALLEYVIEW(dev)) { |
| 814 | I915_WRITE(PIPE_DATA_M1(pipe), TU_SIZE(m_n.tu) | m_n.gmch_m); |
| 815 | I915_WRITE(PIPE_DATA_N1(pipe), m_n.gmch_n); |
| 816 | I915_WRITE(PIPE_LINK_M1(pipe), m_n.link_m); |
| 817 | I915_WRITE(PIPE_LINK_N1(pipe), m_n.link_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 818 | } else { |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 819 | I915_WRITE(PIPE_GMCH_DATA_M(pipe), |
Paulo Zanoni | 7346bfa | 2012-10-15 15:51:35 -0300 | [diff] [blame] | 820 | TU_SIZE(m_n.tu) | m_n.gmch_m); |
Jesse Barnes | 9db4a9c | 2011-02-07 12:26:52 -0800 | [diff] [blame] | 821 | I915_WRITE(PIPE_GMCH_DATA_N(pipe), m_n.gmch_n); |
| 822 | I915_WRITE(PIPE_DP_LINK_M(pipe), m_n.link_m); |
| 823 | I915_WRITE(PIPE_DP_LINK_N(pipe), m_n.link_n); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 824 | } |
| 825 | } |
| 826 | |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 827 | void intel_dp_init_link_config(struct intel_dp *intel_dp) |
| 828 | { |
| 829 | memset(intel_dp->link_configuration, 0, DP_LINK_CONFIGURATION_SIZE); |
| 830 | intel_dp->link_configuration[0] = intel_dp->link_bw; |
| 831 | intel_dp->link_configuration[1] = intel_dp->lane_count; |
| 832 | intel_dp->link_configuration[8] = DP_SET_ANSI_8B10B; |
| 833 | /* |
| 834 | * Check for DPCD version > 1.1 and enhanced framing support |
| 835 | */ |
| 836 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 837 | (intel_dp->dpcd[DP_MAX_LANE_COUNT] & DP_ENHANCED_FRAME_CAP)) { |
| 838 | intel_dp->link_configuration[1] |= DP_LANE_COUNT_ENHANCED_FRAME_EN; |
| 839 | } |
| 840 | } |
| 841 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 842 | static void |
| 843 | intel_dp_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode, |
| 844 | struct drm_display_mode *adjusted_mode) |
| 845 | { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 846 | struct drm_device *dev = encoder->dev; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 847 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 848 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 849 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 850 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
| 851 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 852 | /* |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 853 | * There are four kinds of DP registers: |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 854 | * |
| 855 | * IBX PCH |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 856 | * SNB CPU |
| 857 | * IVB CPU |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 858 | * CPT PCH |
| 859 | * |
| 860 | * IBX PCH and CPU are the same for almost everything, |
| 861 | * except that the CPU DP PLL is configured in this |
| 862 | * register |
| 863 | * |
| 864 | * CPT PCH is quite different, having many bits moved |
| 865 | * to the TRANS_DP_CTL register instead. That |
| 866 | * configuration happens (oddly) in ironlake_pch_enable |
| 867 | */ |
Adam Jackson | 9c9e792 | 2010-04-05 17:57:59 -0400 | [diff] [blame] | 868 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 869 | /* Preserve the BIOS-computed detected bit. This is |
| 870 | * supposed to be read-only. |
| 871 | */ |
| 872 | intel_dp->DP = I915_READ(intel_dp->output_reg) & DP_DETECTED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 873 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 874 | /* Handle DP bits in common between all three register formats */ |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 875 | intel_dp->DP |= DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 876 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 877 | switch (intel_dp->lane_count) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 878 | case 1: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 879 | intel_dp->DP |= DP_PORT_WIDTH_1; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 880 | break; |
| 881 | case 2: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 882 | intel_dp->DP |= DP_PORT_WIDTH_2; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 883 | break; |
| 884 | case 4: |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 885 | intel_dp->DP |= DP_PORT_WIDTH_4; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 886 | break; |
| 887 | } |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 888 | if (intel_dp->has_audio) { |
| 889 | DRM_DEBUG_DRIVER("Enabling DP audio on pipe %c\n", |
| 890 | pipe_name(intel_crtc->pipe)); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 891 | intel_dp->DP |= DP_AUDIO_OUTPUT_ENABLE; |
Wu Fengguang | e0dac65 | 2011-09-05 14:25:34 +0800 | [diff] [blame] | 892 | intel_write_eld(encoder, adjusted_mode); |
| 893 | } |
Paulo Zanoni | 247d89f | 2012-10-15 15:51:33 -0300 | [diff] [blame] | 894 | |
| 895 | intel_dp_init_link_config(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 896 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 897 | /* Split out the IBX/CPU vs CPT settings */ |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 898 | |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 899 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev) && !IS_VALLEYVIEW(dev)) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 900 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 901 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 902 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 903 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 904 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
| 905 | |
| 906 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
| 907 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 908 | |
| 909 | intel_dp->DP |= intel_crtc->pipe << 29; |
| 910 | |
| 911 | /* don't miss out required setting for eDP */ |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 912 | if (adjusted_mode->clock < 200000) |
| 913 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
| 914 | else |
| 915 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
| 916 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 917 | intel_dp->DP |= intel_dp->color_range; |
| 918 | |
| 919 | if (adjusted_mode->flags & DRM_MODE_FLAG_PHSYNC) |
| 920 | intel_dp->DP |= DP_SYNC_HS_HIGH; |
| 921 | if (adjusted_mode->flags & DRM_MODE_FLAG_PVSYNC) |
| 922 | intel_dp->DP |= DP_SYNC_VS_HIGH; |
| 923 | intel_dp->DP |= DP_LINK_TRAIN_OFF; |
| 924 | |
| 925 | if (intel_dp->link_configuration[1] & DP_LANE_COUNT_ENHANCED_FRAME_EN) |
| 926 | intel_dp->DP |= DP_ENHANCED_FRAMING; |
| 927 | |
| 928 | if (intel_crtc->pipe == 1) |
| 929 | intel_dp->DP |= DP_PIPEB_SELECT; |
| 930 | |
| 931 | if (is_cpu_edp(intel_dp)) { |
| 932 | /* don't miss out required setting for eDP */ |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 933 | if (adjusted_mode->clock < 200000) |
| 934 | intel_dp->DP |= DP_PLL_FREQ_160MHZ; |
| 935 | else |
| 936 | intel_dp->DP |= DP_PLL_FREQ_270MHZ; |
| 937 | } |
| 938 | } else { |
| 939 | intel_dp->DP |= DP_LINK_TRAIN_OFF_CPT; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 940 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 941 | } |
| 942 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 943 | #define IDLE_ON_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 944 | #define IDLE_ON_VALUE (PP_ON | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_ON_IDLE) |
| 945 | |
| 946 | #define IDLE_OFF_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | 0 | PP_SEQUENCE_STATE_MASK) |
| 947 | #define IDLE_OFF_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
| 948 | |
| 949 | #define IDLE_CYCLE_MASK (PP_ON | 0 | PP_SEQUENCE_MASK | PP_CYCLE_DELAY_ACTIVE | PP_SEQUENCE_STATE_MASK) |
| 950 | #define IDLE_CYCLE_VALUE (0 | 0 | PP_SEQUENCE_NONE | 0 | PP_SEQUENCE_STATE_OFF_IDLE) |
| 951 | |
| 952 | static void ironlake_wait_panel_status(struct intel_dp *intel_dp, |
| 953 | u32 mask, |
| 954 | u32 value) |
| 955 | { |
| 956 | struct drm_device *dev = intel_dp->base.base.dev; |
| 957 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 958 | |
| 959 | DRM_DEBUG_KMS("mask %08x value %08x status %08x control %08x\n", |
| 960 | mask, value, |
| 961 | I915_READ(PCH_PP_STATUS), |
| 962 | I915_READ(PCH_PP_CONTROL)); |
| 963 | |
| 964 | if (_wait_for((I915_READ(PCH_PP_STATUS) & mask) == value, 5000, 10)) { |
| 965 | DRM_ERROR("Panel status timeout: status %08x control %08x\n", |
| 966 | I915_READ(PCH_PP_STATUS), |
| 967 | I915_READ(PCH_PP_CONTROL)); |
| 968 | } |
| 969 | } |
| 970 | |
| 971 | static void ironlake_wait_panel_on(struct intel_dp *intel_dp) |
| 972 | { |
| 973 | DRM_DEBUG_KMS("Wait for panel power on\n"); |
| 974 | ironlake_wait_panel_status(intel_dp, IDLE_ON_MASK, IDLE_ON_VALUE); |
| 975 | } |
| 976 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 977 | static void ironlake_wait_panel_off(struct intel_dp *intel_dp) |
| 978 | { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 979 | DRM_DEBUG_KMS("Wait for panel power off time\n"); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 980 | ironlake_wait_panel_status(intel_dp, IDLE_OFF_MASK, IDLE_OFF_VALUE); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 981 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 982 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 983 | static void ironlake_wait_panel_power_cycle(struct intel_dp *intel_dp) |
| 984 | { |
| 985 | DRM_DEBUG_KMS("Wait for panel power cycle\n"); |
| 986 | ironlake_wait_panel_status(intel_dp, IDLE_CYCLE_MASK, IDLE_CYCLE_VALUE); |
| 987 | } |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 988 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 989 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 990 | /* Read the current pp_control value, unlocking the register if it |
| 991 | * is locked |
| 992 | */ |
| 993 | |
| 994 | static u32 ironlake_get_pp_control(struct drm_i915_private *dev_priv) |
| 995 | { |
| 996 | u32 control = I915_READ(PCH_PP_CONTROL); |
| 997 | |
| 998 | control &= ~PANEL_UNLOCK_MASK; |
| 999 | control |= PANEL_UNLOCK_REGS; |
| 1000 | return control; |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1001 | } |
| 1002 | |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1003 | static void ironlake_edp_panel_vdd_on(struct intel_dp *intel_dp) |
| 1004 | { |
| 1005 | struct drm_device *dev = intel_dp->base.base.dev; |
| 1006 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1007 | u32 pp; |
| 1008 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1009 | if (!is_edp(intel_dp)) |
| 1010 | return; |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1011 | DRM_DEBUG_KMS("Turn eDP VDD on\n"); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1012 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1013 | WARN(intel_dp->want_panel_vdd, |
| 1014 | "eDP VDD already requested on\n"); |
| 1015 | |
| 1016 | intel_dp->want_panel_vdd = true; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1017 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1018 | if (ironlake_edp_have_panel_vdd(intel_dp)) { |
| 1019 | DRM_DEBUG_KMS("eDP VDD already on\n"); |
| 1020 | return; |
| 1021 | } |
| 1022 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1023 | if (!ironlake_edp_have_panel_power(intel_dp)) |
| 1024 | ironlake_wait_panel_power_cycle(intel_dp); |
| 1025 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1026 | pp = ironlake_get_pp_control(dev_priv); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1027 | pp |= EDP_FORCE_VDD; |
| 1028 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1029 | POSTING_READ(PCH_PP_CONTROL); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1030 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
| 1031 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); |
Keith Packard | ebf33b1 | 2011-09-29 15:53:27 -0700 | [diff] [blame] | 1032 | |
| 1033 | /* |
| 1034 | * If the panel wasn't on, delay before accessing aux channel |
| 1035 | */ |
| 1036 | if (!ironlake_edp_have_panel_power(intel_dp)) { |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1037 | DRM_DEBUG_KMS("eDP was not running\n"); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1038 | msleep(intel_dp->panel_power_up_delay); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1039 | } |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1040 | } |
| 1041 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1042 | static void ironlake_panel_vdd_off_sync(struct intel_dp *intel_dp) |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1043 | { |
| 1044 | struct drm_device *dev = intel_dp->base.base.dev; |
| 1045 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1046 | u32 pp; |
| 1047 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1048 | if (!intel_dp->want_panel_vdd && ironlake_edp_have_panel_vdd(intel_dp)) { |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1049 | pp = ironlake_get_pp_control(dev_priv); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1050 | pp &= ~EDP_FORCE_VDD; |
| 1051 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1052 | POSTING_READ(PCH_PP_CONTROL); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1053 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1054 | /* Make sure sequencer is idle before allowing subsequent activity */ |
| 1055 | DRM_DEBUG_KMS("PCH_PP_STATUS: 0x%08x PCH_PP_CONTROL: 0x%08x\n", |
| 1056 | I915_READ(PCH_PP_STATUS), I915_READ(PCH_PP_CONTROL)); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1057 | |
| 1058 | msleep(intel_dp->panel_power_down_delay); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1059 | } |
| 1060 | } |
| 1061 | |
| 1062 | static void ironlake_panel_vdd_work(struct work_struct *__work) |
| 1063 | { |
| 1064 | struct intel_dp *intel_dp = container_of(to_delayed_work(__work), |
| 1065 | struct intel_dp, panel_vdd_work); |
| 1066 | struct drm_device *dev = intel_dp->base.base.dev; |
| 1067 | |
Keith Packard | 627f767 | 2011-10-31 11:30:10 -0700 | [diff] [blame] | 1068 | mutex_lock(&dev->mode_config.mutex); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1069 | ironlake_panel_vdd_off_sync(intel_dp); |
Keith Packard | 627f767 | 2011-10-31 11:30:10 -0700 | [diff] [blame] | 1070 | mutex_unlock(&dev->mode_config.mutex); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1071 | } |
| 1072 | |
| 1073 | static void ironlake_edp_panel_vdd_off(struct intel_dp *intel_dp, bool sync) |
| 1074 | { |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1075 | if (!is_edp(intel_dp)) |
| 1076 | return; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1077 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1078 | DRM_DEBUG_KMS("Turn eDP VDD off %d\n", intel_dp->want_panel_vdd); |
| 1079 | WARN(!intel_dp->want_panel_vdd, "eDP VDD not forced on"); |
Keith Packard | f2e8b18 | 2011-11-01 20:01:35 -0700 | [diff] [blame] | 1080 | |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1081 | intel_dp->want_panel_vdd = false; |
| 1082 | |
| 1083 | if (sync) { |
| 1084 | ironlake_panel_vdd_off_sync(intel_dp); |
| 1085 | } else { |
| 1086 | /* |
| 1087 | * Queue the timer to fire a long |
| 1088 | * time from now (relative to the power down delay) |
| 1089 | * to keep the panel power up across a sequence of operations |
| 1090 | */ |
| 1091 | schedule_delayed_work(&intel_dp->panel_vdd_work, |
| 1092 | msecs_to_jiffies(intel_dp->panel_power_cycle_delay * 5)); |
| 1093 | } |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 1094 | } |
| 1095 | |
Keith Packard | 86a3073 | 2011-10-20 13:40:33 -0700 | [diff] [blame] | 1096 | static void ironlake_edp_panel_on(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1097 | { |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1098 | struct drm_device *dev = intel_dp->base.base.dev; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1099 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1100 | u32 pp; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1101 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1102 | if (!is_edp(intel_dp)) |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 1103 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1104 | |
| 1105 | DRM_DEBUG_KMS("Turn eDP power on\n"); |
| 1106 | |
| 1107 | if (ironlake_edp_have_panel_power(intel_dp)) { |
| 1108 | DRM_DEBUG_KMS("eDP power already on\n"); |
Keith Packard | 7d639f3 | 2011-09-29 16:05:34 -0700 | [diff] [blame] | 1109 | return; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1110 | } |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1111 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1112 | ironlake_wait_panel_power_cycle(intel_dp); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1113 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1114 | pp = ironlake_get_pp_control(dev_priv); |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1115 | if (IS_GEN5(dev)) { |
| 1116 | /* ILK workaround: disable reset around power sequence */ |
| 1117 | pp &= ~PANEL_POWER_RESET; |
| 1118 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1119 | POSTING_READ(PCH_PP_CONTROL); |
| 1120 | } |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1121 | |
Keith Packard | 1c0ae80 | 2011-09-19 13:59:29 -0700 | [diff] [blame] | 1122 | pp |= POWER_TARGET_ON; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1123 | if (!IS_GEN5(dev)) |
| 1124 | pp |= PANEL_POWER_RESET; |
| 1125 | |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1126 | I915_WRITE(PCH_PP_CONTROL, pp); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1127 | POSTING_READ(PCH_PP_CONTROL); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1128 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1129 | ironlake_wait_panel_on(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1130 | |
Keith Packard | 05ce1a4 | 2011-09-29 16:33:01 -0700 | [diff] [blame] | 1131 | if (IS_GEN5(dev)) { |
| 1132 | pp |= PANEL_POWER_RESET; /* restore panel reset bit */ |
| 1133 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1134 | POSTING_READ(PCH_PP_CONTROL); |
| 1135 | } |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1136 | } |
| 1137 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1138 | static void ironlake_edp_panel_off(struct intel_dp *intel_dp) |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1139 | { |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1140 | struct drm_device *dev = intel_dp->base.base.dev; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1141 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1142 | u32 pp; |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1143 | |
Keith Packard | 97af61f57 | 2011-09-28 16:23:51 -0700 | [diff] [blame] | 1144 | if (!is_edp(intel_dp)) |
| 1145 | return; |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1146 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1147 | DRM_DEBUG_KMS("Turn eDP power off\n"); |
Jesse Barnes | 37c6c9b | 2010-08-11 10:04:43 -0700 | [diff] [blame] | 1148 | |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 1149 | WARN(!intel_dp->want_panel_vdd, "Need VDD to turn off panel\n"); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1150 | |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1151 | pp = ironlake_get_pp_control(dev_priv); |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 1152 | /* We need to switch off panel power _and_ force vdd, for otherwise some |
| 1153 | * panels get very unhappy and cease to work. */ |
| 1154 | pp &= ~(POWER_TARGET_ON | EDP_FORCE_VDD | PANEL_POWER_RESET | EDP_BLC_ENABLE); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1155 | I915_WRITE(PCH_PP_CONTROL, pp); |
| 1156 | POSTING_READ(PCH_PP_CONTROL); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1157 | |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 1158 | intel_dp->want_panel_vdd = false; |
| 1159 | |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 1160 | ironlake_wait_panel_off(intel_dp); |
Jesse Barnes | 9934c13 | 2010-07-22 13:18:19 -0700 | [diff] [blame] | 1161 | } |
| 1162 | |
Keith Packard | 86a3073 | 2011-10-20 13:40:33 -0700 | [diff] [blame] | 1163 | static void ironlake_edp_backlight_on(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1164 | { |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1165 | struct drm_device *dev = intel_dp->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1166 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1167 | u32 pp; |
| 1168 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1169 | if (!is_edp(intel_dp)) |
| 1170 | return; |
| 1171 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1172 | DRM_DEBUG_KMS("\n"); |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 1173 | /* |
| 1174 | * If we enable the backlight right away following a panel power |
| 1175 | * on, we may see slight flicker as the panel syncs with the eDP |
| 1176 | * link. So delay a bit to make sure the image is solid before |
| 1177 | * allowing it to appear. |
| 1178 | */ |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1179 | msleep(intel_dp->backlight_on_delay); |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1180 | pp = ironlake_get_pp_control(dev_priv); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1181 | pp |= EDP_BLC_ENABLE; |
| 1182 | I915_WRITE(PCH_PP_CONTROL, pp); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1183 | POSTING_READ(PCH_PP_CONTROL); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1184 | } |
| 1185 | |
Keith Packard | 86a3073 | 2011-10-20 13:40:33 -0700 | [diff] [blame] | 1186 | static void ironlake_edp_backlight_off(struct intel_dp *intel_dp) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1187 | { |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1188 | struct drm_device *dev = intel_dp->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1189 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1190 | u32 pp; |
| 1191 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1192 | if (!is_edp(intel_dp)) |
| 1193 | return; |
| 1194 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1195 | DRM_DEBUG_KMS("\n"); |
Keith Packard | 832dd3c | 2011-11-01 19:34:06 -0700 | [diff] [blame] | 1196 | pp = ironlake_get_pp_control(dev_priv); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1197 | pp &= ~EDP_BLC_ENABLE; |
| 1198 | I915_WRITE(PCH_PP_CONTROL, pp); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 1199 | POSTING_READ(PCH_PP_CONTROL); |
| 1200 | msleep(intel_dp->backlight_off_delay); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1201 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1202 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1203 | static void ironlake_edp_pll_on(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1204 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1205 | struct drm_device *dev = intel_dp->base.base.dev; |
| 1206 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1207 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1208 | u32 dpa_ctl; |
| 1209 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1210 | assert_pipe_disabled(dev_priv, |
| 1211 | to_intel_crtc(crtc)->pipe); |
| 1212 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1213 | DRM_DEBUG_KMS("\n"); |
| 1214 | dpa_ctl = I915_READ(DP_A); |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 1215 | WARN(dpa_ctl & DP_PLL_ENABLE, "dp pll on, should be off\n"); |
| 1216 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
| 1217 | |
| 1218 | /* We don't adjust intel_dp->DP while tearing down the link, to |
| 1219 | * facilitate link retraining (e.g. after hotplug). Hence clear all |
| 1220 | * enable bits here to ensure that we don't enable too much. */ |
| 1221 | intel_dp->DP &= ~(DP_PORT_EN | DP_AUDIO_OUTPUT_ENABLE); |
| 1222 | intel_dp->DP |= DP_PLL_ENABLE; |
| 1223 | I915_WRITE(DP_A, intel_dp->DP); |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1224 | POSTING_READ(DP_A); |
| 1225 | udelay(200); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1226 | } |
| 1227 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1228 | static void ironlake_edp_pll_off(struct intel_dp *intel_dp) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1229 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1230 | struct drm_device *dev = intel_dp->base.base.dev; |
| 1231 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1232 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1233 | u32 dpa_ctl; |
| 1234 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1235 | assert_pipe_disabled(dev_priv, |
| 1236 | to_intel_crtc(crtc)->pipe); |
| 1237 | |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1238 | dpa_ctl = I915_READ(DP_A); |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 1239 | WARN((dpa_ctl & DP_PLL_ENABLE) == 0, |
| 1240 | "dp pll off, should be on\n"); |
| 1241 | WARN(dpa_ctl & DP_PORT_EN, "dp port still on, should be off\n"); |
| 1242 | |
| 1243 | /* We can't rely on the value tracked for the DP register in |
| 1244 | * intel_dp->DP because link_down must not change that (otherwise link |
| 1245 | * re-training will fail. */ |
Jesse Barnes | 298b0b3 | 2010-10-07 16:01:24 -0700 | [diff] [blame] | 1246 | dpa_ctl &= ~DP_PLL_ENABLE; |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1247 | I915_WRITE(DP_A, dpa_ctl); |
Chris Wilson | 1af5fa1 | 2010-09-08 21:07:28 +0100 | [diff] [blame] | 1248 | POSTING_READ(DP_A); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1249 | udelay(200); |
| 1250 | } |
| 1251 | |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1252 | /* If the sink supports it, try to set the power state appropriately */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1253 | void intel_dp_sink_dpms(struct intel_dp *intel_dp, int mode) |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1254 | { |
| 1255 | int ret, i; |
| 1256 | |
| 1257 | /* Should have a valid DPCD by this point */ |
| 1258 | if (intel_dp->dpcd[DP_DPCD_REV] < 0x11) |
| 1259 | return; |
| 1260 | |
| 1261 | if (mode != DRM_MODE_DPMS_ON) { |
| 1262 | ret = intel_dp_aux_native_write_1(intel_dp, DP_SET_POWER, |
| 1263 | DP_SET_POWER_D3); |
| 1264 | if (ret != 1) |
| 1265 | DRM_DEBUG_DRIVER("failed to write sink power state\n"); |
| 1266 | } else { |
| 1267 | /* |
| 1268 | * When turning on, we need to retry for 1ms to give the sink |
| 1269 | * time to wake up. |
| 1270 | */ |
| 1271 | for (i = 0; i < 3; i++) { |
| 1272 | ret = intel_dp_aux_native_write_1(intel_dp, |
| 1273 | DP_SET_POWER, |
| 1274 | DP_SET_POWER_D0); |
| 1275 | if (ret == 1) |
| 1276 | break; |
| 1277 | msleep(1); |
| 1278 | } |
| 1279 | } |
| 1280 | } |
| 1281 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1282 | static bool intel_dp_get_hw_state(struct intel_encoder *encoder, |
| 1283 | enum pipe *pipe) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1284 | { |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1285 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1286 | struct drm_device *dev = encoder->base.dev; |
| 1287 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1288 | u32 tmp = I915_READ(intel_dp->output_reg); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1289 | |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 1290 | if (!(tmp & DP_PORT_EN)) |
| 1291 | return false; |
| 1292 | |
| 1293 | if (is_cpu_edp(intel_dp) && IS_GEN7(dev)) { |
| 1294 | *pipe = PORT_TO_PIPE_CPT(tmp); |
| 1295 | } else if (!HAS_PCH_CPT(dev) || is_cpu_edp(intel_dp)) { |
| 1296 | *pipe = PORT_TO_PIPE(tmp); |
| 1297 | } else { |
| 1298 | u32 trans_sel; |
| 1299 | u32 trans_dp; |
| 1300 | int i; |
| 1301 | |
| 1302 | switch (intel_dp->output_reg) { |
| 1303 | case PCH_DP_B: |
| 1304 | trans_sel = TRANS_DP_PORT_SEL_B; |
| 1305 | break; |
| 1306 | case PCH_DP_C: |
| 1307 | trans_sel = TRANS_DP_PORT_SEL_C; |
| 1308 | break; |
| 1309 | case PCH_DP_D: |
| 1310 | trans_sel = TRANS_DP_PORT_SEL_D; |
| 1311 | break; |
| 1312 | default: |
| 1313 | return true; |
| 1314 | } |
| 1315 | |
| 1316 | for_each_pipe(i) { |
| 1317 | trans_dp = I915_READ(TRANS_DP_CTL(i)); |
| 1318 | if ((trans_dp & TRANS_DP_PORT_SEL_MASK) == trans_sel) { |
| 1319 | *pipe = i; |
| 1320 | return true; |
| 1321 | } |
| 1322 | } |
| 1323 | } |
| 1324 | |
| 1325 | DRM_DEBUG_KMS("No pipe for dp port 0x%x found\n", intel_dp->output_reg); |
| 1326 | |
| 1327 | return true; |
| 1328 | } |
| 1329 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1330 | static void intel_disable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1331 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1332 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Daniel Vetter | 6cb4983 | 2012-05-20 17:14:50 +0200 | [diff] [blame] | 1333 | |
| 1334 | /* Make sure the panel is off before trying to change the mode. But also |
| 1335 | * ensure that we have vdd while we switch off the panel. */ |
| 1336 | ironlake_edp_panel_vdd_on(intel_dp); |
Keith Packard | 21264c6 | 2011-11-01 20:25:21 -0700 | [diff] [blame] | 1337 | ironlake_edp_backlight_off(intel_dp); |
Jesse Barnes | c7ad381 | 2011-07-07 11:11:03 -0700 | [diff] [blame] | 1338 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
Daniel Vetter | 35a3855 | 2012-08-12 22:17:14 +0200 | [diff] [blame] | 1339 | ironlake_edp_panel_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1340 | |
| 1341 | /* cpu edp my only be disable _after_ the cpu pipe/plane is disabled. */ |
| 1342 | if (!is_cpu_edp(intel_dp)) |
| 1343 | intel_dp_link_down(intel_dp); |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1344 | } |
| 1345 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1346 | static void intel_post_disable_dp(struct intel_encoder *encoder) |
| 1347 | { |
| 1348 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1349 | |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1350 | if (is_cpu_edp(intel_dp)) { |
| 1351 | intel_dp_link_down(intel_dp); |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1352 | ironlake_edp_pll_off(intel_dp); |
Daniel Vetter | 3739850 | 2012-09-06 22:15:44 +0200 | [diff] [blame] | 1353 | } |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1354 | } |
| 1355 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1356 | static void intel_enable_dp(struct intel_encoder *encoder) |
Jesse Barnes | d240f20 | 2010-08-13 15:43:26 -0700 | [diff] [blame] | 1357 | { |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1358 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
| 1359 | struct drm_device *dev = encoder->base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1360 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1361 | uint32_t dp_reg = I915_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1362 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 1363 | if (WARN_ON(dp_reg & DP_PORT_EN)) |
| 1364 | return; |
| 1365 | |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1366 | ironlake_edp_panel_vdd_on(intel_dp); |
| 1367 | intel_dp_sink_dpms(intel_dp, DRM_MODE_DPMS_ON); |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 1368 | intel_dp_start_link_train(intel_dp); |
| 1369 | ironlake_edp_panel_on(intel_dp); |
| 1370 | ironlake_edp_panel_vdd_off(intel_dp, true); |
| 1371 | intel_dp_complete_link_train(intel_dp); |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1372 | ironlake_edp_backlight_on(intel_dp); |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1373 | } |
| 1374 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1375 | static void intel_pre_enable_dp(struct intel_encoder *encoder) |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1376 | { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1377 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 1378 | |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 1379 | if (is_cpu_edp(intel_dp)) |
| 1380 | ironlake_edp_pll_on(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1381 | } |
| 1382 | |
| 1383 | /* |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1384 | * Native read with retry for link status and receiver capability reads for |
| 1385 | * cases where the sink may still be asleep. |
| 1386 | */ |
| 1387 | static bool |
| 1388 | intel_dp_aux_native_read_retry(struct intel_dp *intel_dp, uint16_t address, |
| 1389 | uint8_t *recv, int recv_bytes) |
| 1390 | { |
| 1391 | int ret, i; |
| 1392 | |
| 1393 | /* |
| 1394 | * Sinks are *supposed* to come up within 1ms from an off state, |
| 1395 | * but we're also supposed to retry 3 times per the spec. |
| 1396 | */ |
| 1397 | for (i = 0; i < 3; i++) { |
| 1398 | ret = intel_dp_aux_native_read(intel_dp, address, recv, |
| 1399 | recv_bytes); |
| 1400 | if (ret == recv_bytes) |
| 1401 | return true; |
| 1402 | msleep(1); |
| 1403 | } |
| 1404 | |
| 1405 | return false; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1406 | } |
| 1407 | |
| 1408 | /* |
| 1409 | * Fetch AUX CH registers 0x202 - 0x207 which contain |
| 1410 | * link status information |
| 1411 | */ |
| 1412 | static bool |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1413 | intel_dp_get_link_status(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1414 | { |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1415 | return intel_dp_aux_native_read_retry(intel_dp, |
| 1416 | DP_LANE0_1_STATUS, |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1417 | link_status, |
Jesse Barnes | df0c237 | 2011-07-07 11:11:02 -0700 | [diff] [blame] | 1418 | DP_LINK_STATUS_SIZE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1419 | } |
| 1420 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1421 | #if 0 |
| 1422 | static char *voltage_names[] = { |
| 1423 | "0.4V", "0.6V", "0.8V", "1.2V" |
| 1424 | }; |
| 1425 | static char *pre_emph_names[] = { |
| 1426 | "0dB", "3.5dB", "6dB", "9.5dB" |
| 1427 | }; |
| 1428 | static char *link_train_names[] = { |
| 1429 | "pattern 1", "pattern 2", "idle", "off" |
| 1430 | }; |
| 1431 | #endif |
| 1432 | |
| 1433 | /* |
| 1434 | * These are source-specific values; current Intel hardware supports |
| 1435 | * a maximum voltage of 800mV and a maximum pre-emphasis of 6dB |
| 1436 | */ |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1437 | |
| 1438 | static uint8_t |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1439 | intel_dp_voltage_max(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1440 | { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1441 | struct drm_device *dev = intel_dp->base.base.dev; |
| 1442 | |
| 1443 | if (IS_GEN7(dev) && is_cpu_edp(intel_dp)) |
| 1444 | return DP_TRAIN_VOLTAGE_SWING_800; |
| 1445 | else if (HAS_PCH_CPT(dev) && !is_cpu_edp(intel_dp)) |
| 1446 | return DP_TRAIN_VOLTAGE_SWING_1200; |
| 1447 | else |
| 1448 | return DP_TRAIN_VOLTAGE_SWING_800; |
| 1449 | } |
| 1450 | |
| 1451 | static uint8_t |
| 1452 | intel_dp_pre_emphasis_max(struct intel_dp *intel_dp, uint8_t voltage_swing) |
| 1453 | { |
| 1454 | struct drm_device *dev = intel_dp->base.base.dev; |
| 1455 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1456 | if (IS_HASWELL(dev)) { |
| 1457 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1458 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1459 | return DP_TRAIN_PRE_EMPHASIS_9_5; |
| 1460 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1461 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1462 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1463 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 1464 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1465 | default: |
| 1466 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 1467 | } |
| 1468 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1469 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1470 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1471 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1472 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1473 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1474 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 1475 | default: |
| 1476 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 1477 | } |
| 1478 | } else { |
| 1479 | switch (voltage_swing & DP_TRAIN_VOLTAGE_SWING_MASK) { |
| 1480 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1481 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1482 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1483 | return DP_TRAIN_PRE_EMPHASIS_6; |
| 1484 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1485 | return DP_TRAIN_PRE_EMPHASIS_3_5; |
| 1486 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1487 | default: |
| 1488 | return DP_TRAIN_PRE_EMPHASIS_0; |
| 1489 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1490 | } |
| 1491 | } |
| 1492 | |
| 1493 | static void |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1494 | intel_get_adjust_train(struct intel_dp *intel_dp, uint8_t link_status[DP_LINK_STATUS_SIZE]) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1495 | { |
| 1496 | uint8_t v = 0; |
| 1497 | uint8_t p = 0; |
| 1498 | int lane; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1499 | uint8_t voltage_max; |
| 1500 | uint8_t preemph_max; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1501 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1502 | for (lane = 0; lane < intel_dp->lane_count; lane++) { |
Daniel Vetter | 0f037bd | 2012-10-18 10:15:27 +0200 | [diff] [blame] | 1503 | uint8_t this_v = drm_dp_get_adjust_request_voltage(link_status, lane); |
| 1504 | uint8_t this_p = drm_dp_get_adjust_request_pre_emphasis(link_status, lane); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1505 | |
| 1506 | if (this_v > v) |
| 1507 | v = this_v; |
| 1508 | if (this_p > p) |
| 1509 | p = this_p; |
| 1510 | } |
| 1511 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1512 | voltage_max = intel_dp_voltage_max(intel_dp); |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1513 | if (v >= voltage_max) |
| 1514 | v = voltage_max | DP_TRAIN_MAX_SWING_REACHED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1515 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1516 | preemph_max = intel_dp_pre_emphasis_max(intel_dp, v); |
| 1517 | if (p >= preemph_max) |
| 1518 | p = preemph_max | DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1519 | |
| 1520 | for (lane = 0; lane < 4; lane++) |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1521 | intel_dp->train_set[lane] = v | p; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1522 | } |
| 1523 | |
| 1524 | static uint32_t |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1525 | intel_dp_signal_levels(uint8_t train_set) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1526 | { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1527 | uint32_t signal_levels = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1528 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1529 | switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1530 | case DP_TRAIN_VOLTAGE_SWING_400: |
| 1531 | default: |
| 1532 | signal_levels |= DP_VOLTAGE_0_4; |
| 1533 | break; |
| 1534 | case DP_TRAIN_VOLTAGE_SWING_600: |
| 1535 | signal_levels |= DP_VOLTAGE_0_6; |
| 1536 | break; |
| 1537 | case DP_TRAIN_VOLTAGE_SWING_800: |
| 1538 | signal_levels |= DP_VOLTAGE_0_8; |
| 1539 | break; |
| 1540 | case DP_TRAIN_VOLTAGE_SWING_1200: |
| 1541 | signal_levels |= DP_VOLTAGE_1_2; |
| 1542 | break; |
| 1543 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1544 | switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1545 | case DP_TRAIN_PRE_EMPHASIS_0: |
| 1546 | default: |
| 1547 | signal_levels |= DP_PRE_EMPHASIS_0; |
| 1548 | break; |
| 1549 | case DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1550 | signal_levels |= DP_PRE_EMPHASIS_3_5; |
| 1551 | break; |
| 1552 | case DP_TRAIN_PRE_EMPHASIS_6: |
| 1553 | signal_levels |= DP_PRE_EMPHASIS_6; |
| 1554 | break; |
| 1555 | case DP_TRAIN_PRE_EMPHASIS_9_5: |
| 1556 | signal_levels |= DP_PRE_EMPHASIS_9_5; |
| 1557 | break; |
| 1558 | } |
| 1559 | return signal_levels; |
| 1560 | } |
| 1561 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1562 | /* Gen6's DP voltage swing and pre-emphasis control */ |
| 1563 | static uint32_t |
| 1564 | intel_gen6_edp_signal_levels(uint8_t train_set) |
| 1565 | { |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1566 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 1567 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 1568 | switch (signal_levels) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1569 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1570 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1571 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
| 1572 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1573 | return EDP_LINK_TRAIN_400MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1574 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1575 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 1576 | return EDP_LINK_TRAIN_400_600MV_6DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1577 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1578 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1579 | return EDP_LINK_TRAIN_600_800MV_3_5DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1580 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1581 | case DP_TRAIN_VOLTAGE_SWING_1200 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1582 | return EDP_LINK_TRAIN_800_1200MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1583 | default: |
Yuanhan Liu | 3c5a62b | 2011-01-06 18:26:08 +0800 | [diff] [blame] | 1584 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 1585 | "0x%x\n", signal_levels); |
| 1586 | return EDP_LINK_TRAIN_400_600MV_0DB_SNB_B; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1587 | } |
| 1588 | } |
| 1589 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1590 | /* Gen7's DP voltage swing and pre-emphasis control */ |
| 1591 | static uint32_t |
| 1592 | intel_gen7_edp_signal_levels(uint8_t train_set) |
| 1593 | { |
| 1594 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 1595 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 1596 | switch (signal_levels) { |
| 1597 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1598 | return EDP_LINK_TRAIN_400MV_0DB_IVB; |
| 1599 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1600 | return EDP_LINK_TRAIN_400MV_3_5DB_IVB; |
| 1601 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
| 1602 | return EDP_LINK_TRAIN_400MV_6DB_IVB; |
| 1603 | |
| 1604 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1605 | return EDP_LINK_TRAIN_600MV_0DB_IVB; |
| 1606 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1607 | return EDP_LINK_TRAIN_600MV_3_5DB_IVB; |
| 1608 | |
| 1609 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1610 | return EDP_LINK_TRAIN_800MV_0DB_IVB; |
| 1611 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1612 | return EDP_LINK_TRAIN_800MV_3_5DB_IVB; |
| 1613 | |
| 1614 | default: |
| 1615 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 1616 | "0x%x\n", signal_levels); |
| 1617 | return EDP_LINK_TRAIN_500MV_0DB_IVB; |
| 1618 | } |
| 1619 | } |
| 1620 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1621 | /* Gen7.5's (HSW) DP voltage swing and pre-emphasis control */ |
| 1622 | static uint32_t |
| 1623 | intel_dp_signal_levels_hsw(uint8_t train_set) |
| 1624 | { |
| 1625 | int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | |
| 1626 | DP_TRAIN_PRE_EMPHASIS_MASK); |
| 1627 | switch (signal_levels) { |
| 1628 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1629 | return DDI_BUF_EMP_400MV_0DB_HSW; |
| 1630 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1631 | return DDI_BUF_EMP_400MV_3_5DB_HSW; |
| 1632 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_6: |
| 1633 | return DDI_BUF_EMP_400MV_6DB_HSW; |
| 1634 | case DP_TRAIN_VOLTAGE_SWING_400 | DP_TRAIN_PRE_EMPHASIS_9_5: |
| 1635 | return DDI_BUF_EMP_400MV_9_5DB_HSW; |
| 1636 | |
| 1637 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1638 | return DDI_BUF_EMP_600MV_0DB_HSW; |
| 1639 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1640 | return DDI_BUF_EMP_600MV_3_5DB_HSW; |
| 1641 | case DP_TRAIN_VOLTAGE_SWING_600 | DP_TRAIN_PRE_EMPHASIS_6: |
| 1642 | return DDI_BUF_EMP_600MV_6DB_HSW; |
| 1643 | |
| 1644 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_0: |
| 1645 | return DDI_BUF_EMP_800MV_0DB_HSW; |
| 1646 | case DP_TRAIN_VOLTAGE_SWING_800 | DP_TRAIN_PRE_EMPHASIS_3_5: |
| 1647 | return DDI_BUF_EMP_800MV_3_5DB_HSW; |
| 1648 | default: |
| 1649 | DRM_DEBUG_KMS("Unsupported voltage swing/pre-emphasis level:" |
| 1650 | "0x%x\n", signal_levels); |
| 1651 | return DDI_BUF_EMP_400MV_0DB_HSW; |
| 1652 | } |
| 1653 | } |
| 1654 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1655 | static bool |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1656 | intel_dp_set_link_train(struct intel_dp *intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1657 | uint32_t dp_reg_value, |
Chris Wilson | 58e10eb | 2010-10-03 10:56:11 +0100 | [diff] [blame] | 1658 | uint8_t dp_train_pat) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1659 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1660 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1661 | struct drm_i915_private *dev_priv = dev->dev_private; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1662 | int ret; |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1663 | uint32_t temp; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1664 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1665 | if (IS_HASWELL(dev)) { |
| 1666 | temp = I915_READ(DP_TP_CTL(intel_dp->port)); |
| 1667 | |
| 1668 | if (dp_train_pat & DP_LINK_SCRAMBLING_DISABLE) |
| 1669 | temp |= DP_TP_CTL_SCRAMBLE_DISABLE; |
| 1670 | else |
| 1671 | temp &= ~DP_TP_CTL_SCRAMBLE_DISABLE; |
| 1672 | |
| 1673 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 1674 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 1675 | case DP_TRAINING_PATTERN_DISABLE: |
| 1676 | temp |= DP_TP_CTL_LINK_TRAIN_IDLE; |
| 1677 | I915_WRITE(DP_TP_CTL(intel_dp->port), temp); |
| 1678 | |
| 1679 | if (wait_for((I915_READ(DP_TP_STATUS(intel_dp->port)) & |
| 1680 | DP_TP_STATUS_IDLE_DONE), 1)) |
| 1681 | DRM_ERROR("Timed out waiting for DP idle patterns\n"); |
| 1682 | |
| 1683 | temp &= ~DP_TP_CTL_LINK_TRAIN_MASK; |
| 1684 | temp |= DP_TP_CTL_LINK_TRAIN_NORMAL; |
| 1685 | |
| 1686 | break; |
| 1687 | case DP_TRAINING_PATTERN_1: |
| 1688 | temp |= DP_TP_CTL_LINK_TRAIN_PAT1; |
| 1689 | break; |
| 1690 | case DP_TRAINING_PATTERN_2: |
| 1691 | temp |= DP_TP_CTL_LINK_TRAIN_PAT2; |
| 1692 | break; |
| 1693 | case DP_TRAINING_PATTERN_3: |
| 1694 | temp |= DP_TP_CTL_LINK_TRAIN_PAT3; |
| 1695 | break; |
| 1696 | } |
| 1697 | I915_WRITE(DP_TP_CTL(intel_dp->port), temp); |
| 1698 | |
| 1699 | } else if (HAS_PCH_CPT(dev) && |
| 1700 | (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 1701 | dp_reg_value &= ~DP_LINK_TRAIN_MASK_CPT; |
| 1702 | |
| 1703 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 1704 | case DP_TRAINING_PATTERN_DISABLE: |
| 1705 | dp_reg_value |= DP_LINK_TRAIN_OFF_CPT; |
| 1706 | break; |
| 1707 | case DP_TRAINING_PATTERN_1: |
| 1708 | dp_reg_value |= DP_LINK_TRAIN_PAT_1_CPT; |
| 1709 | break; |
| 1710 | case DP_TRAINING_PATTERN_2: |
| 1711 | dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; |
| 1712 | break; |
| 1713 | case DP_TRAINING_PATTERN_3: |
| 1714 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 1715 | dp_reg_value |= DP_LINK_TRAIN_PAT_2_CPT; |
| 1716 | break; |
| 1717 | } |
| 1718 | |
| 1719 | } else { |
| 1720 | dp_reg_value &= ~DP_LINK_TRAIN_MASK; |
| 1721 | |
| 1722 | switch (dp_train_pat & DP_TRAINING_PATTERN_MASK) { |
| 1723 | case DP_TRAINING_PATTERN_DISABLE: |
| 1724 | dp_reg_value |= DP_LINK_TRAIN_OFF; |
| 1725 | break; |
| 1726 | case DP_TRAINING_PATTERN_1: |
| 1727 | dp_reg_value |= DP_LINK_TRAIN_PAT_1; |
| 1728 | break; |
| 1729 | case DP_TRAINING_PATTERN_2: |
| 1730 | dp_reg_value |= DP_LINK_TRAIN_PAT_2; |
| 1731 | break; |
| 1732 | case DP_TRAINING_PATTERN_3: |
| 1733 | DRM_ERROR("DP training pattern 3 not supported\n"); |
| 1734 | dp_reg_value |= DP_LINK_TRAIN_PAT_2; |
| 1735 | break; |
| 1736 | } |
| 1737 | } |
| 1738 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1739 | I915_WRITE(intel_dp->output_reg, dp_reg_value); |
| 1740 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1741 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1742 | intel_dp_aux_native_write_1(intel_dp, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1743 | DP_TRAINING_PATTERN_SET, |
| 1744 | dp_train_pat); |
| 1745 | |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 1746 | if ((dp_train_pat & DP_TRAINING_PATTERN_MASK) != |
| 1747 | DP_TRAINING_PATTERN_DISABLE) { |
| 1748 | ret = intel_dp_aux_native_write(intel_dp, |
| 1749 | DP_TRAINING_LANE0_SET, |
| 1750 | intel_dp->train_set, |
| 1751 | intel_dp->lane_count); |
| 1752 | if (ret != intel_dp->lane_count) |
| 1753 | return false; |
| 1754 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1755 | |
| 1756 | return true; |
| 1757 | } |
| 1758 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1759 | /* Enable corresponding port and start training pattern 1 */ |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1760 | void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1761 | intel_dp_start_link_train(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1762 | { |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1763 | struct drm_encoder *encoder = &intel_dp->base.base; |
| 1764 | struct drm_device *dev = encoder->dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1765 | int i; |
| 1766 | uint8_t voltage; |
| 1767 | bool clock_recovery = false; |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 1768 | int voltage_tries, loop_tries; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1769 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1770 | |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1771 | if (IS_HASWELL(dev)) |
| 1772 | intel_ddi_prepare_link_retrain(encoder); |
| 1773 | |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1774 | /* Write the link configuration data */ |
| 1775 | intel_dp_aux_native_write(intel_dp, DP_LINK_BW_SET, |
| 1776 | intel_dp->link_configuration, |
| 1777 | DP_LINK_CONFIGURATION_SIZE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1778 | |
| 1779 | DP |= DP_PORT_EN; |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1780 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1781 | memset(intel_dp->train_set, 0, 4); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1782 | voltage = 0xff; |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 1783 | voltage_tries = 0; |
| 1784 | loop_tries = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1785 | clock_recovery = false; |
| 1786 | for (;;) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1787 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1788 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1789 | uint32_t signal_levels; |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 1790 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1791 | if (IS_HASWELL(dev)) { |
| 1792 | signal_levels = intel_dp_signal_levels_hsw( |
| 1793 | intel_dp->train_set[0]); |
| 1794 | DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; |
| 1795 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1796 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); |
| 1797 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; |
| 1798 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1799 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1800 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
| 1801 | } else { |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1802 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1803 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
| 1804 | } |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1805 | DRM_DEBUG_KMS("training pattern 1 signal levels %08x\n", |
| 1806 | signal_levels); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1807 | |
Daniel Vetter | a7c9655 | 2012-10-18 10:15:30 +0200 | [diff] [blame] | 1808 | /* Set training pattern 1 */ |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 1809 | if (!intel_dp_set_link_train(intel_dp, DP, |
Adam Jackson | 8105585 | 2011-07-21 17:48:37 -0400 | [diff] [blame] | 1810 | DP_TRAINING_PATTERN_1 | |
| 1811 | DP_LINK_SCRAMBLING_DISABLE)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1812 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1813 | |
Daniel Vetter | a7c9655 | 2012-10-18 10:15:30 +0200 | [diff] [blame] | 1814 | drm_dp_link_train_clock_recovery_delay(intel_dp->dpcd); |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1815 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
| 1816 | DRM_ERROR("failed to get link status\n"); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1817 | break; |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1818 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1819 | |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 1820 | if (drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1821 | DRM_DEBUG_KMS("clock recovery OK\n"); |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1822 | clock_recovery = true; |
| 1823 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1824 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1825 | |
| 1826 | /* Check to see if we've tried the max voltage */ |
| 1827 | for (i = 0; i < intel_dp->lane_count; i++) |
| 1828 | if ((intel_dp->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) |
| 1829 | break; |
Paulo Zanoni | 0d71068 | 2012-06-29 16:03:34 -0300 | [diff] [blame] | 1830 | if (i == intel_dp->lane_count && voltage_tries == 5) { |
Chris Wilson | 2477367 | 2012-09-26 16:48:30 +0100 | [diff] [blame] | 1831 | if (++loop_tries == 5) { |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 1832 | DRM_DEBUG_KMS("too many full retries, give up\n"); |
| 1833 | break; |
| 1834 | } |
| 1835 | memset(intel_dp->train_set, 0, 4); |
| 1836 | voltage_tries = 0; |
| 1837 | continue; |
| 1838 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1839 | |
| 1840 | /* Check to see if we've tried the same voltage 5 times */ |
Chris Wilson | 2477367 | 2012-09-26 16:48:30 +0100 | [diff] [blame] | 1841 | if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) != voltage) { |
| 1842 | voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; |
Keith Packard | cdb0e95 | 2011-11-01 20:00:06 -0700 | [diff] [blame] | 1843 | voltage_tries = 0; |
Chris Wilson | 2477367 | 2012-09-26 16:48:30 +0100 | [diff] [blame] | 1844 | } else |
| 1845 | ++voltage_tries; |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1846 | |
| 1847 | /* Compute new intel_dp->train_set as requested by target */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1848 | intel_get_adjust_train(intel_dp, link_status); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1849 | } |
| 1850 | |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1851 | intel_dp->DP = DP; |
| 1852 | } |
| 1853 | |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1854 | void |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1855 | intel_dp_complete_link_train(struct intel_dp *intel_dp) |
| 1856 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1857 | struct drm_device *dev = intel_dp->base.base.dev; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1858 | bool channel_eq = false; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1859 | int tries, cr_tries; |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1860 | uint32_t DP = intel_dp->DP; |
| 1861 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1862 | /* channel equalization */ |
| 1863 | tries = 0; |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1864 | cr_tries = 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1865 | channel_eq = false; |
| 1866 | for (;;) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1867 | /* Use intel_dp->train_set[0] to set the voltage and pre emphasis values */ |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1868 | uint32_t signal_levels; |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1869 | uint8_t link_status[DP_LINK_STATUS_SIZE]; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1870 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1871 | if (cr_tries > 5) { |
| 1872 | DRM_ERROR("failed to train DP, aborting\n"); |
| 1873 | intel_dp_link_down(intel_dp); |
| 1874 | break; |
| 1875 | } |
| 1876 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1877 | if (IS_HASWELL(dev)) { |
| 1878 | signal_levels = intel_dp_signal_levels_hsw(intel_dp->train_set[0]); |
| 1879 | DP = (DP & ~DDI_BUF_EMP_MASK) | signal_levels; |
| 1880 | } else if (IS_GEN7(dev) && is_cpu_edp(intel_dp) && !IS_VALLEYVIEW(dev)) { |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1881 | signal_levels = intel_gen7_edp_signal_levels(intel_dp->train_set[0]); |
| 1882 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_IVB) | signal_levels; |
| 1883 | } else if (IS_GEN6(dev) && is_cpu_edp(intel_dp)) { |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 1884 | signal_levels = intel_gen6_edp_signal_levels(intel_dp->train_set[0]); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1885 | DP = (DP & ~EDP_LINK_TRAIN_VOL_EMP_MASK_SNB) | signal_levels; |
| 1886 | } else { |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1887 | signal_levels = intel_dp_signal_levels(intel_dp->train_set[0]); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1888 | DP = (DP & ~(DP_VOLTAGE_MASK|DP_PRE_EMPHASIS_MASK)) | signal_levels; |
| 1889 | } |
| 1890 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1891 | /* channel eq pattern */ |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 1892 | if (!intel_dp_set_link_train(intel_dp, DP, |
Adam Jackson | 8105585 | 2011-07-21 17:48:37 -0400 | [diff] [blame] | 1893 | DP_TRAINING_PATTERN_2 | |
| 1894 | DP_LINK_SCRAMBLING_DISABLE)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1895 | break; |
| 1896 | |
Daniel Vetter | a7c9655 | 2012-10-18 10:15:30 +0200 | [diff] [blame] | 1897 | drm_dp_link_train_channel_eq_delay(intel_dp->dpcd); |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1898 | if (!intel_dp_get_link_status(intel_dp, link_status)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1899 | break; |
Jesse Barnes | 869184a | 2010-10-07 16:01:22 -0700 | [diff] [blame] | 1900 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1901 | /* Make sure clock is still ok */ |
Daniel Vetter | 0191627 | 2012-10-18 10:15:25 +0200 | [diff] [blame] | 1902 | if (!drm_dp_clock_recovery_ok(link_status, intel_dp->lane_count)) { |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1903 | intel_dp_start_link_train(intel_dp); |
| 1904 | cr_tries++; |
| 1905 | continue; |
| 1906 | } |
| 1907 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 1908 | if (drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1909 | channel_eq = true; |
| 1910 | break; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1911 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1912 | |
Jesse Barnes | 37f8097 | 2011-01-05 14:45:24 -0800 | [diff] [blame] | 1913 | /* Try 5 times, then try clock recovery if that fails */ |
| 1914 | if (tries > 5) { |
| 1915 | intel_dp_link_down(intel_dp); |
| 1916 | intel_dp_start_link_train(intel_dp); |
| 1917 | tries = 0; |
| 1918 | cr_tries++; |
| 1919 | continue; |
| 1920 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1921 | |
| 1922 | /* Compute new intel_dp->train_set as requested by target */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 1923 | intel_get_adjust_train(intel_dp, link_status); |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1924 | ++tries; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1925 | } |
Chris Wilson | 3cf2efb | 2010-11-29 10:09:55 +0000 | [diff] [blame] | 1926 | |
Paulo Zanoni | d6c0d72 | 2012-10-15 15:51:34 -0300 | [diff] [blame] | 1927 | if (channel_eq) |
| 1928 | DRM_DEBUG_KMS("Channel EQ done. DP Training successfull\n"); |
| 1929 | |
Paulo Zanoni | 47ea754 | 2012-07-17 16:55:16 -0300 | [diff] [blame] | 1930 | intel_dp_set_link_train(intel_dp, DP, DP_TRAINING_PATTERN_DISABLE); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1931 | } |
| 1932 | |
| 1933 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1934 | intel_dp_link_down(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1935 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 1936 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1937 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1938 | uint32_t DP = intel_dp->DP; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 1939 | |
Paulo Zanoni | c19b066 | 2012-10-15 15:51:41 -0300 | [diff] [blame] | 1940 | /* |
| 1941 | * DDI code has a strict mode set sequence and we should try to respect |
| 1942 | * it, otherwise we might hang the machine in many different ways. So we |
| 1943 | * really should be disabling the port only on a complete crtc_disable |
| 1944 | * sequence. This function is just called under two conditions on DDI |
| 1945 | * code: |
| 1946 | * - Link train failed while doing crtc_enable, and on this case we |
| 1947 | * really should respect the mode set sequence and wait for a |
| 1948 | * crtc_disable. |
| 1949 | * - Someone turned the monitor off and intel_dp_check_link_status |
| 1950 | * called us. We don't need to disable the whole port on this case, so |
| 1951 | * when someone turns the monitor on again, |
| 1952 | * intel_ddi_prepare_link_retrain will take care of redoing the link |
| 1953 | * train. |
| 1954 | */ |
| 1955 | if (IS_HASWELL(dev)) |
| 1956 | return; |
| 1957 | |
Daniel Vetter | 0c33d8d | 2012-09-06 22:15:43 +0200 | [diff] [blame] | 1958 | if (WARN_ON((I915_READ(intel_dp->output_reg) & DP_PORT_EN) == 0)) |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 1959 | return; |
| 1960 | |
Zhao Yakui | 28c9773 | 2009-10-09 11:39:41 +0800 | [diff] [blame] | 1961 | DRM_DEBUG_KMS("\n"); |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 1962 | |
Keith Packard | 1a2eb46 | 2011-11-16 16:26:07 -0800 | [diff] [blame] | 1963 | if (HAS_PCH_CPT(dev) && (IS_GEN7(dev) || !is_cpu_edp(intel_dp))) { |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1964 | DP &= ~DP_LINK_TRAIN_MASK_CPT; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1965 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE_CPT); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1966 | } else { |
| 1967 | DP &= ~DP_LINK_TRAIN_MASK; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 1968 | I915_WRITE(intel_dp->output_reg, DP | DP_LINK_TRAIN_PAT_IDLE); |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 1969 | } |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 1970 | POSTING_READ(intel_dp->output_reg); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1971 | |
Chris Wilson | fe255d0 | 2010-09-11 21:37:48 +0100 | [diff] [blame] | 1972 | msleep(17); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 1973 | |
Daniel Vetter | 493a708 | 2012-05-30 12:31:56 +0200 | [diff] [blame] | 1974 | if (HAS_PCH_IBX(dev) && |
Chris Wilson | 1b39d6f | 2010-12-06 11:20:45 +0000 | [diff] [blame] | 1975 | I915_READ(intel_dp->output_reg) & DP_PIPEB_SELECT) { |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 1976 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
| 1977 | |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 1978 | /* Hardware workaround: leaving our transcoder select |
| 1979 | * set to transcoder B while it's off will prevent the |
| 1980 | * corresponding HDMI output on transcoder A. |
| 1981 | * |
| 1982 | * Combine this with another hardware workaround: |
| 1983 | * transcoder select bit can only be cleared while the |
| 1984 | * port is enabled. |
| 1985 | */ |
| 1986 | DP &= ~DP_PIPEB_SELECT; |
| 1987 | I915_WRITE(intel_dp->output_reg, DP); |
| 1988 | |
| 1989 | /* Changes to enable or select take place the vblank |
| 1990 | * after being written. |
| 1991 | */ |
Chris Wilson | 31acbcc | 2011-04-17 06:38:35 +0100 | [diff] [blame] | 1992 | if (crtc == NULL) { |
| 1993 | /* We can arrive here never having been attached |
| 1994 | * to a CRTC, for instance, due to inheriting |
| 1995 | * random state from the BIOS. |
| 1996 | * |
| 1997 | * If the pipe is not running, play safe and |
| 1998 | * wait for the clocks to stabilise before |
| 1999 | * continuing. |
| 2000 | */ |
| 2001 | POSTING_READ(intel_dp->output_reg); |
| 2002 | msleep(50); |
| 2003 | } else |
| 2004 | intel_wait_for_vblank(dev, to_intel_crtc(crtc)->pipe); |
Eric Anholt | 5bddd17 | 2010-11-18 09:32:59 +0800 | [diff] [blame] | 2005 | } |
| 2006 | |
Wu Fengguang | 832afda | 2011-12-09 20:42:21 +0800 | [diff] [blame] | 2007 | DP &= ~DP_AUDIO_OUTPUT_ENABLE; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2008 | I915_WRITE(intel_dp->output_reg, DP & ~DP_PORT_EN); |
| 2009 | POSTING_READ(intel_dp->output_reg); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2010 | msleep(intel_dp->panel_power_down_delay); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2011 | } |
| 2012 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2013 | static bool |
| 2014 | intel_dp_get_dpcd(struct intel_dp *intel_dp) |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2015 | { |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2016 | if (intel_dp_aux_native_read_retry(intel_dp, 0x000, intel_dp->dpcd, |
Adam Jackson | b091cd9 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 2017 | sizeof(intel_dp->dpcd)) == 0) |
| 2018 | return false; /* aux transfer failed */ |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2019 | |
Adam Jackson | b091cd9 | 2012-09-18 10:58:49 -0400 | [diff] [blame] | 2020 | if (intel_dp->dpcd[DP_DPCD_REV] == 0) |
| 2021 | return false; /* DPCD not present */ |
| 2022 | |
| 2023 | if (!(intel_dp->dpcd[DP_DOWNSTREAMPORT_PRESENT] & |
| 2024 | DP_DWN_STRM_PORT_PRESENT)) |
| 2025 | return true; /* native DP sink */ |
| 2026 | |
| 2027 | if (intel_dp->dpcd[DP_DPCD_REV] == 0x10) |
| 2028 | return true; /* no per-port downstream info */ |
| 2029 | |
| 2030 | if (intel_dp_aux_native_read_retry(intel_dp, DP_DOWNSTREAM_PORT_0, |
| 2031 | intel_dp->downstream_ports, |
| 2032 | DP_MAX_DOWNSTREAM_PORTS) == 0) |
| 2033 | return false; /* downstream port status fetch failed */ |
| 2034 | |
| 2035 | return true; |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2036 | } |
| 2037 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2038 | static void |
| 2039 | intel_dp_probe_oui(struct intel_dp *intel_dp) |
| 2040 | { |
| 2041 | u8 buf[3]; |
| 2042 | |
| 2043 | if (!(intel_dp->dpcd[DP_DOWN_STREAM_PORT_COUNT] & DP_OUI_SUPPORT)) |
| 2044 | return; |
| 2045 | |
Daniel Vetter | 351cfc3 | 2012-06-12 13:20:47 +0200 | [diff] [blame] | 2046 | ironlake_edp_panel_vdd_on(intel_dp); |
| 2047 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2048 | if (intel_dp_aux_native_read_retry(intel_dp, DP_SINK_OUI, buf, 3)) |
| 2049 | DRM_DEBUG_KMS("Sink OUI: %02hx%02hx%02hx\n", |
| 2050 | buf[0], buf[1], buf[2]); |
| 2051 | |
| 2052 | if (intel_dp_aux_native_read_retry(intel_dp, DP_BRANCH_OUI, buf, 3)) |
| 2053 | DRM_DEBUG_KMS("Branch OUI: %02hx%02hx%02hx\n", |
| 2054 | buf[0], buf[1], buf[2]); |
Daniel Vetter | 351cfc3 | 2012-06-12 13:20:47 +0200 | [diff] [blame] | 2055 | |
| 2056 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2057 | } |
| 2058 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2059 | static bool |
| 2060 | intel_dp_get_sink_irq(struct intel_dp *intel_dp, u8 *sink_irq_vector) |
| 2061 | { |
| 2062 | int ret; |
| 2063 | |
| 2064 | ret = intel_dp_aux_native_read_retry(intel_dp, |
| 2065 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 2066 | sink_irq_vector, 1); |
| 2067 | if (!ret) |
| 2068 | return false; |
| 2069 | |
| 2070 | return true; |
| 2071 | } |
| 2072 | |
| 2073 | static void |
| 2074 | intel_dp_handle_test_request(struct intel_dp *intel_dp) |
| 2075 | { |
| 2076 | /* NAK by default */ |
Daniel Vetter | 9324cf7 | 2012-10-20 21:13:05 +0200 | [diff] [blame^] | 2077 | intel_dp_aux_native_write_1(intel_dp, DP_TEST_RESPONSE, DP_TEST_NAK); |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2078 | } |
| 2079 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2080 | /* |
| 2081 | * According to DP spec |
| 2082 | * 5.1.2: |
| 2083 | * 1. Read DPCD |
| 2084 | * 2. Configure link according to Receiver Capabilities |
| 2085 | * 3. Use Link Training from 2.5.3.3 and 3.5.1.3 |
| 2086 | * 4. Check link status on receipt of hot-plug interrupt |
| 2087 | */ |
| 2088 | |
| 2089 | static void |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2090 | intel_dp_check_link_status(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2091 | { |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2092 | u8 sink_irq_vector; |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2093 | u8 link_status[DP_LINK_STATUS_SIZE]; |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2094 | |
Daniel Vetter | 24e804b | 2012-07-26 19:25:46 +0200 | [diff] [blame] | 2095 | if (!intel_dp->base.connectors_active) |
Keith Packard | d2b996a | 2011-07-25 22:37:51 -0700 | [diff] [blame] | 2096 | return; |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 2097 | |
Daniel Vetter | 24e804b | 2012-07-26 19:25:46 +0200 | [diff] [blame] | 2098 | if (WARN_ON(!intel_dp->base.base.crtc)) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2099 | return; |
| 2100 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2101 | /* Try to read receiver status if the link appears to be up */ |
Keith Packard | 93f62da | 2011-11-01 19:45:03 -0700 | [diff] [blame] | 2102 | if (!intel_dp_get_link_status(intel_dp, link_status)) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2103 | intel_dp_link_down(intel_dp); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2104 | return; |
| 2105 | } |
| 2106 | |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2107 | /* Now read the DPCD to see if it's actually running */ |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2108 | if (!intel_dp_get_dpcd(intel_dp)) { |
Jesse Barnes | 59cd09e | 2011-07-07 11:10:59 -0700 | [diff] [blame] | 2109 | intel_dp_link_down(intel_dp); |
| 2110 | return; |
| 2111 | } |
| 2112 | |
Jesse Barnes | a60f0e3 | 2011-10-20 15:09:17 -0700 | [diff] [blame] | 2113 | /* Try to read the source of the interrupt */ |
| 2114 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11 && |
| 2115 | intel_dp_get_sink_irq(intel_dp, &sink_irq_vector)) { |
| 2116 | /* Clear interrupt source */ |
| 2117 | intel_dp_aux_native_write_1(intel_dp, |
| 2118 | DP_DEVICE_SERVICE_IRQ_VECTOR, |
| 2119 | sink_irq_vector); |
| 2120 | |
| 2121 | if (sink_irq_vector & DP_AUTOMATED_TEST_REQUEST) |
| 2122 | intel_dp_handle_test_request(intel_dp); |
| 2123 | if (sink_irq_vector & (DP_CP_IRQ | DP_SINK_SPECIFIC_IRQ)) |
| 2124 | DRM_DEBUG_DRIVER("CP or sink specific irq unhandled\n"); |
| 2125 | } |
| 2126 | |
Daniel Vetter | 1ffdff1 | 2012-10-18 10:15:24 +0200 | [diff] [blame] | 2127 | if (!drm_dp_channel_eq_ok(link_status, intel_dp->lane_count)) { |
Keith Packard | 92fd8fd | 2011-07-25 19:50:10 -0700 | [diff] [blame] | 2128 | DRM_DEBUG_KMS("%s: channel EQ not ok, retraining\n", |
| 2129 | drm_get_encoder_name(&intel_dp->base.base)); |
Jesse Barnes | 33a34e4 | 2010-09-08 12:42:02 -0700 | [diff] [blame] | 2130 | intel_dp_start_link_train(intel_dp); |
| 2131 | intel_dp_complete_link_train(intel_dp); |
| 2132 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2133 | } |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2134 | |
Adam Jackson | 07d3dc1 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2135 | /* XXX this is probably wrong for multiple downstream ports */ |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2136 | static enum drm_connector_status |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2137 | intel_dp_detect_dpcd(struct intel_dp *intel_dp) |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 2138 | { |
Adam Jackson | 07d3dc1 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2139 | uint8_t *dpcd = intel_dp->dpcd; |
| 2140 | bool hpd; |
| 2141 | uint8_t type; |
| 2142 | |
| 2143 | if (!intel_dp_get_dpcd(intel_dp)) |
| 2144 | return connector_status_disconnected; |
| 2145 | |
| 2146 | /* if there's no downstream port, we're done */ |
| 2147 | if (!(dpcd[DP_DOWNSTREAMPORT_PRESENT] & DP_DWN_STRM_PORT_PRESENT)) |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2148 | return connector_status_connected; |
Adam Jackson | 07d3dc1 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2149 | |
| 2150 | /* If we're HPD-aware, SINK_COUNT changes dynamically */ |
| 2151 | hpd = !!(intel_dp->downstream_ports[0] & DP_DS_PORT_HPD); |
| 2152 | if (hpd) { |
Adam Jackson | da131a4 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 2153 | uint8_t reg; |
Adam Jackson | 07d3dc1 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2154 | if (!intel_dp_aux_native_read_retry(intel_dp, DP_SINK_COUNT, |
Adam Jackson | da131a4 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 2155 | ®, 1)) |
Adam Jackson | 07d3dc1 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2156 | return connector_status_unknown; |
Adam Jackson | da131a4 | 2012-09-20 16:42:45 -0400 | [diff] [blame] | 2157 | return DP_GET_SINK_COUNT(reg) ? connector_status_connected |
| 2158 | : connector_status_disconnected; |
Adam Jackson | 07d3dc1 | 2012-09-18 10:58:50 -0400 | [diff] [blame] | 2159 | } |
| 2160 | |
| 2161 | /* If no HPD, poke DDC gently */ |
| 2162 | if (drm_probe_ddc(&intel_dp->adapter)) |
| 2163 | return connector_status_connected; |
| 2164 | |
| 2165 | /* Well we tried, say unknown for unreliable port types */ |
| 2166 | type = intel_dp->downstream_ports[0] & DP_DS_PORT_TYPE_MASK; |
| 2167 | if (type == DP_DS_PORT_TYPE_VGA || type == DP_DS_PORT_TYPE_NON_EDID) |
| 2168 | return connector_status_unknown; |
| 2169 | |
| 2170 | /* Anything else is out of spec, warn and ignore */ |
| 2171 | DRM_DEBUG_KMS("Broken DP branch device, ignoring\n"); |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2172 | return connector_status_disconnected; |
Adam Jackson | 71ba9000 | 2011-07-12 17:38:04 -0400 | [diff] [blame] | 2173 | } |
| 2174 | |
| 2175 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2176 | ironlake_dp_detect(struct intel_dp *intel_dp) |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2177 | { |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2178 | enum drm_connector_status status; |
| 2179 | |
Chris Wilson | fe16d94 | 2011-02-12 10:29:38 +0000 | [diff] [blame] | 2180 | /* Can't disconnect eDP, but you can close the lid... */ |
| 2181 | if (is_edp(intel_dp)) { |
| 2182 | status = intel_panel_detect(intel_dp->base.base.dev); |
| 2183 | if (status == connector_status_unknown) |
| 2184 | status = connector_status_connected; |
| 2185 | return status; |
| 2186 | } |
Jesse Barnes | 01cb9ea | 2010-10-07 16:01:12 -0700 | [diff] [blame] | 2187 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2188 | return intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2189 | } |
| 2190 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2191 | static enum drm_connector_status |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2192 | g4x_dp_detect(struct intel_dp *intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2193 | { |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2194 | struct drm_device *dev = intel_dp->base.base.dev; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2195 | struct drm_i915_private *dev_priv = dev->dev_private; |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 2196 | uint32_t bit; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2197 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2198 | switch (intel_dp->output_reg) { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2199 | case DP_B: |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 2200 | bit = DPB_HOTPLUG_LIVE_STATUS; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2201 | break; |
| 2202 | case DP_C: |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 2203 | bit = DPC_HOTPLUG_LIVE_STATUS; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2204 | break; |
| 2205 | case DP_D: |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 2206 | bit = DPD_HOTPLUG_LIVE_STATUS; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2207 | break; |
| 2208 | default: |
| 2209 | return connector_status_unknown; |
| 2210 | } |
| 2211 | |
Chris Wilson | 10f76a3 | 2012-05-11 18:01:32 +0100 | [diff] [blame] | 2212 | if ((I915_READ(PORT_HOTPLUG_STAT) & bit) == 0) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2213 | return connector_status_disconnected; |
| 2214 | |
Keith Packard | 26d61aa | 2011-07-25 20:01:09 -0700 | [diff] [blame] | 2215 | return intel_dp_detect_dpcd(intel_dp); |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2216 | } |
| 2217 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2218 | static struct edid * |
| 2219 | intel_dp_get_edid(struct drm_connector *connector, struct i2c_adapter *adapter) |
| 2220 | { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2221 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2222 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2223 | /* use cached edid if we have one */ |
| 2224 | if (intel_connector->edid) { |
| 2225 | struct edid *edid; |
| 2226 | int size; |
| 2227 | |
| 2228 | /* invalid edid */ |
| 2229 | if (IS_ERR(intel_connector->edid)) |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2230 | return NULL; |
| 2231 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2232 | size = (intel_connector->edid->extensions + 1) * EDID_LENGTH; |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2233 | edid = kmalloc(size, GFP_KERNEL); |
| 2234 | if (!edid) |
| 2235 | return NULL; |
| 2236 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2237 | memcpy(edid, intel_connector->edid, size); |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2238 | return edid; |
| 2239 | } |
| 2240 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2241 | return drm_get_edid(connector, adapter); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2242 | } |
| 2243 | |
| 2244 | static int |
| 2245 | intel_dp_get_edid_modes(struct drm_connector *connector, struct i2c_adapter *adapter) |
| 2246 | { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2247 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2248 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2249 | /* use cached edid if we have one */ |
| 2250 | if (intel_connector->edid) { |
| 2251 | /* invalid edid */ |
| 2252 | if (IS_ERR(intel_connector->edid)) |
| 2253 | return 0; |
| 2254 | |
| 2255 | return intel_connector_update_modes(connector, |
| 2256 | intel_connector->edid); |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2257 | } |
| 2258 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2259 | return intel_ddc_get_modes(connector, adapter); |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2260 | } |
| 2261 | |
| 2262 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2263 | /** |
| 2264 | * Uses CRT_HOTPLUG_EN and CRT_HOTPLUG_STAT to detect DP connection. |
| 2265 | * |
| 2266 | * \return true if DP port is connected. |
| 2267 | * \return false if DP port is disconnected. |
| 2268 | */ |
| 2269 | static enum drm_connector_status |
| 2270 | intel_dp_detect(struct drm_connector *connector, bool force) |
| 2271 | { |
| 2272 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 2273 | struct drm_device *dev = intel_dp->base.base.dev; |
| 2274 | enum drm_connector_status status; |
| 2275 | struct edid *edid = NULL; |
| 2276 | |
| 2277 | intel_dp->has_audio = false; |
| 2278 | |
| 2279 | if (HAS_PCH_SPLIT(dev)) |
| 2280 | status = ironlake_dp_detect(intel_dp); |
| 2281 | else |
| 2282 | status = g4x_dp_detect(intel_dp); |
Adam Jackson | 1b9be9d | 2011-07-12 17:38:01 -0400 | [diff] [blame] | 2283 | |
Adam Jackson | ac66ae8 | 2011-07-12 17:38:03 -0400 | [diff] [blame] | 2284 | DRM_DEBUG_KMS("DPCD: %02hx%02hx%02hx%02hx%02hx%02hx%02hx%02hx\n", |
| 2285 | intel_dp->dpcd[0], intel_dp->dpcd[1], intel_dp->dpcd[2], |
| 2286 | intel_dp->dpcd[3], intel_dp->dpcd[4], intel_dp->dpcd[5], |
| 2287 | intel_dp->dpcd[6], intel_dp->dpcd[7]); |
Adam Jackson | 1b9be9d | 2011-07-12 17:38:01 -0400 | [diff] [blame] | 2288 | |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2289 | if (status != connector_status_connected) |
| 2290 | return status; |
| 2291 | |
Adam Jackson | 0d19832 | 2012-05-14 16:05:47 -0400 | [diff] [blame] | 2292 | intel_dp_probe_oui(intel_dp); |
| 2293 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 2294 | if (intel_dp->force_audio != HDMI_AUDIO_AUTO) { |
| 2295 | intel_dp->has_audio = (intel_dp->force_audio == HDMI_AUDIO_ON); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2296 | } else { |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2297 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2298 | if (edid) { |
| 2299 | intel_dp->has_audio = drm_detect_monitor_audio(edid); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2300 | kfree(edid); |
| 2301 | } |
Zhenyu Wang | a9756bb | 2010-09-19 13:09:06 +0800 | [diff] [blame] | 2302 | } |
| 2303 | |
| 2304 | return connector_status_connected; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2305 | } |
| 2306 | |
| 2307 | static int intel_dp_get_modes(struct drm_connector *connector) |
| 2308 | { |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2309 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 2310 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2311 | struct drm_device *dev = intel_dp->base.base.dev; |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2312 | int ret; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2313 | |
| 2314 | /* We should parse the EDID data and find out if it has an audio sink |
| 2315 | */ |
| 2316 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2317 | ret = intel_dp_get_edid_modes(connector, &intel_dp->adapter); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2318 | if (ret) |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2319 | return ret; |
| 2320 | |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2321 | /* if eDP has no EDID, fall back to fixed mode */ |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 2322 | if (is_edp(intel_dp) && intel_connector->panel.fixed_mode) { |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2323 | struct drm_display_mode *mode; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 2324 | mode = drm_mode_duplicate(dev, |
| 2325 | intel_connector->panel.fixed_mode); |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2326 | if (mode) { |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2327 | drm_mode_probed_add(connector, mode); |
| 2328 | return 1; |
| 2329 | } |
| 2330 | } |
| 2331 | return 0; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2332 | } |
| 2333 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2334 | static bool |
| 2335 | intel_dp_detect_audio(struct drm_connector *connector) |
| 2336 | { |
| 2337 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 2338 | struct edid *edid; |
| 2339 | bool has_audio = false; |
| 2340 | |
Keith Packard | 8c241fe | 2011-09-28 16:38:44 -0700 | [diff] [blame] | 2341 | edid = intel_dp_get_edid(connector, &intel_dp->adapter); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2342 | if (edid) { |
| 2343 | has_audio = drm_detect_monitor_audio(edid); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2344 | kfree(edid); |
| 2345 | } |
| 2346 | |
| 2347 | return has_audio; |
| 2348 | } |
| 2349 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2350 | static int |
| 2351 | intel_dp_set_property(struct drm_connector *connector, |
| 2352 | struct drm_property *property, |
| 2353 | uint64_t val) |
| 2354 | { |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2355 | struct drm_i915_private *dev_priv = connector->dev->dev_private; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2356 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
| 2357 | int ret; |
| 2358 | |
| 2359 | ret = drm_connector_property_set_value(connector, property, val); |
| 2360 | if (ret) |
| 2361 | return ret; |
| 2362 | |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 2363 | if (property == dev_priv->force_audio_property) { |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2364 | int i = val; |
| 2365 | bool has_audio; |
| 2366 | |
| 2367 | if (i == intel_dp->force_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2368 | return 0; |
| 2369 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2370 | intel_dp->force_audio = i; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2371 | |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 2372 | if (i == HDMI_AUDIO_AUTO) |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2373 | has_audio = intel_dp_detect_audio(connector); |
| 2374 | else |
Daniel Vetter | c3e5f67 | 2012-02-23 17:14:47 +0100 | [diff] [blame] | 2375 | has_audio = (i == HDMI_AUDIO_ON); |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2376 | |
| 2377 | if (has_audio == intel_dp->has_audio) |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2378 | return 0; |
| 2379 | |
Chris Wilson | 1aad7ac | 2011-02-09 18:46:58 +0000 | [diff] [blame] | 2380 | intel_dp->has_audio = has_audio; |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2381 | goto done; |
| 2382 | } |
| 2383 | |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2384 | if (property == dev_priv->broadcast_rgb_property) { |
| 2385 | if (val == !!intel_dp->color_range) |
| 2386 | return 0; |
| 2387 | |
| 2388 | intel_dp->color_range = val ? DP_COLOR_RANGE_16_235 : 0; |
| 2389 | goto done; |
| 2390 | } |
| 2391 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2392 | return -EINVAL; |
| 2393 | |
| 2394 | done: |
| 2395 | if (intel_dp->base.base.crtc) { |
| 2396 | struct drm_crtc *crtc = intel_dp->base.base.crtc; |
Daniel Vetter | a6778b3 | 2012-07-02 09:56:42 +0200 | [diff] [blame] | 2397 | intel_set_mode(crtc, &crtc->mode, |
| 2398 | crtc->x, crtc->y, crtc->fb); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2399 | } |
| 2400 | |
| 2401 | return 0; |
| 2402 | } |
| 2403 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2404 | static void |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2405 | intel_dp_destroy(struct drm_connector *connector) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2406 | { |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 2407 | struct drm_device *dev = connector->dev; |
Jani Nikula | be3cd5e | 2012-10-12 10:33:05 +0300 | [diff] [blame] | 2408 | struct intel_dp *intel_dp = intel_attached_dp(connector); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 2409 | struct intel_connector *intel_connector = to_intel_connector(connector); |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 2410 | |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2411 | if (!IS_ERR_OR_NULL(intel_connector->edid)) |
| 2412 | kfree(intel_connector->edid); |
| 2413 | |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 2414 | if (is_edp(intel_dp)) { |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 2415 | intel_panel_destroy_backlight(dev); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 2416 | intel_panel_fini(&intel_connector->panel); |
| 2417 | } |
Matthew Garrett | aaa6fd2 | 2011-08-12 12:11:33 +0200 | [diff] [blame] | 2418 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2419 | drm_sysfs_connector_remove(connector); |
| 2420 | drm_connector_cleanup(connector); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2421 | kfree(connector); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2422 | } |
| 2423 | |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 2424 | static void intel_dp_encoder_destroy(struct drm_encoder *encoder) |
| 2425 | { |
| 2426 | struct intel_dp *intel_dp = enc_to_intel_dp(encoder); |
| 2427 | |
| 2428 | i2c_del_adapter(&intel_dp->adapter); |
| 2429 | drm_encoder_cleanup(encoder); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2430 | if (is_edp(intel_dp)) { |
| 2431 | cancel_delayed_work_sync(&intel_dp->panel_vdd_work); |
| 2432 | ironlake_panel_vdd_off_sync(intel_dp); |
| 2433 | } |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 2434 | kfree(intel_dp); |
| 2435 | } |
| 2436 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2437 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs = { |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2438 | .mode_fixup = intel_dp_mode_fixup, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2439 | .mode_set = intel_dp_mode_set, |
Daniel Vetter | 1f70385 | 2012-07-11 16:51:39 +0200 | [diff] [blame] | 2440 | .disable = intel_encoder_noop, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2441 | }; |
| 2442 | |
Paulo Zanoni | a7902ac5 | 2012-10-15 15:51:42 -0300 | [diff] [blame] | 2443 | static const struct drm_encoder_helper_funcs intel_dp_helper_funcs_hsw = { |
| 2444 | .mode_fixup = intel_dp_mode_fixup, |
| 2445 | .mode_set = intel_ddi_mode_set, |
| 2446 | .disable = intel_encoder_noop, |
| 2447 | }; |
| 2448 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2449 | static const struct drm_connector_funcs intel_dp_connector_funcs = { |
Daniel Vetter | 2bd2ad6 | 2012-09-06 22:15:41 +0200 | [diff] [blame] | 2450 | .dpms = intel_connector_dpms, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2451 | .detect = intel_dp_detect, |
| 2452 | .fill_modes = drm_helper_probe_single_connector_modes, |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2453 | .set_property = intel_dp_set_property, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2454 | .destroy = intel_dp_destroy, |
| 2455 | }; |
| 2456 | |
| 2457 | static const struct drm_connector_helper_funcs intel_dp_connector_helper_funcs = { |
| 2458 | .get_modes = intel_dp_get_modes, |
| 2459 | .mode_valid = intel_dp_mode_valid, |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2460 | .best_encoder = intel_best_encoder, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2461 | }; |
| 2462 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2463 | static const struct drm_encoder_funcs intel_dp_enc_funcs = { |
Daniel Vetter | 24d0592 | 2010-08-20 18:08:28 +0200 | [diff] [blame] | 2464 | .destroy = intel_dp_encoder_destroy, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2465 | }; |
| 2466 | |
Chris Wilson | 995b676 | 2010-08-20 13:23:26 +0100 | [diff] [blame] | 2467 | static void |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2468 | intel_dp_hot_plug(struct intel_encoder *intel_encoder) |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2469 | { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2470 | struct intel_dp *intel_dp = container_of(intel_encoder, struct intel_dp, base); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2471 | |
Jesse Barnes | 885a501 | 2011-07-07 11:11:01 -0700 | [diff] [blame] | 2472 | intel_dp_check_link_status(intel_dp); |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2473 | } |
| 2474 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2475 | /* Return which DP Port should be selected for Transcoder DP control */ |
| 2476 | int |
Akshay Joshi | 0206e35 | 2011-08-16 15:34:10 -0400 | [diff] [blame] | 2477 | intel_trans_dp_port_sel(struct drm_crtc *crtc) |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2478 | { |
| 2479 | struct drm_device *dev = crtc->dev; |
Daniel Vetter | 6c2b7c12 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 2480 | struct intel_encoder *encoder; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2481 | |
Daniel Vetter | 6c2b7c12 | 2012-07-05 09:50:24 +0200 | [diff] [blame] | 2482 | for_each_encoder_on_crtc(dev, crtc, encoder) { |
| 2483 | struct intel_dp *intel_dp = enc_to_intel_dp(&encoder->base); |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2484 | |
Keith Packard | 417e822 | 2011-11-01 19:54:11 -0700 | [diff] [blame] | 2485 | if (intel_dp->base.type == INTEL_OUTPUT_DISPLAYPORT || |
| 2486 | intel_dp->base.type == INTEL_OUTPUT_EDP) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2487 | return intel_dp->output_reg; |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2488 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2489 | |
Zhenyu Wang | e3421a1 | 2010-04-08 09:43:27 +0800 | [diff] [blame] | 2490 | return -1; |
| 2491 | } |
| 2492 | |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 2493 | /* check the VBT to see whether the eDP is on DP-D port */ |
Adam Jackson | cb0953d | 2010-07-16 14:46:29 -0400 | [diff] [blame] | 2494 | bool intel_dpd_is_edp(struct drm_device *dev) |
Zhao Yakui | 36e83a1 | 2010-06-12 14:32:21 +0800 | [diff] [blame] | 2495 | { |
| 2496 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2497 | struct child_device_config *p_child; |
| 2498 | int i; |
| 2499 | |
| 2500 | if (!dev_priv->child_dev_num) |
| 2501 | return false; |
| 2502 | |
| 2503 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
| 2504 | p_child = dev_priv->child_dev + i; |
| 2505 | |
| 2506 | if (p_child->dvo_port == PORT_IDPD && |
| 2507 | p_child->device_type == DEVICE_TYPE_eDP) |
| 2508 | return true; |
| 2509 | } |
| 2510 | return false; |
| 2511 | } |
| 2512 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2513 | static void |
| 2514 | intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector) |
| 2515 | { |
Chris Wilson | 3f43c48 | 2011-05-12 22:17:24 +0100 | [diff] [blame] | 2516 | intel_attach_force_audio_property(connector); |
Chris Wilson | e953fd7 | 2011-02-21 22:23:52 +0000 | [diff] [blame] | 2517 | intel_attach_broadcast_rgb_property(connector); |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2518 | } |
| 2519 | |
Keith Packard | c8110e5 | 2009-05-06 11:51:10 -0700 | [diff] [blame] | 2520 | void |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 2521 | intel_dp_init(struct drm_device *dev, int output_reg, enum port port) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2522 | { |
| 2523 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2524 | struct drm_connector *connector; |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2525 | struct intel_dp *intel_dp; |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2526 | struct intel_encoder *intel_encoder; |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2527 | struct intel_connector *intel_connector; |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2528 | struct drm_display_mode *fixed_mode = NULL; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2529 | const char *name = NULL; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2530 | int type; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2531 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2532 | intel_dp = kzalloc(sizeof(struct intel_dp), GFP_KERNEL); |
| 2533 | if (!intel_dp) |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2534 | return; |
| 2535 | |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2536 | intel_dp->output_reg = output_reg; |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 2537 | intel_dp->port = port; |
Daniel Vetter | 0767935 | 2012-09-06 22:15:42 +0200 | [diff] [blame] | 2538 | /* Preserve the current hw state. */ |
| 2539 | intel_dp->DP = I915_READ(intel_dp->output_reg); |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2540 | |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2541 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
| 2542 | if (!intel_connector) { |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2543 | kfree(intel_dp); |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2544 | return; |
| 2545 | } |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2546 | intel_encoder = &intel_dp->base; |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 2547 | intel_dp->attached_connector = intel_connector; |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2548 | |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2549 | if (HAS_PCH_SPLIT(dev) && output_reg == PCH_DP_D) |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2550 | if (intel_dpd_is_edp(dev)) |
Chris Wilson | ea5b213 | 2010-08-04 13:50:23 +0100 | [diff] [blame] | 2551 | intel_dp->is_pch_edp = true; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2552 | |
Gajanan Bhat | 19c0392 | 2012-09-27 19:13:07 +0530 | [diff] [blame] | 2553 | /* |
| 2554 | * FIXME : We need to initialize built-in panels before external panels. |
| 2555 | * For X0, DP_C is fixed as eDP. Revisit this as part of VLV eDP cleanup |
| 2556 | */ |
| 2557 | if (IS_VALLEYVIEW(dev) && output_reg == DP_C) { |
| 2558 | type = DRM_MODE_CONNECTOR_eDP; |
| 2559 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 2560 | } else if (output_reg == DP_A || is_pch_edp(intel_dp)) { |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2561 | type = DRM_MODE_CONNECTOR_eDP; |
| 2562 | intel_encoder->type = INTEL_OUTPUT_EDP; |
| 2563 | } else { |
| 2564 | type = DRM_MODE_CONNECTOR_DisplayPort; |
| 2565 | intel_encoder->type = INTEL_OUTPUT_DISPLAYPORT; |
| 2566 | } |
| 2567 | |
Zhenyu Wang | 55f78c4 | 2010-03-29 16:13:57 +0800 | [diff] [blame] | 2568 | connector = &intel_connector->base; |
Adam Jackson | b329530 | 2010-07-16 14:46:28 -0400 | [diff] [blame] | 2569 | drm_connector_init(dev, connector, &intel_dp_connector_funcs, type); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2570 | drm_connector_helper_add(connector, &intel_dp_connector_helper_funcs); |
| 2571 | |
Dave Airlie | eb1f8e4 | 2010-05-07 06:42:51 +0000 | [diff] [blame] | 2572 | connector->polled = DRM_CONNECTOR_POLL_HPD; |
| 2573 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 2574 | intel_encoder->cloneable = false; |
Ma Ling | f8aed70 | 2009-08-24 13:50:24 +0800 | [diff] [blame] | 2575 | |
Daniel Vetter | 66a9278 | 2012-07-12 20:08:18 +0200 | [diff] [blame] | 2576 | INIT_DELAYED_WORK(&intel_dp->panel_vdd_work, |
| 2577 | ironlake_panel_vdd_work); |
Zhenyu Wang | 6251ec0 | 2010-01-12 05:38:32 +0800 | [diff] [blame] | 2578 | |
Jesse Barnes | 27f8227 | 2011-09-02 12:54:37 -0700 | [diff] [blame] | 2579 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
Jesse Barnes | ee7b9f9 | 2012-04-20 17:11:53 +0100 | [diff] [blame] | 2580 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2581 | connector->interlace_allowed = true; |
| 2582 | connector->doublescan_allowed = 0; |
| 2583 | |
Chris Wilson | 4ef69c7 | 2010-09-09 15:14:28 +0100 | [diff] [blame] | 2584 | drm_encoder_init(dev, &intel_encoder->base, &intel_dp_enc_funcs, |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2585 | DRM_MODE_ENCODER_TMDS); |
Paulo Zanoni | a7902ac5 | 2012-10-15 15:51:42 -0300 | [diff] [blame] | 2586 | |
| 2587 | if (IS_HASWELL(dev)) |
| 2588 | drm_encoder_helper_add(&intel_encoder->base, |
| 2589 | &intel_dp_helper_funcs_hsw); |
| 2590 | else |
| 2591 | drm_encoder_helper_add(&intel_encoder->base, |
| 2592 | &intel_dp_helper_funcs); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2593 | |
Chris Wilson | df0e924 | 2010-09-09 16:20:55 +0100 | [diff] [blame] | 2594 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2595 | drm_sysfs_connector_add(connector); |
| 2596 | |
Paulo Zanoni | a7902ac5 | 2012-10-15 15:51:42 -0300 | [diff] [blame] | 2597 | if (IS_HASWELL(dev)) { |
| 2598 | intel_encoder->enable = intel_enable_ddi; |
| 2599 | intel_encoder->pre_enable = intel_ddi_pre_enable; |
| 2600 | intel_encoder->disable = intel_disable_ddi; |
| 2601 | intel_encoder->post_disable = intel_ddi_post_disable; |
| 2602 | intel_encoder->get_hw_state = intel_ddi_get_hw_state; |
| 2603 | } else { |
| 2604 | intel_encoder->enable = intel_enable_dp; |
| 2605 | intel_encoder->pre_enable = intel_pre_enable_dp; |
| 2606 | intel_encoder->disable = intel_disable_dp; |
| 2607 | intel_encoder->post_disable = intel_post_disable_dp; |
| 2608 | intel_encoder->get_hw_state = intel_dp_get_hw_state; |
| 2609 | } |
Daniel Vetter | 19d8fe1 | 2012-07-02 13:26:27 +0200 | [diff] [blame] | 2610 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
Daniel Vetter | e8cb455 | 2012-07-01 13:05:48 +0200 | [diff] [blame] | 2611 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2612 | /* Set up the DDC bus. */ |
Paulo Zanoni | ab9d7c3 | 2012-07-17 17:53:45 -0300 | [diff] [blame] | 2613 | switch (port) { |
| 2614 | case PORT_A: |
| 2615 | name = "DPDDC-A"; |
| 2616 | break; |
| 2617 | case PORT_B: |
| 2618 | dev_priv->hotplug_supported_mask |= DPB_HOTPLUG_INT_STATUS; |
| 2619 | name = "DPDDC-B"; |
| 2620 | break; |
| 2621 | case PORT_C: |
| 2622 | dev_priv->hotplug_supported_mask |= DPC_HOTPLUG_INT_STATUS; |
| 2623 | name = "DPDDC-C"; |
| 2624 | break; |
| 2625 | case PORT_D: |
| 2626 | dev_priv->hotplug_supported_mask |= DPD_HOTPLUG_INT_STATUS; |
| 2627 | name = "DPDDC-D"; |
| 2628 | break; |
| 2629 | default: |
| 2630 | WARN(1, "Invalid port %c\n", port_name(port)); |
| 2631 | break; |
Zhenyu Wang | 5eb08b6 | 2009-07-24 01:00:31 +0800 | [diff] [blame] | 2632 | } |
| 2633 | |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2634 | /* Cache some DPCD data in the eDP case */ |
| 2635 | if (is_edp(intel_dp)) { |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2636 | struct edp_power_seq cur, vbt; |
| 2637 | u32 pp_on, pp_off, pp_div; |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2638 | |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2639 | pp_on = I915_READ(PCH_PP_ON_DELAYS); |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2640 | pp_off = I915_READ(PCH_PP_OFF_DELAYS); |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2641 | pp_div = I915_READ(PCH_PP_DIVISOR); |
| 2642 | |
Jesse Barnes | bfa3384 | 2012-04-10 11:58:04 -0700 | [diff] [blame] | 2643 | if (!pp_on || !pp_off || !pp_div) { |
| 2644 | DRM_INFO("bad panel power sequencing delays, disabling panel\n"); |
| 2645 | intel_dp_encoder_destroy(&intel_dp->base.base); |
| 2646 | intel_dp_destroy(&intel_connector->base); |
| 2647 | return; |
| 2648 | } |
| 2649 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2650 | /* Pull timing values out of registers */ |
| 2651 | cur.t1_t3 = (pp_on & PANEL_POWER_UP_DELAY_MASK) >> |
| 2652 | PANEL_POWER_UP_DELAY_SHIFT; |
| 2653 | |
| 2654 | cur.t8 = (pp_on & PANEL_LIGHT_ON_DELAY_MASK) >> |
| 2655 | PANEL_LIGHT_ON_DELAY_SHIFT; |
Keith Packard | f2e8b18 | 2011-11-01 20:01:35 -0700 | [diff] [blame] | 2656 | |
Keith Packard | f01eca2 | 2011-09-28 16:48:10 -0700 | [diff] [blame] | 2657 | cur.t9 = (pp_off & PANEL_LIGHT_OFF_DELAY_MASK) >> |
| 2658 | PANEL_LIGHT_OFF_DELAY_SHIFT; |
| 2659 | |
| 2660 | cur.t10 = (pp_off & PANEL_POWER_DOWN_DELAY_MASK) >> |
| 2661 | PANEL_POWER_DOWN_DELAY_SHIFT; |
| 2662 | |
| 2663 | cur.t11_t12 = ((pp_div & PANEL_POWER_CYCLE_DELAY_MASK) >> |
| 2664 | PANEL_POWER_CYCLE_DELAY_SHIFT) * 1000; |
| 2665 | |
| 2666 | DRM_DEBUG_KMS("cur t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 2667 | cur.t1_t3, cur.t8, cur.t9, cur.t10, cur.t11_t12); |
| 2668 | |
| 2669 | vbt = dev_priv->edp.pps; |
| 2670 | |
| 2671 | DRM_DEBUG_KMS("vbt t1_t3 %d t8 %d t9 %d t10 %d t11_t12 %d\n", |
| 2672 | vbt.t1_t3, vbt.t8, vbt.t9, vbt.t10, vbt.t11_t12); |
| 2673 | |
| 2674 | #define get_delay(field) ((max(cur.field, vbt.field) + 9) / 10) |
| 2675 | |
| 2676 | intel_dp->panel_power_up_delay = get_delay(t1_t3); |
| 2677 | intel_dp->backlight_on_delay = get_delay(t8); |
| 2678 | intel_dp->backlight_off_delay = get_delay(t9); |
| 2679 | intel_dp->panel_power_down_delay = get_delay(t10); |
| 2680 | intel_dp->panel_power_cycle_delay = get_delay(t11_t12); |
| 2681 | |
| 2682 | DRM_DEBUG_KMS("panel power up delay %d, power down delay %d, power cycle delay %d\n", |
| 2683 | intel_dp->panel_power_up_delay, intel_dp->panel_power_down_delay, |
| 2684 | intel_dp->panel_power_cycle_delay); |
| 2685 | |
| 2686 | DRM_DEBUG_KMS("backlight on delay %d, off delay %d\n", |
| 2687 | intel_dp->backlight_on_delay, intel_dp->backlight_off_delay); |
Dave Airlie | c1f0526 | 2012-08-30 11:06:18 +1000 | [diff] [blame] | 2688 | } |
| 2689 | |
| 2690 | intel_dp_i2c_init(intel_dp, intel_connector, name); |
| 2691 | |
| 2692 | if (is_edp(intel_dp)) { |
| 2693 | bool ret; |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2694 | struct drm_display_mode *scan; |
Dave Airlie | c1f0526 | 2012-08-30 11:06:18 +1000 | [diff] [blame] | 2695 | struct edid *edid; |
Jesse Barnes | 5d61350 | 2011-01-24 17:10:54 -0800 | [diff] [blame] | 2696 | |
| 2697 | ironlake_edp_panel_vdd_on(intel_dp); |
Keith Packard | 59f3e27 | 2011-07-25 20:01:56 -0700 | [diff] [blame] | 2698 | ret = intel_dp_get_dpcd(intel_dp); |
Keith Packard | bd94315 | 2011-09-18 23:09:52 -0700 | [diff] [blame] | 2699 | ironlake_edp_panel_vdd_off(intel_dp, false); |
Keith Packard | 99ea712 | 2011-11-01 19:57:50 -0700 | [diff] [blame] | 2700 | |
Keith Packard | 59f3e27 | 2011-07-25 20:01:56 -0700 | [diff] [blame] | 2701 | if (ret) { |
Jesse Barnes | 7183dc2 | 2011-07-07 11:10:58 -0700 | [diff] [blame] | 2702 | if (intel_dp->dpcd[DP_DPCD_REV] >= 0x11) |
| 2703 | dev_priv->no_aux_handshake = |
| 2704 | intel_dp->dpcd[DP_MAX_DOWNSPREAD] & |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2705 | DP_NO_AUX_HANDSHAKE_LINK_TRAINING; |
| 2706 | } else { |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2707 | /* if this fails, presume the device is a ghost */ |
Takashi Iwai | 48898b0 | 2011-03-18 09:06:49 +0000 | [diff] [blame] | 2708 | DRM_INFO("failed to retrieve link info, disabling eDP\n"); |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2709 | intel_dp_encoder_destroy(&intel_dp->base.base); |
Takashi Iwai | 48898b0 | 2011-03-18 09:06:49 +0000 | [diff] [blame] | 2710 | intel_dp_destroy(&intel_connector->base); |
Chris Wilson | 3d3dc14 | 2011-02-12 10:33:12 +0000 | [diff] [blame] | 2711 | return; |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2712 | } |
Jesse Barnes | 8966738 | 2010-10-07 16:01:21 -0700 | [diff] [blame] | 2713 | |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2714 | ironlake_edp_panel_vdd_on(intel_dp); |
| 2715 | edid = drm_get_edid(connector, &intel_dp->adapter); |
| 2716 | if (edid) { |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2717 | if (drm_add_edid_modes(connector, edid)) { |
| 2718 | drm_mode_connector_update_edid_property(connector, edid); |
| 2719 | drm_edid_to_eld(connector, edid); |
| 2720 | } else { |
| 2721 | kfree(edid); |
| 2722 | edid = ERR_PTR(-EINVAL); |
| 2723 | } |
| 2724 | } else { |
| 2725 | edid = ERR_PTR(-ENOENT); |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2726 | } |
Jani Nikula | 9cd300e | 2012-10-19 14:51:52 +0300 | [diff] [blame] | 2727 | intel_connector->edid = edid; |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2728 | |
| 2729 | /* prefer fixed mode from EDID if available */ |
| 2730 | list_for_each_entry(scan, &connector->probed_modes, head) { |
| 2731 | if ((scan->type & DRM_MODE_TYPE_PREFERRED)) { |
| 2732 | fixed_mode = drm_mode_duplicate(dev, scan); |
| 2733 | break; |
| 2734 | } |
| 2735 | } |
| 2736 | |
| 2737 | /* fallback to VBT if available for eDP */ |
| 2738 | if (!fixed_mode && dev_priv->lfp_lvds_vbt_mode) { |
| 2739 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
| 2740 | if (fixed_mode) |
| 2741 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
| 2742 | } |
Jani Nikula | f8779fd | 2012-10-19 14:51:48 +0300 | [diff] [blame] | 2743 | |
Jesse Barnes | d6f24d0 | 2012-06-14 15:28:33 -0400 | [diff] [blame] | 2744 | ironlake_edp_panel_vdd_off(intel_dp, false); |
| 2745 | } |
Keith Packard | 552fb0b | 2011-09-28 16:31:53 -0700 | [diff] [blame] | 2746 | |
Eric Anholt | 21d40d3 | 2010-03-25 11:11:14 -0700 | [diff] [blame] | 2747 | intel_encoder->hot_plug = intel_dp_hot_plug; |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2748 | |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 2749 | if (is_edp(intel_dp)) { |
Jani Nikula | dd06f90 | 2012-10-19 14:51:50 +0300 | [diff] [blame] | 2750 | intel_panel_init(&intel_connector->panel, fixed_mode); |
Jani Nikula | 0657b6b | 2012-10-19 14:51:46 +0300 | [diff] [blame] | 2751 | intel_panel_setup_backlight(connector); |
Jani Nikula | 1d50870 | 2012-10-19 14:51:49 +0300 | [diff] [blame] | 2752 | } |
Zhenyu Wang | 32f9d65 | 2009-07-24 01:00:32 +0800 | [diff] [blame] | 2753 | |
Chris Wilson | f684960 | 2010-09-19 09:29:33 +0100 | [diff] [blame] | 2754 | intel_dp_add_properties(intel_dp, connector); |
| 2755 | |
Keith Packard | a4fc5ed | 2009-04-07 16:16:42 -0700 | [diff] [blame] | 2756 | /* For G4X desktop chip, PEG_BAND_GAP_DATA 3:0 must first be written |
| 2757 | * 0xd. Failure to do so will result in spurious interrupts being |
| 2758 | * generated on the port when a cable is not attached. |
| 2759 | */ |
| 2760 | if (IS_G4X(dev) && !IS_GM45(dev)) { |
| 2761 | u32 temp = I915_READ(PEG_BAND_GAP_DATA); |
| 2762 | I915_WRITE(PEG_BAND_GAP_DATA, (temp & ~0xf) | 0xd); |
| 2763 | } |
| 2764 | } |