Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 34 | #include <linux/slab.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 35 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 36 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 37 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 38 | static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
| 39 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 40 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 41 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 42 | int write); |
| 43 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 44 | uint64_t offset, |
| 45 | uint64_t size); |
| 46 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 47 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 48 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 49 | unsigned alignment); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 50 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 51 | static int i915_gem_evict_something(struct drm_device *dev, int min_size); |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 52 | static int i915_gem_evict_from_inactive_list(struct drm_device *dev); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 53 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 54 | struct drm_i915_gem_pwrite *args, |
| 55 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 56 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 57 | static LIST_HEAD(shrink_list); |
| 58 | static DEFINE_SPINLOCK(shrink_list_lock); |
| 59 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 60 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
| 61 | unsigned long end) |
| 62 | { |
| 63 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 64 | |
| 65 | if (start >= end || |
| 66 | (start & (PAGE_SIZE - 1)) != 0 || |
| 67 | (end & (PAGE_SIZE - 1)) != 0) { |
| 68 | return -EINVAL; |
| 69 | } |
| 70 | |
| 71 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 72 | end - start); |
| 73 | |
| 74 | dev->gtt_total = (uint32_t) (end - start); |
| 75 | |
| 76 | return 0; |
| 77 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 78 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 79 | int |
| 80 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 81 | struct drm_file *file_priv) |
| 82 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 83 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 84 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 85 | |
| 86 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 87 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 88 | mutex_unlock(&dev->struct_mutex); |
| 89 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 90 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 91 | } |
| 92 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 93 | int |
| 94 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 95 | struct drm_file *file_priv) |
| 96 | { |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 97 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 98 | |
| 99 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 100 | return -ENODEV; |
| 101 | |
| 102 | args->aper_size = dev->gtt_total; |
Keith Packard | 2678d9d | 2008-11-20 22:54:54 -0800 | [diff] [blame] | 103 | args->aper_available_size = (args->aper_size - |
| 104 | atomic_read(&dev->pin_memory)); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 105 | |
| 106 | return 0; |
| 107 | } |
| 108 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 109 | |
| 110 | /** |
| 111 | * Creates a new mm object and returns a handle to it. |
| 112 | */ |
| 113 | int |
| 114 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 115 | struct drm_file *file_priv) |
| 116 | { |
| 117 | struct drm_i915_gem_create *args = data; |
| 118 | struct drm_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 119 | int ret; |
| 120 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 121 | |
| 122 | args->size = roundup(args->size, PAGE_SIZE); |
| 123 | |
| 124 | /* Allocate the new object */ |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 125 | obj = i915_gem_alloc_object(dev, args->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 126 | if (obj == NULL) |
| 127 | return -ENOMEM; |
| 128 | |
| 129 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 130 | drm_gem_object_handle_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 131 | |
| 132 | if (ret) |
| 133 | return ret; |
| 134 | |
| 135 | args->handle = handle; |
| 136 | |
| 137 | return 0; |
| 138 | } |
| 139 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 140 | static inline int |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 141 | fast_shmem_read(struct page **pages, |
| 142 | loff_t page_base, int page_offset, |
| 143 | char __user *data, |
| 144 | int length) |
| 145 | { |
| 146 | char __iomem *vaddr; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 147 | int unwritten; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 148 | |
| 149 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 150 | if (vaddr == NULL) |
| 151 | return -ENOMEM; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 152 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 153 | kunmap_atomic(vaddr, KM_USER0); |
| 154 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 155 | if (unwritten) |
| 156 | return -EFAULT; |
| 157 | |
| 158 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 159 | } |
| 160 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 161 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
| 162 | { |
| 163 | drm_i915_private_t *dev_priv = obj->dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 164 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 165 | |
| 166 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 167 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 168 | } |
| 169 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 170 | static inline void |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 171 | slow_shmem_copy(struct page *dst_page, |
| 172 | int dst_offset, |
| 173 | struct page *src_page, |
| 174 | int src_offset, |
| 175 | int length) |
| 176 | { |
| 177 | char *dst_vaddr, *src_vaddr; |
| 178 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 179 | dst_vaddr = kmap(dst_page); |
| 180 | src_vaddr = kmap(src_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 181 | |
| 182 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 183 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 184 | kunmap(src_page); |
| 185 | kunmap(dst_page); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 186 | } |
| 187 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 188 | static inline void |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 189 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 190 | int gpu_offset, |
| 191 | struct page *cpu_page, |
| 192 | int cpu_offset, |
| 193 | int length, |
| 194 | int is_read) |
| 195 | { |
| 196 | char *gpu_vaddr, *cpu_vaddr; |
| 197 | |
| 198 | /* Use the unswizzled path if this page isn't affected. */ |
| 199 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 200 | if (is_read) |
| 201 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 202 | gpu_page, gpu_offset, length); |
| 203 | else |
| 204 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 205 | cpu_page, cpu_offset, length); |
| 206 | } |
| 207 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 208 | gpu_vaddr = kmap(gpu_page); |
| 209 | cpu_vaddr = kmap(cpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 210 | |
| 211 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 212 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 213 | */ |
| 214 | while (length > 0) { |
| 215 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 216 | int this_length = min(cacheline_end - gpu_offset, length); |
| 217 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 218 | |
| 219 | if (is_read) { |
| 220 | memcpy(cpu_vaddr + cpu_offset, |
| 221 | gpu_vaddr + swizzled_gpu_offset, |
| 222 | this_length); |
| 223 | } else { |
| 224 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 225 | cpu_vaddr + cpu_offset, |
| 226 | this_length); |
| 227 | } |
| 228 | cpu_offset += this_length; |
| 229 | gpu_offset += this_length; |
| 230 | length -= this_length; |
| 231 | } |
| 232 | |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 233 | kunmap(cpu_page); |
| 234 | kunmap(gpu_page); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 235 | } |
| 236 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 237 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 238 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 239 | * from the backing pages of the object to the user's address space. On a |
| 240 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 241 | */ |
| 242 | static int |
| 243 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 244 | struct drm_i915_gem_pread *args, |
| 245 | struct drm_file *file_priv) |
| 246 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 247 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 248 | ssize_t remain; |
| 249 | loff_t offset, page_base; |
| 250 | char __user *user_data; |
| 251 | int page_offset, page_length; |
| 252 | int ret; |
| 253 | |
| 254 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 255 | remain = args->size; |
| 256 | |
| 257 | mutex_lock(&dev->struct_mutex); |
| 258 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 259 | ret = i915_gem_object_get_pages(obj, 0); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 260 | if (ret != 0) |
| 261 | goto fail_unlock; |
| 262 | |
| 263 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 264 | args->size); |
| 265 | if (ret != 0) |
| 266 | goto fail_put_pages; |
| 267 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 268 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 269 | offset = args->offset; |
| 270 | |
| 271 | while (remain > 0) { |
| 272 | /* Operation in this page |
| 273 | * |
| 274 | * page_base = page offset within aperture |
| 275 | * page_offset = offset within page |
| 276 | * page_length = bytes to copy for this page |
| 277 | */ |
| 278 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 279 | page_offset = offset & (PAGE_SIZE-1); |
| 280 | page_length = remain; |
| 281 | if ((page_offset + remain) > PAGE_SIZE) |
| 282 | page_length = PAGE_SIZE - page_offset; |
| 283 | |
| 284 | ret = fast_shmem_read(obj_priv->pages, |
| 285 | page_base, page_offset, |
| 286 | user_data, page_length); |
| 287 | if (ret) |
| 288 | goto fail_put_pages; |
| 289 | |
| 290 | remain -= page_length; |
| 291 | user_data += page_length; |
| 292 | offset += page_length; |
| 293 | } |
| 294 | |
| 295 | fail_put_pages: |
| 296 | i915_gem_object_put_pages(obj); |
| 297 | fail_unlock: |
| 298 | mutex_unlock(&dev->struct_mutex); |
| 299 | |
| 300 | return ret; |
| 301 | } |
| 302 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 303 | static int |
| 304 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) |
| 305 | { |
| 306 | int ret; |
| 307 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 308 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 309 | |
| 310 | /* If we've insufficient memory to map in the pages, attempt |
| 311 | * to make some space by throwing out some old buffers. |
| 312 | */ |
| 313 | if (ret == -ENOMEM) { |
| 314 | struct drm_device *dev = obj->dev; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 315 | |
| 316 | ret = i915_gem_evict_something(dev, obj->size); |
| 317 | if (ret) |
| 318 | return ret; |
| 319 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 320 | ret = i915_gem_object_get_pages(obj, 0); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 321 | } |
| 322 | |
| 323 | return ret; |
| 324 | } |
| 325 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 326 | /** |
| 327 | * This is the fallback shmem pread path, which allocates temporary storage |
| 328 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 329 | * can copy out of the object's backing pages while holding the struct mutex |
| 330 | * and not take page faults. |
| 331 | */ |
| 332 | static int |
| 333 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 334 | struct drm_i915_gem_pread *args, |
| 335 | struct drm_file *file_priv) |
| 336 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 337 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 338 | struct mm_struct *mm = current->mm; |
| 339 | struct page **user_pages; |
| 340 | ssize_t remain; |
| 341 | loff_t offset, pinned_pages, i; |
| 342 | loff_t first_data_page, last_data_page, num_pages; |
| 343 | int shmem_page_index, shmem_page_offset; |
| 344 | int data_page_index, data_page_offset; |
| 345 | int page_length; |
| 346 | int ret; |
| 347 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 348 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 349 | |
| 350 | remain = args->size; |
| 351 | |
| 352 | /* Pin the user pages containing the data. We can't fault while |
| 353 | * holding the struct mutex, yet we want to hold it while |
| 354 | * dereferencing the user data. |
| 355 | */ |
| 356 | first_data_page = data_ptr / PAGE_SIZE; |
| 357 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 358 | num_pages = last_data_page - first_data_page + 1; |
| 359 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 360 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 361 | if (user_pages == NULL) |
| 362 | return -ENOMEM; |
| 363 | |
| 364 | down_read(&mm->mmap_sem); |
| 365 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 366 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 367 | up_read(&mm->mmap_sem); |
| 368 | if (pinned_pages < num_pages) { |
| 369 | ret = -EFAULT; |
| 370 | goto fail_put_user_pages; |
| 371 | } |
| 372 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 373 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 374 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 375 | mutex_lock(&dev->struct_mutex); |
| 376 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 377 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 378 | if (ret) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 379 | goto fail_unlock; |
| 380 | |
| 381 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 382 | args->size); |
| 383 | if (ret != 0) |
| 384 | goto fail_put_pages; |
| 385 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 386 | obj_priv = to_intel_bo(obj); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 387 | offset = args->offset; |
| 388 | |
| 389 | while (remain > 0) { |
| 390 | /* Operation in this page |
| 391 | * |
| 392 | * shmem_page_index = page number within shmem file |
| 393 | * shmem_page_offset = offset within page in shmem file |
| 394 | * data_page_index = page number in get_user_pages return |
| 395 | * data_page_offset = offset with data_page_index page. |
| 396 | * page_length = bytes to copy for this page |
| 397 | */ |
| 398 | shmem_page_index = offset / PAGE_SIZE; |
| 399 | shmem_page_offset = offset & ~PAGE_MASK; |
| 400 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 401 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 402 | |
| 403 | page_length = remain; |
| 404 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 405 | page_length = PAGE_SIZE - shmem_page_offset; |
| 406 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 407 | page_length = PAGE_SIZE - data_page_offset; |
| 408 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 409 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 410 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 411 | shmem_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 412 | user_pages[data_page_index], |
| 413 | data_page_offset, |
| 414 | page_length, |
| 415 | 1); |
| 416 | } else { |
| 417 | slow_shmem_copy(user_pages[data_page_index], |
| 418 | data_page_offset, |
| 419 | obj_priv->pages[shmem_page_index], |
| 420 | shmem_page_offset, |
| 421 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 422 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 423 | |
| 424 | remain -= page_length; |
| 425 | data_ptr += page_length; |
| 426 | offset += page_length; |
| 427 | } |
| 428 | |
| 429 | fail_put_pages: |
| 430 | i915_gem_object_put_pages(obj); |
| 431 | fail_unlock: |
| 432 | mutex_unlock(&dev->struct_mutex); |
| 433 | fail_put_user_pages: |
| 434 | for (i = 0; i < pinned_pages; i++) { |
| 435 | SetPageDirty(user_pages[i]); |
| 436 | page_cache_release(user_pages[i]); |
| 437 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 438 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 439 | |
| 440 | return ret; |
| 441 | } |
| 442 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 443 | /** |
| 444 | * Reads data from the object referenced by handle. |
| 445 | * |
| 446 | * On error, the contents of *data are undefined. |
| 447 | */ |
| 448 | int |
| 449 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 450 | struct drm_file *file_priv) |
| 451 | { |
| 452 | struct drm_i915_gem_pread *args = data; |
| 453 | struct drm_gem_object *obj; |
| 454 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 455 | int ret; |
| 456 | |
| 457 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 458 | if (obj == NULL) |
| 459 | return -EBADF; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 460 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 461 | |
| 462 | /* Bounds check source. |
| 463 | * |
| 464 | * XXX: This could use review for overflow issues... |
| 465 | */ |
| 466 | if (args->offset > obj->size || args->size > obj->size || |
| 467 | args->offset + args->size > obj->size) { |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 468 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 469 | return -EINVAL; |
| 470 | } |
| 471 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 472 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 473 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 474 | } else { |
| 475 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
| 476 | if (ret != 0) |
| 477 | ret = i915_gem_shmem_pread_slow(dev, obj, args, |
| 478 | file_priv); |
| 479 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 480 | |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 481 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 482 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 483 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 484 | } |
| 485 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 486 | /* This is the fast write path which cannot handle |
| 487 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 488 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 489 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 490 | static inline int |
| 491 | fast_user_write(struct io_mapping *mapping, |
| 492 | loff_t page_base, int page_offset, |
| 493 | char __user *user_data, |
| 494 | int length) |
| 495 | { |
| 496 | char *vaddr_atomic; |
| 497 | unsigned long unwritten; |
| 498 | |
| 499 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
| 500 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 501 | user_data, length); |
| 502 | io_mapping_unmap_atomic(vaddr_atomic); |
| 503 | if (unwritten) |
| 504 | return -EFAULT; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 505 | return 0; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 506 | } |
| 507 | |
| 508 | /* Here's the write path which can sleep for |
| 509 | * page faults |
| 510 | */ |
| 511 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 512 | static inline void |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 513 | slow_kernel_write(struct io_mapping *mapping, |
| 514 | loff_t gtt_base, int gtt_offset, |
| 515 | struct page *user_page, int user_offset, |
| 516 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 517 | { |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 518 | char __iomem *dst_vaddr; |
| 519 | char *src_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 520 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 521 | dst_vaddr = io_mapping_map_wc(mapping, gtt_base); |
| 522 | src_vaddr = kmap(user_page); |
| 523 | |
| 524 | memcpy_toio(dst_vaddr + gtt_offset, |
| 525 | src_vaddr + user_offset, |
| 526 | length); |
| 527 | |
| 528 | kunmap(user_page); |
| 529 | io_mapping_unmap(dst_vaddr); |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 530 | } |
| 531 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 532 | static inline int |
| 533 | fast_shmem_write(struct page **pages, |
| 534 | loff_t page_base, int page_offset, |
| 535 | char __user *data, |
| 536 | int length) |
| 537 | { |
| 538 | char __iomem *vaddr; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 539 | unsigned long unwritten; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 540 | |
| 541 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 542 | if (vaddr == NULL) |
| 543 | return -ENOMEM; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 544 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 545 | kunmap_atomic(vaddr, KM_USER0); |
| 546 | |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 547 | if (unwritten) |
| 548 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 549 | return 0; |
| 550 | } |
| 551 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 552 | /** |
| 553 | * This is the fast pwrite path, where we copy the data directly from the |
| 554 | * user into the GTT, uncached. |
| 555 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 556 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 557 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 558 | struct drm_i915_gem_pwrite *args, |
| 559 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 560 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 561 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 562 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 563 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 564 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 565 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 566 | int page_offset, page_length; |
| 567 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 568 | |
| 569 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 570 | remain = args->size; |
| 571 | if (!access_ok(VERIFY_READ, user_data, remain)) |
| 572 | return -EFAULT; |
| 573 | |
| 574 | |
| 575 | mutex_lock(&dev->struct_mutex); |
| 576 | ret = i915_gem_object_pin(obj, 0); |
| 577 | if (ret) { |
| 578 | mutex_unlock(&dev->struct_mutex); |
| 579 | return ret; |
| 580 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 581 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 582 | if (ret) |
| 583 | goto fail; |
| 584 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 585 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 586 | offset = obj_priv->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 587 | |
| 588 | while (remain > 0) { |
| 589 | /* Operation in this page |
| 590 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 591 | * page_base = page offset within aperture |
| 592 | * page_offset = offset within page |
| 593 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 594 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 595 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 596 | page_offset = offset & (PAGE_SIZE-1); |
| 597 | page_length = remain; |
| 598 | if ((page_offset + remain) > PAGE_SIZE) |
| 599 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 600 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 601 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, |
| 602 | page_offset, user_data, page_length); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 603 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 604 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 605 | * source page isn't available. Return the error and we'll |
| 606 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 607 | */ |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 608 | if (ret) |
| 609 | goto fail; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 610 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 611 | remain -= page_length; |
| 612 | user_data += page_length; |
| 613 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 614 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 615 | |
| 616 | fail: |
| 617 | i915_gem_object_unpin(obj); |
| 618 | mutex_unlock(&dev->struct_mutex); |
| 619 | |
| 620 | return ret; |
| 621 | } |
| 622 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 623 | /** |
| 624 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 625 | * the memory and maps it using kmap_atomic for copying. |
| 626 | * |
| 627 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 628 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 629 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 630 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 631 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 632 | struct drm_i915_gem_pwrite *args, |
| 633 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 634 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 635 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 636 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 637 | ssize_t remain; |
| 638 | loff_t gtt_page_base, offset; |
| 639 | loff_t first_data_page, last_data_page, num_pages; |
| 640 | loff_t pinned_pages, i; |
| 641 | struct page **user_pages; |
| 642 | struct mm_struct *mm = current->mm; |
| 643 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 644 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 645 | uint64_t data_ptr = args->data_ptr; |
| 646 | |
| 647 | remain = args->size; |
| 648 | |
| 649 | /* Pin the user pages containing the data. We can't fault while |
| 650 | * holding the struct mutex, and all of the pwrite implementations |
| 651 | * want to hold it while dereferencing the user data. |
| 652 | */ |
| 653 | first_data_page = data_ptr / PAGE_SIZE; |
| 654 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 655 | num_pages = last_data_page - first_data_page + 1; |
| 656 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 657 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 658 | if (user_pages == NULL) |
| 659 | return -ENOMEM; |
| 660 | |
| 661 | down_read(&mm->mmap_sem); |
| 662 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 663 | num_pages, 0, 0, user_pages, NULL); |
| 664 | up_read(&mm->mmap_sem); |
| 665 | if (pinned_pages < num_pages) { |
| 666 | ret = -EFAULT; |
| 667 | goto out_unpin_pages; |
| 668 | } |
| 669 | |
| 670 | mutex_lock(&dev->struct_mutex); |
| 671 | ret = i915_gem_object_pin(obj, 0); |
| 672 | if (ret) |
| 673 | goto out_unlock; |
| 674 | |
| 675 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 676 | if (ret) |
| 677 | goto out_unpin_object; |
| 678 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 679 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 680 | offset = obj_priv->gtt_offset + args->offset; |
| 681 | |
| 682 | while (remain > 0) { |
| 683 | /* Operation in this page |
| 684 | * |
| 685 | * gtt_page_base = page offset within aperture |
| 686 | * gtt_page_offset = offset within page in aperture |
| 687 | * data_page_index = page number in get_user_pages return |
| 688 | * data_page_offset = offset with data_page_index page. |
| 689 | * page_length = bytes to copy for this page |
| 690 | */ |
| 691 | gtt_page_base = offset & PAGE_MASK; |
| 692 | gtt_page_offset = offset & ~PAGE_MASK; |
| 693 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 694 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 695 | |
| 696 | page_length = remain; |
| 697 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 698 | page_length = PAGE_SIZE - gtt_page_offset; |
| 699 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 700 | page_length = PAGE_SIZE - data_page_offset; |
| 701 | |
Chris Wilson | ab34c22 | 2010-05-27 14:15:35 +0100 | [diff] [blame] | 702 | slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 703 | gtt_page_base, gtt_page_offset, |
| 704 | user_pages[data_page_index], |
| 705 | data_page_offset, |
| 706 | page_length); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 707 | |
| 708 | remain -= page_length; |
| 709 | offset += page_length; |
| 710 | data_ptr += page_length; |
| 711 | } |
| 712 | |
| 713 | out_unpin_object: |
| 714 | i915_gem_object_unpin(obj); |
| 715 | out_unlock: |
| 716 | mutex_unlock(&dev->struct_mutex); |
| 717 | out_unpin_pages: |
| 718 | for (i = 0; i < pinned_pages; i++) |
| 719 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 720 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 721 | |
| 722 | return ret; |
| 723 | } |
| 724 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 725 | /** |
| 726 | * This is the fast shmem pwrite path, which attempts to directly |
| 727 | * copy_from_user into the kmapped pages backing the object. |
| 728 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 729 | static int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 730 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 731 | struct drm_i915_gem_pwrite *args, |
| 732 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 733 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 734 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 735 | ssize_t remain; |
| 736 | loff_t offset, page_base; |
| 737 | char __user *user_data; |
| 738 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 739 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 740 | |
| 741 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 742 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 743 | |
| 744 | mutex_lock(&dev->struct_mutex); |
| 745 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 746 | ret = i915_gem_object_get_pages(obj, 0); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 747 | if (ret != 0) |
| 748 | goto fail_unlock; |
| 749 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 750 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 751 | if (ret != 0) |
| 752 | goto fail_put_pages; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 753 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 754 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 755 | offset = args->offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 756 | obj_priv->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 757 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 758 | while (remain > 0) { |
| 759 | /* Operation in this page |
| 760 | * |
| 761 | * page_base = page offset within aperture |
| 762 | * page_offset = offset within page |
| 763 | * page_length = bytes to copy for this page |
| 764 | */ |
| 765 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 766 | page_offset = offset & (PAGE_SIZE-1); |
| 767 | page_length = remain; |
| 768 | if ((page_offset + remain) > PAGE_SIZE) |
| 769 | page_length = PAGE_SIZE - page_offset; |
| 770 | |
| 771 | ret = fast_shmem_write(obj_priv->pages, |
| 772 | page_base, page_offset, |
| 773 | user_data, page_length); |
| 774 | if (ret) |
| 775 | goto fail_put_pages; |
| 776 | |
| 777 | remain -= page_length; |
| 778 | user_data += page_length; |
| 779 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 780 | } |
| 781 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 782 | fail_put_pages: |
| 783 | i915_gem_object_put_pages(obj); |
| 784 | fail_unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 785 | mutex_unlock(&dev->struct_mutex); |
| 786 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 787 | return ret; |
| 788 | } |
| 789 | |
| 790 | /** |
| 791 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 792 | * the memory and maps it using kmap_atomic for copying. |
| 793 | * |
| 794 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 795 | * struct_mutex is held. |
| 796 | */ |
| 797 | static int |
| 798 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 799 | struct drm_i915_gem_pwrite *args, |
| 800 | struct drm_file *file_priv) |
| 801 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 802 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 803 | struct mm_struct *mm = current->mm; |
| 804 | struct page **user_pages; |
| 805 | ssize_t remain; |
| 806 | loff_t offset, pinned_pages, i; |
| 807 | loff_t first_data_page, last_data_page, num_pages; |
| 808 | int shmem_page_index, shmem_page_offset; |
| 809 | int data_page_index, data_page_offset; |
| 810 | int page_length; |
| 811 | int ret; |
| 812 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 813 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 814 | |
| 815 | remain = args->size; |
| 816 | |
| 817 | /* Pin the user pages containing the data. We can't fault while |
| 818 | * holding the struct mutex, and all of the pwrite implementations |
| 819 | * want to hold it while dereferencing the user data. |
| 820 | */ |
| 821 | first_data_page = data_ptr / PAGE_SIZE; |
| 822 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 823 | num_pages = last_data_page - first_data_page + 1; |
| 824 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 825 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 826 | if (user_pages == NULL) |
| 827 | return -ENOMEM; |
| 828 | |
| 829 | down_read(&mm->mmap_sem); |
| 830 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 831 | num_pages, 0, 0, user_pages, NULL); |
| 832 | up_read(&mm->mmap_sem); |
| 833 | if (pinned_pages < num_pages) { |
| 834 | ret = -EFAULT; |
| 835 | goto fail_put_user_pages; |
| 836 | } |
| 837 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 838 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 839 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 840 | mutex_lock(&dev->struct_mutex); |
| 841 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 842 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 843 | if (ret) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 844 | goto fail_unlock; |
| 845 | |
| 846 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 847 | if (ret != 0) |
| 848 | goto fail_put_pages; |
| 849 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 850 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 851 | offset = args->offset; |
| 852 | obj_priv->dirty = 1; |
| 853 | |
| 854 | while (remain > 0) { |
| 855 | /* Operation in this page |
| 856 | * |
| 857 | * shmem_page_index = page number within shmem file |
| 858 | * shmem_page_offset = offset within page in shmem file |
| 859 | * data_page_index = page number in get_user_pages return |
| 860 | * data_page_offset = offset with data_page_index page. |
| 861 | * page_length = bytes to copy for this page |
| 862 | */ |
| 863 | shmem_page_index = offset / PAGE_SIZE; |
| 864 | shmem_page_offset = offset & ~PAGE_MASK; |
| 865 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 866 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 867 | |
| 868 | page_length = remain; |
| 869 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 870 | page_length = PAGE_SIZE - shmem_page_offset; |
| 871 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 872 | page_length = PAGE_SIZE - data_page_offset; |
| 873 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 874 | if (do_bit17_swizzling) { |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 875 | slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 876 | shmem_page_offset, |
| 877 | user_pages[data_page_index], |
| 878 | data_page_offset, |
Chris Wilson | 99a03df | 2010-05-27 14:15:34 +0100 | [diff] [blame] | 879 | page_length, |
| 880 | 0); |
| 881 | } else { |
| 882 | slow_shmem_copy(obj_priv->pages[shmem_page_index], |
| 883 | shmem_page_offset, |
| 884 | user_pages[data_page_index], |
| 885 | data_page_offset, |
| 886 | page_length); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 887 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 888 | |
| 889 | remain -= page_length; |
| 890 | data_ptr += page_length; |
| 891 | offset += page_length; |
| 892 | } |
| 893 | |
| 894 | fail_put_pages: |
| 895 | i915_gem_object_put_pages(obj); |
| 896 | fail_unlock: |
| 897 | mutex_unlock(&dev->struct_mutex); |
| 898 | fail_put_user_pages: |
| 899 | for (i = 0; i < pinned_pages; i++) |
| 900 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 901 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 902 | |
| 903 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 904 | } |
| 905 | |
| 906 | /** |
| 907 | * Writes data to the object referenced by handle. |
| 908 | * |
| 909 | * On error, the contents of the buffer that were to be modified are undefined. |
| 910 | */ |
| 911 | int |
| 912 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 913 | struct drm_file *file_priv) |
| 914 | { |
| 915 | struct drm_i915_gem_pwrite *args = data; |
| 916 | struct drm_gem_object *obj; |
| 917 | struct drm_i915_gem_object *obj_priv; |
| 918 | int ret = 0; |
| 919 | |
| 920 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 921 | if (obj == NULL) |
| 922 | return -EBADF; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 923 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 924 | |
| 925 | /* Bounds check destination. |
| 926 | * |
| 927 | * XXX: This could use review for overflow issues... |
| 928 | */ |
| 929 | if (args->offset > obj->size || args->size > obj->size || |
| 930 | args->offset + args->size > obj->size) { |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 931 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 932 | return -EINVAL; |
| 933 | } |
| 934 | |
| 935 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 936 | * it would end up going through the fenced access, and we'll get |
| 937 | * different detiling behavior between reading and writing. |
| 938 | * pread/pwrite currently are reading and writing from the CPU |
| 939 | * perspective, requiring manual detiling by the client. |
| 940 | */ |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 941 | if (obj_priv->phys_obj) |
| 942 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); |
| 943 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
Chris Wilson | 9b8c4a0 | 2010-05-27 14:21:01 +0100 | [diff] [blame] | 944 | dev->gtt_total != 0 && |
| 945 | obj->write_domain != I915_GEM_DOMAIN_CPU) { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 946 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
| 947 | if (ret == -EFAULT) { |
| 948 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, |
| 949 | file_priv); |
| 950 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 951 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
| 952 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 953 | } else { |
| 954 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); |
| 955 | if (ret == -EFAULT) { |
| 956 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, |
| 957 | file_priv); |
| 958 | } |
| 959 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 960 | |
| 961 | #if WATCH_PWRITE |
| 962 | if (ret) |
| 963 | DRM_INFO("pwrite failed %d\n", ret); |
| 964 | #endif |
| 965 | |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 966 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 967 | |
| 968 | return ret; |
| 969 | } |
| 970 | |
| 971 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 972 | * Called when user space prepares to use an object with the CPU, either |
| 973 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 974 | */ |
| 975 | int |
| 976 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 977 | struct drm_file *file_priv) |
| 978 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 979 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 980 | struct drm_i915_gem_set_domain *args = data; |
| 981 | struct drm_gem_object *obj; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 982 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 983 | uint32_t read_domains = args->read_domains; |
| 984 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 985 | int ret; |
| 986 | |
| 987 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 988 | return -ENODEV; |
| 989 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 990 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 991 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 992 | return -EINVAL; |
| 993 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 994 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 995 | return -EINVAL; |
| 996 | |
| 997 | /* Having something in the write domain implies it's in the read |
| 998 | * domain, and only that read domain. Enforce that in the request. |
| 999 | */ |
| 1000 | if (write_domain != 0 && read_domains != write_domain) |
| 1001 | return -EINVAL; |
| 1002 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1003 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1004 | if (obj == NULL) |
| 1005 | return -EBADF; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1006 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1007 | |
| 1008 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1009 | |
| 1010 | intel_mark_busy(dev, obj); |
| 1011 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1012 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 1013 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1014 | obj, obj->size, read_domains, write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1015 | #endif |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1016 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1017 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1018 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1019 | /* Update the LRU on the fence for the CPU access that's |
| 1020 | * about to occur. |
| 1021 | */ |
| 1022 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1023 | struct drm_i915_fence_reg *reg = |
| 1024 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1025 | list_move_tail(®->lru_list, |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1026 | &dev_priv->mm.fence_list); |
| 1027 | } |
| 1028 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1029 | /* Silently promote "you're not bound, there was nothing to do" |
| 1030 | * to success, since the client was just asking us to |
| 1031 | * make sure everything was done. |
| 1032 | */ |
| 1033 | if (ret == -EINVAL) |
| 1034 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1035 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1036 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1037 | } |
| 1038 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1039 | drm_gem_object_unreference(obj); |
| 1040 | mutex_unlock(&dev->struct_mutex); |
| 1041 | return ret; |
| 1042 | } |
| 1043 | |
| 1044 | /** |
| 1045 | * Called when user space has done writes to this buffer |
| 1046 | */ |
| 1047 | int |
| 1048 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1049 | struct drm_file *file_priv) |
| 1050 | { |
| 1051 | struct drm_i915_gem_sw_finish *args = data; |
| 1052 | struct drm_gem_object *obj; |
| 1053 | struct drm_i915_gem_object *obj_priv; |
| 1054 | int ret = 0; |
| 1055 | |
| 1056 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1057 | return -ENODEV; |
| 1058 | |
| 1059 | mutex_lock(&dev->struct_mutex); |
| 1060 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1061 | if (obj == NULL) { |
| 1062 | mutex_unlock(&dev->struct_mutex); |
| 1063 | return -EBADF; |
| 1064 | } |
| 1065 | |
| 1066 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 1067 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1068 | __func__, args->handle, obj, obj->size); |
| 1069 | #endif |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1070 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1071 | |
| 1072 | /* Pinned buffers may be scanout, so flush the cache */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1073 | if (obj_priv->pin_count) |
| 1074 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1075 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1076 | drm_gem_object_unreference(obj); |
| 1077 | mutex_unlock(&dev->struct_mutex); |
| 1078 | return ret; |
| 1079 | } |
| 1080 | |
| 1081 | /** |
| 1082 | * Maps the contents of an object, returning the address it is mapped |
| 1083 | * into. |
| 1084 | * |
| 1085 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1086 | * imply a ref on the object itself. |
| 1087 | */ |
| 1088 | int |
| 1089 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1090 | struct drm_file *file_priv) |
| 1091 | { |
| 1092 | struct drm_i915_gem_mmap *args = data; |
| 1093 | struct drm_gem_object *obj; |
| 1094 | loff_t offset; |
| 1095 | unsigned long addr; |
| 1096 | |
| 1097 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1098 | return -ENODEV; |
| 1099 | |
| 1100 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1101 | if (obj == NULL) |
| 1102 | return -EBADF; |
| 1103 | |
| 1104 | offset = args->offset; |
| 1105 | |
| 1106 | down_write(¤t->mm->mmap_sem); |
| 1107 | addr = do_mmap(obj->filp, 0, args->size, |
| 1108 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1109 | args->offset); |
| 1110 | up_write(¤t->mm->mmap_sem); |
Luca Barbieri | bc9025b | 2010-02-09 05:49:12 +0000 | [diff] [blame] | 1111 | drm_gem_object_unreference_unlocked(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1112 | if (IS_ERR((void *)addr)) |
| 1113 | return addr; |
| 1114 | |
| 1115 | args->addr_ptr = (uint64_t) addr; |
| 1116 | |
| 1117 | return 0; |
| 1118 | } |
| 1119 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1120 | /** |
| 1121 | * i915_gem_fault - fault a page into the GTT |
| 1122 | * vma: VMA in question |
| 1123 | * vmf: fault info |
| 1124 | * |
| 1125 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1126 | * from userspace. The fault handler takes care of binding the object to |
| 1127 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1128 | * only if needed based on whether the old reg is still valid or the object |
| 1129 | * is tiled) and inserting a new PTE into the faulting process. |
| 1130 | * |
| 1131 | * Note that the faulting process may involve evicting existing objects |
| 1132 | * from the GTT and/or fence registers to make room. So performance may |
| 1133 | * suffer if the GTT working set is large or there are few fence registers |
| 1134 | * left. |
| 1135 | */ |
| 1136 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1137 | { |
| 1138 | struct drm_gem_object *obj = vma->vm_private_data; |
| 1139 | struct drm_device *dev = obj->dev; |
| 1140 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1141 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1142 | pgoff_t page_offset; |
| 1143 | unsigned long pfn; |
| 1144 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1145 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1146 | |
| 1147 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1148 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1149 | PAGE_SHIFT; |
| 1150 | |
| 1151 | /* Now bind it into the GTT if needed */ |
| 1152 | mutex_lock(&dev->struct_mutex); |
| 1153 | if (!obj_priv->gtt_space) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1154 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1155 | if (ret) |
| 1156 | goto unlock; |
Kristian Høgsberg | 07f4f3e | 2009-05-27 14:37:28 -0400 | [diff] [blame] | 1157 | |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 1158 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1159 | |
| 1160 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1161 | if (ret) |
| 1162 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1163 | } |
| 1164 | |
| 1165 | /* Need a new fence register? */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1166 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1167 | ret = i915_gem_object_get_fence_reg(obj); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1168 | if (ret) |
| 1169 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1170 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1171 | |
| 1172 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 1173 | page_offset; |
| 1174 | |
| 1175 | /* Finally, remap it using the new GTT offset */ |
| 1176 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1177 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1178 | mutex_unlock(&dev->struct_mutex); |
| 1179 | |
| 1180 | switch (ret) { |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1181 | case 0: |
| 1182 | case -ERESTARTSYS: |
| 1183 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1184 | case -ENOMEM: |
| 1185 | case -EAGAIN: |
| 1186 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1187 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1188 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1189 | } |
| 1190 | } |
| 1191 | |
| 1192 | /** |
| 1193 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1194 | * @obj: obj in question |
| 1195 | * |
| 1196 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1197 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1198 | * up the object based on the offset and sets up the various memory mapping |
| 1199 | * structures. |
| 1200 | * |
| 1201 | * This routine allocates and attaches a fake offset for @obj. |
| 1202 | */ |
| 1203 | static int |
| 1204 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 1205 | { |
| 1206 | struct drm_device *dev = obj->dev; |
| 1207 | struct drm_gem_mm *mm = dev->mm_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1208 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1209 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1210 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1211 | int ret = 0; |
| 1212 | |
| 1213 | /* Set the object up for mmap'ing */ |
| 1214 | list = &obj->map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1215 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1216 | if (!list->map) |
| 1217 | return -ENOMEM; |
| 1218 | |
| 1219 | map = list->map; |
| 1220 | map->type = _DRM_GEM; |
| 1221 | map->size = obj->size; |
| 1222 | map->handle = obj; |
| 1223 | |
| 1224 | /* Get a DRM GEM mmap offset allocated... */ |
| 1225 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 1226 | obj->size / PAGE_SIZE, 0, 0); |
| 1227 | if (!list->file_offset_node) { |
| 1228 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
| 1229 | ret = -ENOMEM; |
| 1230 | goto out_free_list; |
| 1231 | } |
| 1232 | |
| 1233 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 1234 | obj->size / PAGE_SIZE, 0); |
| 1235 | if (!list->file_offset_node) { |
| 1236 | ret = -ENOMEM; |
| 1237 | goto out_free_list; |
| 1238 | } |
| 1239 | |
| 1240 | list->hash.key = list->file_offset_node->start; |
| 1241 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { |
| 1242 | DRM_ERROR("failed to add to map hash\n"); |
Chris Wilson | 5618ca6 | 2009-12-02 15:15:30 +0000 | [diff] [blame] | 1243 | ret = -ENOMEM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1244 | goto out_free_mm; |
| 1245 | } |
| 1246 | |
| 1247 | /* By now we should be all set, any drm_mmap request on the offset |
| 1248 | * below will get to our mmap & fault handler */ |
| 1249 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; |
| 1250 | |
| 1251 | return 0; |
| 1252 | |
| 1253 | out_free_mm: |
| 1254 | drm_mm_put_block(list->file_offset_node); |
| 1255 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1256 | kfree(list->map); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1257 | |
| 1258 | return ret; |
| 1259 | } |
| 1260 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1261 | /** |
| 1262 | * i915_gem_release_mmap - remove physical page mappings |
| 1263 | * @obj: obj in question |
| 1264 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1265 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1266 | * relinquish ownership of the pages back to the system. |
| 1267 | * |
| 1268 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1269 | * object through the GTT and then lose the fence register due to |
| 1270 | * resource pressure. Similarly if the object has been moved out of the |
| 1271 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1272 | * mapping will then trigger a page fault on the next user access, allowing |
| 1273 | * fixup by i915_gem_fault(). |
| 1274 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1275 | void |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1276 | i915_gem_release_mmap(struct drm_gem_object *obj) |
| 1277 | { |
| 1278 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1279 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1280 | |
| 1281 | if (dev->dev_mapping) |
| 1282 | unmap_mapping_range(dev->dev_mapping, |
| 1283 | obj_priv->mmap_offset, obj->size, 1); |
| 1284 | } |
| 1285 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1286 | static void |
| 1287 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) |
| 1288 | { |
| 1289 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1290 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1291 | struct drm_gem_mm *mm = dev->mm_private; |
| 1292 | struct drm_map_list *list; |
| 1293 | |
| 1294 | list = &obj->map_list; |
| 1295 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
| 1296 | |
| 1297 | if (list->file_offset_node) { |
| 1298 | drm_mm_put_block(list->file_offset_node); |
| 1299 | list->file_offset_node = NULL; |
| 1300 | } |
| 1301 | |
| 1302 | if (list->map) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1303 | kfree(list->map); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1304 | list->map = NULL; |
| 1305 | } |
| 1306 | |
| 1307 | obj_priv->mmap_offset = 0; |
| 1308 | } |
| 1309 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1310 | /** |
| 1311 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1312 | * @obj: object to check |
| 1313 | * |
| 1314 | * Return the required GTT alignment for an object, taking into account |
| 1315 | * potential fence register mapping if needed. |
| 1316 | */ |
| 1317 | static uint32_t |
| 1318 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 1319 | { |
| 1320 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1321 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1322 | int start, i; |
| 1323 | |
| 1324 | /* |
| 1325 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1326 | * if a fence register is needed for the object. |
| 1327 | */ |
| 1328 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) |
| 1329 | return 4096; |
| 1330 | |
| 1331 | /* |
| 1332 | * Previous chips need to be aligned to the size of the smallest |
| 1333 | * fence register that can contain the object. |
| 1334 | */ |
| 1335 | if (IS_I9XX(dev)) |
| 1336 | start = 1024*1024; |
| 1337 | else |
| 1338 | start = 512*1024; |
| 1339 | |
| 1340 | for (i = start; i < obj->size; i <<= 1) |
| 1341 | ; |
| 1342 | |
| 1343 | return i; |
| 1344 | } |
| 1345 | |
| 1346 | /** |
| 1347 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1348 | * @dev: DRM device |
| 1349 | * @data: GTT mapping ioctl data |
| 1350 | * @file_priv: GEM object info |
| 1351 | * |
| 1352 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1353 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1354 | * up so we can get faults in the handler above. |
| 1355 | * |
| 1356 | * The fault handler will take care of binding the object into the GTT |
| 1357 | * (since it may have been evicted to make room for something), allocating |
| 1358 | * a fence register, and mapping the appropriate aperture address into |
| 1359 | * userspace. |
| 1360 | */ |
| 1361 | int |
| 1362 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1363 | struct drm_file *file_priv) |
| 1364 | { |
| 1365 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1366 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1367 | struct drm_gem_object *obj; |
| 1368 | struct drm_i915_gem_object *obj_priv; |
| 1369 | int ret; |
| 1370 | |
| 1371 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1372 | return -ENODEV; |
| 1373 | |
| 1374 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1375 | if (obj == NULL) |
| 1376 | return -EBADF; |
| 1377 | |
| 1378 | mutex_lock(&dev->struct_mutex); |
| 1379 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1380 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1381 | |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1382 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 1383 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
| 1384 | drm_gem_object_unreference(obj); |
| 1385 | mutex_unlock(&dev->struct_mutex); |
| 1386 | return -EINVAL; |
| 1387 | } |
| 1388 | |
| 1389 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1390 | if (!obj_priv->mmap_offset) { |
| 1391 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1392 | if (ret) { |
| 1393 | drm_gem_object_unreference(obj); |
| 1394 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1395 | return ret; |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1396 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1397 | } |
| 1398 | |
| 1399 | args->offset = obj_priv->mmap_offset; |
| 1400 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1401 | /* |
| 1402 | * Pull it into the GTT so that we have a page list (makes the |
| 1403 | * initial fault faster and any subsequent flushing possible). |
| 1404 | */ |
| 1405 | if (!obj_priv->agp_mem) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1406 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1407 | if (ret) { |
| 1408 | drm_gem_object_unreference(obj); |
| 1409 | mutex_unlock(&dev->struct_mutex); |
| 1410 | return ret; |
| 1411 | } |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 1412 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1413 | } |
| 1414 | |
| 1415 | drm_gem_object_unreference(obj); |
| 1416 | mutex_unlock(&dev->struct_mutex); |
| 1417 | |
| 1418 | return 0; |
| 1419 | } |
| 1420 | |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 1421 | void |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1422 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1423 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1424 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1425 | int page_count = obj->size / PAGE_SIZE; |
| 1426 | int i; |
| 1427 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1428 | BUG_ON(obj_priv->pages_refcount == 0); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1429 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1430 | |
| 1431 | if (--obj_priv->pages_refcount != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1432 | return; |
| 1433 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1434 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1435 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1436 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1437 | if (obj_priv->madv == I915_MADV_DONTNEED) |
Chris Wilson | 13a05fd | 2009-09-20 23:03:19 +0100 | [diff] [blame] | 1438 | obj_priv->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1439 | |
| 1440 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1441 | if (obj_priv->dirty) |
| 1442 | set_page_dirty(obj_priv->pages[i]); |
| 1443 | |
| 1444 | if (obj_priv->madv == I915_MADV_WILLNEED) |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1445 | mark_page_accessed(obj_priv->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1446 | |
| 1447 | page_cache_release(obj_priv->pages[i]); |
| 1448 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1449 | obj_priv->dirty = 0; |
| 1450 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1451 | drm_free_large(obj_priv->pages); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1452 | obj_priv->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1453 | } |
| 1454 | |
| 1455 | static void |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1456 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno, |
| 1457 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1458 | { |
| 1459 | struct drm_device *dev = obj->dev; |
| 1460 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1461 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1462 | BUG_ON(ring == NULL); |
| 1463 | obj_priv->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1464 | |
| 1465 | /* Add a reference if we're newly entering the active list. */ |
| 1466 | if (!obj_priv->active) { |
| 1467 | drm_gem_object_reference(obj); |
| 1468 | obj_priv->active = 1; |
| 1469 | } |
| 1470 | /* Move from whatever list we were on to the tail of execution. */ |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1471 | spin_lock(&dev_priv->mm.active_list_lock); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1472 | list_move_tail(&obj_priv->list, &ring->active_list); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1473 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1474 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1475 | } |
| 1476 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1477 | static void |
| 1478 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 1479 | { |
| 1480 | struct drm_device *dev = obj->dev; |
| 1481 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1482 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1483 | |
| 1484 | BUG_ON(!obj_priv->active); |
| 1485 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); |
| 1486 | obj_priv->last_rendering_seqno = 0; |
| 1487 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1488 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1489 | /* Immediately discard the backing storage */ |
| 1490 | static void |
| 1491 | i915_gem_object_truncate(struct drm_gem_object *obj) |
| 1492 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1493 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1494 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1495 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1496 | inode = obj->filp->f_path.dentry->d_inode; |
| 1497 | if (inode->i_op->truncate) |
| 1498 | inode->i_op->truncate (inode); |
| 1499 | |
| 1500 | obj_priv->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1501 | } |
| 1502 | |
| 1503 | static inline int |
| 1504 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) |
| 1505 | { |
| 1506 | return obj_priv->madv == I915_MADV_DONTNEED; |
| 1507 | } |
| 1508 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1509 | static void |
| 1510 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 1511 | { |
| 1512 | struct drm_device *dev = obj->dev; |
| 1513 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1514 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1515 | |
| 1516 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 1517 | if (obj_priv->pin_count != 0) |
| 1518 | list_del_init(&obj_priv->list); |
| 1519 | else |
| 1520 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 1521 | |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 1522 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
| 1523 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1524 | obj_priv->last_rendering_seqno = 0; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1525 | obj_priv->ring = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1526 | if (obj_priv->active) { |
| 1527 | obj_priv->active = 0; |
| 1528 | drm_gem_object_unreference(obj); |
| 1529 | } |
| 1530 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 1531 | } |
| 1532 | |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1533 | static void |
| 1534 | i915_gem_process_flushing_list(struct drm_device *dev, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1535 | uint32_t flush_domains, uint32_t seqno, |
| 1536 | struct intel_ring_buffer *ring) |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1537 | { |
| 1538 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1539 | struct drm_i915_gem_object *obj_priv, *next; |
| 1540 | |
| 1541 | list_for_each_entry_safe(obj_priv, next, |
| 1542 | &dev_priv->mm.gpu_write_list, |
| 1543 | gpu_write_list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 1544 | struct drm_gem_object *obj = &obj_priv->base; |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1545 | |
| 1546 | if ((obj->write_domain & flush_domains) == |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1547 | obj->write_domain && |
| 1548 | obj_priv->ring->ring_flag == ring->ring_flag) { |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1549 | uint32_t old_write_domain = obj->write_domain; |
| 1550 | |
| 1551 | obj->write_domain = 0; |
| 1552 | list_del_init(&obj_priv->gpu_write_list); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1553 | i915_gem_object_move_to_active(obj, seqno, ring); |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1554 | |
| 1555 | /* update the fence lru list */ |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1556 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 1557 | struct drm_i915_fence_reg *reg = |
| 1558 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 1559 | list_move_tail(®->lru_list, |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1560 | &dev_priv->mm.fence_list); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 1561 | } |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1562 | |
| 1563 | trace_i915_gem_object_change_domain(obj, |
| 1564 | obj->read_domains, |
| 1565 | old_write_domain); |
| 1566 | } |
| 1567 | } |
| 1568 | } |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1569 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1570 | uint32_t |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1571 | i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1572 | uint32_t flush_domains, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1573 | { |
| 1574 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1575 | struct drm_i915_file_private *i915_file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1576 | struct drm_i915_gem_request *request; |
| 1577 | uint32_t seqno; |
| 1578 | int was_empty; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1579 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1580 | if (file_priv != NULL) |
| 1581 | i915_file_priv = file_priv->driver_priv; |
| 1582 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1583 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1584 | if (request == NULL) |
| 1585 | return 0; |
| 1586 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1587 | seqno = ring->add_request(dev, ring, file_priv, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1588 | |
| 1589 | request->seqno = seqno; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1590 | request->ring = ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1591 | request->emitted_jiffies = jiffies; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1592 | was_empty = list_empty(&ring->request_list); |
| 1593 | list_add_tail(&request->list, &ring->request_list); |
| 1594 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1595 | if (i915_file_priv) { |
| 1596 | list_add_tail(&request->client_list, |
| 1597 | &i915_file_priv->mm.request_list); |
| 1598 | } else { |
| 1599 | INIT_LIST_HEAD(&request->client_list); |
| 1600 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1601 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1602 | /* Associate any objects on the flushing list matching the write |
| 1603 | * domain we're flushing with our flush. |
| 1604 | */ |
Daniel Vetter | 6356039 | 2010-02-19 11:51:59 +0100 | [diff] [blame] | 1605 | if (flush_domains != 0) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1606 | i915_gem_process_flushing_list(dev, flush_domains, seqno, ring); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1607 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1608 | if (!dev_priv->mm.suspended) { |
| 1609 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
| 1610 | if (was_empty) |
| 1611 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1612 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1613 | return seqno; |
| 1614 | } |
| 1615 | |
| 1616 | /** |
| 1617 | * Command execution barrier |
| 1618 | * |
| 1619 | * Ensures that all commands in the ring are finished |
| 1620 | * before signalling the CPU |
| 1621 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 1622 | static uint32_t |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1623 | i915_retire_commands(struct drm_device *dev, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1624 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1625 | uint32_t flush_domains = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1626 | |
| 1627 | /* The sampler always gets flushed on i965 (sigh) */ |
| 1628 | if (IS_I965G(dev)) |
| 1629 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1630 | |
| 1631 | ring->flush(dev, ring, |
| 1632 | I915_GEM_DOMAIN_COMMAND, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1633 | return flush_domains; |
| 1634 | } |
| 1635 | |
| 1636 | /** |
| 1637 | * Moves buffers associated only with the given active seqno from the active |
| 1638 | * to inactive list, potentially freeing them. |
| 1639 | */ |
| 1640 | static void |
| 1641 | i915_gem_retire_request(struct drm_device *dev, |
| 1642 | struct drm_i915_gem_request *request) |
| 1643 | { |
| 1644 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1645 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1646 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1647 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1648 | /* Move any buffers on the active list that are no longer referenced |
| 1649 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1650 | */ |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1651 | spin_lock(&dev_priv->mm.active_list_lock); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1652 | while (!list_empty(&request->ring->active_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1653 | struct drm_gem_object *obj; |
| 1654 | struct drm_i915_gem_object *obj_priv; |
| 1655 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1656 | obj_priv = list_first_entry(&request->ring->active_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1657 | struct drm_i915_gem_object, |
| 1658 | list); |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 1659 | obj = &obj_priv->base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1660 | |
| 1661 | /* If the seqno being retired doesn't match the oldest in the |
| 1662 | * list, then the oldest in the list must still be newer than |
| 1663 | * this seqno. |
| 1664 | */ |
| 1665 | if (obj_priv->last_rendering_seqno != request->seqno) |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1666 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1667 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1668 | #if WATCH_LRU |
| 1669 | DRM_INFO("%s: retire %d moves to inactive list %p\n", |
| 1670 | __func__, request->seqno, obj); |
| 1671 | #endif |
| 1672 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1673 | if (obj->write_domain != 0) |
| 1674 | i915_gem_object_move_to_flushing(obj); |
Shaohua Li | 68c8434 | 2009-04-08 10:58:23 +0800 | [diff] [blame] | 1675 | else { |
| 1676 | /* Take a reference on the object so it won't be |
| 1677 | * freed while the spinlock is held. The list |
| 1678 | * protection for this spinlock is safe when breaking |
| 1679 | * the lock like this since the next thing we do |
| 1680 | * is just get the head of the list again. |
| 1681 | */ |
| 1682 | drm_gem_object_reference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1683 | i915_gem_object_move_to_inactive(obj); |
Shaohua Li | 68c8434 | 2009-04-08 10:58:23 +0800 | [diff] [blame] | 1684 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 1685 | drm_gem_object_unreference(obj); |
| 1686 | spin_lock(&dev_priv->mm.active_list_lock); |
| 1687 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1688 | } |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1689 | out: |
| 1690 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1691 | } |
| 1692 | |
| 1693 | /** |
| 1694 | * Returns true if seq1 is later than seq2. |
| 1695 | */ |
Ben Gamari | 22be172 | 2009-09-14 17:48:43 -0400 | [diff] [blame] | 1696 | bool |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1697 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 1698 | { |
| 1699 | return (int32_t)(seq1 - seq2) >= 0; |
| 1700 | } |
| 1701 | |
| 1702 | uint32_t |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1703 | i915_get_gem_seqno(struct drm_device *dev, |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1704 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1705 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1706 | return ring->get_gem_seqno(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1707 | } |
| 1708 | |
| 1709 | /** |
| 1710 | * This function clears the request list as sequence numbers are passed. |
| 1711 | */ |
| 1712 | void |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1713 | i915_gem_retire_requests(struct drm_device *dev, |
| 1714 | struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1715 | { |
| 1716 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1717 | uint32_t seqno; |
| 1718 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1719 | if (!ring->status_page.page_addr |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1720 | || list_empty(&ring->request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1721 | return; |
| 1722 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1723 | seqno = i915_get_gem_seqno(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1724 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1725 | while (!list_empty(&ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1726 | struct drm_i915_gem_request *request; |
| 1727 | uint32_t retiring_seqno; |
| 1728 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1729 | request = list_first_entry(&ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1730 | struct drm_i915_gem_request, |
| 1731 | list); |
| 1732 | retiring_seqno = request->seqno; |
| 1733 | |
| 1734 | if (i915_seqno_passed(seqno, retiring_seqno) || |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1735 | atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1736 | i915_gem_retire_request(dev, request); |
| 1737 | |
| 1738 | list_del(&request->list); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1739 | list_del(&request->client_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1740 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1741 | } else |
| 1742 | break; |
| 1743 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1744 | |
| 1745 | if (unlikely (dev_priv->trace_irq_seqno && |
| 1746 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1747 | |
| 1748 | ring->user_irq_put(dev, ring); |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1749 | dev_priv->trace_irq_seqno = 0; |
| 1750 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1751 | } |
| 1752 | |
| 1753 | void |
| 1754 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1755 | { |
| 1756 | drm_i915_private_t *dev_priv; |
| 1757 | struct drm_device *dev; |
| 1758 | |
| 1759 | dev_priv = container_of(work, drm_i915_private_t, |
| 1760 | mm.retire_work.work); |
| 1761 | dev = dev_priv->dev; |
| 1762 | |
| 1763 | mutex_lock(&dev->struct_mutex); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1764 | i915_gem_retire_requests(dev, &dev_priv->render_ring); |
| 1765 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1766 | if (HAS_BSD(dev)) |
| 1767 | i915_gem_retire_requests(dev, &dev_priv->bsd_ring); |
| 1768 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 1769 | if (!dev_priv->mm.suspended && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1770 | (!list_empty(&dev_priv->render_ring.request_list) || |
| 1771 | (HAS_BSD(dev) && |
| 1772 | !list_empty(&dev_priv->bsd_ring.request_list)))) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1773 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1774 | mutex_unlock(&dev->struct_mutex); |
| 1775 | } |
| 1776 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1777 | int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1778 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, |
| 1779 | int interruptible, struct intel_ring_buffer *ring) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1780 | { |
| 1781 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1782 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1783 | int ret = 0; |
| 1784 | |
| 1785 | BUG_ON(seqno == 0); |
| 1786 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1787 | if (atomic_read(&dev_priv->mm.wedged)) |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 1788 | return -EIO; |
| 1789 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1790 | if (!i915_seqno_passed(ring->get_gem_seqno(dev, ring), seqno)) { |
Eric Anholt | bad720f | 2009-10-22 16:11:14 -0700 | [diff] [blame] | 1791 | if (HAS_PCH_SPLIT(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1792 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 1793 | else |
| 1794 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1795 | if (!ier) { |
| 1796 | DRM_ERROR("something (likely vbetool) disabled " |
| 1797 | "interrupts, re-enabling\n"); |
| 1798 | i915_driver_irq_preinstall(dev); |
| 1799 | i915_driver_irq_postinstall(dev); |
| 1800 | } |
| 1801 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1802 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 1803 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1804 | ring->waiting_gem_seqno = seqno; |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1805 | ring->user_irq_get(dev, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1806 | if (interruptible) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1807 | ret = wait_event_interruptible(ring->irq_queue, |
| 1808 | i915_seqno_passed( |
| 1809 | ring->get_gem_seqno(dev, ring), seqno) |
| 1810 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1811 | else |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1812 | wait_event(ring->irq_queue, |
| 1813 | i915_seqno_passed( |
| 1814 | ring->get_gem_seqno(dev, ring), seqno) |
| 1815 | || atomic_read(&dev_priv->mm.wedged)); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1816 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1817 | ring->user_irq_put(dev, ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1818 | ring->waiting_gem_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1819 | |
| 1820 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1821 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1822 | if (atomic_read(&dev_priv->mm.wedged)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1823 | ret = -EIO; |
| 1824 | |
| 1825 | if (ret && ret != -ERESTARTSYS) |
| 1826 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1827 | __func__, ret, seqno, ring->get_gem_seqno(dev, ring)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1828 | |
| 1829 | /* Directly dispatch request retiring. While we have the work queue |
| 1830 | * to handle this, the waiter on a request often wants an associated |
| 1831 | * buffer to have made it to the inactive list, and we would need |
| 1832 | * a separate wait queue to handle that. |
| 1833 | */ |
| 1834 | if (ret == 0) |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1835 | i915_gem_retire_requests(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1836 | |
| 1837 | return ret; |
| 1838 | } |
| 1839 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1840 | /** |
| 1841 | * Waits for a sequence number to be signaled, and cleans up the |
| 1842 | * request and object lists appropriately for that event. |
| 1843 | */ |
| 1844 | static int |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1845 | i915_wait_request(struct drm_device *dev, uint32_t seqno, |
| 1846 | struct intel_ring_buffer *ring) |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1847 | { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1848 | return i915_do_wait_request(dev, seqno, 1, ring); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1849 | } |
| 1850 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1851 | static void |
| 1852 | i915_gem_flush(struct drm_device *dev, |
| 1853 | uint32_t invalidate_domains, |
| 1854 | uint32_t flush_domains) |
| 1855 | { |
| 1856 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1857 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 1858 | drm_agp_chipset_flush(dev); |
| 1859 | dev_priv->render_ring.flush(dev, &dev_priv->render_ring, |
| 1860 | invalidate_domains, |
| 1861 | flush_domains); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 1862 | |
| 1863 | if (HAS_BSD(dev)) |
| 1864 | dev_priv->bsd_ring.flush(dev, &dev_priv->bsd_ring, |
| 1865 | invalidate_domains, |
| 1866 | flush_domains); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 1867 | } |
| 1868 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1869 | static void |
| 1870 | i915_gem_flush_ring(struct drm_device *dev, |
| 1871 | uint32_t invalidate_domains, |
| 1872 | uint32_t flush_domains, |
| 1873 | struct intel_ring_buffer *ring) |
| 1874 | { |
| 1875 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 1876 | drm_agp_chipset_flush(dev); |
| 1877 | ring->flush(dev, ring, |
| 1878 | invalidate_domains, |
| 1879 | flush_domains); |
| 1880 | } |
| 1881 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1882 | /** |
| 1883 | * Ensures that all rendering to the object has completed and the object is |
| 1884 | * safe to unbind from the GTT or access from the CPU. |
| 1885 | */ |
| 1886 | static int |
| 1887 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) |
| 1888 | { |
| 1889 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1890 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1891 | int ret; |
| 1892 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1893 | /* This function only exists to support waiting for existing rendering, |
| 1894 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1895 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1896 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1897 | |
| 1898 | /* If there is rendering queued on the buffer being evicted, wait for |
| 1899 | * it. |
| 1900 | */ |
| 1901 | if (obj_priv->active) { |
| 1902 | #if WATCH_BUF |
| 1903 | DRM_INFO("%s: object %p wait for seqno %08x\n", |
| 1904 | __func__, obj, obj_priv->last_rendering_seqno); |
| 1905 | #endif |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 1906 | ret = i915_wait_request(dev, |
| 1907 | obj_priv->last_rendering_seqno, obj_priv->ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1908 | if (ret != 0) |
| 1909 | return ret; |
| 1910 | } |
| 1911 | |
| 1912 | return 0; |
| 1913 | } |
| 1914 | |
| 1915 | /** |
| 1916 | * Unbinds an object from the GTT aperture. |
| 1917 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1918 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1919 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 1920 | { |
| 1921 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 4a87b8c | 2010-02-19 11:51:57 +0100 | [diff] [blame] | 1922 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 1923 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1924 | int ret = 0; |
| 1925 | |
| 1926 | #if WATCH_BUF |
| 1927 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); |
| 1928 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); |
| 1929 | #endif |
| 1930 | if (obj_priv->gtt_space == NULL) |
| 1931 | return 0; |
| 1932 | |
| 1933 | if (obj_priv->pin_count != 0) { |
| 1934 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 1935 | return -EINVAL; |
| 1936 | } |
| 1937 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 1938 | /* blow away mappings if mapped through GTT */ |
| 1939 | i915_gem_release_mmap(obj); |
| 1940 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1941 | /* Move the object to the CPU domain to ensure that |
| 1942 | * any possible CPU writes while it's not in the GTT |
| 1943 | * are flushed when we go to remap it. This will |
| 1944 | * also ensure that all pending GPU writes are finished |
| 1945 | * before we unbind. |
| 1946 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1947 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1948 | if (ret) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1949 | if (ret != -ERESTARTSYS) |
| 1950 | DRM_ERROR("set_domain failed: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1951 | return ret; |
| 1952 | } |
| 1953 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 1954 | BUG_ON(obj_priv->active); |
| 1955 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 1956 | /* release the fence reg _after_ flushing */ |
| 1957 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 1958 | i915_gem_clear_fence_reg(obj); |
| 1959 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1960 | if (obj_priv->agp_mem != NULL) { |
| 1961 | drm_unbind_agp(obj_priv->agp_mem); |
| 1962 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
| 1963 | obj_priv->agp_mem = NULL; |
| 1964 | } |
| 1965 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1966 | i915_gem_object_put_pages(obj); |
Chris Wilson | a32808c | 2009-09-20 21:29:47 +0100 | [diff] [blame] | 1967 | BUG_ON(obj_priv->pages_refcount); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1968 | |
| 1969 | if (obj_priv->gtt_space) { |
| 1970 | atomic_dec(&dev->gtt_count); |
| 1971 | atomic_sub(obj->size, &dev->gtt_memory); |
| 1972 | |
| 1973 | drm_mm_put_block(obj_priv->gtt_space); |
| 1974 | obj_priv->gtt_space = NULL; |
| 1975 | } |
| 1976 | |
| 1977 | /* Remove ourselves from the LRU list if present. */ |
Daniel Vetter | 4a87b8c | 2010-02-19 11:51:57 +0100 | [diff] [blame] | 1978 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1979 | if (!list_empty(&obj_priv->list)) |
| 1980 | list_del_init(&obj_priv->list); |
Daniel Vetter | 4a87b8c | 2010-02-19 11:51:57 +0100 | [diff] [blame] | 1981 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1982 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1983 | if (i915_gem_object_is_purgeable(obj_priv)) |
| 1984 | i915_gem_object_truncate(obj); |
| 1985 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1986 | trace_i915_gem_object_unbind(obj); |
| 1987 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1988 | return 0; |
| 1989 | } |
| 1990 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 1991 | static struct drm_gem_object * |
| 1992 | i915_gem_find_inactive_object(struct drm_device *dev, int min_size) |
| 1993 | { |
| 1994 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1995 | struct drm_i915_gem_object *obj_priv; |
| 1996 | struct drm_gem_object *best = NULL; |
| 1997 | struct drm_gem_object *first = NULL; |
| 1998 | |
| 1999 | /* Try to find the smallest clean object */ |
| 2000 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 2001 | struct drm_gem_object *obj = &obj_priv->base; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2002 | if (obj->size >= min_size) { |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2003 | if ((!obj_priv->dirty || |
| 2004 | i915_gem_object_is_purgeable(obj_priv)) && |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2005 | (!best || obj->size < best->size)) { |
| 2006 | best = obj; |
| 2007 | if (best->size == min_size) |
| 2008 | return best; |
| 2009 | } |
| 2010 | if (!first) |
| 2011 | first = obj; |
| 2012 | } |
| 2013 | } |
| 2014 | |
| 2015 | return best ? best : first; |
| 2016 | } |
| 2017 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2018 | static int |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2019 | i915_gpu_idle(struct drm_device *dev) |
| 2020 | { |
| 2021 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2022 | bool lists_empty; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2023 | uint32_t seqno1, seqno2; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2024 | int ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2025 | |
| 2026 | spin_lock(&dev_priv->mm.active_list_lock); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2027 | lists_empty = (list_empty(&dev_priv->mm.flushing_list) && |
| 2028 | list_empty(&dev_priv->render_ring.active_list) && |
| 2029 | (!HAS_BSD(dev) || |
| 2030 | list_empty(&dev_priv->bsd_ring.active_list))); |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2031 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 2032 | |
| 2033 | if (lists_empty) |
| 2034 | return 0; |
| 2035 | |
| 2036 | /* Flush everything onto the inactive list. */ |
| 2037 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2038 | seqno1 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2039 | &dev_priv->render_ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2040 | if (seqno1 == 0) |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2041 | return -ENOMEM; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2042 | ret = i915_wait_request(dev, seqno1, &dev_priv->render_ring); |
| 2043 | |
| 2044 | if (HAS_BSD(dev)) { |
| 2045 | seqno2 = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS, |
| 2046 | &dev_priv->bsd_ring); |
| 2047 | if (seqno2 == 0) |
| 2048 | return -ENOMEM; |
| 2049 | |
| 2050 | ret = i915_wait_request(dev, seqno2, &dev_priv->bsd_ring); |
| 2051 | if (ret) |
| 2052 | return ret; |
| 2053 | } |
| 2054 | |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2055 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2056 | return ret; |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2057 | } |
| 2058 | |
| 2059 | static int |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2060 | i915_gem_evict_everything(struct drm_device *dev) |
| 2061 | { |
| 2062 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2063 | int ret; |
| 2064 | bool lists_empty; |
| 2065 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2066 | spin_lock(&dev_priv->mm.active_list_lock); |
| 2067 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && |
| 2068 | list_empty(&dev_priv->mm.flushing_list) && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2069 | list_empty(&dev_priv->render_ring.active_list) && |
| 2070 | (!HAS_BSD(dev) |
| 2071 | || list_empty(&dev_priv->bsd_ring.active_list))); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2072 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 2073 | |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2074 | if (lists_empty) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2075 | return -ENOSPC; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2076 | |
| 2077 | /* Flush everything (on to the inactive lists) and evict */ |
Daniel Vetter | 4df2faf | 2010-02-19 11:52:00 +0100 | [diff] [blame] | 2078 | ret = i915_gpu_idle(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2079 | if (ret) |
| 2080 | return ret; |
| 2081 | |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 2082 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 2083 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 2084 | ret = i915_gem_evict_from_inactive_list(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2085 | if (ret) |
| 2086 | return ret; |
| 2087 | |
| 2088 | spin_lock(&dev_priv->mm.active_list_lock); |
| 2089 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && |
| 2090 | list_empty(&dev_priv->mm.flushing_list) && |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2091 | list_empty(&dev_priv->render_ring.active_list) && |
| 2092 | (!HAS_BSD(dev) |
| 2093 | || list_empty(&dev_priv->bsd_ring.active_list))); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2094 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 2095 | BUG_ON(!lists_empty); |
| 2096 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2097 | return 0; |
| 2098 | } |
| 2099 | |
| 2100 | static int |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2101 | i915_gem_evict_something(struct drm_device *dev, int min_size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2102 | { |
| 2103 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2104 | struct drm_gem_object *obj; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2105 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2106 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2107 | struct intel_ring_buffer *render_ring = &dev_priv->render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2108 | struct intel_ring_buffer *bsd_ring = &dev_priv->bsd_ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2109 | for (;;) { |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2110 | i915_gem_retire_requests(dev, render_ring); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2111 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2112 | if (HAS_BSD(dev)) |
| 2113 | i915_gem_retire_requests(dev, bsd_ring); |
| 2114 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2115 | /* If there's an inactive buffer available now, grab it |
| 2116 | * and be done. |
| 2117 | */ |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2118 | obj = i915_gem_find_inactive_object(dev, min_size); |
| 2119 | if (obj) { |
| 2120 | struct drm_i915_gem_object *obj_priv; |
| 2121 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2122 | #if WATCH_LRU |
| 2123 | DRM_INFO("%s: evicting %p\n", __func__, obj); |
| 2124 | #endif |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2125 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2126 | BUG_ON(obj_priv->pin_count != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2127 | BUG_ON(obj_priv->active); |
| 2128 | |
| 2129 | /* Wait on the rendering and unbind the buffer. */ |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2130 | return i915_gem_object_unbind(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2131 | } |
| 2132 | |
| 2133 | /* If we didn't get anything, but the ring is still processing |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2134 | * things, wait for the next to finish and hopefully leave us |
| 2135 | * a buffer to evict. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2136 | */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2137 | if (!list_empty(&render_ring->request_list)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2138 | struct drm_i915_gem_request *request; |
| 2139 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2140 | request = list_first_entry(&render_ring->request_list, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2141 | struct drm_i915_gem_request, |
| 2142 | list); |
| 2143 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2144 | ret = i915_wait_request(dev, |
| 2145 | request->seqno, request->ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2146 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2147 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2148 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2149 | continue; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2150 | } |
| 2151 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 2152 | if (HAS_BSD(dev) && !list_empty(&bsd_ring->request_list)) { |
| 2153 | struct drm_i915_gem_request *request; |
| 2154 | |
| 2155 | request = list_first_entry(&bsd_ring->request_list, |
| 2156 | struct drm_i915_gem_request, |
| 2157 | list); |
| 2158 | |
| 2159 | ret = i915_wait_request(dev, |
| 2160 | request->seqno, request->ring); |
| 2161 | if (ret) |
| 2162 | return ret; |
| 2163 | |
| 2164 | continue; |
| 2165 | } |
| 2166 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2167 | /* If we didn't have anything on the request list but there |
| 2168 | * are buffers awaiting a flush, emit one and try again. |
| 2169 | * When we wait on it, those buffers waiting for that flush |
| 2170 | * will get moved to inactive. |
| 2171 | */ |
| 2172 | if (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2173 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2174 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2175 | /* Find an object that we can immediately reuse */ |
| 2176 | list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 2177 | obj = &obj_priv->base; |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2178 | if (obj->size >= min_size) |
| 2179 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2180 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2181 | obj = NULL; |
| 2182 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2183 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2184 | if (obj != NULL) { |
| 2185 | uint32_t seqno; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2186 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2187 | i915_gem_flush_ring(dev, |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2188 | obj->write_domain, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2189 | obj->write_domain, |
| 2190 | obj_priv->ring); |
| 2191 | seqno = i915_add_request(dev, NULL, |
| 2192 | obj->write_domain, |
| 2193 | obj_priv->ring); |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2194 | if (seqno == 0) |
| 2195 | return -ENOMEM; |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2196 | continue; |
| 2197 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2198 | } |
| 2199 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2200 | /* If we didn't do any of the above, there's no single buffer |
| 2201 | * large enough to swap out for the new one, so just evict |
| 2202 | * everything and start again. (This should be rare.) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2203 | */ |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2204 | if (!list_empty (&dev_priv->mm.inactive_list)) |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 2205 | return i915_gem_evict_from_inactive_list(dev); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2206 | else |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2207 | return i915_gem_evict_everything(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2208 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2209 | } |
| 2210 | |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 2211 | int |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2212 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 2213 | gfp_t gfpmask) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2214 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2215 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2216 | int page_count, i; |
| 2217 | struct address_space *mapping; |
| 2218 | struct inode *inode; |
| 2219 | struct page *page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2220 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 2221 | BUG_ON(obj_priv->pages_refcount |
| 2222 | == DRM_I915_GEM_OBJECT_MAX_PAGES_REFCOUNT); |
| 2223 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2224 | if (obj_priv->pages_refcount++ != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2225 | return 0; |
| 2226 | |
| 2227 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2228 | * at this point until we release them. |
| 2229 | */ |
| 2230 | page_count = obj->size / PAGE_SIZE; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2231 | BUG_ON(obj_priv->pages != NULL); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 2232 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2233 | if (obj_priv->pages == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2234 | obj_priv->pages_refcount--; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2235 | return -ENOMEM; |
| 2236 | } |
| 2237 | |
| 2238 | inode = obj->filp->f_path.dentry->d_inode; |
| 2239 | mapping = inode->i_mapping; |
| 2240 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2241 | page = read_cache_page_gfp(mapping, i, |
Linus Torvalds | 985b823 | 2010-07-02 10:04:42 +1000 | [diff] [blame] | 2242 | GFP_HIGHUSER | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2243 | __GFP_COLD | |
| 2244 | gfpmask); |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2245 | if (IS_ERR(page)) |
| 2246 | goto err_pages; |
| 2247 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2248 | obj_priv->pages[i] = page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2249 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2250 | |
| 2251 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 2252 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2253 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2254 | return 0; |
Chris Wilson | 1f2b101 | 2010-03-12 19:52:55 +0000 | [diff] [blame] | 2255 | |
| 2256 | err_pages: |
| 2257 | while (i--) |
| 2258 | page_cache_release(obj_priv->pages[i]); |
| 2259 | |
| 2260 | drm_free_large(obj_priv->pages); |
| 2261 | obj_priv->pages = NULL; |
| 2262 | obj_priv->pages_refcount--; |
| 2263 | return PTR_ERR(page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2264 | } |
| 2265 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2266 | static void sandybridge_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2267 | { |
| 2268 | struct drm_gem_object *obj = reg->obj; |
| 2269 | struct drm_device *dev = obj->dev; |
| 2270 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2271 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2272 | int regnum = obj_priv->fence_reg; |
| 2273 | uint64_t val; |
| 2274 | |
| 2275 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2276 | 0xfffff000) << 32; |
| 2277 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2278 | val |= (uint64_t)((obj_priv->stride / 128) - 1) << |
| 2279 | SANDYBRIDGE_FENCE_PITCH_SHIFT; |
| 2280 | |
| 2281 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2282 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2283 | val |= I965_FENCE_REG_VALID; |
| 2284 | |
| 2285 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + (regnum * 8), val); |
| 2286 | } |
| 2287 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2288 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2289 | { |
| 2290 | struct drm_gem_object *obj = reg->obj; |
| 2291 | struct drm_device *dev = obj->dev; |
| 2292 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2293 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2294 | int regnum = obj_priv->fence_reg; |
| 2295 | uint64_t val; |
| 2296 | |
| 2297 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2298 | 0xfffff000) << 32; |
| 2299 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2300 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2301 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2302 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2303 | val |= I965_FENCE_REG_VALID; |
| 2304 | |
| 2305 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 2306 | } |
| 2307 | |
| 2308 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2309 | { |
| 2310 | struct drm_gem_object *obj = reg->obj; |
| 2311 | struct drm_device *dev = obj->dev; |
| 2312 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2313 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2314 | int regnum = obj_priv->fence_reg; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2315 | int tile_width; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2316 | uint32_t fence_reg, val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2317 | uint32_t pitch_val; |
| 2318 | |
| 2319 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2320 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Linus Torvalds | f06da26 | 2009-02-09 08:57:29 -0800 | [diff] [blame] | 2321 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2322 | __func__, obj_priv->gtt_offset, obj->size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2323 | return; |
| 2324 | } |
| 2325 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2326 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2327 | HAS_128_BYTE_Y_TILING(dev)) |
| 2328 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2329 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2330 | tile_width = 512; |
| 2331 | |
| 2332 | /* Note: pitch better be a power of two tile widths */ |
| 2333 | pitch_val = obj_priv->stride / tile_width; |
| 2334 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2335 | |
Daniel Vetter | c36a2a6 | 2010-04-17 15:12:03 +0200 | [diff] [blame] | 2336 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2337 | HAS_128_BYTE_Y_TILING(dev)) |
| 2338 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2339 | else |
| 2340 | WARN_ON(pitch_val > I915_FENCE_MAX_PITCH_VAL); |
| 2341 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2342 | val = obj_priv->gtt_offset; |
| 2343 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2344 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2345 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 2346 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2347 | val |= I830_FENCE_REG_VALID; |
| 2348 | |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2349 | if (regnum < 8) |
| 2350 | fence_reg = FENCE_REG_830_0 + (regnum * 4); |
| 2351 | else |
| 2352 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); |
| 2353 | I915_WRITE(fence_reg, val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2354 | } |
| 2355 | |
| 2356 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2357 | { |
| 2358 | struct drm_gem_object *obj = reg->obj; |
| 2359 | struct drm_device *dev = obj->dev; |
| 2360 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2361 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2362 | int regnum = obj_priv->fence_reg; |
| 2363 | uint32_t val; |
| 2364 | uint32_t pitch_val; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2365 | uint32_t fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2366 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2367 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2368 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2369 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2370 | __func__, obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2371 | return; |
| 2372 | } |
| 2373 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2374 | pitch_val = obj_priv->stride / 128; |
| 2375 | pitch_val = ffs(pitch_val) - 1; |
| 2376 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2377 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2378 | val = obj_priv->gtt_offset; |
| 2379 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2380 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2381 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
| 2382 | WARN_ON(fence_size_bits & ~0x00000f00); |
| 2383 | val |= fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2384 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2385 | val |= I830_FENCE_REG_VALID; |
| 2386 | |
| 2387 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2388 | } |
| 2389 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2390 | static int i915_find_fence_reg(struct drm_device *dev) |
| 2391 | { |
| 2392 | struct drm_i915_fence_reg *reg = NULL; |
| 2393 | struct drm_i915_gem_object *obj_priv = NULL; |
| 2394 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 2395 | struct drm_gem_object *obj = NULL; |
| 2396 | int i, avail, ret; |
| 2397 | |
| 2398 | /* First try to find a free reg */ |
| 2399 | avail = 0; |
| 2400 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2401 | reg = &dev_priv->fence_regs[i]; |
| 2402 | if (!reg->obj) |
| 2403 | return i; |
| 2404 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2405 | obj_priv = to_intel_bo(reg->obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2406 | if (!obj_priv->pin_count) |
| 2407 | avail++; |
| 2408 | } |
| 2409 | |
| 2410 | if (avail == 0) |
| 2411 | return -ENOSPC; |
| 2412 | |
| 2413 | /* None available, try to steal one or wait for a user to finish */ |
| 2414 | i = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2415 | list_for_each_entry(reg, &dev_priv->mm.fence_list, |
| 2416 | lru_list) { |
| 2417 | obj = reg->obj; |
| 2418 | obj_priv = to_intel_bo(obj); |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2419 | |
| 2420 | if (obj_priv->pin_count) |
| 2421 | continue; |
| 2422 | |
| 2423 | /* found one! */ |
| 2424 | i = obj_priv->fence_reg; |
| 2425 | break; |
| 2426 | } |
| 2427 | |
| 2428 | BUG_ON(i == I915_FENCE_REG_NONE); |
| 2429 | |
| 2430 | /* We only have a reference on obj from the active list. put_fence_reg |
| 2431 | * might drop that one, causing a use-after-free in it. So hold a |
| 2432 | * private reference to obj like the other callers of put_fence_reg |
| 2433 | * (set_tiling ioctl) do. */ |
| 2434 | drm_gem_object_reference(obj); |
| 2435 | ret = i915_gem_object_put_fence_reg(obj); |
| 2436 | drm_gem_object_unreference(obj); |
| 2437 | if (ret != 0) |
| 2438 | return ret; |
| 2439 | |
| 2440 | return i; |
| 2441 | } |
| 2442 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2443 | /** |
| 2444 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2445 | * @obj: object to map through a fence reg |
| 2446 | * |
| 2447 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2448 | * to them without having to worry about swizzling if the object is tiled. |
| 2449 | * |
| 2450 | * This function walks the fence regs looking for a free one for @obj, |
| 2451 | * stealing one if it can't find any. |
| 2452 | * |
| 2453 | * It then sets up the reg based on the object's properties: address, pitch |
| 2454 | * and tiling format. |
| 2455 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2456 | int |
| 2457 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2458 | { |
| 2459 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2460 | struct drm_i915_private *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2461 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2462 | struct drm_i915_fence_reg *reg = NULL; |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2463 | int ret; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2464 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2465 | /* Just update our place in the LRU if our fence is getting used. */ |
| 2466 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2467 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
| 2468 | list_move_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2469 | return 0; |
| 2470 | } |
| 2471 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2472 | switch (obj_priv->tiling_mode) { |
| 2473 | case I915_TILING_NONE: |
| 2474 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2475 | break; |
| 2476 | case I915_TILING_X: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2477 | if (!obj_priv->stride) |
| 2478 | return -EINVAL; |
| 2479 | WARN((obj_priv->stride & (512 - 1)), |
| 2480 | "object 0x%08x is X tiled but has non-512B pitch\n", |
| 2481 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2482 | break; |
| 2483 | case I915_TILING_Y: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2484 | if (!obj_priv->stride) |
| 2485 | return -EINVAL; |
| 2486 | WARN((obj_priv->stride & (128 - 1)), |
| 2487 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
| 2488 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2489 | break; |
| 2490 | } |
| 2491 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2492 | ret = i915_find_fence_reg(dev); |
| 2493 | if (ret < 0) |
| 2494 | return ret; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2495 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2496 | obj_priv->fence_reg = ret; |
| 2497 | reg = &dev_priv->fence_regs[obj_priv->fence_reg]; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2498 | list_add_tail(®->lru_list, &dev_priv->mm.fence_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2499 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2500 | reg->obj = obj; |
| 2501 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2502 | if (IS_GEN6(dev)) |
| 2503 | sandybridge_write_fence_reg(reg); |
| 2504 | else if (IS_I965G(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2505 | i965_write_fence_reg(reg); |
| 2506 | else if (IS_I9XX(dev)) |
| 2507 | i915_write_fence_reg(reg); |
| 2508 | else |
| 2509 | i830_write_fence_reg(reg); |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2510 | |
Daniel Vetter | ae3db24 | 2010-02-19 11:51:58 +0100 | [diff] [blame] | 2511 | trace_i915_gem_object_get_fence(obj, obj_priv->fence_reg, |
| 2512 | obj_priv->tiling_mode); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2513 | |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2514 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2515 | } |
| 2516 | |
| 2517 | /** |
| 2518 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2519 | * @obj: object to clear |
| 2520 | * |
| 2521 | * Zeroes out the fence register itself and clears out the associated |
| 2522 | * data structures in dev_priv and obj_priv. |
| 2523 | */ |
| 2524 | static void |
| 2525 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 2526 | { |
| 2527 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2528 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2529 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2530 | struct drm_i915_fence_reg *reg = |
| 2531 | &dev_priv->fence_regs[obj_priv->fence_reg]; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2532 | |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2533 | if (IS_GEN6(dev)) { |
| 2534 | I915_WRITE64(FENCE_REG_SANDYBRIDGE_0 + |
| 2535 | (obj_priv->fence_reg * 8), 0); |
| 2536 | } else if (IS_I965G(dev)) { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2537 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
Eric Anholt | 4e901fd | 2009-10-26 16:44:17 -0700 | [diff] [blame] | 2538 | } else { |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2539 | uint32_t fence_reg; |
| 2540 | |
| 2541 | if (obj_priv->fence_reg < 8) |
| 2542 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
| 2543 | else |
| 2544 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - |
| 2545 | 8) * 4; |
| 2546 | |
| 2547 | I915_WRITE(fence_reg, 0); |
| 2548 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2549 | |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2550 | reg->obj = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2551 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 2552 | list_del_init(®->lru_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2553 | } |
| 2554 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2555 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2556 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2557 | * to the buffer to finish, and then resets the fence register. |
| 2558 | * @obj: tiled object holding a fence register. |
| 2559 | * |
| 2560 | * Zeroes out the fence register itself and clears out the associated |
| 2561 | * data structures in dev_priv and obj_priv. |
| 2562 | */ |
| 2563 | int |
| 2564 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) |
| 2565 | { |
| 2566 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2567 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2568 | |
| 2569 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) |
| 2570 | return 0; |
| 2571 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2572 | /* If we've changed tiling, GTT-mappings of the object |
| 2573 | * need to re-fault to ensure that the correct fence register |
| 2574 | * setup is in place. |
| 2575 | */ |
| 2576 | i915_gem_release_mmap(obj); |
| 2577 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2578 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2579 | * therefore we must wait for any outstanding access to complete |
| 2580 | * before clearing the fence. |
| 2581 | */ |
| 2582 | if (!IS_I965G(dev)) { |
| 2583 | int ret; |
| 2584 | |
| 2585 | i915_gem_object_flush_gpu_write_domain(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2586 | ret = i915_gem_object_wait_rendering(obj); |
| 2587 | if (ret != 0) |
| 2588 | return ret; |
| 2589 | } |
| 2590 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2591 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2592 | i915_gem_clear_fence_reg (obj); |
| 2593 | |
| 2594 | return 0; |
| 2595 | } |
| 2596 | |
| 2597 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2598 | * Finds free space in the GTT aperture and binds the object there. |
| 2599 | */ |
| 2600 | static int |
| 2601 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) |
| 2602 | { |
| 2603 | struct drm_device *dev = obj->dev; |
| 2604 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2605 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2606 | struct drm_mm_node *free_space; |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2607 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2608 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2609 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 2610 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2611 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2612 | return -EINVAL; |
| 2613 | } |
| 2614 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2615 | if (alignment == 0) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2616 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2617 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2618 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2619 | return -EINVAL; |
| 2620 | } |
| 2621 | |
Chris Wilson | 654fc60 | 2010-05-27 13:18:21 +0100 | [diff] [blame] | 2622 | /* If the object is bigger than the entire aperture, reject it early |
| 2623 | * before evicting everything in a vain attempt to find space. |
| 2624 | */ |
| 2625 | if (obj->size > dev->gtt_total) { |
| 2626 | DRM_ERROR("Attempting to bind an object larger than the aperture\n"); |
| 2627 | return -E2BIG; |
| 2628 | } |
| 2629 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2630 | search_free: |
| 2631 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 2632 | obj->size, alignment, 0); |
| 2633 | if (free_space != NULL) { |
| 2634 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, |
| 2635 | alignment); |
| 2636 | if (obj_priv->gtt_space != NULL) { |
| 2637 | obj_priv->gtt_space->private = obj; |
| 2638 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
| 2639 | } |
| 2640 | } |
| 2641 | if (obj_priv->gtt_space == NULL) { |
| 2642 | /* If the gtt is empty and we're still having trouble |
| 2643 | * fitting our object in, we're out of memory. |
| 2644 | */ |
| 2645 | #if WATCH_LRU |
| 2646 | DRM_INFO("%s: GTT full, evicting something\n", __func__); |
| 2647 | #endif |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2648 | ret = i915_gem_evict_something(dev, obj->size); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2649 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2650 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2651 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2652 | goto search_free; |
| 2653 | } |
| 2654 | |
| 2655 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 2656 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2657 | obj->size, obj_priv->gtt_offset); |
| 2658 | #endif |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2659 | ret = i915_gem_object_get_pages(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2660 | if (ret) { |
| 2661 | drm_mm_put_block(obj_priv->gtt_space); |
| 2662 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2663 | |
| 2664 | if (ret == -ENOMEM) { |
| 2665 | /* first try to clear up some space from the GTT */ |
| 2666 | ret = i915_gem_evict_something(dev, obj->size); |
| 2667 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2668 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2669 | if (gfpmask) { |
| 2670 | gfpmask = 0; |
| 2671 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2672 | } |
| 2673 | |
| 2674 | return ret; |
| 2675 | } |
| 2676 | |
| 2677 | goto search_free; |
| 2678 | } |
| 2679 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2680 | return ret; |
| 2681 | } |
| 2682 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2683 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 2684 | * into the GTT. |
| 2685 | */ |
| 2686 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2687 | obj_priv->pages, |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2688 | obj->size >> PAGE_SHIFT, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2689 | obj_priv->gtt_offset, |
| 2690 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2691 | if (obj_priv->agp_mem == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2692 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2693 | drm_mm_put_block(obj_priv->gtt_space); |
| 2694 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2695 | |
| 2696 | ret = i915_gem_evict_something(dev, obj->size); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2697 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2698 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2699 | |
| 2700 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2701 | } |
| 2702 | atomic_inc(&dev->gtt_count); |
| 2703 | atomic_add(obj->size, &dev->gtt_memory); |
| 2704 | |
| 2705 | /* Assert that the object is not currently in any GPU domain. As it |
| 2706 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2707 | * a GPU cache |
| 2708 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 2709 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
| 2710 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2711 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2712 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
| 2713 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2714 | return 0; |
| 2715 | } |
| 2716 | |
| 2717 | void |
| 2718 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 2719 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2720 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2721 | |
| 2722 | /* If we don't have a page list set up, then we're not pinned |
| 2723 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2724 | * again at bind time. |
| 2725 | */ |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2726 | if (obj_priv->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2727 | return; |
| 2728 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2729 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2730 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2731 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2732 | } |
| 2733 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2734 | /** Flushes any GPU write domain for the object if it's dirty. */ |
| 2735 | static void |
| 2736 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) |
| 2737 | { |
| 2738 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2739 | uint32_t old_write_domain; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2740 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2741 | |
| 2742 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
| 2743 | return; |
| 2744 | |
| 2745 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2746 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2747 | i915_gem_flush(dev, 0, obj->write_domain); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2748 | (void) i915_add_request(dev, NULL, obj->write_domain, obj_priv->ring); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 2749 | BUG_ON(obj->write_domain); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2750 | |
| 2751 | trace_i915_gem_object_change_domain(obj, |
| 2752 | obj->read_domains, |
| 2753 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2754 | } |
| 2755 | |
| 2756 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2757 | static void |
| 2758 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 2759 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2760 | uint32_t old_write_domain; |
| 2761 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2762 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 2763 | return; |
| 2764 | |
| 2765 | /* No actual flushing is required for the GTT write domain. Writes |
| 2766 | * to it immediately go to main memory as far as we know, so there's |
| 2767 | * no chipset flush. It also doesn't land in render cache. |
| 2768 | */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2769 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2770 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2771 | |
| 2772 | trace_i915_gem_object_change_domain(obj, |
| 2773 | obj->read_domains, |
| 2774 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2775 | } |
| 2776 | |
| 2777 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2778 | static void |
| 2779 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 2780 | { |
| 2781 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2782 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2783 | |
| 2784 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 2785 | return; |
| 2786 | |
| 2787 | i915_gem_clflush_object(obj); |
| 2788 | drm_agp_chipset_flush(dev); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2789 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2790 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2791 | |
| 2792 | trace_i915_gem_object_change_domain(obj, |
| 2793 | obj->read_domains, |
| 2794 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2795 | } |
| 2796 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2797 | void |
| 2798 | i915_gem_object_flush_write_domain(struct drm_gem_object *obj) |
| 2799 | { |
| 2800 | switch (obj->write_domain) { |
| 2801 | case I915_GEM_DOMAIN_GTT: |
| 2802 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2803 | break; |
| 2804 | case I915_GEM_DOMAIN_CPU: |
| 2805 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2806 | break; |
| 2807 | default: |
| 2808 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2809 | break; |
| 2810 | } |
| 2811 | } |
| 2812 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2813 | /** |
| 2814 | * Moves a single object to the GTT read, and possibly write domain. |
| 2815 | * |
| 2816 | * This function returns when the move is complete, including waiting on |
| 2817 | * flushes to occur. |
| 2818 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2819 | int |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2820 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 2821 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2822 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2823 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2824 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2825 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2826 | /* Not valid to be called on unbound objects. */ |
| 2827 | if (obj_priv->gtt_space == NULL) |
| 2828 | return -EINVAL; |
| 2829 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2830 | i915_gem_object_flush_gpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2831 | /* Wait on any GPU rendering and flushing to occur. */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2832 | ret = i915_gem_object_wait_rendering(obj); |
| 2833 | if (ret != 0) |
| 2834 | return ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2835 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2836 | old_write_domain = obj->write_domain; |
| 2837 | old_read_domains = obj->read_domains; |
| 2838 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2839 | /* If we're writing through the GTT domain, then CPU and GPU caches |
| 2840 | * will need to be invalidated at next use. |
| 2841 | */ |
| 2842 | if (write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2843 | obj->read_domains &= I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2844 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2845 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2846 | |
| 2847 | /* It should now be out of any other write domains, and we can update |
| 2848 | * the domain values for our changes. |
| 2849 | */ |
| 2850 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2851 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2852 | if (write) { |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2853 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2854 | obj_priv->dirty = 1; |
| 2855 | } |
| 2856 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2857 | trace_i915_gem_object_change_domain(obj, |
| 2858 | old_read_domains, |
| 2859 | old_write_domain); |
| 2860 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2861 | return 0; |
| 2862 | } |
| 2863 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2864 | /* |
| 2865 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2866 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2867 | */ |
| 2868 | int |
| 2869 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj) |
| 2870 | { |
| 2871 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 2872 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2873 | uint32_t old_write_domain, old_read_domains; |
| 2874 | int ret; |
| 2875 | |
| 2876 | /* Not valid to be called on unbound objects. */ |
| 2877 | if (obj_priv->gtt_space == NULL) |
| 2878 | return -EINVAL; |
| 2879 | |
| 2880 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2881 | |
| 2882 | /* Wait on any GPU rendering and flushing to occur. */ |
| 2883 | if (obj_priv->active) { |
| 2884 | #if WATCH_BUF |
| 2885 | DRM_INFO("%s: object %p wait for seqno %08x\n", |
| 2886 | __func__, obj, obj_priv->last_rendering_seqno); |
| 2887 | #endif |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 2888 | ret = i915_do_wait_request(dev, |
| 2889 | obj_priv->last_rendering_seqno, |
| 2890 | 0, |
| 2891 | obj_priv->ring); |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2892 | if (ret != 0) |
| 2893 | return ret; |
| 2894 | } |
| 2895 | |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2896 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2897 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2898 | old_write_domain = obj->write_domain; |
| 2899 | old_read_domains = obj->read_domains; |
| 2900 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2901 | /* It should now be out of any other write domains, and we can update |
| 2902 | * the domain values for our changes. |
| 2903 | */ |
| 2904 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
Chris Wilson | b118c1e | 2010-05-27 13:18:14 +0100 | [diff] [blame] | 2905 | obj->read_domains = I915_GEM_DOMAIN_GTT; |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2906 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
| 2907 | obj_priv->dirty = 1; |
| 2908 | |
| 2909 | trace_i915_gem_object_change_domain(obj, |
| 2910 | old_read_domains, |
| 2911 | old_write_domain); |
| 2912 | |
| 2913 | return 0; |
| 2914 | } |
| 2915 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2916 | /** |
| 2917 | * Moves a single object to the CPU read, and possibly write domain. |
| 2918 | * |
| 2919 | * This function returns when the move is complete, including waiting on |
| 2920 | * flushes to occur. |
| 2921 | */ |
| 2922 | static int |
| 2923 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 2924 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2925 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2926 | int ret; |
| 2927 | |
| 2928 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2929 | /* Wait on any GPU rendering and flushing to occur. */ |
| 2930 | ret = i915_gem_object_wait_rendering(obj); |
| 2931 | if (ret != 0) |
| 2932 | return ret; |
| 2933 | |
| 2934 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2935 | |
| 2936 | /* If we have a partially-valid cache of the object in the CPU, |
| 2937 | * finish invalidating it and free the per-page flags. |
| 2938 | */ |
| 2939 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 2940 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2941 | old_write_domain = obj->write_domain; |
| 2942 | old_read_domains = obj->read_domains; |
| 2943 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2944 | /* Flush the CPU cache if it's still invalid. */ |
| 2945 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 2946 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2947 | |
| 2948 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 2949 | } |
| 2950 | |
| 2951 | /* It should now be out of any other write domains, and we can update |
| 2952 | * the domain values for our changes. |
| 2953 | */ |
| 2954 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 2955 | |
| 2956 | /* If we're writing through the CPU, then the GPU read domains will |
| 2957 | * need to be invalidated at next use. |
| 2958 | */ |
| 2959 | if (write) { |
| 2960 | obj->read_domains &= I915_GEM_DOMAIN_CPU; |
| 2961 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2962 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2963 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2964 | trace_i915_gem_object_change_domain(obj, |
| 2965 | old_read_domains, |
| 2966 | old_write_domain); |
| 2967 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2968 | return 0; |
| 2969 | } |
| 2970 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2971 | /* |
| 2972 | * Set the next domain for the specified object. This |
| 2973 | * may not actually perform the necessary flushing/invaliding though, |
| 2974 | * as that may want to be batched with other set_domain operations |
| 2975 | * |
| 2976 | * This is (we hope) the only really tricky part of gem. The goal |
| 2977 | * is fairly simple -- track which caches hold bits of the object |
| 2978 | * and make sure they remain coherent. A few concrete examples may |
| 2979 | * help to explain how it works. For shorthand, we use the notation |
| 2980 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 2981 | * a pair of read and write domain masks. |
| 2982 | * |
| 2983 | * Case 1: the batch buffer |
| 2984 | * |
| 2985 | * 1. Allocated |
| 2986 | * 2. Written by CPU |
| 2987 | * 3. Mapped to GTT |
| 2988 | * 4. Read by GPU |
| 2989 | * 5. Unmapped from GTT |
| 2990 | * 6. Freed |
| 2991 | * |
| 2992 | * Let's take these a step at a time |
| 2993 | * |
| 2994 | * 1. Allocated |
| 2995 | * Pages allocated from the kernel may still have |
| 2996 | * cache contents, so we set them to (CPU, CPU) always. |
| 2997 | * 2. Written by CPU (using pwrite) |
| 2998 | * The pwrite function calls set_domain (CPU, CPU) and |
| 2999 | * this function does nothing (as nothing changes) |
| 3000 | * 3. Mapped by GTT |
| 3001 | * This function asserts that the object is not |
| 3002 | * currently in any GPU-based read or write domains |
| 3003 | * 4. Read by GPU |
| 3004 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 3005 | * As write_domain is zero, this function adds in the |
| 3006 | * current read domains (CPU+COMMAND, 0). |
| 3007 | * flush_domains is set to CPU. |
| 3008 | * invalidate_domains is set to COMMAND |
| 3009 | * clflush is run to get data out of the CPU caches |
| 3010 | * then i915_dev_set_domain calls i915_gem_flush to |
| 3011 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 3012 | * 5. Unmapped from GTT |
| 3013 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 3014 | * flush_domains and invalidate_domains end up both zero |
| 3015 | * so no flushing/invalidating happens |
| 3016 | * 6. Freed |
| 3017 | * yay, done |
| 3018 | * |
| 3019 | * Case 2: The shared render buffer |
| 3020 | * |
| 3021 | * 1. Allocated |
| 3022 | * 2. Mapped to GTT |
| 3023 | * 3. Read/written by GPU |
| 3024 | * 4. set_domain to (CPU,CPU) |
| 3025 | * 5. Read/written by CPU |
| 3026 | * 6. Read/written by GPU |
| 3027 | * |
| 3028 | * 1. Allocated |
| 3029 | * Same as last example, (CPU, CPU) |
| 3030 | * 2. Mapped to GTT |
| 3031 | * Nothing changes (assertions find that it is not in the GPU) |
| 3032 | * 3. Read/written by GPU |
| 3033 | * execbuffer calls set_domain (RENDER, RENDER) |
| 3034 | * flush_domains gets CPU |
| 3035 | * invalidate_domains gets GPU |
| 3036 | * clflush (obj) |
| 3037 | * MI_FLUSH and drm_agp_chipset_flush |
| 3038 | * 4. set_domain (CPU, CPU) |
| 3039 | * flush_domains gets GPU |
| 3040 | * invalidate_domains gets CPU |
| 3041 | * wait_rendering (obj) to make sure all drawing is complete. |
| 3042 | * This will include an MI_FLUSH to get the data from GPU |
| 3043 | * to memory |
| 3044 | * clflush (obj) to invalidate the CPU cache |
| 3045 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 3046 | * 5. Read/written by CPU |
| 3047 | * cache lines are loaded and dirtied |
| 3048 | * 6. Read written by GPU |
| 3049 | * Same as last GPU access |
| 3050 | * |
| 3051 | * Case 3: The constant buffer |
| 3052 | * |
| 3053 | * 1. Allocated |
| 3054 | * 2. Written by CPU |
| 3055 | * 3. Read by GPU |
| 3056 | * 4. Updated (written) by CPU again |
| 3057 | * 5. Read by GPU |
| 3058 | * |
| 3059 | * 1. Allocated |
| 3060 | * (CPU, CPU) |
| 3061 | * 2. Written by CPU |
| 3062 | * (CPU, CPU) |
| 3063 | * 3. Read by GPU |
| 3064 | * (CPU+RENDER, 0) |
| 3065 | * flush_domains = CPU |
| 3066 | * invalidate_domains = RENDER |
| 3067 | * clflush (obj) |
| 3068 | * MI_FLUSH |
| 3069 | * drm_agp_chipset_flush |
| 3070 | * 4. Updated (written) by CPU again |
| 3071 | * (CPU, CPU) |
| 3072 | * flush_domains = 0 (no previous write domain) |
| 3073 | * invalidate_domains = 0 (no new read domains) |
| 3074 | * 5. Read by GPU |
| 3075 | * (CPU+RENDER, 0) |
| 3076 | * flush_domains = CPU |
| 3077 | * invalidate_domains = RENDER |
| 3078 | * clflush (obj) |
| 3079 | * MI_FLUSH |
| 3080 | * drm_agp_chipset_flush |
| 3081 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 3082 | static void |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3083 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3084 | { |
| 3085 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3086 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3087 | uint32_t invalidate_domains = 0; |
| 3088 | uint32_t flush_domains = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3089 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3090 | |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3091 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
| 3092 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3093 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3094 | intel_mark_busy(dev, obj); |
| 3095 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3096 | #if WATCH_BUF |
| 3097 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", |
| 3098 | __func__, obj, |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3099 | obj->read_domains, obj->pending_read_domains, |
| 3100 | obj->write_domain, obj->pending_write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3101 | #endif |
| 3102 | /* |
| 3103 | * If the object isn't moving to a new write domain, |
| 3104 | * let the object stay in multiple read domains |
| 3105 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3106 | if (obj->pending_write_domain == 0) |
| 3107 | obj->pending_read_domains |= obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3108 | else |
| 3109 | obj_priv->dirty = 1; |
| 3110 | |
| 3111 | /* |
| 3112 | * Flush the current write domain if |
| 3113 | * the new read domains don't match. Invalidate |
| 3114 | * any read domains which differ from the old |
| 3115 | * write domain |
| 3116 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3117 | if (obj->write_domain && |
| 3118 | obj->write_domain != obj->pending_read_domains) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3119 | flush_domains |= obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3120 | invalidate_domains |= |
| 3121 | obj->pending_read_domains & ~obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3122 | } |
| 3123 | /* |
| 3124 | * Invalidate any read caches which may have |
| 3125 | * stale data. That is, any new read domains. |
| 3126 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3127 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3128 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
| 3129 | #if WATCH_BUF |
| 3130 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", |
| 3131 | __func__, flush_domains, invalidate_domains); |
| 3132 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3133 | i915_gem_clflush_object(obj); |
| 3134 | } |
| 3135 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3136 | old_read_domains = obj->read_domains; |
| 3137 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3138 | /* The actual obj->write_domain will be updated with |
| 3139 | * pending_write_domain after we emit the accumulated flush for all |
| 3140 | * of our domain changes in execbuffers (which clears objects' |
| 3141 | * write_domains). So if we have a current write domain that we |
| 3142 | * aren't changing, set pending_write_domain to that. |
| 3143 | */ |
| 3144 | if (flush_domains == 0 && obj->pending_write_domain == 0) |
| 3145 | obj->pending_write_domain = obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3146 | obj->read_domains = obj->pending_read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3147 | |
| 3148 | dev->invalidate_domains |= invalidate_domains; |
| 3149 | dev->flush_domains |= flush_domains; |
| 3150 | #if WATCH_BUF |
| 3151 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", |
| 3152 | __func__, |
| 3153 | obj->read_domains, obj->write_domain, |
| 3154 | dev->invalidate_domains, dev->flush_domains); |
| 3155 | #endif |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3156 | |
| 3157 | trace_i915_gem_object_change_domain(obj, |
| 3158 | old_read_domains, |
| 3159 | obj->write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3160 | } |
| 3161 | |
| 3162 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3163 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3164 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3165 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3166 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3167 | */ |
| 3168 | static void |
| 3169 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 3170 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3171 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3172 | |
| 3173 | if (!obj_priv->page_cpu_valid) |
| 3174 | return; |
| 3175 | |
| 3176 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3177 | */ |
| 3178 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3179 | int i; |
| 3180 | |
| 3181 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 3182 | if (obj_priv->page_cpu_valid[i]) |
| 3183 | continue; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3184 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3185 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3186 | } |
| 3187 | |
| 3188 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3189 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3190 | */ |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3191 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3192 | obj_priv->page_cpu_valid = NULL; |
| 3193 | } |
| 3194 | |
| 3195 | /** |
| 3196 | * Set the CPU read domain on a range of the object. |
| 3197 | * |
| 3198 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3199 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3200 | * pages have been flushed, and will be respected by |
| 3201 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3202 | * of the whole object. |
| 3203 | * |
| 3204 | * This function returns when the move is complete, including waiting on |
| 3205 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3206 | */ |
| 3207 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3208 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 3209 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3210 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3211 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3212 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3213 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3214 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3215 | if (offset == 0 && size == obj->size) |
| 3216 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3217 | |
| 3218 | i915_gem_object_flush_gpu_write_domain(obj); |
| 3219 | /* Wait on any GPU rendering and flushing to occur. */ |
| 3220 | ret = i915_gem_object_wait_rendering(obj); |
| 3221 | if (ret != 0) |
| 3222 | return ret; |
| 3223 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3224 | |
| 3225 | /* If we're already fully in the CPU read domain, we're done. */ |
| 3226 | if (obj_priv->page_cpu_valid == NULL && |
| 3227 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3228 | return 0; |
| 3229 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3230 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3231 | * newly adding I915_GEM_DOMAIN_CPU |
| 3232 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3233 | if (obj_priv->page_cpu_valid == NULL) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3234 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
| 3235 | GFP_KERNEL); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3236 | if (obj_priv->page_cpu_valid == NULL) |
| 3237 | return -ENOMEM; |
| 3238 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3239 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3240 | |
| 3241 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3242 | * perspective. |
| 3243 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3244 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3245 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3246 | if (obj_priv->page_cpu_valid[i]) |
| 3247 | continue; |
| 3248 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3249 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3250 | |
| 3251 | obj_priv->page_cpu_valid[i] = 1; |
| 3252 | } |
| 3253 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3254 | /* It should now be out of any other write domains, and we can update |
| 3255 | * the domain values for our changes. |
| 3256 | */ |
| 3257 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3258 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3259 | old_read_domains = obj->read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3260 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3261 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3262 | trace_i915_gem_object_change_domain(obj, |
| 3263 | old_read_domains, |
| 3264 | obj->write_domain); |
| 3265 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3266 | return 0; |
| 3267 | } |
| 3268 | |
| 3269 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3270 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 3271 | */ |
| 3272 | static int |
| 3273 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, |
| 3274 | struct drm_file *file_priv, |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3275 | struct drm_i915_gem_exec_object2 *entry, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3276 | struct drm_i915_gem_relocation_entry *relocs) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3277 | { |
| 3278 | struct drm_device *dev = obj->dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3279 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3280 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3281 | int i, ret; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3282 | void __iomem *reloc_page; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3283 | bool need_fence; |
| 3284 | |
| 3285 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3286 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 3287 | |
| 3288 | /* Check fence reg constraints and rebind if necessary */ |
Chris Wilson | 808b24d6 | 2010-05-27 13:18:15 +0100 | [diff] [blame] | 3289 | if (need_fence && |
| 3290 | !i915_gem_object_fence_offset_ok(obj, |
| 3291 | obj_priv->tiling_mode)) { |
| 3292 | ret = i915_gem_object_unbind(obj); |
| 3293 | if (ret) |
| 3294 | return ret; |
| 3295 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3296 | |
| 3297 | /* Choose the GTT offset for our buffer and put it there. */ |
| 3298 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); |
| 3299 | if (ret) |
| 3300 | return ret; |
| 3301 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3302 | /* |
| 3303 | * Pre-965 chips need a fence register set up in order to |
| 3304 | * properly handle blits to/from tiled surfaces. |
| 3305 | */ |
| 3306 | if (need_fence) { |
| 3307 | ret = i915_gem_object_get_fence_reg(obj); |
| 3308 | if (ret != 0) { |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3309 | i915_gem_object_unpin(obj); |
| 3310 | return ret; |
| 3311 | } |
| 3312 | } |
| 3313 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3314 | entry->offset = obj_priv->gtt_offset; |
| 3315 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3316 | /* Apply the relocations, using the GTT aperture to avoid cache |
| 3317 | * flushing requirements. |
| 3318 | */ |
| 3319 | for (i = 0; i < entry->relocation_count; i++) { |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3320 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3321 | struct drm_gem_object *target_obj; |
| 3322 | struct drm_i915_gem_object *target_obj_priv; |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3323 | uint32_t reloc_val, reloc_offset; |
| 3324 | uint32_t __iomem *reloc_entry; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3325 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3326 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3327 | reloc->target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3328 | if (target_obj == NULL) { |
| 3329 | i915_gem_object_unpin(obj); |
| 3330 | return -EBADF; |
| 3331 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3332 | target_obj_priv = to_intel_bo(target_obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3333 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3334 | #if WATCH_RELOC |
| 3335 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3336 | "read %08x write %08x gtt %08x " |
| 3337 | "presumed %08x delta %08x\n", |
| 3338 | __func__, |
| 3339 | obj, |
| 3340 | (int) reloc->offset, |
| 3341 | (int) reloc->target_handle, |
| 3342 | (int) reloc->read_domains, |
| 3343 | (int) reloc->write_domain, |
| 3344 | (int) target_obj_priv->gtt_offset, |
| 3345 | (int) reloc->presumed_offset, |
| 3346 | reloc->delta); |
| 3347 | #endif |
| 3348 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3349 | /* The target buffer should have appeared before us in the |
| 3350 | * exec_object list, so it should have a GTT space bound by now. |
| 3351 | */ |
| 3352 | if (target_obj_priv->gtt_space == NULL) { |
| 3353 | DRM_ERROR("No GTT space found for object %d\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3354 | reloc->target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3355 | drm_gem_object_unreference(target_obj); |
| 3356 | i915_gem_object_unpin(obj); |
| 3357 | return -EINVAL; |
| 3358 | } |
| 3359 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3360 | /* Validate that the target is in a valid r/w GPU domain */ |
Daniel Vetter | 16edd55 | 2010-02-19 11:52:02 +0100 | [diff] [blame] | 3361 | if (reloc->write_domain & (reloc->write_domain - 1)) { |
| 3362 | DRM_ERROR("reloc with multiple write domains: " |
| 3363 | "obj %p target %d offset %d " |
| 3364 | "read %08x write %08x", |
| 3365 | obj, reloc->target_handle, |
| 3366 | (int) reloc->offset, |
| 3367 | reloc->read_domains, |
| 3368 | reloc->write_domain); |
| 3369 | return -EINVAL; |
| 3370 | } |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3371 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
| 3372 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3373 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3374 | "obj %p target %d offset %d " |
| 3375 | "read %08x write %08x", |
| 3376 | obj, reloc->target_handle, |
| 3377 | (int) reloc->offset, |
| 3378 | reloc->read_domains, |
| 3379 | reloc->write_domain); |
| 3380 | drm_gem_object_unreference(target_obj); |
| 3381 | i915_gem_object_unpin(obj); |
| 3382 | return -EINVAL; |
| 3383 | } |
| 3384 | if (reloc->write_domain && target_obj->pending_write_domain && |
| 3385 | reloc->write_domain != target_obj->pending_write_domain) { |
| 3386 | DRM_ERROR("Write domain conflict: " |
| 3387 | "obj %p target %d offset %d " |
| 3388 | "new %08x old %08x\n", |
| 3389 | obj, reloc->target_handle, |
| 3390 | (int) reloc->offset, |
| 3391 | reloc->write_domain, |
| 3392 | target_obj->pending_write_domain); |
| 3393 | drm_gem_object_unreference(target_obj); |
| 3394 | i915_gem_object_unpin(obj); |
| 3395 | return -EINVAL; |
| 3396 | } |
| 3397 | |
| 3398 | target_obj->pending_read_domains |= reloc->read_domains; |
| 3399 | target_obj->pending_write_domain |= reloc->write_domain; |
| 3400 | |
| 3401 | /* If the relocation already has the right value in it, no |
| 3402 | * more work needs to be done. |
| 3403 | */ |
| 3404 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
| 3405 | drm_gem_object_unreference(target_obj); |
| 3406 | continue; |
| 3407 | } |
| 3408 | |
| 3409 | /* Check that the relocation address is valid... */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3410 | if (reloc->offset > obj->size - 4) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3411 | DRM_ERROR("Relocation beyond object bounds: " |
| 3412 | "obj %p target %d offset %d size %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3413 | obj, reloc->target_handle, |
| 3414 | (int) reloc->offset, (int) obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3415 | drm_gem_object_unreference(target_obj); |
| 3416 | i915_gem_object_unpin(obj); |
| 3417 | return -EINVAL; |
| 3418 | } |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3419 | if (reloc->offset & 3) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3420 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3421 | "obj %p target %d offset %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3422 | obj, reloc->target_handle, |
| 3423 | (int) reloc->offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3424 | drm_gem_object_unreference(target_obj); |
| 3425 | i915_gem_object_unpin(obj); |
| 3426 | return -EINVAL; |
| 3427 | } |
| 3428 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3429 | /* and points to somewhere within the target object. */ |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3430 | if (reloc->delta >= target_obj->size) { |
| 3431 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3432 | "obj %p target %d delta %d size %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3433 | obj, reloc->target_handle, |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3434 | (int) reloc->delta, (int) target_obj->size); |
Chris Wilson | 491152b | 2009-02-11 14:26:32 +0000 | [diff] [blame] | 3435 | drm_gem_object_unreference(target_obj); |
| 3436 | i915_gem_object_unpin(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3437 | return -EINVAL; |
| 3438 | } |
| 3439 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3440 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 3441 | if (ret != 0) { |
| 3442 | drm_gem_object_unreference(target_obj); |
| 3443 | i915_gem_object_unpin(obj); |
| 3444 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3445 | } |
| 3446 | |
| 3447 | /* Map the page containing the relocation we're going to |
| 3448 | * perform. |
| 3449 | */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3450 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3451 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 3452 | (reloc_offset & |
| 3453 | ~(PAGE_SIZE - 1))); |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3454 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3455 | (reloc_offset & (PAGE_SIZE - 1))); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3456 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3457 | |
| 3458 | #if WATCH_BUF |
| 3459 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3460 | obj, (unsigned int) reloc->offset, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3461 | readl(reloc_entry), reloc_val); |
| 3462 | #endif |
| 3463 | writel(reloc_val, reloc_entry); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3464 | io_mapping_unmap_atomic(reloc_page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3465 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3466 | /* The updated presumed offset for this entry will be |
| 3467 | * copied back out to the user. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3468 | */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3469 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3470 | |
| 3471 | drm_gem_object_unreference(target_obj); |
| 3472 | } |
| 3473 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3474 | #if WATCH_BUF |
| 3475 | if (0) |
| 3476 | i915_gem_dump_object(obj, 128, __func__, ~0); |
| 3477 | #endif |
| 3478 | return 0; |
| 3479 | } |
| 3480 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3481 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3482 | * emitted over 20 msec ago. |
| 3483 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3484 | * Note that if we were to use the current jiffies each time around the loop, |
| 3485 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3486 | * render a frame was over 20ms. |
| 3487 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3488 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3489 | * relatively low latency when blocking on a particular request to finish. |
| 3490 | */ |
| 3491 | static int |
| 3492 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) |
| 3493 | { |
| 3494 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 3495 | int ret = 0; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3496 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3497 | |
| 3498 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3499 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
| 3500 | struct drm_i915_gem_request *request; |
| 3501 | |
| 3502 | request = list_first_entry(&i915_file_priv->mm.request_list, |
| 3503 | struct drm_i915_gem_request, |
| 3504 | client_list); |
| 3505 | |
| 3506 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3507 | break; |
| 3508 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3509 | ret = i915_wait_request(dev, request->seqno, request->ring); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3510 | if (ret != 0) |
| 3511 | break; |
| 3512 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3513 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3514 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3515 | return ret; |
| 3516 | } |
| 3517 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3518 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3519 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3520 | uint32_t buffer_count, |
| 3521 | struct drm_i915_gem_relocation_entry **relocs) |
| 3522 | { |
| 3523 | uint32_t reloc_count = 0, reloc_index = 0, i; |
| 3524 | int ret; |
| 3525 | |
| 3526 | *relocs = NULL; |
| 3527 | for (i = 0; i < buffer_count; i++) { |
| 3528 | if (reloc_count + exec_list[i].relocation_count < reloc_count) |
| 3529 | return -EINVAL; |
| 3530 | reloc_count += exec_list[i].relocation_count; |
| 3531 | } |
| 3532 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3533 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3534 | if (*relocs == NULL) { |
| 3535 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3536 | return -ENOMEM; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3537 | } |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3538 | |
| 3539 | for (i = 0; i < buffer_count; i++) { |
| 3540 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 3541 | |
| 3542 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3543 | |
| 3544 | ret = copy_from_user(&(*relocs)[reloc_index], |
| 3545 | user_relocs, |
| 3546 | exec_list[i].relocation_count * |
| 3547 | sizeof(**relocs)); |
| 3548 | if (ret != 0) { |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3549 | drm_free_large(*relocs); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3550 | *relocs = NULL; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3551 | return -EFAULT; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3552 | } |
| 3553 | |
| 3554 | reloc_index += exec_list[i].relocation_count; |
| 3555 | } |
| 3556 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3557 | return 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3558 | } |
| 3559 | |
| 3560 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3561 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3562 | uint32_t buffer_count, |
| 3563 | struct drm_i915_gem_relocation_entry *relocs) |
| 3564 | { |
| 3565 | uint32_t reloc_count = 0, i; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3566 | int ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3567 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3568 | if (relocs == NULL) |
| 3569 | return 0; |
| 3570 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3571 | for (i = 0; i < buffer_count; i++) { |
| 3572 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3573 | int unwritten; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3574 | |
| 3575 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3576 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3577 | unwritten = copy_to_user(user_relocs, |
| 3578 | &relocs[reloc_count], |
| 3579 | exec_list[i].relocation_count * |
| 3580 | sizeof(*relocs)); |
| 3581 | |
| 3582 | if (unwritten) { |
| 3583 | ret = -EFAULT; |
| 3584 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3585 | } |
| 3586 | |
| 3587 | reloc_count += exec_list[i].relocation_count; |
| 3588 | } |
| 3589 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3590 | err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3591 | drm_free_large(relocs); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3592 | |
| 3593 | return ret; |
| 3594 | } |
| 3595 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3596 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3597 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3598 | uint64_t exec_offset) |
| 3599 | { |
| 3600 | uint32_t exec_start, exec_len; |
| 3601 | |
| 3602 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3603 | exec_len = (uint32_t) exec->batch_len; |
| 3604 | |
| 3605 | if ((exec_start | exec_len) & 0x7) |
| 3606 | return -EINVAL; |
| 3607 | |
| 3608 | if (!exec_start) |
| 3609 | return -EINVAL; |
| 3610 | |
| 3611 | return 0; |
| 3612 | } |
| 3613 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3614 | static int |
| 3615 | i915_gem_wait_for_pending_flip(struct drm_device *dev, |
| 3616 | struct drm_gem_object **object_list, |
| 3617 | int count) |
| 3618 | { |
| 3619 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3620 | struct drm_i915_gem_object *obj_priv; |
| 3621 | DEFINE_WAIT(wait); |
| 3622 | int i, ret = 0; |
| 3623 | |
| 3624 | for (;;) { |
| 3625 | prepare_to_wait(&dev_priv->pending_flip_queue, |
| 3626 | &wait, TASK_INTERRUPTIBLE); |
| 3627 | for (i = 0; i < count; i++) { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3628 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3629 | if (atomic_read(&obj_priv->pending_flip) > 0) |
| 3630 | break; |
| 3631 | } |
| 3632 | if (i == count) |
| 3633 | break; |
| 3634 | |
| 3635 | if (!signal_pending(current)) { |
| 3636 | mutex_unlock(&dev->struct_mutex); |
| 3637 | schedule(); |
| 3638 | mutex_lock(&dev->struct_mutex); |
| 3639 | continue; |
| 3640 | } |
| 3641 | ret = -ERESTARTSYS; |
| 3642 | break; |
| 3643 | } |
| 3644 | finish_wait(&dev_priv->pending_flip_queue, &wait); |
| 3645 | |
| 3646 | return ret; |
| 3647 | } |
| 3648 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3649 | int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3650 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
| 3651 | struct drm_file *file_priv, |
| 3652 | struct drm_i915_gem_execbuffer2 *args, |
| 3653 | struct drm_i915_gem_exec_object2 *exec_list) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3654 | { |
| 3655 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3656 | struct drm_gem_object **object_list = NULL; |
| 3657 | struct drm_gem_object *batch_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3658 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3659 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3660 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3661 | int ret = 0, ret2, i, pinned = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3662 | uint64_t exec_offset; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3663 | uint32_t seqno, flush_domains, reloc_index; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3664 | int pin_tries, flips; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3665 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3666 | struct intel_ring_buffer *ring = NULL; |
| 3667 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3668 | #if WATCH_EXEC |
| 3669 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3670 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3671 | #endif |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3672 | if (args->flags & I915_EXEC_BSD) { |
| 3673 | if (!HAS_BSD(dev)) { |
| 3674 | DRM_ERROR("execbuf with wrong flag\n"); |
| 3675 | return -EINVAL; |
| 3676 | } |
| 3677 | ring = &dev_priv->bsd_ring; |
| 3678 | } else { |
| 3679 | ring = &dev_priv->render_ring; |
| 3680 | } |
| 3681 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3682 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3683 | if (args->buffer_count < 1) { |
| 3684 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3685 | return -EINVAL; |
| 3686 | } |
Eric Anholt | c8e0f93 | 2009-11-22 03:49:37 +0100 | [diff] [blame] | 3687 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3688 | if (object_list == NULL) { |
| 3689 | DRM_ERROR("Failed to allocate object list for %d buffers\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3690 | args->buffer_count); |
| 3691 | ret = -ENOMEM; |
| 3692 | goto pre_mutex_err; |
| 3693 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3694 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3695 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3696 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3697 | GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3698 | if (cliprects == NULL) { |
| 3699 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3700 | goto pre_mutex_err; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3701 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3702 | |
| 3703 | ret = copy_from_user(cliprects, |
| 3704 | (struct drm_clip_rect __user *) |
| 3705 | (uintptr_t) args->cliprects_ptr, |
| 3706 | sizeof(*cliprects) * args->num_cliprects); |
| 3707 | if (ret != 0) { |
| 3708 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 3709 | args->num_cliprects, ret); |
| 3710 | goto pre_mutex_err; |
| 3711 | } |
| 3712 | } |
| 3713 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3714 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
| 3715 | &relocs); |
| 3716 | if (ret != 0) |
| 3717 | goto pre_mutex_err; |
| 3718 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3719 | mutex_lock(&dev->struct_mutex); |
| 3720 | |
| 3721 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3722 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3723 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3724 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3725 | ret = -EIO; |
| 3726 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3727 | } |
| 3728 | |
| 3729 | if (dev_priv->mm.suspended) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3730 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3731 | ret = -EBUSY; |
| 3732 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3733 | } |
| 3734 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3735 | /* Look up object handles */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3736 | flips = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3737 | for (i = 0; i < args->buffer_count; i++) { |
| 3738 | object_list[i] = drm_gem_object_lookup(dev, file_priv, |
| 3739 | exec_list[i].handle); |
| 3740 | if (object_list[i] == NULL) { |
| 3741 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 3742 | exec_list[i].handle, i); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3743 | /* prevent error path from reading uninitialized data */ |
| 3744 | args->buffer_count = i + 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3745 | ret = -EBADF; |
| 3746 | goto err; |
| 3747 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3748 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3749 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3750 | if (obj_priv->in_execbuffer) { |
| 3751 | DRM_ERROR("Object %p appears more than once in object list\n", |
| 3752 | object_list[i]); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3753 | /* prevent error path from reading uninitialized data */ |
| 3754 | args->buffer_count = i + 1; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3755 | ret = -EBADF; |
| 3756 | goto err; |
| 3757 | } |
| 3758 | obj_priv->in_execbuffer = true; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3759 | flips += atomic_read(&obj_priv->pending_flip); |
| 3760 | } |
| 3761 | |
| 3762 | if (flips > 0) { |
| 3763 | ret = i915_gem_wait_for_pending_flip(dev, object_list, |
| 3764 | args->buffer_count); |
| 3765 | if (ret) |
| 3766 | goto err; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3767 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3768 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3769 | /* Pin and relocate */ |
| 3770 | for (pin_tries = 0; ; pin_tries++) { |
| 3771 | ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3772 | reloc_index = 0; |
| 3773 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3774 | for (i = 0; i < args->buffer_count; i++) { |
| 3775 | object_list[i]->pending_read_domains = 0; |
| 3776 | object_list[i]->pending_write_domain = 0; |
| 3777 | ret = i915_gem_object_pin_and_relocate(object_list[i], |
| 3778 | file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3779 | &exec_list[i], |
| 3780 | &relocs[reloc_index]); |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3781 | if (ret) |
| 3782 | break; |
| 3783 | pinned = i + 1; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3784 | reloc_index += exec_list[i].relocation_count; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3785 | } |
| 3786 | /* success */ |
| 3787 | if (ret == 0) |
| 3788 | break; |
| 3789 | |
| 3790 | /* error other than GTT full, or we've already tried again */ |
Chris Wilson | 2939e1f | 2009-06-06 09:46:03 +0100 | [diff] [blame] | 3791 | if (ret != -ENOSPC || pin_tries >= 1) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3792 | if (ret != -ERESTARTSYS) { |
| 3793 | unsigned long long total_size = 0; |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3794 | int num_fences = 0; |
| 3795 | for (i = 0; i < args->buffer_count; i++) { |
| 3796 | obj_priv = object_list[i]->driver_private; |
| 3797 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3798 | total_size += object_list[i]->size; |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3799 | num_fences += |
| 3800 | exec_list[i].flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3801 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 3802 | } |
| 3803 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes, %d fences: %d\n", |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3804 | pinned+1, args->buffer_count, |
Chris Wilson | 3d1cc47 | 2010-05-27 13:18:19 +0100 | [diff] [blame] | 3805 | total_size, num_fences, |
| 3806 | ret); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3807 | DRM_ERROR("%d objects [%d pinned], " |
| 3808 | "%d object bytes [%d pinned], " |
| 3809 | "%d/%d gtt bytes\n", |
| 3810 | atomic_read(&dev->object_count), |
| 3811 | atomic_read(&dev->pin_count), |
| 3812 | atomic_read(&dev->object_memory), |
| 3813 | atomic_read(&dev->pin_memory), |
| 3814 | atomic_read(&dev->gtt_memory), |
| 3815 | dev->gtt_total); |
| 3816 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3817 | goto err; |
| 3818 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3819 | |
| 3820 | /* unpin all of our buffers */ |
| 3821 | for (i = 0; i < pinned; i++) |
| 3822 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | b117763 | 2008-12-10 10:09:41 -0800 | [diff] [blame] | 3823 | pinned = 0; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3824 | |
| 3825 | /* evict everyone we can from the aperture */ |
| 3826 | ret = i915_gem_evict_everything(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3827 | if (ret && ret != -ENOSPC) |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3828 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3829 | } |
| 3830 | |
| 3831 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 3832 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 3833 | if (batch_obj->pending_write_domain) { |
| 3834 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 3835 | ret = -EINVAL; |
| 3836 | goto err; |
| 3837 | } |
| 3838 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3839 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3840 | /* Sanity check the batch buffer, prior to moving objects */ |
| 3841 | exec_offset = exec_list[args->buffer_count - 1].offset; |
| 3842 | ret = i915_gem_check_execbuffer (args, exec_offset); |
| 3843 | if (ret != 0) { |
| 3844 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 3845 | goto err; |
| 3846 | } |
| 3847 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3848 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3849 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3850 | /* Zero the global flush/invalidate flags. These |
| 3851 | * will be modified as new domains are computed |
| 3852 | * for each object |
| 3853 | */ |
| 3854 | dev->invalidate_domains = 0; |
| 3855 | dev->flush_domains = 0; |
| 3856 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3857 | for (i = 0; i < args->buffer_count; i++) { |
| 3858 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3859 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3860 | /* Compute new gpu domains and update invalidate/flush */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3861 | i915_gem_object_set_to_gpu_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3862 | } |
| 3863 | |
| 3864 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3865 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3866 | if (dev->invalidate_domains | dev->flush_domains) { |
| 3867 | #if WATCH_EXEC |
| 3868 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3869 | __func__, |
| 3870 | dev->invalidate_domains, |
| 3871 | dev->flush_domains); |
| 3872 | #endif |
| 3873 | i915_gem_flush(dev, |
| 3874 | dev->invalidate_domains, |
| 3875 | dev->flush_domains); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3876 | if (dev->flush_domains & I915_GEM_GPU_DOMAINS) { |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3877 | (void)i915_add_request(dev, file_priv, |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3878 | dev->flush_domains, |
| 3879 | &dev_priv->render_ring); |
| 3880 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 3881 | if (HAS_BSD(dev)) |
| 3882 | (void)i915_add_request(dev, file_priv, |
| 3883 | dev->flush_domains, |
| 3884 | &dev_priv->bsd_ring); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3885 | } |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3886 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3887 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3888 | for (i = 0; i < args->buffer_count; i++) { |
| 3889 | struct drm_gem_object *obj = object_list[i]; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3890 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3891 | uint32_t old_write_domain = obj->write_domain; |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3892 | |
| 3893 | obj->write_domain = obj->pending_write_domain; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 3894 | if (obj->write_domain) |
| 3895 | list_move_tail(&obj_priv->gpu_write_list, |
| 3896 | &dev_priv->mm.gpu_write_list); |
| 3897 | else |
| 3898 | list_del_init(&obj_priv->gpu_write_list); |
| 3899 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3900 | trace_i915_gem_object_change_domain(obj, |
| 3901 | obj->read_domains, |
| 3902 | old_write_domain); |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3903 | } |
| 3904 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3905 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3906 | |
| 3907 | #if WATCH_COHERENCY |
| 3908 | for (i = 0; i < args->buffer_count; i++) { |
| 3909 | i915_gem_object_check_coherency(object_list[i], |
| 3910 | exec_list[i].handle); |
| 3911 | } |
| 3912 | #endif |
| 3913 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3914 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 3915 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3916 | args->batch_len, |
| 3917 | __func__, |
| 3918 | ~0); |
| 3919 | #endif |
| 3920 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3921 | /* Exec the batchbuffer */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3922 | ret = ring->dispatch_gem_execbuffer(dev, ring, args, |
| 3923 | cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3924 | if (ret) { |
| 3925 | DRM_ERROR("dispatch failed %d\n", ret); |
| 3926 | goto err; |
| 3927 | } |
| 3928 | |
| 3929 | /* |
| 3930 | * Ensure that the commands in the batch buffer are |
| 3931 | * finished before the interrupt fires |
| 3932 | */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3933 | flush_domains = i915_retire_commands(dev, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3934 | |
| 3935 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3936 | |
| 3937 | /* |
| 3938 | * Get a seqno representing the execution of the current buffer, |
| 3939 | * which we can wait on. We would like to mitigate these interrupts, |
| 3940 | * likely by only creating seqnos occasionally (so that we have |
| 3941 | * *some* interrupts representing completion of buffers that we can |
| 3942 | * wait on when trying to clear up gtt space). |
| 3943 | */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3944 | seqno = i915_add_request(dev, file_priv, flush_domains, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3945 | BUG_ON(seqno == 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3946 | for (i = 0; i < args->buffer_count; i++) { |
| 3947 | struct drm_gem_object *obj = object_list[i]; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3948 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3949 | |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 3950 | i915_gem_object_move_to_active(obj, seqno, ring); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3951 | #if WATCH_LRU |
| 3952 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); |
| 3953 | #endif |
| 3954 | } |
| 3955 | #if WATCH_LRU |
| 3956 | i915_dump_lru(dev, __func__); |
| 3957 | #endif |
| 3958 | |
| 3959 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3960 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3961 | err: |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3962 | for (i = 0; i < pinned; i++) |
| 3963 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3964 | |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3965 | for (i = 0; i < args->buffer_count; i++) { |
| 3966 | if (object_list[i]) { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 3967 | obj_priv = to_intel_bo(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3968 | obj_priv->in_execbuffer = false; |
| 3969 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3970 | drm_gem_object_unreference(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3971 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3972 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3973 | mutex_unlock(&dev->struct_mutex); |
| 3974 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3975 | pre_mutex_err: |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3976 | /* Copy the updated relocations out regardless of current error |
| 3977 | * state. Failure to update the relocs would mean that the next |
| 3978 | * time userland calls execbuf, it would do so with presumed offset |
| 3979 | * state that didn't match the actual object state. |
| 3980 | */ |
| 3981 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, |
| 3982 | relocs); |
| 3983 | if (ret2 != 0) { |
| 3984 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); |
| 3985 | |
| 3986 | if (ret == 0) |
| 3987 | ret = ret2; |
| 3988 | } |
| 3989 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3990 | drm_free_large(object_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3991 | kfree(cliprects); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3992 | |
| 3993 | return ret; |
| 3994 | } |
| 3995 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3996 | /* |
| 3997 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 3998 | * list array and passes it to the real function. |
| 3999 | */ |
| 4000 | int |
| 4001 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 4002 | struct drm_file *file_priv) |
| 4003 | { |
| 4004 | struct drm_i915_gem_execbuffer *args = data; |
| 4005 | struct drm_i915_gem_execbuffer2 exec2; |
| 4006 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 4007 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4008 | int ret, i; |
| 4009 | |
| 4010 | #if WATCH_EXEC |
| 4011 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4012 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4013 | #endif |
| 4014 | |
| 4015 | if (args->buffer_count < 1) { |
| 4016 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 4017 | return -EINVAL; |
| 4018 | } |
| 4019 | |
| 4020 | /* Copy in the exec list from userland */ |
| 4021 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 4022 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4023 | if (exec_list == NULL || exec2_list == NULL) { |
| 4024 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4025 | args->buffer_count); |
| 4026 | drm_free_large(exec_list); |
| 4027 | drm_free_large(exec2_list); |
| 4028 | return -ENOMEM; |
| 4029 | } |
| 4030 | ret = copy_from_user(exec_list, |
| 4031 | (struct drm_i915_relocation_entry __user *) |
| 4032 | (uintptr_t) args->buffers_ptr, |
| 4033 | sizeof(*exec_list) * args->buffer_count); |
| 4034 | if (ret != 0) { |
| 4035 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4036 | args->buffer_count, ret); |
| 4037 | drm_free_large(exec_list); |
| 4038 | drm_free_large(exec2_list); |
| 4039 | return -EFAULT; |
| 4040 | } |
| 4041 | |
| 4042 | for (i = 0; i < args->buffer_count; i++) { |
| 4043 | exec2_list[i].handle = exec_list[i].handle; |
| 4044 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 4045 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 4046 | exec2_list[i].alignment = exec_list[i].alignment; |
| 4047 | exec2_list[i].offset = exec_list[i].offset; |
| 4048 | if (!IS_I965G(dev)) |
| 4049 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 4050 | else |
| 4051 | exec2_list[i].flags = 0; |
| 4052 | } |
| 4053 | |
| 4054 | exec2.buffers_ptr = args->buffers_ptr; |
| 4055 | exec2.buffer_count = args->buffer_count; |
| 4056 | exec2.batch_start_offset = args->batch_start_offset; |
| 4057 | exec2.batch_len = args->batch_len; |
| 4058 | exec2.DR1 = args->DR1; |
| 4059 | exec2.DR4 = args->DR4; |
| 4060 | exec2.num_cliprects = args->num_cliprects; |
| 4061 | exec2.cliprects_ptr = args->cliprects_ptr; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4062 | exec2.flags = I915_EXEC_RENDER; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4063 | |
| 4064 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); |
| 4065 | if (!ret) { |
| 4066 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4067 | for (i = 0; i < args->buffer_count; i++) |
| 4068 | exec_list[i].offset = exec2_list[i].offset; |
| 4069 | /* ... and back out to userspace */ |
| 4070 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4071 | (uintptr_t) args->buffers_ptr, |
| 4072 | exec_list, |
| 4073 | sizeof(*exec_list) * args->buffer_count); |
| 4074 | if (ret) { |
| 4075 | ret = -EFAULT; |
| 4076 | DRM_ERROR("failed to copy %d exec entries " |
| 4077 | "back to user (%d)\n", |
| 4078 | args->buffer_count, ret); |
| 4079 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4080 | } |
| 4081 | |
| 4082 | drm_free_large(exec_list); |
| 4083 | drm_free_large(exec2_list); |
| 4084 | return ret; |
| 4085 | } |
| 4086 | |
| 4087 | int |
| 4088 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 4089 | struct drm_file *file_priv) |
| 4090 | { |
| 4091 | struct drm_i915_gem_execbuffer2 *args = data; |
| 4092 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4093 | int ret; |
| 4094 | |
| 4095 | #if WATCH_EXEC |
| 4096 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4097 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4098 | #endif |
| 4099 | |
| 4100 | if (args->buffer_count < 1) { |
| 4101 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); |
| 4102 | return -EINVAL; |
| 4103 | } |
| 4104 | |
| 4105 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4106 | if (exec2_list == NULL) { |
| 4107 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4108 | args->buffer_count); |
| 4109 | return -ENOMEM; |
| 4110 | } |
| 4111 | ret = copy_from_user(exec2_list, |
| 4112 | (struct drm_i915_relocation_entry __user *) |
| 4113 | (uintptr_t) args->buffers_ptr, |
| 4114 | sizeof(*exec2_list) * args->buffer_count); |
| 4115 | if (ret != 0) { |
| 4116 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4117 | args->buffer_count, ret); |
| 4118 | drm_free_large(exec2_list); |
| 4119 | return -EFAULT; |
| 4120 | } |
| 4121 | |
| 4122 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); |
| 4123 | if (!ret) { |
| 4124 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4125 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4126 | (uintptr_t) args->buffers_ptr, |
| 4127 | exec2_list, |
| 4128 | sizeof(*exec2_list) * args->buffer_count); |
| 4129 | if (ret) { |
| 4130 | ret = -EFAULT; |
| 4131 | DRM_ERROR("failed to copy %d exec entries " |
| 4132 | "back to user (%d)\n", |
| 4133 | args->buffer_count, ret); |
| 4134 | } |
| 4135 | } |
| 4136 | |
| 4137 | drm_free_large(exec2_list); |
| 4138 | return ret; |
| 4139 | } |
| 4140 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4141 | int |
| 4142 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) |
| 4143 | { |
| 4144 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4145 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4146 | int ret; |
| 4147 | |
Daniel Vetter | 778c354 | 2010-05-13 11:49:44 +0200 | [diff] [blame] | 4148 | BUG_ON(obj_priv->pin_count == DRM_I915_GEM_OBJECT_MAX_PIN_COUNT); |
| 4149 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4150 | i915_verify_inactive(dev, __FILE__, __LINE__); |
Chris Wilson | ac0c6b5 | 2010-05-27 13:18:18 +0100 | [diff] [blame] | 4151 | |
| 4152 | if (obj_priv->gtt_space != NULL) { |
| 4153 | if (alignment == 0) |
| 4154 | alignment = i915_gem_get_gtt_alignment(obj); |
| 4155 | if (obj_priv->gtt_offset & (alignment - 1)) { |
| 4156 | ret = i915_gem_object_unbind(obj); |
| 4157 | if (ret) |
| 4158 | return ret; |
| 4159 | } |
| 4160 | } |
| 4161 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4162 | if (obj_priv->gtt_space == NULL) { |
| 4163 | ret = i915_gem_object_bind_to_gtt(obj, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 4164 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4165 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4166 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4167 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4168 | obj_priv->pin_count++; |
| 4169 | |
| 4170 | /* If the object is not active and not pending a flush, |
| 4171 | * remove it from the inactive list |
| 4172 | */ |
| 4173 | if (obj_priv->pin_count == 1) { |
| 4174 | atomic_inc(&dev->pin_count); |
| 4175 | atomic_add(obj->size, &dev->pin_memory); |
| 4176 | if (!obj_priv->active && |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 4177 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 && |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4178 | !list_empty(&obj_priv->list)) |
| 4179 | list_del_init(&obj_priv->list); |
| 4180 | } |
| 4181 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 4182 | |
| 4183 | return 0; |
| 4184 | } |
| 4185 | |
| 4186 | void |
| 4187 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 4188 | { |
| 4189 | struct drm_device *dev = obj->dev; |
| 4190 | drm_i915_private_t *dev_priv = dev->dev_private; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4191 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4192 | |
| 4193 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 4194 | obj_priv->pin_count--; |
| 4195 | BUG_ON(obj_priv->pin_count < 0); |
| 4196 | BUG_ON(obj_priv->gtt_space == NULL); |
| 4197 | |
| 4198 | /* If the object is no longer pinned, and is |
| 4199 | * neither active nor being flushed, then stick it on |
| 4200 | * the inactive list |
| 4201 | */ |
| 4202 | if (obj_priv->pin_count == 0) { |
| 4203 | if (!obj_priv->active && |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 4204 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4205 | list_move_tail(&obj_priv->list, |
| 4206 | &dev_priv->mm.inactive_list); |
| 4207 | atomic_dec(&dev->pin_count); |
| 4208 | atomic_sub(obj->size, &dev->pin_memory); |
| 4209 | } |
| 4210 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 4211 | } |
| 4212 | |
| 4213 | int |
| 4214 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 4215 | struct drm_file *file_priv) |
| 4216 | { |
| 4217 | struct drm_i915_gem_pin *args = data; |
| 4218 | struct drm_gem_object *obj; |
| 4219 | struct drm_i915_gem_object *obj_priv; |
| 4220 | int ret; |
| 4221 | |
| 4222 | mutex_lock(&dev->struct_mutex); |
| 4223 | |
| 4224 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4225 | if (obj == NULL) { |
| 4226 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", |
| 4227 | args->handle); |
| 4228 | mutex_unlock(&dev->struct_mutex); |
| 4229 | return -EBADF; |
| 4230 | } |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4231 | obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4232 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4233 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 4234 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4235 | drm_gem_object_unreference(obj); |
| 4236 | mutex_unlock(&dev->struct_mutex); |
| 4237 | return -EINVAL; |
| 4238 | } |
| 4239 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4240 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
| 4241 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4242 | args->handle); |
Chris Wilson | 96dec61 | 2009-02-08 19:08:04 +0000 | [diff] [blame] | 4243 | drm_gem_object_unreference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4244 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4245 | return -EINVAL; |
| 4246 | } |
| 4247 | |
| 4248 | obj_priv->user_pin_count++; |
| 4249 | obj_priv->pin_filp = file_priv; |
| 4250 | if (obj_priv->user_pin_count == 1) { |
| 4251 | ret = i915_gem_object_pin(obj, args->alignment); |
| 4252 | if (ret != 0) { |
| 4253 | drm_gem_object_unreference(obj); |
| 4254 | mutex_unlock(&dev->struct_mutex); |
| 4255 | return ret; |
| 4256 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4257 | } |
| 4258 | |
| 4259 | /* XXX - flush the CPU caches for pinned objects |
| 4260 | * as the X server doesn't manage domains yet |
| 4261 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4262 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4263 | args->offset = obj_priv->gtt_offset; |
| 4264 | drm_gem_object_unreference(obj); |
| 4265 | mutex_unlock(&dev->struct_mutex); |
| 4266 | |
| 4267 | return 0; |
| 4268 | } |
| 4269 | |
| 4270 | int |
| 4271 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 4272 | struct drm_file *file_priv) |
| 4273 | { |
| 4274 | struct drm_i915_gem_pin *args = data; |
| 4275 | struct drm_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4276 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4277 | |
| 4278 | mutex_lock(&dev->struct_mutex); |
| 4279 | |
| 4280 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4281 | if (obj == NULL) { |
| 4282 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", |
| 4283 | args->handle); |
| 4284 | mutex_unlock(&dev->struct_mutex); |
| 4285 | return -EBADF; |
| 4286 | } |
| 4287 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4288 | obj_priv = to_intel_bo(obj); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4289 | if (obj_priv->pin_filp != file_priv) { |
| 4290 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4291 | args->handle); |
| 4292 | drm_gem_object_unreference(obj); |
| 4293 | mutex_unlock(&dev->struct_mutex); |
| 4294 | return -EINVAL; |
| 4295 | } |
| 4296 | obj_priv->user_pin_count--; |
| 4297 | if (obj_priv->user_pin_count == 0) { |
| 4298 | obj_priv->pin_filp = NULL; |
| 4299 | i915_gem_object_unpin(obj); |
| 4300 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4301 | |
| 4302 | drm_gem_object_unreference(obj); |
| 4303 | mutex_unlock(&dev->struct_mutex); |
| 4304 | return 0; |
| 4305 | } |
| 4306 | |
| 4307 | int |
| 4308 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4309 | struct drm_file *file_priv) |
| 4310 | { |
| 4311 | struct drm_i915_gem_busy *args = data; |
| 4312 | struct drm_gem_object *obj; |
| 4313 | struct drm_i915_gem_object *obj_priv; |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4314 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4315 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4316 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4317 | if (obj == NULL) { |
| 4318 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", |
| 4319 | args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4320 | return -EBADF; |
| 4321 | } |
| 4322 | |
Chris Wilson | b1ce786 | 2009-06-06 09:46:00 +0100 | [diff] [blame] | 4323 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | f21289b | 2009-02-18 09:44:56 -0800 | [diff] [blame] | 4324 | /* Update the active list for the hardware's current position. |
| 4325 | * Otherwise this only updates on a delayed timer or when irqs are |
| 4326 | * actually unmasked, and our working set ends up being larger than |
| 4327 | * required. |
| 4328 | */ |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4329 | i915_gem_retire_requests(dev, &dev_priv->render_ring); |
Eric Anholt | f21289b | 2009-02-18 09:44:56 -0800 | [diff] [blame] | 4330 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4331 | if (HAS_BSD(dev)) |
| 4332 | i915_gem_retire_requests(dev, &dev_priv->bsd_ring); |
| 4333 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4334 | obj_priv = to_intel_bo(obj); |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4335 | /* Don't count being on the flushing list against the object being |
| 4336 | * done. Otherwise, a buffer left on the flushing list but not getting |
| 4337 | * flushed (because nobody's flushing that domain) won't ever return |
| 4338 | * unbusy and get reused by libdrm's bo cache. The other expected |
| 4339 | * consumer of this interface, OpenGL's occlusion queries, also specs |
| 4340 | * that the objects get unbusy "eventually" without any interference. |
| 4341 | */ |
| 4342 | args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4343 | |
| 4344 | drm_gem_object_unreference(obj); |
| 4345 | mutex_unlock(&dev->struct_mutex); |
| 4346 | return 0; |
| 4347 | } |
| 4348 | |
| 4349 | int |
| 4350 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4351 | struct drm_file *file_priv) |
| 4352 | { |
| 4353 | return i915_gem_ring_throttle(dev, file_priv); |
| 4354 | } |
| 4355 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4356 | int |
| 4357 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4358 | struct drm_file *file_priv) |
| 4359 | { |
| 4360 | struct drm_i915_gem_madvise *args = data; |
| 4361 | struct drm_gem_object *obj; |
| 4362 | struct drm_i915_gem_object *obj_priv; |
| 4363 | |
| 4364 | switch (args->madv) { |
| 4365 | case I915_MADV_DONTNEED: |
| 4366 | case I915_MADV_WILLNEED: |
| 4367 | break; |
| 4368 | default: |
| 4369 | return -EINVAL; |
| 4370 | } |
| 4371 | |
| 4372 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4373 | if (obj == NULL) { |
| 4374 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", |
| 4375 | args->handle); |
| 4376 | return -EBADF; |
| 4377 | } |
| 4378 | |
| 4379 | mutex_lock(&dev->struct_mutex); |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4380 | obj_priv = to_intel_bo(obj); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4381 | |
| 4382 | if (obj_priv->pin_count) { |
| 4383 | drm_gem_object_unreference(obj); |
| 4384 | mutex_unlock(&dev->struct_mutex); |
| 4385 | |
| 4386 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); |
| 4387 | return -EINVAL; |
| 4388 | } |
| 4389 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4390 | if (obj_priv->madv != __I915_MADV_PURGED) |
| 4391 | obj_priv->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4392 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4393 | /* if the object is no longer bound, discard its backing storage */ |
| 4394 | if (i915_gem_object_is_purgeable(obj_priv) && |
| 4395 | obj_priv->gtt_space == NULL) |
| 4396 | i915_gem_object_truncate(obj); |
| 4397 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4398 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
| 4399 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4400 | drm_gem_object_unreference(obj); |
| 4401 | mutex_unlock(&dev->struct_mutex); |
| 4402 | |
| 4403 | return 0; |
| 4404 | } |
| 4405 | |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4406 | struct drm_gem_object * i915_gem_alloc_object(struct drm_device *dev, |
| 4407 | size_t size) |
| 4408 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4409 | struct drm_i915_gem_object *obj; |
| 4410 | |
| 4411 | obj = kzalloc(sizeof(*obj), GFP_KERNEL); |
| 4412 | if (obj == NULL) |
| 4413 | return NULL; |
| 4414 | |
| 4415 | if (drm_gem_object_init(dev, &obj->base, size) != 0) { |
| 4416 | kfree(obj); |
| 4417 | return NULL; |
| 4418 | } |
| 4419 | |
| 4420 | obj->base.write_domain = I915_GEM_DOMAIN_CPU; |
| 4421 | obj->base.read_domains = I915_GEM_DOMAIN_CPU; |
| 4422 | |
| 4423 | obj->agp_type = AGP_USER_MEMORY; |
Daniel Vetter | 62b8b21 | 2010-04-09 19:05:08 +0000 | [diff] [blame] | 4424 | obj->base.driver_private = NULL; |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4425 | obj->fence_reg = I915_FENCE_REG_NONE; |
| 4426 | INIT_LIST_HEAD(&obj->list); |
| 4427 | INIT_LIST_HEAD(&obj->gpu_write_list); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4428 | obj->madv = I915_MADV_WILLNEED; |
| 4429 | |
| 4430 | trace_i915_gem_object_create(&obj->base); |
| 4431 | |
| 4432 | return &obj->base; |
Daniel Vetter | ac52bc5 | 2010-04-09 19:05:06 +0000 | [diff] [blame] | 4433 | } |
| 4434 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4435 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4436 | { |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4437 | BUG(); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4438 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4439 | return 0; |
| 4440 | } |
| 4441 | |
| 4442 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 4443 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4444 | struct drm_device *dev = obj->dev; |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4445 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4446 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4447 | trace_i915_gem_object_destroy(obj); |
| 4448 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4449 | while (obj_priv->pin_count > 0) |
| 4450 | i915_gem_object_unpin(obj); |
| 4451 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4452 | if (obj_priv->phys_obj) |
| 4453 | i915_gem_detach_phys_object(dev, obj); |
| 4454 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4455 | i915_gem_object_unbind(obj); |
| 4456 | |
Chris Wilson | 7e61615 | 2009-09-10 08:53:04 +0100 | [diff] [blame] | 4457 | if (obj_priv->mmap_offset) |
| 4458 | i915_gem_free_mmap_offset(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4459 | |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4460 | drm_gem_object_release(obj); |
| 4461 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4462 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 4463 | kfree(obj_priv->bit_17); |
Daniel Vetter | c397b90 | 2010-04-09 19:05:07 +0000 | [diff] [blame] | 4464 | kfree(obj_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4465 | } |
| 4466 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4467 | /** Unbinds all inactive objects. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4468 | static int |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4469 | i915_gem_evict_from_inactive_list(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4470 | { |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4471 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4472 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4473 | while (!list_empty(&dev_priv->mm.inactive_list)) { |
| 4474 | struct drm_gem_object *obj; |
| 4475 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4476 | |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 4477 | obj = &list_first_entry(&dev_priv->mm.inactive_list, |
| 4478 | struct drm_i915_gem_object, |
| 4479 | list)->base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4480 | |
| 4481 | ret = i915_gem_object_unbind(obj); |
| 4482 | if (ret != 0) { |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4483 | DRM_ERROR("Error unbinding object: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4484 | return ret; |
| 4485 | } |
| 4486 | } |
| 4487 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4488 | return 0; |
| 4489 | } |
| 4490 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4491 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4492 | i915_gem_idle(struct drm_device *dev) |
| 4493 | { |
| 4494 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4495 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4496 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4497 | mutex_lock(&dev->struct_mutex); |
| 4498 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4499 | if (dev_priv->mm.suspended || |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4500 | (dev_priv->render_ring.gem_object == NULL) || |
| 4501 | (HAS_BSD(dev) && |
| 4502 | dev_priv->bsd_ring.gem_object == NULL)) { |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4503 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4504 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4505 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4506 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4507 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4508 | if (ret) { |
| 4509 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4510 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4511 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4512 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4513 | /* Under UMS, be paranoid and evict. */ |
| 4514 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 4515 | ret = i915_gem_evict_from_inactive_list(dev); |
| 4516 | if (ret) { |
| 4517 | mutex_unlock(&dev->struct_mutex); |
| 4518 | return ret; |
| 4519 | } |
| 4520 | } |
| 4521 | |
| 4522 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4523 | * We need to replace this with a semaphore, or something. |
| 4524 | * And not confound mm.suspended! |
| 4525 | */ |
| 4526 | dev_priv->mm.suspended = 1; |
| 4527 | del_timer(&dev_priv->hangcheck_timer); |
| 4528 | |
| 4529 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4530 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4531 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4532 | mutex_unlock(&dev->struct_mutex); |
| 4533 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4534 | /* Cancel the retire work handler, which should be idle now. */ |
| 4535 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4536 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4537 | return 0; |
| 4538 | } |
| 4539 | |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4540 | /* |
| 4541 | * 965+ support PIPE_CONTROL commands, which provide finer grained control |
| 4542 | * over cache flushing. |
| 4543 | */ |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4544 | static int |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4545 | i915_gem_init_pipe_control(struct drm_device *dev) |
| 4546 | { |
| 4547 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4548 | struct drm_gem_object *obj; |
| 4549 | struct drm_i915_gem_object *obj_priv; |
| 4550 | int ret; |
| 4551 | |
Eric Anholt | 34dc4d4 | 2010-05-07 14:30:03 -0700 | [diff] [blame] | 4552 | obj = i915_gem_alloc_object(dev, 4096); |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4553 | if (obj == NULL) { |
| 4554 | DRM_ERROR("Failed to allocate seqno page\n"); |
| 4555 | ret = -ENOMEM; |
| 4556 | goto err; |
| 4557 | } |
| 4558 | obj_priv = to_intel_bo(obj); |
| 4559 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
| 4560 | |
| 4561 | ret = i915_gem_object_pin(obj, 4096); |
| 4562 | if (ret) |
| 4563 | goto err_unref; |
| 4564 | |
| 4565 | dev_priv->seqno_gfx_addr = obj_priv->gtt_offset; |
| 4566 | dev_priv->seqno_page = kmap(obj_priv->pages[0]); |
| 4567 | if (dev_priv->seqno_page == NULL) |
| 4568 | goto err_unpin; |
| 4569 | |
| 4570 | dev_priv->seqno_obj = obj; |
| 4571 | memset(dev_priv->seqno_page, 0, PAGE_SIZE); |
| 4572 | |
| 4573 | return 0; |
| 4574 | |
| 4575 | err_unpin: |
| 4576 | i915_gem_object_unpin(obj); |
| 4577 | err_unref: |
| 4578 | drm_gem_object_unreference(obj); |
| 4579 | err: |
| 4580 | return ret; |
| 4581 | } |
| 4582 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4583 | |
| 4584 | static void |
Jesse Barnes | e552eb7 | 2010-04-21 11:39:23 -0700 | [diff] [blame] | 4585 | i915_gem_cleanup_pipe_control(struct drm_device *dev) |
| 4586 | { |
| 4587 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4588 | struct drm_gem_object *obj; |
| 4589 | struct drm_i915_gem_object *obj_priv; |
| 4590 | |
| 4591 | obj = dev_priv->seqno_obj; |
| 4592 | obj_priv = to_intel_bo(obj); |
| 4593 | kunmap(obj_priv->pages[0]); |
| 4594 | i915_gem_object_unpin(obj); |
| 4595 | drm_gem_object_unreference(obj); |
| 4596 | dev_priv->seqno_obj = NULL; |
| 4597 | |
| 4598 | dev_priv->seqno_page = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4599 | } |
| 4600 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4601 | int |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4602 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4603 | { |
| 4604 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4605 | int ret; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4606 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4607 | dev_priv->render_ring = render_ring; |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4608 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4609 | if (!I915_NEED_GFX_HWS(dev)) { |
| 4610 | dev_priv->render_ring.status_page.page_addr |
| 4611 | = dev_priv->status_page_dmah->vaddr; |
| 4612 | memset(dev_priv->render_ring.status_page.page_addr, |
| 4613 | 0, PAGE_SIZE); |
| 4614 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4615 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4616 | if (HAS_PIPE_CONTROL(dev)) { |
| 4617 | ret = i915_gem_init_pipe_control(dev); |
| 4618 | if (ret) |
| 4619 | return ret; |
| 4620 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4621 | |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4622 | ret = intel_init_ring_buffer(dev, &dev_priv->render_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4623 | if (ret) |
| 4624 | goto cleanup_pipe_control; |
| 4625 | |
| 4626 | if (HAS_BSD(dev)) { |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4627 | dev_priv->bsd_ring = bsd_ring; |
| 4628 | ret = intel_init_ring_buffer(dev, &dev_priv->bsd_ring); |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4629 | if (ret) |
| 4630 | goto cleanup_render_ring; |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4631 | } |
Chris Wilson | 68f95ba | 2010-05-27 13:18:22 +0100 | [diff] [blame] | 4632 | |
| 4633 | return 0; |
| 4634 | |
| 4635 | cleanup_render_ring: |
| 4636 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); |
| 4637 | cleanup_pipe_control: |
| 4638 | if (HAS_PIPE_CONTROL(dev)) |
| 4639 | i915_gem_cleanup_pipe_control(dev); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4640 | return ret; |
| 4641 | } |
| 4642 | |
| 4643 | void |
| 4644 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4645 | { |
| 4646 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4647 | |
| 4648 | intel_cleanup_ring_buffer(dev, &dev_priv->render_ring); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4649 | if (HAS_BSD(dev)) |
| 4650 | intel_cleanup_ring_buffer(dev, &dev_priv->bsd_ring); |
Zou Nan hai | 8187a2b | 2010-05-21 09:08:55 +0800 | [diff] [blame] | 4651 | if (HAS_PIPE_CONTROL(dev)) |
| 4652 | i915_gem_cleanup_pipe_control(dev); |
| 4653 | } |
| 4654 | |
| 4655 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4656 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4657 | struct drm_file *file_priv) |
| 4658 | { |
| 4659 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4660 | int ret; |
| 4661 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4662 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4663 | return 0; |
| 4664 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4665 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4666 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4667 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4668 | } |
| 4669 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4670 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4671 | dev_priv->mm.suspended = 0; |
| 4672 | |
| 4673 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4674 | if (ret != 0) { |
| 4675 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4676 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4677 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4678 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4679 | spin_lock(&dev_priv->mm.active_list_lock); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4680 | BUG_ON(!list_empty(&dev_priv->render_ring.active_list)); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4681 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.active_list)); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4682 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 4683 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4684 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4685 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4686 | BUG_ON(!list_empty(&dev_priv->render_ring.request_list)); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4687 | BUG_ON(HAS_BSD(dev) && !list_empty(&dev_priv->bsd_ring.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4688 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4689 | |
| 4690 | drm_irq_install(dev); |
| 4691 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4692 | return 0; |
| 4693 | } |
| 4694 | |
| 4695 | int |
| 4696 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4697 | struct drm_file *file_priv) |
| 4698 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4699 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4700 | return 0; |
| 4701 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4702 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4703 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4704 | } |
| 4705 | |
| 4706 | void |
| 4707 | i915_gem_lastclose(struct drm_device *dev) |
| 4708 | { |
| 4709 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4710 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4711 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4712 | return; |
| 4713 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4714 | ret = i915_gem_idle(dev); |
| 4715 | if (ret) |
| 4716 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4717 | } |
| 4718 | |
| 4719 | void |
| 4720 | i915_gem_load(struct drm_device *dev) |
| 4721 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4722 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4723 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4724 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4725 | spin_lock_init(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4726 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 4727 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4728 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4729 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4730 | INIT_LIST_HEAD(&dev_priv->render_ring.active_list); |
| 4731 | INIT_LIST_HEAD(&dev_priv->render_ring.request_list); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4732 | if (HAS_BSD(dev)) { |
| 4733 | INIT_LIST_HEAD(&dev_priv->bsd_ring.active_list); |
| 4734 | INIT_LIST_HEAD(&dev_priv->bsd_ring.request_list); |
| 4735 | } |
Daniel Vetter | 007cc8a | 2010-04-28 11:02:31 +0200 | [diff] [blame] | 4736 | for (i = 0; i < 16; i++) |
| 4737 | INIT_LIST_HEAD(&dev_priv->fence_regs[i].lru_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4738 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4739 | i915_gem_retire_work_handler); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4740 | spin_lock(&shrink_list_lock); |
| 4741 | list_add(&dev_priv->mm.shrink_list, &shrink_list); |
| 4742 | spin_unlock(&shrink_list_lock); |
| 4743 | |
Dave Airlie | 9440012 | 2010-07-20 13:15:31 +1000 | [diff] [blame^] | 4744 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ |
| 4745 | if (IS_GEN3(dev)) { |
| 4746 | u32 tmp = I915_READ(MI_ARB_STATE); |
| 4747 | if (!(tmp & MI_ARB_C3_LP_WRITE_ENABLE)) { |
| 4748 | /* arb state is a masked write, so set bit + bit in mask */ |
| 4749 | tmp = MI_ARB_C3_LP_WRITE_ENABLE | (MI_ARB_C3_LP_WRITE_ENABLE << MI_ARB_MASK_SHIFT); |
| 4750 | I915_WRITE(MI_ARB_STATE, tmp); |
| 4751 | } |
| 4752 | } |
| 4753 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4754 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4755 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4756 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4757 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 4758 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4759 | dev_priv->num_fence_regs = 16; |
| 4760 | else |
| 4761 | dev_priv->num_fence_regs = 8; |
| 4762 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4763 | /* Initialize fence registers to zero */ |
| 4764 | if (IS_I965G(dev)) { |
| 4765 | for (i = 0; i < 16; i++) |
| 4766 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
| 4767 | } else { |
| 4768 | for (i = 0; i < 8; i++) |
| 4769 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4770 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4771 | for (i = 0; i < 8; i++) |
| 4772 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
| 4773 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4774 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4775 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4776 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4777 | |
| 4778 | /* |
| 4779 | * Create a physically contiguous memory object for this object |
| 4780 | * e.g. for cursor + overlay regs |
| 4781 | */ |
| 4782 | int i915_gem_init_phys_object(struct drm_device *dev, |
| 4783 | int id, int size) |
| 4784 | { |
| 4785 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4786 | struct drm_i915_gem_phys_object *phys_obj; |
| 4787 | int ret; |
| 4788 | |
| 4789 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4790 | return 0; |
| 4791 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4792 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4793 | if (!phys_obj) |
| 4794 | return -ENOMEM; |
| 4795 | |
| 4796 | phys_obj->id = id; |
| 4797 | |
Zhenyu Wang | e6be8d9 | 2010-01-05 11:25:05 +0800 | [diff] [blame] | 4798 | phys_obj->handle = drm_pci_alloc(dev, size, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4799 | if (!phys_obj->handle) { |
| 4800 | ret = -ENOMEM; |
| 4801 | goto kfree_obj; |
| 4802 | } |
| 4803 | #ifdef CONFIG_X86 |
| 4804 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4805 | #endif |
| 4806 | |
| 4807 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4808 | |
| 4809 | return 0; |
| 4810 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4811 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4812 | return ret; |
| 4813 | } |
| 4814 | |
| 4815 | void i915_gem_free_phys_object(struct drm_device *dev, int id) |
| 4816 | { |
| 4817 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4818 | struct drm_i915_gem_phys_object *phys_obj; |
| 4819 | |
| 4820 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4821 | return; |
| 4822 | |
| 4823 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4824 | if (phys_obj->cur_obj) { |
| 4825 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4826 | } |
| 4827 | |
| 4828 | #ifdef CONFIG_X86 |
| 4829 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4830 | #endif |
| 4831 | drm_pci_free(dev, phys_obj->handle); |
| 4832 | kfree(phys_obj); |
| 4833 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4834 | } |
| 4835 | |
| 4836 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4837 | { |
| 4838 | int i; |
| 4839 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4840 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4841 | i915_gem_free_phys_object(dev, i); |
| 4842 | } |
| 4843 | |
| 4844 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 4845 | struct drm_gem_object *obj) |
| 4846 | { |
| 4847 | struct drm_i915_gem_object *obj_priv; |
| 4848 | int i; |
| 4849 | int ret; |
| 4850 | int page_count; |
| 4851 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4852 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4853 | if (!obj_priv->phys_obj) |
| 4854 | return; |
| 4855 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4856 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4857 | if (ret) |
| 4858 | goto out; |
| 4859 | |
| 4860 | page_count = obj->size / PAGE_SIZE; |
| 4861 | |
| 4862 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4863 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4864 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4865 | |
| 4866 | memcpy(dst, src, PAGE_SIZE); |
| 4867 | kunmap_atomic(dst, KM_USER0); |
| 4868 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4869 | drm_clflush_pages(obj_priv->pages, page_count); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4870 | drm_agp_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4871 | |
| 4872 | i915_gem_object_put_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4873 | out: |
| 4874 | obj_priv->phys_obj->cur_obj = NULL; |
| 4875 | obj_priv->phys_obj = NULL; |
| 4876 | } |
| 4877 | |
| 4878 | int |
| 4879 | i915_gem_attach_phys_object(struct drm_device *dev, |
| 4880 | struct drm_gem_object *obj, int id) |
| 4881 | { |
| 4882 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4883 | struct drm_i915_gem_object *obj_priv; |
| 4884 | int ret = 0; |
| 4885 | int page_count; |
| 4886 | int i; |
| 4887 | |
| 4888 | if (id > I915_MAX_PHYS_OBJECT) |
| 4889 | return -EINVAL; |
| 4890 | |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4891 | obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4892 | |
| 4893 | if (obj_priv->phys_obj) { |
| 4894 | if (obj_priv->phys_obj->id == id) |
| 4895 | return 0; |
| 4896 | i915_gem_detach_phys_object(dev, obj); |
| 4897 | } |
| 4898 | |
| 4899 | |
| 4900 | /* create a new object */ |
| 4901 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4902 | ret = i915_gem_init_phys_object(dev, id, |
| 4903 | obj->size); |
| 4904 | if (ret) { |
Linus Torvalds | aeb565d | 2009-01-26 10:01:53 -0800 | [diff] [blame] | 4905 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4906 | goto out; |
| 4907 | } |
| 4908 | } |
| 4909 | |
| 4910 | /* bind to the object */ |
| 4911 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4912 | obj_priv->phys_obj->cur_obj = obj; |
| 4913 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4914 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4915 | if (ret) { |
| 4916 | DRM_ERROR("failed to get page list\n"); |
| 4917 | goto out; |
| 4918 | } |
| 4919 | |
| 4920 | page_count = obj->size / PAGE_SIZE; |
| 4921 | |
| 4922 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4923 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4924 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4925 | |
| 4926 | memcpy(dst, src, PAGE_SIZE); |
| 4927 | kunmap_atomic(src, KM_USER0); |
| 4928 | } |
| 4929 | |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4930 | i915_gem_object_put_pages(obj); |
| 4931 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4932 | return 0; |
| 4933 | out: |
| 4934 | return ret; |
| 4935 | } |
| 4936 | |
| 4937 | static int |
| 4938 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 4939 | struct drm_i915_gem_pwrite *args, |
| 4940 | struct drm_file *file_priv) |
| 4941 | { |
Daniel Vetter | 23010e4 | 2010-03-08 13:35:02 +0100 | [diff] [blame] | 4942 | struct drm_i915_gem_object *obj_priv = to_intel_bo(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4943 | void *obj_addr; |
| 4944 | int ret; |
| 4945 | char __user *user_data; |
| 4946 | |
| 4947 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 4948 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; |
| 4949 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4950 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4951 | ret = copy_from_user(obj_addr, user_data, args->size); |
| 4952 | if (ret) |
| 4953 | return -EFAULT; |
| 4954 | |
| 4955 | drm_agp_chipset_flush(dev); |
| 4956 | return 0; |
| 4957 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 4958 | |
| 4959 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) |
| 4960 | { |
| 4961 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 4962 | |
| 4963 | /* Clean up our request list when the client is going away, so that |
| 4964 | * later retire_requests won't dereference our soon-to-be-gone |
| 4965 | * file_priv. |
| 4966 | */ |
| 4967 | mutex_lock(&dev->struct_mutex); |
| 4968 | while (!list_empty(&i915_file_priv->mm.request_list)) |
| 4969 | list_del_init(i915_file_priv->mm.request_list.next); |
| 4970 | mutex_unlock(&dev->struct_mutex); |
| 4971 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4972 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4973 | static int |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4974 | i915_gpu_is_active(struct drm_device *dev) |
| 4975 | { |
| 4976 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4977 | int lists_empty; |
| 4978 | |
| 4979 | spin_lock(&dev_priv->mm.active_list_lock); |
| 4980 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 4981 | list_empty(&dev_priv->render_ring.active_list); |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 4982 | if (HAS_BSD(dev)) |
| 4983 | lists_empty &= list_empty(&dev_priv->bsd_ring.active_list); |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 4984 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 4985 | |
| 4986 | return !lists_empty; |
| 4987 | } |
| 4988 | |
| 4989 | static int |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4990 | i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask) |
| 4991 | { |
| 4992 | drm_i915_private_t *dev_priv, *next_dev; |
| 4993 | struct drm_i915_gem_object *obj_priv, *next_obj; |
| 4994 | int cnt = 0; |
| 4995 | int would_deadlock = 1; |
| 4996 | |
| 4997 | /* "fast-path" to count number of available objects */ |
| 4998 | if (nr_to_scan == 0) { |
| 4999 | spin_lock(&shrink_list_lock); |
| 5000 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 5001 | struct drm_device *dev = dev_priv->dev; |
| 5002 | |
| 5003 | if (mutex_trylock(&dev->struct_mutex)) { |
| 5004 | list_for_each_entry(obj_priv, |
| 5005 | &dev_priv->mm.inactive_list, |
| 5006 | list) |
| 5007 | cnt++; |
| 5008 | mutex_unlock(&dev->struct_mutex); |
| 5009 | } |
| 5010 | } |
| 5011 | spin_unlock(&shrink_list_lock); |
| 5012 | |
| 5013 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 5014 | } |
| 5015 | |
| 5016 | spin_lock(&shrink_list_lock); |
| 5017 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5018 | rescan: |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5019 | /* first scan for clean buffers */ |
| 5020 | list_for_each_entry_safe(dev_priv, next_dev, |
| 5021 | &shrink_list, mm.shrink_list) { |
| 5022 | struct drm_device *dev = dev_priv->dev; |
| 5023 | |
| 5024 | if (! mutex_trylock(&dev->struct_mutex)) |
| 5025 | continue; |
| 5026 | |
| 5027 | spin_unlock(&shrink_list_lock); |
Zou Nan hai | 852835f | 2010-05-21 09:08:56 +0800 | [diff] [blame] | 5028 | i915_gem_retire_requests(dev, &dev_priv->render_ring); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5029 | |
Zou Nan hai | d1b851f | 2010-05-21 09:08:57 +0800 | [diff] [blame] | 5030 | if (HAS_BSD(dev)) |
| 5031 | i915_gem_retire_requests(dev, &dev_priv->bsd_ring); |
| 5032 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5033 | list_for_each_entry_safe(obj_priv, next_obj, |
| 5034 | &dev_priv->mm.inactive_list, |
| 5035 | list) { |
| 5036 | if (i915_gem_object_is_purgeable(obj_priv)) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 5037 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5038 | if (--nr_to_scan <= 0) |
| 5039 | break; |
| 5040 | } |
| 5041 | } |
| 5042 | |
| 5043 | spin_lock(&shrink_list_lock); |
| 5044 | mutex_unlock(&dev->struct_mutex); |
| 5045 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 5046 | would_deadlock = 0; |
| 5047 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5048 | if (nr_to_scan <= 0) |
| 5049 | break; |
| 5050 | } |
| 5051 | |
| 5052 | /* second pass, evict/count anything still on the inactive list */ |
| 5053 | list_for_each_entry_safe(dev_priv, next_dev, |
| 5054 | &shrink_list, mm.shrink_list) { |
| 5055 | struct drm_device *dev = dev_priv->dev; |
| 5056 | |
| 5057 | if (! mutex_trylock(&dev->struct_mutex)) |
| 5058 | continue; |
| 5059 | |
| 5060 | spin_unlock(&shrink_list_lock); |
| 5061 | |
| 5062 | list_for_each_entry_safe(obj_priv, next_obj, |
| 5063 | &dev_priv->mm.inactive_list, |
| 5064 | list) { |
| 5065 | if (nr_to_scan > 0) { |
Daniel Vetter | a8089e8 | 2010-04-09 19:05:09 +0000 | [diff] [blame] | 5066 | i915_gem_object_unbind(&obj_priv->base); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5067 | nr_to_scan--; |
| 5068 | } else |
| 5069 | cnt++; |
| 5070 | } |
| 5071 | |
| 5072 | spin_lock(&shrink_list_lock); |
| 5073 | mutex_unlock(&dev->struct_mutex); |
| 5074 | |
| 5075 | would_deadlock = 0; |
| 5076 | } |
| 5077 | |
Chris Wilson | 1637ef4 | 2010-04-20 17:10:35 +0100 | [diff] [blame] | 5078 | if (nr_to_scan) { |
| 5079 | int active = 0; |
| 5080 | |
| 5081 | /* |
| 5082 | * We are desperate for pages, so as a last resort, wait |
| 5083 | * for the GPU to finish and discard whatever we can. |
| 5084 | * This has a dramatic impact to reduce the number of |
| 5085 | * OOM-killer events whilst running the GPU aggressively. |
| 5086 | */ |
| 5087 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 5088 | struct drm_device *dev = dev_priv->dev; |
| 5089 | |
| 5090 | if (!mutex_trylock(&dev->struct_mutex)) |
| 5091 | continue; |
| 5092 | |
| 5093 | spin_unlock(&shrink_list_lock); |
| 5094 | |
| 5095 | if (i915_gpu_is_active(dev)) { |
| 5096 | i915_gpu_idle(dev); |
| 5097 | active++; |
| 5098 | } |
| 5099 | |
| 5100 | spin_lock(&shrink_list_lock); |
| 5101 | mutex_unlock(&dev->struct_mutex); |
| 5102 | } |
| 5103 | |
| 5104 | if (active) |
| 5105 | goto rescan; |
| 5106 | } |
| 5107 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5108 | spin_unlock(&shrink_list_lock); |
| 5109 | |
| 5110 | if (would_deadlock) |
| 5111 | return -1; |
| 5112 | else if (cnt > 0) |
| 5113 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 5114 | else |
| 5115 | return 0; |
| 5116 | } |
| 5117 | |
| 5118 | static struct shrinker shrinker = { |
| 5119 | .shrink = i915_gem_shrink, |
| 5120 | .seeks = DEFAULT_SEEKS, |
| 5121 | }; |
| 5122 | |
| 5123 | __init void |
| 5124 | i915_gem_shrinker_init(void) |
| 5125 | { |
| 5126 | register_shrinker(&shrinker); |
| 5127 | } |
| 5128 | |
| 5129 | __exit void |
| 5130 | i915_gem_shrinker_exit(void) |
| 5131 | { |
| 5132 | unregister_shrinker(&shrinker); |
| 5133 | } |