blob: f6653da0ee16ed2c0cc5a7634f2fa9bb02a483aa [file] [log] [blame]
Matt Porterc2dde5f2012-08-22 21:09:34 -04001/*
2 * TI EDMA DMA engine driver
3 *
4 * Copyright 2012 Texas Instruments
5 *
6 * This program is free software; you can redistribute it and/or
7 * modify it under the terms of the GNU General Public License as
8 * published by the Free Software Foundation version 2.
9 *
10 * This program is distributed "as is" WITHOUT ANY WARRANTY of any
11 * kind, whether express or implied; without even the implied warranty
12 * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 */
15
16#include <linux/dmaengine.h>
17#include <linux/dma-mapping.h>
Lad, Prabhakarb7a4fd52015-02-04 13:03:27 +000018#include <linux/edma.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040019#include <linux/err.h>
20#include <linux/init.h>
21#include <linux/interrupt.h>
22#include <linux/list.h>
23#include <linux/module.h>
24#include <linux/platform_device.h>
25#include <linux/slab.h>
26#include <linux/spinlock.h>
Peter Ujfalusied646102014-07-31 13:12:38 +030027#include <linux/of.h>
Peter Ujfalusidc9b60552015-10-14 14:42:47 +030028#include <linux/of_dma.h>
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +030029#include <linux/of_irq.h>
30#include <linux/of_address.h>
31#include <linux/of_device.h>
32#include <linux/pm_runtime.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040033
Matt Porter3ad7a422013-03-06 11:15:31 -050034#include <linux/platform_data/edma.h>
Matt Porterc2dde5f2012-08-22 21:09:34 -040035
36#include "dmaengine.h"
37#include "virt-dma.h"
38
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +030039/* Offsets matching "struct edmacc_param" */
40#define PARM_OPT 0x00
41#define PARM_SRC 0x04
42#define PARM_A_B_CNT 0x08
43#define PARM_DST 0x0c
44#define PARM_SRC_DST_BIDX 0x10
45#define PARM_LINK_BCNTRLD 0x14
46#define PARM_SRC_DST_CIDX 0x18
47#define PARM_CCNT 0x1c
48
49#define PARM_SIZE 0x20
50
51/* Offsets for EDMA CC global channel registers and their shadows */
52#define SH_ER 0x00 /* 64 bits */
53#define SH_ECR 0x08 /* 64 bits */
54#define SH_ESR 0x10 /* 64 bits */
55#define SH_CER 0x18 /* 64 bits */
56#define SH_EER 0x20 /* 64 bits */
57#define SH_EECR 0x28 /* 64 bits */
58#define SH_EESR 0x30 /* 64 bits */
59#define SH_SER 0x38 /* 64 bits */
60#define SH_SECR 0x40 /* 64 bits */
61#define SH_IER 0x50 /* 64 bits */
62#define SH_IECR 0x58 /* 64 bits */
63#define SH_IESR 0x60 /* 64 bits */
64#define SH_IPR 0x68 /* 64 bits */
65#define SH_ICR 0x70 /* 64 bits */
66#define SH_IEVAL 0x78
67#define SH_QER 0x80
68#define SH_QEER 0x84
69#define SH_QEECR 0x88
70#define SH_QEESR 0x8c
71#define SH_QSER 0x90
72#define SH_QSECR 0x94
73#define SH_SIZE 0x200
74
75/* Offsets for EDMA CC global registers */
76#define EDMA_REV 0x0000
77#define EDMA_CCCFG 0x0004
78#define EDMA_QCHMAP 0x0200 /* 8 registers */
79#define EDMA_DMAQNUM 0x0240 /* 8 registers (4 on OMAP-L1xx) */
80#define EDMA_QDMAQNUM 0x0260
81#define EDMA_QUETCMAP 0x0280
82#define EDMA_QUEPRI 0x0284
83#define EDMA_EMR 0x0300 /* 64 bits */
84#define EDMA_EMCR 0x0308 /* 64 bits */
85#define EDMA_QEMR 0x0310
86#define EDMA_QEMCR 0x0314
87#define EDMA_CCERR 0x0318
88#define EDMA_CCERRCLR 0x031c
89#define EDMA_EEVAL 0x0320
90#define EDMA_DRAE 0x0340 /* 4 x 64 bits*/
91#define EDMA_QRAE 0x0380 /* 4 registers */
92#define EDMA_QUEEVTENTRY 0x0400 /* 2 x 16 registers */
93#define EDMA_QSTAT 0x0600 /* 2 registers */
94#define EDMA_QWMTHRA 0x0620
95#define EDMA_QWMTHRB 0x0624
96#define EDMA_CCSTAT 0x0640
97
98#define EDMA_M 0x1000 /* global channel registers */
99#define EDMA_ECR 0x1008
100#define EDMA_ECRH 0x100C
101#define EDMA_SHADOW0 0x2000 /* 4 shadow regions */
102#define EDMA_PARM 0x4000 /* PaRAM entries */
103
104#define PARM_OFFSET(param_no) (EDMA_PARM + ((param_no) << 5))
105
106#define EDMA_DCHMAP 0x0100 /* 64 registers */
107
108/* CCCFG register */
109#define GET_NUM_DMACH(x) (x & 0x7) /* bits 0-2 */
110#define GET_NUM_PAENTRY(x) ((x & 0x7000) >> 12) /* bits 12-14 */
111#define GET_NUM_EVQUE(x) ((x & 0x70000) >> 16) /* bits 16-18 */
112#define GET_NUM_REGN(x) ((x & 0x300000) >> 20) /* bits 20-21 */
113#define CHMAP_EXIST BIT(24)
114
Matt Porterc2dde5f2012-08-22 21:09:34 -0400115/*
Joel Fernandes2abd5f12013-09-23 18:05:15 -0500116 * Max of 20 segments per channel to conserve PaRAM slots
117 * Also note that MAX_NR_SG should be atleast the no.of periods
118 * that are required for ASoC, otherwise DMA prep calls will
119 * fail. Today davinci-pcm is the only user of this driver and
120 * requires atleast 17 slots, so we setup the default to 20.
121 */
122#define MAX_NR_SG 20
Matt Porterc2dde5f2012-08-22 21:09:34 -0400123#define EDMA_MAX_SLOTS MAX_NR_SG
124#define EDMA_DESCRIPTORS 16
125
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300126#define EDMA_CHANNEL_ANY -1 /* for edma_alloc_channel() */
127#define EDMA_SLOT_ANY -1 /* for edma_alloc_slot() */
128#define EDMA_CONT_PARAMS_ANY 1001
129#define EDMA_CONT_PARAMS_FIXED_EXACT 1002
130#define EDMA_CONT_PARAMS_FIXED_NOT_EXACT 1003
131
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300132/* PaRAM slots are laid out like this */
133struct edmacc_param {
134 u32 opt;
135 u32 src;
136 u32 a_b_cnt;
137 u32 dst;
138 u32 src_dst_bidx;
139 u32 link_bcntrld;
140 u32 src_dst_cidx;
141 u32 ccnt;
142} __packed;
143
144/* fields in edmacc_param.opt */
145#define SAM BIT(0)
146#define DAM BIT(1)
147#define SYNCDIM BIT(2)
148#define STATIC BIT(3)
149#define EDMA_FWID (0x07 << 8)
150#define TCCMODE BIT(11)
151#define EDMA_TCC(t) ((t) << 12)
152#define TCINTEN BIT(20)
153#define ITCINTEN BIT(21)
154#define TCCHEN BIT(22)
155#define ITCCHEN BIT(23)
156
157/*ch_status parameter of callback function possible values*/
158#define EDMA_DMA_COMPLETE 1
159#define EDMA_DMA_CC_ERROR 2
160#define EDMA_DMA_TC1_ERROR 3
161#define EDMA_DMA_TC2_ERROR 4
162
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500163struct edma_pset {
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500164 u32 len;
165 dma_addr_t addr;
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500166 struct edmacc_param param;
167};
168
Matt Porterc2dde5f2012-08-22 21:09:34 -0400169struct edma_desc {
170 struct virt_dma_desc vdesc;
171 struct list_head node;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -0500172 enum dma_transfer_direction direction;
Joel Fernandes50a9c702013-10-31 16:31:23 -0500173 int cyclic;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400174 int absync;
175 int pset_nr;
Thomas Gleixner740b41f2014-04-28 14:34:11 -0500176 struct edma_chan *echan;
Joel Fernandes04361d82014-04-28 15:19:31 -0500177 int processed;
178
179 /*
180 * The following 4 elements are used for residue accounting.
181 *
182 * - processed_stat: the number of SG elements we have traversed
183 * so far to cover accounting. This is updated directly to processed
184 * during edma_callback and is always <= processed, because processed
185 * refers to the number of pending transfer (programmed to EDMA
186 * controller), where as processed_stat tracks number of transfers
187 * accounted for so far.
188 *
189 * - residue: The amount of bytes we have left to transfer for this desc
190 *
191 * - residue_stat: The residue in bytes of data we have covered
192 * so far for accounting. This is updated directly to residue
193 * during callbacks to keep it current.
194 *
195 * - sg_len: Tracks the length of the current intermediate transfer,
196 * this is required to update the residue during intermediate transfer
197 * completion callback.
198 */
199 int processed_stat;
200 u32 sg_len;
201 u32 residue;
202 u32 residue_stat;
203
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -0500204 struct edma_pset pset[0];
Matt Porterc2dde5f2012-08-22 21:09:34 -0400205};
206
207struct edma_cc;
208
209struct edma_chan {
210 struct virt_dma_chan vchan;
211 struct list_head node;
212 struct edma_desc *edesc;
213 struct edma_cc *ecc;
214 int ch_num;
215 bool alloced;
216 int slot[EDMA_MAX_SLOTS];
Joel Fernandesc5f47992013-08-29 18:05:43 -0500217 int missed;
Matt Porter661f7cb2013-01-10 13:41:04 -0500218 struct dma_slave_config cfg;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400219};
220
221struct edma_cc {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300222 struct device *dev;
223 struct edma_soc_info *info;
224 void __iomem *base;
225 int id;
226
227 /* eDMA3 resource information */
228 unsigned num_channels;
229 unsigned num_region;
230 unsigned num_slots;
231 unsigned num_tc;
232 enum dma_event_q default_queue;
233
234 bool unused_chan_list_done;
235 /* The edma_inuse bit for each PaRAM slot is clear unless the
236 * channel is in use ... by ARM or DSP, for QDMA, or whatever.
237 */
Peter Ujfalusicb782052015-10-14 14:42:54 +0300238 unsigned long *edma_inuse;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300239
240 /* The edma_unused bit for each channel is clear unless
241 * it is not being used on this platform. It uses a bit
242 * of SOC-specific initialization code.
243 */
Peter Ujfalusicb782052015-10-14 14:42:54 +0300244 unsigned long *edma_unused;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300245
246 struct dma_interrupt_data {
247 void (*callback)(unsigned channel, unsigned short ch_status,
248 void *data);
249 void *data;
Peter Ujfalusicb782052015-10-14 14:42:54 +0300250 } *intr_data;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300251
Matt Porterc2dde5f2012-08-22 21:09:34 -0400252 struct dma_device dma_slave;
Peter Ujfalusicb782052015-10-14 14:42:54 +0300253 struct edma_chan *slave_chans;
Matt Porterc2dde5f2012-08-22 21:09:34 -0400254 int dummy_slot;
255};
256
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300257/* dummy param set used to (re)initialize parameter RAM slots */
258static const struct edmacc_param dummy_paramset = {
259 .link_bcntrld = 0xffff,
260 .ccnt = 1,
261};
262
263static const struct of_device_id edma_of_ids[] = {
264 { .compatible = "ti,edma3", },
265 {}
266};
267
268static inline unsigned int edma_read(struct edma_cc *ecc, int offset)
269{
270 return (unsigned int)__raw_readl(ecc->base + offset);
271}
272
273static inline void edma_write(struct edma_cc *ecc, int offset, int val)
274{
275 __raw_writel(val, ecc->base + offset);
276}
277
278static inline void edma_modify(struct edma_cc *ecc, int offset, unsigned and,
279 unsigned or)
280{
281 unsigned val = edma_read(ecc, offset);
282
283 val &= and;
284 val |= or;
285 edma_write(ecc, offset, val);
286}
287
288static inline void edma_and(struct edma_cc *ecc, int offset, unsigned and)
289{
290 unsigned val = edma_read(ecc, offset);
291
292 val &= and;
293 edma_write(ecc, offset, val);
294}
295
296static inline void edma_or(struct edma_cc *ecc, int offset, unsigned or)
297{
298 unsigned val = edma_read(ecc, offset);
299
300 val |= or;
301 edma_write(ecc, offset, val);
302}
303
304static inline unsigned int edma_read_array(struct edma_cc *ecc, int offset,
305 int i)
306{
307 return edma_read(ecc, offset + (i << 2));
308}
309
310static inline void edma_write_array(struct edma_cc *ecc, int offset, int i,
311 unsigned val)
312{
313 edma_write(ecc, offset + (i << 2), val);
314}
315
316static inline void edma_modify_array(struct edma_cc *ecc, int offset, int i,
317 unsigned and, unsigned or)
318{
319 edma_modify(ecc, offset + (i << 2), and, or);
320}
321
322static inline void edma_or_array(struct edma_cc *ecc, int offset, int i,
323 unsigned or)
324{
325 edma_or(ecc, offset + (i << 2), or);
326}
327
328static inline void edma_or_array2(struct edma_cc *ecc, int offset, int i, int j,
329 unsigned or)
330{
331 edma_or(ecc, offset + ((i * 2 + j) << 2), or);
332}
333
334static inline void edma_write_array2(struct edma_cc *ecc, int offset, int i,
335 int j, unsigned val)
336{
337 edma_write(ecc, offset + ((i * 2 + j) << 2), val);
338}
339
340static inline unsigned int edma_shadow0_read(struct edma_cc *ecc, int offset)
341{
342 return edma_read(ecc, EDMA_SHADOW0 + offset);
343}
344
345static inline unsigned int edma_shadow0_read_array(struct edma_cc *ecc,
346 int offset, int i)
347{
348 return edma_read(ecc, EDMA_SHADOW0 + offset + (i << 2));
349}
350
351static inline void edma_shadow0_write(struct edma_cc *ecc, int offset,
352 unsigned val)
353{
354 edma_write(ecc, EDMA_SHADOW0 + offset, val);
355}
356
357static inline void edma_shadow0_write_array(struct edma_cc *ecc, int offset,
358 int i, unsigned val)
359{
360 edma_write(ecc, EDMA_SHADOW0 + offset + (i << 2), val);
361}
362
363static inline unsigned int edma_parm_read(struct edma_cc *ecc, int offset,
364 int param_no)
365{
366 return edma_read(ecc, EDMA_PARM + offset + (param_no << 5));
367}
368
369static inline void edma_parm_write(struct edma_cc *ecc, int offset,
370 int param_no, unsigned val)
371{
372 edma_write(ecc, EDMA_PARM + offset + (param_no << 5), val);
373}
374
375static inline void edma_parm_modify(struct edma_cc *ecc, int offset,
376 int param_no, unsigned and, unsigned or)
377{
378 edma_modify(ecc, EDMA_PARM + offset + (param_no << 5), and, or);
379}
380
381static inline void edma_parm_and(struct edma_cc *ecc, int offset, int param_no,
382 unsigned and)
383{
384 edma_and(ecc, EDMA_PARM + offset + (param_no << 5), and);
385}
386
387static inline void edma_parm_or(struct edma_cc *ecc, int offset, int param_no,
388 unsigned or)
389{
390 edma_or(ecc, EDMA_PARM + offset + (param_no << 5), or);
391}
392
393static inline void set_bits(int offset, int len, unsigned long *p)
394{
395 for (; len > 0; len--)
396 set_bit(offset + (len - 1), p);
397}
398
399static inline void clear_bits(int offset, int len, unsigned long *p)
400{
401 for (; len > 0; len--)
402 clear_bit(offset + (len - 1), p);
403}
404
405static void edma_map_dmach_to_queue(struct edma_cc *ecc, unsigned ch_no,
406 enum dma_event_q queue_no)
407{
408 int bit = (ch_no & 0x7) * 4;
409
410 /* default to low priority queue */
411 if (queue_no == EVENTQ_DEFAULT)
412 queue_no = ecc->default_queue;
413
414 queue_no &= 7;
415 edma_modify_array(ecc, EDMA_DMAQNUM, (ch_no >> 3), ~(0x7 << bit),
416 queue_no << bit);
417}
418
419static void edma_assign_priority_to_queue(struct edma_cc *ecc, int queue_no,
420 int priority)
421{
422 int bit = queue_no * 4;
423
424 edma_modify(ecc, EDMA_QUEPRI, ~(0x7 << bit), ((priority & 0x7) << bit));
425}
426
427static void edma_direct_dmach_to_param_mapping(struct edma_cc *ecc)
428{
429 int i;
430
431 for (i = 0; i < ecc->num_channels; i++)
432 edma_write_array(ecc, EDMA_DCHMAP, i, (i << 5));
433}
434
435static int prepare_unused_channel_list(struct device *dev, void *data)
436{
437 struct platform_device *pdev = to_platform_device(dev);
438 struct edma_cc *ecc = data;
Peter Ujfalusicb782052015-10-14 14:42:54 +0300439 int dma_req_min = EDMA_CTLR_CHAN(ecc->id, 0);
440 int dma_req_max = dma_req_min + ecc->num_channels;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300441 int i, count;
442 struct of_phandle_args dma_spec;
443
444 if (dev->of_node) {
445 struct platform_device *dma_pdev;
446
447 count = of_property_count_strings(dev->of_node, "dma-names");
448 if (count < 0)
449 return 0;
450 for (i = 0; i < count; i++) {
451 if (of_parse_phandle_with_args(dev->of_node, "dmas",
452 "#dma-cells", i,
453 &dma_spec))
454 continue;
455
456 if (!of_match_node(edma_of_ids, dma_spec.np)) {
457 of_node_put(dma_spec.np);
458 continue;
459 }
460
461 dma_pdev = of_find_device_by_node(dma_spec.np);
462 if (&dma_pdev->dev != ecc->dev)
463 continue;
464
465 clear_bit(EDMA_CHAN_SLOT(dma_spec.args[0]),
466 ecc->edma_unused);
467 of_node_put(dma_spec.np);
468 }
469 return 0;
470 }
471
472 /* For non-OF case */
473 for (i = 0; i < pdev->num_resources; i++) {
474 struct resource *res = &pdev->resource[i];
Peter Ujfalusicb782052015-10-14 14:42:54 +0300475 int dma_req;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300476
Peter Ujfalusicb782052015-10-14 14:42:54 +0300477 if (!(res->flags & IORESOURCE_DMA))
478 continue;
479
480 dma_req = (int)res->start;
481 if (dma_req >= dma_req_min && dma_req < dma_req_max)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300482 clear_bit(EDMA_CHAN_SLOT(pdev->resource[i].start),
483 ecc->edma_unused);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300484 }
485
486 return 0;
487}
488
489static void edma_setup_interrupt(struct edma_cc *ecc, unsigned lch,
490 void (*callback)(unsigned channel, u16 ch_status, void *data),
491 void *data)
492{
493 lch = EDMA_CHAN_SLOT(lch);
494
495 if (!callback)
496 edma_shadow0_write_array(ecc, SH_IECR, lch >> 5,
497 BIT(lch & 0x1f));
498
499 ecc->intr_data[lch].callback = callback;
500 ecc->intr_data[lch].data = data;
501
502 if (callback) {
503 edma_shadow0_write_array(ecc, SH_ICR, lch >> 5,
504 BIT(lch & 0x1f));
505 edma_shadow0_write_array(ecc, SH_IESR, lch >> 5,
506 BIT(lch & 0x1f));
507 }
508}
509
510/*
511 * paRAM management functions
512 */
513
514/**
515 * edma_write_slot - write parameter RAM data for slot
516 * @ecc: pointer to edma_cc struct
517 * @slot: number of parameter RAM slot being modified
518 * @param: data to be written into parameter RAM slot
519 *
520 * Use this to assign all parameters of a transfer at once. This
521 * allows more efficient setup of transfers than issuing multiple
522 * calls to set up those parameters in small pieces, and provides
523 * complete control over all transfer options.
524 */
525static void edma_write_slot(struct edma_cc *ecc, unsigned slot,
526 const struct edmacc_param *param)
527{
528 slot = EDMA_CHAN_SLOT(slot);
529 if (slot >= ecc->num_slots)
530 return;
531 memcpy_toio(ecc->base + PARM_OFFSET(slot), param, PARM_SIZE);
532}
533
534/**
535 * edma_read_slot - read parameter RAM data from slot
536 * @ecc: pointer to edma_cc struct
537 * @slot: number of parameter RAM slot being copied
538 * @param: where to store copy of parameter RAM data
539 *
540 * Use this to read data from a parameter RAM slot, perhaps to
541 * save them as a template for later reuse.
542 */
543static void edma_read_slot(struct edma_cc *ecc, unsigned slot,
544 struct edmacc_param *param)
545{
546 slot = EDMA_CHAN_SLOT(slot);
547 if (slot >= ecc->num_slots)
548 return;
549 memcpy_fromio(param, ecc->base + PARM_OFFSET(slot), PARM_SIZE);
550}
551
552/**
553 * edma_alloc_slot - allocate DMA parameter RAM
554 * @ecc: pointer to edma_cc struct
555 * @slot: specific slot to allocate; negative for "any unused slot"
556 *
557 * This allocates a parameter RAM slot, initializing it to hold a
558 * dummy transfer. Slots allocated using this routine have not been
559 * mapped to a hardware DMA channel, and will normally be used by
560 * linking to them from a slot associated with a DMA channel.
561 *
562 * Normal use is to pass EDMA_SLOT_ANY as the @slot, but specific
563 * slots may be allocated on behalf of DSP firmware.
564 *
565 * Returns the number of the slot, else negative errno.
566 */
567static int edma_alloc_slot(struct edma_cc *ecc, int slot)
568{
569 if (slot > 0)
570 slot = EDMA_CHAN_SLOT(slot);
571 if (slot < 0) {
572 slot = ecc->num_channels;
573 for (;;) {
574 slot = find_next_zero_bit(ecc->edma_inuse,
575 ecc->num_slots,
576 slot);
577 if (slot == ecc->num_slots)
578 return -ENOMEM;
579 if (!test_and_set_bit(slot, ecc->edma_inuse))
580 break;
581 }
582 } else if (slot < ecc->num_channels || slot >= ecc->num_slots) {
583 return -EINVAL;
584 } else if (test_and_set_bit(slot, ecc->edma_inuse)) {
585 return -EBUSY;
586 }
587
588 edma_write_slot(ecc, slot, &dummy_paramset);
589
590 return EDMA_CTLR_CHAN(ecc->id, slot);
591}
592
593/**
594 * edma_free_slot - deallocate DMA parameter RAM
595 * @ecc: pointer to edma_cc struct
596 * @slot: parameter RAM slot returned from edma_alloc_slot()
597 *
598 * This deallocates the parameter RAM slot allocated by edma_alloc_slot().
599 * Callers are responsible for ensuring the slot is inactive, and will
600 * not be activated.
601 */
602static void edma_free_slot(struct edma_cc *ecc, unsigned slot)
603{
604 slot = EDMA_CHAN_SLOT(slot);
605 if (slot < ecc->num_channels || slot >= ecc->num_slots)
606 return;
607
608 edma_write_slot(ecc, slot, &dummy_paramset);
609 clear_bit(slot, ecc->edma_inuse);
610}
611
612/**
613 * edma_link - link one parameter RAM slot to another
614 * @ecc: pointer to edma_cc struct
615 * @from: parameter RAM slot originating the link
616 * @to: parameter RAM slot which is the link target
617 *
618 * The originating slot should not be part of any active DMA transfer.
619 */
620static void edma_link(struct edma_cc *ecc, unsigned from, unsigned to)
621{
622 from = EDMA_CHAN_SLOT(from);
623 to = EDMA_CHAN_SLOT(to);
624 if (from >= ecc->num_slots || to >= ecc->num_slots)
625 return;
626
627 edma_parm_modify(ecc, PARM_LINK_BCNTRLD, from, 0xffff0000,
628 PARM_OFFSET(to));
629}
630
631/**
632 * edma_get_position - returns the current transfer point
633 * @ecc: pointer to edma_cc struct
634 * @slot: parameter RAM slot being examined
635 * @dst: true selects the dest position, false the source
636 *
637 * Returns the position of the current active slot
638 */
639static dma_addr_t edma_get_position(struct edma_cc *ecc, unsigned slot,
640 bool dst)
641{
642 u32 offs;
643
644 slot = EDMA_CHAN_SLOT(slot);
645 offs = PARM_OFFSET(slot);
646 offs += dst ? PARM_DST : PARM_SRC;
647
648 return edma_read(ecc, offs);
649}
650
651/*-----------------------------------------------------------------------*/
652/**
653 * edma_start - start dma on a channel
654 * @ecc: pointer to edma_cc struct
655 * @channel: channel being activated
656 *
657 * Channels with event associations will be triggered by their hardware
658 * events, and channels without such associations will be triggered by
659 * software. (At this writing there is no interface for using software
660 * triggers except with channels that don't support hardware triggers.)
661 *
662 * Returns zero on success, else negative errno.
663 */
664static int edma_start(struct edma_cc *ecc, unsigned channel)
665{
666 if (ecc->id != EDMA_CTLR(channel)) {
667 dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
668 ecc->id, EDMA_CTLR(channel));
669 return -EINVAL;
670 }
671 channel = EDMA_CHAN_SLOT(channel);
672
673 if (channel < ecc->num_channels) {
674 int j = channel >> 5;
675 unsigned int mask = BIT(channel & 0x1f);
676
677 /* EDMA channels without event association */
678 if (test_bit(channel, ecc->edma_unused)) {
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300679 dev_dbg(ecc->dev, "ESR%d %08x\n", j,
680 edma_shadow0_read_array(ecc, SH_ESR, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300681 edma_shadow0_write_array(ecc, SH_ESR, j, mask);
682 return 0;
683 }
684
685 /* EDMA channel with event association */
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300686 dev_dbg(ecc->dev, "ER%d %08x\n", j,
687 edma_shadow0_read_array(ecc, SH_ER, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300688 /* Clear any pending event or error */
689 edma_write_array(ecc, EDMA_ECR, j, mask);
690 edma_write_array(ecc, EDMA_EMCR, j, mask);
691 /* Clear any SER */
692 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
693 edma_shadow0_write_array(ecc, SH_EESR, j, mask);
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300694 dev_dbg(ecc->dev, "EER%d %08x\n", j,
695 edma_shadow0_read_array(ecc, SH_EER, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300696 return 0;
697 }
698
699 return -EINVAL;
700}
701
702/**
703 * edma_stop - stops dma on the channel passed
704 * @ecc: pointer to edma_cc struct
705 * @channel: channel being deactivated
706 *
707 * When @lch is a channel, any active transfer is paused and
708 * all pending hardware events are cleared. The current transfer
709 * may not be resumed, and the channel's Parameter RAM should be
710 * reinitialized before being reused.
711 */
712static void edma_stop(struct edma_cc *ecc, unsigned channel)
713{
714 if (ecc->id != EDMA_CTLR(channel)) {
715 dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
716 ecc->id, EDMA_CTLR(channel));
717 return;
718 }
719 channel = EDMA_CHAN_SLOT(channel);
720
721 if (channel < ecc->num_channels) {
722 int j = channel >> 5;
723 unsigned int mask = BIT(channel & 0x1f);
724
725 edma_shadow0_write_array(ecc, SH_EECR, j, mask);
726 edma_shadow0_write_array(ecc, SH_ECR, j, mask);
727 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
728 edma_write_array(ecc, EDMA_EMCR, j, mask);
729
730 /* clear possibly pending completion interrupt */
731 edma_shadow0_write_array(ecc, SH_ICR, j, mask);
732
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300733 dev_dbg(ecc->dev, "EER%d %08x\n", j,
734 edma_shadow0_read_array(ecc, SH_EER, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300735
736 /* REVISIT: consider guarding against inappropriate event
737 * chaining by overwriting with dummy_paramset.
738 */
739 }
740}
741
742/**
743 * edma_pause - pause dma on a channel
744 * @ecc: pointer to edma_cc struct
745 * @channel: on which edma_start() has been called
746 *
747 * This temporarily disables EDMA hardware events on the specified channel,
748 * preventing them from triggering new transfers on its behalf
749 */
750static void edma_pause(struct edma_cc *ecc, unsigned channel)
751{
752 if (ecc->id != EDMA_CTLR(channel)) {
753 dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
754 ecc->id, EDMA_CTLR(channel));
755 return;
756 }
757 channel = EDMA_CHAN_SLOT(channel);
758
759 if (channel < ecc->num_channels) {
760 unsigned int mask = BIT(channel & 0x1f);
761
762 edma_shadow0_write_array(ecc, SH_EECR, channel >> 5, mask);
763 }
764}
765
766/**
767 * edma_resume - resumes dma on a paused channel
768 * @ecc: pointer to edma_cc struct
769 * @channel: on which edma_pause() has been called
770 *
771 * This re-enables EDMA hardware events on the specified channel.
772 */
773static void edma_resume(struct edma_cc *ecc, unsigned channel)
774{
775 if (ecc->id != EDMA_CTLR(channel)) {
776 dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
777 ecc->id, EDMA_CTLR(channel));
778 return;
779 }
780 channel = EDMA_CHAN_SLOT(channel);
781
782 if (channel < ecc->num_channels) {
783 unsigned int mask = BIT(channel & 0x1f);
784
785 edma_shadow0_write_array(ecc, SH_EESR, channel >> 5, mask);
786 }
787}
788
789static int edma_trigger_channel(struct edma_cc *ecc, unsigned channel)
790{
791 unsigned int mask;
792
793 if (ecc->id != EDMA_CTLR(channel)) {
794 dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
795 ecc->id, EDMA_CTLR(channel));
796 return -EINVAL;
797 }
798 channel = EDMA_CHAN_SLOT(channel);
799 mask = BIT(channel & 0x1f);
800
801 edma_shadow0_write_array(ecc, SH_ESR, (channel >> 5), mask);
802
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300803 dev_dbg(ecc->dev, "ESR%d %08x\n", (channel >> 5),
804 edma_shadow0_read_array(ecc, SH_ESR, (channel >> 5)));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300805 return 0;
806}
807
808/******************************************************************************
809 *
810 * It cleans ParamEntry qand bring back EDMA to initial state if media has
811 * been removed before EDMA has finished.It is usedful for removable media.
812 * Arguments:
813 * ch_no - channel no
814 *
815 * Return: zero on success, or corresponding error no on failure
816 *
817 * FIXME this should not be needed ... edma_stop() should suffice.
818 *
819 *****************************************************************************/
820
821static void edma_clean_channel(struct edma_cc *ecc, unsigned channel)
822{
823 if (ecc->id != EDMA_CTLR(channel)) {
824 dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
825 ecc->id, EDMA_CTLR(channel));
826 return;
827 }
828 channel = EDMA_CHAN_SLOT(channel);
829
830 if (channel < ecc->num_channels) {
831 int j = (channel >> 5);
832 unsigned int mask = BIT(channel & 0x1f);
833
Peter Ujfalusi3287fb42015-10-14 14:42:57 +0300834 dev_dbg(ecc->dev, "EMR%d %08x\n", j,
835 edma_read_array(ecc, EDMA_EMR, j));
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300836 edma_shadow0_write_array(ecc, SH_ECR, j, mask);
837 /* Clear the corresponding EMR bits */
838 edma_write_array(ecc, EDMA_EMCR, j, mask);
839 /* Clear any SER */
840 edma_shadow0_write_array(ecc, SH_SECR, j, mask);
841 edma_write(ecc, EDMA_CCERRCLR, BIT(16) | BIT(1) | BIT(0));
842 }
843}
844
845/**
846 * edma_alloc_channel - allocate DMA channel and paired parameter RAM
847 * @ecc: pointer to edma_cc struct
848 * @channel: specific channel to allocate; negative for "any unmapped channel"
849 * @callback: optional; to be issued on DMA completion or errors
850 * @data: passed to callback
851 * @eventq_no: an EVENTQ_* constant, used to choose which Transfer
852 * Controller (TC) executes requests using this channel. Use
853 * EVENTQ_DEFAULT unless you really need a high priority queue.
854 *
855 * This allocates a DMA channel and its associated parameter RAM slot.
856 * The parameter RAM is initialized to hold a dummy transfer.
857 *
858 * Normal use is to pass a specific channel number as @channel, to make
859 * use of hardware events mapped to that channel. When the channel will
860 * be used only for software triggering or event chaining, channels not
861 * mapped to hardware events (or mapped to unused events) are preferable.
862 *
863 * DMA transfers start from a channel using edma_start(), or by
864 * chaining. When the transfer described in that channel's parameter RAM
865 * slot completes, that slot's data may be reloaded through a link.
866 *
867 * DMA errors are only reported to the @callback associated with the
868 * channel driving that transfer, but transfer completion callbacks can
869 * be sent to another channel under control of the TCC field in
870 * the option word of the transfer's parameter RAM set. Drivers must not
871 * use DMA transfer completion callbacks for channels they did not allocate.
872 * (The same applies to TCC codes used in transfer chaining.)
873 *
874 * Returns the number of the channel, else negative errno.
875 */
876static int edma_alloc_channel(struct edma_cc *ecc, int channel,
877 void (*callback)(unsigned channel, u16 ch_status, void *data),
878 void *data,
879 enum dma_event_q eventq_no)
880{
881 unsigned done = 0;
882 int ret = 0;
883
884 if (!ecc->unused_chan_list_done) {
885 /*
886 * Scan all the platform devices to find out the EDMA channels
887 * used and clear them in the unused list, making the rest
888 * available for ARM usage.
889 */
890 ret = bus_for_each_dev(&platform_bus_type, NULL, ecc,
891 prepare_unused_channel_list);
892 if (ret < 0)
893 return ret;
894
895 ecc->unused_chan_list_done = true;
896 }
897
898 if (channel >= 0) {
899 if (ecc->id != EDMA_CTLR(channel)) {
900 dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n",
901 __func__, ecc->id, EDMA_CTLR(channel));
902 return -EINVAL;
903 }
904 channel = EDMA_CHAN_SLOT(channel);
905 }
906
907 if (channel < 0) {
908 channel = 0;
909 for (;;) {
910 channel = find_next_bit(ecc->edma_unused,
911 ecc->num_channels, channel);
912 if (channel == ecc->num_channels)
913 break;
914 if (!test_and_set_bit(channel, ecc->edma_inuse)) {
915 done = 1;
916 break;
917 }
918 channel++;
919 }
920 if (!done)
921 return -ENOMEM;
922 } else if (channel >= ecc->num_channels) {
923 return -EINVAL;
924 } else if (test_and_set_bit(channel, ecc->edma_inuse)) {
925 return -EBUSY;
926 }
927
928 /* ensure access through shadow region 0 */
929 edma_or_array2(ecc, EDMA_DRAE, 0, channel >> 5, BIT(channel & 0x1f));
930
931 /* ensure no events are pending */
932 edma_stop(ecc, EDMA_CTLR_CHAN(ecc->id, channel));
933 edma_write_slot(ecc, channel, &dummy_paramset);
934
935 if (callback)
936 edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, channel),
937 callback, data);
938
939 edma_map_dmach_to_queue(ecc, channel, eventq_no);
940
941 return EDMA_CTLR_CHAN(ecc->id, channel);
942}
943
944/**
945 * edma_free_channel - deallocate DMA channel
946 * @ecc: pointer to edma_cc struct
947 * @channel: dma channel returned from edma_alloc_channel()
948 *
949 * This deallocates the DMA channel and associated parameter RAM slot
950 * allocated by edma_alloc_channel().
951 *
952 * Callers are responsible for ensuring the channel is inactive, and
953 * will not be reactivated by linking, chaining, or software calls to
954 * edma_start().
955 */
956static void edma_free_channel(struct edma_cc *ecc, unsigned channel)
957{
958 if (ecc->id != EDMA_CTLR(channel)) {
959 dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
960 ecc->id, EDMA_CTLR(channel));
961 return;
962 }
963 channel = EDMA_CHAN_SLOT(channel);
964
965 if (channel >= ecc->num_channels)
966 return;
967
968 edma_setup_interrupt(ecc, channel, NULL, NULL);
969 /* REVISIT should probably take out of shadow region 0 */
970
Peter Ujfalusi96f5ff02015-10-14 14:42:58 +0300971 edma_write_slot(ecc, channel, &dummy_paramset);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +0300972 clear_bit(channel, ecc->edma_inuse);
973}
974
975/*
976 * edma_assign_channel_eventq - move given channel to desired eventq
977 * Arguments:
978 * channel - channel number
979 * eventq_no - queue to move the channel
980 *
981 * Can be used to move a channel to a selected event queue.
982 */
983static void edma_assign_channel_eventq(struct edma_cc *ecc, unsigned channel,
984 enum dma_event_q eventq_no)
985{
986 if (ecc->id != EDMA_CTLR(channel)) {
987 dev_err(ecc->dev, "%s: ID mismatch for eDMA%d: %d\n", __func__,
988 ecc->id, EDMA_CTLR(channel));
989 return;
990 }
991 channel = EDMA_CHAN_SLOT(channel);
992
993 if (channel >= ecc->num_channels)
994 return;
995
996 /* default to low priority queue */
997 if (eventq_no == EVENTQ_DEFAULT)
998 eventq_no = ecc->default_queue;
999 if (eventq_no >= ecc->num_tc)
1000 return;
1001
1002 edma_map_dmach_to_queue(ecc, channel, eventq_no);
1003}
1004
1005static irqreturn_t dma_irq_handler(int irq, void *data)
1006{
1007 struct edma_cc *ecc = data;
1008 int ctlr;
1009 u32 sh_ier;
1010 u32 sh_ipr;
1011 u32 bank;
1012
1013 ctlr = ecc->id;
1014 if (ctlr < 0)
1015 return IRQ_NONE;
1016
1017 dev_dbg(ecc->dev, "dma_irq_handler\n");
1018
1019 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 0);
1020 if (!sh_ipr) {
1021 sh_ipr = edma_shadow0_read_array(ecc, SH_IPR, 1);
1022 if (!sh_ipr)
1023 return IRQ_NONE;
1024 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 1);
1025 bank = 1;
1026 } else {
1027 sh_ier = edma_shadow0_read_array(ecc, SH_IER, 0);
1028 bank = 0;
1029 }
1030
1031 do {
1032 u32 slot;
1033 u32 channel;
1034
1035 dev_dbg(ecc->dev, "IPR%d %08x\n", bank, sh_ipr);
1036
1037 slot = __ffs(sh_ipr);
1038 sh_ipr &= ~(BIT(slot));
1039
1040 if (sh_ier & BIT(slot)) {
1041 channel = (bank << 5) | slot;
1042 /* Clear the corresponding IPR bits */
1043 edma_shadow0_write_array(ecc, SH_ICR, bank, BIT(slot));
1044 if (ecc->intr_data[channel].callback)
1045 ecc->intr_data[channel].callback(
1046 EDMA_CTLR_CHAN(ctlr, channel),
1047 EDMA_DMA_COMPLETE,
1048 ecc->intr_data[channel].data);
1049 }
1050 } while (sh_ipr);
1051
1052 edma_shadow0_write(ecc, SH_IEVAL, 1);
1053 return IRQ_HANDLED;
1054}
1055
1056/******************************************************************************
1057 *
1058 * DMA error interrupt handler
1059 *
1060 *****************************************************************************/
1061static irqreturn_t dma_ccerr_handler(int irq, void *data)
1062{
1063 struct edma_cc *ecc = data;
1064 int i;
1065 int ctlr;
1066 unsigned int cnt = 0;
1067
1068 ctlr = ecc->id;
1069 if (ctlr < 0)
1070 return IRQ_NONE;
1071
1072 dev_dbg(ecc->dev, "dma_ccerr_handler\n");
1073
1074 if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
1075 (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
1076 (edma_read(ecc, EDMA_QEMR) == 0) &&
1077 (edma_read(ecc, EDMA_CCERR) == 0))
1078 return IRQ_NONE;
1079
1080 while (1) {
1081 int j = -1;
1082
1083 if (edma_read_array(ecc, EDMA_EMR, 0))
1084 j = 0;
1085 else if (edma_read_array(ecc, EDMA_EMR, 1))
1086 j = 1;
1087 if (j >= 0) {
1088 dev_dbg(ecc->dev, "EMR%d %08x\n", j,
1089 edma_read_array(ecc, EDMA_EMR, j));
1090 for (i = 0; i < 32; i++) {
1091 int k = (j << 5) + i;
1092
1093 if (edma_read_array(ecc, EDMA_EMR, j) &
1094 BIT(i)) {
1095 /* Clear the corresponding EMR bits */
1096 edma_write_array(ecc, EDMA_EMCR, j,
1097 BIT(i));
1098 /* Clear any SER */
1099 edma_shadow0_write_array(ecc, SH_SECR,
1100 j, BIT(i));
1101 if (ecc->intr_data[k].callback) {
1102 ecc->intr_data[k].callback(
1103 EDMA_CTLR_CHAN(ctlr, k),
1104 EDMA_DMA_CC_ERROR,
1105 ecc->intr_data[k].data);
1106 }
1107 }
1108 }
1109 } else if (edma_read(ecc, EDMA_QEMR)) {
1110 dev_dbg(ecc->dev, "QEMR %02x\n",
1111 edma_read(ecc, EDMA_QEMR));
1112 for (i = 0; i < 8; i++) {
1113 if (edma_read(ecc, EDMA_QEMR) & BIT(i)) {
1114 /* Clear the corresponding IPR bits */
1115 edma_write(ecc, EDMA_QEMCR, BIT(i));
1116 edma_shadow0_write(ecc, SH_QSECR,
1117 BIT(i));
1118
1119 /* NOTE: not reported!! */
1120 }
1121 }
1122 } else if (edma_read(ecc, EDMA_CCERR)) {
1123 dev_dbg(ecc->dev, "CCERR %08x\n",
1124 edma_read(ecc, EDMA_CCERR));
1125 /* FIXME: CCERR.BIT(16) ignored! much better
1126 * to just write CCERRCLR with CCERR value...
1127 */
1128 for (i = 0; i < 8; i++) {
1129 if (edma_read(ecc, EDMA_CCERR) & BIT(i)) {
1130 /* Clear the corresponding IPR bits */
1131 edma_write(ecc, EDMA_CCERRCLR, BIT(i));
1132
1133 /* NOTE: not reported!! */
1134 }
1135 }
1136 }
1137 if ((edma_read_array(ecc, EDMA_EMR, 0) == 0) &&
1138 (edma_read_array(ecc, EDMA_EMR, 1) == 0) &&
1139 (edma_read(ecc, EDMA_QEMR) == 0) &&
1140 (edma_read(ecc, EDMA_CCERR) == 0))
1141 break;
1142 cnt++;
1143 if (cnt > 10)
1144 break;
1145 }
1146 edma_write(ecc, EDMA_EEVAL, 1);
1147 return IRQ_HANDLED;
1148}
1149
Matt Porterc2dde5f2012-08-22 21:09:34 -04001150static inline struct edma_cc *to_edma_cc(struct dma_device *d)
1151{
1152 return container_of(d, struct edma_cc, dma_slave);
1153}
1154
1155static inline struct edma_chan *to_edma_chan(struct dma_chan *c)
1156{
1157 return container_of(c, struct edma_chan, vchan.chan);
1158}
1159
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001160static inline struct edma_desc *to_edma_desc(struct dma_async_tx_descriptor *tx)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001161{
1162 return container_of(tx, struct edma_desc, vdesc.tx);
1163}
1164
1165static void edma_desc_free(struct virt_dma_desc *vdesc)
1166{
1167 kfree(container_of(vdesc, struct edma_desc, vdesc));
1168}
1169
1170/* Dispatch a queued descriptor to the controller (caller holds lock) */
1171static void edma_execute(struct edma_chan *echan)
1172{
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001173 struct edma_cc *ecc = echan->ecc;
Joel Fernandes53407062013-09-03 10:02:46 -05001174 struct virt_dma_desc *vdesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001175 struct edma_desc *edesc;
Joel Fernandes53407062013-09-03 10:02:46 -05001176 struct device *dev = echan->vchan.chan.device->dev;
1177 int i, j, left, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001178
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001179 if (!echan->edesc) {
1180 /* Setup is needed for the first transfer */
Joel Fernandes53407062013-09-03 10:02:46 -05001181 vdesc = vchan_next_desc(&echan->vchan);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001182 if (!vdesc)
Joel Fernandes53407062013-09-03 10:02:46 -05001183 return;
Joel Fernandes53407062013-09-03 10:02:46 -05001184 list_del(&vdesc->node);
1185 echan->edesc = to_edma_desc(&vdesc->tx);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001186 }
1187
Joel Fernandes53407062013-09-03 10:02:46 -05001188 edesc = echan->edesc;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001189
Joel Fernandes53407062013-09-03 10:02:46 -05001190 /* Find out how many left */
1191 left = edesc->pset_nr - edesc->processed;
1192 nslots = min(MAX_NR_SG, left);
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001193 edesc->sg_len = 0;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001194
1195 /* Write descriptor PaRAM set(s) */
Joel Fernandes53407062013-09-03 10:02:46 -05001196 for (i = 0; i < nslots; i++) {
1197 j = i + edesc->processed;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001198 edma_write_slot(ecc, echan->slot[i], &edesc->pset[j].param);
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001199 edesc->sg_len += edesc->pset[j].len;
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03001200 dev_vdbg(dev,
1201 "\n pset[%d]:\n"
1202 " chnum\t%d\n"
1203 " slot\t%d\n"
1204 " opt\t%08x\n"
1205 " src\t%08x\n"
1206 " dst\t%08x\n"
1207 " abcnt\t%08x\n"
1208 " ccnt\t%08x\n"
1209 " bidx\t%08x\n"
1210 " cidx\t%08x\n"
1211 " lkrld\t%08x\n",
1212 j, echan->ch_num, echan->slot[i],
1213 edesc->pset[j].param.opt,
1214 edesc->pset[j].param.src,
1215 edesc->pset[j].param.dst,
1216 edesc->pset[j].param.a_b_cnt,
1217 edesc->pset[j].param.ccnt,
1218 edesc->pset[j].param.src_dst_bidx,
1219 edesc->pset[j].param.src_dst_cidx,
1220 edesc->pset[j].param.link_bcntrld);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001221 /* Link to the previous slot if not the last set */
Joel Fernandes53407062013-09-03 10:02:46 -05001222 if (i != (nslots - 1))
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001223 edma_link(ecc, echan->slot[i], echan->slot[i + 1]);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001224 }
1225
Joel Fernandes53407062013-09-03 10:02:46 -05001226 edesc->processed += nslots;
1227
Joel Fernandesb267b3b2013-08-29 18:05:44 -05001228 /*
1229 * If this is either the last set in a set of SG-list transactions
1230 * then setup a link to the dummy slot, this results in all future
1231 * events being absorbed and that's OK because we're done
1232 */
Joel Fernandes50a9c702013-10-31 16:31:23 -05001233 if (edesc->processed == edesc->pset_nr) {
1234 if (edesc->cyclic)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001235 edma_link(ecc, echan->slot[nslots - 1], echan->slot[1]);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001236 else
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001237 edma_link(ecc, echan->slot[nslots - 1],
Joel Fernandes50a9c702013-10-31 16:31:23 -05001238 echan->ecc->dummy_slot);
1239 }
Joel Fernandesb267b3b2013-08-29 18:05:44 -05001240
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001241 if (echan->missed) {
1242 /*
1243 * This happens due to setup times between intermediate
1244 * transfers in long SG lists which have to be broken up into
1245 * transfers of MAX_NR_SG
1246 */
1247 dev_dbg(dev, "missed event on channel %d\n", echan->ch_num);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001248 edma_clean_channel(ecc, echan->ch_num);
1249 edma_stop(ecc, echan->ch_num);
1250 edma_start(ecc, echan->ch_num);
1251 edma_trigger_channel(ecc, echan->ch_num);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001252 echan->missed = 0;
1253 } else if (edesc->processed <= MAX_NR_SG) {
Peter Ujfalusi9aac9092014-04-24 10:29:50 +03001254 dev_dbg(dev, "first transfer starting on channel %d\n",
1255 echan->ch_num);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001256 edma_start(ecc, echan->ch_num);
Sekhar Nori5fc68a62014-03-19 11:25:50 +05301257 } else {
1258 dev_dbg(dev, "chan: %d: completed %d elements, resuming\n",
1259 echan->ch_num, edesc->processed);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001260 edma_resume(ecc, echan->ch_num);
Joel Fernandes53407062013-09-03 10:02:46 -05001261 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04001262}
1263
Maxime Ripardaa7c09b2014-11-17 14:42:13 +01001264static int edma_terminate_all(struct dma_chan *chan)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001265{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +01001266 struct edma_chan *echan = to_edma_chan(chan);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001267 unsigned long flags;
1268 LIST_HEAD(head);
1269
1270 spin_lock_irqsave(&echan->vchan.lock, flags);
1271
1272 /*
1273 * Stop DMA activity: we assume the callback will not be called
1274 * after edma_dma() returns (even if it does, it will see
1275 * echan->edesc is NULL and exit.)
1276 */
1277 if (echan->edesc) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001278 edma_stop(echan->ecc, echan->ch_num);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001279 /* Move the cyclic channel back to default queue */
1280 if (echan->edesc->cyclic)
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001281 edma_assign_channel_eventq(echan->ecc, echan->ch_num,
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001282 EVENTQ_DEFAULT);
Petr Kulhavy5ca9e7c2015-03-27 13:35:51 +02001283 /*
1284 * free the running request descriptor
1285 * since it is not in any of the vdesc lists
1286 */
1287 edma_desc_free(&echan->edesc->vdesc);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001288 echan->edesc = NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001289 }
1290
1291 vchan_get_all_descriptors(&echan->vchan, &head);
1292 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1293 vchan_dma_desc_free_list(&echan->vchan, &head);
1294
1295 return 0;
1296}
1297
Maxime Ripardaa7c09b2014-11-17 14:42:13 +01001298static int edma_slave_config(struct dma_chan *chan,
Matt Porter661f7cb2013-01-10 13:41:04 -05001299 struct dma_slave_config *cfg)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001300{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +01001301 struct edma_chan *echan = to_edma_chan(chan);
1302
Matt Porter661f7cb2013-01-10 13:41:04 -05001303 if (cfg->src_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES ||
1304 cfg->dst_addr_width == DMA_SLAVE_BUSWIDTH_8_BYTES)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001305 return -EINVAL;
1306
Matt Porter661f7cb2013-01-10 13:41:04 -05001307 memcpy(&echan->cfg, cfg, sizeof(echan->cfg));
Matt Porterc2dde5f2012-08-22 21:09:34 -04001308
1309 return 0;
1310}
1311
Maxime Ripardaa7c09b2014-11-17 14:42:13 +01001312static int edma_dma_pause(struct dma_chan *chan)
Peter Ujfalusi72c7b672014-04-14 14:41:59 +03001313{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +01001314 struct edma_chan *echan = to_edma_chan(chan);
1315
John Ogness02ec6042015-04-27 13:52:25 +02001316 if (!echan->edesc)
Peter Ujfalusi72c7b672014-04-14 14:41:59 +03001317 return -EINVAL;
1318
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001319 edma_pause(echan->ecc, echan->ch_num);
Peter Ujfalusi72c7b672014-04-14 14:41:59 +03001320 return 0;
1321}
1322
Maxime Ripardaa7c09b2014-11-17 14:42:13 +01001323static int edma_dma_resume(struct dma_chan *chan)
Peter Ujfalusi72c7b672014-04-14 14:41:59 +03001324{
Maxime Ripardaa7c09b2014-11-17 14:42:13 +01001325 struct edma_chan *echan = to_edma_chan(chan);
1326
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001327 edma_resume(echan->ecc, echan->ch_num);
Peter Ujfalusi72c7b672014-04-14 14:41:59 +03001328 return 0;
1329}
1330
Joel Fernandesfd009032013-09-23 18:05:13 -05001331/*
1332 * A PaRAM set configuration abstraction used by other modes
1333 * @chan: Channel who's PaRAM set we're configuring
1334 * @pset: PaRAM set to initialize and setup.
1335 * @src_addr: Source address of the DMA
1336 * @dst_addr: Destination address of the DMA
1337 * @burst: In units of dev_width, how much to send
1338 * @dev_width: How much is the dev_width
1339 * @dma_length: Total length of the DMA transfer
1340 * @direction: Direction of the transfer
1341 */
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001342static int edma_config_pset(struct dma_chan *chan, struct edma_pset *epset,
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001343 dma_addr_t src_addr, dma_addr_t dst_addr, u32 burst,
1344 enum dma_slave_buswidth dev_width,
1345 unsigned int dma_length,
1346 enum dma_transfer_direction direction)
Joel Fernandesfd009032013-09-23 18:05:13 -05001347{
1348 struct edma_chan *echan = to_edma_chan(chan);
1349 struct device *dev = chan->device->dev;
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001350 struct edmacc_param *param = &epset->param;
Joel Fernandesfd009032013-09-23 18:05:13 -05001351 int acnt, bcnt, ccnt, cidx;
1352 int src_bidx, dst_bidx, src_cidx, dst_cidx;
1353 int absync;
1354
1355 acnt = dev_width;
Peter Ujfalusib2b617d2014-04-14 14:41:58 +03001356
1357 /* src/dst_maxburst == 0 is the same case as src/dst_maxburst == 1 */
1358 if (!burst)
1359 burst = 1;
Joel Fernandesfd009032013-09-23 18:05:13 -05001360 /*
1361 * If the maxburst is equal to the fifo width, use
1362 * A-synced transfers. This allows for large contiguous
1363 * buffer transfers using only one PaRAM set.
1364 */
1365 if (burst == 1) {
1366 /*
1367 * For the A-sync case, bcnt and ccnt are the remainder
1368 * and quotient respectively of the division of:
1369 * (dma_length / acnt) by (SZ_64K -1). This is so
1370 * that in case bcnt over flows, we have ccnt to use.
1371 * Note: In A-sync tranfer only, bcntrld is used, but it
1372 * only applies for sg_dma_len(sg) >= SZ_64K.
1373 * In this case, the best way adopted is- bccnt for the
1374 * first frame will be the remainder below. Then for
1375 * every successive frame, bcnt will be SZ_64K-1. This
1376 * is assured as bcntrld = 0xffff in end of function.
1377 */
1378 absync = false;
1379 ccnt = dma_length / acnt / (SZ_64K - 1);
1380 bcnt = dma_length / acnt - ccnt * (SZ_64K - 1);
1381 /*
1382 * If bcnt is non-zero, we have a remainder and hence an
1383 * extra frame to transfer, so increment ccnt.
1384 */
1385 if (bcnt)
1386 ccnt++;
1387 else
1388 bcnt = SZ_64K - 1;
1389 cidx = acnt;
1390 } else {
1391 /*
1392 * If maxburst is greater than the fifo address_width,
1393 * use AB-synced transfers where A count is the fifo
1394 * address_width and B count is the maxburst. In this
1395 * case, we are limited to transfers of C count frames
1396 * of (address_width * maxburst) where C count is limited
1397 * to SZ_64K-1. This places an upper bound on the length
1398 * of an SG segment that can be handled.
1399 */
1400 absync = true;
1401 bcnt = burst;
1402 ccnt = dma_length / (acnt * bcnt);
1403 if (ccnt > (SZ_64K - 1)) {
1404 dev_err(dev, "Exceeded max SG segment size\n");
1405 return -EINVAL;
1406 }
1407 cidx = acnt * bcnt;
1408 }
1409
Thomas Gleixnerc2da2342014-04-28 14:29:57 -05001410 epset->len = dma_length;
1411
Joel Fernandesfd009032013-09-23 18:05:13 -05001412 if (direction == DMA_MEM_TO_DEV) {
1413 src_bidx = acnt;
1414 src_cidx = cidx;
1415 dst_bidx = 0;
1416 dst_cidx = 0;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -05001417 epset->addr = src_addr;
Joel Fernandesfd009032013-09-23 18:05:13 -05001418 } else if (direction == DMA_DEV_TO_MEM) {
1419 src_bidx = 0;
1420 src_cidx = 0;
1421 dst_bidx = acnt;
1422 dst_cidx = cidx;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -05001423 epset->addr = dst_addr;
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001424 } else if (direction == DMA_MEM_TO_MEM) {
1425 src_bidx = acnt;
1426 src_cidx = cidx;
1427 dst_bidx = acnt;
1428 dst_cidx = cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -05001429 } else {
1430 dev_err(dev, "%s: direction not implemented yet\n", __func__);
1431 return -EINVAL;
1432 }
1433
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001434 param->opt = EDMA_TCC(EDMA_CHAN_SLOT(echan->ch_num));
Joel Fernandesfd009032013-09-23 18:05:13 -05001435 /* Configure A or AB synchronized transfers */
1436 if (absync)
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001437 param->opt |= SYNCDIM;
Joel Fernandesfd009032013-09-23 18:05:13 -05001438
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001439 param->src = src_addr;
1440 param->dst = dst_addr;
Joel Fernandesfd009032013-09-23 18:05:13 -05001441
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001442 param->src_dst_bidx = (dst_bidx << 16) | src_bidx;
1443 param->src_dst_cidx = (dst_cidx << 16) | src_cidx;
Joel Fernandesfd009032013-09-23 18:05:13 -05001444
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001445 param->a_b_cnt = bcnt << 16 | acnt;
1446 param->ccnt = ccnt;
Joel Fernandesfd009032013-09-23 18:05:13 -05001447 /*
1448 * Only time when (bcntrld) auto reload is required is for
1449 * A-sync case, and in this case, a requirement of reload value
1450 * of SZ_64K-1 only is assured. 'link' is initially set to NULL
1451 * and then later will be populated by edma_execute.
1452 */
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001453 param->link_bcntrld = 0xffffffff;
Joel Fernandesfd009032013-09-23 18:05:13 -05001454 return absync;
1455}
1456
Matt Porterc2dde5f2012-08-22 21:09:34 -04001457static struct dma_async_tx_descriptor *edma_prep_slave_sg(
1458 struct dma_chan *chan, struct scatterlist *sgl,
1459 unsigned int sg_len, enum dma_transfer_direction direction,
1460 unsigned long tx_flags, void *context)
1461{
1462 struct edma_chan *echan = to_edma_chan(chan);
1463 struct device *dev = chan->device->dev;
1464 struct edma_desc *edesc;
Joel Fernandesfd009032013-09-23 18:05:13 -05001465 dma_addr_t src_addr = 0, dst_addr = 0;
Matt Porter661f7cb2013-01-10 13:41:04 -05001466 enum dma_slave_buswidth dev_width;
1467 u32 burst;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001468 struct scatterlist *sg;
Joel Fernandesfd009032013-09-23 18:05:13 -05001469 int i, nslots, ret;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001470
1471 if (unlikely(!echan || !sgl || !sg_len))
1472 return NULL;
1473
Matt Porter661f7cb2013-01-10 13:41:04 -05001474 if (direction == DMA_DEV_TO_MEM) {
Joel Fernandesfd009032013-09-23 18:05:13 -05001475 src_addr = echan->cfg.src_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -05001476 dev_width = echan->cfg.src_addr_width;
1477 burst = echan->cfg.src_maxburst;
1478 } else if (direction == DMA_MEM_TO_DEV) {
Joel Fernandesfd009032013-09-23 18:05:13 -05001479 dst_addr = echan->cfg.dst_addr;
Matt Porter661f7cb2013-01-10 13:41:04 -05001480 dev_width = echan->cfg.dst_addr_width;
1481 burst = echan->cfg.dst_maxburst;
1482 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +03001483 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Matt Porter661f7cb2013-01-10 13:41:04 -05001484 return NULL;
1485 }
1486
1487 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001488 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001489 return NULL;
1490 }
1491
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001492 edesc = kzalloc(sizeof(*edesc) + sg_len * sizeof(edesc->pset[0]),
1493 GFP_ATOMIC);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001494 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001495 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001496 return NULL;
1497 }
1498
1499 edesc->pset_nr = sg_len;
Thomas Gleixnerb6205c32014-04-28 14:18:45 -05001500 edesc->residue = 0;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -05001501 edesc->direction = direction;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001502 edesc->echan = echan;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001503
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001504 /* Allocate a PaRAM slot, if needed */
1505 nslots = min_t(unsigned, MAX_NR_SG, sg_len);
1506
1507 for (i = 0; i < nslots; i++) {
Matt Porterc2dde5f2012-08-22 21:09:34 -04001508 if (echan->slot[i] < 0) {
1509 echan->slot[i] =
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001510 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001511 if (echan->slot[i] < 0) {
Valentin Ilie4b6271a2013-10-24 16:14:22 +03001512 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +03001513 dev_err(dev, "%s: Failed to allocate slot\n",
1514 __func__);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001515 return NULL;
1516 }
1517 }
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001518 }
1519
1520 /* Configure PaRAM sets for each SG */
1521 for_each_sg(sgl, sg, sg_len, i) {
Joel Fernandesfd009032013-09-23 18:05:13 -05001522 /* Get address for each SG */
1523 if (direction == DMA_DEV_TO_MEM)
1524 dst_addr = sg_dma_address(sg);
1525 else
1526 src_addr = sg_dma_address(sg);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001527
Joel Fernandesfd009032013-09-23 18:05:13 -05001528 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1529 dst_addr, burst, dev_width,
1530 sg_dma_len(sg), direction);
Vinod Koulb967aec2013-10-30 13:07:18 +05301531 if (ret < 0) {
1532 kfree(edesc);
Joel Fernandesfd009032013-09-23 18:05:13 -05001533 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001534 }
1535
Joel Fernandesfd009032013-09-23 18:05:13 -05001536 edesc->absync = ret;
Thomas Gleixnerb6205c32014-04-28 14:18:45 -05001537 edesc->residue += sg_dma_len(sg);
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001538
1539 /* If this is the last in a current SG set of transactions,
1540 enable interrupts so that next set is processed */
1541 if (!((i+1) % MAX_NR_SG))
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001542 edesc->pset[i].param.opt |= TCINTEN;
Joel Fernandes6fbe24d2013-08-29 18:05:40 -05001543
Matt Porterc2dde5f2012-08-22 21:09:34 -04001544 /* If this is the last set, enable completion interrupt flag */
1545 if (i == sg_len - 1)
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001546 edesc->pset[i].param.opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001547 }
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001548 edesc->residue_stat = edesc->residue;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001549
Matt Porterc2dde5f2012-08-22 21:09:34 -04001550 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1551}
Matt Porterc2dde5f2012-08-22 21:09:34 -04001552
Lad, Prabhakarb7a4fd52015-02-04 13:03:27 +00001553static struct dma_async_tx_descriptor *edma_prep_dma_memcpy(
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001554 struct dma_chan *chan, dma_addr_t dest, dma_addr_t src,
1555 size_t len, unsigned long tx_flags)
1556{
1557 int ret;
1558 struct edma_desc *edesc;
1559 struct device *dev = chan->device->dev;
1560 struct edma_chan *echan = to_edma_chan(chan);
1561
1562 if (unlikely(!echan || !len))
1563 return NULL;
1564
1565 edesc = kzalloc(sizeof(*edesc) + sizeof(edesc->pset[0]), GFP_ATOMIC);
1566 if (!edesc) {
1567 dev_dbg(dev, "Failed to allocate a descriptor\n");
1568 return NULL;
1569 }
1570
1571 edesc->pset_nr = 1;
1572
1573 ret = edma_config_pset(chan, &edesc->pset[0], src, dest, 1,
1574 DMA_SLAVE_BUSWIDTH_4_BYTES, len, DMA_MEM_TO_MEM);
1575 if (ret < 0)
1576 return NULL;
1577
1578 edesc->absync = ret;
1579
1580 /*
1581 * Enable intermediate transfer chaining to re-trigger channel
1582 * on completion of every TR, and enable transfer-completion
1583 * interrupt on completion of the whole transfer.
1584 */
Joel Fernandesb0cce4c2014-04-28 15:30:32 -05001585 edesc->pset[0].param.opt |= ITCCHEN;
1586 edesc->pset[0].param.opt |= TCINTEN;
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001587
1588 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1589}
1590
Joel Fernandes50a9c702013-10-31 16:31:23 -05001591static struct dma_async_tx_descriptor *edma_prep_dma_cyclic(
1592 struct dma_chan *chan, dma_addr_t buf_addr, size_t buf_len,
1593 size_t period_len, enum dma_transfer_direction direction,
Laurent Pinchart31c1e5a2014-08-01 12:20:10 +02001594 unsigned long tx_flags)
Joel Fernandes50a9c702013-10-31 16:31:23 -05001595{
1596 struct edma_chan *echan = to_edma_chan(chan);
1597 struct device *dev = chan->device->dev;
1598 struct edma_desc *edesc;
1599 dma_addr_t src_addr, dst_addr;
1600 enum dma_slave_buswidth dev_width;
1601 u32 burst;
1602 int i, ret, nslots;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001603
Joel Fernandes50a9c702013-10-31 16:31:23 -05001604 if (unlikely(!echan || !buf_len || !period_len))
1605 return NULL;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001606
Joel Fernandes50a9c702013-10-31 16:31:23 -05001607 if (direction == DMA_DEV_TO_MEM) {
1608 src_addr = echan->cfg.src_addr;
1609 dst_addr = buf_addr;
1610 dev_width = echan->cfg.src_addr_width;
1611 burst = echan->cfg.src_maxburst;
1612 } else if (direction == DMA_MEM_TO_DEV) {
1613 src_addr = buf_addr;
1614 dst_addr = echan->cfg.dst_addr;
1615 dev_width = echan->cfg.dst_addr_width;
1616 burst = echan->cfg.dst_maxburst;
1617 } else {
Peter Ujfalusie6fad592014-04-14 14:42:05 +03001618 dev_err(dev, "%s: bad direction: %d\n", __func__, direction);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001619 return NULL;
1620 }
1621
1622 if (dev_width == DMA_SLAVE_BUSWIDTH_UNDEFINED) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001623 dev_err(dev, "%s: Undefined slave buswidth\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001624 return NULL;
1625 }
1626
1627 if (unlikely(buf_len % period_len)) {
1628 dev_err(dev, "Period should be multiple of Buffer length\n");
1629 return NULL;
1630 }
1631
1632 nslots = (buf_len / period_len) + 1;
1633
1634 /*
1635 * Cyclic DMA users such as audio cannot tolerate delays introduced
1636 * by cases where the number of periods is more than the maximum
1637 * number of SGs the EDMA driver can handle at a time. For DMA types
1638 * such as Slave SGs, such delays are tolerable and synchronized,
1639 * but the synchronization is difficult to achieve with Cyclic and
1640 * cannot be guaranteed, so we error out early.
1641 */
1642 if (nslots > MAX_NR_SG)
1643 return NULL;
1644
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001645 edesc = kzalloc(sizeof(*edesc) + nslots * sizeof(edesc->pset[0]),
1646 GFP_ATOMIC);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001647 if (!edesc) {
Peter Ujfalusic594c892014-04-14 14:42:03 +03001648 dev_err(dev, "%s: Failed to allocate a descriptor\n", __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001649 return NULL;
1650 }
1651
1652 edesc->cyclic = 1;
1653 edesc->pset_nr = nslots;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001654 edesc->residue = edesc->residue_stat = buf_len;
Thomas Gleixnerc2da2342014-04-28 14:29:57 -05001655 edesc->direction = direction;
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001656 edesc->echan = echan;
Joel Fernandes50a9c702013-10-31 16:31:23 -05001657
Peter Ujfalusi83bb3122014-04-14 14:42:02 +03001658 dev_dbg(dev, "%s: channel=%d nslots=%d period_len=%zu buf_len=%zu\n",
1659 __func__, echan->ch_num, nslots, period_len, buf_len);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001660
1661 for (i = 0; i < nslots; i++) {
1662 /* Allocate a PaRAM slot, if needed */
1663 if (echan->slot[i] < 0) {
1664 echan->slot[i] =
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001665 edma_alloc_slot(echan->ecc, EDMA_SLOT_ANY);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001666 if (echan->slot[i] < 0) {
Christian Engelmayere3ddc972013-12-30 20:48:39 +01001667 kfree(edesc);
Peter Ujfalusic594c892014-04-14 14:42:03 +03001668 dev_err(dev, "%s: Failed to allocate slot\n",
1669 __func__);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001670 return NULL;
1671 }
1672 }
1673
1674 if (i == nslots - 1) {
1675 memcpy(&edesc->pset[i], &edesc->pset[0],
1676 sizeof(edesc->pset[0]));
1677 break;
1678 }
1679
1680 ret = edma_config_pset(chan, &edesc->pset[i], src_addr,
1681 dst_addr, burst, dev_width, period_len,
1682 direction);
Christian Engelmayere3ddc972013-12-30 20:48:39 +01001683 if (ret < 0) {
1684 kfree(edesc);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001685 return NULL;
Christian Engelmayere3ddc972013-12-30 20:48:39 +01001686 }
Joel Fernandes50a9c702013-10-31 16:31:23 -05001687
1688 if (direction == DMA_DEV_TO_MEM)
1689 dst_addr += period_len;
1690 else
1691 src_addr += period_len;
1692
Peter Ujfalusi83bb3122014-04-14 14:42:02 +03001693 dev_vdbg(dev, "%s: Configure period %d of buf:\n", __func__, i);
1694 dev_vdbg(dev,
Joel Fernandes50a9c702013-10-31 16:31:23 -05001695 "\n pset[%d]:\n"
1696 " chnum\t%d\n"
1697 " slot\t%d\n"
1698 " opt\t%08x\n"
1699 " src\t%08x\n"
1700 " dst\t%08x\n"
1701 " abcnt\t%08x\n"
1702 " ccnt\t%08x\n"
1703 " bidx\t%08x\n"
1704 " cidx\t%08x\n"
1705 " lkrld\t%08x\n",
1706 i, echan->ch_num, echan->slot[i],
Thomas Gleixnerb5088ad2014-04-28 14:23:55 -05001707 edesc->pset[i].param.opt,
1708 edesc->pset[i].param.src,
1709 edesc->pset[i].param.dst,
1710 edesc->pset[i].param.a_b_cnt,
1711 edesc->pset[i].param.ccnt,
1712 edesc->pset[i].param.src_dst_bidx,
1713 edesc->pset[i].param.src_dst_cidx,
1714 edesc->pset[i].param.link_bcntrld);
Joel Fernandes50a9c702013-10-31 16:31:23 -05001715
1716 edesc->absync = ret;
1717
1718 /*
Peter Ujfalusia1f146f2014-07-16 15:29:21 +03001719 * Enable period interrupt only if it is requested
Joel Fernandes50a9c702013-10-31 16:31:23 -05001720 */
Peter Ujfalusia1f146f2014-07-16 15:29:21 +03001721 if (tx_flags & DMA_PREP_INTERRUPT)
1722 edesc->pset[i].param.opt |= TCINTEN;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001723 }
1724
Peter Ujfalusi8e8805d2014-07-08 13:46:38 +03001725 /* Place the cyclic channel to highest priority queue */
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001726 edma_assign_channel_eventq(echan->ecc, echan->ch_num, EVENTQ_0);
Peter Ujfalusi8e8805d2014-07-08 13:46:38 +03001727
Matt Porterc2dde5f2012-08-22 21:09:34 -04001728 return vchan_tx_prep(&echan->vchan, &edesc->vdesc, tx_flags);
1729}
1730
1731static void edma_callback(unsigned ch_num, u16 ch_status, void *data)
1732{
1733 struct edma_chan *echan = data;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001734 struct edma_cc *ecc = echan->ecc;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001735 struct device *dev = echan->vchan.chan.device->dev;
1736 struct edma_desc *edesc;
Joel Fernandesc5f47992013-08-29 18:05:43 -05001737 struct edmacc_param p;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001738
Joel Fernandes50a9c702013-10-31 16:31:23 -05001739 edesc = echan->edesc;
1740
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001741 spin_lock(&echan->vchan.lock);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001742 switch (ch_status) {
Vinod Kouldb60d8d2013-10-30 18:22:30 +05301743 case EDMA_DMA_COMPLETE:
Matt Porterc2dde5f2012-08-22 21:09:34 -04001744 if (edesc) {
Joel Fernandes50a9c702013-10-31 16:31:23 -05001745 if (edesc->cyclic) {
1746 vchan_cyclic_callback(&edesc->vdesc);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001747 goto out;
Joel Fernandes50a9c702013-10-31 16:31:23 -05001748 } else if (edesc->processed == edesc->pset_nr) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001749 dev_dbg(dev,
1750 "Transfer completed on channel %d\n",
1751 ch_num);
Thomas Gleixnerb6205c32014-04-28 14:18:45 -05001752 edesc->residue = 0;
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001753 edma_stop(ecc, echan->ch_num);
Joel Fernandes53407062013-09-03 10:02:46 -05001754 vchan_cookie_complete(&edesc->vdesc);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001755 echan->edesc = NULL;
Joel Fernandes53407062013-09-03 10:02:46 -05001756 } else {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001757 dev_dbg(dev,
1758 "Sub transfer completed on channel %d\n",
1759 ch_num);
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001760
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001761 edma_pause(ecc, echan->ch_num);
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001762
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001763 /* Update statistics for tx_status */
1764 edesc->residue -= edesc->sg_len;
1765 edesc->residue_stat = edesc->residue;
1766 edesc->processed_stat = edesc->processed;
Joel Fernandes53407062013-09-03 10:02:46 -05001767 }
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001768 edma_execute(echan);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001769 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04001770 break;
Vinod Kouldb60d8d2013-10-30 18:22:30 +05301771 case EDMA_DMA_CC_ERROR:
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001772 edma_read_slot(ecc, echan->slot[0], &p);
Joel Fernandesc5f47992013-08-29 18:05:43 -05001773
1774 /*
1775 * Issue later based on missed flag which will be sure
1776 * to happen as:
1777 * (1) we finished transmitting an intermediate slot and
1778 * edma_execute is coming up.
1779 * (2) or we finished current transfer and issue will
1780 * call edma_execute.
1781 *
1782 * Important note: issuing can be dangerous here and
1783 * lead to some nasty recursion when we are in a NULL
1784 * slot. So we avoid doing so and set the missed flag.
1785 */
1786 if (p.a_b_cnt == 0 && p.ccnt == 0) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001787 dev_dbg(dev, "Error on null slot, setting miss\n");
Joel Fernandesc5f47992013-08-29 18:05:43 -05001788 echan->missed = 1;
1789 } else {
1790 /*
1791 * The slot is already programmed but the event got
1792 * missed, so its safe to issue it here.
1793 */
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001794 dev_dbg(dev, "Missed event, TRIGGERING\n");
1795 edma_clean_channel(ecc, echan->ch_num);
1796 edma_stop(ecc, echan->ch_num);
1797 edma_start(ecc, echan->ch_num);
1798 edma_trigger_channel(ecc, echan->ch_num);
Joel Fernandesc5f47992013-08-29 18:05:43 -05001799 }
Matt Porterc2dde5f2012-08-22 21:09:34 -04001800 break;
1801 default:
1802 break;
1803 }
Peter Ujfalusi8fa7ff42015-10-14 14:42:45 +03001804out:
1805 spin_unlock(&echan->vchan.lock);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001806}
1807
1808/* Alloc channel resources */
1809static int edma_alloc_chan_resources(struct dma_chan *chan)
1810{
1811 struct edma_chan *echan = to_edma_chan(chan);
1812 struct device *dev = chan->device->dev;
1813 int ret;
1814 int a_ch_num;
1815 LIST_HEAD(descs);
1816
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001817 a_ch_num = edma_alloc_channel(echan->ecc, echan->ch_num,
Peter Ujfalusica304fa2015-10-14 14:42:49 +03001818 edma_callback, echan, EVENTQ_DEFAULT);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001819
1820 if (a_ch_num < 0) {
1821 ret = -ENODEV;
1822 goto err_no_chan;
1823 }
1824
1825 if (a_ch_num != echan->ch_num) {
1826 dev_err(dev, "failed to allocate requested channel %u:%u\n",
1827 EDMA_CTLR(echan->ch_num),
1828 EDMA_CHAN_SLOT(echan->ch_num));
1829 ret = -ENODEV;
1830 goto err_wrong_chan;
1831 }
1832
1833 echan->alloced = true;
1834 echan->slot[0] = echan->ch_num;
1835
Peter Ujfalusi9aac9092014-04-24 10:29:50 +03001836 dev_dbg(dev, "allocated channel %d for %u:%u\n", echan->ch_num,
Ezequiel Garcia0e772c62013-12-13 11:06:18 -03001837 EDMA_CTLR(echan->ch_num), EDMA_CHAN_SLOT(echan->ch_num));
Matt Porterc2dde5f2012-08-22 21:09:34 -04001838
1839 return 0;
1840
1841err_wrong_chan:
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001842 edma_free_channel(echan->ecc, a_ch_num);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001843err_no_chan:
1844 return ret;
1845}
1846
1847/* Free channel resources */
1848static void edma_free_chan_resources(struct dma_chan *chan)
1849{
1850 struct edma_chan *echan = to_edma_chan(chan);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001851 int i;
1852
1853 /* Terminate transfers */
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001854 edma_stop(echan->ecc, echan->ch_num);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001855
1856 vchan_free_chan_resources(&echan->vchan);
1857
1858 /* Free EDMA PaRAM slots */
1859 for (i = 1; i < EDMA_MAX_SLOTS; i++) {
1860 if (echan->slot[i] >= 0) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001861 edma_free_slot(echan->ecc, echan->slot[i]);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001862 echan->slot[i] = -1;
1863 }
1864 }
1865
1866 /* Free EDMA channel */
1867 if (echan->alloced) {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001868 edma_free_channel(echan->ecc, echan->ch_num);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001869 echan->alloced = false;
1870 }
1871
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03001872 dev_dbg(chan->device->dev, "freeing channel for %u\n", echan->ch_num);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001873}
1874
1875/* Send pending descriptor to hardware */
1876static void edma_issue_pending(struct dma_chan *chan)
1877{
1878 struct edma_chan *echan = to_edma_chan(chan);
1879 unsigned long flags;
1880
1881 spin_lock_irqsave(&echan->vchan.lock, flags);
1882 if (vchan_issue_pending(&echan->vchan) && !echan->edesc)
1883 edma_execute(echan);
1884 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1885}
1886
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001887static u32 edma_residue(struct edma_desc *edesc)
1888{
1889 bool dst = edesc->direction == DMA_DEV_TO_MEM;
1890 struct edma_pset *pset = edesc->pset;
1891 dma_addr_t done, pos;
1892 int i;
1893
1894 /*
1895 * We always read the dst/src position from the first RamPar
1896 * pset. That's the one which is active now.
1897 */
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001898 pos = edma_get_position(edesc->echan->ecc, edesc->echan->slot[0], dst);
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001899
1900 /*
1901 * Cyclic is simple. Just subtract pset[0].addr from pos.
1902 *
1903 * We never update edesc->residue in the cyclic case, so we
1904 * can tell the remaining room to the end of the circular
1905 * buffer.
1906 */
1907 if (edesc->cyclic) {
1908 done = pos - pset->addr;
1909 edesc->residue_stat = edesc->residue - done;
1910 return edesc->residue_stat;
1911 }
1912
1913 /*
1914 * For SG operation we catch up with the last processed
1915 * status.
1916 */
1917 pset += edesc->processed_stat;
1918
1919 for (i = edesc->processed_stat; i < edesc->processed; i++, pset++) {
1920 /*
1921 * If we are inside this pset address range, we know
1922 * this is the active one. Get the current delta and
1923 * stop walking the psets.
1924 */
1925 if (pos >= pset->addr && pos < pset->addr + pset->len)
1926 return edesc->residue_stat - (pos - pset->addr);
1927
1928 /* Otherwise mark it done and update residue_stat. */
1929 edesc->processed_stat++;
1930 edesc->residue_stat -= pset->len;
1931 }
1932 return edesc->residue_stat;
1933}
1934
Matt Porterc2dde5f2012-08-22 21:09:34 -04001935/* Check request completion status */
1936static enum dma_status edma_tx_status(struct dma_chan *chan,
1937 dma_cookie_t cookie,
1938 struct dma_tx_state *txstate)
1939{
1940 struct edma_chan *echan = to_edma_chan(chan);
1941 struct virt_dma_desc *vdesc;
1942 enum dma_status ret;
1943 unsigned long flags;
1944
1945 ret = dma_cookie_status(chan, cookie, txstate);
Vinod Koul9d386ec2013-10-16 13:42:15 +05301946 if (ret == DMA_COMPLETE || !txstate)
Matt Porterc2dde5f2012-08-22 21:09:34 -04001947 return ret;
1948
1949 spin_lock_irqsave(&echan->vchan.lock, flags);
Thomas Gleixnerde135932014-04-28 14:19:51 -05001950 if (echan->edesc && echan->edesc->vdesc.tx.cookie == cookie)
Thomas Gleixner740b41f2014-04-28 14:34:11 -05001951 txstate->residue = edma_residue(echan->edesc);
Thomas Gleixnerde135932014-04-28 14:19:51 -05001952 else if ((vdesc = vchan_find_desc(&echan->vchan, cookie)))
1953 txstate->residue = to_edma_desc(&vdesc->tx)->residue;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001954 spin_unlock_irqrestore(&echan->vchan.lock, flags);
1955
1956 return ret;
1957}
1958
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001959static void __init edma_chan_init(struct edma_cc *ecc, struct dma_device *dma,
Matt Porterc2dde5f2012-08-22 21:09:34 -04001960 struct edma_chan *echans)
1961{
1962 int i, j;
1963
Peter Ujfalusicb782052015-10-14 14:42:54 +03001964 for (i = 0; i < ecc->num_channels; i++) {
Matt Porterc2dde5f2012-08-22 21:09:34 -04001965 struct edma_chan *echan = &echans[i];
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03001966 echan->ch_num = EDMA_CTLR_CHAN(ecc->id, i);
Matt Porterc2dde5f2012-08-22 21:09:34 -04001967 echan->ecc = ecc;
1968 echan->vchan.desc_free = edma_desc_free;
1969
1970 vchan_init(&echan->vchan, dma);
1971
1972 INIT_LIST_HEAD(&echan->node);
1973 for (j = 0; j < EDMA_MAX_SLOTS; j++)
1974 echan->slot[j] = -1;
1975 }
1976}
1977
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +03001978#define EDMA_DMA_BUSWIDTHS (BIT(DMA_SLAVE_BUSWIDTH_1_BYTE) | \
1979 BIT(DMA_SLAVE_BUSWIDTH_2_BYTES) | \
Peter Ujfalusie4a899d2014-07-03 07:51:56 +03001980 BIT(DMA_SLAVE_BUSWIDTH_3_BYTES) | \
Peter Ujfalusi2c88ee62014-04-14 14:42:01 +03001981 BIT(DMA_SLAVE_BUSWIDTH_4_BYTES))
1982
Matt Porterc2dde5f2012-08-22 21:09:34 -04001983static void edma_dma_init(struct edma_cc *ecc, struct dma_device *dma,
1984 struct device *dev)
1985{
1986 dma->device_prep_slave_sg = edma_prep_slave_sg;
Joel Fernandes50a9c702013-10-31 16:31:23 -05001987 dma->device_prep_dma_cyclic = edma_prep_dma_cyclic;
Joel Fernandes8cc3e302014-04-18 21:50:33 -05001988 dma->device_prep_dma_memcpy = edma_prep_dma_memcpy;
Matt Porterc2dde5f2012-08-22 21:09:34 -04001989 dma->device_alloc_chan_resources = edma_alloc_chan_resources;
1990 dma->device_free_chan_resources = edma_free_chan_resources;
1991 dma->device_issue_pending = edma_issue_pending;
1992 dma->device_tx_status = edma_tx_status;
Maxime Ripardaa7c09b2014-11-17 14:42:13 +01001993 dma->device_config = edma_slave_config;
1994 dma->device_pause = edma_dma_pause;
1995 dma->device_resume = edma_dma_resume;
1996 dma->device_terminate_all = edma_terminate_all;
Maxime Ripard9f59cd02014-11-17 14:42:47 +01001997
1998 dma->src_addr_widths = EDMA_DMA_BUSWIDTHS;
1999 dma->dst_addr_widths = EDMA_DMA_BUSWIDTHS;
2000 dma->directions = BIT(DMA_DEV_TO_MEM) | BIT(DMA_MEM_TO_DEV);
2001 dma->residue_granularity = DMA_RESIDUE_GRANULARITY_BURST;
2002
Matt Porterc2dde5f2012-08-22 21:09:34 -04002003 dma->dev = dev;
2004
Joel Fernandes8cc3e302014-04-18 21:50:33 -05002005 /*
2006 * code using dma memcpy must make sure alignment of
2007 * length is at dma->copy_align boundary.
2008 */
Maxime Ripard77a68e52015-07-20 10:41:32 +02002009 dma->copy_align = DMAENGINE_ALIGN_4_BYTES;
Joel Fernandes8cc3e302014-04-18 21:50:33 -05002010
Matt Porterc2dde5f2012-08-22 21:09:34 -04002011 INIT_LIST_HEAD(&dma->channels);
2012}
2013
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002014static int edma_setup_from_hw(struct device *dev, struct edma_soc_info *pdata,
2015 struct edma_cc *ecc)
2016{
2017 int i;
2018 u32 value, cccfg;
2019 s8 (*queue_priority_map)[2];
2020
2021 /* Decode the eDMA3 configuration from CCCFG register */
2022 cccfg = edma_read(ecc, EDMA_CCCFG);
2023
2024 value = GET_NUM_REGN(cccfg);
2025 ecc->num_region = BIT(value);
2026
2027 value = GET_NUM_DMACH(cccfg);
2028 ecc->num_channels = BIT(value + 1);
2029
2030 value = GET_NUM_PAENTRY(cccfg);
2031 ecc->num_slots = BIT(value + 4);
2032
2033 value = GET_NUM_EVQUE(cccfg);
2034 ecc->num_tc = value + 1;
2035
2036 dev_dbg(dev, "eDMA3 CC HW configuration (cccfg: 0x%08x):\n", cccfg);
2037 dev_dbg(dev, "num_region: %u\n", ecc->num_region);
2038 dev_dbg(dev, "num_channels: %u\n", ecc->num_channels);
2039 dev_dbg(dev, "num_slots: %u\n", ecc->num_slots);
2040 dev_dbg(dev, "num_tc: %u\n", ecc->num_tc);
2041
2042 /* Nothing need to be done if queue priority is provided */
2043 if (pdata->queue_priority_mapping)
2044 return 0;
2045
2046 /*
2047 * Configure TC/queue priority as follows:
2048 * Q0 - priority 0
2049 * Q1 - priority 1
2050 * Q2 - priority 2
2051 * ...
2052 * The meaning of priority numbers: 0 highest priority, 7 lowest
2053 * priority. So Q0 is the highest priority queue and the last queue has
2054 * the lowest priority.
2055 */
Peter Ujfalusi547c6e22015-10-14 14:42:55 +03002056 queue_priority_map = devm_kcalloc(dev, ecc->num_tc + 1, sizeof(s8),
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002057 GFP_KERNEL);
2058 if (!queue_priority_map)
2059 return -ENOMEM;
2060
2061 for (i = 0; i < ecc->num_tc; i++) {
2062 queue_priority_map[i][0] = i;
2063 queue_priority_map[i][1] = i;
2064 }
2065 queue_priority_map[i][0] = -1;
2066 queue_priority_map[i][1] = -1;
2067
2068 pdata->queue_priority_mapping = queue_priority_map;
2069 /* Default queue has the lowest priority */
2070 pdata->default_queue = i - 1;
2071
2072 return 0;
2073}
2074
2075#if IS_ENABLED(CONFIG_OF)
2076static int edma_xbar_event_map(struct device *dev, struct edma_soc_info *pdata,
2077 size_t sz)
2078{
2079 const char pname[] = "ti,edma-xbar-event-map";
2080 struct resource res;
2081 void __iomem *xbar;
2082 s16 (*xbar_chans)[2];
2083 size_t nelm = sz / sizeof(s16);
2084 u32 shift, offset, mux;
2085 int ret, i;
2086
Peter Ujfalusi547c6e22015-10-14 14:42:55 +03002087 xbar_chans = devm_kcalloc(dev, nelm + 2, sizeof(s16), GFP_KERNEL);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002088 if (!xbar_chans)
2089 return -ENOMEM;
2090
2091 ret = of_address_to_resource(dev->of_node, 1, &res);
2092 if (ret)
2093 return -ENOMEM;
2094
2095 xbar = devm_ioremap(dev, res.start, resource_size(&res));
2096 if (!xbar)
2097 return -ENOMEM;
2098
2099 ret = of_property_read_u16_array(dev->of_node, pname, (u16 *)xbar_chans,
2100 nelm);
2101 if (ret)
2102 return -EIO;
2103
2104 /* Invalidate last entry for the other user of this mess */
2105 nelm >>= 1;
2106 xbar_chans[nelm][0] = -1;
2107 xbar_chans[nelm][1] = -1;
2108
2109 for (i = 0; i < nelm; i++) {
2110 shift = (xbar_chans[i][1] & 0x03) << 3;
2111 offset = xbar_chans[i][1] & 0xfffffffc;
2112 mux = readl(xbar + offset);
2113 mux &= ~(0xff << shift);
2114 mux |= xbar_chans[i][0] << shift;
2115 writel(mux, (xbar + offset));
2116 }
2117
2118 pdata->xbar_chans = (const s16 (*)[2]) xbar_chans;
2119 return 0;
2120}
2121
2122static int edma_of_parse_dt(struct device *dev, struct edma_soc_info *pdata)
2123{
2124 int ret = 0;
2125 struct property *prop;
2126 size_t sz;
2127 struct edma_rsv_info *rsv_info;
2128
2129 rsv_info = devm_kzalloc(dev, sizeof(struct edma_rsv_info), GFP_KERNEL);
2130 if (!rsv_info)
2131 return -ENOMEM;
2132 pdata->rsv = rsv_info;
2133
2134 prop = of_find_property(dev->of_node, "ti,edma-xbar-event-map", &sz);
2135 if (prop)
2136 ret = edma_xbar_event_map(dev, pdata, sz);
2137
2138 return ret;
2139}
2140
2141static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev)
2142{
2143 struct edma_soc_info *info;
2144 int ret;
2145
2146 info = devm_kzalloc(dev, sizeof(struct edma_soc_info), GFP_KERNEL);
2147 if (!info)
2148 return ERR_PTR(-ENOMEM);
2149
2150 ret = edma_of_parse_dt(dev, info);
2151 if (ret)
2152 return ERR_PTR(ret);
2153
2154 return info;
2155}
2156#else
2157static struct edma_soc_info *edma_setup_info_from_dt(struct device *dev)
2158{
2159 return ERR_PTR(-EINVAL);
2160}
2161#endif
2162
Bill Pemberton463a1f82012-11-19 13:22:55 -05002163static int edma_probe(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -04002164{
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002165 struct edma_soc_info *info = pdev->dev.platform_data;
2166 s8 (*queue_priority_mapping)[2];
2167 int i, off, ln;
2168 const s16 (*rsv_chans)[2];
2169 const s16 (*rsv_slots)[2];
2170 const s16 (*xbar_chans)[2];
2171 int irq;
2172 char *irq_name;
2173 struct resource *mem;
2174 struct device_node *node = pdev->dev.of_node;
2175 struct device *dev = &pdev->dev;
2176 struct edma_cc *ecc;
Matt Porterc2dde5f2012-08-22 21:09:34 -04002177 int ret;
2178
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002179 if (node) {
2180 info = edma_setup_info_from_dt(dev);
2181 if (IS_ERR(info)) {
2182 dev_err(dev, "failed to get DT data\n");
2183 return PTR_ERR(info);
2184 }
2185 }
2186
2187 if (!info)
2188 return -ENODEV;
2189
2190 pm_runtime_enable(dev);
2191 ret = pm_runtime_get_sync(dev);
2192 if (ret < 0) {
2193 dev_err(dev, "pm_runtime_get_sync() failed\n");
2194 return ret;
2195 }
2196
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002197 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
Russell King94cb0e72013-06-27 13:45:16 +01002198 if (ret)
2199 return ret;
2200
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002201 ecc = devm_kzalloc(dev, sizeof(*ecc), GFP_KERNEL);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002202 if (!ecc) {
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002203 dev_err(dev, "Can't allocate controller\n");
Matt Porterc2dde5f2012-08-22 21:09:34 -04002204 return -ENOMEM;
2205 }
2206
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002207 ecc->dev = dev;
2208 ecc->id = pdev->id;
2209 /* When booting with DT the pdev->id is -1 */
2210 if (ecc->id < 0)
2211 ecc->id = 0;
Peter Ujfalusica304fa2015-10-14 14:42:49 +03002212
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002213 mem = platform_get_resource_byname(pdev, IORESOURCE_MEM, "edma3_cc");
2214 if (!mem) {
2215 dev_dbg(dev, "mem resource not found, using index 0\n");
2216 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
2217 if (!mem) {
2218 dev_err(dev, "no mem resource?\n");
2219 return -ENODEV;
2220 }
2221 }
2222 ecc->base = devm_ioremap_resource(dev, mem);
2223 if (IS_ERR(ecc->base))
2224 return PTR_ERR(ecc->base);
Peter Ujfalusib2c843a2015-10-14 14:42:50 +03002225
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002226 platform_set_drvdata(pdev, ecc);
2227
2228 /* Get eDMA3 configuration from IP */
2229 ret = edma_setup_from_hw(dev, info, ecc);
2230 if (ret)
2231 return ret;
2232
Peter Ujfalusicb782052015-10-14 14:42:54 +03002233 /* Allocate memory based on the information we got from the IP */
2234 ecc->slave_chans = devm_kcalloc(dev, ecc->num_channels,
2235 sizeof(*ecc->slave_chans), GFP_KERNEL);
2236 if (!ecc->slave_chans)
2237 return -ENOMEM;
2238
2239 ecc->intr_data = devm_kcalloc(dev, ecc->num_channels,
2240 sizeof(*ecc->intr_data), GFP_KERNEL);
2241 if (!ecc->intr_data)
2242 return -ENOMEM;
2243
2244 ecc->edma_unused = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_channels),
2245 sizeof(unsigned long), GFP_KERNEL);
2246 if (!ecc->edma_unused)
2247 return -ENOMEM;
2248
2249 ecc->edma_inuse = devm_kcalloc(dev, BITS_TO_LONGS(ecc->num_slots),
2250 sizeof(unsigned long), GFP_KERNEL);
2251 if (!ecc->edma_inuse)
2252 return -ENOMEM;
2253
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002254 ecc->default_queue = info->default_queue;
2255
2256 for (i = 0; i < ecc->num_slots; i++)
2257 edma_write_slot(ecc, i, &dummy_paramset);
2258
2259 /* Mark all channels as unused */
2260 memset(ecc->edma_unused, 0xff, sizeof(ecc->edma_unused));
2261
2262 if (info->rsv) {
2263 /* Clear the reserved channels in unused list */
2264 rsv_chans = info->rsv->rsv_chans;
2265 if (rsv_chans) {
2266 for (i = 0; rsv_chans[i][0] != -1; i++) {
2267 off = rsv_chans[i][0];
2268 ln = rsv_chans[i][1];
2269 clear_bits(off, ln, ecc->edma_unused);
2270 }
2271 }
2272
2273 /* Set the reserved slots in inuse list */
2274 rsv_slots = info->rsv->rsv_slots;
2275 if (rsv_slots) {
2276 for (i = 0; rsv_slots[i][0] != -1; i++) {
2277 off = rsv_slots[i][0];
2278 ln = rsv_slots[i][1];
2279 set_bits(off, ln, ecc->edma_inuse);
2280 }
2281 }
2282 }
2283
2284 /* Clear the xbar mapped channels in unused list */
2285 xbar_chans = info->xbar_chans;
2286 if (xbar_chans) {
2287 for (i = 0; xbar_chans[i][1] != -1; i++) {
2288 off = xbar_chans[i][1];
2289 clear_bits(off, 1, ecc->edma_unused);
2290 }
2291 }
2292
2293 irq = platform_get_irq_byname(pdev, "edma3_ccint");
2294 if (irq < 0 && node)
2295 irq = irq_of_parse_and_map(node, 0);
2296
2297 if (irq >= 0) {
2298 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccint",
2299 dev_name(dev));
2300 ret = devm_request_irq(dev, irq, dma_irq_handler, 0, irq_name,
2301 ecc);
2302 if (ret) {
2303 dev_err(dev, "CCINT (%d) failed --> %d\n", irq, ret);
2304 return ret;
2305 }
2306 }
2307
2308 irq = platform_get_irq_byname(pdev, "edma3_ccerrint");
2309 if (irq < 0 && node)
2310 irq = irq_of_parse_and_map(node, 2);
2311
2312 if (irq >= 0) {
2313 irq_name = devm_kasprintf(dev, GFP_KERNEL, "%s_ccerrint",
2314 dev_name(dev));
2315 ret = devm_request_irq(dev, irq, dma_ccerr_handler, 0, irq_name,
2316 ecc);
2317 if (ret) {
2318 dev_err(dev, "CCERRINT (%d) failed --> %d\n", irq, ret);
2319 return ret;
2320 }
2321 }
2322
2323 for (i = 0; i < ecc->num_channels; i++)
2324 edma_map_dmach_to_queue(ecc, i, info->default_queue);
2325
2326 queue_priority_mapping = info->queue_priority_mapping;
2327
2328 /* Event queue priority mapping */
2329 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2330 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2331 queue_priority_mapping[i][1]);
2332
2333 /* Map the channel to param entry if channel mapping logic exist */
2334 if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST)
2335 edma_direct_dmach_to_param_mapping(ecc);
2336
2337 for (i = 0; i < ecc->num_region; i++) {
2338 edma_write_array2(ecc, EDMA_DRAE, i, 0, 0x0);
2339 edma_write_array2(ecc, EDMA_DRAE, i, 1, 0x0);
2340 edma_write_array(ecc, EDMA_QRAE, i, 0x0);
2341 }
2342 ecc->info = info;
2343
2344 ecc->dummy_slot = edma_alloc_slot(ecc, EDMA_SLOT_ANY);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002345 if (ecc->dummy_slot < 0) {
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002346 dev_err(dev, "Can't allocate PaRAM dummy slot\n");
Peter Ujfalusi04d537d2014-07-31 13:12:37 +03002347 return ecc->dummy_slot;
Matt Porterc2dde5f2012-08-22 21:09:34 -04002348 }
2349
2350 dma_cap_zero(ecc->dma_slave.cap_mask);
2351 dma_cap_set(DMA_SLAVE, ecc->dma_slave.cap_mask);
Peter Ujfalusi232b223d2014-04-14 14:42:00 +03002352 dma_cap_set(DMA_CYCLIC, ecc->dma_slave.cap_mask);
Joel Fernandes8cc3e302014-04-18 21:50:33 -05002353 dma_cap_set(DMA_MEMCPY, ecc->dma_slave.cap_mask);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002354
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002355 edma_dma_init(ecc, &ecc->dma_slave, dev);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002356
2357 edma_chan_init(ecc, &ecc->dma_slave, ecc->slave_chans);
2358
2359 ret = dma_async_device_register(&ecc->dma_slave);
2360 if (ret)
2361 goto err_reg1;
2362
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002363 if (node)
2364 of_dma_controller_register(node, of_dma_xlate_by_chan_id,
Peter Ujfalusib2c843a2015-10-14 14:42:50 +03002365 &ecc->dma_slave);
Peter Ujfalusidc9b60552015-10-14 14:42:47 +03002366
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002367 dev_info(dev, "TI EDMA DMA engine driver\n");
Matt Porterc2dde5f2012-08-22 21:09:34 -04002368
2369 return 0;
2370
2371err_reg1:
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002372 edma_free_slot(ecc, ecc->dummy_slot);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002373 return ret;
2374}
2375
Greg Kroah-Hartman4bf27b82012-12-21 15:09:59 -08002376static int edma_remove(struct platform_device *pdev)
Matt Porterc2dde5f2012-08-22 21:09:34 -04002377{
2378 struct device *dev = &pdev->dev;
2379 struct edma_cc *ecc = dev_get_drvdata(dev);
2380
Peter Ujfalusi907f74a2015-10-14 14:42:56 +03002381 if (dev->of_node)
2382 of_dma_controller_free(dev->of_node);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002383 dma_async_device_unregister(&ecc->dma_slave);
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002384 edma_free_slot(ecc, ecc->dummy_slot);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002385
2386 return 0;
2387}
2388
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002389#ifdef CONFIG_PM_SLEEP
2390static int edma_pm_resume(struct device *dev)
2391{
2392 struct edma_cc *ecc = dev_get_drvdata(dev);
2393 int i;
2394 s8 (*queue_priority_mapping)[2];
2395
2396 queue_priority_mapping = ecc->info->queue_priority_mapping;
2397
2398 /* Event queue priority mapping */
2399 for (i = 0; queue_priority_mapping[i][0] != -1; i++)
2400 edma_assign_priority_to_queue(ecc, queue_priority_mapping[i][0],
2401 queue_priority_mapping[i][1]);
2402
2403 /* Map the channel to param entry if channel mapping logic */
2404 if (edma_read(ecc, EDMA_CCCFG) & CHMAP_EXIST)
2405 edma_direct_dmach_to_param_mapping(ecc);
2406
2407 for (i = 0; i < ecc->num_channels; i++) {
2408 if (test_bit(i, ecc->edma_inuse)) {
2409 /* ensure access through shadow region 0 */
2410 edma_or_array2(ecc, EDMA_DRAE, 0, i >> 5,
2411 BIT(i & 0x1f));
2412
2413 edma_setup_interrupt(ecc, EDMA_CTLR_CHAN(ecc->id, i),
2414 ecc->intr_data[i].callback,
2415 ecc->intr_data[i].data);
2416 }
2417 }
2418
2419 return 0;
2420}
2421#endif
2422
2423static const struct dev_pm_ops edma_pm_ops = {
2424 SET_LATE_SYSTEM_SLEEP_PM_OPS(NULL, edma_pm_resume)
2425};
2426
Matt Porterc2dde5f2012-08-22 21:09:34 -04002427static struct platform_driver edma_driver = {
2428 .probe = edma_probe,
Bill Pembertona7d6e3e2012-11-19 13:20:04 -05002429 .remove = edma_remove,
Matt Porterc2dde5f2012-08-22 21:09:34 -04002430 .driver = {
Peter Ujfalusi2b6b3b72015-10-14 14:42:53 +03002431 .name = "edma",
2432 .pm = &edma_pm_ops,
2433 .of_match_table = edma_of_ids,
Matt Porterc2dde5f2012-08-22 21:09:34 -04002434 },
2435};
2436
2437bool edma_filter_fn(struct dma_chan *chan, void *param)
2438{
2439 if (chan->device->dev->driver == &edma_driver.driver) {
2440 struct edma_chan *echan = to_edma_chan(chan);
2441 unsigned ch_req = *(unsigned *)param;
2442 return ch_req == echan->ch_num;
2443 }
2444 return false;
2445}
2446EXPORT_SYMBOL(edma_filter_fn);
2447
Matt Porterc2dde5f2012-08-22 21:09:34 -04002448static int edma_init(void)
2449{
Arnd Bergmann5305e4d2014-10-24 18:14:01 +02002450 return platform_driver_register(&edma_driver);
Matt Porterc2dde5f2012-08-22 21:09:34 -04002451}
2452subsys_initcall(edma_init);
2453
2454static void __exit edma_exit(void)
2455{
Matt Porterc2dde5f2012-08-22 21:09:34 -04002456 platform_driver_unregister(&edma_driver);
2457}
2458module_exit(edma_exit);
2459
Josh Boyerd71505b2013-09-04 10:32:50 -04002460MODULE_AUTHOR("Matt Porter <matt.porter@linaro.org>");
Matt Porterc2dde5f2012-08-22 21:09:34 -04002461MODULE_DESCRIPTION("TI EDMA DMA engine driver");
2462MODULE_LICENSE("GPL v2");