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Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +08001/*
2 * at91sam9260.dtsi - Device Tree Include file for AT91SAM9260 family SoC
3 *
4 * Copyright (C) 2011 Atmel,
5 * 2011 Nicolas Ferre <nicolas.ferre@atmel.com>,
6 * 2011 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
7 *
8 * Licensed under GPLv2 or later.
9 */
10
11/include/ "skeleton.dtsi"
12
13/ {
14 model = "Atmel AT91SAM9260 family SoC";
15 compatible = "atmel,at91sam9260";
16 interrupt-parent = <&aic>;
17
18 aliases {
19 serial0 = &dbgu;
20 serial1 = &usart0;
21 serial2 = &usart1;
22 serial3 = &usart2;
23 serial4 = &usart3;
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +080024 serial5 = &uart0;
25 serial6 = &uart1;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080026 gpio0 = &pioA;
27 gpio1 = &pioB;
28 gpio2 = &pioC;
29 tcb0 = &tcb0;
30 tcb1 = &tcb1;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020031 i2c0 = &i2c0;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080032 };
33 cpus {
34 cpu@0 {
35 compatible = "arm,arm926ejs";
36 };
37 };
38
39 memory {
40 reg = <0x20000000 0x04000000>;
41 };
42
43 ahb {
44 compatible = "simple-bus";
45 #address-cells = <1>;
46 #size-cells = <1>;
47 ranges;
48
49 apb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020056 #interrupt-cells = <3>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080057 compatible = "atmel,at91rm9200-aic";
58 interrupt-controller;
59 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080060 atmel,external-irqs = <29 30 31>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080061 };
62
63 ramc0: ramc@ffffea00 {
64 compatible = "atmel,at91sam9260-sdramc";
65 reg = <0xffffea00 0x200>;
66 };
67
68 pmc: pmc@fffffc00 {
69 compatible = "atmel,at91rm9200-pmc";
70 reg = <0xfffffc00 0x100>;
71 };
72
73 rstc@fffffd00 {
74 compatible = "atmel,at91sam9260-rstc";
75 reg = <0xfffffd00 0x10>;
76 };
77
78 shdwc@fffffd10 {
79 compatible = "atmel,at91sam9260-shdwc";
80 reg = <0xfffffd10 0x10>;
81 };
82
83 pit: timer@fffffd30 {
84 compatible = "atmel,at91sam9260-pit";
85 reg = <0xfffffd30 0xf>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020086 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080087 };
88
89 tcb0: timer@fffa0000 {
90 compatible = "atmel,at91rm9200-tcb";
91 reg = <0xfffa0000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020092 interrupts = <17 4 0 18 4 0 19 4 0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080093 };
94
95 tcb1: timer@fffdc000 {
96 compatible = "atmel,at91rm9200-tcb";
97 reg = <0xfffdc000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020098 interrupts = <26 4 0 27 4 0 28 4 0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +080099 };
100
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800101 pinctrl@fffff400 {
102 #address-cells = <1>;
103 #size-cells = <1>;
104 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
105 ranges = <0xfffff400 0xfffff400 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800106
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800107 atmel,mux-mask = <
108 /* A B */
109 0xffffffff 0xffc00c3b /* pioA */
110 0xffffffff 0x7fff3ccf /* pioB */
111 0xffffffff 0x007fffff /* pioC */
112 >;
113
114 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800115 dbgu {
116 pinctrl_dbgu: dbgu-0 {
117 atmel,pins =
118 <1 14 0x1 0x0 /* PB14 periph A */
119 1 15 0x1 0x1>; /* PB15 periph with pullup */
120 };
121 };
122
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800123 usart0 {
124 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800125 atmel,pins =
126 <1 4 0x1 0x0 /* PB4 periph A */
127 1 5 0x1 0x0>; /* PB5 periph A */
128 };
129
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800130 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800131 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800132 <1 26 0x1 0x0>; /* PB26 periph A */
133 };
134
135 pinctrl_usart0_cts: usart0_cts-0 {
136 atmel,pins =
137 <1 27 0x1 0x0>; /* PB27 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800138 };
139
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800140 pinctrl_usart0_dtr_dsr: usart0_dtr_dsr-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800141 atmel,pins =
142 <1 24 0x1 0x0 /* PB24 periph A */
143 1 22 0x1 0x0>; /* PB22 periph A */
144 };
145
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800146 pinctrl_usart0_dcd: usart0_dcd-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800147 atmel,pins =
148 <1 23 0x1 0x0>; /* PB23 periph A */
149 };
150
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800151 pinctrl_usart0_ri: usart0_ri-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800152 atmel,pins =
153 <1 25 0x1 0x0>; /* PB25 periph A */
154 };
155 };
156
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800157 usart1 {
158 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800159 atmel,pins =
160 <2 6 0x1 0x1 /* PB6 periph A with pullup */
161 2 7 0x1 0x0>; /* PB7 periph A */
162 };
163
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800164 pinctrl_usart1_rts: usart1_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800165 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800166 <1 28 0x1 0x0>; /* PB28 periph A */
167 };
168
169 pinctrl_usart1_cts: usart1_cts-0 {
170 atmel,pins =
171 <1 29 0x1 0x0>; /* PB29 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800172 };
173 };
174
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800175 usart2 {
176 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800177 atmel,pins =
178 <1 8 0x1 0x1 /* PB8 periph A with pullup */
179 1 9 0x1 0x0>; /* PB9 periph A */
180 };
181
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800182 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800183 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800184 <0 4 0x1 0x0>; /* PA4 periph A */
185 };
186
187 pinctrl_usart2_cts: usart2_cts-0 {
188 atmel,pins =
189 <0 5 0x1 0x0>; /* PA5 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800190 };
191 };
192
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800193 usart3 {
194 pinctrl_usart3: usart3-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800195 atmel,pins =
196 <2 10 0x1 0x1 /* PB10 periph A with pullup */
197 2 11 0x1 0x0>; /* PB11 periph A */
198 };
199
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800200 pinctrl_usart3_rts: usart3_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800201 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800202 <3 8 0x2 0x0>; /* PB8 periph B */
203 };
204
205 pinctrl_usart3_cts: usart3_cts-0 {
206 atmel,pins =
207 <3 10 0x2 0x0>; /* PB10 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800208 };
209 };
210
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800211 uart0 {
212 pinctrl_uart0: uart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800213 atmel,pins =
214 <0 31 0x2 0x1 /* PA31 periph B with pullup */
215 0 30 0x2 0x0>; /* PA30 periph B */
216 };
217 };
218
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800219 uart1 {
220 pinctrl_uart1: uart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800221 atmel,pins =
222 <2 12 0x1 0x1 /* PB12 periph A with pullup */
223 2 13 0x1 0x0>; /* PB13 periph A */
224 };
225 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800226
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800227 nand {
228 pinctrl_nand: nand-0 {
229 atmel,pins =
230 <2 13 0x0 0x1 /* PC13 gpio RDY pin pull_up */
231 2 14 0x0 0x1>; /* PC14 gpio enable pin pull_up */
232 };
233 };
234
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800235 macb {
236 pinctrl_macb_rmii: macb_rmii-0 {
237 atmel,pins =
238 <0 12 0x1 0x0 /* PA12 periph A */
239 0 13 0x1 0x0 /* PA13 periph A */
240 0 14 0x1 0x0 /* PA14 periph A */
241 0 15 0x1 0x0 /* PA15 periph A */
242 0 16 0x1 0x0 /* PA16 periph A */
243 0 17 0x1 0x0 /* PA17 periph A */
244 0 18 0x1 0x0 /* PA18 periph A */
245 0 19 0x1 0x0 /* PA19 periph A */
246 0 20 0x1 0x0 /* PA20 periph A */
247 0 21 0x1 0x0>; /* PA21 periph A */
248 };
249
250 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
251 atmel,pins =
252 <0 22 0x2 0x0 /* PA22 periph B */
253 0 23 0x2 0x0 /* PA23 periph B */
254 0 24 0x2 0x0 /* PA24 periph B */
255 0 25 0x2 0x0 /* PA25 periph B */
256 0 26 0x2 0x0 /* PA26 periph B */
257 0 27 0x2 0x0 /* PA27 periph B */
258 0 28 0x2 0x0 /* PA28 periph B */
259 0 29 0x2 0x0>; /* PA29 periph B */
260 };
261
262 pinctrl_macb_rmii_mii_alt: macb_rmii_mii-1 {
263 atmel,pins =
264 <0 10 0x2 0x0 /* PA10 periph B */
265 0 11 0x2 0x0 /* PA11 periph B */
266 0 24 0x2 0x0 /* PA24 periph B */
267 0 25 0x2 0x0 /* PA25 periph B */
268 0 26 0x2 0x0 /* PA26 periph B */
269 0 27 0x2 0x0 /* PA27 periph B */
270 0 28 0x2 0x0 /* PA28 periph B */
271 0 29 0x2 0x0>; /* PA29 periph B */
272 };
273 };
274
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800275 pioA: gpio@fffff400 {
276 compatible = "atmel,at91rm9200-gpio";
277 reg = <0xfffff400 0x200>;
278 interrupts = <2 4 1>;
279 #gpio-cells = <2>;
280 gpio-controller;
281 interrupt-controller;
282 #interrupt-cells = <2>;
283 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800284
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800285 pioB: gpio@fffff600 {
286 compatible = "atmel,at91rm9200-gpio";
287 reg = <0xfffff600 0x200>;
288 interrupts = <3 4 1>;
289 #gpio-cells = <2>;
290 gpio-controller;
291 interrupt-controller;
292 #interrupt-cells = <2>;
293 };
294
295 pioC: gpio@fffff800 {
296 compatible = "atmel,at91rm9200-gpio";
297 reg = <0xfffff800 0x200>;
298 interrupts = <4 4 1>;
299 #gpio-cells = <2>;
300 gpio-controller;
301 interrupt-controller;
302 #interrupt-cells = <2>;
303 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800304 };
305
306 dbgu: serial@fffff200 {
307 compatible = "atmel,at91sam9260-usart";
308 reg = <0xfffff200 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200309 interrupts = <1 4 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800310 pinctrl-names = "default";
311 pinctrl-0 = <&pinctrl_dbgu>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800312 status = "disabled";
313 };
314
315 usart0: serial@fffb0000 {
316 compatible = "atmel,at91sam9260-usart";
317 reg = <0xfffb0000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200318 interrupts = <6 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800319 atmel,use-dma-rx;
320 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800321 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800322 pinctrl-0 = <&pinctrl_usart0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800323 status = "disabled";
324 };
325
326 usart1: serial@fffb4000 {
327 compatible = "atmel,at91sam9260-usart";
328 reg = <0xfffb4000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200329 interrupts = <7 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800330 atmel,use-dma-rx;
331 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800332 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800333 pinctrl-0 = <&pinctrl_usart1>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800334 status = "disabled";
335 };
336
337 usart2: serial@fffb8000 {
338 compatible = "atmel,at91sam9260-usart";
339 reg = <0xfffb8000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200340 interrupts = <8 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800341 atmel,use-dma-rx;
342 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800343 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800344 pinctrl-0 = <&pinctrl_usart2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800345 status = "disabled";
346 };
347
348 usart3: serial@fffd0000 {
349 compatible = "atmel,at91sam9260-usart";
350 reg = <0xfffd0000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200351 interrupts = <23 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800352 atmel,use-dma-rx;
353 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800354 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800355 pinctrl-0 = <&pinctrl_usart3>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800356 status = "disabled";
357 };
358
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800359 uart0: serial@fffd4000 {
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800360 compatible = "atmel,at91sam9260-usart";
361 reg = <0xfffd4000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200362 interrupts = <24 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800363 atmel,use-dma-rx;
364 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800365 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800366 pinctrl-0 = <&pinctrl_uart0>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800367 status = "disabled";
368 };
369
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800370 uart1: serial@fffd8000 {
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800371 compatible = "atmel,at91sam9260-usart";
372 reg = <0xfffd8000 0x200>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200373 interrupts = <25 4 5>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800374 atmel,use-dma-rx;
375 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800376 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800377 pinctrl-0 = <&pinctrl_uart1>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800378 status = "disabled";
379 };
380
381 macb0: ethernet@fffc4000 {
382 compatible = "cdns,at32ap7000-macb", "cdns,macb";
383 reg = <0xfffc4000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200384 interrupts = <21 4 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800385 pinctrl-names = "default";
386 pinctrl-0 = <&pinctrl_macb_rmii>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800387 status = "disabled";
388 };
389
390 usb1: gadget@fffa4000 {
391 compatible = "atmel,at91rm9200-udc";
392 reg = <0xfffa4000 0x4000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200393 interrupts = <10 4 2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800394 status = "disabled";
395 };
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200396
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200397 i2c0: i2c@fffac000 {
398 compatible = "atmel,at91sam9260-i2c";
399 reg = <0xfffac000 0x100>;
400 interrupts = <11 4 6>;
401 #address-cells = <1>;
402 #size-cells = <0>;
403 status = "disabled";
404 };
405
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200406 adc0: adc@fffe0000 {
407 compatible = "atmel,at91sam9260-adc";
408 reg = <0xfffe0000 0x100>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200409 interrupts = <5 4 0>;
Nicolas Ferre73d68d92012-05-16 17:37:06 +0200410 atmel,adc-use-external-triggers;
411 atmel,adc-channels-used = <0xf>;
412 atmel,adc-vref = <3300>;
413 atmel,adc-num-channels = <4>;
414 atmel,adc-startup-time = <15>;
415 atmel,adc-channel-base = <0x30>;
416 atmel,adc-drdy-mask = <0x10000>;
417 atmel,adc-status-register = <0x1c>;
418 atmel,adc-trigger-register = <0x04>;
419
420 trigger@0 {
421 trigger-name = "timer-counter-0";
422 trigger-value = <0x1>;
423 };
424 trigger@1 {
425 trigger-name = "timer-counter-1";
426 trigger-value = <0x3>;
427 };
428
429 trigger@2 {
430 trigger-name = "timer-counter-2";
431 trigger-value = <0x5>;
432 };
433
434 trigger@3 {
435 trigger-name = "external";
436 trigger-value = <0x13>;
437 trigger-external;
438 };
439 };
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800440 };
441
442 nand0: nand@40000000 {
443 compatible = "atmel,at91rm9200-nand";
444 #address-cells = <1>;
445 #size-cells = <1>;
446 reg = <0x40000000 0x10000000
447 0xffffe800 0x200
448 >;
449 atmel,nand-addr-offset = <21>;
450 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800451 pinctrl-names = "default";
452 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800453 gpios = <&pioC 13 0
454 &pioC 14 0
455 0
456 >;
457 status = "disabled";
458 };
459
460 usb0: ohci@00500000 {
461 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
462 reg = <0x00500000 0x100000>;
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +0200463 interrupts = <20 4 2>;
Jean-Christophe PLAGNIOL-VILLARD5b6089c2012-04-09 19:26:33 +0800464 status = "disabled";
465 };
466 };
467
468 i2c@0 {
469 compatible = "i2c-gpio";
470 gpios = <&pioA 23 0 /* sda */
471 &pioA 24 0 /* scl */
472 >;
473 i2c-gpio,sda-open-drain;
474 i2c-gpio,scl-open-drain;
475 i2c-gpio,delay-us = <2>; /* ~100 kHz */
476 #address-cells = <1>;
477 #size-cells = <0>;
478 status = "disabled";
479 };
480};