blob: 4259f3fb899db66523f7837fa9c00f5099ef7219 [file] [log] [blame]
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001/*
2 * Copyright (C) 2003 - 2006 NetXen, Inc.
3 * All rights reserved.
Amit S. Kale80922fb2006-12-04 09:18:00 -08004 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -04005 * This program is free software; you can redistribute it and/or
6 * modify it under the terms of the GNU General Public License
7 * as published by the Free Software Foundation; either version 2
8 * of the License, or (at your option) any later version.
Amit S. Kalecb8011a2006-11-29 09:00:10 -08009 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -040010 * This program is distributed in the hope that it will be useful, but
11 * WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
Amit S. Kalecb8011a2006-11-29 09:00:10 -080014 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -040015 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place - Suite 330, Boston,
18 * MA 02111-1307, USA.
Amit S. Kale80922fb2006-12-04 09:18:00 -080019 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -040020 * The full GNU General Public License is included in this distribution
21 * in the file called LICENSE.
Amit S. Kale80922fb2006-12-04 09:18:00 -080022 *
Amit S. Kale3d396eb2006-10-21 15:33:03 -040023 * Contact Information:
24 * info@netxen.com
25 * NetXen,
26 * 3965 Freedom Circle, Fourth floor,
27 * Santa Clara, CA 95054
28 *
29 *
30 * Source file for NIC routines to access the Phantom hardware
31 *
32 */
33
34#include "netxen_nic.h"
35#include "netxen_nic_hw.h"
36#include "netxen_nic_phan_reg.h"
37
Mithlesh Thukral3176ff32007-04-20 07:52:37 -070038
Arnaldo Carvalho de Meloc9bdd4b2007-03-12 20:09:15 -030039#include <net/ip.h>
40
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -070041#define MASK(n) ((1ULL<<(n))-1)
42#define MN_WIN(addr) (((addr & 0x1fc0000) >> 1) | ((addr >> 25) & 0x3ff))
43#define OCM_WIN(addr) (((addr & 0x1ff0000) >> 1) | ((addr >> 25) & 0x3ff))
44#define MS_WIN(addr) (addr & 0x0ffc0000)
45
46#define GET_MEM_OFFS_2M(addr) (addr & MASK(18))
47
48#define CRB_BLK(off) ((off >> 20) & 0x3f)
49#define CRB_SUBBLK(off) ((off >> 16) & 0xf)
50#define CRB_WINDOW_2M (0x130060)
51#define CRB_HI(off) ((crb_hub_agt[CRB_BLK(off)] << 20) | ((off) & 0xf0000))
52#define CRB_INDIRECT_2M (0x1e0000UL)
53
54#define CRB_WIN_LOCK_TIMEOUT 100000000
55static crb_128M_2M_block_map_t crb_128M_2M_map[64] = {
56 {{{0, 0, 0, 0} } }, /* 0: PCI */
57 {{{1, 0x0100000, 0x0102000, 0x120000}, /* 1: PCIE */
58 {1, 0x0110000, 0x0120000, 0x130000},
59 {1, 0x0120000, 0x0122000, 0x124000},
60 {1, 0x0130000, 0x0132000, 0x126000},
61 {1, 0x0140000, 0x0142000, 0x128000},
62 {1, 0x0150000, 0x0152000, 0x12a000},
63 {1, 0x0160000, 0x0170000, 0x110000},
64 {1, 0x0170000, 0x0172000, 0x12e000},
65 {0, 0x0000000, 0x0000000, 0x000000},
66 {0, 0x0000000, 0x0000000, 0x000000},
67 {0, 0x0000000, 0x0000000, 0x000000},
68 {0, 0x0000000, 0x0000000, 0x000000},
69 {0, 0x0000000, 0x0000000, 0x000000},
70 {0, 0x0000000, 0x0000000, 0x000000},
71 {1, 0x01e0000, 0x01e0800, 0x122000},
72 {0, 0x0000000, 0x0000000, 0x000000} } },
73 {{{1, 0x0200000, 0x0210000, 0x180000} } },/* 2: MN */
74 {{{0, 0, 0, 0} } }, /* 3: */
75 {{{1, 0x0400000, 0x0401000, 0x169000} } },/* 4: P2NR1 */
76 {{{1, 0x0500000, 0x0510000, 0x140000} } },/* 5: SRE */
77 {{{1, 0x0600000, 0x0610000, 0x1c0000} } },/* 6: NIU */
78 {{{1, 0x0700000, 0x0704000, 0x1b8000} } },/* 7: QM */
79 {{{1, 0x0800000, 0x0802000, 0x170000}, /* 8: SQM0 */
80 {0, 0x0000000, 0x0000000, 0x000000},
81 {0, 0x0000000, 0x0000000, 0x000000},
82 {0, 0x0000000, 0x0000000, 0x000000},
83 {0, 0x0000000, 0x0000000, 0x000000},
84 {0, 0x0000000, 0x0000000, 0x000000},
85 {0, 0x0000000, 0x0000000, 0x000000},
86 {0, 0x0000000, 0x0000000, 0x000000},
87 {0, 0x0000000, 0x0000000, 0x000000},
88 {0, 0x0000000, 0x0000000, 0x000000},
89 {0, 0x0000000, 0x0000000, 0x000000},
90 {0, 0x0000000, 0x0000000, 0x000000},
91 {0, 0x0000000, 0x0000000, 0x000000},
92 {0, 0x0000000, 0x0000000, 0x000000},
93 {0, 0x0000000, 0x0000000, 0x000000},
94 {1, 0x08f0000, 0x08f2000, 0x172000} } },
95 {{{1, 0x0900000, 0x0902000, 0x174000}, /* 9: SQM1*/
96 {0, 0x0000000, 0x0000000, 0x000000},
97 {0, 0x0000000, 0x0000000, 0x000000},
98 {0, 0x0000000, 0x0000000, 0x000000},
99 {0, 0x0000000, 0x0000000, 0x000000},
100 {0, 0x0000000, 0x0000000, 0x000000},
101 {0, 0x0000000, 0x0000000, 0x000000},
102 {0, 0x0000000, 0x0000000, 0x000000},
103 {0, 0x0000000, 0x0000000, 0x000000},
104 {0, 0x0000000, 0x0000000, 0x000000},
105 {0, 0x0000000, 0x0000000, 0x000000},
106 {0, 0x0000000, 0x0000000, 0x000000},
107 {0, 0x0000000, 0x0000000, 0x000000},
108 {0, 0x0000000, 0x0000000, 0x000000},
109 {0, 0x0000000, 0x0000000, 0x000000},
110 {1, 0x09f0000, 0x09f2000, 0x176000} } },
111 {{{0, 0x0a00000, 0x0a02000, 0x178000}, /* 10: SQM2*/
112 {0, 0x0000000, 0x0000000, 0x000000},
113 {0, 0x0000000, 0x0000000, 0x000000},
114 {0, 0x0000000, 0x0000000, 0x000000},
115 {0, 0x0000000, 0x0000000, 0x000000},
116 {0, 0x0000000, 0x0000000, 0x000000},
117 {0, 0x0000000, 0x0000000, 0x000000},
118 {0, 0x0000000, 0x0000000, 0x000000},
119 {0, 0x0000000, 0x0000000, 0x000000},
120 {0, 0x0000000, 0x0000000, 0x000000},
121 {0, 0x0000000, 0x0000000, 0x000000},
122 {0, 0x0000000, 0x0000000, 0x000000},
123 {0, 0x0000000, 0x0000000, 0x000000},
124 {0, 0x0000000, 0x0000000, 0x000000},
125 {0, 0x0000000, 0x0000000, 0x000000},
126 {1, 0x0af0000, 0x0af2000, 0x17a000} } },
127 {{{0, 0x0b00000, 0x0b02000, 0x17c000}, /* 11: SQM3*/
128 {0, 0x0000000, 0x0000000, 0x000000},
129 {0, 0x0000000, 0x0000000, 0x000000},
130 {0, 0x0000000, 0x0000000, 0x000000},
131 {0, 0x0000000, 0x0000000, 0x000000},
132 {0, 0x0000000, 0x0000000, 0x000000},
133 {0, 0x0000000, 0x0000000, 0x000000},
134 {0, 0x0000000, 0x0000000, 0x000000},
135 {0, 0x0000000, 0x0000000, 0x000000},
136 {0, 0x0000000, 0x0000000, 0x000000},
137 {0, 0x0000000, 0x0000000, 0x000000},
138 {0, 0x0000000, 0x0000000, 0x000000},
139 {0, 0x0000000, 0x0000000, 0x000000},
140 {0, 0x0000000, 0x0000000, 0x000000},
141 {0, 0x0000000, 0x0000000, 0x000000},
142 {1, 0x0bf0000, 0x0bf2000, 0x17e000} } },
143 {{{1, 0x0c00000, 0x0c04000, 0x1d4000} } },/* 12: I2Q */
144 {{{1, 0x0d00000, 0x0d04000, 0x1a4000} } },/* 13: TMR */
145 {{{1, 0x0e00000, 0x0e04000, 0x1a0000} } },/* 14: ROMUSB */
146 {{{1, 0x0f00000, 0x0f01000, 0x164000} } },/* 15: PEG4 */
147 {{{0, 0x1000000, 0x1004000, 0x1a8000} } },/* 16: XDMA */
148 {{{1, 0x1100000, 0x1101000, 0x160000} } },/* 17: PEG0 */
149 {{{1, 0x1200000, 0x1201000, 0x161000} } },/* 18: PEG1 */
150 {{{1, 0x1300000, 0x1301000, 0x162000} } },/* 19: PEG2 */
151 {{{1, 0x1400000, 0x1401000, 0x163000} } },/* 20: PEG3 */
152 {{{1, 0x1500000, 0x1501000, 0x165000} } },/* 21: P2ND */
153 {{{1, 0x1600000, 0x1601000, 0x166000} } },/* 22: P2NI */
154 {{{0, 0, 0, 0} } }, /* 23: */
155 {{{0, 0, 0, 0} } }, /* 24: */
156 {{{0, 0, 0, 0} } }, /* 25: */
157 {{{0, 0, 0, 0} } }, /* 26: */
158 {{{0, 0, 0, 0} } }, /* 27: */
159 {{{0, 0, 0, 0} } }, /* 28: */
160 {{{1, 0x1d00000, 0x1d10000, 0x190000} } },/* 29: MS */
161 {{{1, 0x1e00000, 0x1e01000, 0x16a000} } },/* 30: P2NR2 */
162 {{{1, 0x1f00000, 0x1f10000, 0x150000} } },/* 31: EPG */
163 {{{0} } }, /* 32: PCI */
164 {{{1, 0x2100000, 0x2102000, 0x120000}, /* 33: PCIE */
165 {1, 0x2110000, 0x2120000, 0x130000},
166 {1, 0x2120000, 0x2122000, 0x124000},
167 {1, 0x2130000, 0x2132000, 0x126000},
168 {1, 0x2140000, 0x2142000, 0x128000},
169 {1, 0x2150000, 0x2152000, 0x12a000},
170 {1, 0x2160000, 0x2170000, 0x110000},
171 {1, 0x2170000, 0x2172000, 0x12e000},
172 {0, 0x0000000, 0x0000000, 0x000000},
173 {0, 0x0000000, 0x0000000, 0x000000},
174 {0, 0x0000000, 0x0000000, 0x000000},
175 {0, 0x0000000, 0x0000000, 0x000000},
176 {0, 0x0000000, 0x0000000, 0x000000},
177 {0, 0x0000000, 0x0000000, 0x000000},
178 {0, 0x0000000, 0x0000000, 0x000000},
179 {0, 0x0000000, 0x0000000, 0x000000} } },
180 {{{1, 0x2200000, 0x2204000, 0x1b0000} } },/* 34: CAM */
181 {{{0} } }, /* 35: */
182 {{{0} } }, /* 36: */
183 {{{0} } }, /* 37: */
184 {{{0} } }, /* 38: */
185 {{{0} } }, /* 39: */
186 {{{1, 0x2800000, 0x2804000, 0x1a4000} } },/* 40: TMR */
187 {{{1, 0x2900000, 0x2901000, 0x16b000} } },/* 41: P2NR3 */
188 {{{1, 0x2a00000, 0x2a00400, 0x1ac400} } },/* 42: RPMX1 */
189 {{{1, 0x2b00000, 0x2b00400, 0x1ac800} } },/* 43: RPMX2 */
190 {{{1, 0x2c00000, 0x2c00400, 0x1acc00} } },/* 44: RPMX3 */
191 {{{1, 0x2d00000, 0x2d00400, 0x1ad000} } },/* 45: RPMX4 */
192 {{{1, 0x2e00000, 0x2e00400, 0x1ad400} } },/* 46: RPMX5 */
193 {{{1, 0x2f00000, 0x2f00400, 0x1ad800} } },/* 47: RPMX6 */
194 {{{1, 0x3000000, 0x3000400, 0x1adc00} } },/* 48: RPMX7 */
195 {{{0, 0x3100000, 0x3104000, 0x1a8000} } },/* 49: XDMA */
196 {{{1, 0x3200000, 0x3204000, 0x1d4000} } },/* 50: I2Q */
197 {{{1, 0x3300000, 0x3304000, 0x1a0000} } },/* 51: ROMUSB */
198 {{{0} } }, /* 52: */
199 {{{1, 0x3500000, 0x3500400, 0x1ac000} } },/* 53: RPMX0 */
200 {{{1, 0x3600000, 0x3600400, 0x1ae000} } },/* 54: RPMX8 */
201 {{{1, 0x3700000, 0x3700400, 0x1ae400} } },/* 55: RPMX9 */
202 {{{1, 0x3800000, 0x3804000, 0x1d0000} } },/* 56: OCM0 */
203 {{{1, 0x3900000, 0x3904000, 0x1b4000} } },/* 57: CRYPTO */
204 {{{1, 0x3a00000, 0x3a04000, 0x1d8000} } },/* 58: SMB */
205 {{{0} } }, /* 59: I2C0 */
206 {{{0} } }, /* 60: I2C1 */
207 {{{1, 0x3d00000, 0x3d04000, 0x1d8000} } },/* 61: LPC */
208 {{{1, 0x3e00000, 0x3e01000, 0x167000} } },/* 62: P2NC */
209 {{{1, 0x3f00000, 0x3f01000, 0x168000} } } /* 63: P2NR0 */
210};
211
212/*
213 * top 12 bits of crb internal address (hub, agent)
214 */
215static unsigned crb_hub_agt[64] =
216{
217 0,
218 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
219 NETXEN_HW_CRB_HUB_AGT_ADR_MN,
220 NETXEN_HW_CRB_HUB_AGT_ADR_MS,
221 0,
222 NETXEN_HW_CRB_HUB_AGT_ADR_SRE,
223 NETXEN_HW_CRB_HUB_AGT_ADR_NIU,
224 NETXEN_HW_CRB_HUB_AGT_ADR_QMN,
225 NETXEN_HW_CRB_HUB_AGT_ADR_SQN0,
226 NETXEN_HW_CRB_HUB_AGT_ADR_SQN1,
227 NETXEN_HW_CRB_HUB_AGT_ADR_SQN2,
228 NETXEN_HW_CRB_HUB_AGT_ADR_SQN3,
229 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
230 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
231 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
232 NETXEN_HW_CRB_HUB_AGT_ADR_PGN4,
233 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
234 NETXEN_HW_CRB_HUB_AGT_ADR_PGN0,
235 NETXEN_HW_CRB_HUB_AGT_ADR_PGN1,
236 NETXEN_HW_CRB_HUB_AGT_ADR_PGN2,
237 NETXEN_HW_CRB_HUB_AGT_ADR_PGN3,
238 NETXEN_HW_CRB_HUB_AGT_ADR_PGND,
239 NETXEN_HW_CRB_HUB_AGT_ADR_PGNI,
240 NETXEN_HW_CRB_HUB_AGT_ADR_PGS0,
241 NETXEN_HW_CRB_HUB_AGT_ADR_PGS1,
242 NETXEN_HW_CRB_HUB_AGT_ADR_PGS2,
243 NETXEN_HW_CRB_HUB_AGT_ADR_PGS3,
244 0,
245 NETXEN_HW_CRB_HUB_AGT_ADR_PGSI,
246 NETXEN_HW_CRB_HUB_AGT_ADR_SN,
247 0,
248 NETXEN_HW_CRB_HUB_AGT_ADR_EG,
249 0,
250 NETXEN_HW_CRB_HUB_AGT_ADR_PS,
251 NETXEN_HW_CRB_HUB_AGT_ADR_CAM,
252 0,
253 0,
254 0,
255 0,
256 0,
257 NETXEN_HW_CRB_HUB_AGT_ADR_TIMR,
258 0,
259 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX1,
260 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX2,
261 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX3,
262 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX4,
263 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX5,
264 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX6,
265 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX7,
266 NETXEN_HW_CRB_HUB_AGT_ADR_XDMA,
267 NETXEN_HW_CRB_HUB_AGT_ADR_I2Q,
268 NETXEN_HW_CRB_HUB_AGT_ADR_ROMUSB,
269 0,
270 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX0,
271 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX8,
272 NETXEN_HW_CRB_HUB_AGT_ADR_RPMX9,
273 NETXEN_HW_CRB_HUB_AGT_ADR_OCM0,
274 0,
275 NETXEN_HW_CRB_HUB_AGT_ADR_SMB,
276 NETXEN_HW_CRB_HUB_AGT_ADR_I2C0,
277 NETXEN_HW_CRB_HUB_AGT_ADR_I2C1,
278 0,
279 NETXEN_HW_CRB_HUB_AGT_ADR_PGNC,
280 0,
281};
282
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400283/* PCI Windowing for DDR regions. */
284
285#define ADDR_IN_RANGE(addr, low, high) \
286 (((addr) <= (high)) && ((addr) >= (low)))
287
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700288#define NETXEN_WINDOW_ONE 0x2000000 /*CRB Window: bit 25 of CRB address */
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400289
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800290#define NETXEN_NIC_ZERO_PAUSE_ADDR 0ULL
291#define NETXEN_NIC_UNIT_PAUSE_ADDR 0x200ULL
292#define NETXEN_NIC_EPG_PAUSE_ADDR1 0x2200010000c28001ULL
293#define NETXEN_NIC_EPG_PAUSE_ADDR2 0x0100088866554433ULL
294
295#define NETXEN_NIC_WINDOW_MARGIN 0x100000
296
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400297int netxen_nic_set_mac(struct net_device *netdev, void *p)
298{
Mithlesh Thukral3176ff32007-04-20 07:52:37 -0700299 struct netxen_adapter *adapter = netdev_priv(netdev);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400300 struct sockaddr *addr = p;
301
302 if (netif_running(netdev))
303 return -EBUSY;
304
305 if (!is_valid_ether_addr(addr->sa_data))
306 return -EADDRNOTAVAIL;
307
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400308 memcpy(netdev->dev_addr, addr->sa_data, netdev->addr_len);
309
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700310 /* For P3, MAC addr is not set in NIU */
311 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
312 if (adapter->macaddr_set)
313 adapter->macaddr_set(adapter, addr->sa_data);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400314
315 return 0;
316}
317
Dhananjay Phadke623621b2008-07-21 19:44:01 -0700318#define NETXEN_UNICAST_ADDR(port, index) \
319 (NETXEN_UNICAST_ADDR_BASE+(port*32)+(index*8))
320#define NETXEN_MCAST_ADDR(port, index) \
321 (NETXEN_MULTICAST_ADDR_BASE+(port*0x80)+(index*8))
322#define MAC_HI(addr) \
323 ((addr[2] << 16) | (addr[1] << 8) | (addr[0]))
324#define MAC_LO(addr) \
325 ((addr[5] << 16) | (addr[4] << 8) | (addr[3]))
326
327static int
328netxen_nic_enable_mcast_filter(struct netxen_adapter *adapter)
329{
330 u32 val = 0;
331 u16 port = adapter->physical_port;
332 u8 *addr = adapter->netdev->dev_addr;
333
334 if (adapter->mc_enabled)
335 return 0;
336
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700337 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
Dhananjay Phadke623621b2008-07-21 19:44:01 -0700338 val |= (1UL << (28+port));
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700339 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
Dhananjay Phadke623621b2008-07-21 19:44:01 -0700340
341 /* add broadcast addr to filter */
342 val = 0xffffff;
343 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
344 netxen_crb_writelit_adapter(adapter,
345 NETXEN_UNICAST_ADDR(port, 0)+4, val);
346
347 /* add station addr to filter */
348 val = MAC_HI(addr);
349 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), val);
350 val = MAC_LO(addr);
351 netxen_crb_writelit_adapter(adapter,
352 NETXEN_UNICAST_ADDR(port, 1)+4, val);
353
354 adapter->mc_enabled = 1;
355 return 0;
356}
357
358static int
359netxen_nic_disable_mcast_filter(struct netxen_adapter *adapter)
360{
361 u32 val = 0;
362 u16 port = adapter->physical_port;
363 u8 *addr = adapter->netdev->dev_addr;
364
365 if (!adapter->mc_enabled)
366 return 0;
367
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700368 adapter->hw_read_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
Dhananjay Phadke623621b2008-07-21 19:44:01 -0700369 val &= ~(1UL << (28+port));
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700370 adapter->hw_write_wx(adapter, NETXEN_MAC_ADDR_CNTL_REG, &val, 4);
Dhananjay Phadke623621b2008-07-21 19:44:01 -0700371
372 val = MAC_HI(addr);
373 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 0), val);
374 val = MAC_LO(addr);
375 netxen_crb_writelit_adapter(adapter,
376 NETXEN_UNICAST_ADDR(port, 0)+4, val);
377
378 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1), 0);
379 netxen_crb_writelit_adapter(adapter, NETXEN_UNICAST_ADDR(port, 1)+4, 0);
380
381 adapter->mc_enabled = 0;
382 return 0;
383}
384
385static int
386netxen_nic_set_mcast_addr(struct netxen_adapter *adapter,
387 int index, u8 *addr)
388{
389 u32 hi = 0, lo = 0;
390 u16 port = adapter->physical_port;
391
392 lo = MAC_LO(addr);
393 hi = MAC_HI(addr);
394
395 netxen_crb_writelit_adapter(adapter,
396 NETXEN_MCAST_ADDR(port, index), hi);
397 netxen_crb_writelit_adapter(adapter,
398 NETXEN_MCAST_ADDR(port, index)+4, lo);
399
400 return 0;
401}
402
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700403void netxen_p2_nic_set_multi(struct net_device *netdev)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400404{
Mithlesh Thukral3176ff32007-04-20 07:52:37 -0700405 struct netxen_adapter *adapter = netdev_priv(netdev);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400406 struct dev_mc_list *mc_ptr;
Dhananjay Phadke623621b2008-07-21 19:44:01 -0700407 u8 null_addr[6];
408 int index = 0;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400409
Dhananjay Phadke623621b2008-07-21 19:44:01 -0700410 memset(null_addr, 0, 6);
411
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400412 if (netdev->flags & IFF_PROMISC) {
Dhananjay Phadke623621b2008-07-21 19:44:01 -0700413
414 adapter->set_promisc(adapter,
415 NETXEN_NIU_PROMISC_MODE);
416
417 /* Full promiscuous mode */
418 netxen_nic_disable_mcast_filter(adapter);
419
420 return;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400421 }
Dhananjay Phadke623621b2008-07-21 19:44:01 -0700422
423 if (netdev->mc_count == 0) {
424 adapter->set_promisc(adapter,
425 NETXEN_NIU_NON_PROMISC_MODE);
426 netxen_nic_disable_mcast_filter(adapter);
427 return;
428 }
429
430 adapter->set_promisc(adapter, NETXEN_NIU_ALLMULTI_MODE);
431 if (netdev->flags & IFF_ALLMULTI ||
432 netdev->mc_count > adapter->max_mc_count) {
433 netxen_nic_disable_mcast_filter(adapter);
434 return;
435 }
436
437 netxen_nic_enable_mcast_filter(adapter);
438
439 for (mc_ptr = netdev->mc_list; mc_ptr; mc_ptr = mc_ptr->next, index++)
440 netxen_nic_set_mcast_addr(adapter, index, mc_ptr->dmi_addr);
441
442 if (index != netdev->mc_count)
443 printk(KERN_WARNING "%s: %s multicast address count mismatch\n",
444 netxen_nic_driver_name, netdev->name);
445
446 /* Clear out remaining addresses */
447 for (; index < adapter->max_mc_count; index++)
448 netxen_nic_set_mcast_addr(adapter, index, null_addr);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400449}
450
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700451static int nx_p3_nic_add_mac(struct netxen_adapter *adapter,
452 u8 *addr, nx_mac_list_t **add_list, nx_mac_list_t **del_list)
453{
454 nx_mac_list_t *cur, *prev;
455
456 /* if in del_list, move it to adapter->mac_list */
457 for (cur = *del_list, prev = NULL; cur;) {
458 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0) {
459 if (prev == NULL)
460 *del_list = cur->next;
461 else
462 prev->next = cur->next;
463 cur->next = adapter->mac_list;
464 adapter->mac_list = cur;
465 return 0;
466 }
467 prev = cur;
468 cur = cur->next;
469 }
470
471 /* make sure to add each mac address only once */
472 for (cur = adapter->mac_list; cur; cur = cur->next) {
473 if (memcmp(addr, cur->mac_addr, ETH_ALEN) == 0)
474 return 0;
475 }
476 /* not in del_list, create new entry and add to add_list */
477 cur = kmalloc(sizeof(*cur), in_atomic()? GFP_ATOMIC : GFP_KERNEL);
478 if (cur == NULL) {
479 printk(KERN_ERR "%s: cannot allocate memory. MAC filtering may"
480 "not work properly from now.\n", __func__);
481 return -1;
482 }
483
484 memcpy(cur->mac_addr, addr, ETH_ALEN);
485 cur->next = *add_list;
486 *add_list = cur;
487 return 0;
488}
489
490static int
491netxen_send_cmd_descs(struct netxen_adapter *adapter,
492 struct cmd_desc_type0 *cmd_desc_arr, int nr_elements)
493{
494 uint32_t i, producer;
495 struct netxen_cmd_buffer *pbuf;
496 struct cmd_desc_type0 *cmd_desc;
497
498 if (nr_elements > MAX_PENDING_DESC_BLOCK_SIZE || nr_elements == 0) {
499 printk(KERN_WARNING "%s: Too many command descriptors in a "
500 "request\n", __func__);
501 return -EINVAL;
502 }
503
504 i = 0;
505
506 producer = adapter->cmd_producer;
507 do {
508 cmd_desc = &cmd_desc_arr[i];
509
510 pbuf = &adapter->cmd_buf_arr[producer];
511 pbuf->mss = 0;
512 pbuf->total_length = 0;
513 pbuf->skb = NULL;
514 pbuf->cmd = 0;
515 pbuf->frag_count = 0;
516 pbuf->port = 0;
517
518 /* adapter->ahw.cmd_desc_head[producer] = *cmd_desc; */
519 memcpy(&adapter->ahw.cmd_desc_head[producer],
520 &cmd_desc_arr[i], sizeof(struct cmd_desc_type0));
521
522 producer = get_next_index(producer,
523 adapter->max_tx_desc_count);
524 i++;
525
526 } while (i != nr_elements);
527
528 adapter->cmd_producer = producer;
529
530 /* write producer index to start the xmit */
531
532 netxen_nic_update_cmd_producer(adapter, adapter->cmd_producer);
533
534 return 0;
535}
536
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700537static int nx_p3_sre_macaddr_change(struct net_device *dev,
538 u8 *addr, unsigned op)
539{
540 struct netxen_adapter *adapter = (struct netxen_adapter *)dev->priv;
541 nx_nic_req_t req;
542 nx_mac_req_t mac_req;
543 int rv;
544
545 memset(&req, 0, sizeof(nx_nic_req_t));
Dhananjay Phadke9ad27642008-08-01 03:14:59 -0700546 req.qhdr |= (NX_NIC_REQUEST << 23);
547 req.req_hdr |= NX_MAC_EVENT;
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700548 req.req_hdr |= ((u64)adapter->portnum << 16);
549 mac_req.op = op;
550 memcpy(&mac_req.mac_addr, addr, 6);
551 req.words[0] = cpu_to_le64(*(u64 *)&mac_req);
552
553 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
554 if (rv != 0) {
555 printk(KERN_ERR "ERROR. Could not send mac update\n");
556 return rv;
557 }
558
559 return 0;
560}
561
562void netxen_p3_nic_set_multi(struct net_device *netdev)
563{
564 struct netxen_adapter *adapter = netdev_priv(netdev);
565 nx_mac_list_t *cur, *next, *del_list, *add_list = NULL;
566 struct dev_mc_list *mc_ptr;
567 u8 bcast_addr[ETH_ALEN] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff };
Dhananjay Phadke9ad27642008-08-01 03:14:59 -0700568 u32 mode = VPORT_MISS_MODE_DROP;
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700569
570 del_list = adapter->mac_list;
571 adapter->mac_list = NULL;
572
573 nx_p3_nic_add_mac(adapter, netdev->dev_addr, &add_list, &del_list);
Dhananjay Phadke9ad27642008-08-01 03:14:59 -0700574 nx_p3_nic_add_mac(adapter, bcast_addr, &add_list, &del_list);
575
576 if (netdev->flags & IFF_PROMISC) {
577 mode = VPORT_MISS_MODE_ACCEPT_ALL;
578 goto send_fw_cmd;
579 }
580
581 if ((netdev->flags & IFF_ALLMULTI) ||
582 (netdev->mc_count > adapter->max_mc_count)) {
583 mode = VPORT_MISS_MODE_ACCEPT_MULTI;
584 goto send_fw_cmd;
585 }
586
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700587 if (netdev->mc_count > 0) {
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700588 for (mc_ptr = netdev->mc_list; mc_ptr;
589 mc_ptr = mc_ptr->next) {
590 nx_p3_nic_add_mac(adapter, mc_ptr->dmi_addr,
591 &add_list, &del_list);
592 }
593 }
Dhananjay Phadke9ad27642008-08-01 03:14:59 -0700594
595send_fw_cmd:
596 adapter->set_promisc(adapter, mode);
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700597 for (cur = del_list; cur;) {
598 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_DEL);
599 next = cur->next;
600 kfree(cur);
601 cur = next;
602 }
603 for (cur = add_list; cur;) {
604 nx_p3_sre_macaddr_change(netdev, cur->mac_addr, NETXEN_MAC_ADD);
605 next = cur->next;
606 cur->next = adapter->mac_list;
607 adapter->mac_list = cur;
608 cur = next;
609 }
610}
611
Dhananjay Phadke9ad27642008-08-01 03:14:59 -0700612int netxen_p3_nic_set_promisc(struct netxen_adapter *adapter, u32 mode)
613{
614 nx_nic_req_t req;
615
616 memset(&req, 0, sizeof(nx_nic_req_t));
617
618 req.qhdr |= (NX_HOST_REQUEST << 23);
619 req.req_hdr |= NX_NIC_H2C_OPCODE_PROXY_SET_VPORT_MISS_MODE;
620 req.req_hdr |= ((u64)adapter->portnum << 16);
621 req.words[0] = cpu_to_le64(mode);
622
623 return netxen_send_cmd_descs(adapter,
624 (struct cmd_desc_type0 *)&req, 1);
625}
626
Dhananjay Phadkecd1f8162008-07-21 19:44:09 -0700627#define NETXEN_CONFIG_INTR_COALESCE 3
628
629/*
630 * Send the interrupt coalescing parameter set by ethtool to the card.
631 */
632int netxen_config_intr_coalesce(struct netxen_adapter *adapter)
633{
634 nx_nic_req_t req;
635 int rv;
636
637 memset(&req, 0, sizeof(nx_nic_req_t));
638
Dhananjay Phadke9ad27642008-08-01 03:14:59 -0700639 req.qhdr |= (NX_NIC_REQUEST << 23);
Dhananjay Phadkecd1f8162008-07-21 19:44:09 -0700640 req.req_hdr |= NETXEN_CONFIG_INTR_COALESCE;
641 req.req_hdr |= ((u64)adapter->portnum << 16);
642
643 memcpy(&req.words[0], &adapter->coal, sizeof(adapter->coal));
644
645 rv = netxen_send_cmd_descs(adapter, (struct cmd_desc_type0 *)&req, 1);
646 if (rv != 0) {
647 printk(KERN_ERR "ERROR. Could not send "
648 "interrupt coalescing parameters\n");
649 }
650
651 return rv;
652}
653
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400654/*
655 * netxen_nic_change_mtu - Change the Maximum Transfer Unit
656 * @returns 0 on success, negative on failure
657 */
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700658
659#define MTU_FUDGE_FACTOR 100
660
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400661int netxen_nic_change_mtu(struct net_device *netdev, int mtu)
662{
Mithlesh Thukral3176ff32007-04-20 07:52:37 -0700663 struct netxen_adapter *adapter = netdev_priv(netdev);
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700664 int max_mtu;
Dhananjay Phadke9ad27642008-08-01 03:14:59 -0700665 int rc = 0;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400666
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700667 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
668 max_mtu = P3_MAX_MTU;
669 else
670 max_mtu = P2_MAX_MTU;
671
672 if (mtu > max_mtu) {
673 printk(KERN_ERR "%s: mtu > %d bytes unsupported\n",
674 netdev->name, max_mtu);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400675 return -EINVAL;
676 }
677
Amit S. Kale80922fb2006-12-04 09:18:00 -0800678 if (adapter->set_mtu)
Dhananjay Phadke9ad27642008-08-01 03:14:59 -0700679 rc = adapter->set_mtu(adapter, mtu);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400680
Dhananjay Phadke9ad27642008-08-01 03:14:59 -0700681 if (!rc)
682 netdev->mtu = mtu;
Dhananjay Phadkec9fc8912008-07-21 19:44:07 -0700683
Dhananjay Phadke9ad27642008-08-01 03:14:59 -0700684 return rc;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400685}
686
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400687int netxen_is_flash_supported(struct netxen_adapter *adapter)
688{
689 const int locs[] = { 0, 0x4, 0x100, 0x4000, 0x4128 };
690 int addr, val01, val02, i, j;
691
692 /* if the flash size less than 4Mb, make huge war cry and die */
693 for (j = 1; j < 4; j++) {
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800694 addr = j * NETXEN_NIC_WINDOW_MARGIN;
Denis Chengff8ac602007-09-02 18:30:18 +0800695 for (i = 0; i < ARRAY_SIZE(locs); i++) {
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400696 if (netxen_rom_fast_read(adapter, locs[i], &val01) == 0
697 && netxen_rom_fast_read(adapter, (addr + locs[i]),
698 &val02) == 0) {
699 if (val01 == val02)
700 return -1;
701 } else
702 return -1;
703 }
704 }
705
706 return 0;
707}
708
709static int netxen_get_flash_block(struct netxen_adapter *adapter, int base,
Al Virof305f782007-12-22 19:44:00 +0000710 int size, __le32 * buf)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400711{
712 int i, addr;
Al Virof305f782007-12-22 19:44:00 +0000713 __le32 *ptr32;
714 u32 v;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400715
716 addr = base;
717 ptr32 = buf;
718 for (i = 0; i < size / sizeof(u32); i++) {
Al Virof305f782007-12-22 19:44:00 +0000719 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400720 return -1;
Al Virof305f782007-12-22 19:44:00 +0000721 *ptr32 = cpu_to_le32(v);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400722 ptr32++;
723 addr += sizeof(u32);
724 }
725 if ((char *)buf + size > (char *)ptr32) {
Al Virof305f782007-12-22 19:44:00 +0000726 __le32 local;
727 if (netxen_rom_fast_read(adapter, addr, &v) == -1)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400728 return -1;
Al Virof305f782007-12-22 19:44:00 +0000729 local = cpu_to_le32(v);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400730 memcpy(ptr32, &local, (char *)buf + size - (char *)ptr32);
731 }
732
733 return 0;
734}
735
Al Virof305f782007-12-22 19:44:00 +0000736int netxen_get_flash_mac_addr(struct netxen_adapter *adapter, __le64 mac[])
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400737{
Al Virof305f782007-12-22 19:44:00 +0000738 __le32 *pmac = (__le32 *) & mac[0];
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400739
740 if (netxen_get_flash_block(adapter,
Mithlesh Thukral0d047612007-06-07 04:36:36 -0700741 NETXEN_USER_START +
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400742 offsetof(struct netxen_new_user_info,
743 mac_addr),
744 FLASH_NUM_PORTS * sizeof(u64), pmac) == -1) {
745 return -1;
746 }
Al Virof305f782007-12-22 19:44:00 +0000747 if (*mac == cpu_to_le64(~0ULL)) {
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400748 if (netxen_get_flash_block(adapter,
Mithlesh Thukral0d047612007-06-07 04:36:36 -0700749 NETXEN_USER_START_OLD +
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400750 offsetof(struct netxen_user_old_info,
751 mac_addr),
752 FLASH_NUM_PORTS * sizeof(u64),
753 pmac) == -1)
754 return -1;
Al Virof305f782007-12-22 19:44:00 +0000755 if (*mac == cpu_to_le64(~0ULL))
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400756 return -1;
757 }
758 return 0;
759}
760
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700761#define CRB_WIN_LOCK_TIMEOUT 100000000
762
763static int crb_win_lock(struct netxen_adapter *adapter)
764{
765 int done = 0, timeout = 0;
766
767 while (!done) {
768 /* acquire semaphore3 from PCI HW block */
769 adapter->hw_read_wx(adapter,
770 NETXEN_PCIE_REG(PCIE_SEM7_LOCK), &done, 4);
771 if (done == 1)
772 break;
773 if (timeout >= CRB_WIN_LOCK_TIMEOUT)
774 return -1;
775 timeout++;
776 udelay(1);
777 }
778 netxen_crb_writelit_adapter(adapter,
779 NETXEN_CRB_WIN_LOCK_ID, adapter->portnum);
780 return 0;
781}
782
783static void crb_win_unlock(struct netxen_adapter *adapter)
784{
785 int val;
786
787 adapter->hw_read_wx(adapter,
788 NETXEN_PCIE_REG(PCIE_SEM7_UNLOCK), &val, 4);
789}
790
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400791/*
792 * Changes the CRB window to the specified window.
793 */
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700794void
795netxen_nic_pci_change_crbwindow_128M(struct netxen_adapter *adapter, u32 wndw)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400796{
797 void __iomem *offset;
798 u32 tmp;
799 int count = 0;
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -0700800 uint8_t func = adapter->ahw.pci_func;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400801
802 if (adapter->curr_window == wndw)
803 return;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400804 /*
805 * Move the CRB window.
806 * We need to write to the "direct access" region of PCI
807 * to avoid a race condition where the window register has
808 * not been successfully written across CRB before the target
809 * register address is received by PCI. The direct region bypasses
810 * the CRB bus.
811 */
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -0700812 offset = PCI_OFFSET_SECOND_RANGE(adapter,
813 NETXEN_PCIX_PH_REG(PCIE_CRB_WINDOW_REG(func)));
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400814
815 if (wndw & 0x1)
816 wndw = NETXEN_WINDOW_ONE;
817
818 writel(wndw, offset);
819
820 /* MUST make sure window is set before we forge on... */
821 while ((tmp = readl(offset)) != wndw) {
822 printk(KERN_WARNING "%s: %s WARNING: CRB window value not "
823 "registered properly: 0x%08x.\n",
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700824 netxen_nic_driver_name, __func__, tmp);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400825 mdelay(1);
826 if (count >= 10)
827 break;
828 count++;
829 }
830
Mithlesh Thukral6c80b182007-04-20 07:55:26 -0700831 if (wndw == NETXEN_WINDOW_ONE)
832 adapter->curr_window = 1;
833 else
834 adapter->curr_window = 0;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400835}
836
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700837/*
838 * Return -1 if off is not valid,
839 * 1 if window access is needed. 'off' is set to offset from
840 * CRB space in 128M pci map
841 * 0 if no window access is needed. 'off' is set to 2M addr
842 * In: 'off' is offset from base in 128M pci map
843 */
844static int
845netxen_nic_pci_get_crb_addr_2M(struct netxen_adapter *adapter,
846 ulong *off, int len)
847{
848 unsigned long end = *off + len;
849 crb_128M_2M_sub_block_map_t *m;
850
851
852 if (*off >= NETXEN_CRB_MAX)
853 return -1;
854
855 if (*off >= NETXEN_PCI_CAMQM && (end <= NETXEN_PCI_CAMQM_2M_END)) {
856 *off = (*off - NETXEN_PCI_CAMQM) + NETXEN_PCI_CAMQM_2M_BASE +
857 (ulong)adapter->ahw.pci_base0;
858 return 0;
859 }
860
861 if (*off < NETXEN_PCI_CRBSPACE)
862 return -1;
863
864 *off -= NETXEN_PCI_CRBSPACE;
865 end = *off + len;
866
867 /*
868 * Try direct map
869 */
870 m = &crb_128M_2M_map[CRB_BLK(*off)].sub_block[CRB_SUBBLK(*off)];
871
872 if (m->valid && (m->start_128M <= *off) && (m->end_128M >= end)) {
873 *off = *off + m->start_2M - m->start_128M +
874 (ulong)adapter->ahw.pci_base0;
875 return 0;
876 }
877
878 /*
879 * Not in direct map, use crb window
880 */
881 return 1;
882}
883
884/*
885 * In: 'off' is offset from CRB space in 128M pci map
886 * Out: 'off' is 2M pci map addr
887 * side effect: lock crb window
888 */
889static void
890netxen_nic_pci_set_crbwindow_2M(struct netxen_adapter *adapter, ulong *off)
891{
892 u32 win_read;
893
894 adapter->crb_win = CRB_HI(*off);
895 writel(adapter->crb_win, (void *)(CRB_WINDOW_2M +
896 adapter->ahw.pci_base0));
897 /*
898 * Read back value to make sure write has gone through before trying
899 * to use it.
900 */
901 win_read = readl((void *)(CRB_WINDOW_2M + adapter->ahw.pci_base0));
902 if (win_read != adapter->crb_win) {
903 printk(KERN_ERR "%s: Written crbwin (0x%x) != "
904 "Read crbwin (0x%x), off=0x%lx\n",
905 __func__, adapter->crb_win, win_read, *off);
906 }
907 *off = (*off & MASK(16)) + CRB_INDIRECT_2M +
908 (ulong)adapter->ahw.pci_base0;
909}
910
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +0530911int netxen_load_firmware(struct netxen_adapter *adapter)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400912{
913 int i;
Linsys Contractor Mithlesh Thukrale0e20a12007-02-28 05:16:40 -0800914 u32 data, size = 0;
Dhananjay Phadke29566402008-07-21 19:44:04 -0700915 u32 flashaddr = NETXEN_BOOTLD_START, memaddr = NETXEN_BOOTLD_START;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400916
Dhananjay Phadke29566402008-07-21 19:44:04 -0700917 size = (NETXEN_IMAGE_START - NETXEN_BOOTLD_START)/4;
918
919 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
920 adapter->pci_write_normalize(adapter,
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700921 NETXEN_ROMUSB_GLB_CAS_RST, 1);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400922
923 for (i = 0; i < size; i++) {
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +0530924 if (netxen_rom_fast_read(adapter, flashaddr, (int *)&data) != 0)
925 return -EIO;
926
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700927 adapter->pci_mem_write(adapter, memaddr, &data, 4);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400928 flashaddr += 4;
929 memaddr += 4;
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700930 cond_resched();
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400931 }
Dhananjay Phadke29566402008-07-21 19:44:04 -0700932 msleep(1);
933
934 if (NX_IS_REVISION_P3(adapter->ahw.revision_id))
935 adapter->pci_write_normalize(adapter,
936 NETXEN_ROMUSB_GLB_SW_RESET, 0x80001d);
937 else {
938 adapter->pci_write_normalize(adapter,
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700939 NETXEN_ROMUSB_GLB_CHIP_CLK_CTRL, 0x3fff);
Dhananjay Phadke29566402008-07-21 19:44:04 -0700940 adapter->pci_write_normalize(adapter,
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700941 NETXEN_ROMUSB_GLB_CAS_RST, 0);
Dhananjay Phadke29566402008-07-21 19:44:04 -0700942 }
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400943
Dhananjay Phadke96acb6e2007-07-02 09:37:57 +0530944 return 0;
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400945}
946
947int
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700948netxen_nic_hw_write_wx_128M(struct netxen_adapter *adapter,
949 ulong off, void *data, int len)
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400950{
951 void __iomem *addr;
952
953 if (ADDR_IN_WINDOW1(off)) {
954 addr = NETXEN_CRB_NORMALIZE(adapter, off);
955 } else { /* Window 0 */
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800956 addr = pci_base_offset(adapter, off);
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700957 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400958 }
959
960 DPRINTK(INFO, "writing to base %lx offset %llx addr %p"
961 " data %llx len %d\n",
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800962 pci_base(adapter, off), off, addr,
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400963 *(unsigned long long *)data, len);
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800964 if (!addr) {
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700965 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
Amit S. Kalecb8011a2006-11-29 09:00:10 -0800966 return 1;
967 }
968
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400969 switch (len) {
970 case 1:
971 writeb(*(u8 *) data, addr);
972 break;
973 case 2:
974 writew(*(u16 *) data, addr);
975 break;
976 case 4:
977 writel(*(u32 *) data, addr);
978 break;
979 case 8:
980 writeq(*(u64 *) data, addr);
981 break;
982 default:
983 DPRINTK(INFO,
984 "writing data %lx to offset %llx, num words=%d\n",
985 *(unsigned long *)data, off, (len >> 3));
986
987 netxen_nic_hw_block_write64((u64 __iomem *) data, addr,
988 (len >> 3));
989 break;
990 }
991 if (!ADDR_IN_WINDOW1(off))
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700992 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
Amit S. Kale3d396eb2006-10-21 15:33:03 -0400993
994 return 0;
995}
996
997int
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -0700998netxen_nic_hw_read_wx_128M(struct netxen_adapter *adapter,
999 ulong off, void *data, int len)
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001000{
1001 void __iomem *addr;
1002
1003 if (ADDR_IN_WINDOW1(off)) { /* Window 1 */
1004 addr = NETXEN_CRB_NORMALIZE(adapter, off);
1005 } else { /* Window 0 */
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001006 addr = pci_base_offset(adapter, off);
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001007 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001008 }
1009
1010 DPRINTK(INFO, "reading from base %lx offset %llx addr %p\n",
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001011 pci_base(adapter, off), off, addr);
1012 if (!addr) {
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001013 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001014 return 1;
1015 }
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001016 switch (len) {
1017 case 1:
1018 *(u8 *) data = readb(addr);
1019 break;
1020 case 2:
1021 *(u16 *) data = readw(addr);
1022 break;
1023 case 4:
1024 *(u32 *) data = readl(addr);
1025 break;
1026 case 8:
1027 *(u64 *) data = readq(addr);
1028 break;
1029 default:
1030 netxen_nic_hw_block_read64((u64 __iomem *) data, addr,
1031 (len >> 3));
1032 break;
1033 }
1034 DPRINTK(INFO, "read %lx\n", *(unsigned long *)data);
1035
1036 if (!ADDR_IN_WINDOW1(off))
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001037 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1038
1039 return 0;
1040}
1041
1042int
1043netxen_nic_hw_write_wx_2M(struct netxen_adapter *adapter,
1044 ulong off, void *data, int len)
1045{
1046 unsigned long flags = 0;
1047 int rv;
1048
1049 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1050
1051 if (rv == -1) {
1052 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1053 __func__, off);
1054 dump_stack();
1055 return -1;
1056 }
1057
1058 if (rv == 1) {
1059 write_lock_irqsave(&adapter->adapter_lock, flags);
1060 crb_win_lock(adapter);
1061 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1062 }
1063
1064 DPRINTK(1, INFO, "write data %lx to offset %llx, len=%d\n",
1065 *(unsigned long *)data, off, len);
1066
1067 switch (len) {
1068 case 1:
1069 writeb(*(uint8_t *)data, (void *)off);
1070 break;
1071 case 2:
1072 writew(*(uint16_t *)data, (void *)off);
1073 break;
1074 case 4:
1075 writel(*(uint32_t *)data, (void *)off);
1076 break;
1077 case 8:
1078 writeq(*(uint64_t *)data, (void *)off);
1079 break;
1080 default:
1081 DPRINTK(1, INFO,
1082 "writing data %lx to offset %llx, num words=%d\n",
1083 *(unsigned long *)data, off, (len>>3));
1084 break;
1085 }
1086 if (rv == 1) {
1087 crb_win_unlock(adapter);
1088 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1089 }
1090
1091 return 0;
1092}
1093
1094int
1095netxen_nic_hw_read_wx_2M(struct netxen_adapter *adapter,
1096 ulong off, void *data, int len)
1097{
1098 unsigned long flags = 0;
1099 int rv;
1100
1101 rv = netxen_nic_pci_get_crb_addr_2M(adapter, &off, len);
1102
1103 if (rv == -1) {
1104 printk(KERN_ERR "%s: invalid offset: 0x%016lx\n",
1105 __func__, off);
1106 dump_stack();
1107 return -1;
1108 }
1109
1110 if (rv == 1) {
1111 write_lock_irqsave(&adapter->adapter_lock, flags);
1112 crb_win_lock(adapter);
1113 netxen_nic_pci_set_crbwindow_2M(adapter, &off);
1114 }
1115
1116 DPRINTK(1, INFO, "read from offset %lx, len=%d\n", off, len);
1117
1118 switch (len) {
1119 case 1:
1120 *(uint8_t *)data = readb((void *)off);
1121 break;
1122 case 2:
1123 *(uint16_t *)data = readw((void *)off);
1124 break;
1125 case 4:
1126 *(uint32_t *)data = readl((void *)off);
1127 break;
1128 case 8:
1129 *(uint64_t *)data = readq((void *)off);
1130 break;
1131 default:
1132 break;
1133 }
1134
1135 DPRINTK(1, INFO, "read %lx\n", *(unsigned long *)data);
1136
1137 if (rv == 1) {
1138 crb_win_unlock(adapter);
1139 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1140 }
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001141
1142 return 0;
1143}
1144
1145void netxen_nic_reg_write(struct netxen_adapter *adapter, u64 off, u32 val)
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001146{
1147 adapter->hw_write_wx(adapter, off, &val, 4);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001148}
1149
1150int netxen_nic_reg_read(struct netxen_adapter *adapter, u64 off)
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001151{
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001152 int val;
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001153 adapter->hw_read_wx(adapter, off, &val, 4);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001154 return val;
1155}
1156
1157/* Change the window to 0, write and change back to window 1. */
1158void netxen_nic_write_w0(struct netxen_adapter *adapter, u32 index, u32 value)
1159{
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001160 adapter->hw_write_wx(adapter, index, &value, 4);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001161}
1162
1163/* Change the window to 0, read and change back to window 1. */
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001164void netxen_nic_read_w0(struct netxen_adapter *adapter, u32 index, u32 *value)
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001165{
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001166 adapter->hw_read_wx(adapter, index, value, 4);
1167}
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001168
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001169void netxen_nic_write_w1(struct netxen_adapter *adapter, u32 index, u32 value)
1170{
1171 adapter->hw_write_wx(adapter, index, &value, 4);
1172}
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001173
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001174void netxen_nic_read_w1(struct netxen_adapter *adapter, u32 index, u32 *value)
1175{
1176 adapter->hw_read_wx(adapter, index, value, 4);
1177}
1178
1179/*
1180 * check memory access boundary.
1181 * used by test agent. support ddr access only for now
1182 */
1183static unsigned long
1184netxen_nic_pci_mem_bound_check(struct netxen_adapter *adapter,
1185 unsigned long long addr, int size)
1186{
1187 if (!ADDR_IN_RANGE(addr,
1188 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1189 !ADDR_IN_RANGE(addr+size-1,
1190 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX) ||
1191 ((size != 1) && (size != 2) && (size != 4) && (size != 8))) {
1192 return 0;
1193 }
1194
1195 return 1;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001196}
1197
Jeff Garzik47906542007-11-23 21:23:36 -05001198static int netxen_pci_set_window_warning_count;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001199
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001200unsigned long
1201netxen_nic_pci_set_window_128M(struct netxen_adapter *adapter,
1202 unsigned long long addr)
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001203{
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07001204 void __iomem *offset;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001205 int window;
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001206 unsigned long long qdr_max;
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07001207 uint8_t func = adapter->ahw.pci_func;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001208
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001209 if (NX_IS_REVISION_P2(adapter->ahw.revision_id)) {
1210 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1211 } else {
1212 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1213 }
1214
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001215 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1216 /* DDR network side */
1217 addr -= NETXEN_ADDR_DDR_NET;
1218 window = (addr >> 25) & 0x3ff;
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001219 if (adapter->ahw.ddr_mn_window != window) {
1220 adapter->ahw.ddr_mn_window = window;
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07001221 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1222 NETXEN_PCIX_PH_REG(PCIE_MN_WINDOW_REG(func)));
1223 writel(window, offset);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001224 /* MUST make sure window is set before we forge on... */
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07001225 readl(offset);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001226 }
Amit S. Kalecb8011a2006-11-29 09:00:10 -08001227 addr -= (window * NETXEN_WINDOW_ONE);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001228 addr += NETXEN_PCI_DDR_NET;
1229 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1230 addr -= NETXEN_ADDR_OCM0;
1231 addr += NETXEN_PCI_OCM0;
1232 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1233 addr -= NETXEN_ADDR_OCM1;
1234 addr += NETXEN_PCI_OCM1;
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001235 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001236 /* QDR network side */
1237 addr -= NETXEN_ADDR_QDR_NET;
1238 window = (addr >> 22) & 0x3f;
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001239 if (adapter->ahw.qdr_sn_window != window) {
1240 adapter->ahw.qdr_sn_window = window;
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07001241 offset = PCI_OFFSET_SECOND_RANGE(adapter,
1242 NETXEN_PCIX_PH_REG(PCIE_SN_WINDOW_REG(func)));
1243 writel((window << 22), offset);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001244 /* MUST make sure window is set before we forge on... */
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07001245 readl(offset);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001246 }
1247 addr -= (window * 0x400000);
1248 addr += NETXEN_PCI_QDR_NET;
1249 } else {
1250 /*
1251 * peg gdb frequently accesses memory that doesn't exist,
1252 * this limits the chit chat so debugging isn't slowed down.
1253 */
1254 if ((netxen_pci_set_window_warning_count++ < 8)
1255 || (netxen_pci_set_window_warning_count % 64 == 0))
1256 printk("%s: Warning:netxen_nic_pci_set_window()"
1257 " Unknown address range!\n",
1258 netxen_nic_driver_name);
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001259 addr = -1UL;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001260 }
1261 return addr;
1262}
1263
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07001264/*
1265 * Note : only 32-bit writes!
1266 */
1267int netxen_nic_pci_write_immediate_128M(struct netxen_adapter *adapter,
1268 u64 off, u32 data)
1269{
1270 writel(data, (void __iomem *)(PCI_OFFSET_SECOND_RANGE(adapter, off)));
1271 return 0;
1272}
1273
1274u32 netxen_nic_pci_read_immediate_128M(struct netxen_adapter *adapter, u64 off)
1275{
1276 return readl((void __iomem *)(pci_base_offset(adapter, off)));
1277}
1278
1279void netxen_nic_pci_write_normalize_128M(struct netxen_adapter *adapter,
1280 u64 off, u32 data)
1281{
1282 writel(data, NETXEN_CRB_NORMALIZE(adapter, off));
1283}
1284
1285u32 netxen_nic_pci_read_normalize_128M(struct netxen_adapter *adapter, u64 off)
1286{
1287 return readl(NETXEN_CRB_NORMALIZE(adapter, off));
1288}
1289
1290unsigned long
1291netxen_nic_pci_set_window_2M(struct netxen_adapter *adapter,
1292 unsigned long long addr)
1293{
1294 int window;
1295 u32 win_read;
1296
1297 if (ADDR_IN_RANGE(addr, NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1298 /* DDR network side */
1299 window = MN_WIN(addr);
1300 adapter->ahw.ddr_mn_window = window;
1301 adapter->hw_write_wx(adapter,
1302 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1303 &window, 4);
1304 adapter->hw_read_wx(adapter,
1305 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1306 &win_read, 4);
1307 if ((win_read << 17) != window) {
1308 printk(KERN_INFO "Written MNwin (0x%x) != "
1309 "Read MNwin (0x%x)\n", window, win_read);
1310 }
1311 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_DDR_NET;
1312 } else if (ADDR_IN_RANGE(addr,
1313 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1314 if ((addr & 0x00ff800) == 0xff800) {
1315 printk("%s: QM access not handled.\n", __func__);
1316 addr = -1UL;
1317 }
1318
1319 window = OCM_WIN(addr);
1320 adapter->ahw.ddr_mn_window = window;
1321 adapter->hw_write_wx(adapter,
1322 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1323 &window, 4);
1324 adapter->hw_read_wx(adapter,
1325 adapter->ahw.mn_win_crb | NETXEN_PCI_CRBSPACE,
1326 &win_read, 4);
1327 if ((win_read >> 7) != window) {
1328 printk(KERN_INFO "%s: Written OCMwin (0x%x) != "
1329 "Read OCMwin (0x%x)\n",
1330 __func__, window, win_read);
1331 }
1332 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_OCM0_2M;
1333
1334 } else if (ADDR_IN_RANGE(addr,
1335 NETXEN_ADDR_QDR_NET, NETXEN_ADDR_QDR_NET_MAX_P3)) {
1336 /* QDR network side */
1337 window = MS_WIN(addr);
1338 adapter->ahw.qdr_sn_window = window;
1339 adapter->hw_write_wx(adapter,
1340 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1341 &window, 4);
1342 adapter->hw_read_wx(adapter,
1343 adapter->ahw.ms_win_crb | NETXEN_PCI_CRBSPACE,
1344 &win_read, 4);
1345 if (win_read != window) {
1346 printk(KERN_INFO "%s: Written MSwin (0x%x) != "
1347 "Read MSwin (0x%x)\n",
1348 __func__, window, win_read);
1349 }
1350 addr = GET_MEM_OFFS_2M(addr) + NETXEN_PCI_QDR_NET;
1351
1352 } else {
1353 /*
1354 * peg gdb frequently accesses memory that doesn't exist,
1355 * this limits the chit chat so debugging isn't slowed down.
1356 */
1357 if ((netxen_pci_set_window_warning_count++ < 8)
1358 || (netxen_pci_set_window_warning_count%64 == 0)) {
1359 printk("%s: Warning:%s Unknown address range!\n",
1360 __func__, netxen_nic_driver_name);
1361}
1362 addr = -1UL;
1363 }
1364 return addr;
1365}
1366
1367static int netxen_nic_pci_is_same_window(struct netxen_adapter *adapter,
1368 unsigned long long addr)
1369{
1370 int window;
1371 unsigned long long qdr_max;
1372
1373 if (NX_IS_REVISION_P2(adapter->ahw.revision_id))
1374 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P2;
1375 else
1376 qdr_max = NETXEN_ADDR_QDR_NET_MAX_P3;
1377
1378 if (ADDR_IN_RANGE(addr,
1379 NETXEN_ADDR_DDR_NET, NETXEN_ADDR_DDR_NET_MAX)) {
1380 /* DDR network side */
1381 BUG(); /* MN access can not come here */
1382 } else if (ADDR_IN_RANGE(addr,
1383 NETXEN_ADDR_OCM0, NETXEN_ADDR_OCM0_MAX)) {
1384 return 1;
1385 } else if (ADDR_IN_RANGE(addr,
1386 NETXEN_ADDR_OCM1, NETXEN_ADDR_OCM1_MAX)) {
1387 return 1;
1388 } else if (ADDR_IN_RANGE(addr, NETXEN_ADDR_QDR_NET, qdr_max)) {
1389 /* QDR network side */
1390 window = ((addr - NETXEN_ADDR_QDR_NET) >> 22) & 0x3f;
1391 if (adapter->ahw.qdr_sn_window == window)
1392 return 1;
1393 }
1394
1395 return 0;
1396}
1397
1398static int netxen_nic_pci_mem_read_direct(struct netxen_adapter *adapter,
1399 u64 off, void *data, int size)
1400{
1401 unsigned long flags;
1402 void *addr;
1403 int ret = 0;
1404 u64 start;
1405 uint8_t *mem_ptr = NULL;
1406 unsigned long mem_base;
1407 unsigned long mem_page;
1408
1409 write_lock_irqsave(&adapter->adapter_lock, flags);
1410
1411 /*
1412 * If attempting to access unknown address or straddle hw windows,
1413 * do not access.
1414 */
1415 start = adapter->pci_set_window(adapter, off);
1416 if ((start == -1UL) ||
1417 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1418 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1419 printk(KERN_ERR "%s out of bound pci memory access. "
1420 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1421 return -1;
1422 }
1423
1424 addr = (void *)(pci_base_offset(adapter, start));
1425 if (!addr) {
1426 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1427 mem_base = pci_resource_start(adapter->pdev, 0);
1428 mem_page = start & PAGE_MASK;
1429 /* Map two pages whenever user tries to access addresses in two
1430 consecutive pages.
1431 */
1432 if (mem_page != ((start + size - 1) & PAGE_MASK))
1433 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE * 2);
1434 else
1435 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1436 if (mem_ptr == 0UL) {
1437 *(uint8_t *)data = 0;
1438 return -1;
1439 }
1440 addr = mem_ptr;
1441 addr += start & (PAGE_SIZE - 1);
1442 write_lock_irqsave(&adapter->adapter_lock, flags);
1443 }
1444
1445 switch (size) {
1446 case 1:
1447 *(uint8_t *)data = readb(addr);
1448 break;
1449 case 2:
1450 *(uint16_t *)data = readw(addr);
1451 break;
1452 case 4:
1453 *(uint32_t *)data = readl(addr);
1454 break;
1455 case 8:
1456 *(uint64_t *)data = readq(addr);
1457 break;
1458 default:
1459 ret = -1;
1460 break;
1461 }
1462 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1463 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1464
1465 if (mem_ptr)
1466 iounmap(mem_ptr);
1467 return ret;
1468}
1469
1470static int
1471netxen_nic_pci_mem_write_direct(struct netxen_adapter *adapter, u64 off,
1472 void *data, int size)
1473{
1474 unsigned long flags;
1475 void *addr;
1476 int ret = 0;
1477 u64 start;
1478 uint8_t *mem_ptr = NULL;
1479 unsigned long mem_base;
1480 unsigned long mem_page;
1481
1482 write_lock_irqsave(&adapter->adapter_lock, flags);
1483
1484 /*
1485 * If attempting to access unknown address or straddle hw windows,
1486 * do not access.
1487 */
1488 start = adapter->pci_set_window(adapter, off);
1489 if ((start == -1UL) ||
1490 (netxen_nic_pci_is_same_window(adapter, off+size-1) == 0)) {
1491 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1492 printk(KERN_ERR "%s out of bound pci memory access. "
1493 "offset is 0x%llx\n", netxen_nic_driver_name, off);
1494 return -1;
1495 }
1496
1497 addr = (void *)(pci_base_offset(adapter, start));
1498 if (!addr) {
1499 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1500 mem_base = pci_resource_start(adapter->pdev, 0);
1501 mem_page = start & PAGE_MASK;
1502 /* Map two pages whenever user tries to access addresses in two
1503 * consecutive pages.
1504 */
1505 if (mem_page != ((start + size - 1) & PAGE_MASK))
1506 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE*2);
1507 else
1508 mem_ptr = ioremap(mem_base + mem_page, PAGE_SIZE);
1509 if (mem_ptr == 0UL)
1510 return -1;
1511 addr = mem_ptr;
1512 addr += start & (PAGE_SIZE - 1);
1513 write_lock_irqsave(&adapter->adapter_lock, flags);
1514 }
1515
1516 switch (size) {
1517 case 1:
1518 writeb(*(uint8_t *)data, addr);
1519 break;
1520 case 2:
1521 writew(*(uint16_t *)data, addr);
1522 break;
1523 case 4:
1524 writel(*(uint32_t *)data, addr);
1525 break;
1526 case 8:
1527 writeq(*(uint64_t *)data, addr);
1528 break;
1529 default:
1530 ret = -1;
1531 break;
1532 }
1533 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1534 DPRINTK(1, INFO, "writing data %llx to offset %llx\n",
1535 *(unsigned long long *)data, start);
1536 if (mem_ptr)
1537 iounmap(mem_ptr);
1538 return ret;
1539}
1540
1541#define MAX_CTL_CHECK 1000
1542
1543int
1544netxen_nic_pci_mem_write_128M(struct netxen_adapter *adapter,
1545 u64 off, void *data, int size)
1546{
1547 unsigned long flags, mem_crb;
1548 int i, j, ret = 0, loop, sz[2], off0;
1549 uint32_t temp;
1550 uint64_t off8, tmpw, word[2] = {0, 0};
1551
1552 /*
1553 * If not MN, go check for MS or invalid.
1554 */
1555 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1556 return netxen_nic_pci_mem_write_direct(adapter,
1557 off, data, size);
1558
1559 off8 = off & 0xfffffff8;
1560 off0 = off & 0x7;
1561 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1562 sz[1] = size - sz[0];
1563 loop = ((off0 + size - 1) >> 3) + 1;
1564 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1565
1566 if ((size != 8) || (off0 != 0)) {
1567 for (i = 0; i < loop; i++) {
1568 if (adapter->pci_mem_read(adapter,
1569 off8 + (i << 3), &word[i], 8))
1570 return -1;
1571 }
1572 }
1573
1574 switch (size) {
1575 case 1:
1576 tmpw = *((uint8_t *)data);
1577 break;
1578 case 2:
1579 tmpw = *((uint16_t *)data);
1580 break;
1581 case 4:
1582 tmpw = *((uint32_t *)data);
1583 break;
1584 case 8:
1585 default:
1586 tmpw = *((uint64_t *)data);
1587 break;
1588 }
1589 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1590 word[0] |= tmpw << (off0 * 8);
1591
1592 if (loop == 2) {
1593 word[1] &= ~(~0ULL << (sz[1] * 8));
1594 word[1] |= tmpw >> (sz[0] * 8);
1595 }
1596
1597 write_lock_irqsave(&adapter->adapter_lock, flags);
1598 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1599
1600 for (i = 0; i < loop; i++) {
1601 writel((uint32_t)(off8 + (i << 3)),
1602 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1603 writel(0,
1604 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1605 writel(word[i] & 0xffffffff,
1606 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_LO));
1607 writel((word[i] >> 32) & 0xffffffff,
1608 (void *)(mem_crb+MIU_TEST_AGT_WRDATA_HI));
1609 writel(MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1610 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1611 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE|MIU_TA_CTL_WRITE,
1612 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1613
1614 for (j = 0; j < MAX_CTL_CHECK; j++) {
1615 temp = readl(
1616 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1617 if ((temp & MIU_TA_CTL_BUSY) == 0)
1618 break;
1619 }
1620
1621 if (j >= MAX_CTL_CHECK) {
1622 printk("%s: %s Fail to write through agent\n",
1623 __func__, netxen_nic_driver_name);
1624 ret = -1;
1625 break;
1626 }
1627 }
1628
1629 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1630 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1631 return ret;
1632}
1633
1634int
1635netxen_nic_pci_mem_read_128M(struct netxen_adapter *adapter,
1636 u64 off, void *data, int size)
1637{
1638 unsigned long flags, mem_crb;
1639 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1640 uint32_t temp;
1641 uint64_t off8, val, word[2] = {0, 0};
1642
1643
1644 /*
1645 * If not MN, go check for MS or invalid.
1646 */
1647 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1648 return netxen_nic_pci_mem_read_direct(adapter, off, data, size);
1649
1650 off8 = off & 0xfffffff8;
1651 off0[0] = off & 0x7;
1652 off0[1] = 0;
1653 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1654 sz[1] = size - sz[0];
1655 loop = ((off0[0] + size - 1) >> 3) + 1;
1656 mem_crb = (unsigned long)pci_base_offset(adapter, NETXEN_CRB_DDR_NET);
1657
1658 write_lock_irqsave(&adapter->adapter_lock, flags);
1659 netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1660
1661 for (i = 0; i < loop; i++) {
1662 writel((uint32_t)(off8 + (i << 3)),
1663 (void *)(mem_crb+MIU_TEST_AGT_ADDR_LO));
1664 writel(0,
1665 (void *)(mem_crb+MIU_TEST_AGT_ADDR_HI));
1666 writel(MIU_TA_CTL_ENABLE,
1667 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1668 writel(MIU_TA_CTL_START|MIU_TA_CTL_ENABLE,
1669 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1670
1671 for (j = 0; j < MAX_CTL_CHECK; j++) {
1672 temp = readl(
1673 (void *)(mem_crb+MIU_TEST_AGT_CTRL));
1674 if ((temp & MIU_TA_CTL_BUSY) == 0)
1675 break;
1676 }
1677
1678 if (j >= MAX_CTL_CHECK) {
1679 printk(KERN_ERR "%s: %s Fail to read through agent\n",
1680 __func__, netxen_nic_driver_name);
1681 break;
1682 }
1683
1684 start = off0[i] >> 2;
1685 end = (off0[i] + sz[i] - 1) >> 2;
1686 for (k = start; k <= end; k++) {
1687 word[i] |= ((uint64_t) readl(
1688 (void *)(mem_crb +
1689 MIU_TEST_AGT_RDDATA(k))) << (32*k));
1690 }
1691 }
1692
1693 netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1694 write_unlock_irqrestore(&adapter->adapter_lock, flags);
1695
1696 if (j >= MAX_CTL_CHECK)
1697 return -1;
1698
1699 if (sz[0] == 8) {
1700 val = word[0];
1701 } else {
1702 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1703 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1704 }
1705
1706 switch (size) {
1707 case 1:
1708 *(uint8_t *)data = val;
1709 break;
1710 case 2:
1711 *(uint16_t *)data = val;
1712 break;
1713 case 4:
1714 *(uint32_t *)data = val;
1715 break;
1716 case 8:
1717 *(uint64_t *)data = val;
1718 break;
1719 }
1720 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1721 return 0;
1722}
1723
1724int
1725netxen_nic_pci_mem_write_2M(struct netxen_adapter *adapter,
1726 u64 off, void *data, int size)
1727{
1728 int i, j, ret = 0, loop, sz[2], off0;
1729 uint32_t temp;
1730 uint64_t off8, mem_crb, tmpw, word[2] = {0, 0};
1731
1732 /*
1733 * If not MN, go check for MS or invalid.
1734 */
1735 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1736 mem_crb = NETXEN_CRB_QDR_NET;
1737 else {
1738 mem_crb = NETXEN_CRB_DDR_NET;
1739 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1740 return netxen_nic_pci_mem_write_direct(adapter,
1741 off, data, size);
1742 }
1743
1744 off8 = off & 0xfffffff8;
1745 off0 = off & 0x7;
1746 sz[0] = (size < (8 - off0)) ? size : (8 - off0);
1747 sz[1] = size - sz[0];
1748 loop = ((off0 + size - 1) >> 3) + 1;
1749
1750 if ((size != 8) || (off0 != 0)) {
1751 for (i = 0; i < loop; i++) {
1752 if (adapter->pci_mem_read(adapter, off8 + (i << 3),
1753 &word[i], 8))
1754 return -1;
1755 }
1756 }
1757
1758 switch (size) {
1759 case 1:
1760 tmpw = *((uint8_t *)data);
1761 break;
1762 case 2:
1763 tmpw = *((uint16_t *)data);
1764 break;
1765 case 4:
1766 tmpw = *((uint32_t *)data);
1767 break;
1768 case 8:
1769 default:
1770 tmpw = *((uint64_t *)data);
1771 break;
1772 }
1773
1774 word[0] &= ~((~(~0ULL << (sz[0] * 8))) << (off0 * 8));
1775 word[0] |= tmpw << (off0 * 8);
1776
1777 if (loop == 2) {
1778 word[1] &= ~(~0ULL << (sz[1] * 8));
1779 word[1] |= tmpw >> (sz[0] * 8);
1780 }
1781
1782 /*
1783 * don't lock here - write_wx gets the lock if each time
1784 * write_lock_irqsave(&adapter->adapter_lock, flags);
1785 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1786 */
1787
1788 for (i = 0; i < loop; i++) {
1789 temp = off8 + (i << 3);
1790 adapter->hw_write_wx(adapter,
1791 mem_crb+MIU_TEST_AGT_ADDR_LO, &temp, 4);
1792 temp = 0;
1793 adapter->hw_write_wx(adapter,
1794 mem_crb+MIU_TEST_AGT_ADDR_HI, &temp, 4);
1795 temp = word[i] & 0xffffffff;
1796 adapter->hw_write_wx(adapter,
1797 mem_crb+MIU_TEST_AGT_WRDATA_LO, &temp, 4);
1798 temp = (word[i] >> 32) & 0xffffffff;
1799 adapter->hw_write_wx(adapter,
1800 mem_crb+MIU_TEST_AGT_WRDATA_HI, &temp, 4);
1801 temp = MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1802 adapter->hw_write_wx(adapter,
1803 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1804 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE | MIU_TA_CTL_WRITE;
1805 adapter->hw_write_wx(adapter,
1806 mem_crb+MIU_TEST_AGT_CTRL, &temp, 4);
1807
1808 for (j = 0; j < MAX_CTL_CHECK; j++) {
1809 adapter->hw_read_wx(adapter,
1810 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1811 if ((temp & MIU_TA_CTL_BUSY) == 0)
1812 break;
1813 }
1814
1815 if (j >= MAX_CTL_CHECK) {
1816 printk(KERN_ERR "%s: Fail to write through agent\n",
1817 netxen_nic_driver_name);
1818 ret = -1;
1819 break;
1820 }
1821 }
1822
1823 /*
1824 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1825 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1826 */
1827 return ret;
1828}
1829
1830int
1831netxen_nic_pci_mem_read_2M(struct netxen_adapter *adapter,
1832 u64 off, void *data, int size)
1833{
1834 int i, j = 0, k, start, end, loop, sz[2], off0[2];
1835 uint32_t temp;
1836 uint64_t off8, val, mem_crb, word[2] = {0, 0};
1837
1838 /*
1839 * If not MN, go check for MS or invalid.
1840 */
1841
1842 if (off >= NETXEN_ADDR_QDR_NET && off <= NETXEN_ADDR_QDR_NET_MAX_P3)
1843 mem_crb = NETXEN_CRB_QDR_NET;
1844 else {
1845 mem_crb = NETXEN_CRB_DDR_NET;
1846 if (netxen_nic_pci_mem_bound_check(adapter, off, size) == 0)
1847 return netxen_nic_pci_mem_read_direct(adapter,
1848 off, data, size);
1849 }
1850
1851 off8 = off & 0xfffffff8;
1852 off0[0] = off & 0x7;
1853 off0[1] = 0;
1854 sz[0] = (size < (8 - off0[0])) ? size : (8 - off0[0]);
1855 sz[1] = size - sz[0];
1856 loop = ((off0[0] + size - 1) >> 3) + 1;
1857
1858 /*
1859 * don't lock here - write_wx gets the lock if each time
1860 * write_lock_irqsave(&adapter->adapter_lock, flags);
1861 * netxen_nic_pci_change_crbwindow_128M(adapter, 0);
1862 */
1863
1864 for (i = 0; i < loop; i++) {
1865 temp = off8 + (i << 3);
1866 adapter->hw_write_wx(adapter,
1867 mem_crb + MIU_TEST_AGT_ADDR_LO, &temp, 4);
1868 temp = 0;
1869 adapter->hw_write_wx(adapter,
1870 mem_crb + MIU_TEST_AGT_ADDR_HI, &temp, 4);
1871 temp = MIU_TA_CTL_ENABLE;
1872 adapter->hw_write_wx(adapter,
1873 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1874 temp = MIU_TA_CTL_START | MIU_TA_CTL_ENABLE;
1875 adapter->hw_write_wx(adapter,
1876 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1877
1878 for (j = 0; j < MAX_CTL_CHECK; j++) {
1879 adapter->hw_read_wx(adapter,
1880 mem_crb + MIU_TEST_AGT_CTRL, &temp, 4);
1881 if ((temp & MIU_TA_CTL_BUSY) == 0)
1882 break;
1883 }
1884
1885 if (j >= MAX_CTL_CHECK) {
1886 printk(KERN_ERR "%s: Fail to read through agent\n",
1887 netxen_nic_driver_name);
1888 break;
1889 }
1890
1891 start = off0[i] >> 2;
1892 end = (off0[i] + sz[i] - 1) >> 2;
1893 for (k = start; k <= end; k++) {
1894 adapter->hw_read_wx(adapter,
1895 mem_crb + MIU_TEST_AGT_RDDATA(k), &temp, 4);
1896 word[i] |= ((uint64_t)temp << (32 * k));
1897 }
1898 }
1899
1900 /*
1901 * netxen_nic_pci_change_crbwindow_128M(adapter, 1);
1902 * write_unlock_irqrestore(&adapter->adapter_lock, flags);
1903 */
1904
1905 if (j >= MAX_CTL_CHECK)
1906 return -1;
1907
1908 if (sz[0] == 8) {
1909 val = word[0];
1910 } else {
1911 val = ((word[0] >> (off0[0] * 8)) & (~(~0ULL << (sz[0] * 8)))) |
1912 ((word[1] & (~(~0ULL << (sz[1] * 8)))) << (sz[0] * 8));
1913 }
1914
1915 switch (size) {
1916 case 1:
1917 *(uint8_t *)data = val;
1918 break;
1919 case 2:
1920 *(uint16_t *)data = val;
1921 break;
1922 case 4:
1923 *(uint32_t *)data = val;
1924 break;
1925 case 8:
1926 *(uint64_t *)data = val;
1927 break;
1928 }
1929 DPRINTK(1, INFO, "read %llx\n", *(unsigned long long *)data);
1930 return 0;
1931}
1932
1933/*
1934 * Note : only 32-bit writes!
1935 */
1936int netxen_nic_pci_write_immediate_2M(struct netxen_adapter *adapter,
1937 u64 off, u32 data)
1938{
1939 adapter->hw_write_wx(adapter, off, &data, 4);
1940
1941 return 0;
1942}
1943
1944u32 netxen_nic_pci_read_immediate_2M(struct netxen_adapter *adapter, u64 off)
1945{
1946 u32 temp;
1947 adapter->hw_read_wx(adapter, off, &temp, 4);
1948 return temp;
1949}
1950
1951void netxen_nic_pci_write_normalize_2M(struct netxen_adapter *adapter,
1952 u64 off, u32 data)
1953{
1954 adapter->hw_write_wx(adapter, off, &data, 4);
1955}
1956
1957u32 netxen_nic_pci_read_normalize_2M(struct netxen_adapter *adapter, u64 off)
1958{
1959 u32 temp;
1960 adapter->hw_read_wx(adapter, off, &temp, 4);
1961 return temp;
1962}
1963
Adrian Bunk993fb902007-11-05 18:07:31 +01001964#if 0
Mithlesh Thukral13ba9c72007-04-20 07:53:05 -07001965int
1966netxen_nic_erase_pxe(struct netxen_adapter *adapter)
1967{
Mithlesh Thukral0d047612007-06-07 04:36:36 -07001968 if (netxen_rom_fast_write(adapter, NETXEN_PXE_START, 0) == -1) {
Jeff Garzik47906542007-11-23 21:23:36 -05001969 printk(KERN_ERR "%s: erase pxe failed\n",
Mithlesh Thukral13ba9c72007-04-20 07:53:05 -07001970 netxen_nic_driver_name);
1971 return -1;
1972 }
1973 return 0;
1974}
Adrian Bunk993fb902007-11-05 18:07:31 +01001975#endif /* 0 */
Mithlesh Thukral13ba9c72007-04-20 07:53:05 -07001976
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001977int netxen_nic_get_board_info(struct netxen_adapter *adapter)
1978{
1979 int rv = 0;
Mithlesh Thukral0d047612007-06-07 04:36:36 -07001980 int addr = NETXEN_BRDCFG_START;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04001981 struct netxen_board_info *boardinfo;
1982 int index;
1983 u32 *ptr32;
1984
1985 boardinfo = &adapter->ahw.boardcfg;
1986 ptr32 = (u32 *) boardinfo;
1987
1988 for (index = 0; index < sizeof(struct netxen_board_info) / sizeof(u32);
1989 index++) {
1990 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
1991 return -EIO;
1992 }
1993 ptr32++;
1994 addr += sizeof(u32);
1995 }
1996 if (boardinfo->magic != NETXEN_BDINFO_MAGIC) {
1997 printk("%s: ERROR reading %s board config."
1998 " Read %x, expected %x\n", netxen_nic_driver_name,
1999 netxen_nic_driver_name,
2000 boardinfo->magic, NETXEN_BDINFO_MAGIC);
2001 rv = -1;
2002 }
2003 if (boardinfo->header_version != NETXEN_BDINFO_VERSION) {
2004 printk("%s: Unknown board config version."
2005 " Read %x, expected %x\n", netxen_nic_driver_name,
2006 boardinfo->header_version, NETXEN_BDINFO_VERSION);
2007 rv = -1;
2008 }
2009
2010 DPRINTK(INFO, "Discovered board type:0x%x ", boardinfo->board_type);
2011 switch ((netxen_brdtype_t) boardinfo->board_type) {
2012 case NETXEN_BRDTYPE_P2_SB35_4G:
2013 adapter->ahw.board_type = NETXEN_NIC_GBE;
2014 break;
2015 case NETXEN_BRDTYPE_P2_SB31_10G:
2016 case NETXEN_BRDTYPE_P2_SB31_10G_IMEZ:
2017 case NETXEN_BRDTYPE_P2_SB31_10G_HMEZ:
2018 case NETXEN_BRDTYPE_P2_SB31_10G_CX4:
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07002019 case NETXEN_BRDTYPE_P3_HMEZ:
2020 case NETXEN_BRDTYPE_P3_XG_LOM:
2021 case NETXEN_BRDTYPE_P3_10G_CX4:
2022 case NETXEN_BRDTYPE_P3_10G_CX4_LP:
2023 case NETXEN_BRDTYPE_P3_IMEZ:
2024 case NETXEN_BRDTYPE_P3_10G_SFP_PLUS:
Dhananjay Phadkea70f9392008-08-01 03:14:56 -07002025 case NETXEN_BRDTYPE_P3_10G_SFP_CT:
2026 case NETXEN_BRDTYPE_P3_10G_SFP_QT:
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07002027 case NETXEN_BRDTYPE_P3_10G_XFP:
2028 case NETXEN_BRDTYPE_P3_10000_BASE_T:
2029
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002030 adapter->ahw.board_type = NETXEN_NIC_XGBE;
2031 break;
2032 case NETXEN_BRDTYPE_P1_BD:
2033 case NETXEN_BRDTYPE_P1_SB:
2034 case NETXEN_BRDTYPE_P1_SMAX:
2035 case NETXEN_BRDTYPE_P1_SOCK:
Dhananjay Phadkee4c93c82008-07-21 19:44:02 -07002036 case NETXEN_BRDTYPE_P3_REF_QG:
2037 case NETXEN_BRDTYPE_P3_4_GB:
2038 case NETXEN_BRDTYPE_P3_4_GB_MM:
2039
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002040 adapter->ahw.board_type = NETXEN_NIC_GBE;
2041 break;
2042 default:
2043 printk("%s: Unknown(%x)\n", netxen_nic_driver_name,
2044 boardinfo->board_type);
Dhananjay Phadkea70f9392008-08-01 03:14:56 -07002045 rv = -ENODEV;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002046 break;
2047 }
2048
2049 return rv;
2050}
2051
2052/* NIU access sections */
2053
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002054int netxen_nic_set_mtu_gb(struct netxen_adapter *adapter, int new_mtu)
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002055{
Dhananjay Phadke9ad27642008-08-01 03:14:59 -07002056 new_mtu += MTU_FUDGE_FACTOR;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002057 netxen_nic_write_w0(adapter,
Dhananjay Phadke3276fba2008-06-15 22:59:44 -07002058 NETXEN_NIU_GB_MAX_FRAME_SIZE(adapter->physical_port),
2059 new_mtu);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002060 return 0;
2061}
2062
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002063int netxen_nic_set_mtu_xgb(struct netxen_adapter *adapter, int new_mtu)
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002064{
Dhananjay Phadke9ad27642008-08-01 03:14:59 -07002065 new_mtu += MTU_FUDGE_FACTOR;
Dhananjay Phadke3276fba2008-06-15 22:59:44 -07002066 if (adapter->physical_port == 0)
Jeff Garzik47906542007-11-23 21:23:36 -05002067 netxen_nic_write_w0(adapter, NETXEN_NIU_XGE_MAX_FRAME_SIZE,
Mithlesh Thukral595e3fb2007-04-20 07:53:52 -07002068 new_mtu);
Jeff Garzik47906542007-11-23 21:23:36 -05002069 else
Mithlesh Thukral595e3fb2007-04-20 07:53:52 -07002070 netxen_nic_write_w0(adapter, NETXEN_NIU_XG1_MAX_FRAME_SIZE,
2071 new_mtu);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002072 return 0;
2073}
2074
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002075void
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07002076netxen_crb_writelit_adapter(struct netxen_adapter *adapter,
2077 unsigned long off, int data)
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002078{
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07002079 adapter->hw_write_wx(adapter, off, &data, 4);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002080}
2081
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002082void netxen_nic_set_link_parameters(struct netxen_adapter *adapter)
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002083{
Al Viroa608ab9c2007-01-02 10:39:10 +00002084 __u32 status;
2085 __u32 autoneg;
2086 __u32 mode;
Dhananjay Phadke24a7a452008-08-01 03:14:55 -07002087 __u32 port_mode;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002088
2089 netxen_nic_read_w0(adapter, NETXEN_NIU_MODE, &mode);
2090 if (netxen_get_niu_enable_ge(mode)) { /* Gb 10/100/1000 Mbps mode */
Dhananjay Phadke24a7a452008-08-01 03:14:55 -07002091
2092 adapter->hw_read_wx(adapter,
2093 NETXEN_PORT_MODE_ADDR, &port_mode, 4);
2094 if (port_mode == NETXEN_PORT_MODE_802_3_AP) {
2095 adapter->link_speed = SPEED_1000;
2096 adapter->link_duplex = DUPLEX_FULL;
2097 adapter->link_autoneg = AUTONEG_DISABLE;
2098 return;
2099 }
2100
Amit S. Kale80922fb2006-12-04 09:18:00 -08002101 if (adapter->phy_read
Dhananjay Phadke24a7a452008-08-01 03:14:55 -07002102 && adapter->phy_read(adapter,
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002103 NETXEN_NIU_GB_MII_MGMT_ADDR_PHY_STATUS,
2104 &status) == 0) {
2105 if (netxen_get_phy_link(status)) {
2106 switch (netxen_get_phy_speed(status)) {
2107 case 0:
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002108 adapter->link_speed = SPEED_10;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002109 break;
2110 case 1:
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002111 adapter->link_speed = SPEED_100;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002112 break;
2113 case 2:
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002114 adapter->link_speed = SPEED_1000;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002115 break;
2116 default:
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002117 adapter->link_speed = -1;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002118 break;
2119 }
2120 switch (netxen_get_phy_duplex(status)) {
2121 case 0:
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002122 adapter->link_duplex = DUPLEX_HALF;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002123 break;
2124 case 1:
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002125 adapter->link_duplex = DUPLEX_FULL;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002126 break;
2127 default:
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002128 adapter->link_duplex = -1;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002129 break;
2130 }
Amit S. Kale80922fb2006-12-04 09:18:00 -08002131 if (adapter->phy_read
Dhananjay Phadke24a7a452008-08-01 03:14:55 -07002132 && adapter->phy_read(adapter,
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002133 NETXEN_NIU_GB_MII_MGMT_ADDR_AUTONEG,
Amit S. Kaleed25ffa2006-12-04 09:23:25 -08002134 &autoneg) != 0)
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002135 adapter->link_autoneg = autoneg;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002136 } else
2137 goto link_down;
2138 } else {
2139 link_down:
Mithlesh Thukral3176ff32007-04-20 07:52:37 -07002140 adapter->link_speed = -1;
2141 adapter->link_duplex = -1;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002142 }
2143 }
2144}
2145
2146void netxen_nic_flash_print(struct netxen_adapter *adapter)
2147{
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002148 u32 fw_major = 0;
2149 u32 fw_minor = 0;
2150 u32 fw_build = 0;
Amit S. Kalecb8011a2006-11-29 09:00:10 -08002151 char brd_name[NETXEN_MAX_SHORT_NAME];
Harvey Harrison8d748492008-04-22 11:48:35 -07002152 char serial_num[32];
2153 int i, addr;
Mithlesh Thukral6d1495f2007-04-20 07:56:42 -07002154 __le32 *ptr32;
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002155
2156 struct netxen_board_info *board_info = &(adapter->ahw.boardcfg);
Harvey Harrison8d748492008-04-22 11:48:35 -07002157
Dhananjay Phadkedcd56fd2008-06-15 22:59:45 -07002158 adapter->driver_mismatch = 0;
2159
2160 ptr32 = (u32 *)&serial_num;
2161 addr = NETXEN_USER_START +
2162 offsetof(struct netxen_new_user_info, serial_num);
2163 for (i = 0; i < 8; i++) {
2164 if (netxen_rom_fast_read(adapter, addr, ptr32) == -1) {
2165 printk("%s: ERROR reading %s board userarea.\n",
2166 netxen_nic_driver_name,
2167 netxen_nic_driver_name);
2168 adapter->driver_mismatch = 1;
2169 return;
2170 }
2171 ptr32++;
2172 addr += sizeof(u32);
2173 }
2174
Dhananjay Phadke3ce06a32008-07-21 19:44:03 -07002175 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MAJOR, &fw_major, 4);
2176 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_MINOR, &fw_minor, 4);
2177 adapter->hw_read_wx(adapter, NETXEN_FW_VERSION_SUB, &fw_build, 4);
Dhananjay Phadkedcd56fd2008-06-15 22:59:45 -07002178
Dhananjay Phadke29566402008-07-21 19:44:04 -07002179 adapter->fw_major = fw_major;
2180
Dhananjay Phadkedcd56fd2008-06-15 22:59:45 -07002181 if (adapter->portnum == 0) {
Amit S. Kalecb8011a2006-11-29 09:00:10 -08002182 get_brd_name_by_type(board_info->board_type, brd_name);
2183
2184 printk("NetXen %s Board S/N %s Chip id 0x%x\n",
Dhananjay Phadkedcd56fd2008-06-15 22:59:45 -07002185 brd_name, serial_num, board_info->chip_id);
2186 printk("NetXen Firmware version %d.%d.%d\n", fw_major,
2187 fw_minor, fw_build);
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002188 }
Dhananjay Phadkedcd56fd2008-06-15 22:59:45 -07002189
Dhananjay Phadke58735562008-07-21 19:44:10 -07002190 if (NETXEN_VERSION_CODE(fw_major, fw_minor, fw_build) <
2191 NETXEN_VERSION_CODE(3, 4, 216)) {
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002192 adapter->driver_mismatch = 1;
Dhananjay Phadke58735562008-07-21 19:44:10 -07002193 printk(KERN_ERR "%s: firmware version %d.%d.%d unsupported\n",
2194 netxen_nic_driver_name,
2195 fw_major, fw_minor, fw_build);
Dhananjay Phadkedcd56fd2008-06-15 22:59:45 -07002196 return;
2197 }
Amit S. Kale3d396eb2006-10-21 15:33:03 -04002198}
2199