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Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +08001/*
2 * at91sam9263.dtsi - Device Tree Include file for AT91SAM9263 family SoC
3 *
4 * Copyright (C) 2012 Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
5 *
6 * Licensed under GPLv2 only.
7 */
8
Jean-Christophe PLAGNIOL-VILLARD6db64d22013-05-15 01:21:50 +08009#include "skeleton.dtsi"
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +080010#include <dt-bindings/pinctrl/at91.h>
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080011#include <dt-bindings/interrupt-controller/irq.h>
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +080012#include <dt-bindings/gpio/gpio.h>
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080013
14/ {
15 model = "Atmel AT91SAM9263 family SoC";
16 compatible = "atmel,at91sam9263";
17 interrupt-parent = <&aic>;
18
19 aliases {
20 serial0 = &dbgu;
21 serial1 = &usart0;
22 serial2 = &usart1;
23 serial3 = &usart2;
24 gpio0 = &pioA;
25 gpio1 = &pioB;
26 gpio2 = &pioC;
27 gpio3 = &pioD;
28 gpio4 = &pioE;
29 tcb0 = &tcb0;
Ludovic Desroches05dcd362012-09-12 08:42:16 +020030 i2c0 = &i2c0;
Bo Shen099343c2012-11-07 11:41:41 +080031 ssc0 = &ssc0;
32 ssc1 = &ssc1;
Bo Shenf3ab0522013-12-19 11:59:17 +080033 pwm0 = &pwm0;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080034 };
35 cpus {
Lorenzo Pieralisie757a6e2013-04-18 18:31:35 +010036 #address-cells = <0>;
37 #size-cells = <0>;
38
39 cpu {
40 compatible = "arm,arm926ej-s";
41 device_type = "cpu";
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080042 };
43 };
44
45 memory {
46 reg = <0x20000000 0x08000000>;
47 };
48
49 ahb {
50 compatible = "simple-bus";
51 #address-cells = <1>;
52 #size-cells = <1>;
53 ranges;
54
55 apb {
56 compatible = "simple-bus";
57 #address-cells = <1>;
58 #size-cells = <1>;
59 ranges;
60
61 aic: interrupt-controller@fffff000 {
Ludovic Desrochesf8a073e2012-06-20 16:13:30 +020062 #interrupt-cells = <3>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080063 compatible = "atmel,at91rm9200-aic";
64 interrupt-controller;
65 reg = <0xfffff000 0x200>;
Jean-Christophe PLAGNIOL-VILLARDc6573942012-04-09 19:36:36 +080066 atmel,external-irqs = <30 31>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080067 };
68
69 pmc: pmc@fffffc00 {
70 compatible = "atmel,at91rm9200-pmc";
71 reg = <0xfffffc00 0x100>;
72 };
73
74 ramc: ramc@ffffe200 {
75 compatible = "atmel,at91sam9260-sdramc";
76 reg = <0xffffe200 0x200
77 0xffffe800 0x200>;
78 };
79
80 pit: timer@fffffd30 {
81 compatible = "atmel,at91sam9260-pit";
82 reg = <0xfffffd30 0xf>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080083 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080084 };
85
86 tcb0: timer@fff7c000 {
87 compatible = "atmel,at91rm9200-tcb";
88 reg = <0xfff7c000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +080089 interrupts = <19 IRQ_TYPE_LEVEL_HIGH 0>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +080090 };
91
92 rstc@fffffd00 {
93 compatible = "atmel,at91sam9260-rstc";
94 reg = <0xfffffd00 0x10>;
95 };
96
97 shdwc@fffffd10 {
98 compatible = "atmel,at91sam9260-shdwc";
99 reg = <0xfffffd10 0x10>;
100 };
101
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800102 pinctrl@fffff200 {
103 #address-cells = <1>;
104 #size-cells = <1>;
105 compatible = "atmel,at91rm9200-pinctrl", "simple-bus";
106 ranges = <0xfffff200 0xfffff200 0xa00>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800107
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800108 atmel,mux-mask = <
109 /* A B */
110 0xfffffffb 0xffffe07f /* pioA */
111 0x0007ffff 0x39072fff /* pioB */
112 0xffffffff 0x3ffffff8 /* pioC */
113 0xfffffbff 0xffffffff /* pioD */
114 0xffe00fff 0xfbfcff00 /* pioE */
115 >;
116
117 /* shared pinctrl settings */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800118 dbgu {
119 pinctrl_dbgu: dbgu-0 {
120 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800121 <AT91_PIOC 30 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC30 periph A */
122 AT91_PIOC 31 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PC31 periph with pullup */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800123 };
124 };
125
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800126 usart0 {
127 pinctrl_usart0: usart0-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800128 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800129 <AT91_PIOA 26 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA26 periph A with pullup */
130 AT91_PIOA 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA27 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800131 };
132
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800133 pinctrl_usart0_rts: usart0_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800134 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800135 <AT91_PIOA 28 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA28 periph A */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800136 };
137
138 pinctrl_usart0_cts: usart0_cts-0 {
139 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800140 <AT91_PIOA 29 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA29 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800141 };
142 };
143
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800144 usart1 {
145 pinctrl_usart1: usart1-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800146 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800147 <AT91_PIOD 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD0 periph A with pullup */
148 AT91_PIOD 1 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD1 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800149 };
150
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800151 pinctrl_usart1_rts: usart1_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800152 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800153 <AT91_PIOD 7 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD7 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800154 };
155
156 pinctrl_usart1_cts: usart1_cts-0 {
157 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800158 <AT91_PIOD 8 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD8 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800159 };
160 };
161
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800162 usart2 {
163 pinctrl_usart2: usart2-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800164 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800165 <AT91_PIOD 2 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PD2 periph A with pullup */
166 AT91_PIOD 3 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PD3 periph A */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800167 };
168
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800169 pinctrl_usart2_rts: usart2_rts-0 {
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800170 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800171 <AT91_PIOD 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD5 periph B */
Jean-Christophe PLAGNIOL-VILLARDc58c0c52012-11-19 07:30:01 +0800172 };
173
174 pinctrl_usart2_cts: usart2_cts-0 {
175 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800176 <AT91_PIOD 6 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PD6 periph B */
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800177 };
178 };
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800179
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800180 nand {
181 pinctrl_nand: nand-0 {
182 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800183 <AT91_PIOA 22 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP /* PA22 gpio RDY pin pull_up*/
184 AT91_PIOD 15 AT91_PERIPH_GPIO AT91_PINCTRL_PULL_UP>; /* PD15 gpio enable pin pull_up */
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800185 };
186 };
187
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800188 macb {
189 pinctrl_macb_rmii: macb_rmii-0 {
190 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800191 <AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
192 AT91_PIOE 21 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE21 periph A */
193 AT91_PIOE 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE23 periph A */
194 AT91_PIOE 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE24 periph A */
195 AT91_PIOE 25 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE25 periph A */
196 AT91_PIOE 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE26 periph A */
197 AT91_PIOE 27 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE27 periph A */
198 AT91_PIOE 28 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE28 periph A */
199 AT91_PIOE 29 AT91_PERIPH_A AT91_PINCTRL_NONE /* PE29 periph A */
200 AT91_PIOE 30 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PE30 periph A */
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800201 };
202
203 pinctrl_macb_rmii_mii: macb_rmii_mii-0 {
204 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800205 <AT91_PIOC 20 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC20 periph B */
206 AT91_PIOC 21 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC21 periph B */
207 AT91_PIOC 22 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC22 periph B */
208 AT91_PIOC 23 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC23 periph B */
209 AT91_PIOC 24 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC24 periph B */
210 AT91_PIOC 25 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC25 periph B */
211 AT91_PIOC 27 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC27 periph B */
212 AT91_PIOE 22 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PE22 periph B */
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800213 };
214 };
215
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800216 mmc0 {
217 pinctrl_mmc0_clk: mmc0_clk-0 {
218 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800219 <AT91_PIOA 12 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA12 periph A */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800220 };
221
222 pinctrl_mmc0_slot0_cmd_dat0: mmc0_slot0_cmd_dat0-0 {
223 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800224 <AT91_PIOA 1 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA1 periph A with pullup */
225 AT91_PIOA 0 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA0 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800226 };
227
228 pinctrl_mmc0_slot0_dat1_3: mmc0_slot0_dat1_3-0 {
229 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800230 <AT91_PIOA 3 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA3 periph A with pullup */
231 AT91_PIOA 4 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA4 periph A with pullup */
232 AT91_PIOA 5 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA5 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800233 };
234
235 pinctrl_mmc0_slot1_cmd_dat0: mmc0_slot1_cmd_dat0-0 {
236 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800237 <AT91_PIOA 16 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA16 periph A with pullup */
238 AT91_PIOA 17 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA17 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800239 };
240
241 pinctrl_mmc0_slot1_dat1_3: mmc0_slot1_dat1_3-0 {
242 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800243 <AT91_PIOA 18 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA18 periph A with pullup */
244 AT91_PIOA 19 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA19 periph A with pullup */
245 AT91_PIOA 20 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA20 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800246 };
247 };
248
249 mmc1 {
250 pinctrl_mmc1_clk: mmc1_clk-0 {
251 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800252 <AT91_PIOA 6 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PA6 periph A */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800253 };
254
255 pinctrl_mmc1_slot0_cmd_dat0: mmc1_slot0_cmd_dat0-0 {
256 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800257 <AT91_PIOA 7 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA7 periph A with pullup */
258 AT91_PIOA 8 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA8 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800259 };
260
261 pinctrl_mmc1_slot0_dat1_3: mmc1_slot0_dat1_3-0 {
262 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800263 <AT91_PIOA 9 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA9 periph A with pullup */
264 AT91_PIOA 10 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA10 periph A with pullup */
265 AT91_PIOA 11 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA11 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800266 };
267
268 pinctrl_mmc1_slot1_cmd_dat0: mmc1_slot1_cmd_dat0-0 {
269 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800270 <AT91_PIOA 21 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA21 periph A with pullup */
271 AT91_PIOA 22 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA22 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800272 };
273
274 pinctrl_mmc1_slot1_dat1_3: mmc1_slot1_dat1_3-0 {
275 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800276 <AT91_PIOA 23 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA23 periph A with pullup */
277 AT91_PIOA 24 AT91_PERIPH_A AT91_PINCTRL_PULL_UP /* PA24 periph A with pullup */
278 AT91_PIOA 25 AT91_PERIPH_A AT91_PINCTRL_PULL_UP>; /* PA25 periph A with pullup */
Jean-Christophe PLAGNIOL-VILLARDd4fe9ac2012-11-16 08:24:17 +0800279 };
280 };
281
Bo Shen544ae6b2013-01-11 15:08:30 +0100282 ssc0 {
283 pinctrl_ssc0_tx: ssc0_tx-0 {
284 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800285 <AT91_PIOB 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB0 periph B */
286 AT91_PIOB 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB1 periph B */
287 AT91_PIOB 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB2 periph B */
Bo Shen544ae6b2013-01-11 15:08:30 +0100288 };
289
290 pinctrl_ssc0_rx: ssc0_rx-0 {
291 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800292 <AT91_PIOB 3 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB3 periph B */
293 AT91_PIOB 4 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB4 periph B */
294 AT91_PIOB 5 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PB5 periph B */
Bo Shen544ae6b2013-01-11 15:08:30 +0100295 };
296 };
297
298 ssc1 {
299 pinctrl_ssc1_tx: ssc1_tx-0 {
300 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800301 <AT91_PIOB 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB6 periph A */
302 AT91_PIOB 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB7 periph A */
303 AT91_PIOB 8 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB8 periph A */
Bo Shen544ae6b2013-01-11 15:08:30 +0100304 };
305
306 pinctrl_ssc1_rx: ssc1_rx-0 {
307 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800308 <AT91_PIOB 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB9 periph A */
309 AT91_PIOB 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB10 periph A */
310 AT91_PIOB 11 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB11 periph A */
Bo Shen544ae6b2013-01-11 15:08:30 +0100311 };
312 };
313
Wenyou Yanga68b7282013-04-03 14:03:52 +0800314 spi0 {
315 pinctrl_spi0: spi0-0 {
316 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800317 <AT91_PIOA 0 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA0 periph B SPI0_MISO pin */
318 AT91_PIOA 1 AT91_PERIPH_B AT91_PINCTRL_NONE /* PA1 periph B SPI0_MOSI pin */
319 AT91_PIOA 2 AT91_PERIPH_B AT91_PINCTRL_NONE>; /* PA2 periph B SPI0_SPCK pin */
Wenyou Yanga68b7282013-04-03 14:03:52 +0800320 };
321 };
322
323 spi1 {
324 pinctrl_spi1: spi1-0 {
325 atmel,pins =
Jean-Christophe PLAGNIOL-VILLARDc9d0f312013-04-24 08:34:25 +0800326 <AT91_PIOB 12 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB12 periph A SPI1_MISO pin */
327 AT91_PIOB 13 AT91_PERIPH_A AT91_PINCTRL_NONE /* PB13 periph A SPI1_MOSI pin */
328 AT91_PIOB 14 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PB14 periph A SPI1_SPCK pin */
Wenyou Yanga68b7282013-04-03 14:03:52 +0800329 };
330 };
331
Boris BREZILLON028633c2013-05-24 10:05:56 +0000332 tcb0 {
333 pinctrl_tcb0_tclk0: tcb0_tclk0-0 {
334 atmel,pins = <AT91_PIOB 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
335 };
336
337 pinctrl_tcb0_tclk1: tcb0_tclk1-0 {
338 atmel,pins = <AT91_PIOC 28 AT91_PERIPH_B AT91_PINCTRL_NONE>;
339 };
340
341 pinctrl_tcb0_tclk2: tcb0_tclk2-0 {
342 atmel,pins = <AT91_PIOA 15 AT91_PERIPH_A AT91_PINCTRL_NONE>;
343 };
344
345 pinctrl_tcb0_tioa0: tcb0_tioa0-0 {
346 atmel,pins = <AT91_PIOE 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
347 };
348
349 pinctrl_tcb0_tioa1: tcb0_tioa1-0 {
350 atmel,pins = <AT91_PIOE 8 AT91_PERIPH_B AT91_PINCTRL_NONE>;
351 };
352
353 pinctrl_tcb0_tioa2: tcb0_tioa2-0 {
354 atmel,pins = <AT91_PIOB 17 AT91_PERIPH_B AT91_PINCTRL_NONE>;
355 };
356
357 pinctrl_tcb0_tiob0: tcb0_tiob0-0 {
358 atmel,pins = <AT91_PIOE 19 AT91_PERIPH_B AT91_PINCTRL_NONE>;
359 };
360
361 pinctrl_tcb0_tiob1: tcb0_tiob1-0 {
362 atmel,pins = <AT91_PIOE 9 AT91_PERIPH_B AT91_PINCTRL_NONE>;
363 };
364
365 pinctrl_tcb0_tiob2: tcb0_tiob2-0 {
366 atmel,pins = <AT91_PIOB 18 AT91_PERIPH_B AT91_PINCTRL_NONE>;
367 };
368 };
369
Jean-Christophe PLAGNIOL-VILLARDf8a0d792013-03-29 04:50:46 +0800370 fb {
371 pinctrl_fb: fb-0 {
372 atmel,pins =
373 <AT91_PIOC 1 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC1 periph A */
374 AT91_PIOC 2 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC2 periph A */
375 AT91_PIOC 3 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC3 periph A */
376 AT91_PIOB 9 AT91_PERIPH_B AT91_PINCTRL_NONE /* PB9 periph B */
377 AT91_PIOC 6 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC6 periph A */
378 AT91_PIOC 7 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC7 periph A */
379 AT91_PIOC 8 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC8 periph A */
380 AT91_PIOC 9 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC9 periph A */
381 AT91_PIOC 10 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC10 periph A */
382 AT91_PIOC 11 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC11 periph A */
383 AT91_PIOC 14 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC14 periph A */
384 AT91_PIOC 15 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC15 periph A */
385 AT91_PIOC 16 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC16 periph A */
386 AT91_PIOC 12 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC12 periph B */
387 AT91_PIOC 18 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC18 periph A */
388 AT91_PIOC 19 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC19 periph A */
389 AT91_PIOC 22 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC22 periph A */
390 AT91_PIOC 23 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC23 periph A */
391 AT91_PIOC 24 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC24 periph A */
392 AT91_PIOC 17 AT91_PERIPH_B AT91_PINCTRL_NONE /* PC17 periph B */
393 AT91_PIOC 26 AT91_PERIPH_A AT91_PINCTRL_NONE /* PC26 periph A */
394 AT91_PIOC 27 AT91_PERIPH_A AT91_PINCTRL_NONE>; /* PC27 periph A */
395 };
396 };
397
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800398 pioA: gpio@fffff200 {
399 compatible = "atmel,at91rm9200-gpio";
400 reg = <0xfffff200 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800401 interrupts = <2 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800402 #gpio-cells = <2>;
403 gpio-controller;
404 interrupt-controller;
405 #interrupt-cells = <2>;
406 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800407
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800408 pioB: gpio@fffff400 {
409 compatible = "atmel,at91rm9200-gpio";
410 reg = <0xfffff400 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800411 interrupts = <3 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800412 #gpio-cells = <2>;
413 gpio-controller;
414 interrupt-controller;
415 #interrupt-cells = <2>;
416 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800417
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800418 pioC: gpio@fffff600 {
419 compatible = "atmel,at91rm9200-gpio";
420 reg = <0xfffff600 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800421 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800422 #gpio-cells = <2>;
423 gpio-controller;
424 interrupt-controller;
425 #interrupt-cells = <2>;
426 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800427
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800428 pioD: gpio@fffff800 {
429 compatible = "atmel,at91rm9200-gpio";
430 reg = <0xfffff800 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800431 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800432 #gpio-cells = <2>;
433 gpio-controller;
434 interrupt-controller;
435 #interrupt-cells = <2>;
436 };
437
438 pioE: gpio@fffffa00 {
439 compatible = "atmel,at91rm9200-gpio";
440 reg = <0xfffffa00 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800441 interrupts = <4 IRQ_TYPE_LEVEL_HIGH 1>;
Jean-Christophe PLAGNIOL-VILLARDe4541ff2012-07-04 17:20:46 +0800442 #gpio-cells = <2>;
443 gpio-controller;
444 interrupt-controller;
445 #interrupt-cells = <2>;
Jean-Christophe PLAGNIOL-VILLARD5314ec82012-07-05 16:56:09 +0800446 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800447 };
448
449 dbgu: serial@ffffee00 {
450 compatible = "atmel,at91sam9260-usart";
451 reg = <0xffffee00 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800452 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800453 pinctrl-names = "default";
454 pinctrl-0 = <&pinctrl_dbgu>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800455 status = "disabled";
456 };
457
458 usart0: serial@fff8c000 {
459 compatible = "atmel,at91sam9260-usart";
460 reg = <0xfff8c000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800461 interrupts = <7 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800462 atmel,use-dma-rx;
463 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800464 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800465 pinctrl-0 = <&pinctrl_usart0>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800466 status = "disabled";
467 };
468
469 usart1: serial@fff90000 {
470 compatible = "atmel,at91sam9260-usart";
471 reg = <0xfff90000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800472 interrupts = <8 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800473 atmel,use-dma-rx;
474 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800475 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800476 pinctrl-0 = <&pinctrl_usart1>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800477 status = "disabled";
478 };
479
480 usart2: serial@fff94000 {
481 compatible = "atmel,at91sam9260-usart";
482 reg = <0xfff94000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800483 interrupts = <9 IRQ_TYPE_LEVEL_HIGH 5>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800484 atmel,use-dma-rx;
485 atmel,use-dma-tx;
Jean-Christophe PLAGNIOL-VILLARDec6754a2012-07-05 16:56:09 +0800486 pinctrl-names = "default";
Jean-Christophe PLAGNIOL-VILLARD9e3129e2012-11-19 06:40:01 +0800487 pinctrl-0 = <&pinctrl_usart2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800488 status = "disabled";
489 };
490
Bo Shen099343c2012-11-07 11:41:41 +0800491 ssc0: ssc@fff98000 {
492 compatible = "atmel,at91rm9200-ssc";
493 reg = <0xfff98000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800494 interrupts = <16 IRQ_TYPE_LEVEL_HIGH 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100495 pinctrl-names = "default";
496 pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
Bo Shen315656b2012-12-13 10:05:07 +0800497 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800498 };
499
500 ssc1: ssc@fff9c000 {
501 compatible = "atmel,at91rm9200-ssc";
502 reg = <0xfff9c000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800503 interrupts = <17 IRQ_TYPE_LEVEL_HIGH 5>;
Bo Shen544ae6b2013-01-11 15:08:30 +0100504 pinctrl-names = "default";
505 pinctrl-0 = <&pinctrl_ssc1_tx &pinctrl_ssc1_rx>;
Bo Shen315656b2012-12-13 10:05:07 +0800506 status = "disabled";
Bo Shen099343c2012-11-07 11:41:41 +0800507 };
508
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800509 macb0: ethernet@fffbc000 {
510 compatible = "cdns,at32ap7000-macb", "cdns,macb";
511 reg = <0xfffbc000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800512 interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
Jean-Christophe PLAGNIOL-VILLARDd9b4fe82012-10-23 10:19:11 +0800513 pinctrl-names = "default";
514 pinctrl-0 = <&pinctrl_macb_rmii>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800515 status = "disabled";
516 };
517
518 usb1: gadget@fff78000 {
519 compatible = "atmel,at91rm9200-udc";
520 reg = <0xfff78000 0x4000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800521 interrupts = <24 IRQ_TYPE_LEVEL_HIGH 2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800522 status = "disabled";
523 };
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200524
525 i2c0: i2c@fff88000 {
Jean-Jacques Hiblot821003b2014-01-15 11:24:46 +0100526 compatible = "atmel,at91sam9260-i2c";
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200527 reg = <0xfff88000 0x100>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800528 interrupts = <13 IRQ_TYPE_LEVEL_HIGH 6>;
Ludovic Desroches05dcd362012-09-12 08:42:16 +0200529 #address-cells = <1>;
530 #size-cells = <0>;
531 status = "disabled";
532 };
Ludovic Desroches98731372012-11-19 12:23:36 +0100533
534 mmc0: mmc@fff80000 {
535 compatible = "atmel,hsmci";
536 reg = <0xfff80000 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800537 interrupts = <10 IRQ_TYPE_LEVEL_HIGH 0>;
Ludovic Desroches98731372012-11-19 12:23:36 +0100538 #address-cells = <1>;
539 #size-cells = <0>;
540 status = "disabled";
541 };
542
543 mmc1: mmc@fff84000 {
544 compatible = "atmel,hsmci";
545 reg = <0xfff84000 0x600>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800546 interrupts = <11 IRQ_TYPE_LEVEL_HIGH 0>;
Ludovic Desroches98731372012-11-19 12:23:36 +0100547 #address-cells = <1>;
548 #size-cells = <0>;
549 status = "disabled";
550 };
Linus Torvaldsdb5b0ae2012-12-13 10:39:26 -0800551
Fabio Porcedda7492e7c2012-11-12 09:37:26 +0100552 watchdog@fffffd40 {
553 compatible = "atmel,at91sam9260-wdt";
554 reg = <0xfffffd40 0x10>;
Boris BREZILLONfe46aa62013-10-04 09:24:14 +0200555 interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
556 atmel,watchdog-type = "hardware";
557 atmel,reset-type = "all";
558 atmel,dbg-halt;
559 atmel,idle-halt;
Fabio Porcedda7492e7c2012-11-12 09:37:26 +0100560 status = "disabled";
561 };
Richard Genoudd50f88a2013-04-03 14:02:18 +0800562
563 spi0: spi@fffa4000 {
564 #address-cells = <1>;
565 #size-cells = <0>;
566 compatible = "atmel,at91rm9200-spi";
567 reg = <0xfffa4000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800568 interrupts = <14 IRQ_TYPE_LEVEL_HIGH 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800569 pinctrl-names = "default";
570 pinctrl-0 = <&pinctrl_spi0>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800571 status = "disabled";
572 };
573
574 spi1: spi@fffa8000 {
575 #address-cells = <1>;
576 #size-cells = <0>;
577 compatible = "atmel,at91rm9200-spi";
578 reg = <0xfffa8000 0x200>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800579 interrupts = <15 IRQ_TYPE_LEVEL_HIGH 3>;
Wenyou Yanga68b7282013-04-03 14:03:52 +0800580 pinctrl-names = "default";
581 pinctrl-0 = <&pinctrl_spi1>;
Richard Genoudd50f88a2013-04-03 14:02:18 +0800582 status = "disabled";
583 };
Bo Shenf3ab0522013-12-19 11:59:17 +0800584
585 pwm0: pwm@fffb8000 {
586 compatible = "atmel,at91sam9rl-pwm";
587 reg = <0xfffb8000 0x300>;
588 interrupts = <20 IRQ_TYPE_LEVEL_HIGH 4>;
589 #pwm-cells = <3>;
590 status = "disabled";
591 };
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800592 };
593
Jean-Christophe PLAGNIOL-VILLARDf8a0d792013-03-29 04:50:46 +0800594 fb0: fb@0x00700000 {
595 compatible = "atmel,at91sam9263-lcdc";
596 reg = <0x00700000 0x1000>;
597 interrupts = <26 IRQ_TYPE_LEVEL_HIGH 3>;
598 pinctrl-names = "default";
599 pinctrl-0 = <&pinctrl_fb>;
600 status = "disabled";
601 };
602
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800603 nand0: nand@40000000 {
604 compatible = "atmel,at91rm9200-nand";
605 #address-cells = <1>;
606 #size-cells = <1>;
607 reg = <0x40000000 0x10000000
608 0xffffe000 0x200
609 >;
610 atmel,nand-addr-offset = <21>;
611 atmel,nand-cmd-offset = <22>;
Jean-Christophe PLAGNIOL-VILLARD7a38d452012-07-12 23:36:52 +0800612 pinctrl-names = "default";
613 pinctrl-0 = <&pinctrl_nand>;
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800614 gpios = <&pioA 22 GPIO_ACTIVE_HIGH
615 &pioD 15 GPIO_ACTIVE_HIGH
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800616 0
617 >;
618 status = "disabled";
619 };
620
621 usb0: ohci@00a00000 {
622 compatible = "atmel,at91rm9200-ohci", "usb-ohci";
623 reg = <0x00a00000 0x100000>;
Jean-Christophe PLAGNIOL-VILLARD5e8b3bc2013-04-24 08:34:25 +0800624 interrupts = <29 IRQ_TYPE_LEVEL_HIGH 2>;
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800625 status = "disabled";
626 };
627 };
628
629 i2c@0 {
630 compatible = "i2c-gpio";
Jean-Christophe PLAGNIOL-VILLARD92f86292013-04-24 08:34:25 +0800631 gpios = <&pioB 4 GPIO_ACTIVE_HIGH /* sda */
632 &pioB 5 GPIO_ACTIVE_HIGH /* scl */
Jean-Christophe PLAGNIOL-VILLARD4abb3672012-02-26 19:12:43 +0800633 >;
634 i2c-gpio,sda-open-drain;
635 i2c-gpio,scl-open-drain;
636 i2c-gpio,delay-us = <2>; /* ~100 kHz */
637 #address-cells = <1>;
638 #size-cells = <0>;
639 status = "disabled";
640 };
641};