blob: 01d841ea3140f701cdd1cef414ad20cbf8de6ee2 [file] [log] [blame]
Jani Nikula59de0812013-05-22 15:36:16 +03001/*
2 * Copyright © 2013 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 */
24
25#include "i915_drv.h"
26#include "intel_drv.h"
27
Jesse Barnesd8228d02013-10-11 12:09:30 -070028/*
29 * IOSF sideband, see VLV2_SidebandMsg_HAS.docx and
30 * VLV_VLV2_PUNIT_HAS_0.8.docx
31 */
Imre Deakcf63e4a2014-05-19 11:41:17 +030032
33/* Standard MMIO read, non-posted */
34#define SB_MRD_NP 0x00
35/* Standard MMIO write, non-posted */
36#define SB_MWR_NP 0x01
37/* Private register read, double-word addressing, non-posted */
38#define SB_CRRDDA_NP 0x06
39/* Private register write, double-word addressing, non-posted */
40#define SB_CRWRDA_NP 0x07
41
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030042static int vlv_sideband_rw(struct drm_i915_private *dev_priv, u32 devfn,
43 u32 port, u32 opcode, u32 addr, u32 *val)
Jani Nikula59de0812013-05-22 15:36:16 +030044{
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030045 u32 cmd, be = 0xf, bar = 0;
Imre Deakcf63e4a2014-05-19 11:41:17 +030046 bool is_read = (opcode == SB_MRD_NP || opcode == SB_CRRDDA_NP);
Jani Nikula59de0812013-05-22 15:36:16 +030047
48 cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
49 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
50 (bar << IOSF_BAR_SHIFT);
51
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030052 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
Jani Nikula59de0812013-05-22 15:36:16 +030053
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030054 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
55 DRM_DEBUG_DRIVER("IOSF sideband idle wait (%s) timed out\n",
56 is_read ? "read" : "write");
Jani Nikula59de0812013-05-22 15:36:16 +030057 return -EAGAIN;
58 }
59
60 I915_WRITE(VLV_IOSF_ADDR, addr);
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030061 if (!is_read)
Jani Nikula59de0812013-05-22 15:36:16 +030062 I915_WRITE(VLV_IOSF_DATA, *val);
63 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
64
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030065 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0, 5)) {
66 DRM_DEBUG_DRIVER("IOSF sideband finish wait (%s) timed out\n",
67 is_read ? "read" : "write");
Jani Nikula59de0812013-05-22 15:36:16 +030068 return -ETIMEDOUT;
69 }
70
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030071 if (is_read)
Jani Nikula59de0812013-05-22 15:36:16 +030072 *val = I915_READ(VLV_IOSF_DATA);
73 I915_WRITE(VLV_IOSF_DATA, 0);
74
75 return 0;
76}
77
Jani Nikula64936252013-05-22 15:36:20 +030078u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr)
Jani Nikula59de0812013-05-22 15:36:16 +030079{
Jani Nikula64936252013-05-22 15:36:20 +030080 u32 val = 0;
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030081
82 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
83
84 mutex_lock(&dev_priv->dpio_lock);
Jani Nikula64936252013-05-22 15:36:20 +030085 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
Imre Deakcf63e4a2014-05-19 11:41:17 +030086 SB_CRRDDA_NP, addr, &val);
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030087 mutex_unlock(&dev_priv->dpio_lock);
88
Jani Nikula64936252013-05-22 15:36:20 +030089 return val;
Jani Nikula59de0812013-05-22 15:36:16 +030090}
91
Jani Nikula64936252013-05-22 15:36:20 +030092void vlv_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
Jani Nikula59de0812013-05-22 15:36:16 +030093{
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030094 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
95
96 mutex_lock(&dev_priv->dpio_lock);
Jani Nikula64936252013-05-22 15:36:20 +030097 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_PUNIT,
Imre Deakcf63e4a2014-05-19 11:41:17 +030098 SB_CRWRDA_NP, addr, &val);
Jani Nikula5a09ae9f2013-05-22 15:36:17 +030099 mutex_unlock(&dev_priv->dpio_lock);
Jani Nikula59de0812013-05-22 15:36:16 +0300100}
101
Jesse Barnesf3419152013-11-04 11:52:44 -0800102u32 vlv_bunit_read(struct drm_i915_private *dev_priv, u32 reg)
103{
104 u32 val = 0;
105
106 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300107 SB_CRRDDA_NP, reg, &val);
Jesse Barnesf3419152013-11-04 11:52:44 -0800108
109 return val;
110}
111
112void vlv_bunit_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
113{
114 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_BUNIT,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300115 SB_CRWRDA_NP, reg, &val);
Jesse Barnesf3419152013-11-04 11:52:44 -0800116}
117
Jani Nikula64936252013-05-22 15:36:20 +0300118u32 vlv_nc_read(struct drm_i915_private *dev_priv, u8 addr)
Jani Nikula59de0812013-05-22 15:36:16 +0300119{
Jani Nikula64936252013-05-22 15:36:20 +0300120 u32 val = 0;
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300121
122 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
123
124 mutex_lock(&dev_priv->dpio_lock);
Jani Nikula64936252013-05-22 15:36:20 +0300125 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_NC,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300126 SB_CRRDDA_NP, addr, &val);
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300127 mutex_unlock(&dev_priv->dpio_lock);
128
Jani Nikula64936252013-05-22 15:36:20 +0300129 return val;
Jani Nikula59de0812013-05-22 15:36:16 +0300130}
131
Jani Nikulae9f882a2013-08-27 15:12:14 +0300132u32 vlv_gpio_nc_read(struct drm_i915_private *dev_priv, u32 reg)
133{
134 u32 val = 0;
135 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300136 SB_CRRDDA_NP, reg, &val);
Jani Nikulae9f882a2013-08-27 15:12:14 +0300137 return val;
138}
139
140void vlv_gpio_nc_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
141{
142 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPIO_NC,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300143 SB_CRWRDA_NP, reg, &val);
Jani Nikulae9f882a2013-08-27 15:12:14 +0300144}
145
146u32 vlv_cck_read(struct drm_i915_private *dev_priv, u32 reg)
147{
148 u32 val = 0;
149 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300150 SB_CRRDDA_NP, reg, &val);
Jani Nikulae9f882a2013-08-27 15:12:14 +0300151 return val;
152}
153
154void vlv_cck_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
155{
156 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCK,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300157 SB_CRWRDA_NP, reg, &val);
Jani Nikulae9f882a2013-08-27 15:12:14 +0300158}
159
160u32 vlv_ccu_read(struct drm_i915_private *dev_priv, u32 reg)
161{
162 u32 val = 0;
163 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300164 SB_CRRDDA_NP, reg, &val);
Jani Nikulae9f882a2013-08-27 15:12:14 +0300165 return val;
166}
167
168void vlv_ccu_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
169{
170 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_CCU,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300171 SB_CRWRDA_NP, reg, &val);
Jani Nikulae9f882a2013-08-27 15:12:14 +0300172}
173
174u32 vlv_gps_core_read(struct drm_i915_private *dev_priv, u32 reg)
175{
176 u32 val = 0;
177 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300178 SB_CRRDDA_NP, reg, &val);
Jani Nikulae9f882a2013-08-27 15:12:14 +0300179 return val;
180}
181
182void vlv_gps_core_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
183{
184 vlv_sideband_rw(dev_priv, PCI_DEVFN(2, 0), IOSF_PORT_GPS_CORE,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300185 SB_CRWRDA_NP, reg, &val);
Jani Nikulae9f882a2013-08-27 15:12:14 +0300186}
187
Chon Ming Lee5e69f972013-09-05 20:41:49 +0800188u32 vlv_dpio_read(struct drm_i915_private *dev_priv, enum pipe pipe, int reg)
Jani Nikula59de0812013-05-22 15:36:16 +0300189{
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300190 u32 val = 0;
Jani Nikula59de0812013-05-22 15:36:16 +0300191
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800192 vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
Imre Deakcf63e4a2014-05-19 11:41:17 +0300193 SB_MRD_NP, reg, &val);
Ville Syrjälä0d95e112014-03-31 18:21:27 +0300194
195 /*
196 * FIXME: There might be some registers where all 1's is a valid value,
197 * so ideally we should check the register offset instead...
198 */
199 WARN(val == 0xffffffff, "DPIO read pipe %c reg 0x%x == 0x%x\n",
200 pipe_name(pipe), reg, val);
201
Jani Nikula5a09ae9f2013-05-22 15:36:17 +0300202 return val;
Jani Nikula59de0812013-05-22 15:36:16 +0300203}
204
Chon Ming Lee5e69f972013-09-05 20:41:49 +0800205void vlv_dpio_write(struct drm_i915_private *dev_priv, enum pipe pipe, int reg, u32 val)
Jani Nikula59de0812013-05-22 15:36:16 +0300206{
Chon Ming Leee4607fc2013-11-06 14:36:35 +0800207 vlv_sideband_rw(dev_priv, DPIO_DEVFN, DPIO_PHY_IOSF_PORT(DPIO_PHY(pipe)),
Imre Deakcf63e4a2014-05-19 11:41:17 +0300208 SB_MWR_NP, reg, &val);
Jani Nikula59de0812013-05-22 15:36:16 +0300209}
210
211/* SBI access */
212u32 intel_sbi_read(struct drm_i915_private *dev_priv, u16 reg,
213 enum intel_sbi_destination destination)
214{
215 u32 value = 0;
216 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
217
218 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
219 100)) {
220 DRM_ERROR("timeout waiting for SBI to become ready\n");
221 return 0;
222 }
223
224 I915_WRITE(SBI_ADDR, (reg << 16));
225
226 if (destination == SBI_ICLK)
227 value = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRRD;
228 else
229 value = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IORD;
230 I915_WRITE(SBI_CTL_STAT, value | SBI_BUSY);
231
232 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
233 100)) {
234 DRM_ERROR("timeout waiting for SBI to complete read transaction\n");
235 return 0;
236 }
237
238 return I915_READ(SBI_DATA);
239}
240
241void intel_sbi_write(struct drm_i915_private *dev_priv, u16 reg, u32 value,
242 enum intel_sbi_destination destination)
243{
244 u32 tmp;
245
246 WARN_ON(!mutex_is_locked(&dev_priv->dpio_lock));
247
248 if (wait_for((I915_READ(SBI_CTL_STAT) & SBI_BUSY) == 0,
249 100)) {
250 DRM_ERROR("timeout waiting for SBI to become ready\n");
251 return;
252 }
253
254 I915_WRITE(SBI_ADDR, (reg << 16));
255 I915_WRITE(SBI_DATA, value);
256
257 if (destination == SBI_ICLK)
258 tmp = SBI_CTL_DEST_ICLK | SBI_CTL_OP_CRWR;
259 else
260 tmp = SBI_CTL_DEST_MPHY | SBI_CTL_OP_IOWR;
261 I915_WRITE(SBI_CTL_STAT, SBI_BUSY | tmp);
262
263 if (wait_for((I915_READ(SBI_CTL_STAT) & (SBI_BUSY | SBI_RESPONSE_FAIL)) == 0,
264 100)) {
265 DRM_ERROR("timeout waiting for SBI to complete write transaction\n");
266 return;
267 }
268}
Shobhit Kumare9fe51c2013-12-10 12:14:55 +0530269
270u32 vlv_flisdsi_read(struct drm_i915_private *dev_priv, u32 reg)
271{
272 u32 val = 0;
Imre Deak42a88e92014-05-19 11:41:18 +0300273 vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRRDDA_NP,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300274 reg, &val);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +0530275 return val;
276}
277
278void vlv_flisdsi_write(struct drm_i915_private *dev_priv, u32 reg, u32 val)
279{
Imre Deak42a88e92014-05-19 11:41:18 +0300280 vlv_sideband_rw(dev_priv, DPIO_DEVFN, IOSF_PORT_FLISDSI, SB_CRWRDA_NP,
Imre Deakcf63e4a2014-05-19 11:41:17 +0300281 reg, &val);
Shobhit Kumare9fe51c2013-12-10 12:14:55 +0530282}