Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Hardware modules present on the OMAP44xx chips |
| 3 | * |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 4 | * Copyright (C) 2009-2012 Texas Instruments, Inc. |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 5 | * Copyright (C) 2009-2010 Nokia Corporation |
| 6 | * |
| 7 | * Paul Walmsley |
| 8 | * Benoit Cousson |
| 9 | * |
| 10 | * This file is automatically generated from the OMAP hardware databases. |
| 11 | * We respectfully ask that any modifications to this file be coordinated |
| 12 | * with the public linux-omap@vger.kernel.org mailing list and the |
| 13 | * authors above to ensure that the autogeneration scripts are kept |
| 14 | * up-to-date with the file contents. |
| 15 | * |
| 16 | * This program is free software; you can redistribute it and/or modify |
| 17 | * it under the terms of the GNU General Public License version 2 as |
| 18 | * published by the Free Software Foundation. |
| 19 | */ |
| 20 | |
| 21 | #include <linux/io.h> |
| 22 | |
| 23 | #include <plat/omap_hwmod.h> |
| 24 | #include <plat/cpu.h> |
Avinash.H.M | 6d3c55f | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 25 | #include <plat/i2c.h> |
Benoit Cousson | 9780a9c | 2010-12-07 16:26:57 -0800 | [diff] [blame] | 26 | #include <plat/gpio.h> |
Benoit Cousson | 531ce0d | 2010-12-20 18:27:19 -0800 | [diff] [blame] | 27 | #include <plat/dma.h> |
Benoit Cousson | 905a74d | 2011-02-18 14:01:06 +0100 | [diff] [blame] | 28 | #include <plat/mcspi.h> |
Kishon Vijay Abraham I | cb7e9de | 2011-02-24 15:16:50 +0530 | [diff] [blame] | 29 | #include <plat/mcbsp.h> |
Kishore Kadiyala | 6ab8946 | 2011-03-01 13:12:56 -0800 | [diff] [blame] | 30 | #include <plat/mmc.h> |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 31 | #include <plat/dmtimer.h> |
Tomi Valkeinen | 13662dc | 2011-11-08 03:16:13 -0700 | [diff] [blame] | 32 | #include <plat/common.h> |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 33 | |
| 34 | #include "omap_hwmod_common_data.h" |
| 35 | |
Shweta Gulati | cea6b94 | 2012-02-29 23:33:37 +0100 | [diff] [blame] | 36 | #include "smartreflex.h" |
Paul Walmsley | d198b51 | 2010-12-21 15:30:54 -0700 | [diff] [blame] | 37 | #include "cm1_44xx.h" |
| 38 | #include "cm2_44xx.h" |
| 39 | #include "prm44xx.h" |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 40 | #include "prm-regbits-44xx.h" |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 41 | #include "wd_timer.h" |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 42 | |
| 43 | /* Base offset for all OMAP4 interrupts external to MPUSS */ |
| 44 | #define OMAP44XX_IRQ_GIC_START 32 |
| 45 | |
| 46 | /* Base offset for all OMAP4 dma requests */ |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 47 | #define OMAP44XX_DMA_REQ_START 1 |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 48 | |
| 49 | /* |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 50 | * IP blocks |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 51 | */ |
| 52 | |
| 53 | /* |
| 54 | * 'dmm' class |
| 55 | * instance(s): dmm |
| 56 | */ |
| 57 | static struct omap_hwmod_class omap44xx_dmm_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 58 | .name = "dmm", |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 59 | }; |
| 60 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 61 | /* dmm */ |
| 62 | static struct omap_hwmod_irq_info omap44xx_dmm_irqs[] = { |
| 63 | { .irq = 113 + OMAP44XX_IRQ_GIC_START }, |
| 64 | { .irq = -1 } |
| 65 | }; |
| 66 | |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 67 | static struct omap_hwmod omap44xx_dmm_hwmod = { |
| 68 | .name = "dmm", |
| 69 | .class = &omap44xx_dmm_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 70 | .clkdm_name = "l3_emif_clkdm", |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 71 | .mpu_irqs = omap44xx_dmm_irqs, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 72 | .prcm = { |
| 73 | .omap4 = { |
| 74 | .clkctrl_offs = OMAP4_CM_MEMIF_DMM_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 75 | .context_offs = OMAP4_RM_MEMIF_DMM_CONTEXT_OFFSET, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 76 | }, |
| 77 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 78 | }; |
| 79 | |
| 80 | /* |
| 81 | * 'emif_fw' class |
| 82 | * instance(s): emif_fw |
| 83 | */ |
| 84 | static struct omap_hwmod_class omap44xx_emif_fw_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 85 | .name = "emif_fw", |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 86 | }; |
| 87 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 88 | /* emif_fw */ |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 89 | static struct omap_hwmod omap44xx_emif_fw_hwmod = { |
| 90 | .name = "emif_fw", |
| 91 | .class = &omap44xx_emif_fw_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 92 | .clkdm_name = "l3_emif_clkdm", |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 93 | .prcm = { |
| 94 | .omap4 = { |
| 95 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_FW_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 96 | .context_offs = OMAP4_RM_MEMIF_EMIF_FW_CONTEXT_OFFSET, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 97 | }, |
| 98 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 99 | }; |
| 100 | |
| 101 | /* |
| 102 | * 'l3' class |
| 103 | * instance(s): l3_instr, l3_main_1, l3_main_2, l3_main_3 |
| 104 | */ |
| 105 | static struct omap_hwmod_class omap44xx_l3_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 106 | .name = "l3", |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 107 | }; |
| 108 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 109 | /* l3_instr */ |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 110 | static struct omap_hwmod omap44xx_l3_instr_hwmod = { |
| 111 | .name = "l3_instr", |
| 112 | .class = &omap44xx_l3_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 113 | .clkdm_name = "l3_instr_clkdm", |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 114 | .prcm = { |
| 115 | .omap4 = { |
| 116 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_INSTR_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 117 | .context_offs = OMAP4_RM_L3INSTR_L3_INSTR_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 118 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 119 | }, |
| 120 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 121 | }; |
| 122 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 123 | /* l3_main_1 */ |
Benoit Cousson | 9b4021b | 2011-07-09 19:14:27 -0600 | [diff] [blame] | 124 | static struct omap_hwmod_irq_info omap44xx_l3_main_1_irqs[] = { |
| 125 | { .name = "dbg_err", .irq = 9 + OMAP44XX_IRQ_GIC_START }, |
| 126 | { .name = "app_err", .irq = 10 + OMAP44XX_IRQ_GIC_START }, |
| 127 | { .irq = -1 } |
| 128 | }; |
| 129 | |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 130 | static struct omap_hwmod omap44xx_l3_main_1_hwmod = { |
| 131 | .name = "l3_main_1", |
| 132 | .class = &omap44xx_l3_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 133 | .clkdm_name = "l3_1_clkdm", |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 134 | .mpu_irqs = omap44xx_l3_main_1_irqs, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 135 | .prcm = { |
| 136 | .omap4 = { |
| 137 | .clkctrl_offs = OMAP4_CM_L3_1_L3_1_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 138 | .context_offs = OMAP4_RM_L3_1_L3_1_CONTEXT_OFFSET, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 139 | }, |
| 140 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 141 | }; |
| 142 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 143 | /* l3_main_2 */ |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 144 | static struct omap_hwmod omap44xx_l3_main_2_hwmod = { |
| 145 | .name = "l3_main_2", |
| 146 | .class = &omap44xx_l3_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 147 | .clkdm_name = "l3_2_clkdm", |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 148 | .prcm = { |
| 149 | .omap4 = { |
| 150 | .clkctrl_offs = OMAP4_CM_L3_2_L3_2_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 151 | .context_offs = OMAP4_RM_L3_2_L3_2_CONTEXT_OFFSET, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 152 | }, |
| 153 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 154 | }; |
| 155 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 156 | /* l3_main_3 */ |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 157 | static struct omap_hwmod omap44xx_l3_main_3_hwmod = { |
| 158 | .name = "l3_main_3", |
| 159 | .class = &omap44xx_l3_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 160 | .clkdm_name = "l3_instr_clkdm", |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 161 | .prcm = { |
| 162 | .omap4 = { |
| 163 | .clkctrl_offs = OMAP4_CM_L3INSTR_L3_3_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 164 | .context_offs = OMAP4_RM_L3INSTR_L3_3_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 165 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 166 | }, |
| 167 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 168 | }; |
| 169 | |
| 170 | /* |
| 171 | * 'l4' class |
| 172 | * instance(s): l4_abe, l4_cfg, l4_per, l4_wkup |
| 173 | */ |
| 174 | static struct omap_hwmod_class omap44xx_l4_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 175 | .name = "l4", |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 176 | }; |
| 177 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 178 | /* l4_abe */ |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 179 | static struct omap_hwmod omap44xx_l4_abe_hwmod = { |
| 180 | .name = "l4_abe", |
| 181 | .class = &omap44xx_l4_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 182 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 183 | .prcm = { |
| 184 | .omap4 = { |
| 185 | .clkctrl_offs = OMAP4_CM1_ABE_L4ABE_CLKCTRL_OFFSET, |
| 186 | }, |
| 187 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 188 | }; |
| 189 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 190 | /* l4_cfg */ |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 191 | static struct omap_hwmod omap44xx_l4_cfg_hwmod = { |
| 192 | .name = "l4_cfg", |
| 193 | .class = &omap44xx_l4_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 194 | .clkdm_name = "l4_cfg_clkdm", |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 195 | .prcm = { |
| 196 | .omap4 = { |
| 197 | .clkctrl_offs = OMAP4_CM_L4CFG_L4_CFG_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 198 | .context_offs = OMAP4_RM_L4CFG_L4_CFG_CONTEXT_OFFSET, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 199 | }, |
| 200 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 201 | }; |
| 202 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 203 | /* l4_per */ |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 204 | static struct omap_hwmod omap44xx_l4_per_hwmod = { |
| 205 | .name = "l4_per", |
| 206 | .class = &omap44xx_l4_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 207 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 208 | .prcm = { |
| 209 | .omap4 = { |
| 210 | .clkctrl_offs = OMAP4_CM_L4PER_L4PER_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 211 | .context_offs = OMAP4_RM_L4PER_L4_PER_CONTEXT_OFFSET, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 212 | }, |
| 213 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 214 | }; |
| 215 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 216 | /* l4_wkup */ |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 217 | static struct omap_hwmod omap44xx_l4_wkup_hwmod = { |
| 218 | .name = "l4_wkup", |
| 219 | .class = &omap44xx_l4_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 220 | .clkdm_name = "l4_wkup_clkdm", |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 221 | .prcm = { |
| 222 | .omap4 = { |
| 223 | .clkctrl_offs = OMAP4_CM_WKUP_L4WKUP_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 224 | .context_offs = OMAP4_RM_WKUP_L4WKUP_CONTEXT_OFFSET, |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 225 | }, |
| 226 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 227 | }; |
| 228 | |
| 229 | /* |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 230 | * 'mpu_bus' class |
| 231 | * instance(s): mpu_private |
| 232 | */ |
| 233 | static struct omap_hwmod_class omap44xx_mpu_bus_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 234 | .name = "mpu_bus", |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 235 | }; |
| 236 | |
Benoit Cousson | 7e69ed9 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 237 | /* mpu_private */ |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 238 | static struct omap_hwmod omap44xx_mpu_private_hwmod = { |
| 239 | .name = "mpu_private", |
| 240 | .class = &omap44xx_mpu_bus_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 241 | .clkdm_name = "mpuss_clkdm", |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 242 | }; |
| 243 | |
| 244 | /* |
| 245 | * Modules omap_hwmod structures |
| 246 | * |
| 247 | * The following IPs are excluded for the moment because: |
| 248 | * - They do not need an explicit SW control using omap_hwmod API. |
| 249 | * - They still need to be validated with the driver |
| 250 | * properly adapted to omap_hwmod / omap_device |
| 251 | * |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 252 | * c2c |
| 253 | * c2c_target_fw |
| 254 | * cm_core |
| 255 | * cm_core_aon |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 256 | * ctrl_module_core |
| 257 | * ctrl_module_pad_core |
| 258 | * ctrl_module_pad_wkup |
| 259 | * ctrl_module_wkup |
| 260 | * debugss |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 261 | * efuse_ctrl_cust |
| 262 | * efuse_ctrl_std |
| 263 | * elm |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 264 | * mcasp |
| 265 | * mpu_c0 |
| 266 | * mpu_c1 |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 267 | * ocmc_ram |
| 268 | * ocp2scp_usb_phy |
| 269 | * ocp_wp_noc |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 270 | * prcm_mpu |
| 271 | * prm |
| 272 | * scrm |
| 273 | * sl2if |
| 274 | * slimbus1 |
| 275 | * slimbus2 |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 276 | * usb_host_fs |
| 277 | * usb_host_hs |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 278 | * usb_phy_cm |
| 279 | * usb_tll_hs |
| 280 | * usim |
| 281 | */ |
| 282 | |
| 283 | /* |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 284 | * 'aess' class |
| 285 | * audio engine sub system |
| 286 | */ |
| 287 | |
| 288 | static struct omap_hwmod_class_sysconfig omap44xx_aess_sysc = { |
| 289 | .rev_offs = 0x0000, |
| 290 | .sysc_offs = 0x0010, |
| 291 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), |
| 292 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
Benoit Cousson | c614ebf | 2011-07-01 22:54:01 +0200 | [diff] [blame] | 293 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART | |
| 294 | MSTANDBY_SMART_WKUP), |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 295 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 296 | }; |
| 297 | |
| 298 | static struct omap_hwmod_class omap44xx_aess_hwmod_class = { |
| 299 | .name = "aess", |
| 300 | .sysc = &omap44xx_aess_sysc, |
| 301 | }; |
| 302 | |
| 303 | /* aess */ |
| 304 | static struct omap_hwmod_irq_info omap44xx_aess_irqs[] = { |
| 305 | { .irq = 99 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 306 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 307 | }; |
| 308 | |
| 309 | static struct omap_hwmod_dma_info omap44xx_aess_sdma_reqs[] = { |
| 310 | { .name = "fifo0", .dma_req = 100 + OMAP44XX_DMA_REQ_START }, |
| 311 | { .name = "fifo1", .dma_req = 101 + OMAP44XX_DMA_REQ_START }, |
| 312 | { .name = "fifo2", .dma_req = 102 + OMAP44XX_DMA_REQ_START }, |
| 313 | { .name = "fifo3", .dma_req = 103 + OMAP44XX_DMA_REQ_START }, |
| 314 | { .name = "fifo4", .dma_req = 104 + OMAP44XX_DMA_REQ_START }, |
| 315 | { .name = "fifo5", .dma_req = 105 + OMAP44XX_DMA_REQ_START }, |
| 316 | { .name = "fifo6", .dma_req = 106 + OMAP44XX_DMA_REQ_START }, |
| 317 | { .name = "fifo7", .dma_req = 107 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 318 | { .dma_req = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 319 | }; |
| 320 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 321 | static struct omap_hwmod omap44xx_aess_hwmod = { |
| 322 | .name = "aess", |
| 323 | .class = &omap44xx_aess_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 324 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 325 | .mpu_irqs = omap44xx_aess_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 326 | .sdma_reqs = omap44xx_aess_sdma_reqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 327 | .main_clk = "aess_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 328 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 329 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 330 | .clkctrl_offs = OMAP4_CM1_ABE_AESS_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 331 | .context_offs = OMAP4_RM_ABE_AESS_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 332 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 333 | }, |
| 334 | }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 335 | }; |
| 336 | |
| 337 | /* |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 338 | * 'counter' class |
| 339 | * 32-bit ordinary counter, clocked by the falling edge of the 32 khz clock |
| 340 | */ |
| 341 | |
| 342 | static struct omap_hwmod_class_sysconfig omap44xx_counter_sysc = { |
| 343 | .rev_offs = 0x0000, |
| 344 | .sysc_offs = 0x0004, |
| 345 | .sysc_flags = SYSC_HAS_SIDLEMODE, |
| 346 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 347 | SIDLE_SMART_WKUP), |
| 348 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 349 | }; |
| 350 | |
| 351 | static struct omap_hwmod_class omap44xx_counter_hwmod_class = { |
| 352 | .name = "counter", |
| 353 | .sysc = &omap44xx_counter_sysc, |
| 354 | }; |
| 355 | |
| 356 | /* counter_32k */ |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 357 | static struct omap_hwmod omap44xx_counter_32k_hwmod = { |
| 358 | .name = "counter_32k", |
| 359 | .class = &omap44xx_counter_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 360 | .clkdm_name = "l4_wkup_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 361 | .flags = HWMOD_SWSUP_SIDLE, |
| 362 | .main_clk = "sys_32k_ck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 363 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 364 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 365 | .clkctrl_offs = OMAP4_CM_WKUP_SYNCTIMER_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 366 | .context_offs = OMAP4_RM_WKUP_SYNCTIMER_CONTEXT_OFFSET, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 367 | }, |
| 368 | }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 369 | }; |
| 370 | |
| 371 | /* |
Benoit Cousson | d7cf5f3 | 2010-12-23 22:30:31 +0000 | [diff] [blame] | 372 | * 'dma' class |
| 373 | * dma controller for data exchange between memory to memory (i.e. internal or |
| 374 | * external memory) and gp peripherals to memory or memory to gp peripherals |
| 375 | */ |
| 376 | |
| 377 | static struct omap_hwmod_class_sysconfig omap44xx_dma_sysc = { |
| 378 | .rev_offs = 0x0000, |
| 379 | .sysc_offs = 0x002c, |
| 380 | .syss_offs = 0x0028, |
| 381 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | |
| 382 | SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | |
| 383 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 384 | SYSS_HAS_RESET_STATUS), |
| 385 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 386 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 387 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 388 | }; |
| 389 | |
| 390 | static struct omap_hwmod_class omap44xx_dma_hwmod_class = { |
| 391 | .name = "dma", |
| 392 | .sysc = &omap44xx_dma_sysc, |
| 393 | }; |
| 394 | |
| 395 | /* dma dev_attr */ |
| 396 | static struct omap_dma_dev_attr dma_dev_attr = { |
| 397 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | |
| 398 | IS_CSSA_32 | IS_CDSA_32 | IS_RW_PRIORITY, |
| 399 | .lch_count = 32, |
| 400 | }; |
| 401 | |
| 402 | /* dma_system */ |
| 403 | static struct omap_hwmod_irq_info omap44xx_dma_system_irqs[] = { |
| 404 | { .name = "0", .irq = 12 + OMAP44XX_IRQ_GIC_START }, |
| 405 | { .name = "1", .irq = 13 + OMAP44XX_IRQ_GIC_START }, |
| 406 | { .name = "2", .irq = 14 + OMAP44XX_IRQ_GIC_START }, |
| 407 | { .name = "3", .irq = 15 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 408 | { .irq = -1 } |
Benoit Cousson | d7cf5f3 | 2010-12-23 22:30:31 +0000 | [diff] [blame] | 409 | }; |
| 410 | |
Benoit Cousson | d7cf5f3 | 2010-12-23 22:30:31 +0000 | [diff] [blame] | 411 | static struct omap_hwmod omap44xx_dma_system_hwmod = { |
| 412 | .name = "dma_system", |
| 413 | .class = &omap44xx_dma_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 414 | .clkdm_name = "l3_dma_clkdm", |
Benoit Cousson | d7cf5f3 | 2010-12-23 22:30:31 +0000 | [diff] [blame] | 415 | .mpu_irqs = omap44xx_dma_system_irqs, |
Benoit Cousson | d7cf5f3 | 2010-12-23 22:30:31 +0000 | [diff] [blame] | 416 | .main_clk = "l3_div_ck", |
| 417 | .prcm = { |
| 418 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 419 | .clkctrl_offs = OMAP4_CM_SDMA_SDMA_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 420 | .context_offs = OMAP4_RM_SDMA_SDMA_CONTEXT_OFFSET, |
Benoit Cousson | d7cf5f3 | 2010-12-23 22:30:31 +0000 | [diff] [blame] | 421 | }, |
| 422 | }, |
| 423 | .dev_attr = &dma_dev_attr, |
Benoit Cousson | d7cf5f3 | 2010-12-23 22:30:31 +0000 | [diff] [blame] | 424 | }; |
| 425 | |
| 426 | /* |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 427 | * 'dmic' class |
| 428 | * digital microphone controller |
| 429 | */ |
| 430 | |
| 431 | static struct omap_hwmod_class_sysconfig omap44xx_dmic_sysc = { |
| 432 | .rev_offs = 0x0000, |
| 433 | .sysc_offs = 0x0010, |
| 434 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | |
| 435 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), |
| 436 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 437 | SIDLE_SMART_WKUP), |
| 438 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 439 | }; |
| 440 | |
| 441 | static struct omap_hwmod_class omap44xx_dmic_hwmod_class = { |
| 442 | .name = "dmic", |
| 443 | .sysc = &omap44xx_dmic_sysc, |
| 444 | }; |
| 445 | |
| 446 | /* dmic */ |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 447 | static struct omap_hwmod_irq_info omap44xx_dmic_irqs[] = { |
| 448 | { .irq = 114 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 449 | { .irq = -1 } |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 450 | }; |
| 451 | |
| 452 | static struct omap_hwmod_dma_info omap44xx_dmic_sdma_reqs[] = { |
| 453 | { .dma_req = 66 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 454 | { .dma_req = -1 } |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 455 | }; |
| 456 | |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 457 | static struct omap_hwmod omap44xx_dmic_hwmod = { |
| 458 | .name = "dmic", |
| 459 | .class = &omap44xx_dmic_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 460 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 461 | .mpu_irqs = omap44xx_dmic_irqs, |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 462 | .sdma_reqs = omap44xx_dmic_sdma_reqs, |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 463 | .main_clk = "dmic_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 464 | .prcm = { |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 465 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 466 | .clkctrl_offs = OMAP4_CM1_ABE_DMIC_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 467 | .context_offs = OMAP4_RM_ABE_DMIC_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 468 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 469 | }, |
| 470 | }, |
Benoit Cousson | 8ca476d | 2011-01-25 22:01:00 +0000 | [diff] [blame] | 471 | }; |
| 472 | |
| 473 | /* |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 474 | * 'dsp' class |
| 475 | * dsp sub-system |
| 476 | */ |
| 477 | |
| 478 | static struct omap_hwmod_class omap44xx_dsp_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 479 | .name = "dsp", |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 480 | }; |
| 481 | |
| 482 | /* dsp */ |
| 483 | static struct omap_hwmod_irq_info omap44xx_dsp_irqs[] = { |
| 484 | { .irq = 28 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 485 | { .irq = -1 } |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 486 | }; |
| 487 | |
| 488 | static struct omap_hwmod_rst_info omap44xx_dsp_resets[] = { |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 489 | { .name = "dsp", .rst_shift = 0 }, |
Paul Walmsley | f2f5736 | 2012-04-18 19:10:02 -0600 | [diff] [blame] | 490 | { .name = "mmu_cache", .rst_shift = 1 }, |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 491 | }; |
| 492 | |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 493 | static struct omap_hwmod omap44xx_dsp_hwmod = { |
| 494 | .name = "dsp", |
| 495 | .class = &omap44xx_dsp_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 496 | .clkdm_name = "tesla_clkdm", |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 497 | .mpu_irqs = omap44xx_dsp_irqs, |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 498 | .rst_lines = omap44xx_dsp_resets, |
| 499 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_dsp_resets), |
| 500 | .main_clk = "dsp_fck", |
| 501 | .prcm = { |
| 502 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 503 | .clkctrl_offs = OMAP4_CM_TESLA_TESLA_CLKCTRL_OFFSET, |
Benoit Cousson | eaac329 | 2011-07-10 05:56:31 -0600 | [diff] [blame] | 504 | .rstctrl_offs = OMAP4_RM_TESLA_RSTCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 505 | .context_offs = OMAP4_RM_TESLA_TESLA_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 506 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 507 | }, |
| 508 | }, |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 509 | }; |
| 510 | |
| 511 | /* |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 512 | * 'dss' class |
| 513 | * display sub-system |
| 514 | */ |
| 515 | |
| 516 | static struct omap_hwmod_class_sysconfig omap44xx_dss_sysc = { |
| 517 | .rev_offs = 0x0000, |
| 518 | .syss_offs = 0x0014, |
| 519 | .sysc_flags = SYSS_HAS_RESET_STATUS, |
| 520 | }; |
| 521 | |
| 522 | static struct omap_hwmod_class omap44xx_dss_hwmod_class = { |
| 523 | .name = "dss", |
| 524 | .sysc = &omap44xx_dss_sysc, |
Tomi Valkeinen | 13662dc | 2011-11-08 03:16:13 -0700 | [diff] [blame] | 525 | .reset = omap_dss_reset, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 526 | }; |
| 527 | |
| 528 | /* dss */ |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 529 | static struct omap_hwmod_opt_clk dss_opt_clks[] = { |
| 530 | { .role = "sys_clk", .clk = "dss_sys_clk" }, |
| 531 | { .role = "tv_clk", .clk = "dss_tv_clk" }, |
Tomi Valkeinen | 4d0698d | 2011-11-08 03:16:12 -0700 | [diff] [blame] | 532 | { .role = "hdmi_clk", .clk = "dss_48mhz_clk" }, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 533 | }; |
| 534 | |
| 535 | static struct omap_hwmod omap44xx_dss_hwmod = { |
| 536 | .name = "dss_core", |
Tomi Valkeinen | 37ad085 | 2011-11-08 03:16:11 -0700 | [diff] [blame] | 537 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 538 | .class = &omap44xx_dss_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 539 | .clkdm_name = "l3_dss_clkdm", |
Tomi Valkeinen | da7cdfa | 2011-07-09 20:39:45 -0600 | [diff] [blame] | 540 | .main_clk = "dss_dss_clk", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 541 | .prcm = { |
| 542 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 543 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 544 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 545 | }, |
| 546 | }, |
| 547 | .opt_clks = dss_opt_clks, |
| 548 | .opt_clks_cnt = ARRAY_SIZE(dss_opt_clks), |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 549 | }; |
| 550 | |
| 551 | /* |
| 552 | * 'dispc' class |
| 553 | * display controller |
| 554 | */ |
| 555 | |
| 556 | static struct omap_hwmod_class_sysconfig omap44xx_dispc_sysc = { |
| 557 | .rev_offs = 0x0000, |
| 558 | .sysc_offs = 0x0010, |
| 559 | .syss_offs = 0x0014, |
| 560 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | |
| 561 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_MIDLEMODE | |
| 562 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 563 | SYSS_HAS_RESET_STATUS), |
| 564 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 565 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 566 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 567 | }; |
| 568 | |
| 569 | static struct omap_hwmod_class omap44xx_dispc_hwmod_class = { |
| 570 | .name = "dispc", |
| 571 | .sysc = &omap44xx_dispc_sysc, |
| 572 | }; |
| 573 | |
| 574 | /* dss_dispc */ |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 575 | static struct omap_hwmod_irq_info omap44xx_dss_dispc_irqs[] = { |
| 576 | { .irq = 25 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 577 | { .irq = -1 } |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 578 | }; |
| 579 | |
| 580 | static struct omap_hwmod_dma_info omap44xx_dss_dispc_sdma_reqs[] = { |
| 581 | { .dma_req = 5 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 582 | { .dma_req = -1 } |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 583 | }; |
| 584 | |
Archit Taneja | b923d40 | 2011-10-06 18:04:08 -0600 | [diff] [blame] | 585 | static struct omap_dss_dispc_dev_attr omap44xx_dss_dispc_dev_attr = { |
| 586 | .manager_count = 3, |
| 587 | .has_framedonetv_irq = 1 |
| 588 | }; |
| 589 | |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 590 | static struct omap_hwmod omap44xx_dss_dispc_hwmod = { |
| 591 | .name = "dss_dispc", |
| 592 | .class = &omap44xx_dispc_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 593 | .clkdm_name = "l3_dss_clkdm", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 594 | .mpu_irqs = omap44xx_dss_dispc_irqs, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 595 | .sdma_reqs = omap44xx_dss_dispc_sdma_reqs, |
Tomi Valkeinen | da7cdfa | 2011-07-09 20:39:45 -0600 | [diff] [blame] | 596 | .main_clk = "dss_dss_clk", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 597 | .prcm = { |
| 598 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 599 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 600 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 601 | }, |
| 602 | }, |
Archit Taneja | b923d40 | 2011-10-06 18:04:08 -0600 | [diff] [blame] | 603 | .dev_attr = &omap44xx_dss_dispc_dev_attr |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 604 | }; |
| 605 | |
| 606 | /* |
| 607 | * 'dsi' class |
| 608 | * display serial interface controller |
| 609 | */ |
| 610 | |
| 611 | static struct omap_hwmod_class_sysconfig omap44xx_dsi_sysc = { |
| 612 | .rev_offs = 0x0000, |
| 613 | .sysc_offs = 0x0010, |
| 614 | .syss_offs = 0x0014, |
| 615 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | |
| 616 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 617 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 618 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 619 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 620 | }; |
| 621 | |
| 622 | static struct omap_hwmod_class omap44xx_dsi_hwmod_class = { |
| 623 | .name = "dsi", |
| 624 | .sysc = &omap44xx_dsi_sysc, |
| 625 | }; |
| 626 | |
| 627 | /* dss_dsi1 */ |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 628 | static struct omap_hwmod_irq_info omap44xx_dss_dsi1_irqs[] = { |
| 629 | { .irq = 53 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 630 | { .irq = -1 } |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 631 | }; |
| 632 | |
| 633 | static struct omap_hwmod_dma_info omap44xx_dss_dsi1_sdma_reqs[] = { |
| 634 | { .dma_req = 74 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 635 | { .dma_req = -1 } |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 636 | }; |
| 637 | |
Tomi Valkeinen | 3a23aaf | 2011-07-09 20:39:44 -0600 | [diff] [blame] | 638 | static struct omap_hwmod_opt_clk dss_dsi1_opt_clks[] = { |
| 639 | { .role = "sys_clk", .clk = "dss_sys_clk" }, |
| 640 | }; |
| 641 | |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 642 | static struct omap_hwmod omap44xx_dss_dsi1_hwmod = { |
| 643 | .name = "dss_dsi1", |
| 644 | .class = &omap44xx_dsi_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 645 | .clkdm_name = "l3_dss_clkdm", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 646 | .mpu_irqs = omap44xx_dss_dsi1_irqs, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 647 | .sdma_reqs = omap44xx_dss_dsi1_sdma_reqs, |
Tomi Valkeinen | da7cdfa | 2011-07-09 20:39:45 -0600 | [diff] [blame] | 648 | .main_clk = "dss_dss_clk", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 649 | .prcm = { |
| 650 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 651 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 652 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 653 | }, |
| 654 | }, |
Tomi Valkeinen | 3a23aaf | 2011-07-09 20:39:44 -0600 | [diff] [blame] | 655 | .opt_clks = dss_dsi1_opt_clks, |
| 656 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi1_opt_clks), |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 657 | }; |
| 658 | |
| 659 | /* dss_dsi2 */ |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 660 | static struct omap_hwmod_irq_info omap44xx_dss_dsi2_irqs[] = { |
| 661 | { .irq = 84 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 662 | { .irq = -1 } |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 663 | }; |
| 664 | |
| 665 | static struct omap_hwmod_dma_info omap44xx_dss_dsi2_sdma_reqs[] = { |
| 666 | { .dma_req = 83 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 667 | { .dma_req = -1 } |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 668 | }; |
| 669 | |
Tomi Valkeinen | 3a23aaf | 2011-07-09 20:39:44 -0600 | [diff] [blame] | 670 | static struct omap_hwmod_opt_clk dss_dsi2_opt_clks[] = { |
| 671 | { .role = "sys_clk", .clk = "dss_sys_clk" }, |
| 672 | }; |
| 673 | |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 674 | static struct omap_hwmod omap44xx_dss_dsi2_hwmod = { |
| 675 | .name = "dss_dsi2", |
| 676 | .class = &omap44xx_dsi_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 677 | .clkdm_name = "l3_dss_clkdm", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 678 | .mpu_irqs = omap44xx_dss_dsi2_irqs, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 679 | .sdma_reqs = omap44xx_dss_dsi2_sdma_reqs, |
Tomi Valkeinen | da7cdfa | 2011-07-09 20:39:45 -0600 | [diff] [blame] | 680 | .main_clk = "dss_dss_clk", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 681 | .prcm = { |
| 682 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 683 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 684 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 685 | }, |
| 686 | }, |
Tomi Valkeinen | 3a23aaf | 2011-07-09 20:39:44 -0600 | [diff] [blame] | 687 | .opt_clks = dss_dsi2_opt_clks, |
| 688 | .opt_clks_cnt = ARRAY_SIZE(dss_dsi2_opt_clks), |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 689 | }; |
| 690 | |
| 691 | /* |
| 692 | * 'hdmi' class |
| 693 | * hdmi controller |
| 694 | */ |
| 695 | |
| 696 | static struct omap_hwmod_class_sysconfig omap44xx_hdmi_sysc = { |
| 697 | .rev_offs = 0x0000, |
| 698 | .sysc_offs = 0x0010, |
| 699 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | |
| 700 | SYSC_HAS_SOFTRESET), |
| 701 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 702 | SIDLE_SMART_WKUP), |
| 703 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 704 | }; |
| 705 | |
| 706 | static struct omap_hwmod_class omap44xx_hdmi_hwmod_class = { |
| 707 | .name = "hdmi", |
| 708 | .sysc = &omap44xx_hdmi_sysc, |
| 709 | }; |
| 710 | |
| 711 | /* dss_hdmi */ |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 712 | static struct omap_hwmod_irq_info omap44xx_dss_hdmi_irqs[] = { |
| 713 | { .irq = 101 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 714 | { .irq = -1 } |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 715 | }; |
| 716 | |
| 717 | static struct omap_hwmod_dma_info omap44xx_dss_hdmi_sdma_reqs[] = { |
| 718 | { .dma_req = 75 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 719 | { .dma_req = -1 } |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 720 | }; |
| 721 | |
Tomi Valkeinen | 3a23aaf | 2011-07-09 20:39:44 -0600 | [diff] [blame] | 722 | static struct omap_hwmod_opt_clk dss_hdmi_opt_clks[] = { |
| 723 | { .role = "sys_clk", .clk = "dss_sys_clk" }, |
| 724 | }; |
| 725 | |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 726 | static struct omap_hwmod omap44xx_dss_hdmi_hwmod = { |
| 727 | .name = "dss_hdmi", |
| 728 | .class = &omap44xx_hdmi_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 729 | .clkdm_name = "l3_dss_clkdm", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 730 | .mpu_irqs = omap44xx_dss_hdmi_irqs, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 731 | .sdma_reqs = omap44xx_dss_hdmi_sdma_reqs, |
Tomi Valkeinen | 4d0698d | 2011-11-08 03:16:12 -0700 | [diff] [blame] | 732 | .main_clk = "dss_48mhz_clk", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 733 | .prcm = { |
| 734 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 735 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 736 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 737 | }, |
| 738 | }, |
Tomi Valkeinen | 3a23aaf | 2011-07-09 20:39:44 -0600 | [diff] [blame] | 739 | .opt_clks = dss_hdmi_opt_clks, |
| 740 | .opt_clks_cnt = ARRAY_SIZE(dss_hdmi_opt_clks), |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 741 | }; |
| 742 | |
| 743 | /* |
| 744 | * 'rfbi' class |
| 745 | * remote frame buffer interface |
| 746 | */ |
| 747 | |
| 748 | static struct omap_hwmod_class_sysconfig omap44xx_rfbi_sysc = { |
| 749 | .rev_offs = 0x0000, |
| 750 | .sysc_offs = 0x0010, |
| 751 | .syss_offs = 0x0014, |
| 752 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | |
| 753 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 754 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 755 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 756 | }; |
| 757 | |
| 758 | static struct omap_hwmod_class omap44xx_rfbi_hwmod_class = { |
| 759 | .name = "rfbi", |
| 760 | .sysc = &omap44xx_rfbi_sysc, |
| 761 | }; |
| 762 | |
| 763 | /* dss_rfbi */ |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 764 | static struct omap_hwmod_dma_info omap44xx_dss_rfbi_sdma_reqs[] = { |
| 765 | { .dma_req = 13 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 766 | { .dma_req = -1 } |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 767 | }; |
| 768 | |
Tomi Valkeinen | 3a23aaf | 2011-07-09 20:39:44 -0600 | [diff] [blame] | 769 | static struct omap_hwmod_opt_clk dss_rfbi_opt_clks[] = { |
| 770 | { .role = "ick", .clk = "dss_fck" }, |
| 771 | }; |
| 772 | |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 773 | static struct omap_hwmod omap44xx_dss_rfbi_hwmod = { |
| 774 | .name = "dss_rfbi", |
| 775 | .class = &omap44xx_rfbi_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 776 | .clkdm_name = "l3_dss_clkdm", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 777 | .sdma_reqs = omap44xx_dss_rfbi_sdma_reqs, |
Tomi Valkeinen | da7cdfa | 2011-07-09 20:39:45 -0600 | [diff] [blame] | 778 | .main_clk = "dss_dss_clk", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 779 | .prcm = { |
| 780 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 781 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 782 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 783 | }, |
| 784 | }, |
Tomi Valkeinen | 3a23aaf | 2011-07-09 20:39:44 -0600 | [diff] [blame] | 785 | .opt_clks = dss_rfbi_opt_clks, |
| 786 | .opt_clks_cnt = ARRAY_SIZE(dss_rfbi_opt_clks), |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 787 | }; |
| 788 | |
| 789 | /* |
| 790 | * 'venc' class |
| 791 | * video encoder |
| 792 | */ |
| 793 | |
| 794 | static struct omap_hwmod_class omap44xx_venc_hwmod_class = { |
| 795 | .name = "venc", |
| 796 | }; |
| 797 | |
| 798 | /* dss_venc */ |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 799 | static struct omap_hwmod omap44xx_dss_venc_hwmod = { |
| 800 | .name = "dss_venc", |
| 801 | .class = &omap44xx_venc_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 802 | .clkdm_name = "l3_dss_clkdm", |
Tomi Valkeinen | 4d0698d | 2011-11-08 03:16:12 -0700 | [diff] [blame] | 803 | .main_clk = "dss_tv_clk", |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 804 | .prcm = { |
| 805 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 806 | .clkctrl_offs = OMAP4_CM_DSS_DSS_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 807 | .context_offs = OMAP4_RM_DSS_DSS_CONTEXT_OFFSET, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 808 | }, |
| 809 | }, |
Benoit Cousson | d63bd74 | 2011-01-27 11:17:03 +0000 | [diff] [blame] | 810 | }; |
| 811 | |
| 812 | /* |
Paul Walmsley | bf30f95 | 2012-04-19 13:33:52 -0600 | [diff] [blame] | 813 | * 'emif' class |
| 814 | * external memory interface no1 |
| 815 | */ |
| 816 | |
| 817 | static struct omap_hwmod_class_sysconfig omap44xx_emif_sysc = { |
| 818 | .rev_offs = 0x0000, |
| 819 | }; |
| 820 | |
| 821 | static struct omap_hwmod_class omap44xx_emif_hwmod_class = { |
| 822 | .name = "emif", |
| 823 | .sysc = &omap44xx_emif_sysc, |
| 824 | }; |
| 825 | |
| 826 | /* emif1 */ |
| 827 | static struct omap_hwmod_irq_info omap44xx_emif1_irqs[] = { |
| 828 | { .irq = 110 + OMAP44XX_IRQ_GIC_START }, |
| 829 | { .irq = -1 } |
| 830 | }; |
| 831 | |
| 832 | static struct omap_hwmod omap44xx_emif1_hwmod = { |
| 833 | .name = "emif1", |
| 834 | .class = &omap44xx_emif_hwmod_class, |
| 835 | .clkdm_name = "l3_emif_clkdm", |
| 836 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
| 837 | .mpu_irqs = omap44xx_emif1_irqs, |
| 838 | .main_clk = "ddrphy_ck", |
| 839 | .prcm = { |
| 840 | .omap4 = { |
| 841 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_1_CLKCTRL_OFFSET, |
| 842 | .context_offs = OMAP4_RM_MEMIF_EMIF_1_CONTEXT_OFFSET, |
| 843 | .modulemode = MODULEMODE_HWCTRL, |
| 844 | }, |
| 845 | }, |
| 846 | }; |
| 847 | |
| 848 | /* emif2 */ |
| 849 | static struct omap_hwmod_irq_info omap44xx_emif2_irqs[] = { |
| 850 | { .irq = 111 + OMAP44XX_IRQ_GIC_START }, |
| 851 | { .irq = -1 } |
| 852 | }; |
| 853 | |
| 854 | static struct omap_hwmod omap44xx_emif2_hwmod = { |
| 855 | .name = "emif2", |
| 856 | .class = &omap44xx_emif_hwmod_class, |
| 857 | .clkdm_name = "l3_emif_clkdm", |
| 858 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
| 859 | .mpu_irqs = omap44xx_emif2_irqs, |
| 860 | .main_clk = "ddrphy_ck", |
| 861 | .prcm = { |
| 862 | .omap4 = { |
| 863 | .clkctrl_offs = OMAP4_CM_MEMIF_EMIF_2_CLKCTRL_OFFSET, |
| 864 | .context_offs = OMAP4_RM_MEMIF_EMIF_2_CONTEXT_OFFSET, |
| 865 | .modulemode = MODULEMODE_HWCTRL, |
| 866 | }, |
| 867 | }, |
| 868 | }; |
| 869 | |
| 870 | /* |
Ming Lei | b050f68 | 2012-04-19 13:33:50 -0600 | [diff] [blame] | 871 | * 'fdif' class |
| 872 | * face detection hw accelerator module |
| 873 | */ |
| 874 | |
| 875 | static struct omap_hwmod_class_sysconfig omap44xx_fdif_sysc = { |
| 876 | .rev_offs = 0x0000, |
| 877 | .sysc_offs = 0x0010, |
| 878 | /* |
| 879 | * FDIF needs 100 OCP clk cycles delay after a softreset before |
| 880 | * accessing sysconfig again. |
| 881 | * The lowest frequency at the moment for L3 bus is 100 MHz, so |
| 882 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). |
| 883 | * |
| 884 | * TODO: Indicate errata when available. |
| 885 | */ |
| 886 | .srst_udelay = 2, |
| 887 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
| 888 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), |
| 889 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 890 | MSTANDBY_FORCE | MSTANDBY_NO | MSTANDBY_SMART), |
| 891 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 892 | }; |
| 893 | |
| 894 | static struct omap_hwmod_class omap44xx_fdif_hwmod_class = { |
| 895 | .name = "fdif", |
| 896 | .sysc = &omap44xx_fdif_sysc, |
| 897 | }; |
| 898 | |
| 899 | /* fdif */ |
| 900 | static struct omap_hwmod_irq_info omap44xx_fdif_irqs[] = { |
| 901 | { .irq = 69 + OMAP44XX_IRQ_GIC_START }, |
| 902 | { .irq = -1 } |
| 903 | }; |
| 904 | |
| 905 | static struct omap_hwmod omap44xx_fdif_hwmod = { |
| 906 | .name = "fdif", |
| 907 | .class = &omap44xx_fdif_hwmod_class, |
| 908 | .clkdm_name = "iss_clkdm", |
| 909 | .mpu_irqs = omap44xx_fdif_irqs, |
| 910 | .main_clk = "fdif_fck", |
| 911 | .prcm = { |
| 912 | .omap4 = { |
| 913 | .clkctrl_offs = OMAP4_CM_CAM_FDIF_CLKCTRL_OFFSET, |
| 914 | .context_offs = OMAP4_RM_CAM_FDIF_CONTEXT_OFFSET, |
| 915 | .modulemode = MODULEMODE_SWCTRL, |
| 916 | }, |
| 917 | }, |
| 918 | }; |
| 919 | |
| 920 | /* |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 921 | * 'gpio' class |
| 922 | * general purpose io module |
| 923 | */ |
| 924 | |
| 925 | static struct omap_hwmod_class_sysconfig omap44xx_gpio_sysc = { |
| 926 | .rev_offs = 0x0000, |
| 927 | .sysc_offs = 0x0010, |
| 928 | .syss_offs = 0x0114, |
Benoit Cousson | 0cfe875 | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 929 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
| 930 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 931 | SYSS_HAS_RESET_STATUS), |
Benoit Cousson | 7cffa6b | 2010-12-21 21:31:28 -0700 | [diff] [blame] | 932 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 933 | SIDLE_SMART_WKUP), |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 934 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 935 | }; |
| 936 | |
| 937 | static struct omap_hwmod_class omap44xx_gpio_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 938 | .name = "gpio", |
| 939 | .sysc = &omap44xx_gpio_sysc, |
| 940 | .rev = 2, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 941 | }; |
| 942 | |
| 943 | /* gpio dev_attr */ |
| 944 | static struct omap_gpio_dev_attr gpio_dev_attr = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 945 | .bank_width = 32, |
| 946 | .dbck_flag = true, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 947 | }; |
| 948 | |
| 949 | /* gpio1 */ |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 950 | static struct omap_hwmod_irq_info omap44xx_gpio1_irqs[] = { |
| 951 | { .irq = 29 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 952 | { .irq = -1 } |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 953 | }; |
| 954 | |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 955 | static struct omap_hwmod_opt_clk gpio1_opt_clks[] = { |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 956 | { .role = "dbclk", .clk = "gpio1_dbclk" }, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 957 | }; |
| 958 | |
| 959 | static struct omap_hwmod omap44xx_gpio1_hwmod = { |
| 960 | .name = "gpio1", |
| 961 | .class = &omap44xx_gpio_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 962 | .clkdm_name = "l4_wkup_clkdm", |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 963 | .mpu_irqs = omap44xx_gpio1_irqs, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 964 | .main_clk = "gpio1_ick", |
| 965 | .prcm = { |
| 966 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 967 | .clkctrl_offs = OMAP4_CM_WKUP_GPIO1_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 968 | .context_offs = OMAP4_RM_WKUP_GPIO1_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 969 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 970 | }, |
| 971 | }, |
| 972 | .opt_clks = gpio1_opt_clks, |
| 973 | .opt_clks_cnt = ARRAY_SIZE(gpio1_opt_clks), |
| 974 | .dev_attr = &gpio_dev_attr, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 975 | }; |
| 976 | |
| 977 | /* gpio2 */ |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 978 | static struct omap_hwmod_irq_info omap44xx_gpio2_irqs[] = { |
| 979 | { .irq = 30 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 980 | { .irq = -1 } |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 981 | }; |
| 982 | |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 983 | static struct omap_hwmod_opt_clk gpio2_opt_clks[] = { |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 984 | { .role = "dbclk", .clk = "gpio2_dbclk" }, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 985 | }; |
| 986 | |
| 987 | static struct omap_hwmod omap44xx_gpio2_hwmod = { |
| 988 | .name = "gpio2", |
| 989 | .class = &omap44xx_gpio_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 990 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 991 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 992 | .mpu_irqs = omap44xx_gpio2_irqs, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 993 | .main_clk = "gpio2_ick", |
| 994 | .prcm = { |
| 995 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 996 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO2_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 997 | .context_offs = OMAP4_RM_L4PER_GPIO2_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 998 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 999 | }, |
| 1000 | }, |
| 1001 | .opt_clks = gpio2_opt_clks, |
| 1002 | .opt_clks_cnt = ARRAY_SIZE(gpio2_opt_clks), |
| 1003 | .dev_attr = &gpio_dev_attr, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1004 | }; |
| 1005 | |
| 1006 | /* gpio3 */ |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1007 | static struct omap_hwmod_irq_info omap44xx_gpio3_irqs[] = { |
| 1008 | { .irq = 31 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1009 | { .irq = -1 } |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1010 | }; |
| 1011 | |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1012 | static struct omap_hwmod_opt_clk gpio3_opt_clks[] = { |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1013 | { .role = "dbclk", .clk = "gpio3_dbclk" }, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1014 | }; |
| 1015 | |
| 1016 | static struct omap_hwmod omap44xx_gpio3_hwmod = { |
| 1017 | .name = "gpio3", |
| 1018 | .class = &omap44xx_gpio_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1019 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1020 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1021 | .mpu_irqs = omap44xx_gpio3_irqs, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1022 | .main_clk = "gpio3_ick", |
| 1023 | .prcm = { |
| 1024 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1025 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO3_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1026 | .context_offs = OMAP4_RM_L4PER_GPIO3_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1027 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1028 | }, |
| 1029 | }, |
| 1030 | .opt_clks = gpio3_opt_clks, |
| 1031 | .opt_clks_cnt = ARRAY_SIZE(gpio3_opt_clks), |
| 1032 | .dev_attr = &gpio_dev_attr, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1033 | }; |
| 1034 | |
| 1035 | /* gpio4 */ |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1036 | static struct omap_hwmod_irq_info omap44xx_gpio4_irqs[] = { |
| 1037 | { .irq = 32 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1038 | { .irq = -1 } |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1039 | }; |
| 1040 | |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1041 | static struct omap_hwmod_opt_clk gpio4_opt_clks[] = { |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1042 | { .role = "dbclk", .clk = "gpio4_dbclk" }, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1043 | }; |
| 1044 | |
| 1045 | static struct omap_hwmod omap44xx_gpio4_hwmod = { |
| 1046 | .name = "gpio4", |
| 1047 | .class = &omap44xx_gpio_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1048 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1049 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1050 | .mpu_irqs = omap44xx_gpio4_irqs, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1051 | .main_clk = "gpio4_ick", |
| 1052 | .prcm = { |
| 1053 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1054 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO4_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1055 | .context_offs = OMAP4_RM_L4PER_GPIO4_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1056 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1057 | }, |
| 1058 | }, |
| 1059 | .opt_clks = gpio4_opt_clks, |
| 1060 | .opt_clks_cnt = ARRAY_SIZE(gpio4_opt_clks), |
| 1061 | .dev_attr = &gpio_dev_attr, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1062 | }; |
| 1063 | |
| 1064 | /* gpio5 */ |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1065 | static struct omap_hwmod_irq_info omap44xx_gpio5_irqs[] = { |
| 1066 | { .irq = 33 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1067 | { .irq = -1 } |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1068 | }; |
| 1069 | |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1070 | static struct omap_hwmod_opt_clk gpio5_opt_clks[] = { |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1071 | { .role = "dbclk", .clk = "gpio5_dbclk" }, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1072 | }; |
| 1073 | |
| 1074 | static struct omap_hwmod omap44xx_gpio5_hwmod = { |
| 1075 | .name = "gpio5", |
| 1076 | .class = &omap44xx_gpio_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1077 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1078 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1079 | .mpu_irqs = omap44xx_gpio5_irqs, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1080 | .main_clk = "gpio5_ick", |
| 1081 | .prcm = { |
| 1082 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1083 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO5_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1084 | .context_offs = OMAP4_RM_L4PER_GPIO5_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1085 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1086 | }, |
| 1087 | }, |
| 1088 | .opt_clks = gpio5_opt_clks, |
| 1089 | .opt_clks_cnt = ARRAY_SIZE(gpio5_opt_clks), |
| 1090 | .dev_attr = &gpio_dev_attr, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1091 | }; |
| 1092 | |
| 1093 | /* gpio6 */ |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1094 | static struct omap_hwmod_irq_info omap44xx_gpio6_irqs[] = { |
| 1095 | { .irq = 34 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1096 | { .irq = -1 } |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1097 | }; |
| 1098 | |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1099 | static struct omap_hwmod_opt_clk gpio6_opt_clks[] = { |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1100 | { .role = "dbclk", .clk = "gpio6_dbclk" }, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1101 | }; |
| 1102 | |
| 1103 | static struct omap_hwmod omap44xx_gpio6_hwmod = { |
| 1104 | .name = "gpio6", |
| 1105 | .class = &omap44xx_gpio_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1106 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | b399bca | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1107 | .flags = HWMOD_CONTROL_OPT_CLKS_IN_RESET, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1108 | .mpu_irqs = omap44xx_gpio6_irqs, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1109 | .main_clk = "gpio6_ick", |
| 1110 | .prcm = { |
| 1111 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1112 | .clkctrl_offs = OMAP4_CM_L4PER_GPIO6_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1113 | .context_offs = OMAP4_RM_L4PER_GPIO6_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1114 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1115 | }, |
| 1116 | }, |
| 1117 | .opt_clks = gpio6_opt_clks, |
| 1118 | .opt_clks_cnt = ARRAY_SIZE(gpio6_opt_clks), |
| 1119 | .dev_attr = &gpio_dev_attr, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1120 | }; |
| 1121 | |
| 1122 | /* |
BenoƮt Cousson | eb42b5d | 2012-04-19 13:33:51 -0600 | [diff] [blame] | 1123 | * 'gpmc' class |
| 1124 | * general purpose memory controller |
| 1125 | */ |
| 1126 | |
| 1127 | static struct omap_hwmod_class_sysconfig omap44xx_gpmc_sysc = { |
| 1128 | .rev_offs = 0x0000, |
| 1129 | .sysc_offs = 0x0010, |
| 1130 | .syss_offs = 0x0014, |
| 1131 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SIDLEMODE | |
| 1132 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 1133 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1134 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1135 | }; |
| 1136 | |
| 1137 | static struct omap_hwmod_class omap44xx_gpmc_hwmod_class = { |
| 1138 | .name = "gpmc", |
| 1139 | .sysc = &omap44xx_gpmc_sysc, |
| 1140 | }; |
| 1141 | |
| 1142 | /* gpmc */ |
| 1143 | static struct omap_hwmod_irq_info omap44xx_gpmc_irqs[] = { |
| 1144 | { .irq = 20 + OMAP44XX_IRQ_GIC_START }, |
| 1145 | { .irq = -1 } |
| 1146 | }; |
| 1147 | |
| 1148 | static struct omap_hwmod_dma_info omap44xx_gpmc_sdma_reqs[] = { |
| 1149 | { .dma_req = 3 + OMAP44XX_DMA_REQ_START }, |
| 1150 | { .dma_req = -1 } |
| 1151 | }; |
| 1152 | |
| 1153 | static struct omap_hwmod omap44xx_gpmc_hwmod = { |
| 1154 | .name = "gpmc", |
| 1155 | .class = &omap44xx_gpmc_hwmod_class, |
| 1156 | .clkdm_name = "l3_2_clkdm", |
| 1157 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
| 1158 | .mpu_irqs = omap44xx_gpmc_irqs, |
| 1159 | .sdma_reqs = omap44xx_gpmc_sdma_reqs, |
| 1160 | .prcm = { |
| 1161 | .omap4 = { |
| 1162 | .clkctrl_offs = OMAP4_CM_L3_2_GPMC_CLKCTRL_OFFSET, |
| 1163 | .context_offs = OMAP4_RM_L3_2_GPMC_CONTEXT_OFFSET, |
| 1164 | .modulemode = MODULEMODE_HWCTRL, |
| 1165 | }, |
| 1166 | }, |
| 1167 | }; |
| 1168 | |
| 1169 | /* |
Paul Walmsley | 9def390 | 2012-04-19 13:33:53 -0600 | [diff] [blame^] | 1170 | * 'gpu' class |
| 1171 | * 2d/3d graphics accelerator |
| 1172 | */ |
| 1173 | |
| 1174 | static struct omap_hwmod_class_sysconfig omap44xx_gpu_sysc = { |
| 1175 | .rev_offs = 0x1fc00, |
| 1176 | .sysc_offs = 0x1fc10, |
| 1177 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE), |
| 1178 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1179 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | |
| 1180 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
| 1181 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 1182 | }; |
| 1183 | |
| 1184 | static struct omap_hwmod_class omap44xx_gpu_hwmod_class = { |
| 1185 | .name = "gpu", |
| 1186 | .sysc = &omap44xx_gpu_sysc, |
| 1187 | }; |
| 1188 | |
| 1189 | /* gpu */ |
| 1190 | static struct omap_hwmod_irq_info omap44xx_gpu_irqs[] = { |
| 1191 | { .irq = 21 + OMAP44XX_IRQ_GIC_START }, |
| 1192 | { .irq = -1 } |
| 1193 | }; |
| 1194 | |
| 1195 | static struct omap_hwmod omap44xx_gpu_hwmod = { |
| 1196 | .name = "gpu", |
| 1197 | .class = &omap44xx_gpu_hwmod_class, |
| 1198 | .clkdm_name = "l3_gfx_clkdm", |
| 1199 | .mpu_irqs = omap44xx_gpu_irqs, |
| 1200 | .main_clk = "gpu_fck", |
| 1201 | .prcm = { |
| 1202 | .omap4 = { |
| 1203 | .clkctrl_offs = OMAP4_CM_GFX_GFX_CLKCTRL_OFFSET, |
| 1204 | .context_offs = OMAP4_RM_GFX_GFX_CONTEXT_OFFSET, |
| 1205 | .modulemode = MODULEMODE_SWCTRL, |
| 1206 | }, |
| 1207 | }, |
| 1208 | }; |
| 1209 | |
| 1210 | /* |
Paul Walmsley | a091c08 | 2012-04-19 13:33:50 -0600 | [diff] [blame] | 1211 | * 'hdq1w' class |
| 1212 | * hdq / 1-wire serial interface controller |
| 1213 | */ |
| 1214 | |
| 1215 | static struct omap_hwmod_class_sysconfig omap44xx_hdq1w_sysc = { |
| 1216 | .rev_offs = 0x0000, |
| 1217 | .sysc_offs = 0x0014, |
| 1218 | .syss_offs = 0x0018, |
| 1219 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_SOFTRESET | |
| 1220 | SYSS_HAS_RESET_STATUS), |
| 1221 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1222 | }; |
| 1223 | |
| 1224 | static struct omap_hwmod_class omap44xx_hdq1w_hwmod_class = { |
| 1225 | .name = "hdq1w", |
| 1226 | .sysc = &omap44xx_hdq1w_sysc, |
| 1227 | }; |
| 1228 | |
| 1229 | /* hdq1w */ |
| 1230 | static struct omap_hwmod_irq_info omap44xx_hdq1w_irqs[] = { |
| 1231 | { .irq = 58 + OMAP44XX_IRQ_GIC_START }, |
| 1232 | { .irq = -1 } |
| 1233 | }; |
| 1234 | |
| 1235 | static struct omap_hwmod omap44xx_hdq1w_hwmod = { |
| 1236 | .name = "hdq1w", |
| 1237 | .class = &omap44xx_hdq1w_hwmod_class, |
| 1238 | .clkdm_name = "l4_per_clkdm", |
| 1239 | .flags = HWMOD_INIT_NO_RESET, /* XXX temporary */ |
| 1240 | .mpu_irqs = omap44xx_hdq1w_irqs, |
| 1241 | .main_clk = "hdq1w_fck", |
| 1242 | .prcm = { |
| 1243 | .omap4 = { |
| 1244 | .clkctrl_offs = OMAP4_CM_L4PER_HDQ1W_CLKCTRL_OFFSET, |
| 1245 | .context_offs = OMAP4_RM_L4PER_HDQ1W_CONTEXT_OFFSET, |
| 1246 | .modulemode = MODULEMODE_SWCTRL, |
| 1247 | }, |
| 1248 | }, |
| 1249 | }; |
| 1250 | |
| 1251 | /* |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1252 | * 'hsi' class |
| 1253 | * mipi high-speed synchronous serial interface (multichannel and full-duplex |
| 1254 | * serial if) |
| 1255 | */ |
| 1256 | |
| 1257 | static struct omap_hwmod_class_sysconfig omap44xx_hsi_sysc = { |
| 1258 | .rev_offs = 0x0000, |
| 1259 | .sysc_offs = 0x0010, |
| 1260 | .syss_offs = 0x0014, |
| 1261 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_EMUFREE | |
| 1262 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | |
| 1263 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 1264 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1265 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | |
Benoit Cousson | c614ebf | 2011-07-01 22:54:01 +0200 | [diff] [blame] | 1266 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1267 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1268 | }; |
| 1269 | |
| 1270 | static struct omap_hwmod_class omap44xx_hsi_hwmod_class = { |
| 1271 | .name = "hsi", |
| 1272 | .sysc = &omap44xx_hsi_sysc, |
| 1273 | }; |
| 1274 | |
| 1275 | /* hsi */ |
| 1276 | static struct omap_hwmod_irq_info omap44xx_hsi_irqs[] = { |
| 1277 | { .name = "mpu_p1", .irq = 67 + OMAP44XX_IRQ_GIC_START }, |
| 1278 | { .name = "mpu_p2", .irq = 68 + OMAP44XX_IRQ_GIC_START }, |
| 1279 | { .name = "mpu_dma", .irq = 71 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1280 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1281 | }; |
| 1282 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1283 | static struct omap_hwmod omap44xx_hsi_hwmod = { |
| 1284 | .name = "hsi", |
| 1285 | .class = &omap44xx_hsi_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1286 | .clkdm_name = "l3_init_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1287 | .mpu_irqs = omap44xx_hsi_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1288 | .main_clk = "hsi_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 1289 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1290 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1291 | .clkctrl_offs = OMAP4_CM_L3INIT_HSI_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1292 | .context_offs = OMAP4_RM_L3INIT_HSI_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1293 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1294 | }, |
| 1295 | }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1296 | }; |
| 1297 | |
| 1298 | /* |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1299 | * 'i2c' class |
| 1300 | * multimaster high-speed i2c controller |
| 1301 | */ |
| 1302 | |
| 1303 | static struct omap_hwmod_class_sysconfig omap44xx_i2c_sysc = { |
| 1304 | .sysc_offs = 0x0010, |
| 1305 | .syss_offs = 0x0090, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1306 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | |
| 1307 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
Benoit Cousson | 0cfe875 | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 1308 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
Benoit Cousson | 7cffa6b | 2010-12-21 21:31:28 -0700 | [diff] [blame] | 1309 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1310 | SIDLE_SMART_WKUP), |
Shubhrajyoti D | 3e47dc6 | 2011-12-13 16:25:54 +0530 | [diff] [blame] | 1311 | .clockact = CLOCKACT_TEST_ICLK, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1312 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1313 | }; |
| 1314 | |
| 1315 | static struct omap_hwmod_class omap44xx_i2c_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 1316 | .name = "i2c", |
| 1317 | .sysc = &omap44xx_i2c_sysc, |
Andy Green | db791a7 | 2011-07-10 05:27:15 -0600 | [diff] [blame] | 1318 | .rev = OMAP_I2C_IP_VERSION_2, |
Avinash.H.M | 6d3c55f | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 1319 | .reset = &omap_i2c_reset, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1320 | }; |
| 1321 | |
Andy Green | 4d4441a | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 1322 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
| 1323 | .flags = OMAP_I2C_FLAG_BUS_SHIFT_NONE, |
| 1324 | }; |
| 1325 | |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1326 | /* i2c1 */ |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1327 | static struct omap_hwmod_irq_info omap44xx_i2c1_irqs[] = { |
| 1328 | { .irq = 56 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1329 | { .irq = -1 } |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1330 | }; |
| 1331 | |
| 1332 | static struct omap_hwmod_dma_info omap44xx_i2c1_sdma_reqs[] = { |
| 1333 | { .name = "tx", .dma_req = 26 + OMAP44XX_DMA_REQ_START }, |
| 1334 | { .name = "rx", .dma_req = 27 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1335 | { .dma_req = -1 } |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1336 | }; |
| 1337 | |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1338 | static struct omap_hwmod omap44xx_i2c1_hwmod = { |
| 1339 | .name = "i2c1", |
| 1340 | .class = &omap44xx_i2c_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1341 | .clkdm_name = "l4_per_clkdm", |
Shubhrajyoti D | 3e47dc6 | 2011-12-13 16:25:54 +0530 | [diff] [blame] | 1342 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1343 | .mpu_irqs = omap44xx_i2c1_irqs, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1344 | .sdma_reqs = omap44xx_i2c1_sdma_reqs, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1345 | .main_clk = "i2c1_fck", |
| 1346 | .prcm = { |
| 1347 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1348 | .clkctrl_offs = OMAP4_CM_L4PER_I2C1_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1349 | .context_offs = OMAP4_RM_L4PER_I2C1_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1350 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1351 | }, |
| 1352 | }, |
Andy Green | 4d4441a | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 1353 | .dev_attr = &i2c_dev_attr, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1354 | }; |
| 1355 | |
| 1356 | /* i2c2 */ |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1357 | static struct omap_hwmod_irq_info omap44xx_i2c2_irqs[] = { |
| 1358 | { .irq = 57 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1359 | { .irq = -1 } |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1360 | }; |
| 1361 | |
| 1362 | static struct omap_hwmod_dma_info omap44xx_i2c2_sdma_reqs[] = { |
| 1363 | { .name = "tx", .dma_req = 28 + OMAP44XX_DMA_REQ_START }, |
| 1364 | { .name = "rx", .dma_req = 29 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1365 | { .dma_req = -1 } |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1366 | }; |
| 1367 | |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1368 | static struct omap_hwmod omap44xx_i2c2_hwmod = { |
| 1369 | .name = "i2c2", |
| 1370 | .class = &omap44xx_i2c_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1371 | .clkdm_name = "l4_per_clkdm", |
Shubhrajyoti D | 3e47dc6 | 2011-12-13 16:25:54 +0530 | [diff] [blame] | 1372 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1373 | .mpu_irqs = omap44xx_i2c2_irqs, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1374 | .sdma_reqs = omap44xx_i2c2_sdma_reqs, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1375 | .main_clk = "i2c2_fck", |
| 1376 | .prcm = { |
| 1377 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1378 | .clkctrl_offs = OMAP4_CM_L4PER_I2C2_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1379 | .context_offs = OMAP4_RM_L4PER_I2C2_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1380 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1381 | }, |
| 1382 | }, |
Andy Green | 4d4441a | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 1383 | .dev_attr = &i2c_dev_attr, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1384 | }; |
| 1385 | |
| 1386 | /* i2c3 */ |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1387 | static struct omap_hwmod_irq_info omap44xx_i2c3_irqs[] = { |
| 1388 | { .irq = 61 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1389 | { .irq = -1 } |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1390 | }; |
| 1391 | |
| 1392 | static struct omap_hwmod_dma_info omap44xx_i2c3_sdma_reqs[] = { |
| 1393 | { .name = "tx", .dma_req = 24 + OMAP44XX_DMA_REQ_START }, |
| 1394 | { .name = "rx", .dma_req = 25 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1395 | { .dma_req = -1 } |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1396 | }; |
| 1397 | |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1398 | static struct omap_hwmod omap44xx_i2c3_hwmod = { |
| 1399 | .name = "i2c3", |
| 1400 | .class = &omap44xx_i2c_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1401 | .clkdm_name = "l4_per_clkdm", |
Shubhrajyoti D | 3e47dc6 | 2011-12-13 16:25:54 +0530 | [diff] [blame] | 1402 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1403 | .mpu_irqs = omap44xx_i2c3_irqs, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1404 | .sdma_reqs = omap44xx_i2c3_sdma_reqs, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1405 | .main_clk = "i2c3_fck", |
| 1406 | .prcm = { |
| 1407 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1408 | .clkctrl_offs = OMAP4_CM_L4PER_I2C3_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1409 | .context_offs = OMAP4_RM_L4PER_I2C3_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1410 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1411 | }, |
| 1412 | }, |
Andy Green | 4d4441a | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 1413 | .dev_attr = &i2c_dev_attr, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1414 | }; |
| 1415 | |
| 1416 | /* i2c4 */ |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1417 | static struct omap_hwmod_irq_info omap44xx_i2c4_irqs[] = { |
| 1418 | { .irq = 62 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1419 | { .irq = -1 } |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1420 | }; |
| 1421 | |
| 1422 | static struct omap_hwmod_dma_info omap44xx_i2c4_sdma_reqs[] = { |
| 1423 | { .name = "tx", .dma_req = 123 + OMAP44XX_DMA_REQ_START }, |
| 1424 | { .name = "rx", .dma_req = 124 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1425 | { .dma_req = -1 } |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1426 | }; |
| 1427 | |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1428 | static struct omap_hwmod omap44xx_i2c4_hwmod = { |
| 1429 | .name = "i2c4", |
| 1430 | .class = &omap44xx_i2c_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1431 | .clkdm_name = "l4_per_clkdm", |
Shubhrajyoti D | 3e47dc6 | 2011-12-13 16:25:54 +0530 | [diff] [blame] | 1432 | .flags = HWMOD_16BIT_REG | HWMOD_SET_DEFAULT_CLOCKACT, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1433 | .mpu_irqs = omap44xx_i2c4_irqs, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1434 | .sdma_reqs = omap44xx_i2c4_sdma_reqs, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1435 | .main_clk = "i2c4_fck", |
| 1436 | .prcm = { |
| 1437 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1438 | .clkctrl_offs = OMAP4_CM_L4PER_I2C4_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1439 | .context_offs = OMAP4_RM_L4PER_I2C4_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1440 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1441 | }, |
| 1442 | }, |
Andy Green | 4d4441a | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 1443 | .dev_attr = &i2c_dev_attr, |
Benoit Cousson | f776471 | 2010-09-21 19:37:14 +0530 | [diff] [blame] | 1444 | }; |
| 1445 | |
| 1446 | /* |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1447 | * 'ipu' class |
| 1448 | * imaging processor unit |
| 1449 | */ |
| 1450 | |
| 1451 | static struct omap_hwmod_class omap44xx_ipu_hwmod_class = { |
| 1452 | .name = "ipu", |
| 1453 | }; |
| 1454 | |
| 1455 | /* ipu */ |
| 1456 | static struct omap_hwmod_irq_info omap44xx_ipu_irqs[] = { |
| 1457 | { .irq = 100 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1458 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1459 | }; |
| 1460 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1461 | static struct omap_hwmod_rst_info omap44xx_ipu_resets[] = { |
Paul Walmsley | f2f5736 | 2012-04-18 19:10:02 -0600 | [diff] [blame] | 1462 | { .name = "cpu0", .rst_shift = 0 }, |
| 1463 | { .name = "cpu1", .rst_shift = 1 }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1464 | { .name = "mmu_cache", .rst_shift = 2 }, |
| 1465 | }; |
| 1466 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1467 | static struct omap_hwmod omap44xx_ipu_hwmod = { |
| 1468 | .name = "ipu", |
| 1469 | .class = &omap44xx_ipu_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1470 | .clkdm_name = "ducati_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1471 | .mpu_irqs = omap44xx_ipu_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1472 | .rst_lines = omap44xx_ipu_resets, |
| 1473 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_ipu_resets), |
| 1474 | .main_clk = "ipu_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 1475 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1476 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1477 | .clkctrl_offs = OMAP4_CM_DUCATI_DUCATI_CLKCTRL_OFFSET, |
Benoit Cousson | eaac329 | 2011-07-10 05:56:31 -0600 | [diff] [blame] | 1478 | .rstctrl_offs = OMAP4_RM_DUCATI_RSTCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1479 | .context_offs = OMAP4_RM_DUCATI_DUCATI_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1480 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1481 | }, |
| 1482 | }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1483 | }; |
| 1484 | |
| 1485 | /* |
| 1486 | * 'iss' class |
| 1487 | * external images sensor pixel data processor |
| 1488 | */ |
| 1489 | |
| 1490 | static struct omap_hwmod_class_sysconfig omap44xx_iss_sysc = { |
| 1491 | .rev_offs = 0x0000, |
| 1492 | .sysc_offs = 0x0010, |
Fernando Guzman Lugo | d99de7f | 2012-04-13 05:08:03 -0600 | [diff] [blame] | 1493 | /* |
| 1494 | * ISS needs 100 OCP clk cycles delay after a softreset before |
| 1495 | * accessing sysconfig again. |
| 1496 | * The lowest frequency at the moment for L3 bus is 100 MHz, so |
| 1497 | * 1usec delay is needed. Add an x2 margin to be safe (2 usecs). |
| 1498 | * |
| 1499 | * TODO: Indicate errata when available. |
| 1500 | */ |
| 1501 | .srst_udelay = 2, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1502 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_RESET_STATUS | |
| 1503 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), |
| 1504 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1505 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | |
Benoit Cousson | c614ebf | 2011-07-01 22:54:01 +0200 | [diff] [blame] | 1506 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1507 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 1508 | }; |
| 1509 | |
| 1510 | static struct omap_hwmod_class omap44xx_iss_hwmod_class = { |
| 1511 | .name = "iss", |
| 1512 | .sysc = &omap44xx_iss_sysc, |
| 1513 | }; |
| 1514 | |
| 1515 | /* iss */ |
| 1516 | static struct omap_hwmod_irq_info omap44xx_iss_irqs[] = { |
| 1517 | { .irq = 24 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1518 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1519 | }; |
| 1520 | |
| 1521 | static struct omap_hwmod_dma_info omap44xx_iss_sdma_reqs[] = { |
| 1522 | { .name = "1", .dma_req = 8 + OMAP44XX_DMA_REQ_START }, |
| 1523 | { .name = "2", .dma_req = 9 + OMAP44XX_DMA_REQ_START }, |
| 1524 | { .name = "3", .dma_req = 11 + OMAP44XX_DMA_REQ_START }, |
| 1525 | { .name = "4", .dma_req = 12 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1526 | { .dma_req = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1527 | }; |
| 1528 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1529 | static struct omap_hwmod_opt_clk iss_opt_clks[] = { |
| 1530 | { .role = "ctrlclk", .clk = "iss_ctrlclk" }, |
| 1531 | }; |
| 1532 | |
| 1533 | static struct omap_hwmod omap44xx_iss_hwmod = { |
| 1534 | .name = "iss", |
| 1535 | .class = &omap44xx_iss_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1536 | .clkdm_name = "iss_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1537 | .mpu_irqs = omap44xx_iss_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1538 | .sdma_reqs = omap44xx_iss_sdma_reqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1539 | .main_clk = "iss_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 1540 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1541 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1542 | .clkctrl_offs = OMAP4_CM_CAM_ISS_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1543 | .context_offs = OMAP4_RM_CAM_ISS_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1544 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1545 | }, |
| 1546 | }, |
| 1547 | .opt_clks = iss_opt_clks, |
| 1548 | .opt_clks_cnt = ARRAY_SIZE(iss_opt_clks), |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1549 | }; |
| 1550 | |
| 1551 | /* |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1552 | * 'iva' class |
| 1553 | * multi-standard video encoder/decoder hardware accelerator |
| 1554 | */ |
| 1555 | |
| 1556 | static struct omap_hwmod_class omap44xx_iva_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 1557 | .name = "iva", |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1558 | }; |
| 1559 | |
| 1560 | /* iva */ |
| 1561 | static struct omap_hwmod_irq_info omap44xx_iva_irqs[] = { |
| 1562 | { .name = "sync_1", .irq = 103 + OMAP44XX_IRQ_GIC_START }, |
| 1563 | { .name = "sync_0", .irq = 104 + OMAP44XX_IRQ_GIC_START }, |
| 1564 | { .name = "mailbox_0", .irq = 107 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1565 | { .irq = -1 } |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1566 | }; |
| 1567 | |
| 1568 | static struct omap_hwmod_rst_info omap44xx_iva_resets[] = { |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1569 | { .name = "seq0", .rst_shift = 0 }, |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1570 | { .name = "seq1", .rst_shift = 1 }, |
Paul Walmsley | f2f5736 | 2012-04-18 19:10:02 -0600 | [diff] [blame] | 1571 | { .name = "logic", .rst_shift = 2 }, |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1572 | }; |
| 1573 | |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1574 | static struct omap_hwmod omap44xx_iva_hwmod = { |
| 1575 | .name = "iva", |
| 1576 | .class = &omap44xx_iva_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1577 | .clkdm_name = "ivahd_clkdm", |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1578 | .mpu_irqs = omap44xx_iva_irqs, |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1579 | .rst_lines = omap44xx_iva_resets, |
| 1580 | .rst_lines_cnt = ARRAY_SIZE(omap44xx_iva_resets), |
| 1581 | .main_clk = "iva_fck", |
| 1582 | .prcm = { |
| 1583 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1584 | .clkctrl_offs = OMAP4_CM_IVAHD_IVAHD_CLKCTRL_OFFSET, |
Benoit Cousson | eaac329 | 2011-07-10 05:56:31 -0600 | [diff] [blame] | 1585 | .rstctrl_offs = OMAP4_RM_IVAHD_RSTCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1586 | .context_offs = OMAP4_RM_IVAHD_IVAHD_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1587 | .modulemode = MODULEMODE_HWCTRL, |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1588 | }, |
| 1589 | }, |
Benoit Cousson | 8f25bdc | 2010-12-21 21:08:34 -0700 | [diff] [blame] | 1590 | }; |
| 1591 | |
| 1592 | /* |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1593 | * 'kbd' class |
| 1594 | * keyboard controller |
| 1595 | */ |
| 1596 | |
| 1597 | static struct omap_hwmod_class_sysconfig omap44xx_kbd_sysc = { |
| 1598 | .rev_offs = 0x0000, |
| 1599 | .sysc_offs = 0x0010, |
| 1600 | .syss_offs = 0x0014, |
| 1601 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | |
| 1602 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | |
| 1603 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 1604 | SYSS_HAS_RESET_STATUS), |
| 1605 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1606 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1607 | }; |
| 1608 | |
| 1609 | static struct omap_hwmod_class omap44xx_kbd_hwmod_class = { |
| 1610 | .name = "kbd", |
| 1611 | .sysc = &omap44xx_kbd_sysc, |
| 1612 | }; |
| 1613 | |
| 1614 | /* kbd */ |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1615 | static struct omap_hwmod_irq_info omap44xx_kbd_irqs[] = { |
| 1616 | { .irq = 120 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1617 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1618 | }; |
| 1619 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1620 | static struct omap_hwmod omap44xx_kbd_hwmod = { |
| 1621 | .name = "kbd", |
| 1622 | .class = &omap44xx_kbd_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1623 | .clkdm_name = "l4_wkup_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1624 | .mpu_irqs = omap44xx_kbd_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1625 | .main_clk = "kbd_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 1626 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1627 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1628 | .clkctrl_offs = OMAP4_CM_WKUP_KEYBOARD_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1629 | .context_offs = OMAP4_RM_WKUP_KEYBOARD_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1630 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1631 | }, |
| 1632 | }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1633 | }; |
| 1634 | |
| 1635 | /* |
Benoit Cousson | ec5df92 | 2011-02-02 19:27:21 +0000 | [diff] [blame] | 1636 | * 'mailbox' class |
| 1637 | * mailbox module allowing communication between the on-chip processors using a |
| 1638 | * queued mailbox-interrupt mechanism. |
| 1639 | */ |
| 1640 | |
| 1641 | static struct omap_hwmod_class_sysconfig omap44xx_mailbox_sysc = { |
| 1642 | .rev_offs = 0x0000, |
| 1643 | .sysc_offs = 0x0010, |
| 1644 | .sysc_flags = (SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | |
| 1645 | SYSC_HAS_SOFTRESET), |
| 1646 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1647 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 1648 | }; |
| 1649 | |
| 1650 | static struct omap_hwmod_class omap44xx_mailbox_hwmod_class = { |
| 1651 | .name = "mailbox", |
| 1652 | .sysc = &omap44xx_mailbox_sysc, |
| 1653 | }; |
| 1654 | |
| 1655 | /* mailbox */ |
Benoit Cousson | ec5df92 | 2011-02-02 19:27:21 +0000 | [diff] [blame] | 1656 | static struct omap_hwmod_irq_info omap44xx_mailbox_irqs[] = { |
| 1657 | { .irq = 26 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1658 | { .irq = -1 } |
Benoit Cousson | ec5df92 | 2011-02-02 19:27:21 +0000 | [diff] [blame] | 1659 | }; |
| 1660 | |
Benoit Cousson | ec5df92 | 2011-02-02 19:27:21 +0000 | [diff] [blame] | 1661 | static struct omap_hwmod omap44xx_mailbox_hwmod = { |
| 1662 | .name = "mailbox", |
| 1663 | .class = &omap44xx_mailbox_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1664 | .clkdm_name = "l4_cfg_clkdm", |
Benoit Cousson | ec5df92 | 2011-02-02 19:27:21 +0000 | [diff] [blame] | 1665 | .mpu_irqs = omap44xx_mailbox_irqs, |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 1666 | .prcm = { |
Benoit Cousson | ec5df92 | 2011-02-02 19:27:21 +0000 | [diff] [blame] | 1667 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1668 | .clkctrl_offs = OMAP4_CM_L4CFG_MAILBOX_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1669 | .context_offs = OMAP4_RM_L4CFG_MAILBOX_CONTEXT_OFFSET, |
Benoit Cousson | ec5df92 | 2011-02-02 19:27:21 +0000 | [diff] [blame] | 1670 | }, |
| 1671 | }, |
Benoit Cousson | ec5df92 | 2011-02-02 19:27:21 +0000 | [diff] [blame] | 1672 | }; |
| 1673 | |
| 1674 | /* |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1675 | * 'mcbsp' class |
| 1676 | * multi channel buffered serial port controller |
| 1677 | */ |
| 1678 | |
| 1679 | static struct omap_hwmod_class_sysconfig omap44xx_mcbsp_sysc = { |
| 1680 | .sysc_offs = 0x008c, |
| 1681 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_ENAWAKEUP | |
| 1682 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), |
| 1683 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 1684 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 1685 | }; |
| 1686 | |
| 1687 | static struct omap_hwmod_class omap44xx_mcbsp_hwmod_class = { |
| 1688 | .name = "mcbsp", |
| 1689 | .sysc = &omap44xx_mcbsp_sysc, |
Kishon Vijay Abraham I | cb7e9de | 2011-02-24 15:16:50 +0530 | [diff] [blame] | 1690 | .rev = MCBSP_CONFIG_TYPE4, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1691 | }; |
| 1692 | |
| 1693 | /* mcbsp1 */ |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1694 | static struct omap_hwmod_irq_info omap44xx_mcbsp1_irqs[] = { |
| 1695 | { .irq = 17 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1696 | { .irq = -1 } |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1697 | }; |
| 1698 | |
| 1699 | static struct omap_hwmod_dma_info omap44xx_mcbsp1_sdma_reqs[] = { |
| 1700 | { .name = "tx", .dma_req = 32 + OMAP44XX_DMA_REQ_START }, |
| 1701 | { .name = "rx", .dma_req = 33 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1702 | { .dma_req = -1 } |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1703 | }; |
| 1704 | |
Paul Walmsley | 503d0ea | 2012-04-04 09:11:48 -0600 | [diff] [blame] | 1705 | static struct omap_hwmod_opt_clk mcbsp1_opt_clks[] = { |
| 1706 | { .role = "pad_fck", .clk = "pad_clks_ck" }, |
| 1707 | { .role = "prcm_clk", .clk = "mcbsp1_sync_mux_ck" }, |
| 1708 | }; |
| 1709 | |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1710 | static struct omap_hwmod omap44xx_mcbsp1_hwmod = { |
| 1711 | .name = "mcbsp1", |
| 1712 | .class = &omap44xx_mcbsp_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1713 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1714 | .mpu_irqs = omap44xx_mcbsp1_irqs, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1715 | .sdma_reqs = omap44xx_mcbsp1_sdma_reqs, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1716 | .main_clk = "mcbsp1_fck", |
| 1717 | .prcm = { |
| 1718 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1719 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP1_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1720 | .context_offs = OMAP4_RM_ABE_MCBSP1_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1721 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1722 | }, |
| 1723 | }, |
Paul Walmsley | 503d0ea | 2012-04-04 09:11:48 -0600 | [diff] [blame] | 1724 | .opt_clks = mcbsp1_opt_clks, |
| 1725 | .opt_clks_cnt = ARRAY_SIZE(mcbsp1_opt_clks), |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1726 | }; |
| 1727 | |
| 1728 | /* mcbsp2 */ |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1729 | static struct omap_hwmod_irq_info omap44xx_mcbsp2_irqs[] = { |
| 1730 | { .irq = 22 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1731 | { .irq = -1 } |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1732 | }; |
| 1733 | |
| 1734 | static struct omap_hwmod_dma_info omap44xx_mcbsp2_sdma_reqs[] = { |
| 1735 | { .name = "tx", .dma_req = 16 + OMAP44XX_DMA_REQ_START }, |
| 1736 | { .name = "rx", .dma_req = 17 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1737 | { .dma_req = -1 } |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1738 | }; |
| 1739 | |
Paul Walmsley | 503d0ea | 2012-04-04 09:11:48 -0600 | [diff] [blame] | 1740 | static struct omap_hwmod_opt_clk mcbsp2_opt_clks[] = { |
| 1741 | { .role = "pad_fck", .clk = "pad_clks_ck" }, |
| 1742 | { .role = "prcm_clk", .clk = "mcbsp2_sync_mux_ck" }, |
| 1743 | }; |
| 1744 | |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1745 | static struct omap_hwmod omap44xx_mcbsp2_hwmod = { |
| 1746 | .name = "mcbsp2", |
| 1747 | .class = &omap44xx_mcbsp_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1748 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1749 | .mpu_irqs = omap44xx_mcbsp2_irqs, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1750 | .sdma_reqs = omap44xx_mcbsp2_sdma_reqs, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1751 | .main_clk = "mcbsp2_fck", |
| 1752 | .prcm = { |
| 1753 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1754 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP2_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1755 | .context_offs = OMAP4_RM_ABE_MCBSP2_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1756 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1757 | }, |
| 1758 | }, |
Paul Walmsley | 503d0ea | 2012-04-04 09:11:48 -0600 | [diff] [blame] | 1759 | .opt_clks = mcbsp2_opt_clks, |
| 1760 | .opt_clks_cnt = ARRAY_SIZE(mcbsp2_opt_clks), |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1761 | }; |
| 1762 | |
| 1763 | /* mcbsp3 */ |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1764 | static struct omap_hwmod_irq_info omap44xx_mcbsp3_irqs[] = { |
| 1765 | { .irq = 23 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1766 | { .irq = -1 } |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1767 | }; |
| 1768 | |
| 1769 | static struct omap_hwmod_dma_info omap44xx_mcbsp3_sdma_reqs[] = { |
| 1770 | { .name = "tx", .dma_req = 18 + OMAP44XX_DMA_REQ_START }, |
| 1771 | { .name = "rx", .dma_req = 19 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1772 | { .dma_req = -1 } |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1773 | }; |
| 1774 | |
Paul Walmsley | 503d0ea | 2012-04-04 09:11:48 -0600 | [diff] [blame] | 1775 | static struct omap_hwmod_opt_clk mcbsp3_opt_clks[] = { |
| 1776 | { .role = "pad_fck", .clk = "pad_clks_ck" }, |
| 1777 | { .role = "prcm_clk", .clk = "mcbsp3_sync_mux_ck" }, |
| 1778 | }; |
| 1779 | |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1780 | static struct omap_hwmod omap44xx_mcbsp3_hwmod = { |
| 1781 | .name = "mcbsp3", |
| 1782 | .class = &omap44xx_mcbsp_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1783 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1784 | .mpu_irqs = omap44xx_mcbsp3_irqs, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1785 | .sdma_reqs = omap44xx_mcbsp3_sdma_reqs, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1786 | .main_clk = "mcbsp3_fck", |
| 1787 | .prcm = { |
| 1788 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1789 | .clkctrl_offs = OMAP4_CM1_ABE_MCBSP3_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1790 | .context_offs = OMAP4_RM_ABE_MCBSP3_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1791 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1792 | }, |
| 1793 | }, |
Paul Walmsley | 503d0ea | 2012-04-04 09:11:48 -0600 | [diff] [blame] | 1794 | .opt_clks = mcbsp3_opt_clks, |
| 1795 | .opt_clks_cnt = ARRAY_SIZE(mcbsp3_opt_clks), |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1796 | }; |
| 1797 | |
| 1798 | /* mcbsp4 */ |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1799 | static struct omap_hwmod_irq_info omap44xx_mcbsp4_irqs[] = { |
| 1800 | { .irq = 16 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1801 | { .irq = -1 } |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1802 | }; |
| 1803 | |
| 1804 | static struct omap_hwmod_dma_info omap44xx_mcbsp4_sdma_reqs[] = { |
| 1805 | { .name = "tx", .dma_req = 30 + OMAP44XX_DMA_REQ_START }, |
| 1806 | { .name = "rx", .dma_req = 31 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1807 | { .dma_req = -1 } |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1808 | }; |
| 1809 | |
Paul Walmsley | 503d0ea | 2012-04-04 09:11:48 -0600 | [diff] [blame] | 1810 | static struct omap_hwmod_opt_clk mcbsp4_opt_clks[] = { |
| 1811 | { .role = "pad_fck", .clk = "pad_clks_ck" }, |
| 1812 | { .role = "prcm_clk", .clk = "mcbsp4_sync_mux_ck" }, |
| 1813 | }; |
| 1814 | |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1815 | static struct omap_hwmod omap44xx_mcbsp4_hwmod = { |
| 1816 | .name = "mcbsp4", |
| 1817 | .class = &omap44xx_mcbsp_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1818 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1819 | .mpu_irqs = omap44xx_mcbsp4_irqs, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1820 | .sdma_reqs = omap44xx_mcbsp4_sdma_reqs, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1821 | .main_clk = "mcbsp4_fck", |
| 1822 | .prcm = { |
| 1823 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1824 | .clkctrl_offs = OMAP4_CM_L4PER_MCBSP4_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1825 | .context_offs = OMAP4_RM_L4PER_MCBSP4_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1826 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1827 | }, |
| 1828 | }, |
Paul Walmsley | 503d0ea | 2012-04-04 09:11:48 -0600 | [diff] [blame] | 1829 | .opt_clks = mcbsp4_opt_clks, |
| 1830 | .opt_clks_cnt = ARRAY_SIZE(mcbsp4_opt_clks), |
Benoit Cousson | 4ddff49 | 2011-01-31 14:50:30 +0000 | [diff] [blame] | 1831 | }; |
| 1832 | |
| 1833 | /* |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1834 | * 'mcpdm' class |
| 1835 | * multi channel pdm controller (proprietary interface with phoenix power |
| 1836 | * ic) |
| 1837 | */ |
| 1838 | |
| 1839 | static struct omap_hwmod_class_sysconfig omap44xx_mcpdm_sysc = { |
| 1840 | .rev_offs = 0x0000, |
| 1841 | .sysc_offs = 0x0010, |
| 1842 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | |
| 1843 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), |
| 1844 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1845 | SIDLE_SMART_WKUP), |
| 1846 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 1847 | }; |
| 1848 | |
| 1849 | static struct omap_hwmod_class omap44xx_mcpdm_hwmod_class = { |
| 1850 | .name = "mcpdm", |
| 1851 | .sysc = &omap44xx_mcpdm_sysc, |
| 1852 | }; |
| 1853 | |
| 1854 | /* mcpdm */ |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1855 | static struct omap_hwmod_irq_info omap44xx_mcpdm_irqs[] = { |
| 1856 | { .irq = 112 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1857 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1858 | }; |
| 1859 | |
| 1860 | static struct omap_hwmod_dma_info omap44xx_mcpdm_sdma_reqs[] = { |
| 1861 | { .name = "up_link", .dma_req = 64 + OMAP44XX_DMA_REQ_START }, |
| 1862 | { .name = "dn_link", .dma_req = 65 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1863 | { .dma_req = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1864 | }; |
| 1865 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1866 | static struct omap_hwmod omap44xx_mcpdm_hwmod = { |
| 1867 | .name = "mcpdm", |
| 1868 | .class = &omap44xx_mcpdm_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1869 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1870 | .mpu_irqs = omap44xx_mcpdm_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1871 | .sdma_reqs = omap44xx_mcpdm_sdma_reqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1872 | .main_clk = "mcpdm_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 1873 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1874 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1875 | .clkctrl_offs = OMAP4_CM1_ABE_PDM_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1876 | .context_offs = OMAP4_RM_ABE_PDM_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1877 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1878 | }, |
| 1879 | }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 1880 | }; |
| 1881 | |
| 1882 | /* |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1883 | * 'mcspi' class |
| 1884 | * multichannel serial port interface (mcspi) / master/slave synchronous serial |
| 1885 | * bus |
| 1886 | */ |
| 1887 | |
| 1888 | static struct omap_hwmod_class_sysconfig omap44xx_mcspi_sysc = { |
| 1889 | .rev_offs = 0x0000, |
| 1890 | .sysc_offs = 0x0010, |
| 1891 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | |
| 1892 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), |
| 1893 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 1894 | SIDLE_SMART_WKUP), |
| 1895 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 1896 | }; |
| 1897 | |
| 1898 | static struct omap_hwmod_class omap44xx_mcspi_hwmod_class = { |
| 1899 | .name = "mcspi", |
| 1900 | .sysc = &omap44xx_mcspi_sysc, |
Benoit Cousson | 905a74d | 2011-02-18 14:01:06 +0100 | [diff] [blame] | 1901 | .rev = OMAP4_MCSPI_REV, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1902 | }; |
| 1903 | |
| 1904 | /* mcspi1 */ |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1905 | static struct omap_hwmod_irq_info omap44xx_mcspi1_irqs[] = { |
| 1906 | { .irq = 65 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1907 | { .irq = -1 } |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1908 | }; |
| 1909 | |
| 1910 | static struct omap_hwmod_dma_info omap44xx_mcspi1_sdma_reqs[] = { |
| 1911 | { .name = "tx0", .dma_req = 34 + OMAP44XX_DMA_REQ_START }, |
| 1912 | { .name = "rx0", .dma_req = 35 + OMAP44XX_DMA_REQ_START }, |
| 1913 | { .name = "tx1", .dma_req = 36 + OMAP44XX_DMA_REQ_START }, |
| 1914 | { .name = "rx1", .dma_req = 37 + OMAP44XX_DMA_REQ_START }, |
| 1915 | { .name = "tx2", .dma_req = 38 + OMAP44XX_DMA_REQ_START }, |
| 1916 | { .name = "rx2", .dma_req = 39 + OMAP44XX_DMA_REQ_START }, |
| 1917 | { .name = "tx3", .dma_req = 40 + OMAP44XX_DMA_REQ_START }, |
| 1918 | { .name = "rx3", .dma_req = 41 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1919 | { .dma_req = -1 } |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1920 | }; |
| 1921 | |
Benoit Cousson | 905a74d | 2011-02-18 14:01:06 +0100 | [diff] [blame] | 1922 | /* mcspi1 dev_attr */ |
| 1923 | static struct omap2_mcspi_dev_attr mcspi1_dev_attr = { |
| 1924 | .num_chipselect = 4, |
| 1925 | }; |
| 1926 | |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1927 | static struct omap_hwmod omap44xx_mcspi1_hwmod = { |
| 1928 | .name = "mcspi1", |
| 1929 | .class = &omap44xx_mcspi_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1930 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1931 | .mpu_irqs = omap44xx_mcspi1_irqs, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1932 | .sdma_reqs = omap44xx_mcspi1_sdma_reqs, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1933 | .main_clk = "mcspi1_fck", |
| 1934 | .prcm = { |
| 1935 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1936 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI1_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1937 | .context_offs = OMAP4_RM_L4PER_MCSPI1_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1938 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1939 | }, |
| 1940 | }, |
Benoit Cousson | 905a74d | 2011-02-18 14:01:06 +0100 | [diff] [blame] | 1941 | .dev_attr = &mcspi1_dev_attr, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1942 | }; |
| 1943 | |
| 1944 | /* mcspi2 */ |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1945 | static struct omap_hwmod_irq_info omap44xx_mcspi2_irqs[] = { |
| 1946 | { .irq = 66 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1947 | { .irq = -1 } |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1948 | }; |
| 1949 | |
| 1950 | static struct omap_hwmod_dma_info omap44xx_mcspi2_sdma_reqs[] = { |
| 1951 | { .name = "tx0", .dma_req = 42 + OMAP44XX_DMA_REQ_START }, |
| 1952 | { .name = "rx0", .dma_req = 43 + OMAP44XX_DMA_REQ_START }, |
| 1953 | { .name = "tx1", .dma_req = 44 + OMAP44XX_DMA_REQ_START }, |
| 1954 | { .name = "rx1", .dma_req = 45 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1955 | { .dma_req = -1 } |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1956 | }; |
| 1957 | |
Benoit Cousson | 905a74d | 2011-02-18 14:01:06 +0100 | [diff] [blame] | 1958 | /* mcspi2 dev_attr */ |
| 1959 | static struct omap2_mcspi_dev_attr mcspi2_dev_attr = { |
| 1960 | .num_chipselect = 2, |
| 1961 | }; |
| 1962 | |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1963 | static struct omap_hwmod omap44xx_mcspi2_hwmod = { |
| 1964 | .name = "mcspi2", |
| 1965 | .class = &omap44xx_mcspi_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 1966 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1967 | .mpu_irqs = omap44xx_mcspi2_irqs, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1968 | .sdma_reqs = omap44xx_mcspi2_sdma_reqs, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1969 | .main_clk = "mcspi2_fck", |
| 1970 | .prcm = { |
| 1971 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 1972 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI2_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1973 | .context_offs = OMAP4_RM_L4PER_MCSPI2_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 1974 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1975 | }, |
| 1976 | }, |
Benoit Cousson | 905a74d | 2011-02-18 14:01:06 +0100 | [diff] [blame] | 1977 | .dev_attr = &mcspi2_dev_attr, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1978 | }; |
| 1979 | |
| 1980 | /* mcspi3 */ |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1981 | static struct omap_hwmod_irq_info omap44xx_mcspi3_irqs[] = { |
| 1982 | { .irq = 91 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 1983 | { .irq = -1 } |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1984 | }; |
| 1985 | |
| 1986 | static struct omap_hwmod_dma_info omap44xx_mcspi3_sdma_reqs[] = { |
| 1987 | { .name = "tx0", .dma_req = 14 + OMAP44XX_DMA_REQ_START }, |
| 1988 | { .name = "rx0", .dma_req = 15 + OMAP44XX_DMA_REQ_START }, |
| 1989 | { .name = "tx1", .dma_req = 22 + OMAP44XX_DMA_REQ_START }, |
| 1990 | { .name = "rx1", .dma_req = 23 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 1991 | { .dma_req = -1 } |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1992 | }; |
| 1993 | |
Benoit Cousson | 905a74d | 2011-02-18 14:01:06 +0100 | [diff] [blame] | 1994 | /* mcspi3 dev_attr */ |
| 1995 | static struct omap2_mcspi_dev_attr mcspi3_dev_attr = { |
| 1996 | .num_chipselect = 2, |
| 1997 | }; |
| 1998 | |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 1999 | static struct omap_hwmod omap44xx_mcspi3_hwmod = { |
| 2000 | .name = "mcspi3", |
| 2001 | .class = &omap44xx_mcspi_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2002 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2003 | .mpu_irqs = omap44xx_mcspi3_irqs, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2004 | .sdma_reqs = omap44xx_mcspi3_sdma_reqs, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2005 | .main_clk = "mcspi3_fck", |
| 2006 | .prcm = { |
| 2007 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2008 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI3_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2009 | .context_offs = OMAP4_RM_L4PER_MCSPI3_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2010 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2011 | }, |
| 2012 | }, |
Benoit Cousson | 905a74d | 2011-02-18 14:01:06 +0100 | [diff] [blame] | 2013 | .dev_attr = &mcspi3_dev_attr, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2014 | }; |
| 2015 | |
| 2016 | /* mcspi4 */ |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2017 | static struct omap_hwmod_irq_info omap44xx_mcspi4_irqs[] = { |
| 2018 | { .irq = 48 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2019 | { .irq = -1 } |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2020 | }; |
| 2021 | |
| 2022 | static struct omap_hwmod_dma_info omap44xx_mcspi4_sdma_reqs[] = { |
| 2023 | { .name = "tx0", .dma_req = 69 + OMAP44XX_DMA_REQ_START }, |
| 2024 | { .name = "rx0", .dma_req = 70 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 2025 | { .dma_req = -1 } |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2026 | }; |
| 2027 | |
Benoit Cousson | 905a74d | 2011-02-18 14:01:06 +0100 | [diff] [blame] | 2028 | /* mcspi4 dev_attr */ |
| 2029 | static struct omap2_mcspi_dev_attr mcspi4_dev_attr = { |
| 2030 | .num_chipselect = 1, |
| 2031 | }; |
| 2032 | |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2033 | static struct omap_hwmod omap44xx_mcspi4_hwmod = { |
| 2034 | .name = "mcspi4", |
| 2035 | .class = &omap44xx_mcspi_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2036 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2037 | .mpu_irqs = omap44xx_mcspi4_irqs, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2038 | .sdma_reqs = omap44xx_mcspi4_sdma_reqs, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2039 | .main_clk = "mcspi4_fck", |
| 2040 | .prcm = { |
| 2041 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2042 | .clkctrl_offs = OMAP4_CM_L4PER_MCSPI4_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2043 | .context_offs = OMAP4_RM_L4PER_MCSPI4_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2044 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2045 | }, |
| 2046 | }, |
Benoit Cousson | 905a74d | 2011-02-18 14:01:06 +0100 | [diff] [blame] | 2047 | .dev_attr = &mcspi4_dev_attr, |
Benoit Cousson | 9bcbd7f | 2011-02-02 17:52:13 +0530 | [diff] [blame] | 2048 | }; |
| 2049 | |
| 2050 | /* |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2051 | * 'mmc' class |
| 2052 | * multimedia card high-speed/sd/sdio (mmc/sd/sdio) host controller |
| 2053 | */ |
| 2054 | |
| 2055 | static struct omap_hwmod_class_sysconfig omap44xx_mmc_sysc = { |
| 2056 | .rev_offs = 0x0000, |
| 2057 | .sysc_offs = 0x0010, |
| 2058 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_MIDLEMODE | |
| 2059 | SYSC_HAS_RESET_STATUS | SYSC_HAS_SIDLEMODE | |
| 2060 | SYSC_HAS_SOFTRESET), |
| 2061 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 2062 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | |
Benoit Cousson | c614ebf | 2011-07-01 22:54:01 +0200 | [diff] [blame] | 2063 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2064 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 2065 | }; |
| 2066 | |
| 2067 | static struct omap_hwmod_class omap44xx_mmc_hwmod_class = { |
| 2068 | .name = "mmc", |
| 2069 | .sysc = &omap44xx_mmc_sysc, |
| 2070 | }; |
| 2071 | |
| 2072 | /* mmc1 */ |
| 2073 | static struct omap_hwmod_irq_info omap44xx_mmc1_irqs[] = { |
| 2074 | { .irq = 83 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2075 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2076 | }; |
| 2077 | |
| 2078 | static struct omap_hwmod_dma_info omap44xx_mmc1_sdma_reqs[] = { |
| 2079 | { .name = "tx", .dma_req = 60 + OMAP44XX_DMA_REQ_START }, |
| 2080 | { .name = "rx", .dma_req = 61 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 2081 | { .dma_req = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2082 | }; |
| 2083 | |
Kishore Kadiyala | 6ab8946 | 2011-03-01 13:12:56 -0800 | [diff] [blame] | 2084 | /* mmc1 dev_attr */ |
| 2085 | static struct omap_mmc_dev_attr mmc1_dev_attr = { |
| 2086 | .flags = OMAP_HSMMC_SUPPORTS_DUAL_VOLT, |
| 2087 | }; |
| 2088 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2089 | static struct omap_hwmod omap44xx_mmc1_hwmod = { |
| 2090 | .name = "mmc1", |
| 2091 | .class = &omap44xx_mmc_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2092 | .clkdm_name = "l3_init_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2093 | .mpu_irqs = omap44xx_mmc1_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2094 | .sdma_reqs = omap44xx_mmc1_sdma_reqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2095 | .main_clk = "mmc1_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 2096 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2097 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2098 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC1_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2099 | .context_offs = OMAP4_RM_L3INIT_MMC1_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2100 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2101 | }, |
| 2102 | }, |
Kishore Kadiyala | 6ab8946 | 2011-03-01 13:12:56 -0800 | [diff] [blame] | 2103 | .dev_attr = &mmc1_dev_attr, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2104 | }; |
| 2105 | |
| 2106 | /* mmc2 */ |
| 2107 | static struct omap_hwmod_irq_info omap44xx_mmc2_irqs[] = { |
| 2108 | { .irq = 86 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2109 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2110 | }; |
| 2111 | |
| 2112 | static struct omap_hwmod_dma_info omap44xx_mmc2_sdma_reqs[] = { |
| 2113 | { .name = "tx", .dma_req = 46 + OMAP44XX_DMA_REQ_START }, |
| 2114 | { .name = "rx", .dma_req = 47 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 2115 | { .dma_req = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2116 | }; |
| 2117 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2118 | static struct omap_hwmod omap44xx_mmc2_hwmod = { |
| 2119 | .name = "mmc2", |
| 2120 | .class = &omap44xx_mmc_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2121 | .clkdm_name = "l3_init_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2122 | .mpu_irqs = omap44xx_mmc2_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2123 | .sdma_reqs = omap44xx_mmc2_sdma_reqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2124 | .main_clk = "mmc2_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 2125 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2126 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2127 | .clkctrl_offs = OMAP4_CM_L3INIT_MMC2_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2128 | .context_offs = OMAP4_RM_L3INIT_MMC2_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2129 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2130 | }, |
| 2131 | }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2132 | }; |
| 2133 | |
| 2134 | /* mmc3 */ |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2135 | static struct omap_hwmod_irq_info omap44xx_mmc3_irqs[] = { |
| 2136 | { .irq = 94 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2137 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2138 | }; |
| 2139 | |
| 2140 | static struct omap_hwmod_dma_info omap44xx_mmc3_sdma_reqs[] = { |
| 2141 | { .name = "tx", .dma_req = 76 + OMAP44XX_DMA_REQ_START }, |
| 2142 | { .name = "rx", .dma_req = 77 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 2143 | { .dma_req = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2144 | }; |
| 2145 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2146 | static struct omap_hwmod omap44xx_mmc3_hwmod = { |
| 2147 | .name = "mmc3", |
| 2148 | .class = &omap44xx_mmc_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2149 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2150 | .mpu_irqs = omap44xx_mmc3_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2151 | .sdma_reqs = omap44xx_mmc3_sdma_reqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2152 | .main_clk = "mmc3_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 2153 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2154 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2155 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD3_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2156 | .context_offs = OMAP4_RM_L4PER_MMCSD3_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2157 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2158 | }, |
| 2159 | }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2160 | }; |
| 2161 | |
| 2162 | /* mmc4 */ |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2163 | static struct omap_hwmod_irq_info omap44xx_mmc4_irqs[] = { |
| 2164 | { .irq = 96 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2165 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2166 | }; |
| 2167 | |
| 2168 | static struct omap_hwmod_dma_info omap44xx_mmc4_sdma_reqs[] = { |
| 2169 | { .name = "tx", .dma_req = 56 + OMAP44XX_DMA_REQ_START }, |
| 2170 | { .name = "rx", .dma_req = 57 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 2171 | { .dma_req = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2172 | }; |
| 2173 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2174 | static struct omap_hwmod omap44xx_mmc4_hwmod = { |
| 2175 | .name = "mmc4", |
| 2176 | .class = &omap44xx_mmc_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2177 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2178 | .mpu_irqs = omap44xx_mmc4_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2179 | .sdma_reqs = omap44xx_mmc4_sdma_reqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2180 | .main_clk = "mmc4_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 2181 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2182 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2183 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD4_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2184 | .context_offs = OMAP4_RM_L4PER_MMCSD4_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2185 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2186 | }, |
| 2187 | }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2188 | }; |
| 2189 | |
| 2190 | /* mmc5 */ |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2191 | static struct omap_hwmod_irq_info omap44xx_mmc5_irqs[] = { |
| 2192 | { .irq = 59 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2193 | { .irq = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2194 | }; |
| 2195 | |
| 2196 | static struct omap_hwmod_dma_info omap44xx_mmc5_sdma_reqs[] = { |
| 2197 | { .name = "tx", .dma_req = 58 + OMAP44XX_DMA_REQ_START }, |
| 2198 | { .name = "rx", .dma_req = 59 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 2199 | { .dma_req = -1 } |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2200 | }; |
| 2201 | |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2202 | static struct omap_hwmod omap44xx_mmc5_hwmod = { |
| 2203 | .name = "mmc5", |
| 2204 | .class = &omap44xx_mmc_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2205 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2206 | .mpu_irqs = omap44xx_mmc5_irqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2207 | .sdma_reqs = omap44xx_mmc5_sdma_reqs, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2208 | .main_clk = "mmc5_fck", |
Benoit Cousson | 00fe610 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 2209 | .prcm = { |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2210 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2211 | .clkctrl_offs = OMAP4_CM_L4PER_MMCSD5_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2212 | .context_offs = OMAP4_RM_L4PER_MMCSD5_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2213 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2214 | }, |
| 2215 | }, |
Benoit Cousson | 407a688 | 2011-02-15 22:39:48 +0100 | [diff] [blame] | 2216 | }; |
| 2217 | |
| 2218 | /* |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 2219 | * 'mpu' class |
| 2220 | * mpu sub-system |
| 2221 | */ |
| 2222 | |
| 2223 | static struct omap_hwmod_class omap44xx_mpu_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 2224 | .name = "mpu", |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 2225 | }; |
| 2226 | |
| 2227 | /* mpu */ |
| 2228 | static struct omap_hwmod_irq_info omap44xx_mpu_irqs[] = { |
| 2229 | { .name = "pl310", .irq = 0 + OMAP44XX_IRQ_GIC_START }, |
| 2230 | { .name = "cti0", .irq = 1 + OMAP44XX_IRQ_GIC_START }, |
| 2231 | { .name = "cti1", .irq = 2 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2232 | { .irq = -1 } |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 2233 | }; |
| 2234 | |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 2235 | static struct omap_hwmod omap44xx_mpu_hwmod = { |
| 2236 | .name = "mpu", |
| 2237 | .class = &omap44xx_mpu_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2238 | .clkdm_name = "mpuss_clkdm", |
Benoit Cousson | 7ecc5373 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 2239 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 2240 | .mpu_irqs = omap44xx_mpu_irqs, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 2241 | .main_clk = "dpll_mpu_m2_ck", |
| 2242 | .prcm = { |
| 2243 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2244 | .clkctrl_offs = OMAP4_CM_MPU_MPU_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2245 | .context_offs = OMAP4_RM_MPU_MPU_CONTEXT_OFFSET, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 2246 | }, |
| 2247 | }, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 2248 | }; |
| 2249 | |
Benoit Cousson | 92b18d1 | 2010-09-23 20:02:41 +0530 | [diff] [blame] | 2250 | /* |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2251 | * 'smartreflex' class |
| 2252 | * smartreflex module (monitor silicon performance and outputs a measure of |
| 2253 | * performance error) |
| 2254 | */ |
| 2255 | |
| 2256 | /* The IP is not compliant to type1 / type2 scheme */ |
| 2257 | static struct omap_hwmod_sysc_fields omap_hwmod_sysc_type_smartreflex = { |
| 2258 | .sidle_shift = 24, |
| 2259 | .enwkup_shift = 26, |
| 2260 | }; |
| 2261 | |
| 2262 | static struct omap_hwmod_class_sysconfig omap44xx_smartreflex_sysc = { |
| 2263 | .sysc_offs = 0x0038, |
| 2264 | .sysc_flags = (SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE), |
| 2265 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 2266 | SIDLE_SMART_WKUP), |
| 2267 | .sysc_fields = &omap_hwmod_sysc_type_smartreflex, |
| 2268 | }; |
| 2269 | |
| 2270 | static struct omap_hwmod_class omap44xx_smartreflex_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 2271 | .name = "smartreflex", |
| 2272 | .sysc = &omap44xx_smartreflex_sysc, |
| 2273 | .rev = 2, |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2274 | }; |
| 2275 | |
| 2276 | /* smartreflex_core */ |
Shweta Gulati | cea6b94 | 2012-02-29 23:33:37 +0100 | [diff] [blame] | 2277 | static struct omap_smartreflex_dev_attr smartreflex_core_dev_attr = { |
| 2278 | .sensor_voltdm_name = "core", |
| 2279 | }; |
| 2280 | |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2281 | static struct omap_hwmod_irq_info omap44xx_smartreflex_core_irqs[] = { |
| 2282 | { .irq = 19 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2283 | { .irq = -1 } |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2284 | }; |
| 2285 | |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2286 | static struct omap_hwmod omap44xx_smartreflex_core_hwmod = { |
| 2287 | .name = "smartreflex_core", |
| 2288 | .class = &omap44xx_smartreflex_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2289 | .clkdm_name = "l4_ao_clkdm", |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2290 | .mpu_irqs = omap44xx_smartreflex_core_irqs, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2291 | |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2292 | .main_clk = "smartreflex_core_fck", |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2293 | .prcm = { |
| 2294 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2295 | .clkctrl_offs = OMAP4_CM_ALWON_SR_CORE_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2296 | .context_offs = OMAP4_RM_ALWON_SR_CORE_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2297 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2298 | }, |
| 2299 | }, |
Shweta Gulati | cea6b94 | 2012-02-29 23:33:37 +0100 | [diff] [blame] | 2300 | .dev_attr = &smartreflex_core_dev_attr, |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2301 | }; |
| 2302 | |
| 2303 | /* smartreflex_iva */ |
Shweta Gulati | cea6b94 | 2012-02-29 23:33:37 +0100 | [diff] [blame] | 2304 | static struct omap_smartreflex_dev_attr smartreflex_iva_dev_attr = { |
| 2305 | .sensor_voltdm_name = "iva", |
| 2306 | }; |
| 2307 | |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2308 | static struct omap_hwmod_irq_info omap44xx_smartreflex_iva_irqs[] = { |
| 2309 | { .irq = 102 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2310 | { .irq = -1 } |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2311 | }; |
| 2312 | |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2313 | static struct omap_hwmod omap44xx_smartreflex_iva_hwmod = { |
| 2314 | .name = "smartreflex_iva", |
| 2315 | .class = &omap44xx_smartreflex_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2316 | .clkdm_name = "l4_ao_clkdm", |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2317 | .mpu_irqs = omap44xx_smartreflex_iva_irqs, |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2318 | .main_clk = "smartreflex_iva_fck", |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2319 | .prcm = { |
| 2320 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2321 | .clkctrl_offs = OMAP4_CM_ALWON_SR_IVA_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2322 | .context_offs = OMAP4_RM_ALWON_SR_IVA_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2323 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2324 | }, |
| 2325 | }, |
Shweta Gulati | cea6b94 | 2012-02-29 23:33:37 +0100 | [diff] [blame] | 2326 | .dev_attr = &smartreflex_iva_dev_attr, |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2327 | }; |
| 2328 | |
| 2329 | /* smartreflex_mpu */ |
Shweta Gulati | cea6b94 | 2012-02-29 23:33:37 +0100 | [diff] [blame] | 2330 | static struct omap_smartreflex_dev_attr smartreflex_mpu_dev_attr = { |
| 2331 | .sensor_voltdm_name = "mpu", |
| 2332 | }; |
| 2333 | |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2334 | static struct omap_hwmod_irq_info omap44xx_smartreflex_mpu_irqs[] = { |
| 2335 | { .irq = 18 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2336 | { .irq = -1 } |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2337 | }; |
| 2338 | |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2339 | static struct omap_hwmod omap44xx_smartreflex_mpu_hwmod = { |
| 2340 | .name = "smartreflex_mpu", |
| 2341 | .class = &omap44xx_smartreflex_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2342 | .clkdm_name = "l4_ao_clkdm", |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2343 | .mpu_irqs = omap44xx_smartreflex_mpu_irqs, |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2344 | .main_clk = "smartreflex_mpu_fck", |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2345 | .prcm = { |
| 2346 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2347 | .clkctrl_offs = OMAP4_CM_ALWON_SR_MPU_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2348 | .context_offs = OMAP4_RM_ALWON_SR_MPU_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2349 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2350 | }, |
| 2351 | }, |
Shweta Gulati | cea6b94 | 2012-02-29 23:33:37 +0100 | [diff] [blame] | 2352 | .dev_attr = &smartreflex_mpu_dev_attr, |
Benoit Cousson | 1f6a717 | 2010-12-23 22:30:30 +0000 | [diff] [blame] | 2353 | }; |
| 2354 | |
| 2355 | /* |
Benoit Cousson | d11c217 | 2011-02-02 12:04:36 +0000 | [diff] [blame] | 2356 | * 'spinlock' class |
| 2357 | * spinlock provides hardware assistance for synchronizing the processes |
| 2358 | * running on multiple processors |
| 2359 | */ |
| 2360 | |
| 2361 | static struct omap_hwmod_class_sysconfig omap44xx_spinlock_sysc = { |
| 2362 | .rev_offs = 0x0000, |
| 2363 | .sysc_offs = 0x0010, |
| 2364 | .syss_offs = 0x0014, |
| 2365 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | |
| 2366 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SIDLEMODE | |
| 2367 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 2368 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 2369 | SIDLE_SMART_WKUP), |
| 2370 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 2371 | }; |
| 2372 | |
| 2373 | static struct omap_hwmod_class omap44xx_spinlock_hwmod_class = { |
| 2374 | .name = "spinlock", |
| 2375 | .sysc = &omap44xx_spinlock_sysc, |
| 2376 | }; |
| 2377 | |
| 2378 | /* spinlock */ |
Benoit Cousson | d11c217 | 2011-02-02 12:04:36 +0000 | [diff] [blame] | 2379 | static struct omap_hwmod omap44xx_spinlock_hwmod = { |
| 2380 | .name = "spinlock", |
| 2381 | .class = &omap44xx_spinlock_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2382 | .clkdm_name = "l4_cfg_clkdm", |
Benoit Cousson | d11c217 | 2011-02-02 12:04:36 +0000 | [diff] [blame] | 2383 | .prcm = { |
| 2384 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2385 | .clkctrl_offs = OMAP4_CM_L4CFG_HW_SEM_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2386 | .context_offs = OMAP4_RM_L4CFG_HW_SEM_CONTEXT_OFFSET, |
Benoit Cousson | d11c217 | 2011-02-02 12:04:36 +0000 | [diff] [blame] | 2387 | }, |
| 2388 | }, |
Benoit Cousson | d11c217 | 2011-02-02 12:04:36 +0000 | [diff] [blame] | 2389 | }; |
| 2390 | |
| 2391 | /* |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2392 | * 'timer' class |
| 2393 | * general purpose timer module with accurate 1ms tick |
| 2394 | * This class contains several variants: ['timer_1ms', 'timer'] |
| 2395 | */ |
| 2396 | |
| 2397 | static struct omap_hwmod_class_sysconfig omap44xx_timer_1ms_sysc = { |
| 2398 | .rev_offs = 0x0000, |
| 2399 | .sysc_offs = 0x0010, |
| 2400 | .syss_offs = 0x0014, |
| 2401 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_CLOCKACTIVITY | |
| 2402 | SYSC_HAS_EMUFREE | SYSC_HAS_ENAWAKEUP | |
| 2403 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 2404 | SYSS_HAS_RESET_STATUS), |
| 2405 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 2406 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 2407 | }; |
| 2408 | |
| 2409 | static struct omap_hwmod_class omap44xx_timer_1ms_hwmod_class = { |
| 2410 | .name = "timer", |
| 2411 | .sysc = &omap44xx_timer_1ms_sysc, |
| 2412 | }; |
| 2413 | |
| 2414 | static struct omap_hwmod_class_sysconfig omap44xx_timer_sysc = { |
| 2415 | .rev_offs = 0x0000, |
| 2416 | .sysc_offs = 0x0010, |
| 2417 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_RESET_STATUS | |
| 2418 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET), |
| 2419 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 2420 | SIDLE_SMART_WKUP), |
| 2421 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 2422 | }; |
| 2423 | |
| 2424 | static struct omap_hwmod_class omap44xx_timer_hwmod_class = { |
| 2425 | .name = "timer", |
| 2426 | .sysc = &omap44xx_timer_sysc, |
| 2427 | }; |
| 2428 | |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2429 | /* always-on timers dev attribute */ |
| 2430 | static struct omap_timer_capability_dev_attr capability_alwon_dev_attr = { |
| 2431 | .timer_capability = OMAP_TIMER_ALWON, |
| 2432 | }; |
| 2433 | |
| 2434 | /* pwm timers dev attribute */ |
| 2435 | static struct omap_timer_capability_dev_attr capability_pwm_dev_attr = { |
| 2436 | .timer_capability = OMAP_TIMER_HAS_PWM, |
| 2437 | }; |
| 2438 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2439 | /* timer1 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2440 | static struct omap_hwmod_irq_info omap44xx_timer1_irqs[] = { |
| 2441 | { .irq = 37 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2442 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2443 | }; |
| 2444 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2445 | static struct omap_hwmod omap44xx_timer1_hwmod = { |
| 2446 | .name = "timer1", |
| 2447 | .class = &omap44xx_timer_1ms_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2448 | .clkdm_name = "l4_wkup_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2449 | .mpu_irqs = omap44xx_timer1_irqs, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2450 | .main_clk = "timer1_fck", |
| 2451 | .prcm = { |
| 2452 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2453 | .clkctrl_offs = OMAP4_CM_WKUP_TIMER1_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2454 | .context_offs = OMAP4_RM_WKUP_TIMER1_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2455 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2456 | }, |
| 2457 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2458 | .dev_attr = &capability_alwon_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2459 | }; |
| 2460 | |
| 2461 | /* timer2 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2462 | static struct omap_hwmod_irq_info omap44xx_timer2_irqs[] = { |
| 2463 | { .irq = 38 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2464 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2465 | }; |
| 2466 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2467 | static struct omap_hwmod omap44xx_timer2_hwmod = { |
| 2468 | .name = "timer2", |
| 2469 | .class = &omap44xx_timer_1ms_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2470 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2471 | .mpu_irqs = omap44xx_timer2_irqs, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2472 | .main_clk = "timer2_fck", |
| 2473 | .prcm = { |
| 2474 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2475 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER2_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2476 | .context_offs = OMAP4_RM_L4PER_DMTIMER2_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2477 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2478 | }, |
| 2479 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2480 | .dev_attr = &capability_alwon_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2481 | }; |
| 2482 | |
| 2483 | /* timer3 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2484 | static struct omap_hwmod_irq_info omap44xx_timer3_irqs[] = { |
| 2485 | { .irq = 39 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2486 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2487 | }; |
| 2488 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2489 | static struct omap_hwmod omap44xx_timer3_hwmod = { |
| 2490 | .name = "timer3", |
| 2491 | .class = &omap44xx_timer_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2492 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2493 | .mpu_irqs = omap44xx_timer3_irqs, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2494 | .main_clk = "timer3_fck", |
| 2495 | .prcm = { |
| 2496 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2497 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER3_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2498 | .context_offs = OMAP4_RM_L4PER_DMTIMER3_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2499 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2500 | }, |
| 2501 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2502 | .dev_attr = &capability_alwon_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2503 | }; |
| 2504 | |
| 2505 | /* timer4 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2506 | static struct omap_hwmod_irq_info omap44xx_timer4_irqs[] = { |
| 2507 | { .irq = 40 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2508 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2509 | }; |
| 2510 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2511 | static struct omap_hwmod omap44xx_timer4_hwmod = { |
| 2512 | .name = "timer4", |
| 2513 | .class = &omap44xx_timer_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2514 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2515 | .mpu_irqs = omap44xx_timer4_irqs, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2516 | .main_clk = "timer4_fck", |
| 2517 | .prcm = { |
| 2518 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2519 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER4_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2520 | .context_offs = OMAP4_RM_L4PER_DMTIMER4_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2521 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2522 | }, |
| 2523 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2524 | .dev_attr = &capability_alwon_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2525 | }; |
| 2526 | |
| 2527 | /* timer5 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2528 | static struct omap_hwmod_irq_info omap44xx_timer5_irqs[] = { |
| 2529 | { .irq = 41 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2530 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2531 | }; |
| 2532 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2533 | static struct omap_hwmod omap44xx_timer5_hwmod = { |
| 2534 | .name = "timer5", |
| 2535 | .class = &omap44xx_timer_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2536 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2537 | .mpu_irqs = omap44xx_timer5_irqs, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2538 | .main_clk = "timer5_fck", |
| 2539 | .prcm = { |
| 2540 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2541 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER5_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2542 | .context_offs = OMAP4_RM_ABE_TIMER5_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2543 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2544 | }, |
| 2545 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2546 | .dev_attr = &capability_alwon_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2547 | }; |
| 2548 | |
| 2549 | /* timer6 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2550 | static struct omap_hwmod_irq_info omap44xx_timer6_irqs[] = { |
| 2551 | { .irq = 42 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2552 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2553 | }; |
| 2554 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2555 | static struct omap_hwmod omap44xx_timer6_hwmod = { |
| 2556 | .name = "timer6", |
| 2557 | .class = &omap44xx_timer_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2558 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2559 | .mpu_irqs = omap44xx_timer6_irqs, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2560 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2561 | .main_clk = "timer6_fck", |
| 2562 | .prcm = { |
| 2563 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2564 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER6_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2565 | .context_offs = OMAP4_RM_ABE_TIMER6_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2566 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2567 | }, |
| 2568 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2569 | .dev_attr = &capability_alwon_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2570 | }; |
| 2571 | |
| 2572 | /* timer7 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2573 | static struct omap_hwmod_irq_info omap44xx_timer7_irqs[] = { |
| 2574 | { .irq = 43 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2575 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2576 | }; |
| 2577 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2578 | static struct omap_hwmod omap44xx_timer7_hwmod = { |
| 2579 | .name = "timer7", |
| 2580 | .class = &omap44xx_timer_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2581 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2582 | .mpu_irqs = omap44xx_timer7_irqs, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2583 | .main_clk = "timer7_fck", |
| 2584 | .prcm = { |
| 2585 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2586 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER7_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2587 | .context_offs = OMAP4_RM_ABE_TIMER7_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2588 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2589 | }, |
| 2590 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2591 | .dev_attr = &capability_alwon_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2592 | }; |
| 2593 | |
| 2594 | /* timer8 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2595 | static struct omap_hwmod_irq_info omap44xx_timer8_irqs[] = { |
| 2596 | { .irq = 44 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2597 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2598 | }; |
| 2599 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2600 | static struct omap_hwmod omap44xx_timer8_hwmod = { |
| 2601 | .name = "timer8", |
| 2602 | .class = &omap44xx_timer_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2603 | .clkdm_name = "abe_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2604 | .mpu_irqs = omap44xx_timer8_irqs, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2605 | .main_clk = "timer8_fck", |
| 2606 | .prcm = { |
| 2607 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2608 | .clkctrl_offs = OMAP4_CM1_ABE_TIMER8_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2609 | .context_offs = OMAP4_RM_ABE_TIMER8_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2610 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2611 | }, |
| 2612 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2613 | .dev_attr = &capability_pwm_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2614 | }; |
| 2615 | |
| 2616 | /* timer9 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2617 | static struct omap_hwmod_irq_info omap44xx_timer9_irqs[] = { |
| 2618 | { .irq = 45 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2619 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2620 | }; |
| 2621 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2622 | static struct omap_hwmod omap44xx_timer9_hwmod = { |
| 2623 | .name = "timer9", |
| 2624 | .class = &omap44xx_timer_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2625 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2626 | .mpu_irqs = omap44xx_timer9_irqs, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2627 | .main_clk = "timer9_fck", |
| 2628 | .prcm = { |
| 2629 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2630 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER9_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2631 | .context_offs = OMAP4_RM_L4PER_DMTIMER9_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2632 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2633 | }, |
| 2634 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2635 | .dev_attr = &capability_pwm_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2636 | }; |
| 2637 | |
| 2638 | /* timer10 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2639 | static struct omap_hwmod_irq_info omap44xx_timer10_irqs[] = { |
| 2640 | { .irq = 46 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2641 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2642 | }; |
| 2643 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2644 | static struct omap_hwmod omap44xx_timer10_hwmod = { |
| 2645 | .name = "timer10", |
| 2646 | .class = &omap44xx_timer_1ms_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2647 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2648 | .mpu_irqs = omap44xx_timer10_irqs, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2649 | .main_clk = "timer10_fck", |
| 2650 | .prcm = { |
| 2651 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2652 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER10_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2653 | .context_offs = OMAP4_RM_L4PER_DMTIMER10_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2654 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2655 | }, |
| 2656 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2657 | .dev_attr = &capability_pwm_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2658 | }; |
| 2659 | |
| 2660 | /* timer11 */ |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2661 | static struct omap_hwmod_irq_info omap44xx_timer11_irqs[] = { |
| 2662 | { .irq = 47 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2663 | { .irq = -1 } |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2664 | }; |
| 2665 | |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2666 | static struct omap_hwmod omap44xx_timer11_hwmod = { |
| 2667 | .name = "timer11", |
| 2668 | .class = &omap44xx_timer_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2669 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2670 | .mpu_irqs = omap44xx_timer11_irqs, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2671 | .main_clk = "timer11_fck", |
| 2672 | .prcm = { |
| 2673 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2674 | .clkctrl_offs = OMAP4_CM_L4PER_DMTIMER11_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2675 | .context_offs = OMAP4_RM_L4PER_DMTIMER11_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2676 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2677 | }, |
| 2678 | }, |
Tarun Kanti DebBarma | c345c8b | 2011-09-20 17:00:18 +0530 | [diff] [blame] | 2679 | .dev_attr = &capability_pwm_dev_attr, |
Benoit Cousson | 35d1a66 | 2011-02-11 11:17:14 +0000 | [diff] [blame] | 2680 | }; |
| 2681 | |
| 2682 | /* |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2683 | * 'uart' class |
| 2684 | * universal asynchronous receiver/transmitter (uart) |
| 2685 | */ |
| 2686 | |
| 2687 | static struct omap_hwmod_class_sysconfig omap44xx_uart_sysc = { |
| 2688 | .rev_offs = 0x0050, |
| 2689 | .sysc_offs = 0x0054, |
| 2690 | .syss_offs = 0x0058, |
Benoit Cousson | 3b54baa | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 2691 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
Benoit Cousson | 0cfe875 | 2010-12-21 21:08:33 -0700 | [diff] [blame] | 2692 | SYSC_HAS_SIDLEMODE | SYSC_HAS_SOFTRESET | |
| 2693 | SYSS_HAS_RESET_STATUS), |
Benoit Cousson | 7cffa6b | 2010-12-21 21:31:28 -0700 | [diff] [blame] | 2694 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 2695 | SIDLE_SMART_WKUP), |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2696 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 2697 | }; |
| 2698 | |
| 2699 | static struct omap_hwmod_class omap44xx_uart_hwmod_class = { |
Benoit Cousson | fe13471 | 2010-12-23 22:30:32 +0000 | [diff] [blame] | 2700 | .name = "uart", |
| 2701 | .sysc = &omap44xx_uart_sysc, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2702 | }; |
| 2703 | |
| 2704 | /* uart1 */ |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2705 | static struct omap_hwmod_irq_info omap44xx_uart1_irqs[] = { |
| 2706 | { .irq = 72 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2707 | { .irq = -1 } |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2708 | }; |
| 2709 | |
| 2710 | static struct omap_hwmod_dma_info omap44xx_uart1_sdma_reqs[] = { |
| 2711 | { .name = "tx", .dma_req = 48 + OMAP44XX_DMA_REQ_START }, |
| 2712 | { .name = "rx", .dma_req = 49 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 2713 | { .dma_req = -1 } |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2714 | }; |
| 2715 | |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2716 | static struct omap_hwmod omap44xx_uart1_hwmod = { |
| 2717 | .name = "uart1", |
| 2718 | .class = &omap44xx_uart_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2719 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2720 | .mpu_irqs = omap44xx_uart1_irqs, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2721 | .sdma_reqs = omap44xx_uart1_sdma_reqs, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2722 | .main_clk = "uart1_fck", |
| 2723 | .prcm = { |
| 2724 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2725 | .clkctrl_offs = OMAP4_CM_L4PER_UART1_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2726 | .context_offs = OMAP4_RM_L4PER_UART1_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2727 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2728 | }, |
| 2729 | }, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2730 | }; |
| 2731 | |
| 2732 | /* uart2 */ |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2733 | static struct omap_hwmod_irq_info omap44xx_uart2_irqs[] = { |
| 2734 | { .irq = 73 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2735 | { .irq = -1 } |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2736 | }; |
| 2737 | |
| 2738 | static struct omap_hwmod_dma_info omap44xx_uart2_sdma_reqs[] = { |
| 2739 | { .name = "tx", .dma_req = 50 + OMAP44XX_DMA_REQ_START }, |
| 2740 | { .name = "rx", .dma_req = 51 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 2741 | { .dma_req = -1 } |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2742 | }; |
| 2743 | |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2744 | static struct omap_hwmod omap44xx_uart2_hwmod = { |
| 2745 | .name = "uart2", |
| 2746 | .class = &omap44xx_uart_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2747 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2748 | .mpu_irqs = omap44xx_uart2_irqs, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2749 | .sdma_reqs = omap44xx_uart2_sdma_reqs, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2750 | .main_clk = "uart2_fck", |
| 2751 | .prcm = { |
| 2752 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2753 | .clkctrl_offs = OMAP4_CM_L4PER_UART2_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2754 | .context_offs = OMAP4_RM_L4PER_UART2_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2755 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2756 | }, |
| 2757 | }, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2758 | }; |
| 2759 | |
| 2760 | /* uart3 */ |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2761 | static struct omap_hwmod_irq_info omap44xx_uart3_irqs[] = { |
| 2762 | { .irq = 74 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2763 | { .irq = -1 } |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2764 | }; |
| 2765 | |
| 2766 | static struct omap_hwmod_dma_info omap44xx_uart3_sdma_reqs[] = { |
| 2767 | { .name = "tx", .dma_req = 52 + OMAP44XX_DMA_REQ_START }, |
| 2768 | { .name = "rx", .dma_req = 53 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 2769 | { .dma_req = -1 } |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2770 | }; |
| 2771 | |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2772 | static struct omap_hwmod omap44xx_uart3_hwmod = { |
| 2773 | .name = "uart3", |
| 2774 | .class = &omap44xx_uart_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2775 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | 7ecc5373 | 2011-07-09 19:14:28 -0600 | [diff] [blame] | 2776 | .flags = HWMOD_INIT_NO_IDLE | HWMOD_INIT_NO_RESET, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2777 | .mpu_irqs = omap44xx_uart3_irqs, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2778 | .sdma_reqs = omap44xx_uart3_sdma_reqs, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2779 | .main_clk = "uart3_fck", |
| 2780 | .prcm = { |
| 2781 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2782 | .clkctrl_offs = OMAP4_CM_L4PER_UART3_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2783 | .context_offs = OMAP4_RM_L4PER_UART3_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2784 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2785 | }, |
| 2786 | }, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2787 | }; |
| 2788 | |
| 2789 | /* uart4 */ |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2790 | static struct omap_hwmod_irq_info omap44xx_uart4_irqs[] = { |
| 2791 | { .irq = 70 + OMAP44XX_IRQ_GIC_START }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 2792 | { .irq = -1 } |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2793 | }; |
| 2794 | |
| 2795 | static struct omap_hwmod_dma_info omap44xx_uart4_sdma_reqs[] = { |
| 2796 | { .name = "tx", .dma_req = 54 + OMAP44XX_DMA_REQ_START }, |
| 2797 | { .name = "rx", .dma_req = 55 + OMAP44XX_DMA_REQ_START }, |
Paul Walmsley | bc61495 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 2798 | { .dma_req = -1 } |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2799 | }; |
| 2800 | |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2801 | static struct omap_hwmod omap44xx_uart4_hwmod = { |
| 2802 | .name = "uart4", |
| 2803 | .class = &omap44xx_uart_hwmod_class, |
Benoit Cousson | a5322c6 | 2011-07-10 05:56:29 -0600 | [diff] [blame] | 2804 | .clkdm_name = "l4_per_clkdm", |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2805 | .mpu_irqs = omap44xx_uart4_irqs, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2806 | .sdma_reqs = omap44xx_uart4_sdma_reqs, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2807 | .main_clk = "uart4_fck", |
| 2808 | .prcm = { |
| 2809 | .omap4 = { |
Benoit Cousson | d0f0631 | 2011-07-10 05:56:30 -0600 | [diff] [blame] | 2810 | .clkctrl_offs = OMAP4_CM_L4PER_UART4_CLKCTRL_OFFSET, |
Benoit Cousson | 27bb00b | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2811 | .context_offs = OMAP4_RM_L4PER_UART4_CONTEXT_OFFSET, |
Benoit Cousson | 03fdefe5 | 2011-07-10 05:56:32 -0600 | [diff] [blame] | 2812 | .modulemode = MODULEMODE_SWCTRL, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2813 | }, |
| 2814 | }, |
Benoit Cousson | db12ba5 | 2010-09-27 20:19:19 +0530 | [diff] [blame] | 2815 | }; |
| 2816 | |
Benoit Cousson | 9780a9c | 2010-12-07 16:26:57 -0800 | [diff] [blame] | 2817 | /* |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 2818 | * 'usb_host_hs' class |
| 2819 | * high-speed multi-port usb host controller |
| 2820 | */ |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 2821 | |
| 2822 | static struct omap_hwmod_class_sysconfig omap44xx_usb_host_hs_sysc = { |
| 2823 | .rev_offs = 0x0000, |
| 2824 | .sysc_offs = 0x0010, |
| 2825 | .syss_offs = 0x0014, |
| 2826 | .sysc_flags = (SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | |
| 2827 | SYSC_HAS_SOFTRESET), |
| 2828 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 2829 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | |
| 2830 | MSTANDBY_SMART | MSTANDBY_SMART_WKUP), |
| 2831 | .sysc_fields = &omap_hwmod_sysc_type2, |
| 2832 | }; |
| 2833 | |
| 2834 | static struct omap_hwmod_class omap44xx_usb_host_hs_hwmod_class = { |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 2835 | .name = "usb_host_hs", |
| 2836 | .sysc = &omap44xx_usb_host_hs_sysc, |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 2837 | }; |
| 2838 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 2839 | /* usb_host_hs */ |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 2840 | static struct omap_hwmod_irq_info omap44xx_usb_host_hs_irqs[] = { |
| 2841 | { .name = "ohci-irq", .irq = 76 + OMAP44XX_IRQ_GIC_START }, |
| 2842 | { .name = "ehci-irq", .irq = 77 + OMAP44XX_IRQ_GIC_START }, |
| 2843 | { .irq = -1 } |
| 2844 | }; |
| 2845 | |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 2846 | static struct omap_hwmod omap44xx_usb_host_hs_hwmod = { |
| 2847 | .name = "usb_host_hs", |
| 2848 | .class = &omap44xx_usb_host_hs_hwmod_class, |
| 2849 | .clkdm_name = "l3_init_clkdm", |
| 2850 | .main_clk = "usb_host_hs_fck", |
| 2851 | .prcm = { |
| 2852 | .omap4 = { |
| 2853 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_HOST_CLKCTRL_OFFSET, |
| 2854 | .context_offs = OMAP4_RM_L3INIT_USB_HOST_CONTEXT_OFFSET, |
| 2855 | .modulemode = MODULEMODE_SWCTRL, |
| 2856 | }, |
| 2857 | }, |
| 2858 | .mpu_irqs = omap44xx_usb_host_hs_irqs, |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 2859 | |
| 2860 | /* |
| 2861 | * Errata: USBHOST Configured In Smart-Idle Can Lead To a Deadlock |
| 2862 | * id: i660 |
| 2863 | * |
| 2864 | * Description: |
| 2865 | * In the following configuration : |
| 2866 | * - USBHOST module is set to smart-idle mode |
| 2867 | * - PRCM asserts idle_req to the USBHOST module ( This typically |
| 2868 | * happens when the system is going to a low power mode : all ports |
| 2869 | * have been suspended, the master part of the USBHOST module has |
| 2870 | * entered the standby state, and SW has cut the functional clocks) |
| 2871 | * - an USBHOST interrupt occurs before the module is able to answer |
| 2872 | * idle_ack, typically a remote wakeup IRQ. |
| 2873 | * Then the USB HOST module will enter a deadlock situation where it |
| 2874 | * is no more accessible nor functional. |
| 2875 | * |
| 2876 | * Workaround: |
| 2877 | * Don't use smart idle; use only force idle, hence HWMOD_SWSUP_SIDLE |
| 2878 | */ |
| 2879 | |
| 2880 | /* |
| 2881 | * Errata: USB host EHCI may stall when entering smart-standby mode |
| 2882 | * Id: i571 |
| 2883 | * |
| 2884 | * Description: |
| 2885 | * When the USBHOST module is set to smart-standby mode, and when it is |
| 2886 | * ready to enter the standby state (i.e. all ports are suspended and |
| 2887 | * all attached devices are in suspend mode), then it can wrongly assert |
| 2888 | * the Mstandby signal too early while there are still some residual OCP |
| 2889 | * transactions ongoing. If this condition occurs, the internal state |
| 2890 | * machine may go to an undefined state and the USB link may be stuck |
| 2891 | * upon the next resume. |
| 2892 | * |
| 2893 | * Workaround: |
| 2894 | * Don't use smart standby; use only force standby, |
| 2895 | * hence HWMOD_SWSUP_MSTANDBY |
| 2896 | */ |
| 2897 | |
| 2898 | /* |
| 2899 | * During system boot; If the hwmod framework resets the module |
| 2900 | * the module will have smart idle settings; which can lead to deadlock |
| 2901 | * (above Errata Id:i660); so, dont reset the module during boot; |
| 2902 | * Use HWMOD_INIT_NO_RESET. |
| 2903 | */ |
| 2904 | |
| 2905 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY | |
| 2906 | HWMOD_INIT_NO_RESET, |
| 2907 | }; |
| 2908 | |
| 2909 | /* |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 2910 | * 'usb_otg_hs' class |
| 2911 | * high-speed on-the-go universal serial bus (usb_otg_hs) controller |
| 2912 | */ |
| 2913 | |
| 2914 | static struct omap_hwmod_class_sysconfig omap44xx_usb_otg_hs_sysc = { |
| 2915 | .rev_offs = 0x0400, |
| 2916 | .sysc_offs = 0x0404, |
| 2917 | .syss_offs = 0x0408, |
| 2918 | .sysc_flags = (SYSC_HAS_AUTOIDLE | SYSC_HAS_ENAWAKEUP | |
| 2919 | SYSC_HAS_MIDLEMODE | SYSC_HAS_SIDLEMODE | |
| 2920 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 2921 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 2922 | SIDLE_SMART_WKUP | MSTANDBY_FORCE | MSTANDBY_NO | |
| 2923 | MSTANDBY_SMART), |
| 2924 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 2925 | }; |
| 2926 | |
| 2927 | static struct omap_hwmod_class omap44xx_usb_otg_hs_hwmod_class = { |
| 2928 | .name = "usb_otg_hs", |
| 2929 | .sysc = &omap44xx_usb_otg_hs_sysc, |
| 2930 | }; |
| 2931 | |
| 2932 | /* usb_otg_hs */ |
| 2933 | static struct omap_hwmod_irq_info omap44xx_usb_otg_hs_irqs[] = { |
| 2934 | { .name = "mc", .irq = 92 + OMAP44XX_IRQ_GIC_START }, |
| 2935 | { .name = "dma", .irq = 93 + OMAP44XX_IRQ_GIC_START }, |
| 2936 | { .irq = -1 } |
| 2937 | }; |
| 2938 | |
| 2939 | static struct omap_hwmod_opt_clk usb_otg_hs_opt_clks[] = { |
| 2940 | { .role = "xclk", .clk = "usb_otg_hs_xclk" }, |
| 2941 | }; |
| 2942 | |
| 2943 | static struct omap_hwmod omap44xx_usb_otg_hs_hwmod = { |
| 2944 | .name = "usb_otg_hs", |
| 2945 | .class = &omap44xx_usb_otg_hs_hwmod_class, |
| 2946 | .clkdm_name = "l3_init_clkdm", |
| 2947 | .flags = HWMOD_SWSUP_SIDLE | HWMOD_SWSUP_MSTANDBY, |
| 2948 | .mpu_irqs = omap44xx_usb_otg_hs_irqs, |
| 2949 | .main_clk = "usb_otg_hs_ick", |
| 2950 | .prcm = { |
| 2951 | .omap4 = { |
| 2952 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_OTG_CLKCTRL_OFFSET, |
| 2953 | .context_offs = OMAP4_RM_L3INIT_USB_OTG_CONTEXT_OFFSET, |
| 2954 | .modulemode = MODULEMODE_HWCTRL, |
| 2955 | }, |
| 2956 | }, |
| 2957 | .opt_clks = usb_otg_hs_opt_clks, |
| 2958 | .opt_clks_cnt = ARRAY_SIZE(usb_otg_hs_opt_clks), |
| 2959 | }; |
| 2960 | |
| 2961 | /* |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 2962 | * 'usb_tll_hs' class |
| 2963 | * usb_tll_hs module is the adapter on the usb_host_hs ports |
| 2964 | */ |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 2965 | |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 2966 | static struct omap_hwmod_class_sysconfig omap44xx_usb_tll_hs_sysc = { |
| 2967 | .rev_offs = 0x0000, |
| 2968 | .sysc_offs = 0x0010, |
| 2969 | .syss_offs = 0x0014, |
| 2970 | .sysc_flags = (SYSC_HAS_CLOCKACTIVITY | SYSC_HAS_SIDLEMODE | |
| 2971 | SYSC_HAS_ENAWAKEUP | SYSC_HAS_SOFTRESET | |
| 2972 | SYSC_HAS_AUTOIDLE), |
| 2973 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART), |
| 2974 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 2975 | }; |
| 2976 | |
| 2977 | static struct omap_hwmod_class omap44xx_usb_tll_hs_hwmod_class = { |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 2978 | .name = "usb_tll_hs", |
| 2979 | .sysc = &omap44xx_usb_tll_hs_sysc, |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 2980 | }; |
| 2981 | |
| 2982 | static struct omap_hwmod_irq_info omap44xx_usb_tll_hs_irqs[] = { |
| 2983 | { .name = "tll-irq", .irq = 78 + OMAP44XX_IRQ_GIC_START }, |
| 2984 | { .irq = -1 } |
| 2985 | }; |
| 2986 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 2987 | static struct omap_hwmod omap44xx_usb_tll_hs_hwmod = { |
| 2988 | .name = "usb_tll_hs", |
| 2989 | .class = &omap44xx_usb_tll_hs_hwmod_class, |
| 2990 | .clkdm_name = "l3_init_clkdm", |
| 2991 | .mpu_irqs = omap44xx_usb_tll_hs_irqs, |
| 2992 | .main_clk = "usb_tll_hs_ick", |
| 2993 | .prcm = { |
| 2994 | .omap4 = { |
| 2995 | .clkctrl_offs = OMAP4_CM_L3INIT_USB_TLL_CLKCTRL_OFFSET, |
| 2996 | .context_offs = OMAP4_RM_L3INIT_USB_TLL_CONTEXT_OFFSET, |
| 2997 | .modulemode = MODULEMODE_HWCTRL, |
| 2998 | }, |
| 2999 | }, |
| 3000 | }; |
| 3001 | |
| 3002 | /* |
| 3003 | * 'wd_timer' class |
| 3004 | * 32-bit watchdog upward counter that generates a pulse on the reset pin on |
| 3005 | * overflow condition |
| 3006 | */ |
| 3007 | |
| 3008 | static struct omap_hwmod_class_sysconfig omap44xx_wd_timer_sysc = { |
| 3009 | .rev_offs = 0x0000, |
| 3010 | .sysc_offs = 0x0010, |
| 3011 | .syss_offs = 0x0014, |
| 3012 | .sysc_flags = (SYSC_HAS_EMUFREE | SYSC_HAS_SIDLEMODE | |
| 3013 | SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
| 3014 | .idlemodes = (SIDLE_FORCE | SIDLE_NO | SIDLE_SMART | |
| 3015 | SIDLE_SMART_WKUP), |
| 3016 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 3017 | }; |
| 3018 | |
| 3019 | static struct omap_hwmod_class omap44xx_wd_timer_hwmod_class = { |
| 3020 | .name = "wd_timer", |
| 3021 | .sysc = &omap44xx_wd_timer_sysc, |
| 3022 | .pre_shutdown = &omap2_wd_timer_disable, |
| 3023 | }; |
| 3024 | |
| 3025 | /* wd_timer2 */ |
| 3026 | static struct omap_hwmod_irq_info omap44xx_wd_timer2_irqs[] = { |
| 3027 | { .irq = 80 + OMAP44XX_IRQ_GIC_START }, |
| 3028 | { .irq = -1 } |
| 3029 | }; |
| 3030 | |
| 3031 | static struct omap_hwmod omap44xx_wd_timer2_hwmod = { |
| 3032 | .name = "wd_timer2", |
| 3033 | .class = &omap44xx_wd_timer_hwmod_class, |
| 3034 | .clkdm_name = "l4_wkup_clkdm", |
| 3035 | .mpu_irqs = omap44xx_wd_timer2_irqs, |
| 3036 | .main_clk = "wd_timer2_fck", |
| 3037 | .prcm = { |
| 3038 | .omap4 = { |
| 3039 | .clkctrl_offs = OMAP4_CM_WKUP_WDT2_CLKCTRL_OFFSET, |
| 3040 | .context_offs = OMAP4_RM_WKUP_WDT2_CONTEXT_OFFSET, |
| 3041 | .modulemode = MODULEMODE_SWCTRL, |
| 3042 | }, |
| 3043 | }, |
| 3044 | }; |
| 3045 | |
| 3046 | /* wd_timer3 */ |
| 3047 | static struct omap_hwmod_irq_info omap44xx_wd_timer3_irqs[] = { |
| 3048 | { .irq = 36 + OMAP44XX_IRQ_GIC_START }, |
| 3049 | { .irq = -1 } |
| 3050 | }; |
| 3051 | |
| 3052 | static struct omap_hwmod omap44xx_wd_timer3_hwmod = { |
| 3053 | .name = "wd_timer3", |
| 3054 | .class = &omap44xx_wd_timer_hwmod_class, |
| 3055 | .clkdm_name = "abe_clkdm", |
| 3056 | .mpu_irqs = omap44xx_wd_timer3_irqs, |
| 3057 | .main_clk = "wd_timer3_fck", |
| 3058 | .prcm = { |
| 3059 | .omap4 = { |
| 3060 | .clkctrl_offs = OMAP4_CM1_ABE_WDT3_CLKCTRL_OFFSET, |
| 3061 | .context_offs = OMAP4_RM_ABE_WDT3_CONTEXT_OFFSET, |
| 3062 | .modulemode = MODULEMODE_SWCTRL, |
| 3063 | }, |
| 3064 | }, |
| 3065 | }; |
| 3066 | |
| 3067 | |
| 3068 | /* |
| 3069 | * interfaces |
| 3070 | */ |
| 3071 | |
| 3072 | /* l3_main_1 -> dmm */ |
| 3073 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__dmm = { |
| 3074 | .master = &omap44xx_l3_main_1_hwmod, |
| 3075 | .slave = &omap44xx_dmm_hwmod, |
| 3076 | .clk = "l3_div_ck", |
| 3077 | .user = OCP_USER_SDMA, |
| 3078 | }; |
| 3079 | |
| 3080 | static struct omap_hwmod_addr_space omap44xx_dmm_addrs[] = { |
| 3081 | { |
| 3082 | .pa_start = 0x4e000000, |
| 3083 | .pa_end = 0x4e0007ff, |
| 3084 | .flags = ADDR_TYPE_RT |
| 3085 | }, |
| 3086 | { } |
| 3087 | }; |
| 3088 | |
| 3089 | /* mpu -> dmm */ |
| 3090 | static struct omap_hwmod_ocp_if omap44xx_mpu__dmm = { |
| 3091 | .master = &omap44xx_mpu_hwmod, |
| 3092 | .slave = &omap44xx_dmm_hwmod, |
| 3093 | .clk = "l3_div_ck", |
| 3094 | .addr = omap44xx_dmm_addrs, |
| 3095 | .user = OCP_USER_MPU, |
| 3096 | }; |
| 3097 | |
| 3098 | /* dmm -> emif_fw */ |
| 3099 | static struct omap_hwmod_ocp_if omap44xx_dmm__emif_fw = { |
| 3100 | .master = &omap44xx_dmm_hwmod, |
| 3101 | .slave = &omap44xx_emif_fw_hwmod, |
| 3102 | .clk = "l3_div_ck", |
| 3103 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3104 | }; |
| 3105 | |
| 3106 | static struct omap_hwmod_addr_space omap44xx_emif_fw_addrs[] = { |
| 3107 | { |
| 3108 | .pa_start = 0x4a20c000, |
| 3109 | .pa_end = 0x4a20c0ff, |
| 3110 | .flags = ADDR_TYPE_RT |
| 3111 | }, |
| 3112 | { } |
| 3113 | }; |
| 3114 | |
| 3115 | /* l4_cfg -> emif_fw */ |
| 3116 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__emif_fw = { |
| 3117 | .master = &omap44xx_l4_cfg_hwmod, |
| 3118 | .slave = &omap44xx_emif_fw_hwmod, |
| 3119 | .clk = "l4_div_ck", |
| 3120 | .addr = omap44xx_emif_fw_addrs, |
| 3121 | .user = OCP_USER_MPU, |
| 3122 | }; |
| 3123 | |
| 3124 | /* iva -> l3_instr */ |
| 3125 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_instr = { |
| 3126 | .master = &omap44xx_iva_hwmod, |
| 3127 | .slave = &omap44xx_l3_instr_hwmod, |
| 3128 | .clk = "l3_div_ck", |
| 3129 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3130 | }; |
| 3131 | |
| 3132 | /* l3_main_3 -> l3_instr */ |
| 3133 | static struct omap_hwmod_ocp_if omap44xx_l3_main_3__l3_instr = { |
| 3134 | .master = &omap44xx_l3_main_3_hwmod, |
| 3135 | .slave = &omap44xx_l3_instr_hwmod, |
| 3136 | .clk = "l3_div_ck", |
| 3137 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3138 | }; |
| 3139 | |
| 3140 | /* dsp -> l3_main_1 */ |
| 3141 | static struct omap_hwmod_ocp_if omap44xx_dsp__l3_main_1 = { |
| 3142 | .master = &omap44xx_dsp_hwmod, |
| 3143 | .slave = &omap44xx_l3_main_1_hwmod, |
| 3144 | .clk = "l3_div_ck", |
| 3145 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3146 | }; |
| 3147 | |
| 3148 | /* dss -> l3_main_1 */ |
| 3149 | static struct omap_hwmod_ocp_if omap44xx_dss__l3_main_1 = { |
| 3150 | .master = &omap44xx_dss_hwmod, |
| 3151 | .slave = &omap44xx_l3_main_1_hwmod, |
| 3152 | .clk = "l3_div_ck", |
| 3153 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3154 | }; |
| 3155 | |
| 3156 | /* l3_main_2 -> l3_main_1 */ |
| 3157 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_1 = { |
| 3158 | .master = &omap44xx_l3_main_2_hwmod, |
| 3159 | .slave = &omap44xx_l3_main_1_hwmod, |
| 3160 | .clk = "l3_div_ck", |
| 3161 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3162 | }; |
| 3163 | |
| 3164 | /* l4_cfg -> l3_main_1 */ |
| 3165 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_1 = { |
| 3166 | .master = &omap44xx_l4_cfg_hwmod, |
| 3167 | .slave = &omap44xx_l3_main_1_hwmod, |
| 3168 | .clk = "l4_div_ck", |
| 3169 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3170 | }; |
| 3171 | |
| 3172 | /* mmc1 -> l3_main_1 */ |
| 3173 | static struct omap_hwmod_ocp_if omap44xx_mmc1__l3_main_1 = { |
| 3174 | .master = &omap44xx_mmc1_hwmod, |
| 3175 | .slave = &omap44xx_l3_main_1_hwmod, |
| 3176 | .clk = "l3_div_ck", |
| 3177 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3178 | }; |
| 3179 | |
| 3180 | /* mmc2 -> l3_main_1 */ |
| 3181 | static struct omap_hwmod_ocp_if omap44xx_mmc2__l3_main_1 = { |
| 3182 | .master = &omap44xx_mmc2_hwmod, |
| 3183 | .slave = &omap44xx_l3_main_1_hwmod, |
| 3184 | .clk = "l3_div_ck", |
| 3185 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3186 | }; |
| 3187 | |
| 3188 | static struct omap_hwmod_addr_space omap44xx_l3_main_1_addrs[] = { |
| 3189 | { |
| 3190 | .pa_start = 0x44000000, |
| 3191 | .pa_end = 0x44000fff, |
| 3192 | .flags = ADDR_TYPE_RT |
| 3193 | }, |
| 3194 | { } |
| 3195 | }; |
| 3196 | |
| 3197 | /* mpu -> l3_main_1 */ |
| 3198 | static struct omap_hwmod_ocp_if omap44xx_mpu__l3_main_1 = { |
| 3199 | .master = &omap44xx_mpu_hwmod, |
| 3200 | .slave = &omap44xx_l3_main_1_hwmod, |
| 3201 | .clk = "l3_div_ck", |
| 3202 | .addr = omap44xx_l3_main_1_addrs, |
| 3203 | .user = OCP_USER_MPU, |
| 3204 | }; |
| 3205 | |
| 3206 | /* dma_system -> l3_main_2 */ |
| 3207 | static struct omap_hwmod_ocp_if omap44xx_dma_system__l3_main_2 = { |
| 3208 | .master = &omap44xx_dma_system_hwmod, |
| 3209 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3210 | .clk = "l3_div_ck", |
| 3211 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3212 | }; |
| 3213 | |
Ming Lei | b050f68 | 2012-04-19 13:33:50 -0600 | [diff] [blame] | 3214 | /* fdif -> l3_main_2 */ |
| 3215 | static struct omap_hwmod_ocp_if omap44xx_fdif__l3_main_2 = { |
| 3216 | .master = &omap44xx_fdif_hwmod, |
| 3217 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3218 | .clk = "l3_div_ck", |
| 3219 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3220 | }; |
| 3221 | |
Paul Walmsley | 9def390 | 2012-04-19 13:33:53 -0600 | [diff] [blame^] | 3222 | /* gpu -> l3_main_2 */ |
| 3223 | static struct omap_hwmod_ocp_if omap44xx_gpu__l3_main_2 = { |
| 3224 | .master = &omap44xx_gpu_hwmod, |
| 3225 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3226 | .clk = "l3_div_ck", |
| 3227 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3228 | }; |
| 3229 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 3230 | /* hsi -> l3_main_2 */ |
| 3231 | static struct omap_hwmod_ocp_if omap44xx_hsi__l3_main_2 = { |
| 3232 | .master = &omap44xx_hsi_hwmod, |
| 3233 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3234 | .clk = "l3_div_ck", |
| 3235 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3236 | }; |
| 3237 | |
| 3238 | /* ipu -> l3_main_2 */ |
| 3239 | static struct omap_hwmod_ocp_if omap44xx_ipu__l3_main_2 = { |
| 3240 | .master = &omap44xx_ipu_hwmod, |
| 3241 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3242 | .clk = "l3_div_ck", |
| 3243 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3244 | }; |
| 3245 | |
| 3246 | /* iss -> l3_main_2 */ |
| 3247 | static struct omap_hwmod_ocp_if omap44xx_iss__l3_main_2 = { |
| 3248 | .master = &omap44xx_iss_hwmod, |
| 3249 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3250 | .clk = "l3_div_ck", |
| 3251 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3252 | }; |
| 3253 | |
| 3254 | /* iva -> l3_main_2 */ |
| 3255 | static struct omap_hwmod_ocp_if omap44xx_iva__l3_main_2 = { |
| 3256 | .master = &omap44xx_iva_hwmod, |
| 3257 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3258 | .clk = "l3_div_ck", |
| 3259 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3260 | }; |
| 3261 | |
| 3262 | static struct omap_hwmod_addr_space omap44xx_l3_main_2_addrs[] = { |
| 3263 | { |
| 3264 | .pa_start = 0x44800000, |
| 3265 | .pa_end = 0x44801fff, |
| 3266 | .flags = ADDR_TYPE_RT |
| 3267 | }, |
| 3268 | { } |
| 3269 | }; |
| 3270 | |
| 3271 | /* l3_main_1 -> l3_main_2 */ |
| 3272 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_2 = { |
| 3273 | .master = &omap44xx_l3_main_1_hwmod, |
| 3274 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3275 | .clk = "l3_div_ck", |
| 3276 | .addr = omap44xx_l3_main_2_addrs, |
| 3277 | .user = OCP_USER_MPU, |
| 3278 | }; |
| 3279 | |
| 3280 | /* l4_cfg -> l3_main_2 */ |
| 3281 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_2 = { |
| 3282 | .master = &omap44xx_l4_cfg_hwmod, |
| 3283 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3284 | .clk = "l4_div_ck", |
| 3285 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3286 | }; |
| 3287 | |
| 3288 | /* usb_host_hs -> l3_main_2 */ |
| 3289 | static struct omap_hwmod_ocp_if omap44xx_usb_host_hs__l3_main_2 = { |
| 3290 | .master = &omap44xx_usb_host_hs_hwmod, |
| 3291 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3292 | .clk = "l3_div_ck", |
| 3293 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3294 | }; |
| 3295 | |
| 3296 | /* usb_otg_hs -> l3_main_2 */ |
| 3297 | static struct omap_hwmod_ocp_if omap44xx_usb_otg_hs__l3_main_2 = { |
| 3298 | .master = &omap44xx_usb_otg_hs_hwmod, |
| 3299 | .slave = &omap44xx_l3_main_2_hwmod, |
| 3300 | .clk = "l3_div_ck", |
| 3301 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3302 | }; |
| 3303 | |
| 3304 | static struct omap_hwmod_addr_space omap44xx_l3_main_3_addrs[] = { |
| 3305 | { |
| 3306 | .pa_start = 0x45000000, |
| 3307 | .pa_end = 0x45000fff, |
| 3308 | .flags = ADDR_TYPE_RT |
| 3309 | }, |
| 3310 | { } |
| 3311 | }; |
| 3312 | |
| 3313 | /* l3_main_1 -> l3_main_3 */ |
| 3314 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l3_main_3 = { |
| 3315 | .master = &omap44xx_l3_main_1_hwmod, |
| 3316 | .slave = &omap44xx_l3_main_3_hwmod, |
| 3317 | .clk = "l3_div_ck", |
| 3318 | .addr = omap44xx_l3_main_3_addrs, |
| 3319 | .user = OCP_USER_MPU, |
| 3320 | }; |
| 3321 | |
| 3322 | /* l3_main_2 -> l3_main_3 */ |
| 3323 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l3_main_3 = { |
| 3324 | .master = &omap44xx_l3_main_2_hwmod, |
| 3325 | .slave = &omap44xx_l3_main_3_hwmod, |
| 3326 | .clk = "l3_div_ck", |
| 3327 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3328 | }; |
| 3329 | |
| 3330 | /* l4_cfg -> l3_main_3 */ |
| 3331 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l3_main_3 = { |
| 3332 | .master = &omap44xx_l4_cfg_hwmod, |
| 3333 | .slave = &omap44xx_l3_main_3_hwmod, |
| 3334 | .clk = "l4_div_ck", |
| 3335 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3336 | }; |
| 3337 | |
| 3338 | /* aess -> l4_abe */ |
| 3339 | static struct omap_hwmod_ocp_if omap44xx_aess__l4_abe = { |
| 3340 | .master = &omap44xx_aess_hwmod, |
| 3341 | .slave = &omap44xx_l4_abe_hwmod, |
| 3342 | .clk = "ocp_abe_iclk", |
| 3343 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3344 | }; |
| 3345 | |
| 3346 | /* dsp -> l4_abe */ |
| 3347 | static struct omap_hwmod_ocp_if omap44xx_dsp__l4_abe = { |
| 3348 | .master = &omap44xx_dsp_hwmod, |
| 3349 | .slave = &omap44xx_l4_abe_hwmod, |
| 3350 | .clk = "ocp_abe_iclk", |
| 3351 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3352 | }; |
| 3353 | |
| 3354 | /* l3_main_1 -> l4_abe */ |
| 3355 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_abe = { |
| 3356 | .master = &omap44xx_l3_main_1_hwmod, |
| 3357 | .slave = &omap44xx_l4_abe_hwmod, |
| 3358 | .clk = "l3_div_ck", |
| 3359 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3360 | }; |
| 3361 | |
| 3362 | /* mpu -> l4_abe */ |
| 3363 | static struct omap_hwmod_ocp_if omap44xx_mpu__l4_abe = { |
| 3364 | .master = &omap44xx_mpu_hwmod, |
| 3365 | .slave = &omap44xx_l4_abe_hwmod, |
| 3366 | .clk = "ocp_abe_iclk", |
| 3367 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3368 | }; |
| 3369 | |
| 3370 | /* l3_main_1 -> l4_cfg */ |
| 3371 | static struct omap_hwmod_ocp_if omap44xx_l3_main_1__l4_cfg = { |
| 3372 | .master = &omap44xx_l3_main_1_hwmod, |
| 3373 | .slave = &omap44xx_l4_cfg_hwmod, |
| 3374 | .clk = "l3_div_ck", |
| 3375 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3376 | }; |
| 3377 | |
| 3378 | /* l3_main_2 -> l4_per */ |
| 3379 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__l4_per = { |
| 3380 | .master = &omap44xx_l3_main_2_hwmod, |
| 3381 | .slave = &omap44xx_l4_per_hwmod, |
| 3382 | .clk = "l3_div_ck", |
| 3383 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3384 | }; |
| 3385 | |
| 3386 | /* l4_cfg -> l4_wkup */ |
| 3387 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__l4_wkup = { |
| 3388 | .master = &omap44xx_l4_cfg_hwmod, |
| 3389 | .slave = &omap44xx_l4_wkup_hwmod, |
| 3390 | .clk = "l4_div_ck", |
| 3391 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3392 | }; |
| 3393 | |
| 3394 | /* mpu -> mpu_private */ |
| 3395 | static struct omap_hwmod_ocp_if omap44xx_mpu__mpu_private = { |
| 3396 | .master = &omap44xx_mpu_hwmod, |
| 3397 | .slave = &omap44xx_mpu_private_hwmod, |
| 3398 | .clk = "l3_div_ck", |
| 3399 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3400 | }; |
| 3401 | |
| 3402 | static struct omap_hwmod_addr_space omap44xx_aess_addrs[] = { |
| 3403 | { |
| 3404 | .pa_start = 0x401f1000, |
| 3405 | .pa_end = 0x401f13ff, |
| 3406 | .flags = ADDR_TYPE_RT |
| 3407 | }, |
| 3408 | { } |
| 3409 | }; |
| 3410 | |
| 3411 | /* l4_abe -> aess */ |
| 3412 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess = { |
| 3413 | .master = &omap44xx_l4_abe_hwmod, |
| 3414 | .slave = &omap44xx_aess_hwmod, |
| 3415 | .clk = "ocp_abe_iclk", |
| 3416 | .addr = omap44xx_aess_addrs, |
| 3417 | .user = OCP_USER_MPU, |
| 3418 | }; |
| 3419 | |
| 3420 | static struct omap_hwmod_addr_space omap44xx_aess_dma_addrs[] = { |
| 3421 | { |
| 3422 | .pa_start = 0x490f1000, |
| 3423 | .pa_end = 0x490f13ff, |
| 3424 | .flags = ADDR_TYPE_RT |
| 3425 | }, |
| 3426 | { } |
| 3427 | }; |
| 3428 | |
| 3429 | /* l4_abe -> aess (dma) */ |
| 3430 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__aess_dma = { |
| 3431 | .master = &omap44xx_l4_abe_hwmod, |
| 3432 | .slave = &omap44xx_aess_hwmod, |
| 3433 | .clk = "ocp_abe_iclk", |
| 3434 | .addr = omap44xx_aess_dma_addrs, |
| 3435 | .user = OCP_USER_SDMA, |
| 3436 | }; |
| 3437 | |
| 3438 | static struct omap_hwmod_addr_space omap44xx_counter_32k_addrs[] = { |
| 3439 | { |
| 3440 | .pa_start = 0x4a304000, |
| 3441 | .pa_end = 0x4a30401f, |
| 3442 | .flags = ADDR_TYPE_RT |
| 3443 | }, |
| 3444 | { } |
| 3445 | }; |
| 3446 | |
| 3447 | /* l4_wkup -> counter_32k */ |
| 3448 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__counter_32k = { |
| 3449 | .master = &omap44xx_l4_wkup_hwmod, |
| 3450 | .slave = &omap44xx_counter_32k_hwmod, |
| 3451 | .clk = "l4_wkup_clk_mux_ck", |
| 3452 | .addr = omap44xx_counter_32k_addrs, |
| 3453 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3454 | }; |
| 3455 | |
| 3456 | static struct omap_hwmod_addr_space omap44xx_dma_system_addrs[] = { |
| 3457 | { |
| 3458 | .pa_start = 0x4a056000, |
| 3459 | .pa_end = 0x4a056fff, |
| 3460 | .flags = ADDR_TYPE_RT |
| 3461 | }, |
| 3462 | { } |
| 3463 | }; |
| 3464 | |
| 3465 | /* l4_cfg -> dma_system */ |
| 3466 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dma_system = { |
| 3467 | .master = &omap44xx_l4_cfg_hwmod, |
| 3468 | .slave = &omap44xx_dma_system_hwmod, |
| 3469 | .clk = "l4_div_ck", |
| 3470 | .addr = omap44xx_dma_system_addrs, |
| 3471 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3472 | }; |
| 3473 | |
| 3474 | static struct omap_hwmod_addr_space omap44xx_dmic_addrs[] = { |
| 3475 | { |
| 3476 | .name = "mpu", |
| 3477 | .pa_start = 0x4012e000, |
| 3478 | .pa_end = 0x4012e07f, |
| 3479 | .flags = ADDR_TYPE_RT |
| 3480 | }, |
| 3481 | { } |
| 3482 | }; |
| 3483 | |
| 3484 | /* l4_abe -> dmic */ |
| 3485 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic = { |
| 3486 | .master = &omap44xx_l4_abe_hwmod, |
| 3487 | .slave = &omap44xx_dmic_hwmod, |
| 3488 | .clk = "ocp_abe_iclk", |
| 3489 | .addr = omap44xx_dmic_addrs, |
| 3490 | .user = OCP_USER_MPU, |
| 3491 | }; |
| 3492 | |
| 3493 | static struct omap_hwmod_addr_space omap44xx_dmic_dma_addrs[] = { |
| 3494 | { |
| 3495 | .name = "dma", |
| 3496 | .pa_start = 0x4902e000, |
| 3497 | .pa_end = 0x4902e07f, |
| 3498 | .flags = ADDR_TYPE_RT |
| 3499 | }, |
| 3500 | { } |
| 3501 | }; |
| 3502 | |
| 3503 | /* l4_abe -> dmic (dma) */ |
| 3504 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__dmic_dma = { |
| 3505 | .master = &omap44xx_l4_abe_hwmod, |
| 3506 | .slave = &omap44xx_dmic_hwmod, |
| 3507 | .clk = "ocp_abe_iclk", |
| 3508 | .addr = omap44xx_dmic_dma_addrs, |
| 3509 | .user = OCP_USER_SDMA, |
| 3510 | }; |
| 3511 | |
| 3512 | /* dsp -> iva */ |
| 3513 | static struct omap_hwmod_ocp_if omap44xx_dsp__iva = { |
| 3514 | .master = &omap44xx_dsp_hwmod, |
| 3515 | .slave = &omap44xx_iva_hwmod, |
| 3516 | .clk = "dpll_iva_m5x2_ck", |
| 3517 | .user = OCP_USER_DSP, |
| 3518 | }; |
| 3519 | |
| 3520 | /* l4_cfg -> dsp */ |
| 3521 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__dsp = { |
| 3522 | .master = &omap44xx_l4_cfg_hwmod, |
| 3523 | .slave = &omap44xx_dsp_hwmod, |
| 3524 | .clk = "l4_div_ck", |
| 3525 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3526 | }; |
| 3527 | |
| 3528 | static struct omap_hwmod_addr_space omap44xx_dss_dma_addrs[] = { |
| 3529 | { |
| 3530 | .pa_start = 0x58000000, |
| 3531 | .pa_end = 0x5800007f, |
| 3532 | .flags = ADDR_TYPE_RT |
| 3533 | }, |
| 3534 | { } |
| 3535 | }; |
| 3536 | |
| 3537 | /* l3_main_2 -> dss */ |
| 3538 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss = { |
| 3539 | .master = &omap44xx_l3_main_2_hwmod, |
| 3540 | .slave = &omap44xx_dss_hwmod, |
| 3541 | .clk = "dss_fck", |
| 3542 | .addr = omap44xx_dss_dma_addrs, |
| 3543 | .user = OCP_USER_SDMA, |
| 3544 | }; |
| 3545 | |
| 3546 | static struct omap_hwmod_addr_space omap44xx_dss_addrs[] = { |
| 3547 | { |
| 3548 | .pa_start = 0x48040000, |
| 3549 | .pa_end = 0x4804007f, |
| 3550 | .flags = ADDR_TYPE_RT |
| 3551 | }, |
| 3552 | { } |
| 3553 | }; |
| 3554 | |
| 3555 | /* l4_per -> dss */ |
| 3556 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss = { |
| 3557 | .master = &omap44xx_l4_per_hwmod, |
| 3558 | .slave = &omap44xx_dss_hwmod, |
| 3559 | .clk = "l4_div_ck", |
| 3560 | .addr = omap44xx_dss_addrs, |
| 3561 | .user = OCP_USER_MPU, |
| 3562 | }; |
| 3563 | |
| 3564 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_dma_addrs[] = { |
| 3565 | { |
| 3566 | .pa_start = 0x58001000, |
| 3567 | .pa_end = 0x58001fff, |
| 3568 | .flags = ADDR_TYPE_RT |
| 3569 | }, |
| 3570 | { } |
| 3571 | }; |
| 3572 | |
| 3573 | /* l3_main_2 -> dss_dispc */ |
| 3574 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dispc = { |
| 3575 | .master = &omap44xx_l3_main_2_hwmod, |
| 3576 | .slave = &omap44xx_dss_dispc_hwmod, |
| 3577 | .clk = "dss_fck", |
| 3578 | .addr = omap44xx_dss_dispc_dma_addrs, |
| 3579 | .user = OCP_USER_SDMA, |
| 3580 | }; |
| 3581 | |
| 3582 | static struct omap_hwmod_addr_space omap44xx_dss_dispc_addrs[] = { |
| 3583 | { |
| 3584 | .pa_start = 0x48041000, |
| 3585 | .pa_end = 0x48041fff, |
| 3586 | .flags = ADDR_TYPE_RT |
| 3587 | }, |
| 3588 | { } |
| 3589 | }; |
| 3590 | |
| 3591 | /* l4_per -> dss_dispc */ |
| 3592 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dispc = { |
| 3593 | .master = &omap44xx_l4_per_hwmod, |
| 3594 | .slave = &omap44xx_dss_dispc_hwmod, |
| 3595 | .clk = "l4_div_ck", |
| 3596 | .addr = omap44xx_dss_dispc_addrs, |
| 3597 | .user = OCP_USER_MPU, |
| 3598 | }; |
| 3599 | |
| 3600 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_dma_addrs[] = { |
| 3601 | { |
| 3602 | .pa_start = 0x58004000, |
| 3603 | .pa_end = 0x580041ff, |
| 3604 | .flags = ADDR_TYPE_RT |
| 3605 | }, |
| 3606 | { } |
| 3607 | }; |
| 3608 | |
| 3609 | /* l3_main_2 -> dss_dsi1 */ |
| 3610 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi1 = { |
| 3611 | .master = &omap44xx_l3_main_2_hwmod, |
| 3612 | .slave = &omap44xx_dss_dsi1_hwmod, |
| 3613 | .clk = "dss_fck", |
| 3614 | .addr = omap44xx_dss_dsi1_dma_addrs, |
| 3615 | .user = OCP_USER_SDMA, |
| 3616 | }; |
| 3617 | |
| 3618 | static struct omap_hwmod_addr_space omap44xx_dss_dsi1_addrs[] = { |
| 3619 | { |
| 3620 | .pa_start = 0x48044000, |
| 3621 | .pa_end = 0x480441ff, |
| 3622 | .flags = ADDR_TYPE_RT |
| 3623 | }, |
| 3624 | { } |
| 3625 | }; |
| 3626 | |
| 3627 | /* l4_per -> dss_dsi1 */ |
| 3628 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi1 = { |
| 3629 | .master = &omap44xx_l4_per_hwmod, |
| 3630 | .slave = &omap44xx_dss_dsi1_hwmod, |
| 3631 | .clk = "l4_div_ck", |
| 3632 | .addr = omap44xx_dss_dsi1_addrs, |
| 3633 | .user = OCP_USER_MPU, |
| 3634 | }; |
| 3635 | |
| 3636 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_dma_addrs[] = { |
| 3637 | { |
| 3638 | .pa_start = 0x58005000, |
| 3639 | .pa_end = 0x580051ff, |
| 3640 | .flags = ADDR_TYPE_RT |
| 3641 | }, |
| 3642 | { } |
| 3643 | }; |
| 3644 | |
| 3645 | /* l3_main_2 -> dss_dsi2 */ |
| 3646 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_dsi2 = { |
| 3647 | .master = &omap44xx_l3_main_2_hwmod, |
| 3648 | .slave = &omap44xx_dss_dsi2_hwmod, |
| 3649 | .clk = "dss_fck", |
| 3650 | .addr = omap44xx_dss_dsi2_dma_addrs, |
| 3651 | .user = OCP_USER_SDMA, |
| 3652 | }; |
| 3653 | |
| 3654 | static struct omap_hwmod_addr_space omap44xx_dss_dsi2_addrs[] = { |
| 3655 | { |
| 3656 | .pa_start = 0x48045000, |
| 3657 | .pa_end = 0x480451ff, |
| 3658 | .flags = ADDR_TYPE_RT |
| 3659 | }, |
| 3660 | { } |
| 3661 | }; |
| 3662 | |
| 3663 | /* l4_per -> dss_dsi2 */ |
| 3664 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_dsi2 = { |
| 3665 | .master = &omap44xx_l4_per_hwmod, |
| 3666 | .slave = &omap44xx_dss_dsi2_hwmod, |
| 3667 | .clk = "l4_div_ck", |
| 3668 | .addr = omap44xx_dss_dsi2_addrs, |
| 3669 | .user = OCP_USER_MPU, |
| 3670 | }; |
| 3671 | |
| 3672 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_dma_addrs[] = { |
| 3673 | { |
| 3674 | .pa_start = 0x58006000, |
| 3675 | .pa_end = 0x58006fff, |
| 3676 | .flags = ADDR_TYPE_RT |
| 3677 | }, |
| 3678 | { } |
| 3679 | }; |
| 3680 | |
| 3681 | /* l3_main_2 -> dss_hdmi */ |
| 3682 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_hdmi = { |
| 3683 | .master = &omap44xx_l3_main_2_hwmod, |
| 3684 | .slave = &omap44xx_dss_hdmi_hwmod, |
| 3685 | .clk = "dss_fck", |
| 3686 | .addr = omap44xx_dss_hdmi_dma_addrs, |
| 3687 | .user = OCP_USER_SDMA, |
| 3688 | }; |
| 3689 | |
| 3690 | static struct omap_hwmod_addr_space omap44xx_dss_hdmi_addrs[] = { |
| 3691 | { |
| 3692 | .pa_start = 0x48046000, |
| 3693 | .pa_end = 0x48046fff, |
| 3694 | .flags = ADDR_TYPE_RT |
| 3695 | }, |
| 3696 | { } |
| 3697 | }; |
| 3698 | |
| 3699 | /* l4_per -> dss_hdmi */ |
| 3700 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_hdmi = { |
| 3701 | .master = &omap44xx_l4_per_hwmod, |
| 3702 | .slave = &omap44xx_dss_hdmi_hwmod, |
| 3703 | .clk = "l4_div_ck", |
| 3704 | .addr = omap44xx_dss_hdmi_addrs, |
| 3705 | .user = OCP_USER_MPU, |
| 3706 | }; |
| 3707 | |
| 3708 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_dma_addrs[] = { |
| 3709 | { |
| 3710 | .pa_start = 0x58002000, |
| 3711 | .pa_end = 0x580020ff, |
| 3712 | .flags = ADDR_TYPE_RT |
| 3713 | }, |
| 3714 | { } |
| 3715 | }; |
| 3716 | |
| 3717 | /* l3_main_2 -> dss_rfbi */ |
| 3718 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_rfbi = { |
| 3719 | .master = &omap44xx_l3_main_2_hwmod, |
| 3720 | .slave = &omap44xx_dss_rfbi_hwmod, |
| 3721 | .clk = "dss_fck", |
| 3722 | .addr = omap44xx_dss_rfbi_dma_addrs, |
| 3723 | .user = OCP_USER_SDMA, |
| 3724 | }; |
| 3725 | |
| 3726 | static struct omap_hwmod_addr_space omap44xx_dss_rfbi_addrs[] = { |
| 3727 | { |
| 3728 | .pa_start = 0x48042000, |
| 3729 | .pa_end = 0x480420ff, |
| 3730 | .flags = ADDR_TYPE_RT |
| 3731 | }, |
| 3732 | { } |
| 3733 | }; |
| 3734 | |
| 3735 | /* l4_per -> dss_rfbi */ |
| 3736 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_rfbi = { |
| 3737 | .master = &omap44xx_l4_per_hwmod, |
| 3738 | .slave = &omap44xx_dss_rfbi_hwmod, |
| 3739 | .clk = "l4_div_ck", |
| 3740 | .addr = omap44xx_dss_rfbi_addrs, |
| 3741 | .user = OCP_USER_MPU, |
| 3742 | }; |
| 3743 | |
| 3744 | static struct omap_hwmod_addr_space omap44xx_dss_venc_dma_addrs[] = { |
| 3745 | { |
| 3746 | .pa_start = 0x58003000, |
| 3747 | .pa_end = 0x580030ff, |
| 3748 | .flags = ADDR_TYPE_RT |
| 3749 | }, |
| 3750 | { } |
| 3751 | }; |
| 3752 | |
| 3753 | /* l3_main_2 -> dss_venc */ |
| 3754 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__dss_venc = { |
| 3755 | .master = &omap44xx_l3_main_2_hwmod, |
| 3756 | .slave = &omap44xx_dss_venc_hwmod, |
| 3757 | .clk = "dss_fck", |
| 3758 | .addr = omap44xx_dss_venc_dma_addrs, |
| 3759 | .user = OCP_USER_SDMA, |
| 3760 | }; |
| 3761 | |
| 3762 | static struct omap_hwmod_addr_space omap44xx_dss_venc_addrs[] = { |
| 3763 | { |
| 3764 | .pa_start = 0x48043000, |
| 3765 | .pa_end = 0x480430ff, |
| 3766 | .flags = ADDR_TYPE_RT |
| 3767 | }, |
| 3768 | { } |
| 3769 | }; |
| 3770 | |
| 3771 | /* l4_per -> dss_venc */ |
| 3772 | static struct omap_hwmod_ocp_if omap44xx_l4_per__dss_venc = { |
| 3773 | .master = &omap44xx_l4_per_hwmod, |
| 3774 | .slave = &omap44xx_dss_venc_hwmod, |
| 3775 | .clk = "l4_div_ck", |
| 3776 | .addr = omap44xx_dss_venc_addrs, |
| 3777 | .user = OCP_USER_MPU, |
| 3778 | }; |
| 3779 | |
Paul Walmsley | bf30f95 | 2012-04-19 13:33:52 -0600 | [diff] [blame] | 3780 | static struct omap_hwmod_addr_space omap44xx_emif1_addrs[] = { |
| 3781 | { |
| 3782 | .pa_start = 0x4c000000, |
| 3783 | .pa_end = 0x4c0000ff, |
| 3784 | .flags = ADDR_TYPE_RT |
| 3785 | }, |
| 3786 | { } |
| 3787 | }; |
| 3788 | |
| 3789 | /* emif_fw -> emif1 */ |
| 3790 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif1 = { |
| 3791 | .master = &omap44xx_emif_fw_hwmod, |
| 3792 | .slave = &omap44xx_emif1_hwmod, |
| 3793 | .clk = "l3_div_ck", |
| 3794 | .addr = omap44xx_emif1_addrs, |
| 3795 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3796 | }; |
| 3797 | |
| 3798 | static struct omap_hwmod_addr_space omap44xx_emif2_addrs[] = { |
| 3799 | { |
| 3800 | .pa_start = 0x4d000000, |
| 3801 | .pa_end = 0x4d0000ff, |
| 3802 | .flags = ADDR_TYPE_RT |
| 3803 | }, |
| 3804 | { } |
| 3805 | }; |
| 3806 | |
| 3807 | /* emif_fw -> emif2 */ |
| 3808 | static struct omap_hwmod_ocp_if omap44xx_emif_fw__emif2 = { |
| 3809 | .master = &omap44xx_emif_fw_hwmod, |
| 3810 | .slave = &omap44xx_emif2_hwmod, |
| 3811 | .clk = "l3_div_ck", |
| 3812 | .addr = omap44xx_emif2_addrs, |
| 3813 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3814 | }; |
| 3815 | |
Ming Lei | b050f68 | 2012-04-19 13:33:50 -0600 | [diff] [blame] | 3816 | static struct omap_hwmod_addr_space omap44xx_fdif_addrs[] = { |
| 3817 | { |
| 3818 | .pa_start = 0x4a10a000, |
| 3819 | .pa_end = 0x4a10a1ff, |
| 3820 | .flags = ADDR_TYPE_RT |
| 3821 | }, |
| 3822 | { } |
| 3823 | }; |
| 3824 | |
| 3825 | /* l4_cfg -> fdif */ |
| 3826 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__fdif = { |
| 3827 | .master = &omap44xx_l4_cfg_hwmod, |
| 3828 | .slave = &omap44xx_fdif_hwmod, |
| 3829 | .clk = "l4_div_ck", |
| 3830 | .addr = omap44xx_fdif_addrs, |
| 3831 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3832 | }; |
| 3833 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 3834 | static struct omap_hwmod_addr_space omap44xx_gpio1_addrs[] = { |
| 3835 | { |
| 3836 | .pa_start = 0x4a310000, |
| 3837 | .pa_end = 0x4a3101ff, |
| 3838 | .flags = ADDR_TYPE_RT |
| 3839 | }, |
| 3840 | { } |
| 3841 | }; |
| 3842 | |
| 3843 | /* l4_wkup -> gpio1 */ |
| 3844 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__gpio1 = { |
| 3845 | .master = &omap44xx_l4_wkup_hwmod, |
| 3846 | .slave = &omap44xx_gpio1_hwmod, |
| 3847 | .clk = "l4_wkup_clk_mux_ck", |
| 3848 | .addr = omap44xx_gpio1_addrs, |
| 3849 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3850 | }; |
| 3851 | |
| 3852 | static struct omap_hwmod_addr_space omap44xx_gpio2_addrs[] = { |
| 3853 | { |
| 3854 | .pa_start = 0x48055000, |
| 3855 | .pa_end = 0x480551ff, |
| 3856 | .flags = ADDR_TYPE_RT |
| 3857 | }, |
| 3858 | { } |
| 3859 | }; |
| 3860 | |
| 3861 | /* l4_per -> gpio2 */ |
| 3862 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio2 = { |
| 3863 | .master = &omap44xx_l4_per_hwmod, |
| 3864 | .slave = &omap44xx_gpio2_hwmod, |
| 3865 | .clk = "l4_div_ck", |
| 3866 | .addr = omap44xx_gpio2_addrs, |
| 3867 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3868 | }; |
| 3869 | |
| 3870 | static struct omap_hwmod_addr_space omap44xx_gpio3_addrs[] = { |
| 3871 | { |
| 3872 | .pa_start = 0x48057000, |
| 3873 | .pa_end = 0x480571ff, |
| 3874 | .flags = ADDR_TYPE_RT |
| 3875 | }, |
| 3876 | { } |
| 3877 | }; |
| 3878 | |
| 3879 | /* l4_per -> gpio3 */ |
| 3880 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio3 = { |
| 3881 | .master = &omap44xx_l4_per_hwmod, |
| 3882 | .slave = &omap44xx_gpio3_hwmod, |
| 3883 | .clk = "l4_div_ck", |
| 3884 | .addr = omap44xx_gpio3_addrs, |
| 3885 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3886 | }; |
| 3887 | |
| 3888 | static struct omap_hwmod_addr_space omap44xx_gpio4_addrs[] = { |
| 3889 | { |
| 3890 | .pa_start = 0x48059000, |
| 3891 | .pa_end = 0x480591ff, |
| 3892 | .flags = ADDR_TYPE_RT |
| 3893 | }, |
| 3894 | { } |
| 3895 | }; |
| 3896 | |
| 3897 | /* l4_per -> gpio4 */ |
| 3898 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio4 = { |
| 3899 | .master = &omap44xx_l4_per_hwmod, |
| 3900 | .slave = &omap44xx_gpio4_hwmod, |
| 3901 | .clk = "l4_div_ck", |
| 3902 | .addr = omap44xx_gpio4_addrs, |
| 3903 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3904 | }; |
| 3905 | |
| 3906 | static struct omap_hwmod_addr_space omap44xx_gpio5_addrs[] = { |
| 3907 | { |
| 3908 | .pa_start = 0x4805b000, |
| 3909 | .pa_end = 0x4805b1ff, |
| 3910 | .flags = ADDR_TYPE_RT |
| 3911 | }, |
| 3912 | { } |
| 3913 | }; |
| 3914 | |
| 3915 | /* l4_per -> gpio5 */ |
| 3916 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio5 = { |
| 3917 | .master = &omap44xx_l4_per_hwmod, |
| 3918 | .slave = &omap44xx_gpio5_hwmod, |
| 3919 | .clk = "l4_div_ck", |
| 3920 | .addr = omap44xx_gpio5_addrs, |
| 3921 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3922 | }; |
| 3923 | |
| 3924 | static struct omap_hwmod_addr_space omap44xx_gpio6_addrs[] = { |
| 3925 | { |
| 3926 | .pa_start = 0x4805d000, |
| 3927 | .pa_end = 0x4805d1ff, |
| 3928 | .flags = ADDR_TYPE_RT |
| 3929 | }, |
| 3930 | { } |
| 3931 | }; |
| 3932 | |
| 3933 | /* l4_per -> gpio6 */ |
| 3934 | static struct omap_hwmod_ocp_if omap44xx_l4_per__gpio6 = { |
| 3935 | .master = &omap44xx_l4_per_hwmod, |
| 3936 | .slave = &omap44xx_gpio6_hwmod, |
| 3937 | .clk = "l4_div_ck", |
| 3938 | .addr = omap44xx_gpio6_addrs, |
| 3939 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3940 | }; |
| 3941 | |
BenoƮt Cousson | eb42b5d | 2012-04-19 13:33:51 -0600 | [diff] [blame] | 3942 | static struct omap_hwmod_addr_space omap44xx_gpmc_addrs[] = { |
| 3943 | { |
| 3944 | .pa_start = 0x50000000, |
| 3945 | .pa_end = 0x500003ff, |
| 3946 | .flags = ADDR_TYPE_RT |
| 3947 | }, |
| 3948 | { } |
| 3949 | }; |
| 3950 | |
| 3951 | /* l3_main_2 -> gpmc */ |
| 3952 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpmc = { |
| 3953 | .master = &omap44xx_l3_main_2_hwmod, |
| 3954 | .slave = &omap44xx_gpmc_hwmod, |
| 3955 | .clk = "l3_div_ck", |
| 3956 | .addr = omap44xx_gpmc_addrs, |
| 3957 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3958 | }; |
| 3959 | |
Paul Walmsley | 9def390 | 2012-04-19 13:33:53 -0600 | [diff] [blame^] | 3960 | static struct omap_hwmod_addr_space omap44xx_gpu_addrs[] = { |
| 3961 | { |
| 3962 | .pa_start = 0x56000000, |
| 3963 | .pa_end = 0x5600ffff, |
| 3964 | .flags = ADDR_TYPE_RT |
| 3965 | }, |
| 3966 | { } |
| 3967 | }; |
| 3968 | |
| 3969 | /* l3_main_2 -> gpu */ |
| 3970 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__gpu = { |
| 3971 | .master = &omap44xx_l3_main_2_hwmod, |
| 3972 | .slave = &omap44xx_gpu_hwmod, |
| 3973 | .clk = "l3_div_ck", |
| 3974 | .addr = omap44xx_gpu_addrs, |
| 3975 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3976 | }; |
| 3977 | |
Paul Walmsley | a091c08 | 2012-04-19 13:33:50 -0600 | [diff] [blame] | 3978 | static struct omap_hwmod_addr_space omap44xx_hdq1w_addrs[] = { |
| 3979 | { |
| 3980 | .pa_start = 0x480b2000, |
| 3981 | .pa_end = 0x480b201f, |
| 3982 | .flags = ADDR_TYPE_RT |
| 3983 | }, |
| 3984 | { } |
| 3985 | }; |
| 3986 | |
| 3987 | /* l4_per -> hdq1w */ |
| 3988 | static struct omap_hwmod_ocp_if omap44xx_l4_per__hdq1w = { |
| 3989 | .master = &omap44xx_l4_per_hwmod, |
| 3990 | .slave = &omap44xx_hdq1w_hwmod, |
| 3991 | .clk = "l4_div_ck", |
| 3992 | .addr = omap44xx_hdq1w_addrs, |
| 3993 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 3994 | }; |
| 3995 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 3996 | static struct omap_hwmod_addr_space omap44xx_hsi_addrs[] = { |
| 3997 | { |
| 3998 | .pa_start = 0x4a058000, |
| 3999 | .pa_end = 0x4a05bfff, |
| 4000 | .flags = ADDR_TYPE_RT |
| 4001 | }, |
| 4002 | { } |
| 4003 | }; |
| 4004 | |
| 4005 | /* l4_cfg -> hsi */ |
| 4006 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__hsi = { |
| 4007 | .master = &omap44xx_l4_cfg_hwmod, |
| 4008 | .slave = &omap44xx_hsi_hwmod, |
| 4009 | .clk = "l4_div_ck", |
| 4010 | .addr = omap44xx_hsi_addrs, |
| 4011 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4012 | }; |
| 4013 | |
| 4014 | static struct omap_hwmod_addr_space omap44xx_i2c1_addrs[] = { |
| 4015 | { |
| 4016 | .pa_start = 0x48070000, |
| 4017 | .pa_end = 0x480700ff, |
| 4018 | .flags = ADDR_TYPE_RT |
| 4019 | }, |
| 4020 | { } |
| 4021 | }; |
| 4022 | |
| 4023 | /* l4_per -> i2c1 */ |
| 4024 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c1 = { |
| 4025 | .master = &omap44xx_l4_per_hwmod, |
| 4026 | .slave = &omap44xx_i2c1_hwmod, |
| 4027 | .clk = "l4_div_ck", |
| 4028 | .addr = omap44xx_i2c1_addrs, |
| 4029 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4030 | }; |
| 4031 | |
| 4032 | static struct omap_hwmod_addr_space omap44xx_i2c2_addrs[] = { |
| 4033 | { |
| 4034 | .pa_start = 0x48072000, |
| 4035 | .pa_end = 0x480720ff, |
| 4036 | .flags = ADDR_TYPE_RT |
| 4037 | }, |
| 4038 | { } |
| 4039 | }; |
| 4040 | |
| 4041 | /* l4_per -> i2c2 */ |
| 4042 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c2 = { |
| 4043 | .master = &omap44xx_l4_per_hwmod, |
| 4044 | .slave = &omap44xx_i2c2_hwmod, |
| 4045 | .clk = "l4_div_ck", |
| 4046 | .addr = omap44xx_i2c2_addrs, |
| 4047 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4048 | }; |
| 4049 | |
| 4050 | static struct omap_hwmod_addr_space omap44xx_i2c3_addrs[] = { |
| 4051 | { |
| 4052 | .pa_start = 0x48060000, |
| 4053 | .pa_end = 0x480600ff, |
| 4054 | .flags = ADDR_TYPE_RT |
| 4055 | }, |
| 4056 | { } |
| 4057 | }; |
| 4058 | |
| 4059 | /* l4_per -> i2c3 */ |
| 4060 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c3 = { |
| 4061 | .master = &omap44xx_l4_per_hwmod, |
| 4062 | .slave = &omap44xx_i2c3_hwmod, |
| 4063 | .clk = "l4_div_ck", |
| 4064 | .addr = omap44xx_i2c3_addrs, |
| 4065 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4066 | }; |
| 4067 | |
| 4068 | static struct omap_hwmod_addr_space omap44xx_i2c4_addrs[] = { |
| 4069 | { |
| 4070 | .pa_start = 0x48350000, |
| 4071 | .pa_end = 0x483500ff, |
| 4072 | .flags = ADDR_TYPE_RT |
| 4073 | }, |
| 4074 | { } |
| 4075 | }; |
| 4076 | |
| 4077 | /* l4_per -> i2c4 */ |
| 4078 | static struct omap_hwmod_ocp_if omap44xx_l4_per__i2c4 = { |
| 4079 | .master = &omap44xx_l4_per_hwmod, |
| 4080 | .slave = &omap44xx_i2c4_hwmod, |
| 4081 | .clk = "l4_div_ck", |
| 4082 | .addr = omap44xx_i2c4_addrs, |
| 4083 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4084 | }; |
| 4085 | |
| 4086 | /* l3_main_2 -> ipu */ |
| 4087 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__ipu = { |
| 4088 | .master = &omap44xx_l3_main_2_hwmod, |
| 4089 | .slave = &omap44xx_ipu_hwmod, |
| 4090 | .clk = "l3_div_ck", |
| 4091 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4092 | }; |
| 4093 | |
| 4094 | static struct omap_hwmod_addr_space omap44xx_iss_addrs[] = { |
| 4095 | { |
| 4096 | .pa_start = 0x52000000, |
| 4097 | .pa_end = 0x520000ff, |
| 4098 | .flags = ADDR_TYPE_RT |
| 4099 | }, |
| 4100 | { } |
| 4101 | }; |
| 4102 | |
| 4103 | /* l3_main_2 -> iss */ |
| 4104 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iss = { |
| 4105 | .master = &omap44xx_l3_main_2_hwmod, |
| 4106 | .slave = &omap44xx_iss_hwmod, |
| 4107 | .clk = "l3_div_ck", |
| 4108 | .addr = omap44xx_iss_addrs, |
| 4109 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4110 | }; |
| 4111 | |
| 4112 | static struct omap_hwmod_addr_space omap44xx_iva_addrs[] = { |
| 4113 | { |
| 4114 | .pa_start = 0x5a000000, |
| 4115 | .pa_end = 0x5a07ffff, |
| 4116 | .flags = ADDR_TYPE_RT |
| 4117 | }, |
| 4118 | { } |
| 4119 | }; |
| 4120 | |
| 4121 | /* l3_main_2 -> iva */ |
| 4122 | static struct omap_hwmod_ocp_if omap44xx_l3_main_2__iva = { |
| 4123 | .master = &omap44xx_l3_main_2_hwmod, |
| 4124 | .slave = &omap44xx_iva_hwmod, |
| 4125 | .clk = "l3_div_ck", |
| 4126 | .addr = omap44xx_iva_addrs, |
| 4127 | .user = OCP_USER_MPU, |
| 4128 | }; |
| 4129 | |
| 4130 | static struct omap_hwmod_addr_space omap44xx_kbd_addrs[] = { |
| 4131 | { |
| 4132 | .pa_start = 0x4a31c000, |
| 4133 | .pa_end = 0x4a31c07f, |
| 4134 | .flags = ADDR_TYPE_RT |
| 4135 | }, |
| 4136 | { } |
| 4137 | }; |
| 4138 | |
| 4139 | /* l4_wkup -> kbd */ |
| 4140 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__kbd = { |
| 4141 | .master = &omap44xx_l4_wkup_hwmod, |
| 4142 | .slave = &omap44xx_kbd_hwmod, |
| 4143 | .clk = "l4_wkup_clk_mux_ck", |
| 4144 | .addr = omap44xx_kbd_addrs, |
| 4145 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4146 | }; |
| 4147 | |
| 4148 | static struct omap_hwmod_addr_space omap44xx_mailbox_addrs[] = { |
| 4149 | { |
| 4150 | .pa_start = 0x4a0f4000, |
| 4151 | .pa_end = 0x4a0f41ff, |
| 4152 | .flags = ADDR_TYPE_RT |
| 4153 | }, |
| 4154 | { } |
| 4155 | }; |
| 4156 | |
| 4157 | /* l4_cfg -> mailbox */ |
| 4158 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__mailbox = { |
| 4159 | .master = &omap44xx_l4_cfg_hwmod, |
| 4160 | .slave = &omap44xx_mailbox_hwmod, |
| 4161 | .clk = "l4_div_ck", |
| 4162 | .addr = omap44xx_mailbox_addrs, |
| 4163 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4164 | }; |
| 4165 | |
| 4166 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_addrs[] = { |
| 4167 | { |
| 4168 | .name = "mpu", |
| 4169 | .pa_start = 0x40122000, |
| 4170 | .pa_end = 0x401220ff, |
| 4171 | .flags = ADDR_TYPE_RT |
| 4172 | }, |
| 4173 | { } |
| 4174 | }; |
| 4175 | |
| 4176 | /* l4_abe -> mcbsp1 */ |
| 4177 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1 = { |
| 4178 | .master = &omap44xx_l4_abe_hwmod, |
| 4179 | .slave = &omap44xx_mcbsp1_hwmod, |
| 4180 | .clk = "ocp_abe_iclk", |
| 4181 | .addr = omap44xx_mcbsp1_addrs, |
| 4182 | .user = OCP_USER_MPU, |
| 4183 | }; |
| 4184 | |
| 4185 | static struct omap_hwmod_addr_space omap44xx_mcbsp1_dma_addrs[] = { |
| 4186 | { |
| 4187 | .name = "dma", |
| 4188 | .pa_start = 0x49022000, |
| 4189 | .pa_end = 0x490220ff, |
| 4190 | .flags = ADDR_TYPE_RT |
| 4191 | }, |
| 4192 | { } |
| 4193 | }; |
| 4194 | |
| 4195 | /* l4_abe -> mcbsp1 (dma) */ |
| 4196 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp1_dma = { |
| 4197 | .master = &omap44xx_l4_abe_hwmod, |
| 4198 | .slave = &omap44xx_mcbsp1_hwmod, |
| 4199 | .clk = "ocp_abe_iclk", |
| 4200 | .addr = omap44xx_mcbsp1_dma_addrs, |
| 4201 | .user = OCP_USER_SDMA, |
| 4202 | }; |
| 4203 | |
| 4204 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_addrs[] = { |
| 4205 | { |
| 4206 | .name = "mpu", |
| 4207 | .pa_start = 0x40124000, |
| 4208 | .pa_end = 0x401240ff, |
| 4209 | .flags = ADDR_TYPE_RT |
| 4210 | }, |
| 4211 | { } |
| 4212 | }; |
| 4213 | |
| 4214 | /* l4_abe -> mcbsp2 */ |
| 4215 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2 = { |
| 4216 | .master = &omap44xx_l4_abe_hwmod, |
| 4217 | .slave = &omap44xx_mcbsp2_hwmod, |
| 4218 | .clk = "ocp_abe_iclk", |
| 4219 | .addr = omap44xx_mcbsp2_addrs, |
| 4220 | .user = OCP_USER_MPU, |
| 4221 | }; |
| 4222 | |
| 4223 | static struct omap_hwmod_addr_space omap44xx_mcbsp2_dma_addrs[] = { |
| 4224 | { |
| 4225 | .name = "dma", |
| 4226 | .pa_start = 0x49024000, |
| 4227 | .pa_end = 0x490240ff, |
| 4228 | .flags = ADDR_TYPE_RT |
| 4229 | }, |
| 4230 | { } |
| 4231 | }; |
| 4232 | |
| 4233 | /* l4_abe -> mcbsp2 (dma) */ |
| 4234 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp2_dma = { |
| 4235 | .master = &omap44xx_l4_abe_hwmod, |
| 4236 | .slave = &omap44xx_mcbsp2_hwmod, |
| 4237 | .clk = "ocp_abe_iclk", |
| 4238 | .addr = omap44xx_mcbsp2_dma_addrs, |
| 4239 | .user = OCP_USER_SDMA, |
| 4240 | }; |
| 4241 | |
| 4242 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_addrs[] = { |
| 4243 | { |
| 4244 | .name = "mpu", |
| 4245 | .pa_start = 0x40126000, |
| 4246 | .pa_end = 0x401260ff, |
| 4247 | .flags = ADDR_TYPE_RT |
| 4248 | }, |
| 4249 | { } |
| 4250 | }; |
| 4251 | |
| 4252 | /* l4_abe -> mcbsp3 */ |
| 4253 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3 = { |
| 4254 | .master = &omap44xx_l4_abe_hwmod, |
| 4255 | .slave = &omap44xx_mcbsp3_hwmod, |
| 4256 | .clk = "ocp_abe_iclk", |
| 4257 | .addr = omap44xx_mcbsp3_addrs, |
| 4258 | .user = OCP_USER_MPU, |
| 4259 | }; |
| 4260 | |
| 4261 | static struct omap_hwmod_addr_space omap44xx_mcbsp3_dma_addrs[] = { |
| 4262 | { |
| 4263 | .name = "dma", |
| 4264 | .pa_start = 0x49026000, |
| 4265 | .pa_end = 0x490260ff, |
| 4266 | .flags = ADDR_TYPE_RT |
| 4267 | }, |
| 4268 | { } |
| 4269 | }; |
| 4270 | |
| 4271 | /* l4_abe -> mcbsp3 (dma) */ |
| 4272 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcbsp3_dma = { |
| 4273 | .master = &omap44xx_l4_abe_hwmod, |
| 4274 | .slave = &omap44xx_mcbsp3_hwmod, |
| 4275 | .clk = "ocp_abe_iclk", |
| 4276 | .addr = omap44xx_mcbsp3_dma_addrs, |
| 4277 | .user = OCP_USER_SDMA, |
| 4278 | }; |
| 4279 | |
| 4280 | static struct omap_hwmod_addr_space omap44xx_mcbsp4_addrs[] = { |
| 4281 | { |
| 4282 | .pa_start = 0x48096000, |
| 4283 | .pa_end = 0x480960ff, |
| 4284 | .flags = ADDR_TYPE_RT |
| 4285 | }, |
| 4286 | { } |
| 4287 | }; |
| 4288 | |
| 4289 | /* l4_per -> mcbsp4 */ |
| 4290 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcbsp4 = { |
| 4291 | .master = &omap44xx_l4_per_hwmod, |
| 4292 | .slave = &omap44xx_mcbsp4_hwmod, |
| 4293 | .clk = "l4_div_ck", |
| 4294 | .addr = omap44xx_mcbsp4_addrs, |
| 4295 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4296 | }; |
| 4297 | |
| 4298 | static struct omap_hwmod_addr_space omap44xx_mcpdm_addrs[] = { |
| 4299 | { |
| 4300 | .pa_start = 0x40132000, |
| 4301 | .pa_end = 0x4013207f, |
| 4302 | .flags = ADDR_TYPE_RT |
| 4303 | }, |
| 4304 | { } |
| 4305 | }; |
| 4306 | |
| 4307 | /* l4_abe -> mcpdm */ |
| 4308 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm = { |
| 4309 | .master = &omap44xx_l4_abe_hwmod, |
| 4310 | .slave = &omap44xx_mcpdm_hwmod, |
| 4311 | .clk = "ocp_abe_iclk", |
| 4312 | .addr = omap44xx_mcpdm_addrs, |
| 4313 | .user = OCP_USER_MPU, |
| 4314 | }; |
| 4315 | |
| 4316 | static struct omap_hwmod_addr_space omap44xx_mcpdm_dma_addrs[] = { |
| 4317 | { |
| 4318 | .pa_start = 0x49032000, |
| 4319 | .pa_end = 0x4903207f, |
| 4320 | .flags = ADDR_TYPE_RT |
| 4321 | }, |
| 4322 | { } |
| 4323 | }; |
| 4324 | |
| 4325 | /* l4_abe -> mcpdm (dma) */ |
| 4326 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__mcpdm_dma = { |
| 4327 | .master = &omap44xx_l4_abe_hwmod, |
| 4328 | .slave = &omap44xx_mcpdm_hwmod, |
| 4329 | .clk = "ocp_abe_iclk", |
| 4330 | .addr = omap44xx_mcpdm_dma_addrs, |
| 4331 | .user = OCP_USER_SDMA, |
| 4332 | }; |
| 4333 | |
| 4334 | static struct omap_hwmod_addr_space omap44xx_mcspi1_addrs[] = { |
| 4335 | { |
| 4336 | .pa_start = 0x48098000, |
| 4337 | .pa_end = 0x480981ff, |
| 4338 | .flags = ADDR_TYPE_RT |
| 4339 | }, |
| 4340 | { } |
| 4341 | }; |
| 4342 | |
| 4343 | /* l4_per -> mcspi1 */ |
| 4344 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi1 = { |
| 4345 | .master = &omap44xx_l4_per_hwmod, |
| 4346 | .slave = &omap44xx_mcspi1_hwmod, |
| 4347 | .clk = "l4_div_ck", |
| 4348 | .addr = omap44xx_mcspi1_addrs, |
| 4349 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4350 | }; |
| 4351 | |
| 4352 | static struct omap_hwmod_addr_space omap44xx_mcspi2_addrs[] = { |
| 4353 | { |
| 4354 | .pa_start = 0x4809a000, |
| 4355 | .pa_end = 0x4809a1ff, |
| 4356 | .flags = ADDR_TYPE_RT |
| 4357 | }, |
| 4358 | { } |
| 4359 | }; |
| 4360 | |
| 4361 | /* l4_per -> mcspi2 */ |
| 4362 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi2 = { |
| 4363 | .master = &omap44xx_l4_per_hwmod, |
| 4364 | .slave = &omap44xx_mcspi2_hwmod, |
| 4365 | .clk = "l4_div_ck", |
| 4366 | .addr = omap44xx_mcspi2_addrs, |
| 4367 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4368 | }; |
| 4369 | |
| 4370 | static struct omap_hwmod_addr_space omap44xx_mcspi3_addrs[] = { |
| 4371 | { |
| 4372 | .pa_start = 0x480b8000, |
| 4373 | .pa_end = 0x480b81ff, |
| 4374 | .flags = ADDR_TYPE_RT |
| 4375 | }, |
| 4376 | { } |
| 4377 | }; |
| 4378 | |
| 4379 | /* l4_per -> mcspi3 */ |
| 4380 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi3 = { |
| 4381 | .master = &omap44xx_l4_per_hwmod, |
| 4382 | .slave = &omap44xx_mcspi3_hwmod, |
| 4383 | .clk = "l4_div_ck", |
| 4384 | .addr = omap44xx_mcspi3_addrs, |
| 4385 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4386 | }; |
| 4387 | |
| 4388 | static struct omap_hwmod_addr_space omap44xx_mcspi4_addrs[] = { |
| 4389 | { |
| 4390 | .pa_start = 0x480ba000, |
| 4391 | .pa_end = 0x480ba1ff, |
| 4392 | .flags = ADDR_TYPE_RT |
| 4393 | }, |
| 4394 | { } |
| 4395 | }; |
| 4396 | |
| 4397 | /* l4_per -> mcspi4 */ |
| 4398 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mcspi4 = { |
| 4399 | .master = &omap44xx_l4_per_hwmod, |
| 4400 | .slave = &omap44xx_mcspi4_hwmod, |
| 4401 | .clk = "l4_div_ck", |
| 4402 | .addr = omap44xx_mcspi4_addrs, |
| 4403 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4404 | }; |
| 4405 | |
| 4406 | static struct omap_hwmod_addr_space omap44xx_mmc1_addrs[] = { |
| 4407 | { |
| 4408 | .pa_start = 0x4809c000, |
| 4409 | .pa_end = 0x4809c3ff, |
| 4410 | .flags = ADDR_TYPE_RT |
| 4411 | }, |
| 4412 | { } |
| 4413 | }; |
| 4414 | |
| 4415 | /* l4_per -> mmc1 */ |
| 4416 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc1 = { |
| 4417 | .master = &omap44xx_l4_per_hwmod, |
| 4418 | .slave = &omap44xx_mmc1_hwmod, |
| 4419 | .clk = "l4_div_ck", |
| 4420 | .addr = omap44xx_mmc1_addrs, |
| 4421 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4422 | }; |
| 4423 | |
| 4424 | static struct omap_hwmod_addr_space omap44xx_mmc2_addrs[] = { |
| 4425 | { |
| 4426 | .pa_start = 0x480b4000, |
| 4427 | .pa_end = 0x480b43ff, |
| 4428 | .flags = ADDR_TYPE_RT |
| 4429 | }, |
| 4430 | { } |
| 4431 | }; |
| 4432 | |
| 4433 | /* l4_per -> mmc2 */ |
| 4434 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc2 = { |
| 4435 | .master = &omap44xx_l4_per_hwmod, |
| 4436 | .slave = &omap44xx_mmc2_hwmod, |
| 4437 | .clk = "l4_div_ck", |
| 4438 | .addr = omap44xx_mmc2_addrs, |
| 4439 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4440 | }; |
| 4441 | |
| 4442 | static struct omap_hwmod_addr_space omap44xx_mmc3_addrs[] = { |
| 4443 | { |
| 4444 | .pa_start = 0x480ad000, |
| 4445 | .pa_end = 0x480ad3ff, |
| 4446 | .flags = ADDR_TYPE_RT |
| 4447 | }, |
| 4448 | { } |
| 4449 | }; |
| 4450 | |
| 4451 | /* l4_per -> mmc3 */ |
| 4452 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc3 = { |
| 4453 | .master = &omap44xx_l4_per_hwmod, |
| 4454 | .slave = &omap44xx_mmc3_hwmod, |
| 4455 | .clk = "l4_div_ck", |
| 4456 | .addr = omap44xx_mmc3_addrs, |
| 4457 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4458 | }; |
| 4459 | |
| 4460 | static struct omap_hwmod_addr_space omap44xx_mmc4_addrs[] = { |
| 4461 | { |
| 4462 | .pa_start = 0x480d1000, |
| 4463 | .pa_end = 0x480d13ff, |
| 4464 | .flags = ADDR_TYPE_RT |
| 4465 | }, |
| 4466 | { } |
| 4467 | }; |
| 4468 | |
| 4469 | /* l4_per -> mmc4 */ |
| 4470 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc4 = { |
| 4471 | .master = &omap44xx_l4_per_hwmod, |
| 4472 | .slave = &omap44xx_mmc4_hwmod, |
| 4473 | .clk = "l4_div_ck", |
| 4474 | .addr = omap44xx_mmc4_addrs, |
| 4475 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4476 | }; |
| 4477 | |
| 4478 | static struct omap_hwmod_addr_space omap44xx_mmc5_addrs[] = { |
| 4479 | { |
| 4480 | .pa_start = 0x480d5000, |
| 4481 | .pa_end = 0x480d53ff, |
| 4482 | .flags = ADDR_TYPE_RT |
| 4483 | }, |
| 4484 | { } |
| 4485 | }; |
| 4486 | |
| 4487 | /* l4_per -> mmc5 */ |
| 4488 | static struct omap_hwmod_ocp_if omap44xx_l4_per__mmc5 = { |
| 4489 | .master = &omap44xx_l4_per_hwmod, |
| 4490 | .slave = &omap44xx_mmc5_hwmod, |
| 4491 | .clk = "l4_div_ck", |
| 4492 | .addr = omap44xx_mmc5_addrs, |
| 4493 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4494 | }; |
| 4495 | |
| 4496 | static struct omap_hwmod_addr_space omap44xx_smartreflex_core_addrs[] = { |
| 4497 | { |
| 4498 | .pa_start = 0x4a0dd000, |
| 4499 | .pa_end = 0x4a0dd03f, |
| 4500 | .flags = ADDR_TYPE_RT |
| 4501 | }, |
| 4502 | { } |
| 4503 | }; |
| 4504 | |
| 4505 | /* l4_cfg -> smartreflex_core */ |
| 4506 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_core = { |
| 4507 | .master = &omap44xx_l4_cfg_hwmod, |
| 4508 | .slave = &omap44xx_smartreflex_core_hwmod, |
| 4509 | .clk = "l4_div_ck", |
| 4510 | .addr = omap44xx_smartreflex_core_addrs, |
| 4511 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4512 | }; |
| 4513 | |
| 4514 | static struct omap_hwmod_addr_space omap44xx_smartreflex_iva_addrs[] = { |
| 4515 | { |
| 4516 | .pa_start = 0x4a0db000, |
| 4517 | .pa_end = 0x4a0db03f, |
| 4518 | .flags = ADDR_TYPE_RT |
| 4519 | }, |
| 4520 | { } |
| 4521 | }; |
| 4522 | |
| 4523 | /* l4_cfg -> smartreflex_iva */ |
| 4524 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_iva = { |
| 4525 | .master = &omap44xx_l4_cfg_hwmod, |
| 4526 | .slave = &omap44xx_smartreflex_iva_hwmod, |
| 4527 | .clk = "l4_div_ck", |
| 4528 | .addr = omap44xx_smartreflex_iva_addrs, |
| 4529 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4530 | }; |
| 4531 | |
| 4532 | static struct omap_hwmod_addr_space omap44xx_smartreflex_mpu_addrs[] = { |
| 4533 | { |
| 4534 | .pa_start = 0x4a0d9000, |
| 4535 | .pa_end = 0x4a0d903f, |
| 4536 | .flags = ADDR_TYPE_RT |
| 4537 | }, |
| 4538 | { } |
| 4539 | }; |
| 4540 | |
| 4541 | /* l4_cfg -> smartreflex_mpu */ |
| 4542 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__smartreflex_mpu = { |
| 4543 | .master = &omap44xx_l4_cfg_hwmod, |
| 4544 | .slave = &omap44xx_smartreflex_mpu_hwmod, |
| 4545 | .clk = "l4_div_ck", |
| 4546 | .addr = omap44xx_smartreflex_mpu_addrs, |
| 4547 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4548 | }; |
| 4549 | |
| 4550 | static struct omap_hwmod_addr_space omap44xx_spinlock_addrs[] = { |
| 4551 | { |
| 4552 | .pa_start = 0x4a0f6000, |
| 4553 | .pa_end = 0x4a0f6fff, |
| 4554 | .flags = ADDR_TYPE_RT |
| 4555 | }, |
| 4556 | { } |
| 4557 | }; |
| 4558 | |
| 4559 | /* l4_cfg -> spinlock */ |
| 4560 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__spinlock = { |
| 4561 | .master = &omap44xx_l4_cfg_hwmod, |
| 4562 | .slave = &omap44xx_spinlock_hwmod, |
| 4563 | .clk = "l4_div_ck", |
| 4564 | .addr = omap44xx_spinlock_addrs, |
| 4565 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4566 | }; |
| 4567 | |
| 4568 | static struct omap_hwmod_addr_space omap44xx_timer1_addrs[] = { |
| 4569 | { |
| 4570 | .pa_start = 0x4a318000, |
| 4571 | .pa_end = 0x4a31807f, |
| 4572 | .flags = ADDR_TYPE_RT |
| 4573 | }, |
| 4574 | { } |
| 4575 | }; |
| 4576 | |
| 4577 | /* l4_wkup -> timer1 */ |
| 4578 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__timer1 = { |
| 4579 | .master = &omap44xx_l4_wkup_hwmod, |
| 4580 | .slave = &omap44xx_timer1_hwmod, |
| 4581 | .clk = "l4_wkup_clk_mux_ck", |
| 4582 | .addr = omap44xx_timer1_addrs, |
| 4583 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4584 | }; |
| 4585 | |
| 4586 | static struct omap_hwmod_addr_space omap44xx_timer2_addrs[] = { |
| 4587 | { |
| 4588 | .pa_start = 0x48032000, |
| 4589 | .pa_end = 0x4803207f, |
| 4590 | .flags = ADDR_TYPE_RT |
| 4591 | }, |
| 4592 | { } |
| 4593 | }; |
| 4594 | |
| 4595 | /* l4_per -> timer2 */ |
| 4596 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer2 = { |
| 4597 | .master = &omap44xx_l4_per_hwmod, |
| 4598 | .slave = &omap44xx_timer2_hwmod, |
| 4599 | .clk = "l4_div_ck", |
| 4600 | .addr = omap44xx_timer2_addrs, |
| 4601 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4602 | }; |
| 4603 | |
| 4604 | static struct omap_hwmod_addr_space omap44xx_timer3_addrs[] = { |
| 4605 | { |
| 4606 | .pa_start = 0x48034000, |
| 4607 | .pa_end = 0x4803407f, |
| 4608 | .flags = ADDR_TYPE_RT |
| 4609 | }, |
| 4610 | { } |
| 4611 | }; |
| 4612 | |
| 4613 | /* l4_per -> timer3 */ |
| 4614 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer3 = { |
| 4615 | .master = &omap44xx_l4_per_hwmod, |
| 4616 | .slave = &omap44xx_timer3_hwmod, |
| 4617 | .clk = "l4_div_ck", |
| 4618 | .addr = omap44xx_timer3_addrs, |
| 4619 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4620 | }; |
| 4621 | |
| 4622 | static struct omap_hwmod_addr_space omap44xx_timer4_addrs[] = { |
| 4623 | { |
| 4624 | .pa_start = 0x48036000, |
| 4625 | .pa_end = 0x4803607f, |
| 4626 | .flags = ADDR_TYPE_RT |
| 4627 | }, |
| 4628 | { } |
| 4629 | }; |
| 4630 | |
| 4631 | /* l4_per -> timer4 */ |
| 4632 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer4 = { |
| 4633 | .master = &omap44xx_l4_per_hwmod, |
| 4634 | .slave = &omap44xx_timer4_hwmod, |
| 4635 | .clk = "l4_div_ck", |
| 4636 | .addr = omap44xx_timer4_addrs, |
| 4637 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4638 | }; |
| 4639 | |
| 4640 | static struct omap_hwmod_addr_space omap44xx_timer5_addrs[] = { |
| 4641 | { |
| 4642 | .pa_start = 0x40138000, |
| 4643 | .pa_end = 0x4013807f, |
| 4644 | .flags = ADDR_TYPE_RT |
| 4645 | }, |
| 4646 | { } |
| 4647 | }; |
| 4648 | |
| 4649 | /* l4_abe -> timer5 */ |
| 4650 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5 = { |
| 4651 | .master = &omap44xx_l4_abe_hwmod, |
| 4652 | .slave = &omap44xx_timer5_hwmod, |
| 4653 | .clk = "ocp_abe_iclk", |
| 4654 | .addr = omap44xx_timer5_addrs, |
| 4655 | .user = OCP_USER_MPU, |
| 4656 | }; |
| 4657 | |
| 4658 | static struct omap_hwmod_addr_space omap44xx_timer5_dma_addrs[] = { |
| 4659 | { |
| 4660 | .pa_start = 0x49038000, |
| 4661 | .pa_end = 0x4903807f, |
| 4662 | .flags = ADDR_TYPE_RT |
| 4663 | }, |
| 4664 | { } |
| 4665 | }; |
| 4666 | |
| 4667 | /* l4_abe -> timer5 (dma) */ |
| 4668 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer5_dma = { |
| 4669 | .master = &omap44xx_l4_abe_hwmod, |
| 4670 | .slave = &omap44xx_timer5_hwmod, |
| 4671 | .clk = "ocp_abe_iclk", |
| 4672 | .addr = omap44xx_timer5_dma_addrs, |
| 4673 | .user = OCP_USER_SDMA, |
| 4674 | }; |
| 4675 | |
| 4676 | static struct omap_hwmod_addr_space omap44xx_timer6_addrs[] = { |
| 4677 | { |
| 4678 | .pa_start = 0x4013a000, |
| 4679 | .pa_end = 0x4013a07f, |
| 4680 | .flags = ADDR_TYPE_RT |
| 4681 | }, |
| 4682 | { } |
| 4683 | }; |
| 4684 | |
| 4685 | /* l4_abe -> timer6 */ |
| 4686 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6 = { |
| 4687 | .master = &omap44xx_l4_abe_hwmod, |
| 4688 | .slave = &omap44xx_timer6_hwmod, |
| 4689 | .clk = "ocp_abe_iclk", |
| 4690 | .addr = omap44xx_timer6_addrs, |
| 4691 | .user = OCP_USER_MPU, |
| 4692 | }; |
| 4693 | |
| 4694 | static struct omap_hwmod_addr_space omap44xx_timer6_dma_addrs[] = { |
| 4695 | { |
| 4696 | .pa_start = 0x4903a000, |
| 4697 | .pa_end = 0x4903a07f, |
| 4698 | .flags = ADDR_TYPE_RT |
| 4699 | }, |
| 4700 | { } |
| 4701 | }; |
| 4702 | |
| 4703 | /* l4_abe -> timer6 (dma) */ |
| 4704 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer6_dma = { |
| 4705 | .master = &omap44xx_l4_abe_hwmod, |
| 4706 | .slave = &omap44xx_timer6_hwmod, |
| 4707 | .clk = "ocp_abe_iclk", |
| 4708 | .addr = omap44xx_timer6_dma_addrs, |
| 4709 | .user = OCP_USER_SDMA, |
| 4710 | }; |
| 4711 | |
| 4712 | static struct omap_hwmod_addr_space omap44xx_timer7_addrs[] = { |
| 4713 | { |
| 4714 | .pa_start = 0x4013c000, |
| 4715 | .pa_end = 0x4013c07f, |
| 4716 | .flags = ADDR_TYPE_RT |
| 4717 | }, |
| 4718 | { } |
| 4719 | }; |
| 4720 | |
| 4721 | /* l4_abe -> timer7 */ |
| 4722 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7 = { |
| 4723 | .master = &omap44xx_l4_abe_hwmod, |
| 4724 | .slave = &omap44xx_timer7_hwmod, |
| 4725 | .clk = "ocp_abe_iclk", |
| 4726 | .addr = omap44xx_timer7_addrs, |
| 4727 | .user = OCP_USER_MPU, |
| 4728 | }; |
| 4729 | |
| 4730 | static struct omap_hwmod_addr_space omap44xx_timer7_dma_addrs[] = { |
| 4731 | { |
| 4732 | .pa_start = 0x4903c000, |
| 4733 | .pa_end = 0x4903c07f, |
| 4734 | .flags = ADDR_TYPE_RT |
| 4735 | }, |
| 4736 | { } |
| 4737 | }; |
| 4738 | |
| 4739 | /* l4_abe -> timer7 (dma) */ |
| 4740 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer7_dma = { |
| 4741 | .master = &omap44xx_l4_abe_hwmod, |
| 4742 | .slave = &omap44xx_timer7_hwmod, |
| 4743 | .clk = "ocp_abe_iclk", |
| 4744 | .addr = omap44xx_timer7_dma_addrs, |
| 4745 | .user = OCP_USER_SDMA, |
| 4746 | }; |
| 4747 | |
| 4748 | static struct omap_hwmod_addr_space omap44xx_timer8_addrs[] = { |
| 4749 | { |
| 4750 | .pa_start = 0x4013e000, |
| 4751 | .pa_end = 0x4013e07f, |
| 4752 | .flags = ADDR_TYPE_RT |
| 4753 | }, |
| 4754 | { } |
| 4755 | }; |
| 4756 | |
| 4757 | /* l4_abe -> timer8 */ |
| 4758 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8 = { |
| 4759 | .master = &omap44xx_l4_abe_hwmod, |
| 4760 | .slave = &omap44xx_timer8_hwmod, |
| 4761 | .clk = "ocp_abe_iclk", |
| 4762 | .addr = omap44xx_timer8_addrs, |
| 4763 | .user = OCP_USER_MPU, |
| 4764 | }; |
| 4765 | |
| 4766 | static struct omap_hwmod_addr_space omap44xx_timer8_dma_addrs[] = { |
| 4767 | { |
| 4768 | .pa_start = 0x4903e000, |
| 4769 | .pa_end = 0x4903e07f, |
| 4770 | .flags = ADDR_TYPE_RT |
| 4771 | }, |
| 4772 | { } |
| 4773 | }; |
| 4774 | |
| 4775 | /* l4_abe -> timer8 (dma) */ |
| 4776 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__timer8_dma = { |
| 4777 | .master = &omap44xx_l4_abe_hwmod, |
| 4778 | .slave = &omap44xx_timer8_hwmod, |
| 4779 | .clk = "ocp_abe_iclk", |
| 4780 | .addr = omap44xx_timer8_dma_addrs, |
| 4781 | .user = OCP_USER_SDMA, |
| 4782 | }; |
| 4783 | |
| 4784 | static struct omap_hwmod_addr_space omap44xx_timer9_addrs[] = { |
| 4785 | { |
| 4786 | .pa_start = 0x4803e000, |
| 4787 | .pa_end = 0x4803e07f, |
| 4788 | .flags = ADDR_TYPE_RT |
| 4789 | }, |
| 4790 | { } |
| 4791 | }; |
| 4792 | |
| 4793 | /* l4_per -> timer9 */ |
| 4794 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer9 = { |
| 4795 | .master = &omap44xx_l4_per_hwmod, |
| 4796 | .slave = &omap44xx_timer9_hwmod, |
| 4797 | .clk = "l4_div_ck", |
| 4798 | .addr = omap44xx_timer9_addrs, |
| 4799 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4800 | }; |
| 4801 | |
| 4802 | static struct omap_hwmod_addr_space omap44xx_timer10_addrs[] = { |
| 4803 | { |
| 4804 | .pa_start = 0x48086000, |
| 4805 | .pa_end = 0x4808607f, |
| 4806 | .flags = ADDR_TYPE_RT |
| 4807 | }, |
| 4808 | { } |
| 4809 | }; |
| 4810 | |
| 4811 | /* l4_per -> timer10 */ |
| 4812 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer10 = { |
| 4813 | .master = &omap44xx_l4_per_hwmod, |
| 4814 | .slave = &omap44xx_timer10_hwmod, |
| 4815 | .clk = "l4_div_ck", |
| 4816 | .addr = omap44xx_timer10_addrs, |
| 4817 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4818 | }; |
| 4819 | |
| 4820 | static struct omap_hwmod_addr_space omap44xx_timer11_addrs[] = { |
| 4821 | { |
| 4822 | .pa_start = 0x48088000, |
| 4823 | .pa_end = 0x4808807f, |
| 4824 | .flags = ADDR_TYPE_RT |
| 4825 | }, |
| 4826 | { } |
| 4827 | }; |
| 4828 | |
| 4829 | /* l4_per -> timer11 */ |
| 4830 | static struct omap_hwmod_ocp_if omap44xx_l4_per__timer11 = { |
| 4831 | .master = &omap44xx_l4_per_hwmod, |
| 4832 | .slave = &omap44xx_timer11_hwmod, |
| 4833 | .clk = "l4_div_ck", |
| 4834 | .addr = omap44xx_timer11_addrs, |
| 4835 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4836 | }; |
| 4837 | |
| 4838 | static struct omap_hwmod_addr_space omap44xx_uart1_addrs[] = { |
| 4839 | { |
| 4840 | .pa_start = 0x4806a000, |
| 4841 | .pa_end = 0x4806a0ff, |
| 4842 | .flags = ADDR_TYPE_RT |
| 4843 | }, |
| 4844 | { } |
| 4845 | }; |
| 4846 | |
| 4847 | /* l4_per -> uart1 */ |
| 4848 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart1 = { |
| 4849 | .master = &omap44xx_l4_per_hwmod, |
| 4850 | .slave = &omap44xx_uart1_hwmod, |
| 4851 | .clk = "l4_div_ck", |
| 4852 | .addr = omap44xx_uart1_addrs, |
| 4853 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4854 | }; |
| 4855 | |
| 4856 | static struct omap_hwmod_addr_space omap44xx_uart2_addrs[] = { |
| 4857 | { |
| 4858 | .pa_start = 0x4806c000, |
| 4859 | .pa_end = 0x4806c0ff, |
| 4860 | .flags = ADDR_TYPE_RT |
| 4861 | }, |
| 4862 | { } |
| 4863 | }; |
| 4864 | |
| 4865 | /* l4_per -> uart2 */ |
| 4866 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart2 = { |
| 4867 | .master = &omap44xx_l4_per_hwmod, |
| 4868 | .slave = &omap44xx_uart2_hwmod, |
| 4869 | .clk = "l4_div_ck", |
| 4870 | .addr = omap44xx_uart2_addrs, |
| 4871 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4872 | }; |
| 4873 | |
| 4874 | static struct omap_hwmod_addr_space omap44xx_uart3_addrs[] = { |
| 4875 | { |
| 4876 | .pa_start = 0x48020000, |
| 4877 | .pa_end = 0x480200ff, |
| 4878 | .flags = ADDR_TYPE_RT |
| 4879 | }, |
| 4880 | { } |
| 4881 | }; |
| 4882 | |
| 4883 | /* l4_per -> uart3 */ |
| 4884 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart3 = { |
| 4885 | .master = &omap44xx_l4_per_hwmod, |
| 4886 | .slave = &omap44xx_uart3_hwmod, |
| 4887 | .clk = "l4_div_ck", |
| 4888 | .addr = omap44xx_uart3_addrs, |
| 4889 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4890 | }; |
| 4891 | |
| 4892 | static struct omap_hwmod_addr_space omap44xx_uart4_addrs[] = { |
| 4893 | { |
| 4894 | .pa_start = 0x4806e000, |
| 4895 | .pa_end = 0x4806e0ff, |
| 4896 | .flags = ADDR_TYPE_RT |
| 4897 | }, |
| 4898 | { } |
| 4899 | }; |
| 4900 | |
| 4901 | /* l4_per -> uart4 */ |
| 4902 | static struct omap_hwmod_ocp_if omap44xx_l4_per__uart4 = { |
| 4903 | .master = &omap44xx_l4_per_hwmod, |
| 4904 | .slave = &omap44xx_uart4_hwmod, |
| 4905 | .clk = "l4_div_ck", |
| 4906 | .addr = omap44xx_uart4_addrs, |
| 4907 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4908 | }; |
| 4909 | |
| 4910 | static struct omap_hwmod_addr_space omap44xx_usb_host_hs_addrs[] = { |
| 4911 | { |
| 4912 | .name = "uhh", |
| 4913 | .pa_start = 0x4a064000, |
| 4914 | .pa_end = 0x4a0647ff, |
| 4915 | .flags = ADDR_TYPE_RT |
| 4916 | }, |
| 4917 | { |
| 4918 | .name = "ohci", |
| 4919 | .pa_start = 0x4a064800, |
| 4920 | .pa_end = 0x4a064bff, |
| 4921 | }, |
| 4922 | { |
| 4923 | .name = "ehci", |
| 4924 | .pa_start = 0x4a064c00, |
| 4925 | .pa_end = 0x4a064fff, |
| 4926 | }, |
| 4927 | {} |
| 4928 | }; |
| 4929 | |
| 4930 | /* l4_cfg -> usb_host_hs */ |
| 4931 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_host_hs = { |
| 4932 | .master = &omap44xx_l4_cfg_hwmod, |
| 4933 | .slave = &omap44xx_usb_host_hs_hwmod, |
| 4934 | .clk = "l4_div_ck", |
| 4935 | .addr = omap44xx_usb_host_hs_addrs, |
| 4936 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4937 | }; |
| 4938 | |
| 4939 | static struct omap_hwmod_addr_space omap44xx_usb_otg_hs_addrs[] = { |
| 4940 | { |
| 4941 | .pa_start = 0x4a0ab000, |
| 4942 | .pa_end = 0x4a0ab003, |
| 4943 | .flags = ADDR_TYPE_RT |
| 4944 | }, |
| 4945 | { } |
| 4946 | }; |
| 4947 | |
| 4948 | /* l4_cfg -> usb_otg_hs */ |
| 4949 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_otg_hs = { |
| 4950 | .master = &omap44xx_l4_cfg_hwmod, |
| 4951 | .slave = &omap44xx_usb_otg_hs_hwmod, |
| 4952 | .clk = "l4_div_ck", |
| 4953 | .addr = omap44xx_usb_otg_hs_addrs, |
| 4954 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4955 | }; |
| 4956 | |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 4957 | static struct omap_hwmod_addr_space omap44xx_usb_tll_hs_addrs[] = { |
| 4958 | { |
| 4959 | .name = "tll", |
| 4960 | .pa_start = 0x4a062000, |
| 4961 | .pa_end = 0x4a063fff, |
| 4962 | .flags = ADDR_TYPE_RT |
| 4963 | }, |
| 4964 | {} |
| 4965 | }; |
| 4966 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 4967 | /* l4_cfg -> usb_tll_hs */ |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 4968 | static struct omap_hwmod_ocp_if omap44xx_l4_cfg__usb_tll_hs = { |
| 4969 | .master = &omap44xx_l4_cfg_hwmod, |
| 4970 | .slave = &omap44xx_usb_tll_hs_hwmod, |
| 4971 | .clk = "l4_div_ck", |
| 4972 | .addr = omap44xx_usb_tll_hs_addrs, |
| 4973 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4974 | }; |
| 4975 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 4976 | static struct omap_hwmod_addr_space omap44xx_wd_timer2_addrs[] = { |
| 4977 | { |
| 4978 | .pa_start = 0x4a314000, |
| 4979 | .pa_end = 0x4a31407f, |
| 4980 | .flags = ADDR_TYPE_RT |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 4981 | }, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 4982 | { } |
| 4983 | }; |
| 4984 | |
| 4985 | /* l4_wkup -> wd_timer2 */ |
| 4986 | static struct omap_hwmod_ocp_if omap44xx_l4_wkup__wd_timer2 = { |
| 4987 | .master = &omap44xx_l4_wkup_hwmod, |
| 4988 | .slave = &omap44xx_wd_timer2_hwmod, |
| 4989 | .clk = "l4_wkup_clk_mux_ck", |
| 4990 | .addr = omap44xx_wd_timer2_addrs, |
| 4991 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 4992 | }; |
| 4993 | |
| 4994 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_addrs[] = { |
| 4995 | { |
| 4996 | .pa_start = 0x40130000, |
| 4997 | .pa_end = 0x4013007f, |
| 4998 | .flags = ADDR_TYPE_RT |
| 4999 | }, |
| 5000 | { } |
| 5001 | }; |
| 5002 | |
| 5003 | /* l4_abe -> wd_timer3 */ |
| 5004 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3 = { |
| 5005 | .master = &omap44xx_l4_abe_hwmod, |
| 5006 | .slave = &omap44xx_wd_timer3_hwmod, |
| 5007 | .clk = "ocp_abe_iclk", |
| 5008 | .addr = omap44xx_wd_timer3_addrs, |
| 5009 | .user = OCP_USER_MPU, |
| 5010 | }; |
| 5011 | |
| 5012 | static struct omap_hwmod_addr_space omap44xx_wd_timer3_dma_addrs[] = { |
| 5013 | { |
| 5014 | .pa_start = 0x49030000, |
| 5015 | .pa_end = 0x4903007f, |
| 5016 | .flags = ADDR_TYPE_RT |
| 5017 | }, |
| 5018 | { } |
| 5019 | }; |
| 5020 | |
| 5021 | /* l4_abe -> wd_timer3 (dma) */ |
| 5022 | static struct omap_hwmod_ocp_if omap44xx_l4_abe__wd_timer3_dma = { |
| 5023 | .master = &omap44xx_l4_abe_hwmod, |
| 5024 | .slave = &omap44xx_wd_timer3_hwmod, |
| 5025 | .clk = "ocp_abe_iclk", |
| 5026 | .addr = omap44xx_wd_timer3_dma_addrs, |
| 5027 | .user = OCP_USER_SDMA, |
Benoit Cousson | af88fa9 | 2011-12-15 23:15:18 -0700 | [diff] [blame] | 5028 | }; |
| 5029 | |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 5030 | static struct omap_hwmod_ocp_if *omap44xx_hwmod_ocp_ifs[] __initdata = { |
| 5031 | &omap44xx_l3_main_1__dmm, |
| 5032 | &omap44xx_mpu__dmm, |
| 5033 | &omap44xx_dmm__emif_fw, |
| 5034 | &omap44xx_l4_cfg__emif_fw, |
| 5035 | &omap44xx_iva__l3_instr, |
| 5036 | &omap44xx_l3_main_3__l3_instr, |
| 5037 | &omap44xx_dsp__l3_main_1, |
| 5038 | &omap44xx_dss__l3_main_1, |
| 5039 | &omap44xx_l3_main_2__l3_main_1, |
| 5040 | &omap44xx_l4_cfg__l3_main_1, |
| 5041 | &omap44xx_mmc1__l3_main_1, |
| 5042 | &omap44xx_mmc2__l3_main_1, |
| 5043 | &omap44xx_mpu__l3_main_1, |
| 5044 | &omap44xx_dma_system__l3_main_2, |
Ming Lei | b050f68 | 2012-04-19 13:33:50 -0600 | [diff] [blame] | 5045 | &omap44xx_fdif__l3_main_2, |
Paul Walmsley | 9def390 | 2012-04-19 13:33:53 -0600 | [diff] [blame^] | 5046 | &omap44xx_gpu__l3_main_2, |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 5047 | &omap44xx_hsi__l3_main_2, |
| 5048 | &omap44xx_ipu__l3_main_2, |
| 5049 | &omap44xx_iss__l3_main_2, |
| 5050 | &omap44xx_iva__l3_main_2, |
| 5051 | &omap44xx_l3_main_1__l3_main_2, |
| 5052 | &omap44xx_l4_cfg__l3_main_2, |
| 5053 | &omap44xx_usb_host_hs__l3_main_2, |
| 5054 | &omap44xx_usb_otg_hs__l3_main_2, |
| 5055 | &omap44xx_l3_main_1__l3_main_3, |
| 5056 | &omap44xx_l3_main_2__l3_main_3, |
| 5057 | &omap44xx_l4_cfg__l3_main_3, |
| 5058 | &omap44xx_aess__l4_abe, |
| 5059 | &omap44xx_dsp__l4_abe, |
| 5060 | &omap44xx_l3_main_1__l4_abe, |
| 5061 | &omap44xx_mpu__l4_abe, |
| 5062 | &omap44xx_l3_main_1__l4_cfg, |
| 5063 | &omap44xx_l3_main_2__l4_per, |
| 5064 | &omap44xx_l4_cfg__l4_wkup, |
| 5065 | &omap44xx_mpu__mpu_private, |
| 5066 | &omap44xx_l4_abe__aess, |
| 5067 | &omap44xx_l4_abe__aess_dma, |
| 5068 | &omap44xx_l4_wkup__counter_32k, |
| 5069 | &omap44xx_l4_cfg__dma_system, |
| 5070 | &omap44xx_l4_abe__dmic, |
| 5071 | &omap44xx_l4_abe__dmic_dma, |
| 5072 | &omap44xx_dsp__iva, |
| 5073 | &omap44xx_l4_cfg__dsp, |
| 5074 | &omap44xx_l3_main_2__dss, |
| 5075 | &omap44xx_l4_per__dss, |
| 5076 | &omap44xx_l3_main_2__dss_dispc, |
| 5077 | &omap44xx_l4_per__dss_dispc, |
| 5078 | &omap44xx_l3_main_2__dss_dsi1, |
| 5079 | &omap44xx_l4_per__dss_dsi1, |
| 5080 | &omap44xx_l3_main_2__dss_dsi2, |
| 5081 | &omap44xx_l4_per__dss_dsi2, |
| 5082 | &omap44xx_l3_main_2__dss_hdmi, |
| 5083 | &omap44xx_l4_per__dss_hdmi, |
| 5084 | &omap44xx_l3_main_2__dss_rfbi, |
| 5085 | &omap44xx_l4_per__dss_rfbi, |
| 5086 | &omap44xx_l3_main_2__dss_venc, |
| 5087 | &omap44xx_l4_per__dss_venc, |
Paul Walmsley | bf30f95 | 2012-04-19 13:33:52 -0600 | [diff] [blame] | 5088 | &omap44xx_emif_fw__emif1, |
| 5089 | &omap44xx_emif_fw__emif2, |
Ming Lei | b050f68 | 2012-04-19 13:33:50 -0600 | [diff] [blame] | 5090 | &omap44xx_l4_cfg__fdif, |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 5091 | &omap44xx_l4_wkup__gpio1, |
| 5092 | &omap44xx_l4_per__gpio2, |
| 5093 | &omap44xx_l4_per__gpio3, |
| 5094 | &omap44xx_l4_per__gpio4, |
| 5095 | &omap44xx_l4_per__gpio5, |
| 5096 | &omap44xx_l4_per__gpio6, |
BenoƮt Cousson | eb42b5d | 2012-04-19 13:33:51 -0600 | [diff] [blame] | 5097 | &omap44xx_l3_main_2__gpmc, |
Paul Walmsley | 9def390 | 2012-04-19 13:33:53 -0600 | [diff] [blame^] | 5098 | &omap44xx_l3_main_2__gpu, |
Paul Walmsley | a091c08 | 2012-04-19 13:33:50 -0600 | [diff] [blame] | 5099 | &omap44xx_l4_per__hdq1w, |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 5100 | &omap44xx_l4_cfg__hsi, |
| 5101 | &omap44xx_l4_per__i2c1, |
| 5102 | &omap44xx_l4_per__i2c2, |
| 5103 | &omap44xx_l4_per__i2c3, |
| 5104 | &omap44xx_l4_per__i2c4, |
| 5105 | &omap44xx_l3_main_2__ipu, |
| 5106 | &omap44xx_l3_main_2__iss, |
| 5107 | &omap44xx_l3_main_2__iva, |
| 5108 | &omap44xx_l4_wkup__kbd, |
| 5109 | &omap44xx_l4_cfg__mailbox, |
| 5110 | &omap44xx_l4_abe__mcbsp1, |
| 5111 | &omap44xx_l4_abe__mcbsp1_dma, |
| 5112 | &omap44xx_l4_abe__mcbsp2, |
| 5113 | &omap44xx_l4_abe__mcbsp2_dma, |
| 5114 | &omap44xx_l4_abe__mcbsp3, |
| 5115 | &omap44xx_l4_abe__mcbsp3_dma, |
| 5116 | &omap44xx_l4_per__mcbsp4, |
| 5117 | &omap44xx_l4_abe__mcpdm, |
| 5118 | &omap44xx_l4_abe__mcpdm_dma, |
| 5119 | &omap44xx_l4_per__mcspi1, |
| 5120 | &omap44xx_l4_per__mcspi2, |
| 5121 | &omap44xx_l4_per__mcspi3, |
| 5122 | &omap44xx_l4_per__mcspi4, |
| 5123 | &omap44xx_l4_per__mmc1, |
| 5124 | &omap44xx_l4_per__mmc2, |
| 5125 | &omap44xx_l4_per__mmc3, |
| 5126 | &omap44xx_l4_per__mmc4, |
| 5127 | &omap44xx_l4_per__mmc5, |
| 5128 | &omap44xx_l4_cfg__smartreflex_core, |
| 5129 | &omap44xx_l4_cfg__smartreflex_iva, |
| 5130 | &omap44xx_l4_cfg__smartreflex_mpu, |
| 5131 | &omap44xx_l4_cfg__spinlock, |
| 5132 | &omap44xx_l4_wkup__timer1, |
| 5133 | &omap44xx_l4_per__timer2, |
| 5134 | &omap44xx_l4_per__timer3, |
| 5135 | &omap44xx_l4_per__timer4, |
| 5136 | &omap44xx_l4_abe__timer5, |
| 5137 | &omap44xx_l4_abe__timer5_dma, |
| 5138 | &omap44xx_l4_abe__timer6, |
| 5139 | &omap44xx_l4_abe__timer6_dma, |
| 5140 | &omap44xx_l4_abe__timer7, |
| 5141 | &omap44xx_l4_abe__timer7_dma, |
| 5142 | &omap44xx_l4_abe__timer8, |
| 5143 | &omap44xx_l4_abe__timer8_dma, |
| 5144 | &omap44xx_l4_per__timer9, |
| 5145 | &omap44xx_l4_per__timer10, |
| 5146 | &omap44xx_l4_per__timer11, |
| 5147 | &omap44xx_l4_per__uart1, |
| 5148 | &omap44xx_l4_per__uart2, |
| 5149 | &omap44xx_l4_per__uart3, |
| 5150 | &omap44xx_l4_per__uart4, |
| 5151 | &omap44xx_l4_cfg__usb_host_hs, |
| 5152 | &omap44xx_l4_cfg__usb_otg_hs, |
| 5153 | &omap44xx_l4_cfg__usb_tll_hs, |
| 5154 | &omap44xx_l4_wkup__wd_timer2, |
| 5155 | &omap44xx_l4_abe__wd_timer3, |
| 5156 | &omap44xx_l4_abe__wd_timer3_dma, |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 5157 | NULL, |
| 5158 | }; |
| 5159 | |
| 5160 | int __init omap44xx_hwmod_init(void) |
| 5161 | { |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 5162 | return omap_hwmod_register_links(omap44xx_hwmod_ocp_ifs); |
Benoit Cousson | 55d2cb0 | 2010-05-12 17:54:36 +0200 | [diff] [blame] | 5163 | } |
| 5164 | |