Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Processor capabilities determination functions. |
| 3 | * |
| 4 | * Copyright (C) xxxx the Anonymous |
Ralf Baechle | 010b853 | 2006-01-29 18:42:08 +0000 | [diff] [blame] | 5 | * Copyright (C) 1994 - 2006 Ralf Baechle |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 6 | * Copyright (C) 2003, 2004 Maciej W. Rozycki |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 7 | * Copyright (C) 2001, 2004 MIPS Inc. |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 8 | * |
| 9 | * This program is free software; you can redistribute it and/or |
| 10 | * modify it under the terms of the GNU General Public License |
| 11 | * as published by the Free Software Foundation; either version |
| 12 | * 2 of the License, or (at your option) any later version. |
| 13 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 14 | #include <linux/init.h> |
| 15 | #include <linux/kernel.h> |
| 16 | #include <linux/ptrace.h> |
Ralf Baechle | 631330f | 2009-06-19 14:05:26 +0100 | [diff] [blame] | 17 | #include <linux/smp.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 18 | #include <linux/stddef.h> |
Wu Zhangjin | f8ede0f | 2009-11-17 01:32:59 +0800 | [diff] [blame] | 19 | #include <linux/module.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 20 | |
Ralf Baechle | 5759906 | 2007-02-18 19:07:31 +0000 | [diff] [blame] | 21 | #include <asm/bugs.h> |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <asm/cpu.h> |
| 23 | #include <asm/fpu.h> |
| 24 | #include <asm/mipsregs.h> |
| 25 | #include <asm/system.h> |
David Daney | 654f57b | 2008-09-23 00:07:16 -0700 | [diff] [blame] | 26 | #include <asm/watch.h> |
Chris Dearman | a074f0e | 2009-07-10 01:51:27 -0700 | [diff] [blame] | 27 | #include <asm/spram.h> |
David Daney | 949e51b | 2010-10-14 11:32:33 -0700 | [diff] [blame] | 28 | #include <asm/uaccess.h> |
| 29 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 30 | /* |
| 31 | * Not all of the MIPS CPUs have the "wait" instruction available. Moreover, |
| 32 | * the implementation of the "wait" feature differs between CPU families. This |
| 33 | * points to the function that implements CPU specific wait. |
| 34 | * The wait instruction stops the pipeline and reduces the power consumption of |
| 35 | * the CPU very much. |
| 36 | */ |
Ralf Baechle | 982f6ff | 2009-09-17 02:25:07 +0200 | [diff] [blame] | 37 | void (*cpu_wait)(void); |
Wu Zhangjin | f8ede0f | 2009-11-17 01:32:59 +0800 | [diff] [blame] | 38 | EXPORT_SYMBOL(cpu_wait); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 39 | |
| 40 | static void r3081_wait(void) |
| 41 | { |
| 42 | unsigned long cfg = read_c0_conf(); |
| 43 | write_c0_conf(cfg | R30XX_CONF_HALT); |
| 44 | } |
| 45 | |
| 46 | static void r39xx_wait(void) |
| 47 | { |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 48 | local_irq_disable(); |
| 49 | if (!need_resched()) |
| 50 | write_c0_conf(read_c0_conf() | TX39_CONF_HALT); |
| 51 | local_irq_enable(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 52 | } |
| 53 | |
Atsushi Nemoto | c65a548 | 2007-11-12 02:05:18 +0900 | [diff] [blame] | 54 | extern void r4k_wait(void); |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 55 | |
| 56 | /* |
| 57 | * This variant is preferable as it allows testing need_resched and going to |
| 58 | * sleep depending on the outcome atomically. Unfortunately the "It is |
| 59 | * implementation-dependent whether the pipeline restarts when a non-enabled |
| 60 | * interrupt is requested" restriction in the MIPS32/MIPS64 architecture makes |
| 61 | * using this version a gamble. |
| 62 | */ |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 63 | void r4k_wait_irqoff(void) |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 64 | { |
| 65 | local_irq_disable(); |
| 66 | if (!need_resched()) |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 67 | __asm__(" .set push \n" |
| 68 | " .set mips3 \n" |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 69 | " wait \n" |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 70 | " .set pop \n"); |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 71 | local_irq_enable(); |
Kevin D. Kissell | 8531a35 | 2008-09-09 21:48:52 +0200 | [diff] [blame] | 72 | __asm__(" .globl __pastwait \n" |
| 73 | "__pastwait: \n"); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 74 | } |
| 75 | |
Ralf Baechle | 5a81299 | 2007-07-17 18:49:48 +0100 | [diff] [blame] | 76 | /* |
| 77 | * The RM7000 variant has to handle erratum 38. The workaround is to not |
| 78 | * have any pending stores when the WAIT instruction is executed. |
| 79 | */ |
| 80 | static void rm7k_wait_irqoff(void) |
| 81 | { |
| 82 | local_irq_disable(); |
| 83 | if (!need_resched()) |
| 84 | __asm__( |
| 85 | " .set push \n" |
| 86 | " .set mips3 \n" |
| 87 | " .set noat \n" |
| 88 | " mfc0 $1, $12 \n" |
| 89 | " sync \n" |
| 90 | " mtc0 $1, $12 # stalls until W stage \n" |
| 91 | " wait \n" |
| 92 | " mtc0 $1, $12 # stalls until W stage \n" |
| 93 | " .set pop \n"); |
| 94 | local_irq_enable(); |
| 95 | } |
| 96 | |
Manuel Lauss | 2882b0c | 2009-08-22 18:09:27 +0200 | [diff] [blame] | 97 | /* |
| 98 | * The Au1xxx wait is available only if using 32khz counter or |
| 99 | * external timer source, but specifically not CP0 Counter. |
| 100 | * alchemy/common/time.c may override cpu_wait! |
| 101 | */ |
Pete Popov | 494900a | 2005-04-07 00:42:10 +0000 | [diff] [blame] | 102 | static void au1k_wait(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 103 | { |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 104 | __asm__(" .set mips3 \n" |
| 105 | " cache 0x14, 0(%0) \n" |
| 106 | " cache 0x14, 32(%0) \n" |
| 107 | " sync \n" |
| 108 | " nop \n" |
| 109 | " wait \n" |
| 110 | " nop \n" |
| 111 | " nop \n" |
| 112 | " nop \n" |
| 113 | " nop \n" |
| 114 | " .set mips0 \n" |
Ralf Baechle | 10f650d | 2005-05-25 13:32:49 +0000 | [diff] [blame] | 115 | : : "r" (au1k_wait)); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 116 | } |
| 117 | |
Ralf Baechle | 982f6ff | 2009-09-17 02:25:07 +0200 | [diff] [blame] | 118 | static int __initdata nowait; |
Ralf Baechle | 55d04df | 2005-07-13 19:22:45 +0000 | [diff] [blame] | 119 | |
Atsushi Nemoto | f49a747 | 2007-02-18 01:02:14 +0900 | [diff] [blame] | 120 | static int __init wait_disable(char *s) |
Ralf Baechle | 55d04df | 2005-07-13 19:22:45 +0000 | [diff] [blame] | 121 | { |
| 122 | nowait = 1; |
| 123 | |
| 124 | return 1; |
| 125 | } |
| 126 | |
| 127 | __setup("nowait", wait_disable); |
| 128 | |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 129 | static int __cpuinitdata mips_fpu_disabled; |
| 130 | |
| 131 | static int __init fpu_disable(char *s) |
| 132 | { |
| 133 | cpu_data[0].options &= ~MIPS_CPU_FPU; |
| 134 | mips_fpu_disabled = 1; |
| 135 | |
| 136 | return 1; |
| 137 | } |
| 138 | |
| 139 | __setup("nofpu", fpu_disable); |
| 140 | |
| 141 | int __cpuinitdata mips_dsp_disabled; |
| 142 | |
| 143 | static int __init dsp_disable(char *s) |
| 144 | { |
| 145 | cpu_data[0].ases &= ~MIPS_ASE_DSP; |
| 146 | mips_dsp_disabled = 1; |
| 147 | |
| 148 | return 1; |
| 149 | } |
| 150 | |
| 151 | __setup("nodsp", dsp_disable); |
| 152 | |
Atsushi Nemoto | c65a548 | 2007-11-12 02:05:18 +0900 | [diff] [blame] | 153 | void __init check_wait(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 154 | { |
| 155 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 156 | |
Ralf Baechle | 55d04df | 2005-07-13 19:22:45 +0000 | [diff] [blame] | 157 | if (nowait) { |
Ralf Baechle | c237923 | 2006-11-30 01:14:44 +0000 | [diff] [blame] | 158 | printk("Wait instruction disabled.\n"); |
Ralf Baechle | 55d04df | 2005-07-13 19:22:45 +0000 | [diff] [blame] | 159 | return; |
| 160 | } |
| 161 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 162 | switch (c->cputype) { |
| 163 | case CPU_R3081: |
| 164 | case CPU_R3081E: |
| 165 | cpu_wait = r3081_wait; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | break; |
| 167 | case CPU_TX3927: |
| 168 | cpu_wait = r39xx_wait; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | break; |
| 170 | case CPU_R4200: |
| 171 | /* case CPU_R4300: */ |
| 172 | case CPU_R4600: |
| 173 | case CPU_R4640: |
| 174 | case CPU_R4650: |
| 175 | case CPU_R4700: |
| 176 | case CPU_R5000: |
Shinya Kuribayashi | a644b27 | 2009-03-03 18:05:51 +0900 | [diff] [blame] | 177 | case CPU_R5500: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 178 | case CPU_NEVADA: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 179 | case CPU_4KC: |
| 180 | case CPU_4KEC: |
| 181 | case CPU_4KSC: |
| 182 | case CPU_5KC: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 183 | case CPU_25KF: |
Ralf Baechle | 4b3e975 | 2007-06-21 00:22:34 +0100 | [diff] [blame] | 184 | case CPU_PR4450: |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 185 | case CPU_BMIPS3300: |
| 186 | case CPU_BMIPS4350: |
| 187 | case CPU_BMIPS4380: |
| 188 | case CPU_BMIPS5000: |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 189 | case CPU_CAVIUM_OCTEON: |
David Daney | 6f32946 | 2010-02-10 15:12:48 -0800 | [diff] [blame] | 190 | case CPU_CAVIUM_OCTEON_PLUS: |
David Daney | 0e56b38 | 2010-10-07 16:03:45 -0700 | [diff] [blame] | 191 | case CPU_CAVIUM_OCTEON2: |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 192 | case CPU_JZRISC: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 193 | cpu_wait = r4k_wait; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 194 | break; |
Ralf Baechle | 4b3e975 | 2007-06-21 00:22:34 +0100 | [diff] [blame] | 195 | |
Ralf Baechle | 5a81299 | 2007-07-17 18:49:48 +0100 | [diff] [blame] | 196 | case CPU_RM7000: |
| 197 | cpu_wait = rm7k_wait_irqoff; |
| 198 | break; |
| 199 | |
Ralf Baechle | 4b3e975 | 2007-06-21 00:22:34 +0100 | [diff] [blame] | 200 | case CPU_24K: |
| 201 | case CPU_34K: |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 202 | case CPU_1004K: |
Ralf Baechle | 4b3e975 | 2007-06-21 00:22:34 +0100 | [diff] [blame] | 203 | cpu_wait = r4k_wait; |
| 204 | if (read_c0_config7() & MIPS_CONF7_WII) |
| 205 | cpu_wait = r4k_wait_irqoff; |
| 206 | break; |
| 207 | |
| 208 | case CPU_74K: |
| 209 | cpu_wait = r4k_wait; |
| 210 | if ((c->processor_id & 0xff) >= PRID_REV_ENCODE_332(2, 1, 0)) |
| 211 | cpu_wait = r4k_wait_irqoff; |
| 212 | break; |
| 213 | |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 214 | case CPU_TX49XX: |
| 215 | cpu_wait = r4k_wait_irqoff; |
Atsushi Nemoto | 60a6c37 | 2006-06-08 01:09:01 +0900 | [diff] [blame] | 216 | break; |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 217 | case CPU_ALCHEMY: |
Manuel Lauss | 0c694de | 2008-12-21 09:26:23 +0100 | [diff] [blame] | 218 | cpu_wait = au1k_wait; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 219 | break; |
Ralf Baechle | c8eae71 | 2007-06-12 13:04:09 +0100 | [diff] [blame] | 220 | case CPU_20KC: |
| 221 | /* |
| 222 | * WAIT on Rev1.0 has E1, E2, E3 and E16. |
| 223 | * WAIT on Rev2.0 and Rev3.0 has E16. |
| 224 | * Rev3.1 WAIT is nop, why bother |
| 225 | */ |
| 226 | if ((c->processor_id & 0xff) <= 0x64) |
| 227 | break; |
| 228 | |
Ralf Baechle | 50da469 | 2007-09-14 19:08:43 +0100 | [diff] [blame] | 229 | /* |
| 230 | * Another rev is incremeting c0_count at a reduced clock |
| 231 | * rate while in WAIT mode. So we basically have the choice |
| 232 | * between using the cp0 timer as clocksource or avoiding |
| 233 | * the WAIT instruction. Until more details are known, |
| 234 | * disable the use of WAIT for 20Kc entirely. |
| 235 | cpu_wait = r4k_wait; |
| 236 | */ |
Ralf Baechle | c8eae71 | 2007-06-12 13:04:09 +0100 | [diff] [blame] | 237 | break; |
Ralf Baechle | 441ee34 | 2006-06-02 11:48:11 +0100 | [diff] [blame] | 238 | case CPU_RM9000: |
Ralf Baechle | c237923 | 2006-11-30 01:14:44 +0000 | [diff] [blame] | 239 | if ((c->processor_id & 0x00ff) >= 0x40) |
Ralf Baechle | 441ee34 | 2006-06-02 11:48:11 +0100 | [diff] [blame] | 240 | cpu_wait = r4k_wait; |
Ralf Baechle | 441ee34 | 2006-06-02 11:48:11 +0100 | [diff] [blame] | 241 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 242 | default: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 243 | break; |
| 244 | } |
| 245 | } |
| 246 | |
Marc St-Jean | 9267a30 | 2007-06-14 15:55:31 -0600 | [diff] [blame] | 247 | static inline void check_errata(void) |
| 248 | { |
| 249 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 250 | |
| 251 | switch (c->cputype) { |
| 252 | case CPU_34K: |
| 253 | /* |
| 254 | * Erratum "RPS May Cause Incorrect Instruction Execution" |
| 255 | * This code only handles VPE0, any SMP/SMTC/RTOS code |
| 256 | * making use of VPE1 will be responsable for that VPE. |
| 257 | */ |
| 258 | if ((c->processor_id & PRID_REV_MASK) <= PRID_REV_34K_V1_0_2) |
| 259 | write_c0_config7(read_c0_config7() | MIPS_CONF7_RPS); |
| 260 | break; |
| 261 | default: |
| 262 | break; |
| 263 | } |
| 264 | } |
| 265 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 266 | void __init check_bugs32(void) |
| 267 | { |
Marc St-Jean | 9267a30 | 2007-06-14 15:55:31 -0600 | [diff] [blame] | 268 | check_errata(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 269 | } |
| 270 | |
| 271 | /* |
| 272 | * Probe whether cpu has config register by trying to play with |
| 273 | * alternate cache bit and see whether it matters. |
| 274 | * It's used by cpu_probe to distinguish between R3000A and R3081. |
| 275 | */ |
| 276 | static inline int cpu_has_confreg(void) |
| 277 | { |
| 278 | #ifdef CONFIG_CPU_R3000 |
| 279 | extern unsigned long r3k_cache_size(unsigned long); |
| 280 | unsigned long size1, size2; |
| 281 | unsigned long cfg = read_c0_conf(); |
| 282 | |
| 283 | size1 = r3k_cache_size(ST0_ISC); |
| 284 | write_c0_conf(cfg ^ R30XX_CONF_AC); |
| 285 | size2 = r3k_cache_size(ST0_ISC); |
| 286 | write_c0_conf(cfg); |
| 287 | return size1 != size2; |
| 288 | #else |
| 289 | return 0; |
| 290 | #endif |
| 291 | } |
| 292 | |
Robert Millan | c094c99 | 2011-04-18 11:37:55 -0700 | [diff] [blame] | 293 | static inline void set_elf_platform(int cpu, const char *plat) |
| 294 | { |
| 295 | if (cpu == 0) |
| 296 | __elf_platform = plat; |
| 297 | } |
| 298 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 299 | /* |
| 300 | * Get the FPU Implementation/Revision. |
| 301 | */ |
| 302 | static inline unsigned long cpu_get_fpu_id(void) |
| 303 | { |
| 304 | unsigned long tmp, fpu_id; |
| 305 | |
| 306 | tmp = read_c0_status(); |
| 307 | __enable_fpu(); |
| 308 | fpu_id = read_32bit_cp1_register(CP1_REVISION); |
| 309 | write_c0_status(tmp); |
| 310 | return fpu_id; |
| 311 | } |
| 312 | |
| 313 | /* |
| 314 | * Check the CPU has an FPU the official way. |
| 315 | */ |
| 316 | static inline int __cpu_has_fpu(void) |
| 317 | { |
| 318 | return ((cpu_get_fpu_id() & 0xff00) != FPIR_IMP_NONE); |
| 319 | } |
| 320 | |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 321 | static inline void cpu_probe_vmbits(struct cpuinfo_mips *c) |
| 322 | { |
| 323 | #ifdef __NEED_VMBITS_PROBE |
David Daney | 5b7efa8 | 2010-02-08 12:27:00 -0800 | [diff] [blame] | 324 | write_c0_entryhi(0x3fffffffffffe000ULL); |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 325 | back_to_back_c0_hazard(); |
David Daney | 5b7efa8 | 2010-02-08 12:27:00 -0800 | [diff] [blame] | 326 | c->vmbits = fls64(read_c0_entryhi() & 0x3fffffffffffe000ULL); |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 327 | #endif |
| 328 | } |
| 329 | |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 330 | #define R4K_OPTS (MIPS_CPU_TLB | MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE \ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 331 | | MIPS_CPU_COUNTER) |
| 332 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 333 | static inline void cpu_probe_legacy(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 334 | { |
| 335 | switch (c->processor_id & 0xff00) { |
| 336 | case PRID_IMP_R2000: |
| 337 | c->cputype = CPU_R2000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 338 | __cpu_name[cpu] = "R2000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 339 | c->isa_level = MIPS_CPU_ISA_I; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 340 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
| 341 | MIPS_CPU_NOFPUEX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 342 | if (__cpu_has_fpu()) |
| 343 | c->options |= MIPS_CPU_FPU; |
| 344 | c->tlbsize = 64; |
| 345 | break; |
| 346 | case PRID_IMP_R3000: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 347 | if ((c->processor_id & 0xff) == PRID_REV_R3000A) { |
| 348 | if (cpu_has_confreg()) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 349 | c->cputype = CPU_R3081E; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 350 | __cpu_name[cpu] = "R3081"; |
| 351 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 352 | c->cputype = CPU_R3000A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 353 | __cpu_name[cpu] = "R3000A"; |
| 354 | } |
| 355 | break; |
| 356 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 357 | c->cputype = CPU_R3000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 358 | __cpu_name[cpu] = "R3000"; |
| 359 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 360 | c->isa_level = MIPS_CPU_ISA_I; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 361 | c->options = MIPS_CPU_TLB | MIPS_CPU_3K_CACHE | |
| 362 | MIPS_CPU_NOFPUEX; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 363 | if (__cpu_has_fpu()) |
| 364 | c->options |= MIPS_CPU_FPU; |
| 365 | c->tlbsize = 64; |
| 366 | break; |
| 367 | case PRID_IMP_R4000: |
| 368 | if (read_c0_config() & CONF_SC) { |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 369 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 370 | c->cputype = CPU_R4400PC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 371 | __cpu_name[cpu] = "R4400PC"; |
| 372 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 373 | c->cputype = CPU_R4000PC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 374 | __cpu_name[cpu] = "R4000PC"; |
| 375 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 376 | } else { |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 377 | if ((c->processor_id & 0xff) >= PRID_REV_R4400) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 378 | c->cputype = CPU_R4400SC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 379 | __cpu_name[cpu] = "R4400SC"; |
| 380 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 381 | c->cputype = CPU_R4000SC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 382 | __cpu_name[cpu] = "R4000SC"; |
| 383 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 384 | } |
| 385 | |
| 386 | c->isa_level = MIPS_CPU_ISA_III; |
| 387 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 388 | MIPS_CPU_WATCH | MIPS_CPU_VCE | |
| 389 | MIPS_CPU_LLSC; |
| 390 | c->tlbsize = 48; |
| 391 | break; |
| 392 | case PRID_IMP_VR41XX: |
| 393 | switch (c->processor_id & 0xf0) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 394 | case PRID_REV_VR4111: |
| 395 | c->cputype = CPU_VR4111; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 396 | __cpu_name[cpu] = "NEC VR4111"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 397 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 398 | case PRID_REV_VR4121: |
| 399 | c->cputype = CPU_VR4121; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 400 | __cpu_name[cpu] = "NEC VR4121"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 401 | break; |
| 402 | case PRID_REV_VR4122: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 403 | if ((c->processor_id & 0xf) < 0x3) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 404 | c->cputype = CPU_VR4122; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 405 | __cpu_name[cpu] = "NEC VR4122"; |
| 406 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 407 | c->cputype = CPU_VR4181A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 408 | __cpu_name[cpu] = "NEC VR4181A"; |
| 409 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 410 | break; |
| 411 | case PRID_REV_VR4130: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 412 | if ((c->processor_id & 0xf) < 0x4) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | c->cputype = CPU_VR4131; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 414 | __cpu_name[cpu] = "NEC VR4131"; |
| 415 | } else { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 416 | c->cputype = CPU_VR4133; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 417 | __cpu_name[cpu] = "NEC VR4133"; |
| 418 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 419 | break; |
| 420 | default: |
| 421 | printk(KERN_INFO "Unexpected CPU of NEC VR4100 series\n"); |
| 422 | c->cputype = CPU_VR41XX; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 423 | __cpu_name[cpu] = "NEC Vr41xx"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 424 | break; |
| 425 | } |
| 426 | c->isa_level = MIPS_CPU_ISA_III; |
| 427 | c->options = R4K_OPTS; |
| 428 | c->tlbsize = 32; |
| 429 | break; |
| 430 | case PRID_IMP_R4300: |
| 431 | c->cputype = CPU_R4300; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 432 | __cpu_name[cpu] = "R4300"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 433 | c->isa_level = MIPS_CPU_ISA_III; |
| 434 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 435 | MIPS_CPU_LLSC; |
| 436 | c->tlbsize = 32; |
| 437 | break; |
| 438 | case PRID_IMP_R4600: |
| 439 | c->cputype = CPU_R4600; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 440 | __cpu_name[cpu] = "R4600"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 441 | c->isa_level = MIPS_CPU_ISA_III; |
Thiemo Seufer | 075e750 | 2005-07-27 21:48:12 +0000 | [diff] [blame] | 442 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 443 | MIPS_CPU_LLSC; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 444 | c->tlbsize = 48; |
| 445 | break; |
| 446 | #if 0 |
| 447 | case PRID_IMP_R4650: |
| 448 | /* |
| 449 | * This processor doesn't have an MMU, so it's not |
| 450 | * "real easy" to run Linux on it. It is left purely |
| 451 | * for documentation. Commented out because it shares |
| 452 | * it's c0_prid id number with the TX3900. |
| 453 | */ |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 454 | c->cputype = CPU_R4650; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 455 | __cpu_name[cpu] = "R4650"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 456 | c->isa_level = MIPS_CPU_ISA_III; |
| 457 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_LLSC; |
| 458 | c->tlbsize = 48; |
| 459 | break; |
| 460 | #endif |
| 461 | case PRID_IMP_TX39: |
| 462 | c->isa_level = MIPS_CPU_ISA_I; |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 463 | c->options = MIPS_CPU_TLB | MIPS_CPU_TX39_CACHE; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 464 | |
| 465 | if ((c->processor_id & 0xf0) == (PRID_REV_TX3927 & 0xf0)) { |
| 466 | c->cputype = CPU_TX3927; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 467 | __cpu_name[cpu] = "TX3927"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 468 | c->tlbsize = 64; |
| 469 | } else { |
| 470 | switch (c->processor_id & 0xff) { |
| 471 | case PRID_REV_TX3912: |
| 472 | c->cputype = CPU_TX3912; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 473 | __cpu_name[cpu] = "TX3912"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 474 | c->tlbsize = 32; |
| 475 | break; |
| 476 | case PRID_REV_TX3922: |
| 477 | c->cputype = CPU_TX3922; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 478 | __cpu_name[cpu] = "TX3922"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 479 | c->tlbsize = 64; |
| 480 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 481 | } |
| 482 | } |
| 483 | break; |
| 484 | case PRID_IMP_R4700: |
| 485 | c->cputype = CPU_R4700; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 486 | __cpu_name[cpu] = "R4700"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 487 | c->isa_level = MIPS_CPU_ISA_III; |
| 488 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 489 | MIPS_CPU_LLSC; |
| 490 | c->tlbsize = 48; |
| 491 | break; |
| 492 | case PRID_IMP_TX49: |
| 493 | c->cputype = CPU_TX49XX; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 494 | __cpu_name[cpu] = "R49XX"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 495 | c->isa_level = MIPS_CPU_ISA_III; |
| 496 | c->options = R4K_OPTS | MIPS_CPU_LLSC; |
| 497 | if (!(c->processor_id & 0x08)) |
| 498 | c->options |= MIPS_CPU_FPU | MIPS_CPU_32FPR; |
| 499 | c->tlbsize = 48; |
| 500 | break; |
| 501 | case PRID_IMP_R5000: |
| 502 | c->cputype = CPU_R5000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 503 | __cpu_name[cpu] = "R5000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 504 | c->isa_level = MIPS_CPU_ISA_IV; |
| 505 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 506 | MIPS_CPU_LLSC; |
| 507 | c->tlbsize = 48; |
| 508 | break; |
| 509 | case PRID_IMP_R5432: |
| 510 | c->cputype = CPU_R5432; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 511 | __cpu_name[cpu] = "R5432"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 512 | c->isa_level = MIPS_CPU_ISA_IV; |
| 513 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 514 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
| 515 | c->tlbsize = 48; |
| 516 | break; |
| 517 | case PRID_IMP_R5500: |
| 518 | c->cputype = CPU_R5500; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 519 | __cpu_name[cpu] = "R5500"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 520 | c->isa_level = MIPS_CPU_ISA_IV; |
| 521 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 522 | MIPS_CPU_WATCH | MIPS_CPU_LLSC; |
| 523 | c->tlbsize = 48; |
| 524 | break; |
| 525 | case PRID_IMP_NEVADA: |
| 526 | c->cputype = CPU_NEVADA; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 527 | __cpu_name[cpu] = "Nevada"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 528 | c->isa_level = MIPS_CPU_ISA_IV; |
| 529 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 530 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC; |
| 531 | c->tlbsize = 48; |
| 532 | break; |
| 533 | case PRID_IMP_R6000: |
| 534 | c->cputype = CPU_R6000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 535 | __cpu_name[cpu] = "R6000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 536 | c->isa_level = MIPS_CPU_ISA_II; |
| 537 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
| 538 | MIPS_CPU_LLSC; |
| 539 | c->tlbsize = 32; |
| 540 | break; |
| 541 | case PRID_IMP_R6000A: |
| 542 | c->cputype = CPU_R6000A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 543 | __cpu_name[cpu] = "R6000A"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 544 | c->isa_level = MIPS_CPU_ISA_II; |
| 545 | c->options = MIPS_CPU_TLB | MIPS_CPU_FPU | |
| 546 | MIPS_CPU_LLSC; |
| 547 | c->tlbsize = 32; |
| 548 | break; |
| 549 | case PRID_IMP_RM7000: |
| 550 | c->cputype = CPU_RM7000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 551 | __cpu_name[cpu] = "RM7000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 552 | c->isa_level = MIPS_CPU_ISA_IV; |
| 553 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 554 | MIPS_CPU_LLSC; |
| 555 | /* |
| 556 | * Undocumented RM7000: Bit 29 in the info register of |
| 557 | * the RM7000 v2.0 indicates if the TLB has 48 or 64 |
| 558 | * entries. |
| 559 | * |
| 560 | * 29 1 => 64 entry JTLB |
| 561 | * 0 => 48 entry JTLB |
| 562 | */ |
| 563 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; |
| 564 | break; |
| 565 | case PRID_IMP_RM9000: |
| 566 | c->cputype = CPU_RM9000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 567 | __cpu_name[cpu] = "RM9000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 568 | c->isa_level = MIPS_CPU_ISA_IV; |
| 569 | c->options = R4K_OPTS | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 570 | MIPS_CPU_LLSC; |
| 571 | /* |
| 572 | * Bit 29 in the info register of the RM9000 |
| 573 | * indicates if the TLB has 48 or 64 entries. |
| 574 | * |
| 575 | * 29 1 => 64 entry JTLB |
| 576 | * 0 => 48 entry JTLB |
| 577 | */ |
| 578 | c->tlbsize = (read_c0_info() & (1 << 29)) ? 64 : 48; |
| 579 | break; |
| 580 | case PRID_IMP_R8000: |
| 581 | c->cputype = CPU_R8000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 582 | __cpu_name[cpu] = "RM8000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 583 | c->isa_level = MIPS_CPU_ISA_IV; |
| 584 | c->options = MIPS_CPU_TLB | MIPS_CPU_4KEX | |
| 585 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 586 | MIPS_CPU_LLSC; |
| 587 | c->tlbsize = 384; /* has weird TLB: 3-way x 128 */ |
| 588 | break; |
| 589 | case PRID_IMP_R10000: |
| 590 | c->cputype = CPU_R10000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 591 | __cpu_name[cpu] = "R10000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 592 | c->isa_level = MIPS_CPU_ISA_IV; |
Ralf Baechle | 8b36612 | 2005-11-22 17:53:59 +0000 | [diff] [blame] | 593 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 594 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 595 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
| 596 | MIPS_CPU_LLSC; |
| 597 | c->tlbsize = 64; |
| 598 | break; |
| 599 | case PRID_IMP_R12000: |
| 600 | c->cputype = CPU_R12000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 601 | __cpu_name[cpu] = "R12000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 602 | c->isa_level = MIPS_CPU_ISA_IV; |
Ralf Baechle | 8b36612 | 2005-11-22 17:53:59 +0000 | [diff] [blame] | 603 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 604 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 605 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
| 606 | MIPS_CPU_LLSC; |
| 607 | c->tlbsize = 64; |
| 608 | break; |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 609 | case PRID_IMP_R14000: |
| 610 | c->cputype = CPU_R14000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 611 | __cpu_name[cpu] = "R14000"; |
Kumba | 44d921b | 2006-05-16 22:23:59 -0400 | [diff] [blame] | 612 | c->isa_level = MIPS_CPU_ISA_IV; |
| 613 | c->options = MIPS_CPU_TLB | MIPS_CPU_4K_CACHE | MIPS_CPU_4KEX | |
| 614 | MIPS_CPU_FPU | MIPS_CPU_32FPR | |
| 615 | MIPS_CPU_COUNTER | MIPS_CPU_WATCH | |
| 616 | MIPS_CPU_LLSC; |
| 617 | c->tlbsize = 64; |
| 618 | break; |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 619 | case PRID_IMP_LOONGSON2: |
| 620 | c->cputype = CPU_LOONGSON2; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 621 | __cpu_name[cpu] = "ICT Loongson-2"; |
Robert Millan | 5aac1e8 | 2011-04-16 11:29:29 -0700 | [diff] [blame] | 622 | |
| 623 | switch (c->processor_id & PRID_REV_MASK) { |
| 624 | case PRID_REV_LOONGSON2E: |
| 625 | set_elf_platform(cpu, "loongson2e"); |
| 626 | break; |
| 627 | case PRID_REV_LOONGSON2F: |
| 628 | set_elf_platform(cpu, "loongson2f"); |
| 629 | break; |
| 630 | } |
| 631 | |
Fuxin Zhang | 2a21c73 | 2007-06-06 14:52:43 +0800 | [diff] [blame] | 632 | c->isa_level = MIPS_CPU_ISA_III; |
| 633 | c->options = R4K_OPTS | |
| 634 | MIPS_CPU_FPU | MIPS_CPU_LLSC | |
| 635 | MIPS_CPU_32FPR; |
| 636 | c->tlbsize = 64; |
| 637 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 638 | } |
| 639 | } |
| 640 | |
Ralf Baechle | 234fcd1 | 2008-03-08 09:56:28 +0000 | [diff] [blame] | 641 | static char unknown_isa[] __cpuinitdata = KERN_ERR \ |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 642 | "Unsupported ISA type, c0.config0: %d."; |
| 643 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 644 | static inline unsigned int decode_config0(struct cpuinfo_mips *c) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 645 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 646 | unsigned int config0; |
| 647 | int isa; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 648 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 649 | config0 = read_c0_config(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 650 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 651 | if (((config0 & MIPS_CONF_MT) >> 7) == 1) |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 652 | c->options |= MIPS_CPU_TLB; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 653 | isa = (config0 & MIPS_CONF_AT) >> 13; |
| 654 | switch (isa) { |
| 655 | case 0: |
Thiemo Seufer | 3a01c49 | 2006-07-03 13:30:01 +0100 | [diff] [blame] | 656 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 657 | case 0: |
| 658 | c->isa_level = MIPS_CPU_ISA_M32R1; |
| 659 | break; |
| 660 | case 1: |
| 661 | c->isa_level = MIPS_CPU_ISA_M32R2; |
| 662 | break; |
| 663 | default: |
| 664 | goto unknown; |
| 665 | } |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 666 | break; |
| 667 | case 2: |
Thiemo Seufer | 3a01c49 | 2006-07-03 13:30:01 +0100 | [diff] [blame] | 668 | switch ((config0 & MIPS_CONF_AR) >> 10) { |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 669 | case 0: |
| 670 | c->isa_level = MIPS_CPU_ISA_M64R1; |
| 671 | break; |
| 672 | case 1: |
| 673 | c->isa_level = MIPS_CPU_ISA_M64R2; |
| 674 | break; |
| 675 | default: |
| 676 | goto unknown; |
| 677 | } |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 678 | break; |
| 679 | default: |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 680 | goto unknown; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 681 | } |
| 682 | |
| 683 | return config0 & MIPS_CONF_M; |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 684 | |
| 685 | unknown: |
| 686 | panic(unknown_isa, config0); |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 687 | } |
| 688 | |
| 689 | static inline unsigned int decode_config1(struct cpuinfo_mips *c) |
| 690 | { |
| 691 | unsigned int config1; |
| 692 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 693 | config1 = read_c0_config1(); |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 694 | |
| 695 | if (config1 & MIPS_CONF1_MD) |
| 696 | c->ases |= MIPS_ASE_MDMX; |
| 697 | if (config1 & MIPS_CONF1_WR) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 698 | c->options |= MIPS_CPU_WATCH; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 699 | if (config1 & MIPS_CONF1_CA) |
| 700 | c->ases |= MIPS_ASE_MIPS16; |
| 701 | if (config1 & MIPS_CONF1_EP) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 702 | c->options |= MIPS_CPU_EJTAG; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 703 | if (config1 & MIPS_CONF1_FP) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 704 | c->options |= MIPS_CPU_FPU; |
| 705 | c->options |= MIPS_CPU_32FPR; |
| 706 | } |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 707 | if (cpu_has_tlb) |
| 708 | c->tlbsize = ((config1 & MIPS_CONF1_TLBS) >> 25) + 1; |
| 709 | |
| 710 | return config1 & MIPS_CONF_M; |
| 711 | } |
| 712 | |
| 713 | static inline unsigned int decode_config2(struct cpuinfo_mips *c) |
| 714 | { |
| 715 | unsigned int config2; |
| 716 | |
| 717 | config2 = read_c0_config2(); |
| 718 | |
| 719 | if (config2 & MIPS_CONF2_SL) |
| 720 | c->scache.flags &= ~MIPS_CACHE_NOT_PRESENT; |
| 721 | |
| 722 | return config2 & MIPS_CONF_M; |
| 723 | } |
| 724 | |
| 725 | static inline unsigned int decode_config3(struct cpuinfo_mips *c) |
| 726 | { |
| 727 | unsigned int config3; |
| 728 | |
| 729 | config3 = read_c0_config3(); |
| 730 | |
| 731 | if (config3 & MIPS_CONF3_SM) |
| 732 | c->ases |= MIPS_ASE_SMARTMIPS; |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 733 | if (config3 & MIPS_CONF3_DSP) |
| 734 | c->ases |= MIPS_ASE_DSP; |
Ralf Baechle | 8f40611 | 2005-07-14 07:34:18 +0000 | [diff] [blame] | 735 | if (config3 & MIPS_CONF3_VINT) |
| 736 | c->options |= MIPS_CPU_VINT; |
| 737 | if (config3 & MIPS_CONF3_VEIC) |
| 738 | c->options |= MIPS_CPU_VEIC; |
| 739 | if (config3 & MIPS_CONF3_MT) |
Ralf Baechle | e0daad4 | 2007-02-05 00:10:11 +0000 | [diff] [blame] | 740 | c->ases |= MIPS_ASE_MIPSMT; |
Ralf Baechle | a369202 | 2007-07-10 17:33:02 +0100 | [diff] [blame] | 741 | if (config3 & MIPS_CONF3_ULRI) |
| 742 | c->options |= MIPS_CPU_ULRI; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 743 | |
| 744 | return config3 & MIPS_CONF_M; |
| 745 | } |
| 746 | |
David Daney | 1b362e3 | 2010-01-22 14:41:15 -0800 | [diff] [blame] | 747 | static inline unsigned int decode_config4(struct cpuinfo_mips *c) |
| 748 | { |
| 749 | unsigned int config4; |
| 750 | |
| 751 | config4 = read_c0_config4(); |
| 752 | |
| 753 | if ((config4 & MIPS_CONF4_MMUEXTDEF) == MIPS_CONF4_MMUEXTDEF_MMUSIZEEXT |
| 754 | && cpu_has_tlb) |
| 755 | c->tlbsize += (config4 & MIPS_CONF4_MMUSIZEEXT) * 0x40; |
| 756 | |
David Daney | e77c32f | 2010-12-21 14:19:09 -0800 | [diff] [blame] | 757 | c->kscratch_mask = (config4 >> 16) & 0xff; |
| 758 | |
David Daney | 1b362e3 | 2010-01-22 14:41:15 -0800 | [diff] [blame] | 759 | return config4 & MIPS_CONF_M; |
| 760 | } |
| 761 | |
Ralf Baechle | 234fcd1 | 2008-03-08 09:56:28 +0000 | [diff] [blame] | 762 | static void __cpuinit decode_configs(struct cpuinfo_mips *c) |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 763 | { |
Ralf Baechle | 558ce12 | 2008-10-29 12:33:34 +0000 | [diff] [blame] | 764 | int ok; |
| 765 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 766 | /* MIPS32 or MIPS64 compliant CPU. */ |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 767 | c->options = MIPS_CPU_4KEX | MIPS_CPU_4K_CACHE | MIPS_CPU_COUNTER | |
| 768 | MIPS_CPU_DIVEC | MIPS_CPU_LLSC | MIPS_CPU_MCHECK; |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 769 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 770 | c->scache.flags = MIPS_CACHE_NOT_PRESENT; |
| 771 | |
Ralf Baechle | 558ce12 | 2008-10-29 12:33:34 +0000 | [diff] [blame] | 772 | ok = decode_config0(c); /* Read Config registers. */ |
| 773 | BUG_ON(!ok); /* Arch spec violation! */ |
| 774 | if (ok) |
| 775 | ok = decode_config1(c); |
| 776 | if (ok) |
| 777 | ok = decode_config2(c); |
| 778 | if (ok) |
| 779 | ok = decode_config3(c); |
David Daney | 1b362e3 | 2010-01-22 14:41:15 -0800 | [diff] [blame] | 780 | if (ok) |
| 781 | ok = decode_config4(c); |
Ralf Baechle | 558ce12 | 2008-10-29 12:33:34 +0000 | [diff] [blame] | 782 | |
| 783 | mips_probe_watch_registers(c); |
David Daney | 0c2f455 | 2010-07-26 14:29:37 -0700 | [diff] [blame] | 784 | |
| 785 | if (cpu_has_mips_r2) |
| 786 | c->core = read_c0_ebase() & 0x3ff; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 787 | } |
| 788 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 789 | static inline void cpu_probe_mips(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 790 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 791 | decode_configs(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 792 | switch (c->processor_id & 0xff00) { |
| 793 | case PRID_IMP_4KC: |
| 794 | c->cputype = CPU_4KC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 795 | __cpu_name[cpu] = "MIPS 4Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 796 | break; |
| 797 | case PRID_IMP_4KEC: |
Ralf Baechle | 2b07bd0 | 2005-04-08 20:36:05 +0000 | [diff] [blame] | 798 | case PRID_IMP_4KECR2: |
| 799 | c->cputype = CPU_4KEC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 800 | __cpu_name[cpu] = "MIPS 4KEc"; |
Ralf Baechle | 2b07bd0 | 2005-04-08 20:36:05 +0000 | [diff] [blame] | 801 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 802 | case PRID_IMP_4KSC: |
Ralf Baechle | 8afcb5d | 2005-10-04 15:01:26 +0100 | [diff] [blame] | 803 | case PRID_IMP_4KSD: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 804 | c->cputype = CPU_4KSC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 805 | __cpu_name[cpu] = "MIPS 4KSc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 806 | break; |
| 807 | case PRID_IMP_5KC: |
| 808 | c->cputype = CPU_5KC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 809 | __cpu_name[cpu] = "MIPS 5Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 810 | break; |
| 811 | case PRID_IMP_20KC: |
| 812 | c->cputype = CPU_20KC; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 813 | __cpu_name[cpu] = "MIPS 20Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 814 | break; |
| 815 | case PRID_IMP_24K: |
Ralf Baechle | e50c0a8 | 2005-05-31 11:49:19 +0000 | [diff] [blame] | 816 | case PRID_IMP_24KE: |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 817 | c->cputype = CPU_24K; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 818 | __cpu_name[cpu] = "MIPS 24Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 819 | break; |
| 820 | case PRID_IMP_25KF: |
| 821 | c->cputype = CPU_25KF; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 822 | __cpu_name[cpu] = "MIPS 25Kc"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 823 | break; |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 824 | case PRID_IMP_34K: |
| 825 | c->cputype = CPU_34K; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 826 | __cpu_name[cpu] = "MIPS 34Kc"; |
Ralf Baechle | bbc7f22 | 2005-07-12 16:12:05 +0000 | [diff] [blame] | 827 | break; |
Chris Dearman | c620953 | 2006-05-02 14:08:46 +0100 | [diff] [blame] | 828 | case PRID_IMP_74K: |
| 829 | c->cputype = CPU_74K; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 830 | __cpu_name[cpu] = "MIPS 74Kc"; |
Chris Dearman | c620953 | 2006-05-02 14:08:46 +0100 | [diff] [blame] | 831 | break; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 832 | case PRID_IMP_1004K: |
| 833 | c->cputype = CPU_1004K; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 834 | __cpu_name[cpu] = "MIPS 1004Kc"; |
Ralf Baechle | 39b8d52 | 2008-04-28 17:14:26 +0100 | [diff] [blame] | 835 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 836 | } |
Chris Dearman | 0b6d497 | 2007-09-13 12:32:02 +0100 | [diff] [blame] | 837 | |
| 838 | spram_config(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 839 | } |
| 840 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 841 | static inline void cpu_probe_alchemy(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 842 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 843 | decode_configs(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 844 | switch (c->processor_id & 0xff00) { |
| 845 | case PRID_IMP_AU1_REV1: |
| 846 | case PRID_IMP_AU1_REV2: |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 847 | c->cputype = CPU_ALCHEMY; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 848 | switch ((c->processor_id >> 24) & 0xff) { |
| 849 | case 0: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 850 | __cpu_name[cpu] = "Au1000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 851 | break; |
| 852 | case 1: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 853 | __cpu_name[cpu] = "Au1500"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 854 | break; |
| 855 | case 2: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 856 | __cpu_name[cpu] = "Au1100"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 857 | break; |
| 858 | case 3: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 859 | __cpu_name[cpu] = "Au1550"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 860 | break; |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 861 | case 4: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 862 | __cpu_name[cpu] = "Au1200"; |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 863 | if ((c->processor_id & 0xff) == 2) |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 864 | __cpu_name[cpu] = "Au1250"; |
Manuel Lauss | 237cfee | 2007-12-06 09:07:55 +0100 | [diff] [blame] | 865 | break; |
| 866 | case 5: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 867 | __cpu_name[cpu] = "Au1210"; |
Pete Popov | e3ad1c2 | 2005-03-01 06:33:16 +0000 | [diff] [blame] | 868 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 869 | default: |
Manuel Lauss | 270717a | 2009-03-25 17:49:28 +0100 | [diff] [blame] | 870 | __cpu_name[cpu] = "Au1xxx"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 871 | break; |
| 872 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 873 | break; |
| 874 | } |
| 875 | } |
| 876 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 877 | static inline void cpu_probe_sibyte(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 878 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 879 | decode_configs(c); |
Ralf Baechle | 02cf211 | 2005-10-01 13:06:32 +0100 | [diff] [blame] | 880 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 881 | switch (c->processor_id & 0xff00) { |
| 882 | case PRID_IMP_SB1: |
| 883 | c->cputype = CPU_SB1; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 884 | __cpu_name[cpu] = "SiByte SB1"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 885 | /* FPU in pass1 is known to have issues. */ |
Ralf Baechle | aa32374 | 2006-05-29 00:02:12 +0100 | [diff] [blame] | 886 | if ((c->processor_id & 0xff) < 0x02) |
Ralf Baechle | 010b853 | 2006-01-29 18:42:08 +0000 | [diff] [blame] | 887 | c->options &= ~(MIPS_CPU_FPU | MIPS_CPU_32FPR); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 888 | break; |
Andrew Isaacson | 93ce2f52 | 2005-10-19 23:56:20 -0700 | [diff] [blame] | 889 | case PRID_IMP_SB1A: |
| 890 | c->cputype = CPU_SB1A; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 891 | __cpu_name[cpu] = "SiByte SB1A"; |
Andrew Isaacson | 93ce2f52 | 2005-10-19 23:56:20 -0700 | [diff] [blame] | 892 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 893 | } |
| 894 | } |
| 895 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 896 | static inline void cpu_probe_sandcraft(struct cpuinfo_mips *c, unsigned int cpu) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 897 | { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 898 | decode_configs(c); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 899 | switch (c->processor_id & 0xff00) { |
| 900 | case PRID_IMP_SR71000: |
| 901 | c->cputype = CPU_SR71000; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 902 | __cpu_name[cpu] = "Sandcraft SR71000"; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 903 | c->scache.ways = 8; |
| 904 | c->tlbsize = 64; |
| 905 | break; |
| 906 | } |
| 907 | } |
| 908 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 909 | static inline void cpu_probe_nxp(struct cpuinfo_mips *c, unsigned int cpu) |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 910 | { |
| 911 | decode_configs(c); |
| 912 | switch (c->processor_id & 0xff00) { |
| 913 | case PRID_IMP_PR4450: |
| 914 | c->cputype = CPU_PR4450; |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 915 | __cpu_name[cpu] = "Philips PR4450"; |
Ralf Baechle | e7958bb | 2005-12-08 13:00:20 +0000 | [diff] [blame] | 916 | c->isa_level = MIPS_CPU_ISA_M32R1; |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 917 | break; |
Pete Popov | bdf21b1 | 2005-07-14 17:47:57 +0000 | [diff] [blame] | 918 | } |
| 919 | } |
| 920 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 921 | static inline void cpu_probe_broadcom(struct cpuinfo_mips *c, unsigned int cpu) |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 922 | { |
| 923 | decode_configs(c); |
| 924 | switch (c->processor_id & 0xff00) { |
Kevin Cernekee | 190fca3 | 2010-11-23 10:26:45 -0800 | [diff] [blame] | 925 | case PRID_IMP_BMIPS32_REV4: |
| 926 | case PRID_IMP_BMIPS32_REV8: |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 927 | c->cputype = CPU_BMIPS32; |
| 928 | __cpu_name[cpu] = "Broadcom BMIPS32"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 929 | set_elf_platform(cpu, "bmips32"); |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 930 | break; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 931 | case PRID_IMP_BMIPS3300: |
| 932 | case PRID_IMP_BMIPS3300_ALT: |
| 933 | case PRID_IMP_BMIPS3300_BUG: |
| 934 | c->cputype = CPU_BMIPS3300; |
| 935 | __cpu_name[cpu] = "Broadcom BMIPS3300"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 936 | set_elf_platform(cpu, "bmips3300"); |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 937 | break; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 938 | case PRID_IMP_BMIPS43XX: { |
| 939 | int rev = c->processor_id & 0xff; |
| 940 | |
| 941 | if (rev >= PRID_REV_BMIPS4380_LO && |
| 942 | rev <= PRID_REV_BMIPS4380_HI) { |
| 943 | c->cputype = CPU_BMIPS4380; |
| 944 | __cpu_name[cpu] = "Broadcom BMIPS4380"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 945 | set_elf_platform(cpu, "bmips4380"); |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 946 | } else { |
| 947 | c->cputype = CPU_BMIPS4350; |
| 948 | __cpu_name[cpu] = "Broadcom BMIPS4350"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 949 | set_elf_platform(cpu, "bmips4350"); |
Maxime Bizon | 0de663e | 2009-08-18 13:23:37 +0100 | [diff] [blame] | 950 | } |
| 951 | break; |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 952 | } |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 953 | case PRID_IMP_BMIPS5000: |
| 954 | c->cputype = CPU_BMIPS5000; |
| 955 | __cpu_name[cpu] = "Broadcom BMIPS5000"; |
Kevin Cernekee | 06785df | 2011-04-16 11:29:28 -0700 | [diff] [blame] | 956 | set_elf_platform(cpu, "bmips5000"); |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 957 | c->options |= MIPS_CPU_ULRI; |
| 958 | break; |
Kevin Cernekee | 602977b | 2010-10-16 14:22:30 -0700 | [diff] [blame] | 959 | } |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 960 | } |
| 961 | |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 962 | static inline void cpu_probe_cavium(struct cpuinfo_mips *c, unsigned int cpu) |
| 963 | { |
| 964 | decode_configs(c); |
| 965 | switch (c->processor_id & 0xff00) { |
| 966 | case PRID_IMP_CAVIUM_CN38XX: |
| 967 | case PRID_IMP_CAVIUM_CN31XX: |
| 968 | case PRID_IMP_CAVIUM_CN30XX: |
David Daney | 6f32946 | 2010-02-10 15:12:48 -0800 | [diff] [blame] | 969 | c->cputype = CPU_CAVIUM_OCTEON; |
| 970 | __cpu_name[cpu] = "Cavium Octeon"; |
| 971 | goto platform; |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 972 | case PRID_IMP_CAVIUM_CN58XX: |
| 973 | case PRID_IMP_CAVIUM_CN56XX: |
| 974 | case PRID_IMP_CAVIUM_CN50XX: |
| 975 | case PRID_IMP_CAVIUM_CN52XX: |
David Daney | 6f32946 | 2010-02-10 15:12:48 -0800 | [diff] [blame] | 976 | c->cputype = CPU_CAVIUM_OCTEON_PLUS; |
| 977 | __cpu_name[cpu] = "Cavium Octeon+"; |
| 978 | platform: |
Robert Millan | c094c99 | 2011-04-18 11:37:55 -0700 | [diff] [blame] | 979 | set_elf_platform(cpu, "octeon"); |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 980 | break; |
David Daney | a1431b6 | 2011-09-24 02:29:54 +0200 | [diff] [blame^] | 981 | case PRID_IMP_CAVIUM_CN61XX: |
David Daney | 0e56b38 | 2010-10-07 16:03:45 -0700 | [diff] [blame] | 982 | case PRID_IMP_CAVIUM_CN63XX: |
David Daney | a1431b6 | 2011-09-24 02:29:54 +0200 | [diff] [blame^] | 983 | case PRID_IMP_CAVIUM_CN66XX: |
| 984 | case PRID_IMP_CAVIUM_CN68XX: |
David Daney | 0e56b38 | 2010-10-07 16:03:45 -0700 | [diff] [blame] | 985 | c->cputype = CPU_CAVIUM_OCTEON2; |
| 986 | __cpu_name[cpu] = "Cavium Octeon II"; |
Robert Millan | c094c99 | 2011-04-18 11:37:55 -0700 | [diff] [blame] | 987 | set_elf_platform(cpu, "octeon2"); |
David Daney | 0e56b38 | 2010-10-07 16:03:45 -0700 | [diff] [blame] | 988 | break; |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 989 | default: |
| 990 | printk(KERN_INFO "Unknown Octeon chip!\n"); |
| 991 | c->cputype = CPU_UNKNOWN; |
| 992 | break; |
| 993 | } |
| 994 | } |
| 995 | |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 996 | static inline void cpu_probe_ingenic(struct cpuinfo_mips *c, unsigned int cpu) |
| 997 | { |
| 998 | decode_configs(c); |
| 999 | /* JZRISC does not implement the CP0 counter. */ |
| 1000 | c->options &= ~MIPS_CPU_COUNTER; |
| 1001 | switch (c->processor_id & 0xff00) { |
| 1002 | case PRID_IMP_JZRISC: |
| 1003 | c->cputype = CPU_JZRISC; |
| 1004 | __cpu_name[cpu] = "Ingenic JZRISC"; |
| 1005 | break; |
| 1006 | default: |
| 1007 | panic("Unknown Ingenic Processor ID!"); |
| 1008 | break; |
| 1009 | } |
| 1010 | } |
| 1011 | |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1012 | static inline void cpu_probe_netlogic(struct cpuinfo_mips *c, int cpu) |
| 1013 | { |
| 1014 | decode_configs(c); |
| 1015 | |
| 1016 | c->options = (MIPS_CPU_TLB | |
| 1017 | MIPS_CPU_4KEX | |
| 1018 | MIPS_CPU_COUNTER | |
| 1019 | MIPS_CPU_DIVEC | |
| 1020 | MIPS_CPU_WATCH | |
| 1021 | MIPS_CPU_EJTAG | |
| 1022 | MIPS_CPU_LLSC); |
| 1023 | |
| 1024 | switch (c->processor_id & 0xff00) { |
| 1025 | case PRID_IMP_NETLOGIC_XLR732: |
| 1026 | case PRID_IMP_NETLOGIC_XLR716: |
| 1027 | case PRID_IMP_NETLOGIC_XLR532: |
| 1028 | case PRID_IMP_NETLOGIC_XLR308: |
| 1029 | case PRID_IMP_NETLOGIC_XLR532C: |
| 1030 | case PRID_IMP_NETLOGIC_XLR516C: |
| 1031 | case PRID_IMP_NETLOGIC_XLR508C: |
| 1032 | case PRID_IMP_NETLOGIC_XLR308C: |
| 1033 | c->cputype = CPU_XLR; |
| 1034 | __cpu_name[cpu] = "Netlogic XLR"; |
| 1035 | break; |
| 1036 | |
| 1037 | case PRID_IMP_NETLOGIC_XLS608: |
| 1038 | case PRID_IMP_NETLOGIC_XLS408: |
| 1039 | case PRID_IMP_NETLOGIC_XLS404: |
| 1040 | case PRID_IMP_NETLOGIC_XLS208: |
| 1041 | case PRID_IMP_NETLOGIC_XLS204: |
| 1042 | case PRID_IMP_NETLOGIC_XLS108: |
| 1043 | case PRID_IMP_NETLOGIC_XLS104: |
| 1044 | case PRID_IMP_NETLOGIC_XLS616B: |
| 1045 | case PRID_IMP_NETLOGIC_XLS608B: |
| 1046 | case PRID_IMP_NETLOGIC_XLS416B: |
| 1047 | case PRID_IMP_NETLOGIC_XLS412B: |
| 1048 | case PRID_IMP_NETLOGIC_XLS408B: |
| 1049 | case PRID_IMP_NETLOGIC_XLS404B: |
| 1050 | c->cputype = CPU_XLR; |
| 1051 | __cpu_name[cpu] = "Netlogic XLS"; |
| 1052 | break; |
| 1053 | |
| 1054 | default: |
| 1055 | printk(KERN_INFO "Unknown Netlogic chip id [%02x]!\n", |
| 1056 | c->processor_id); |
| 1057 | c->cputype = CPU_XLR; |
| 1058 | break; |
| 1059 | } |
| 1060 | |
| 1061 | c->isa_level = MIPS_CPU_ISA_M64R1; |
| 1062 | c->tlbsize = ((read_c0_config1() >> 25) & 0x3f) + 1; |
| 1063 | } |
| 1064 | |
David Daney | 949e51b | 2010-10-14 11:32:33 -0700 | [diff] [blame] | 1065 | #ifdef CONFIG_64BIT |
| 1066 | /* For use by uaccess.h */ |
| 1067 | u64 __ua_limit; |
| 1068 | EXPORT_SYMBOL(__ua_limit); |
| 1069 | #endif |
| 1070 | |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1071 | const char *__cpu_name[NR_CPUS]; |
David Daney | 874fd3b | 2010-01-28 16:52:12 -0800 | [diff] [blame] | 1072 | const char *__elf_platform; |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1073 | |
Ralf Baechle | 234fcd1 | 2008-03-08 09:56:28 +0000 | [diff] [blame] | 1074 | __cpuinit void cpu_probe(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1075 | { |
| 1076 | struct cpuinfo_mips *c = ¤t_cpu_data; |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1077 | unsigned int cpu = smp_processor_id(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1078 | |
| 1079 | c->processor_id = PRID_IMP_UNKNOWN; |
| 1080 | c->fpu_id = FPIR_IMP_NONE; |
| 1081 | c->cputype = CPU_UNKNOWN; |
| 1082 | |
| 1083 | c->processor_id = read_c0_prid(); |
| 1084 | switch (c->processor_id & 0xff0000) { |
| 1085 | case PRID_COMP_LEGACY: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1086 | cpu_probe_legacy(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1087 | break; |
| 1088 | case PRID_COMP_MIPS: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1089 | cpu_probe_mips(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1090 | break; |
| 1091 | case PRID_COMP_ALCHEMY: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1092 | cpu_probe_alchemy(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1093 | break; |
| 1094 | case PRID_COMP_SIBYTE: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1095 | cpu_probe_sibyte(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1096 | break; |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1097 | case PRID_COMP_BROADCOM: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1098 | cpu_probe_broadcom(c, cpu); |
Aurelien Jarno | 1c0c13e | 2007-09-25 15:40:12 +0200 | [diff] [blame] | 1099 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1100 | case PRID_COMP_SANDCRAFT: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1101 | cpu_probe_sandcraft(c, cpu); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1102 | break; |
Daniel Laird | a92b058 | 2008-03-06 09:07:18 +0000 | [diff] [blame] | 1103 | case PRID_COMP_NXP: |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1104 | cpu_probe_nxp(c, cpu); |
Ralf Baechle | a3dddd5 | 2006-03-11 08:18:41 +0000 | [diff] [blame] | 1105 | break; |
David Daney | 0dd4781 | 2008-12-11 15:33:26 -0800 | [diff] [blame] | 1106 | case PRID_COMP_CAVIUM: |
| 1107 | cpu_probe_cavium(c, cpu); |
| 1108 | break; |
Lars-Peter Clausen | 83ccf69 | 2010-07-17 11:07:51 +0000 | [diff] [blame] | 1109 | case PRID_COMP_INGENIC: |
| 1110 | cpu_probe_ingenic(c, cpu); |
| 1111 | break; |
Jayachandran C | a7117c6 | 2011-05-11 12:04:58 +0530 | [diff] [blame] | 1112 | case PRID_COMP_NETLOGIC: |
| 1113 | cpu_probe_netlogic(c, cpu); |
| 1114 | break; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1115 | } |
Franck Bui-Huu | dec8b1c | 2007-10-08 16:11:51 +0200 | [diff] [blame] | 1116 | |
Ralf Baechle | cea7e2d | 2008-10-30 13:38:45 +0000 | [diff] [blame] | 1117 | BUG_ON(!__cpu_name[cpu]); |
| 1118 | BUG_ON(c->cputype == CPU_UNKNOWN); |
| 1119 | |
Franck Bui-Huu | dec8b1c | 2007-10-08 16:11:51 +0200 | [diff] [blame] | 1120 | /* |
| 1121 | * Platform code can force the cpu type to optimize code |
| 1122 | * generation. In that case be sure the cpu type is correctly |
| 1123 | * manually setup otherwise it could trigger some nasty bugs. |
| 1124 | */ |
| 1125 | BUG_ON(current_cpu_type() != c->cputype); |
| 1126 | |
Kevin Cernekee | 0103d23 | 2010-05-02 14:43:52 -0700 | [diff] [blame] | 1127 | if (mips_fpu_disabled) |
| 1128 | c->options &= ~MIPS_CPU_FPU; |
| 1129 | |
| 1130 | if (mips_dsp_disabled) |
| 1131 | c->ases &= ~MIPS_ASE_DSP; |
| 1132 | |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1133 | if (c->options & MIPS_CPU_FPU) { |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1134 | c->fpu_id = cpu_get_fpu_id(); |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1135 | |
Ralf Baechle | e7958bb | 2005-12-08 13:00:20 +0000 | [diff] [blame] | 1136 | if (c->isa_level == MIPS_CPU_ISA_M32R1 || |
Ralf Baechle | b4672d3 | 2005-12-08 14:04:24 +0000 | [diff] [blame] | 1137 | c->isa_level == MIPS_CPU_ISA_M32R2 || |
| 1138 | c->isa_level == MIPS_CPU_ISA_M64R1 || |
| 1139 | c->isa_level == MIPS_CPU_ISA_M64R2) { |
Ralf Baechle | 4194318 | 2005-05-05 16:45:59 +0000 | [diff] [blame] | 1140 | if (c->fpu_id & MIPS_FPIR_3D) |
| 1141 | c->ases |= MIPS_ASE_MIPS3D; |
| 1142 | } |
| 1143 | } |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1144 | |
Ralf Baechle | f6771db | 2007-11-08 18:02:29 +0000 | [diff] [blame] | 1145 | if (cpu_has_mips_r2) |
| 1146 | c->srsets = ((read_c0_srsctl() >> 26) & 0x0f) + 1; |
| 1147 | else |
| 1148 | c->srsets = 1; |
Guenter Roeck | 91dfc42 | 2010-02-02 08:52:20 -0800 | [diff] [blame] | 1149 | |
| 1150 | cpu_probe_vmbits(c); |
David Daney | 949e51b | 2010-10-14 11:32:33 -0700 | [diff] [blame] | 1151 | |
| 1152 | #ifdef CONFIG_64BIT |
| 1153 | if (cpu == 0) |
| 1154 | __ua_limit = ~((1ull << cpu_vmbits) - 1); |
| 1155 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1156 | } |
| 1157 | |
Ralf Baechle | 234fcd1 | 2008-03-08 09:56:28 +0000 | [diff] [blame] | 1158 | __cpuinit void cpu_report(void) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1159 | { |
| 1160 | struct cpuinfo_mips *c = ¤t_cpu_data; |
| 1161 | |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1162 | printk(KERN_INFO "CPU revision is: %08x (%s)\n", |
| 1163 | c->processor_id, cpu_name_string()); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1164 | if (c->options & MIPS_CPU_FPU) |
Ralf Baechle | 9966db25 | 2007-10-11 23:46:17 +0100 | [diff] [blame] | 1165 | printk(KERN_INFO "FPU revision is: %08x\n", c->fpu_id); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 1166 | } |