Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 1 | /* |
Michal Simek | 1e52980 | 2013-08-27 12:02:54 +0200 | [diff] [blame] | 2 | * Copyright (C) 2007-2013 Michal Simek <monstr@monstr.eu> |
| 3 | * Copyright (C) 2012-2013 Xilinx, Inc. |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 4 | * Copyright (C) 2007-2009 PetaLogix |
| 5 | * Copyright (C) 2006 Atmark Techno, Inc. |
| 6 | * |
| 7 | * This file is subject to the terms and conditions of the GNU General Public |
| 8 | * License. See the file "COPYING" in the main directory of this archive |
| 9 | * for more details. |
| 10 | */ |
| 11 | |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 12 | #include <linux/interrupt.h> |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 13 | #include <linux/delay.h> |
| 14 | #include <linux/sched.h> |
Michal Simek | 839396a | 2013-12-20 10:16:40 +0100 | [diff] [blame] | 15 | #include <linux/sched_clock.h> |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 16 | #include <linux/clk.h> |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 17 | #include <linux/clockchips.h> |
Michal Simek | cfd4eae | 2013-08-27 11:52:32 +0200 | [diff] [blame] | 18 | #include <linux/of_address.h> |
Rob Herring | 5c9f303 | 2013-09-07 14:05:10 -0500 | [diff] [blame] | 19 | #include <linux/of_irq.h> |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 20 | #include <asm/cpuinfo.h> |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 21 | |
Michal Simek | cfd4eae | 2013-08-27 11:52:32 +0200 | [diff] [blame] | 22 | static void __iomem *timer_baseaddr; |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 23 | |
Michal Simek | 29e3dbb | 2011-02-07 11:33:47 +0100 | [diff] [blame] | 24 | static unsigned int freq_div_hz; |
| 25 | static unsigned int timer_clock_freq; |
Michal Simek | ccea0e6 | 2010-10-07 17:39:21 +1000 | [diff] [blame] | 26 | |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 27 | #define TCSR0 (0x00) |
| 28 | #define TLR0 (0x04) |
| 29 | #define TCR0 (0x08) |
| 30 | #define TCSR1 (0x10) |
| 31 | #define TLR1 (0x14) |
| 32 | #define TCR1 (0x18) |
| 33 | |
| 34 | #define TCSR_MDT (1<<0) |
| 35 | #define TCSR_UDT (1<<1) |
| 36 | #define TCSR_GENT (1<<2) |
| 37 | #define TCSR_CAPT (1<<3) |
| 38 | #define TCSR_ARHT (1<<4) |
| 39 | #define TCSR_LOAD (1<<5) |
| 40 | #define TCSR_ENIT (1<<6) |
| 41 | #define TCSR_ENT (1<<7) |
| 42 | #define TCSR_TINT (1<<8) |
| 43 | #define TCSR_PWMA (1<<9) |
| 44 | #define TCSR_ENALL (1<<10) |
| 45 | |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 46 | static unsigned int (*read_fn)(void __iomem *); |
| 47 | static void (*write_fn)(u32, void __iomem *); |
| 48 | |
| 49 | static void timer_write32(u32 val, void __iomem *addr) |
| 50 | { |
| 51 | iowrite32(val, addr); |
| 52 | } |
| 53 | |
| 54 | static unsigned int timer_read32(void __iomem *addr) |
| 55 | { |
| 56 | return ioread32(addr); |
| 57 | } |
| 58 | |
| 59 | static void timer_write32_be(u32 val, void __iomem *addr) |
| 60 | { |
| 61 | iowrite32be(val, addr); |
| 62 | } |
| 63 | |
| 64 | static unsigned int timer_read32_be(void __iomem *addr) |
| 65 | { |
| 66 | return ioread32be(addr); |
| 67 | } |
| 68 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 69 | static inline void xilinx_timer0_stop(void) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 70 | { |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 71 | write_fn(read_fn(timer_baseaddr + TCSR0) & ~TCSR_ENT, |
| 72 | timer_baseaddr + TCSR0); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 73 | } |
| 74 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 75 | static inline void xilinx_timer0_start_periodic(unsigned long load_val) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 76 | { |
| 77 | if (!load_val) |
| 78 | load_val = 1; |
Michal Simek | 9e77dab | 2013-08-27 09:57:52 +0200 | [diff] [blame] | 79 | /* loading value to timer reg */ |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 80 | write_fn(load_val, timer_baseaddr + TLR0); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 81 | |
| 82 | /* load the initial value */ |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 83 | write_fn(TCSR_LOAD, timer_baseaddr + TCSR0); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 84 | |
| 85 | /* see timer data sheet for detail |
| 86 | * !ENALL - don't enable 'em all |
| 87 | * !PWMA - disable pwm |
| 88 | * TINT - clear interrupt status |
| 89 | * ENT- enable timer itself |
Michal Simek | f7f4786 | 2011-04-05 15:49:22 +0200 | [diff] [blame] | 90 | * ENIT - enable interrupt |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 91 | * !LOAD - clear the bit to let go |
| 92 | * ARHT - auto reload |
| 93 | * !CAPT - no external trigger |
| 94 | * !GENT - no external signal |
| 95 | * UDT - set the timer as down counter |
| 96 | * !MDT0 - generate mode |
| 97 | */ |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 98 | write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT, |
| 99 | timer_baseaddr + TCSR0); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 100 | } |
| 101 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 102 | static inline void xilinx_timer0_start_oneshot(unsigned long load_val) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 103 | { |
| 104 | if (!load_val) |
| 105 | load_val = 1; |
Michal Simek | 9e77dab | 2013-08-27 09:57:52 +0200 | [diff] [blame] | 106 | /* loading value to timer reg */ |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 107 | write_fn(load_val, timer_baseaddr + TLR0); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 108 | |
| 109 | /* load the initial value */ |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 110 | write_fn(TCSR_LOAD, timer_baseaddr + TCSR0); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 111 | |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 112 | write_fn(TCSR_TINT|TCSR_ENIT|TCSR_ENT|TCSR_ARHT|TCSR_UDT, |
| 113 | timer_baseaddr + TCSR0); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 114 | } |
| 115 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 116 | static int xilinx_timer_set_next_event(unsigned long delta, |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 117 | struct clock_event_device *dev) |
| 118 | { |
| 119 | pr_debug("%s: next event, delta %x\n", __func__, (u32)delta); |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 120 | xilinx_timer0_start_oneshot(delta); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 121 | return 0; |
| 122 | } |
| 123 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 124 | static void xilinx_timer_set_mode(enum clock_event_mode mode, |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 125 | struct clock_event_device *evt) |
| 126 | { |
| 127 | switch (mode) { |
| 128 | case CLOCK_EVT_MODE_PERIODIC: |
Michal Simek | aaa5241 | 2012-10-04 14:24:58 +0200 | [diff] [blame] | 129 | pr_info("%s: periodic\n", __func__); |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 130 | xilinx_timer0_start_periodic(freq_div_hz); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 131 | break; |
| 132 | case CLOCK_EVT_MODE_ONESHOT: |
Michal Simek | aaa5241 | 2012-10-04 14:24:58 +0200 | [diff] [blame] | 133 | pr_info("%s: oneshot\n", __func__); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 134 | break; |
| 135 | case CLOCK_EVT_MODE_UNUSED: |
Michal Simek | aaa5241 | 2012-10-04 14:24:58 +0200 | [diff] [blame] | 136 | pr_info("%s: unused\n", __func__); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 137 | break; |
| 138 | case CLOCK_EVT_MODE_SHUTDOWN: |
Michal Simek | aaa5241 | 2012-10-04 14:24:58 +0200 | [diff] [blame] | 139 | pr_info("%s: shutdown\n", __func__); |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 140 | xilinx_timer0_stop(); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 141 | break; |
| 142 | case CLOCK_EVT_MODE_RESUME: |
Michal Simek | aaa5241 | 2012-10-04 14:24:58 +0200 | [diff] [blame] | 143 | pr_info("%s: resume\n", __func__); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 144 | break; |
| 145 | } |
| 146 | } |
| 147 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 148 | static struct clock_event_device clockevent_xilinx_timer = { |
| 149 | .name = "xilinx_clockevent", |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 150 | .features = CLOCK_EVT_FEAT_ONESHOT | CLOCK_EVT_FEAT_PERIODIC, |
Michal Simek | c8f7743 | 2010-06-10 16:04:05 +0200 | [diff] [blame] | 151 | .shift = 8, |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 152 | .rating = 300, |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 153 | .set_next_event = xilinx_timer_set_next_event, |
| 154 | .set_mode = xilinx_timer_set_mode, |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 155 | }; |
| 156 | |
| 157 | static inline void timer_ack(void) |
| 158 | { |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 159 | write_fn(read_fn(timer_baseaddr + TCSR0), timer_baseaddr + TCSR0); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 160 | } |
| 161 | |
| 162 | static irqreturn_t timer_interrupt(int irq, void *dev_id) |
| 163 | { |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 164 | struct clock_event_device *evt = &clockevent_xilinx_timer; |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 165 | #ifdef CONFIG_HEART_BEAT |
Guenter Roeck | 79c157a | 2014-02-17 22:46:54 -0800 | [diff] [blame] | 166 | microblaze_heartbeat(); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 167 | #endif |
| 168 | timer_ack(); |
| 169 | evt->event_handler(evt); |
| 170 | return IRQ_HANDLED; |
| 171 | } |
| 172 | |
| 173 | static struct irqaction timer_irqaction = { |
| 174 | .handler = timer_interrupt, |
Michal Simek | db2a7df | 2013-08-20 16:45:36 +0200 | [diff] [blame] | 175 | .flags = IRQF_TIMER, |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 176 | .name = "timer", |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 177 | .dev_id = &clockevent_xilinx_timer, |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 178 | }; |
| 179 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 180 | static __init void xilinx_clockevent_init(void) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 181 | { |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 182 | clockevent_xilinx_timer.mult = |
Michal Simek | ccea0e6 | 2010-10-07 17:39:21 +1000 | [diff] [blame] | 183 | div_sc(timer_clock_freq, NSEC_PER_SEC, |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 184 | clockevent_xilinx_timer.shift); |
| 185 | clockevent_xilinx_timer.max_delta_ns = |
| 186 | clockevent_delta2ns((u32)~0, &clockevent_xilinx_timer); |
| 187 | clockevent_xilinx_timer.min_delta_ns = |
| 188 | clockevent_delta2ns(1, &clockevent_xilinx_timer); |
| 189 | clockevent_xilinx_timer.cpumask = cpumask_of(0); |
| 190 | clockevents_register_device(&clockevent_xilinx_timer); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 191 | } |
| 192 | |
Michal Simek | 839396a | 2013-12-20 10:16:40 +0100 | [diff] [blame] | 193 | static u64 xilinx_clock_read(void) |
| 194 | { |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 195 | return read_fn(timer_baseaddr + TCR1); |
Michal Simek | 839396a | 2013-12-20 10:16:40 +0100 | [diff] [blame] | 196 | } |
| 197 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 198 | static cycle_t xilinx_read(struct clocksource *cs) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 199 | { |
| 200 | /* reading actual value of timer 1 */ |
Michal Simek | 839396a | 2013-12-20 10:16:40 +0100 | [diff] [blame] | 201 | return (cycle_t)xilinx_clock_read(); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 202 | } |
| 203 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 204 | static struct timecounter xilinx_tc = { |
Michal Simek | 519e9f4 | 2009-11-06 12:31:00 +0100 | [diff] [blame] | 205 | .cc = NULL, |
| 206 | }; |
| 207 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 208 | static cycle_t xilinx_cc_read(const struct cyclecounter *cc) |
Michal Simek | 519e9f4 | 2009-11-06 12:31:00 +0100 | [diff] [blame] | 209 | { |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 210 | return xilinx_read(NULL); |
Michal Simek | 519e9f4 | 2009-11-06 12:31:00 +0100 | [diff] [blame] | 211 | } |
| 212 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 213 | static struct cyclecounter xilinx_cc = { |
| 214 | .read = xilinx_cc_read, |
Michal Simek | 519e9f4 | 2009-11-06 12:31:00 +0100 | [diff] [blame] | 215 | .mask = CLOCKSOURCE_MASK(32), |
Michal Simek | c8f7743 | 2010-06-10 16:04:05 +0200 | [diff] [blame] | 216 | .shift = 8, |
Michal Simek | 519e9f4 | 2009-11-06 12:31:00 +0100 | [diff] [blame] | 217 | }; |
| 218 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 219 | static int __init init_xilinx_timecounter(void) |
Michal Simek | 519e9f4 | 2009-11-06 12:31:00 +0100 | [diff] [blame] | 220 | { |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 221 | xilinx_cc.mult = div_sc(timer_clock_freq, NSEC_PER_SEC, |
| 222 | xilinx_cc.shift); |
Michal Simek | 519e9f4 | 2009-11-06 12:31:00 +0100 | [diff] [blame] | 223 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 224 | timecounter_init(&xilinx_tc, &xilinx_cc, sched_clock()); |
Michal Simek | 519e9f4 | 2009-11-06 12:31:00 +0100 | [diff] [blame] | 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 229 | static struct clocksource clocksource_microblaze = { |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 230 | .name = "xilinx_clocksource", |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 231 | .rating = 300, |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 232 | .read = xilinx_read, |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 233 | .mask = CLOCKSOURCE_MASK(32), |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 234 | .flags = CLOCK_SOURCE_IS_CONTINUOUS, |
| 235 | }; |
| 236 | |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 237 | static int __init xilinx_clocksource_init(void) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 238 | { |
John Stultz | b8f39f7 | 2010-04-26 20:22:23 -0700 | [diff] [blame] | 239 | if (clocksource_register_hz(&clocksource_microblaze, timer_clock_freq)) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 240 | panic("failed to register clocksource"); |
| 241 | |
| 242 | /* stop timer1 */ |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 243 | write_fn(read_fn(timer_baseaddr + TCSR1) & ~TCSR_ENT, |
| 244 | timer_baseaddr + TCSR1); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 245 | /* start timer1 - up counting without interrupt */ |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 246 | write_fn(TCSR_TINT|TCSR_ENT|TCSR_ARHT, timer_baseaddr + TCSR1); |
Michal Simek | 519e9f4 | 2009-11-06 12:31:00 +0100 | [diff] [blame] | 247 | |
| 248 | /* register timecounter - for ftrace support */ |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 249 | init_xilinx_timecounter(); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 250 | return 0; |
| 251 | } |
| 252 | |
Michal Simek | 4bcd943 | 2013-08-27 11:13:29 +0200 | [diff] [blame] | 253 | static void __init xilinx_timer_init(struct device_node *timer) |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 254 | { |
Michal Simek | c112054 | 2013-12-18 17:18:48 +0100 | [diff] [blame] | 255 | struct clk *clk; |
Michal Simek | 03fe0d3 | 2014-01-27 10:41:59 +0100 | [diff] [blame] | 256 | static int initialized; |
Michal Simek | 5a26cd6 | 2011-12-09 12:26:16 +0100 | [diff] [blame] | 257 | u32 irq; |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 258 | u32 timer_num = 1; |
Michal Simek | 9e77dab | 2013-08-27 09:57:52 +0200 | [diff] [blame] | 259 | |
Michal Simek | 03fe0d3 | 2014-01-27 10:41:59 +0100 | [diff] [blame] | 260 | if (initialized) |
| 261 | return; |
| 262 | |
| 263 | initialized = 1; |
| 264 | |
Michal Simek | cfd4eae | 2013-08-27 11:52:32 +0200 | [diff] [blame] | 265 | timer_baseaddr = of_iomap(timer, 0); |
| 266 | if (!timer_baseaddr) { |
| 267 | pr_err("ERROR: invalid timer base address\n"); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 268 | BUG(); |
| 269 | } |
| 270 | |
Michal Simek | a1715bb | 2014-02-24 15:04:03 +0100 | [diff] [blame^] | 271 | write_fn = timer_write32; |
| 272 | read_fn = timer_read32; |
| 273 | |
| 274 | write_fn(TCSR_MDT, timer_baseaddr + TCSR0); |
| 275 | if (!(read_fn(timer_baseaddr + TCSR0) & TCSR_MDT)) { |
| 276 | write_fn = timer_write32_be; |
| 277 | read_fn = timer_read32_be; |
| 278 | } |
| 279 | |
Michal Simek | cfd4eae | 2013-08-27 11:52:32 +0200 | [diff] [blame] | 280 | irq = irq_of_parse_and_map(timer, 0); |
| 281 | |
| 282 | of_property_read_u32(timer, "xlnx,one-timer-only", &timer_num); |
| 283 | if (timer_num) { |
| 284 | pr_emerg("Please enable two timers in HW\n"); |
| 285 | BUG(); |
| 286 | } |
| 287 | |
| 288 | pr_info("%s: irq=%d\n", timer->full_name, irq); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 289 | |
Michal Simek | c112054 | 2013-12-18 17:18:48 +0100 | [diff] [blame] | 290 | clk = of_clk_get(timer, 0); |
| 291 | if (IS_ERR(clk)) { |
| 292 | pr_err("ERROR: timer CCF input clock not found\n"); |
| 293 | /* If there is clock-frequency property than use it */ |
| 294 | of_property_read_u32(timer, "clock-frequency", |
| 295 | &timer_clock_freq); |
| 296 | } else { |
| 297 | timer_clock_freq = clk_get_rate(clk); |
| 298 | } |
| 299 | |
| 300 | if (!timer_clock_freq) { |
| 301 | pr_err("ERROR: Using CPU clock frequency\n"); |
Michal Simek | ccea0e6 | 2010-10-07 17:39:21 +1000 | [diff] [blame] | 302 | timer_clock_freq = cpuinfo.cpu_clock_freq; |
Michal Simek | c112054 | 2013-12-18 17:18:48 +0100 | [diff] [blame] | 303 | } |
Michal Simek | ccea0e6 | 2010-10-07 17:39:21 +1000 | [diff] [blame] | 304 | |
| 305 | freq_div_hz = timer_clock_freq / HZ; |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 306 | |
| 307 | setup_irq(irq, &timer_irqaction); |
| 308 | #ifdef CONFIG_HEART_BEAT |
Guenter Roeck | 79c157a | 2014-02-17 22:46:54 -0800 | [diff] [blame] | 309 | microblaze_setup_heartbeat(); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 310 | #endif |
Michal Simek | 5955563a | 2013-08-27 12:04:39 +0200 | [diff] [blame] | 311 | xilinx_clocksource_init(); |
| 312 | xilinx_clockevent_init(); |
Michal Simek | 6f34b08 | 2010-04-16 09:50:13 +0200 | [diff] [blame] | 313 | |
Michal Simek | 839396a | 2013-12-20 10:16:40 +0100 | [diff] [blame] | 314 | sched_clock_register(xilinx_clock_read, 32, timer_clock_freq); |
Michal Simek | eedbdab | 2009-03-27 14:25:49 +0100 | [diff] [blame] | 315 | } |
Michal Simek | 4bcd943 | 2013-08-27 11:13:29 +0200 | [diff] [blame] | 316 | |
| 317 | CLOCKSOURCE_OF_DECLARE(xilinx_timer, "xlnx,xps-timer-1.00.a", |
| 318 | xilinx_timer_init); |