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gerrit-public.fairphone.software / kernel / msm-4.9 / aa1b9b4836a8ab093ec06b0780553566a5430da7 / . / drivers / gpu / drm / nouveau / core / subdev / device / nv40.c
blob: 320ccc4ae05c3501b2b15c5f98563a22a8b7c76a [file] [log] [blame]
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]1/*
2 * Copyright 2012 Red Hat Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice shall be included in
12 * all copies or substantial portions of the Software.
13 *
14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
15 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
16 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
17 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
18 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
20 * OTHER DEALINGS IN THE SOFTWARE.
21 *
22 * Authors: Ben Skeggs
23 */
24
25#include <subdev/device.h>
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]26#include <subdev/bios.h>
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]27#include <subdev/gpio.h>
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]28#include <subdev/i2c.h>
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]29#include <subdev/clock.h>
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]30#include <subdev/therm.h>
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]31#include <subdev/devinit.h>
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]32#include <subdev/mc.h>
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]33#include <subdev/timer.h>
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]34#include <subdev/fb.h>
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]35#include <subdev/instmem.h>
36#include <subdev/vm.h>
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]37
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]38#include <engine/dmaobj.h>
39#include <engine/fifo.h>
40#include <engine/software.h>
41#include <engine/graph.h>
42#include <engine/mpeg.h>
43#include <engine/disp.h>
44
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]45int
46nv40_identify(struct nouveau_device *device)
47{
48 switch (device->chipset) {
49 case 0x40:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]50 device->cname = "NV40";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]51 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]52 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]53 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]54 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]55 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]56 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]57 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]58 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]59 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]60 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
61 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]62 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
63 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
64 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
65 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
66 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
67 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]68 break;
69 case 0x41:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]70 device->cname = "NV41";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]71 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]72 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]73 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]74 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]75 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]76 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]77 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]78 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]79 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]80 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
81 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]82 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
83 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
84 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
85 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
86 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
87 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]88 break;
89 case 0x42:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]90 device->cname = "NV42";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]91 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]92 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]93 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]94 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]95 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]96 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]97 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]98 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]99 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]100 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
101 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]102 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
103 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
104 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
105 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
106 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
107 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]108 break;
109 case 0x43:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]110 device->cname = "NV43";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]111 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]112 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]113 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]114 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]115 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]116 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]117 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]118 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]119 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]120 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
121 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]122 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
123 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
124 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
125 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
126 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
127 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]128 break;
129 case 0x45:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]130 device->cname = "NV45";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]131 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]132 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]133 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]134 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]135 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]136 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]137 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]138 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]139 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]140 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
141 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]142 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
143 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
144 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
145 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
146 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
147 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]148 break;
149 case 0x47:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]150 device->cname = "G70";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]151 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]152 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]153 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]154 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]155 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]156 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]157 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]158 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]159 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]160 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
161 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]162 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
163 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
164 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
165 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
166 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
167 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]168 break;
169 case 0x49:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]170 device->cname = "G71";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]171 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]172 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]173 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]174 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]175 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]176 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]177 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]178 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]179 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]180 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
181 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]182 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
183 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
184 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
185 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
186 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
187 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]188 break;
189 case 0x4b:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]190 device->cname = "G73";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]191 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]192 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]193 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]194 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]195 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]196 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]197 device->oclass[NVDEV_SUBDEV_MC ] = &nv04_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]198 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]199 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]200 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
201 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]202 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
203 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
204 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
205 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
206 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
207 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]208 break;
209 case 0x44:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]210 device->cname = "NV44";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]211 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]212 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]213 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]214 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]215 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]216 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]217 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]218 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]219 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]220 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
221 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]222 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
223 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
224 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
225 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
226 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
227 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]228 break;
229 case 0x46:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]230 device->cname = "G72";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]231 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]232 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]233 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]234 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]235 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]236 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]237 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]238 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]239 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]240 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
241 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]242 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
243 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
244 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
245 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
246 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
247 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]248 break;
249 case 0x4a:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]250 device->cname = "NV44A";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]251 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]252 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]253 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]254 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]255 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]256 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]257 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]258 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]259 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]260 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
261 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]262 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
263 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
264 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
265 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
266 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
267 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]268 break;
269 case 0x4c:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]270 device->cname = "C61";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]271 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]272 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]273 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]274 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]275 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]276 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]277 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]278 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]279 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]280 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
281 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]282 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
283 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
284 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
285 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
286 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
287 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]288 break;
289 case 0x4e:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]290 device->cname = "C51";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]291 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]292 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]293 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]294 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]295 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]296 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]297 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]298 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]299 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]300 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
301 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]302 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
303 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
304 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
305 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
306 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
307 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]308 break;
309 case 0x63:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]310 device->cname = "C73";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]311 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]312 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]313 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]314 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]315 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]316 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]317 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]318 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]319 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]320 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
321 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]322 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
323 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
324 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
325 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
326 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
327 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]328 break;
329 case 0x67:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]330 device->cname = "C67";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]331 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]332 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]333 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]334 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]335 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]336 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]337 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]338 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]339 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]340 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
341 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]342 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
343 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
344 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
345 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
346 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
347 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]348 break;
349 case 0x68:
Ben Skeggs2094dd82012-07-27 08:28:20 +1000[diff] [blame]350 device->cname = "C68";
Ben Skeggs70c0f262012-07-10 10:49:22 +1000[diff] [blame]351 device->oclass[NVDEV_SUBDEV_VBIOS ] = &nouveau_bios_oclass;
Ben Skeggse0996ae2012-07-10 12:20:17 +1000[diff] [blame]352 device->oclass[NVDEV_SUBDEV_GPIO ] = &nv10_gpio_oclass;
Ben Skeggs4196faa2012-07-10 14:36:38 +1000[diff] [blame]353 device->oclass[NVDEV_SUBDEV_I2C ] = &nouveau_i2c_oclass;
Ben Skeggs8aceb7d2012-07-10 16:45:24 +1000[diff] [blame]354 device->oclass[NVDEV_SUBDEV_CLOCK ] = &nv40_clock_oclass;
Martin Peresaa1b9b42012-09-02 02:55:58 +0200[diff] [blame^]355 device->oclass[NVDEV_SUBDEV_THERM ] = &nv40_therm_oclass;
Ben Skeggscb75d972012-07-11 10:44:20 +1000[diff] [blame]356 device->oclass[NVDEV_SUBDEV_DEVINIT] = &nv1a_devinit_oclass;
Ben Skeggs7d9115d2012-07-11 15:58:56 +1000[diff] [blame]357 device->oclass[NVDEV_SUBDEV_MC ] = &nv44_mc_oclass;
Ben Skeggs5a5c7432012-07-11 16:08:25 +1000[diff] [blame]358 device->oclass[NVDEV_SUBDEV_TIMER ] = &nv04_timer_oclass;
Ben Skeggs861d2102012-07-11 19:05:01 +1000[diff] [blame]359 device->oclass[NVDEV_SUBDEV_FB ] = &nv40_fb_oclass;
Ben Skeggs3863c9b2012-07-14 19:09:17 +1000[diff] [blame]360 device->oclass[NVDEV_SUBDEV_INSTMEM] = &nv40_instmem_oclass;
361 device->oclass[NVDEV_SUBDEV_VM ] = &nv04_vmmgr_oclass;
Ben Skeggsebb945a2012-07-20 08:17:34 +1000[diff] [blame]362 device->oclass[NVDEV_ENGINE_DMAOBJ ] = &nv04_dmaeng_oclass;
363 device->oclass[NVDEV_ENGINE_FIFO ] = &nv40_fifo_oclass;
364 device->oclass[NVDEV_ENGINE_SW ] = &nv10_software_oclass;
365 device->oclass[NVDEV_ENGINE_GR ] = &nv40_graph_oclass;
366 device->oclass[NVDEV_ENGINE_MPEG ] = &nv40_mpeg_oclass;
367 device->oclass[NVDEV_ENGINE_DISP ] = &nv04_disp_oclass;
Ben Skeggs9274f4a2012-07-06 07:36:43 +1000[diff] [blame]368 break;
369 default:
370 nv_fatal(device, "unknown Curie chipset\n");
371 return -EINVAL;
372 }
373
374 return 0;
375}