Blame - drivers/irqchip/Kconfig - kernel/msm-4.9

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Thomas Petazzoni	f6e916b	2012-11-20 23:00:52 +0100	[diff] [blame]	1	config IRQCHIP
				2	def_bool y
				3	depends on OF_IRQ
				4
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	5	config ARM_GIC
				6	bool
				7	select IRQ_DOMAIN
Yingjoe Chen	9a1091e	2014-11-25 16:04:19 +0800	[diff] [blame]	8	select IRQ_DOMAIN_HIERARCHY
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	9	select MULTI_IRQ_HANDLER
				10
Suravee Suthikulpanit	853a33c	2014-11-25 18:47:22 +0000	[diff] [blame]	11	config ARM_GIC_V2M
				12	bool
				13	depends on ARM_GIC
				14	depends on PCI && PCI_MSI
				15	select PCI_MSI_IRQ_DOMAIN
				16
Rob Herring	81243e4	2012-11-20 21:21:40 -0600	[diff] [blame]	17	config GIC_NON_BANKED
				18	bool
				19
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	20	config ARM_GIC_V3
				21	bool
				22	select IRQ_DOMAIN
				23	select MULTI_IRQ_HANDLER
Marc Zyngier	443acc4	2014-11-24 14:35:09 +0000	[diff] [blame]	24	select IRQ_DOMAIN_HIERARCHY
Marc Zyngier	021f653	2014-06-30 16:01:31 +0100	[diff] [blame]	25
Marc Zyngier	1981272	2014-11-24 14:35:19 +0000	[diff] [blame]	26	config ARM_GIC_V3_ITS
				27	bool
				28	select PCI_MSI_IRQ_DOMAIN
Uwe Kleine-König	292ec08	2013-06-26 09:18:48 +0200	[diff] [blame]	29
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	30	config ARM_NVIC
				31	bool
				32	select IRQ_DOMAIN
Stefan Agner	2d9f59f	2015-05-16 11:44:16 +0200	[diff] [blame]	33	select IRQ_DOMAIN_HIERARCHY
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	34	select GENERIC_IRQ_CHIP
				35
				36	config ARM_VIC
				37	bool
				38	select IRQ_DOMAIN
				39	select MULTI_IRQ_HANDLER
				40
				41	config ARM_VIC_NR
				42	int
				43	default 4 if ARCH_S5PV210
Rob Herring	44430ec	2012-10-27 17:25:26 -0500	[diff] [blame]	44	default 2
				45	depends on ARM_VIC
				46	help
				47	The maximum number of VICs available in the system, for
				48	power management.
				49
Boris BREZILLON	b1479eb	2014-07-10 19:14:18 +0200	[diff] [blame]	50	config ATMEL_AIC_IRQ
				51	bool
				52	select GENERIC_IRQ_CHIP
				53	select IRQ_DOMAIN
				54	select MULTI_IRQ_HANDLER
				55	select SPARSE_IRQ
				56
				57	config ATMEL_AIC5_IRQ
				58	bool
				59	select GENERIC_IRQ_CHIP
				60	select IRQ_DOMAIN
				61	select MULTI_IRQ_HANDLER
				62	select SPARSE_IRQ
				63
Ralf Baechle	0509cfd	2015-07-08 14:46:08 +0200	[diff] [blame]	64	config I8259
				65	bool
				66	select IRQ_DOMAIN
				67
Kevin Cernekee	5f7f031	2014-12-25 09:49:06 -0800	[diff] [blame]	68	config BCM7038_L1_IRQ
				69	bool
				70	select GENERIC_IRQ_CHIP
				71	select IRQ_DOMAIN
				72
Kevin Cernekee	a4fcbb8	2014-11-06 22:44:27 -0800	[diff] [blame]	73	config BCM7120_L2_IRQ
				74	bool
				75	select GENERIC_IRQ_CHIP
				76	select IRQ_DOMAIN
				77
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	78	config BRCMSTB_L2_IRQ
				79	bool
Florian Fainelli	7f646e9	2014-05-23 17:40:53 -0700	[diff] [blame]	80	select GENERIC_IRQ_CHIP
				81	select IRQ_DOMAIN
				82
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	83	config DW_APB_ICTL
				84	bool
Jisheng Zhang	e158849	2014-10-22 20:59:10 +0800	[diff] [blame]	85	select GENERIC_IRQ_CHIP
Sebastian Hesselbarth	350d71b9	2013-09-09 14:01:20 +0200	[diff] [blame]	86	select IRQ_DOMAIN
				87
James Hogan	b6ef916	2013-04-22 15:43:50 +0100	[diff] [blame]	88	config IMGPDC_IRQ
				89	bool
				90	select GENERIC_IRQ_CHIP
				91	select IRQ_DOMAIN
				92
Ralf Baechle	67e38cf	2015-05-26 18:20:06 +0200	[diff] [blame]	93	config IRQ_MIPS_CPU
				94	bool
				95	select GENERIC_IRQ_CHIP
				96	select IRQ_DOMAIN
				97
Alexander Shiyan	afc98d9	2014-02-02 12:07:46 +0400	[diff] [blame]	98	config CLPS711X_IRQCHIP
				99	bool
				100	depends on ARCH_CLPS711X
				101	select IRQ_DOMAIN
				102	select MULTI_IRQ_HANDLER
				103	select SPARSE_IRQ
				104	default y
				105
Stefan Kristiansson	4db8e6d	2014-05-26 23:31:42 +0300	[diff] [blame]	106	config OR1K_PIC
				107	bool
				108	select IRQ_DOMAIN
				109
Felipe Balbi	8598066	2014-09-15 16:15:02 -0500	[diff] [blame]	110	config OMAP_IRQCHIP
				111	bool
				112	select GENERIC_IRQ_CHIP
				113	select IRQ_DOMAIN
				114
Sebastian Hesselbarth	9dbd90f	2013-06-06 18:27:09 +0200	[diff] [blame]	115	config ORION_IRQCHIP
				116	bool
				117	select IRQ_DOMAIN
				118	select MULTI_IRQ_HANDLER
				119
Cristian Birsan	aaa8666	2016-01-13 18:15:35 -0700	[diff] [blame^]	120	config PIC32_EVIC
				121	bool
				122	select GENERIC_IRQ_CHIP
				123	select IRQ_DOMAIN
				124
Magnus Damm	4435804	2013-02-18 23:28:34 +0900	[diff] [blame]	125	config RENESAS_INTC_IRQPIN
				126	bool
				127	select IRQ_DOMAIN
				128
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	129	config RENESAS_IRQC
				130	bool
Magnus Damm	99c221d	2015-09-28 18:42:37 +0900	[diff] [blame]	131	select GENERIC_IRQ_CHIP
Magnus Damm	fbc83b7	2013-02-27 17:15:01 +0900	[diff] [blame]	132	select IRQ_DOMAIN
				133
Lee Jones	0708848	2015-02-18 15:13:58 +0000	[diff] [blame]	134	config ST_IRQCHIP
				135	bool
				136	select REGMAP
				137	select MFD_SYSCON
				138	help
				139	Enables SysCfg Controlled IRQs on STi based platforms.
				140
Christian Ruppert	b06eb01	2013-06-25 18:29:57 +0200	[diff] [blame]	141	config TB10X_IRQC
				142	bool
				143	select IRQ_DOMAIN
				144	select GENERIC_IRQ_CHIP
				145
Linus Walleij	2389d50	2012-10-31 22:04:31 +0100	[diff] [blame]	146	config VERSATILE_FPGA_IRQ
				147	bool
				148	select IRQ_DOMAIN
				149
				150	config VERSATILE_FPGA_IRQ_NR
				151	int
				152	default 4
				153	depends on VERSATILE_FPGA_IRQ
Max Filippov	26a8e96	2013-12-01 12:04:57 +0400	[diff] [blame]	154
				155	config XTENSA_MX
				156	bool
				157	select IRQ_DOMAIN
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	158
				159	config IRQ_CROSSBAR
				160	bool
				161	help
Masanari Iida	f54619f	2014-09-18 12:09:42 +0900	[diff] [blame]	162	Support for a CROSSBAR ip that precedes the main interrupt controller.
Sricharan R	96ca848	2013-12-03 15:57:23 +0530	[diff] [blame]	163	The primary irqchip invokes the crossbar's callback which inturn allocates
				164	a free irq and configures the IP. Thus the peripheral interrupts are
				165	routed to one of the free irqchip interrupt lines.
Grygorii Strashko	89323f8	2014-07-23 17:40:30 +0300	[diff] [blame]	166
				167	config KEYSTONE_IRQ
				168	tristate "Keystone 2 IRQ controller IP"
				169	depends on ARCH_KEYSTONE
				170	help
				171	Support for Texas Instruments Keystone 2 IRQ controller IP which
				172	is part of the Keystone 2 IPC mechanism
Andrew Bresticker	8a19b8f	2014-09-18 14:47:19 -0700	[diff] [blame]	173
				174	config MIPS_GIC
				175	bool
				176	select MIPS_CM
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	177
Paul Burton	44e08e7	2015-05-24 16:11:31 +0100	[diff] [blame]	178	config INGENIC_IRQ
				179	bool
				180	depends on MACH_INGENIC
				181	default y
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	182
Yoshinori Sato	8a76448	2015-05-10 02:30:47 +0900	[diff] [blame]	183	config RENESAS_H8300H_INTC
				184	bool
				185	select IRQ_DOMAIN
				186
				187	config RENESAS_H8S_INTC
				188	bool
Linus Torvalds	78c10e5	2015-06-27 12:44:34 -0700	[diff] [blame]	189	select IRQ_DOMAIN
Shenwei Wang	e324c4d	2015-08-24 14:04:15 -0500	[diff] [blame]	190
				191	config IMX_GPCV2
				192	bool
				193	select IRQ_DOMAIN
				194	help
				195	Enables the wakeup IRQs for IMX platforms with GPCv2 block
Oleksij Rempel	7e4ac67	2015-10-12 21:15:34 +0200	[diff] [blame]	196
				197	config IRQ_MXS
				198	def_bool y if MACH_ASM9260 \|\| ARCH_MXS
				199	select IRQ_DOMAIN
				200	select STMP_DEVICE