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Joerg Roedelb6c02712008-06-26 21:27:53 +02001/*
Joerg Roedel5d0d7152010-10-13 11:13:21 +02002 * Copyright (C) 2007-2010 Advanced Micro Devices, Inc.
Joerg Roedel63ce3ae2015-02-04 16:12:55 +01003 * Author: Joerg Roedel <jroedel@suse.de>
Joerg Roedelb6c02712008-06-26 21:27:53 +02004 * Leo Duran <leo.duran@amd.com>
5 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 as published
8 * by the Free Software Foundation.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 * You should have received a copy of the GNU General Public License
16 * along with this program; if not, write to the Free Software
17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 */
19
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010020#include <linux/ratelimit.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020021#include <linux/pci.h>
Joerg Roedelcb41ed82011-04-05 11:00:53 +020022#include <linux/pci-ats.h>
Akinobu Mitaa66022c2009-12-15 16:48:28 -080023#include <linux/bitmap.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090024#include <linux/slab.h>
Joerg Roedel7f265082008-12-12 13:50:21 +010025#include <linux/debugfs.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020026#include <linux/scatterlist.h>
FUJITA Tomonori51491362009-01-05 23:47:25 +090027#include <linux/dma-mapping.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020028#include <linux/iommu-helper.h>
Joerg Roedelc156e342008-12-02 18:13:27 +010029#include <linux/iommu.h>
Joerg Roedel815b33f2011-04-06 17:26:49 +020030#include <linux/delay.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020031#include <linux/amd-iommu.h>
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010032#include <linux/notifier.h>
33#include <linux/export.h>
Joerg Roedel2b324502012-06-21 16:29:10 +020034#include <linux/irq.h>
35#include <linux/msi.h>
Joerg Roedel3b839a52015-04-01 14:58:47 +020036#include <linux/dma-contiguous.h>
Jiang Liu7c71d302015-04-13 14:11:33 +080037#include <linux/irqdomain.h>
Joerg Roedel2b324502012-06-21 16:29:10 +020038#include <asm/irq_remapping.h>
39#include <asm/io_apic.h>
40#include <asm/apic.h>
41#include <asm/hw_irq.h>
Joerg Roedel17f5b562011-07-06 17:14:44 +020042#include <asm/msidef.h>
Joerg Roedelb6c02712008-06-26 21:27:53 +020043#include <asm/proto.h>
FUJITA Tomonori46a7fa22008-07-11 10:23:42 +090044#include <asm/iommu.h>
Joerg Roedel1d9b16d2008-11-27 18:39:15 +010045#include <asm/gart.h>
Joerg Roedel27c21272011-05-30 15:56:24 +020046#include <asm/dma.h>
Joerg Roedel403f81d2011-06-14 16:44:25 +020047
48#include "amd_iommu_proto.h"
49#include "amd_iommu_types.h"
Joerg Roedel6b474b82012-06-26 16:46:04 +020050#include "irq_remapping.h"
Joerg Roedelb6c02712008-06-26 21:27:53 +020051
52#define CMD_SET_TYPE(cmd, t) ((cmd)->data[1] |= ((t) << 28))
53
Joerg Roedel815b33f2011-04-06 17:26:49 +020054#define LOOP_TIMEOUT 100000
Joerg Roedel136f78a2008-07-11 17:14:27 +020055
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020056/*
57 * This bitmap is used to advertise the page sizes our hardware support
58 * to the IOMMU core, which will then use this information to split
59 * physically contiguous memory regions it is mapping into page sizes
60 * that we support.
61 *
Joerg Roedel954e3dd2012-12-02 15:35:37 +010062 * 512GB Pages are not supported due to a hardware bug
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020063 */
Joerg Roedel954e3dd2012-12-02 15:35:37 +010064#define AMD_IOMMU_PGSIZES ((~0xFFFUL) & ~(2ULL << 38))
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +020065
Joerg Roedelb6c02712008-06-26 21:27:53 +020066static DEFINE_RWLOCK(amd_iommu_devtable_lock);
67
Joerg Roedel8fa5f802011-06-09 12:24:45 +020068/* List of all available dev_data structures */
69static LIST_HEAD(dev_data_list);
70static DEFINE_SPINLOCK(dev_data_list_lock);
71
Joerg Roedel6efed632012-06-14 15:52:58 +020072LIST_HEAD(ioapic_map);
73LIST_HEAD(hpet_map);
74
Joerg Roedel0feae532009-08-26 15:26:30 +020075/*
76 * Domain for untranslated devices - only allocated
77 * if iommu=pt passed on kernel cmd line.
78 */
Thierry Redingb22f6432014-06-27 09:03:12 +020079static const struct iommu_ops amd_iommu_ops;
Joerg Roedel26961ef2008-12-03 17:00:17 +010080
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010081static ATOMIC_NOTIFIER_HEAD(ppr_notifier);
Joerg Roedel52815b72011-11-17 17:24:28 +010082int amd_iommu_max_glx_val = -1;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +010083
Joerg Roedelac1534a2012-06-21 14:52:40 +020084static struct dma_map_ops amd_iommu_dma_ops;
85
Joerg Roedel431b2a22008-07-11 17:14:22 +020086/*
Joerg Roedel50917e22014-08-05 16:38:38 +020087 * This struct contains device specific data for the IOMMU
88 */
89struct iommu_dev_data {
90 struct list_head list; /* For domain->dev_list */
91 struct list_head dev_data_list; /* For global dev_data_list */
Joerg Roedelf251e182014-08-05 16:48:10 +020092 struct list_head alias_list; /* Link alias-groups together */
Joerg Roedel50917e22014-08-05 16:38:38 +020093 struct iommu_dev_data *alias_data;/* The alias dev_data */
94 struct protection_domain *domain; /* Domain the device is bound to */
Joerg Roedel50917e22014-08-05 16:38:38 +020095 u16 devid; /* PCI Device ID */
96 bool iommu_v2; /* Device can make use of IOMMUv2 */
Joerg Roedel1e6a7b02015-07-28 16:58:48 +020097 bool passthrough; /* Device is identity mapped */
Joerg Roedel50917e22014-08-05 16:38:38 +020098 struct {
99 bool enabled;
100 int qdep;
101 } ats; /* ATS state */
102 bool pri_tlp; /* PASID TLB required for
103 PPR completions */
104 u32 errata; /* Bitmap for errata to apply */
105};
106
107/*
Joerg Roedel431b2a22008-07-11 17:14:22 +0200108 * general struct to manage commands send to an IOMMU
109 */
Joerg Roedeld6449532008-07-11 17:14:28 +0200110struct iommu_cmd {
Joerg Roedelb6c02712008-06-26 21:27:53 +0200111 u32 data[4];
112};
113
Joerg Roedel05152a02012-06-15 16:53:51 +0200114struct kmem_cache *amd_iommu_irq_cache;
115
Joerg Roedel04bfdd82009-09-02 16:00:23 +0200116static void update_domain(struct protection_domain *domain);
Joerg Roedel7a5a5662015-06-30 08:56:11 +0200117static int protection_domain_init(struct protection_domain *domain);
Chris Wrightc1eee672009-05-21 00:56:58 -0700118
Joerg Roedel15898bb2009-11-24 15:39:42 +0100119/****************************************************************************
120 *
121 * Helper functions
122 *
123 ****************************************************************************/
124
Joerg Roedel3f4b87b2015-03-26 13:43:07 +0100125static struct protection_domain *to_pdomain(struct iommu_domain *dom)
126{
127 return container_of(dom, struct protection_domain, domain);
128}
129
Joerg Roedelf62dda62011-06-09 12:55:35 +0200130static struct iommu_dev_data *alloc_dev_data(u16 devid)
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200131{
132 struct iommu_dev_data *dev_data;
133 unsigned long flags;
134
135 dev_data = kzalloc(sizeof(*dev_data), GFP_KERNEL);
136 if (!dev_data)
137 return NULL;
138
Joerg Roedelf251e182014-08-05 16:48:10 +0200139 INIT_LIST_HEAD(&dev_data->alias_list);
140
Joerg Roedelf62dda62011-06-09 12:55:35 +0200141 dev_data->devid = devid;
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200142
143 spin_lock_irqsave(&dev_data_list_lock, flags);
144 list_add_tail(&dev_data->dev_data_list, &dev_data_list);
145 spin_unlock_irqrestore(&dev_data_list_lock, flags);
146
147 return dev_data;
148}
149
150static void free_dev_data(struct iommu_dev_data *dev_data)
151{
152 unsigned long flags;
153
154 spin_lock_irqsave(&dev_data_list_lock, flags);
155 list_del(&dev_data->dev_data_list);
156 spin_unlock_irqrestore(&dev_data_list_lock, flags);
157
158 kfree(dev_data);
159}
160
Joerg Roedel3b03bb72011-06-09 18:53:25 +0200161static struct iommu_dev_data *search_dev_data(u16 devid)
162{
163 struct iommu_dev_data *dev_data;
164 unsigned long flags;
165
166 spin_lock_irqsave(&dev_data_list_lock, flags);
167 list_for_each_entry(dev_data, &dev_data_list, dev_data_list) {
168 if (dev_data->devid == devid)
169 goto out_unlock;
170 }
171
172 dev_data = NULL;
173
174out_unlock:
175 spin_unlock_irqrestore(&dev_data_list_lock, flags);
176
177 return dev_data;
178}
179
180static struct iommu_dev_data *find_dev_data(u16 devid)
181{
182 struct iommu_dev_data *dev_data;
183
184 dev_data = search_dev_data(devid);
185
186 if (dev_data == NULL)
187 dev_data = alloc_dev_data(devid);
188
189 return dev_data;
190}
191
Joerg Roedel15898bb2009-11-24 15:39:42 +0100192static inline u16 get_device_id(struct device *dev)
193{
194 struct pci_dev *pdev = to_pci_dev(dev);
195
Shuah Khan6f2729b2013-02-27 17:07:30 -0700196 return PCI_DEVID(pdev->bus->number, pdev->devfn);
Joerg Roedel15898bb2009-11-24 15:39:42 +0100197}
198
Joerg Roedel657cbb62009-11-23 15:26:46 +0100199static struct iommu_dev_data *get_dev_data(struct device *dev)
200{
201 return dev->archdata.iommu;
202}
203
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100204static bool pci_iommuv2_capable(struct pci_dev *pdev)
205{
206 static const int caps[] = {
207 PCI_EXT_CAP_ID_ATS,
Joerg Roedel46277b72011-12-07 14:34:02 +0100208 PCI_EXT_CAP_ID_PRI,
209 PCI_EXT_CAP_ID_PASID,
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100210 };
211 int i, pos;
212
213 for (i = 0; i < 3; ++i) {
214 pos = pci_find_ext_capability(pdev, caps[i]);
215 if (pos == 0)
216 return false;
217 }
218
219 return true;
220}
221
Joerg Roedel6a113dd2011-12-01 12:04:58 +0100222static bool pdev_pri_erratum(struct pci_dev *pdev, u32 erratum)
223{
224 struct iommu_dev_data *dev_data;
225
226 dev_data = get_dev_data(&pdev->dev);
227
228 return dev_data->errata & (1 << erratum) ? true : false;
229}
230
Joerg Roedel71c70982009-11-24 16:43:06 +0100231/*
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200232 * This function actually applies the mapping to the page table of the
233 * dma_ops domain.
Joerg Roedel71c70982009-11-24 16:43:06 +0100234 */
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200235static void alloc_unity_mapping(struct dma_ops_domain *dma_dom,
236 struct unity_map_entry *e)
Joerg Roedel71c70982009-11-24 16:43:06 +0100237{
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200238 u64 addr;
Joerg Roedel71c70982009-11-24 16:43:06 +0100239
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200240 for (addr = e->address_start; addr < e->address_end;
241 addr += PAGE_SIZE) {
242 if (addr < dma_dom->aperture_size)
243 __set_bit(addr >> PAGE_SHIFT,
244 dma_dom->aperture[0]->bitmap);
Joerg Roedel71c70982009-11-24 16:43:06 +0100245 }
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200246}
Joerg Roedel71c70982009-11-24 16:43:06 +0100247
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200248/*
249 * Inits the unity mappings required for a specific device
250 */
251static void init_unity_mappings_for_device(struct device *dev,
252 struct dma_ops_domain *dma_dom)
253{
254 struct unity_map_entry *e;
255 u16 devid;
Joerg Roedel71c70982009-11-24 16:43:06 +0100256
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200257 devid = get_device_id(dev);
258
259 list_for_each_entry(e, &amd_iommu_unity_map, list) {
260 if (!(devid >= e->devid_start && devid <= e->devid_end))
261 continue;
262 alloc_unity_mapping(dma_dom, e);
263 }
Joerg Roedel71c70982009-11-24 16:43:06 +0100264}
265
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100266/*
267 * This function checks if the driver got a valid device from the caller to
268 * avoid dereferencing invalid pointers.
269 */
270static bool check_device(struct device *dev)
271{
272 u16 devid;
273
274 if (!dev || !dev->dma_mask)
275 return false;
276
Yijing Wangb82a2272013-12-05 19:42:41 +0800277 /* No PCI device */
278 if (!dev_is_pci(dev))
Joerg Roedel98fc5a62009-11-24 17:19:23 +0100279 return false;
280
281 devid = get_device_id(dev);
282
283 /* Out of our scope? */
284 if (devid > amd_iommu_last_bdf)
285 return false;
286
287 if (amd_iommu_rlookup_table[devid] == NULL)
288 return false;
289
290 return true;
291}
292
Alex Williamson25b11ce2014-09-19 10:03:13 -0600293static void init_iommu_group(struct device *dev)
Alex Williamson2851db22012-10-08 22:49:41 -0600294{
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200295 struct dma_ops_domain *dma_domain;
296 struct iommu_domain *domain;
Alex Williamson2851db22012-10-08 22:49:41 -0600297 struct iommu_group *group;
Alex Williamson2851db22012-10-08 22:49:41 -0600298
Alex Williamson65d53522014-07-03 09:51:30 -0600299 group = iommu_group_get_for_dev(dev);
Joerg Roedel0bb6e242015-05-28 18:41:40 +0200300 if (IS_ERR(group))
301 return;
302
303 domain = iommu_group_default_domain(group);
304 if (!domain)
305 goto out;
306
307 dma_domain = to_pdomain(domain)->priv;
308
309 init_unity_mappings_for_device(dev, dma_domain);
310out:
311 iommu_group_put(group);
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600312}
313
Alex Williamsonc1931092014-07-03 09:51:24 -0600314static int __last_alias(struct pci_dev *pdev, u16 alias, void *data)
315{
316 *(u16 *)data = alias;
317 return 0;
318}
319
320static u16 get_alias(struct device *dev)
321{
322 struct pci_dev *pdev = to_pci_dev(dev);
323 u16 devid, ivrs_alias, pci_alias;
324
325 devid = get_device_id(dev);
326 ivrs_alias = amd_iommu_alias_table[devid];
327 pci_for_each_dma_alias(pdev, __last_alias, &pci_alias);
328
329 if (ivrs_alias == pci_alias)
330 return ivrs_alias;
331
332 /*
333 * DMA alias showdown
334 *
335 * The IVRS is fairly reliable in telling us about aliases, but it
336 * can't know about every screwy device. If we don't have an IVRS
337 * reported alias, use the PCI reported alias. In that case we may
338 * still need to initialize the rlookup and dev_table entries if the
339 * alias is to a non-existent device.
340 */
341 if (ivrs_alias == devid) {
342 if (!amd_iommu_rlookup_table[pci_alias]) {
343 amd_iommu_rlookup_table[pci_alias] =
344 amd_iommu_rlookup_table[devid];
345 memcpy(amd_iommu_dev_table[pci_alias].data,
346 amd_iommu_dev_table[devid].data,
347 sizeof(amd_iommu_dev_table[pci_alias].data));
348 }
349
350 return pci_alias;
351 }
352
353 pr_info("AMD-Vi: Using IVRS reported alias %02x:%02x.%d "
354 "for device %s[%04x:%04x], kernel reported alias "
355 "%02x:%02x.%d\n", PCI_BUS_NUM(ivrs_alias), PCI_SLOT(ivrs_alias),
356 PCI_FUNC(ivrs_alias), dev_name(dev), pdev->vendor, pdev->device,
357 PCI_BUS_NUM(pci_alias), PCI_SLOT(pci_alias),
358 PCI_FUNC(pci_alias));
359
360 /*
361 * If we don't have a PCI DMA alias and the IVRS alias is on the same
362 * bus, then the IVRS table may know about a quirk that we don't.
363 */
364 if (pci_alias == devid &&
365 PCI_BUS_NUM(ivrs_alias) == pdev->bus->number) {
366 pdev->dev_flags |= PCI_DEV_FLAGS_DMA_ALIAS_DEVFN;
367 pdev->dma_alias_devfn = ivrs_alias & 0xff;
368 pr_info("AMD-Vi: Added PCI DMA alias %02x.%d for %s\n",
369 PCI_SLOT(ivrs_alias), PCI_FUNC(ivrs_alias),
370 dev_name(dev));
371 }
372
373 return ivrs_alias;
374}
375
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600376static int iommu_init_device(struct device *dev)
377{
378 struct pci_dev *pdev = to_pci_dev(dev);
379 struct iommu_dev_data *dev_data;
380 u16 alias;
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600381
382 if (dev->archdata.iommu)
383 return 0;
384
385 dev_data = find_dev_data(get_device_id(dev));
386 if (!dev_data)
387 return -ENOMEM;
388
Alex Williamsonc1931092014-07-03 09:51:24 -0600389 alias = get_alias(dev);
390
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600391 if (alias != dev_data->devid) {
392 struct iommu_dev_data *alias_data;
393
394 alias_data = find_dev_data(alias);
395 if (alias_data == NULL) {
396 pr_err("AMD-Vi: Warning: Unhandled device %s\n",
397 dev_name(dev));
398 free_dev_data(dev_data);
399 return -ENOTSUPP;
400 }
401 dev_data->alias_data = alias_data;
Alex Williamsoneb9c9522012-10-08 22:49:35 -0600402
Joerg Roedelf251e182014-08-05 16:48:10 +0200403 /* Add device to the alias_list */
404 list_add(&dev_data->alias_list, &alias_data->alias_list);
Radmila Kompováe644a012013-05-02 17:24:25 +0200405 }
Alex Williamson9dcd6132012-05-30 14:19:07 -0600406
Joerg Roedel5abcdba2011-12-01 15:49:45 +0100407 if (pci_iommuv2_capable(pdev)) {
408 struct amd_iommu *iommu;
409
410 iommu = amd_iommu_rlookup_table[dev_data->devid];
411 dev_data->iommu_v2 = iommu->is_iommu_v2;
412 }
413
Joerg Roedel657cbb62009-11-23 15:26:46 +0100414 dev->archdata.iommu = dev_data;
415
Alex Williamson066f2e92014-06-12 16:12:37 -0600416 iommu_device_link(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
417 dev);
418
Joerg Roedel657cbb62009-11-23 15:26:46 +0100419 return 0;
420}
421
Joerg Roedel26018872011-06-06 16:50:14 +0200422static void iommu_ignore_device(struct device *dev)
423{
424 u16 devid, alias;
425
426 devid = get_device_id(dev);
427 alias = amd_iommu_alias_table[devid];
428
429 memset(&amd_iommu_dev_table[devid], 0, sizeof(struct dev_table_entry));
430 memset(&amd_iommu_dev_table[alias], 0, sizeof(struct dev_table_entry));
431
432 amd_iommu_rlookup_table[devid] = NULL;
433 amd_iommu_rlookup_table[alias] = NULL;
434}
435
Joerg Roedel657cbb62009-11-23 15:26:46 +0100436static void iommu_uninit_device(struct device *dev)
437{
Alex Williamsonc1931092014-07-03 09:51:24 -0600438 struct iommu_dev_data *dev_data = search_dev_data(get_device_id(dev));
439
440 if (!dev_data)
441 return;
442
Alex Williamson066f2e92014-06-12 16:12:37 -0600443 iommu_device_unlink(amd_iommu_rlookup_table[dev_data->devid]->iommu_dev,
444 dev);
445
Alex Williamson9dcd6132012-05-30 14:19:07 -0600446 iommu_group_remove_device(dev);
447
Alex Williamsonc1931092014-07-03 09:51:24 -0600448 /* Unlink from alias, it may change if another device is re-plugged */
449 dev_data->alias_data = NULL;
450
Joerg Roedelaafd8ba2015-05-28 18:41:39 +0200451 /* Remove dma-ops */
452 dev->archdata.dma_ops = NULL;
453
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200454 /*
Alex Williamsonc1931092014-07-03 09:51:24 -0600455 * We keep dev_data around for unplugged devices and reuse it when the
456 * device is re-plugged - not doing so would introduce a ton of races.
Joerg Roedel8fa5f802011-06-09 12:24:45 +0200457 */
Joerg Roedel657cbb62009-11-23 15:26:46 +0100458}
Joerg Roedelb7cc9552009-12-10 11:03:39 +0100459
Joerg Roedel7f265082008-12-12 13:50:21 +0100460#ifdef CONFIG_AMD_IOMMU_STATS
461
462/*
463 * Initialization code for statistics collection
464 */
465
Joerg Roedelda49f6d2008-12-12 14:59:58 +0100466DECLARE_STATS_COUNTER(compl_wait);
Joerg Roedel0f2a86f2008-12-12 15:05:16 +0100467DECLARE_STATS_COUNTER(cnt_map_single);
Joerg Roedel146a6912008-12-12 15:07:12 +0100468DECLARE_STATS_COUNTER(cnt_unmap_single);
Joerg Roedeld03f067a2008-12-12 15:09:48 +0100469DECLARE_STATS_COUNTER(cnt_map_sg);
Joerg Roedel55877a62008-12-12 15:12:14 +0100470DECLARE_STATS_COUNTER(cnt_unmap_sg);
Joerg Roedelc8f0fb32008-12-12 15:14:21 +0100471DECLARE_STATS_COUNTER(cnt_alloc_coherent);
Joerg Roedel5d31ee72008-12-12 15:16:38 +0100472DECLARE_STATS_COUNTER(cnt_free_coherent);
Joerg Roedelc1858972008-12-12 15:42:39 +0100473DECLARE_STATS_COUNTER(cross_page);
Joerg Roedelf57d98a2008-12-12 15:46:29 +0100474DECLARE_STATS_COUNTER(domain_flush_single);
Joerg Roedel18811f52008-12-12 15:48:28 +0100475DECLARE_STATS_COUNTER(domain_flush_all);
Joerg Roedel5774f7c2008-12-12 15:57:30 +0100476DECLARE_STATS_COUNTER(alloced_io_mem);
Joerg Roedel8ecaf8f2008-12-12 16:13:04 +0100477DECLARE_STATS_COUNTER(total_map_requests);
Joerg Roedel399be2f2011-12-01 16:53:47 +0100478DECLARE_STATS_COUNTER(complete_ppr);
479DECLARE_STATS_COUNTER(invalidate_iotlb);
480DECLARE_STATS_COUNTER(invalidate_iotlb_all);
481DECLARE_STATS_COUNTER(pri_requests);
482
Joerg Roedel7f265082008-12-12 13:50:21 +0100483static struct dentry *stats_dir;
Joerg Roedel7f265082008-12-12 13:50:21 +0100484static struct dentry *de_fflush;
485
486static void amd_iommu_stats_add(struct __iommu_counter *cnt)
487{
488 if (stats_dir == NULL)
489 return;
490
491 cnt->dent = debugfs_create_u64(cnt->name, 0444, stats_dir,
492 &cnt->value);
493}
494
495static void amd_iommu_stats_init(void)
496{
497 stats_dir = debugfs_create_dir("amd-iommu", NULL);
498 if (stats_dir == NULL)
499 return;
500
Joerg Roedel7f265082008-12-12 13:50:21 +0100501 de_fflush = debugfs_create_bool("fullflush", 0444, stats_dir,
Dan Carpenter3775d482012-06-27 12:09:18 +0300502 &amd_iommu_unmap_flush);
Joerg Roedelda49f6d2008-12-12 14:59:58 +0100503
504 amd_iommu_stats_add(&compl_wait);
Joerg Roedel0f2a86f2008-12-12 15:05:16 +0100505 amd_iommu_stats_add(&cnt_map_single);
Joerg Roedel146a6912008-12-12 15:07:12 +0100506 amd_iommu_stats_add(&cnt_unmap_single);
Joerg Roedeld03f067a2008-12-12 15:09:48 +0100507 amd_iommu_stats_add(&cnt_map_sg);
Joerg Roedel55877a62008-12-12 15:12:14 +0100508 amd_iommu_stats_add(&cnt_unmap_sg);
Joerg Roedelc8f0fb32008-12-12 15:14:21 +0100509 amd_iommu_stats_add(&cnt_alloc_coherent);
Joerg Roedel5d31ee72008-12-12 15:16:38 +0100510 amd_iommu_stats_add(&cnt_free_coherent);
Joerg Roedelc1858972008-12-12 15:42:39 +0100511 amd_iommu_stats_add(&cross_page);
Joerg Roedelf57d98a2008-12-12 15:46:29 +0100512 amd_iommu_stats_add(&domain_flush_single);
Joerg Roedel18811f52008-12-12 15:48:28 +0100513 amd_iommu_stats_add(&domain_flush_all);
Joerg Roedel5774f7c2008-12-12 15:57:30 +0100514 amd_iommu_stats_add(&alloced_io_mem);
Joerg Roedel8ecaf8f2008-12-12 16:13:04 +0100515 amd_iommu_stats_add(&total_map_requests);
Joerg Roedel399be2f2011-12-01 16:53:47 +0100516 amd_iommu_stats_add(&complete_ppr);
517 amd_iommu_stats_add(&invalidate_iotlb);
518 amd_iommu_stats_add(&invalidate_iotlb_all);
519 amd_iommu_stats_add(&pri_requests);
Joerg Roedel7f265082008-12-12 13:50:21 +0100520}
521
522#endif
523
Joerg Roedel431b2a22008-07-11 17:14:22 +0200524/****************************************************************************
525 *
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200526 * Interrupt handling functions
527 *
528 ****************************************************************************/
529
Joerg Roedele3e59872009-09-03 14:02:10 +0200530static void dump_dte_entry(u16 devid)
531{
532 int i;
533
Joerg Roedelee6c2862011-11-09 12:06:03 +0100534 for (i = 0; i < 4; ++i)
535 pr_err("AMD-Vi: DTE[%d]: %016llx\n", i,
Joerg Roedele3e59872009-09-03 14:02:10 +0200536 amd_iommu_dev_table[devid].data[i]);
537}
538
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200539static void dump_command(unsigned long phys_addr)
540{
541 struct iommu_cmd *cmd = phys_to_virt(phys_addr);
542 int i;
543
544 for (i = 0; i < 4; ++i)
545 pr_err("AMD-Vi: CMD[%d]: %08x\n", i, cmd->data[i]);
546}
547
Joerg Roedela345b232009-09-03 15:01:43 +0200548static void iommu_print_event(struct amd_iommu *iommu, void *__evt)
Joerg Roedel90008ee2008-09-09 16:41:05 +0200549{
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200550 int type, devid, domid, flags;
551 volatile u32 *event = __evt;
552 int count = 0;
553 u64 address;
554
555retry:
556 type = (event[1] >> EVENT_TYPE_SHIFT) & EVENT_TYPE_MASK;
557 devid = (event[0] >> EVENT_DEVID_SHIFT) & EVENT_DEVID_MASK;
558 domid = (event[1] >> EVENT_DOMID_SHIFT) & EVENT_DOMID_MASK;
559 flags = (event[1] >> EVENT_FLAGS_SHIFT) & EVENT_FLAGS_MASK;
560 address = (u64)(((u64)event[3]) << 32) | event[2];
561
562 if (type == 0) {
563 /* Did we hit the erratum? */
564 if (++count == LOOP_TIMEOUT) {
565 pr_err("AMD-Vi: No event written to event log\n");
566 return;
567 }
568 udelay(1);
569 goto retry;
570 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200571
Joerg Roedel4c6f40d2009-09-01 16:43:58 +0200572 printk(KERN_ERR "AMD-Vi: Event logged [");
Joerg Roedel90008ee2008-09-09 16:41:05 +0200573
574 switch (type) {
575 case EVENT_TYPE_ILL_DEV:
576 printk("ILLEGAL_DEV_TABLE_ENTRY device=%02x:%02x.%x "
577 "address=0x%016llx flags=0x%04x]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700578 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200579 address, flags);
Joerg Roedele3e59872009-09-03 14:02:10 +0200580 dump_dte_entry(devid);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200581 break;
582 case EVENT_TYPE_IO_FAULT:
583 printk("IO_PAGE_FAULT device=%02x:%02x.%x "
584 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700585 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200586 domid, address, flags);
587 break;
588 case EVENT_TYPE_DEV_TAB_ERR:
589 printk("DEV_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
590 "address=0x%016llx flags=0x%04x]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700591 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200592 address, flags);
593 break;
594 case EVENT_TYPE_PAGE_TAB_ERR:
595 printk("PAGE_TAB_HARDWARE_ERROR device=%02x:%02x.%x "
596 "domain=0x%04x address=0x%016llx flags=0x%04x]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700597 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200598 domid, address, flags);
599 break;
600 case EVENT_TYPE_ILL_CMD:
601 printk("ILLEGAL_COMMAND_ERROR address=0x%016llx]\n", address);
Joerg Roedel945b4ac2009-09-03 14:25:02 +0200602 dump_command(address);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200603 break;
604 case EVENT_TYPE_CMD_HARD_ERR:
605 printk("COMMAND_HARDWARE_ERROR address=0x%016llx "
606 "flags=0x%04x]\n", address, flags);
607 break;
608 case EVENT_TYPE_IOTLB_INV_TO:
609 printk("IOTLB_INV_TIMEOUT device=%02x:%02x.%x "
610 "address=0x%016llx]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700611 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200612 address);
613 break;
614 case EVENT_TYPE_INV_DEV_REQ:
615 printk("INVALID_DEVICE_REQUEST device=%02x:%02x.%x "
616 "address=0x%016llx flags=0x%04x]\n",
Shuah Khanc5081cd2013-02-27 17:07:19 -0700617 PCI_BUS_NUM(devid), PCI_SLOT(devid), PCI_FUNC(devid),
Joerg Roedel90008ee2008-09-09 16:41:05 +0200618 address, flags);
619 break;
620 default:
621 printk(KERN_ERR "UNKNOWN type=0x%02x]\n", type);
622 }
Joerg Roedel3d06fca2012-04-12 14:12:00 +0200623
624 memset(__evt, 0, 4 * sizeof(u32));
Joerg Roedel90008ee2008-09-09 16:41:05 +0200625}
626
627static void iommu_poll_events(struct amd_iommu *iommu)
628{
629 u32 head, tail;
Joerg Roedel90008ee2008-09-09 16:41:05 +0200630
631 head = readl(iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
632 tail = readl(iommu->mmio_base + MMIO_EVT_TAIL_OFFSET);
633
634 while (head != tail) {
Joerg Roedela345b232009-09-03 15:01:43 +0200635 iommu_print_event(iommu, iommu->evt_buf + head);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200636 head = (head + EVENT_ENTRY_SIZE) % iommu->evt_buf_size;
637 }
638
639 writel(head, iommu->mmio_base + MMIO_EVT_HEAD_OFFSET);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200640}
641
Joerg Roedeleee53532012-06-01 15:20:23 +0200642static void iommu_handle_ppr_entry(struct amd_iommu *iommu, u64 *raw)
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100643{
644 struct amd_iommu_fault fault;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100645
Joerg Roedel399be2f2011-12-01 16:53:47 +0100646 INC_STATS_COUNTER(pri_requests);
647
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100648 if (PPR_REQ_TYPE(raw[0]) != PPR_REQ_FAULT) {
649 pr_err_ratelimited("AMD-Vi: Unknown PPR request received\n");
650 return;
651 }
652
653 fault.address = raw[1];
654 fault.pasid = PPR_PASID(raw[0]);
655 fault.device_id = PPR_DEVID(raw[0]);
656 fault.tag = PPR_TAG(raw[0]);
657 fault.flags = PPR_FLAGS(raw[0]);
658
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100659 atomic_notifier_call_chain(&ppr_notifier, 0, &fault);
660}
661
662static void iommu_poll_ppr_log(struct amd_iommu *iommu)
663{
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100664 u32 head, tail;
665
666 if (iommu->ppr_log == NULL)
667 return;
668
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100669 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
670 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
671
672 while (head != tail) {
Joerg Roedeleee53532012-06-01 15:20:23 +0200673 volatile u64 *raw;
674 u64 entry[2];
675 int i;
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100676
Joerg Roedeleee53532012-06-01 15:20:23 +0200677 raw = (u64 *)(iommu->ppr_log + head);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100678
Joerg Roedeleee53532012-06-01 15:20:23 +0200679 /*
680 * Hardware bug: Interrupt may arrive before the entry is
681 * written to memory. If this happens we need to wait for the
682 * entry to arrive.
683 */
684 for (i = 0; i < LOOP_TIMEOUT; ++i) {
685 if (PPR_REQ_TYPE(raw[0]) != 0)
686 break;
687 udelay(1);
688 }
689
690 /* Avoid memcpy function-call overhead */
691 entry[0] = raw[0];
692 entry[1] = raw[1];
693
694 /*
695 * To detect the hardware bug we need to clear the entry
696 * back to zero.
697 */
698 raw[0] = raw[1] = 0UL;
699
700 /* Update head pointer of hardware ring-buffer */
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100701 head = (head + PPR_ENTRY_SIZE) % PPR_LOG_SIZE;
702 writel(head, iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
Joerg Roedeleee53532012-06-01 15:20:23 +0200703
Joerg Roedeleee53532012-06-01 15:20:23 +0200704 /* Handle PPR entry */
705 iommu_handle_ppr_entry(iommu, entry);
706
Joerg Roedeleee53532012-06-01 15:20:23 +0200707 /* Refresh ring-buffer information */
708 head = readl(iommu->mmio_base + MMIO_PPR_HEAD_OFFSET);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100709 tail = readl(iommu->mmio_base + MMIO_PPR_TAIL_OFFSET);
710 }
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100711}
712
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200713irqreturn_t amd_iommu_int_thread(int irq, void *data)
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200714{
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -0500715 struct amd_iommu *iommu = (struct amd_iommu *) data;
716 u32 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
Joerg Roedel90008ee2008-09-09 16:41:05 +0200717
Suravee Suthikulpanit3f398bc2013-04-22 16:32:34 -0500718 while (status & (MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK)) {
719 /* Enable EVT and PPR interrupts again */
720 writel((MMIO_STATUS_EVT_INT_MASK | MMIO_STATUS_PPR_INT_MASK),
721 iommu->mmio_base + MMIO_STATUS_OFFSET);
722
723 if (status & MMIO_STATUS_EVT_INT_MASK) {
724 pr_devel("AMD-Vi: Processing IOMMU Event Log\n");
725 iommu_poll_events(iommu);
726 }
727
728 if (status & MMIO_STATUS_PPR_INT_MASK) {
729 pr_devel("AMD-Vi: Processing IOMMU PPR Log\n");
730 iommu_poll_ppr_log(iommu);
731 }
732
733 /*
734 * Hardware bug: ERBT1312
735 * When re-enabling interrupt (by writing 1
736 * to clear the bit), the hardware might also try to set
737 * the interrupt bit in the event status register.
738 * In this scenario, the bit will be set, and disable
739 * subsequent interrupts.
740 *
741 * Workaround: The IOMMU driver should read back the
742 * status register and check if the interrupt bits are cleared.
743 * If not, driver will need to go through the interrupt handler
744 * again and re-clear the bits
745 */
746 status = readl(iommu->mmio_base + MMIO_STATUS_OFFSET);
Joerg Roedel72e1dcc2011-11-10 19:13:51 +0100747 }
Joerg Roedel90008ee2008-09-09 16:41:05 +0200748 return IRQ_HANDLED;
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200749}
750
Joerg Roedel72fe00f2011-05-10 10:50:42 +0200751irqreturn_t amd_iommu_int_handler(int irq, void *data)
752{
753 return IRQ_WAKE_THREAD;
754}
755
Joerg Roedela80dc3e2008-09-11 16:51:41 +0200756/****************************************************************************
757 *
Joerg Roedel431b2a22008-07-11 17:14:22 +0200758 * IOMMU command queuing functions
759 *
760 ****************************************************************************/
761
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200762static int wait_on_sem(volatile u64 *sem)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200763{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200764 int i = 0;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200765
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200766 while (*sem == 0 && i < LOOP_TIMEOUT) {
767 udelay(1);
768 i += 1;
769 }
770
771 if (i == LOOP_TIMEOUT) {
772 pr_alert("AMD-Vi: Completion-Wait loop timed out\n");
773 return -EIO;
774 }
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200775
776 return 0;
777}
778
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200779static void copy_cmd_to_buffer(struct amd_iommu *iommu,
780 struct iommu_cmd *cmd,
781 u32 tail)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200782{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200783 u8 *target;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200784
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200785 target = iommu->cmd_buf + tail;
786 tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200787
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200788 /* Copy command to buffer */
789 memcpy(target, cmd, sizeof(*cmd));
790
791 /* Tell the IOMMU about it */
792 writel(tail, iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
793}
794
Joerg Roedel815b33f2011-04-06 17:26:49 +0200795static void build_completion_wait(struct iommu_cmd *cmd, u64 address)
Joerg Roedelded46732011-04-06 10:53:48 +0200796{
Joerg Roedel815b33f2011-04-06 17:26:49 +0200797 WARN_ON(address & 0x7ULL);
798
Joerg Roedelded46732011-04-06 10:53:48 +0200799 memset(cmd, 0, sizeof(*cmd));
Joerg Roedel815b33f2011-04-06 17:26:49 +0200800 cmd->data[0] = lower_32_bits(__pa(address)) | CMD_COMPL_WAIT_STORE_MASK;
801 cmd->data[1] = upper_32_bits(__pa(address));
802 cmd->data[2] = 1;
Joerg Roedelded46732011-04-06 10:53:48 +0200803 CMD_SET_TYPE(cmd, CMD_COMPL_WAIT);
804}
805
Joerg Roedel94fe79e2011-04-06 11:07:21 +0200806static void build_inv_dte(struct iommu_cmd *cmd, u16 devid)
807{
808 memset(cmd, 0, sizeof(*cmd));
809 cmd->data[0] = devid;
810 CMD_SET_TYPE(cmd, CMD_INV_DEV_ENTRY);
811}
812
Joerg Roedel11b64022011-04-06 11:49:28 +0200813static void build_inv_iommu_pages(struct iommu_cmd *cmd, u64 address,
814 size_t size, u16 domid, int pde)
815{
816 u64 pages;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100817 bool s;
Joerg Roedel11b64022011-04-06 11:49:28 +0200818
819 pages = iommu_num_pages(address, size, PAGE_SIZE);
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100820 s = false;
Joerg Roedel11b64022011-04-06 11:49:28 +0200821
822 if (pages > 1) {
823 /*
824 * If we have to flush more than one page, flush all
825 * TLB entries for this domain
826 */
827 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100828 s = true;
Joerg Roedel11b64022011-04-06 11:49:28 +0200829 }
830
831 address &= PAGE_MASK;
832
833 memset(cmd, 0, sizeof(*cmd));
834 cmd->data[1] |= domid;
835 cmd->data[2] = lower_32_bits(address);
836 cmd->data[3] = upper_32_bits(address);
837 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
838 if (s) /* size bit - we flush more than one 4kb page */
839 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
Frank Arnolddf805ab2012-08-27 19:21:04 +0200840 if (pde) /* PDE bit - we want to flush everything, not only the PTEs */
Joerg Roedel11b64022011-04-06 11:49:28 +0200841 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
842}
843
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200844static void build_inv_iotlb_pages(struct iommu_cmd *cmd, u16 devid, int qdep,
845 u64 address, size_t size)
846{
847 u64 pages;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100848 bool s;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200849
850 pages = iommu_num_pages(address, size, PAGE_SIZE);
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100851 s = false;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200852
853 if (pages > 1) {
854 /*
855 * If we have to flush more than one page, flush all
856 * TLB entries for this domain
857 */
858 address = CMD_INV_IOMMU_ALL_PAGES_ADDRESS;
Quentin Lambertae0cbbb2015-02-04 11:40:07 +0100859 s = true;
Joerg Roedelcb41ed82011-04-05 11:00:53 +0200860 }
861
862 address &= PAGE_MASK;
863
864 memset(cmd, 0, sizeof(*cmd));
865 cmd->data[0] = devid;
866 cmd->data[0] |= (qdep & 0xff) << 24;
867 cmd->data[1] = devid;
868 cmd->data[2] = lower_32_bits(address);
869 cmd->data[3] = upper_32_bits(address);
870 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
871 if (s)
872 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
873}
874
Joerg Roedel22e266c2011-11-21 15:59:08 +0100875static void build_inv_iommu_pasid(struct iommu_cmd *cmd, u16 domid, int pasid,
876 u64 address, bool size)
877{
878 memset(cmd, 0, sizeof(*cmd));
879
880 address &= ~(0xfffULL);
881
Suravee Suthikulpanita919a012014-03-05 18:54:18 -0600882 cmd->data[0] = pasid;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100883 cmd->data[1] = domid;
884 cmd->data[2] = lower_32_bits(address);
885 cmd->data[3] = upper_32_bits(address);
886 cmd->data[2] |= CMD_INV_IOMMU_PAGES_PDE_MASK;
887 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
888 if (size)
889 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
890 CMD_SET_TYPE(cmd, CMD_INV_IOMMU_PAGES);
891}
892
893static void build_inv_iotlb_pasid(struct iommu_cmd *cmd, u16 devid, int pasid,
894 int qdep, u64 address, bool size)
895{
896 memset(cmd, 0, sizeof(*cmd));
897
898 address &= ~(0xfffULL);
899
900 cmd->data[0] = devid;
Jay Cornwalle8d2d822014-02-26 15:49:31 -0600901 cmd->data[0] |= ((pasid >> 8) & 0xff) << 16;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100902 cmd->data[0] |= (qdep & 0xff) << 24;
903 cmd->data[1] = devid;
Jay Cornwalle8d2d822014-02-26 15:49:31 -0600904 cmd->data[1] |= (pasid & 0xff) << 16;
Joerg Roedel22e266c2011-11-21 15:59:08 +0100905 cmd->data[2] = lower_32_bits(address);
906 cmd->data[2] |= CMD_INV_IOMMU_PAGES_GN_MASK;
907 cmd->data[3] = upper_32_bits(address);
908 if (size)
909 cmd->data[2] |= CMD_INV_IOMMU_PAGES_SIZE_MASK;
910 CMD_SET_TYPE(cmd, CMD_INV_IOTLB_PAGES);
911}
912
Joerg Roedelc99afa22011-11-21 18:19:25 +0100913static void build_complete_ppr(struct iommu_cmd *cmd, u16 devid, int pasid,
914 int status, int tag, bool gn)
915{
916 memset(cmd, 0, sizeof(*cmd));
917
918 cmd->data[0] = devid;
919 if (gn) {
Suravee Suthikulpanita919a012014-03-05 18:54:18 -0600920 cmd->data[1] = pasid;
Joerg Roedelc99afa22011-11-21 18:19:25 +0100921 cmd->data[2] = CMD_INV_IOMMU_PAGES_GN_MASK;
922 }
923 cmd->data[3] = tag & 0x1ff;
924 cmd->data[3] |= (status & PPR_STATUS_MASK) << PPR_STATUS_SHIFT;
925
926 CMD_SET_TYPE(cmd, CMD_COMPLETE_PPR);
927}
928
Joerg Roedel58fc7f12011-04-11 11:13:24 +0200929static void build_inv_all(struct iommu_cmd *cmd)
930{
931 memset(cmd, 0, sizeof(*cmd));
932 CMD_SET_TYPE(cmd, CMD_INV_ALL);
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200933}
934
Joerg Roedel7ef27982012-06-21 16:46:04 +0200935static void build_inv_irt(struct iommu_cmd *cmd, u16 devid)
936{
937 memset(cmd, 0, sizeof(*cmd));
938 cmd->data[0] = devid;
939 CMD_SET_TYPE(cmd, CMD_INV_IRT);
940}
941
Joerg Roedel431b2a22008-07-11 17:14:22 +0200942/*
Joerg Roedelb6c02712008-06-26 21:27:53 +0200943 * Writes the command to the IOMMUs command buffer and informs the
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200944 * hardware about the new command.
Joerg Roedel431b2a22008-07-11 17:14:22 +0200945 */
Joerg Roedelf1ca1512011-09-02 14:10:32 +0200946static int iommu_queue_command_sync(struct amd_iommu *iommu,
947 struct iommu_cmd *cmd,
948 bool sync)
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200949{
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200950 u32 left, tail, head, next_tail;
Joerg Roedel815b33f2011-04-06 17:26:49 +0200951 unsigned long flags;
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200952
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200953 WARN_ON(iommu->cmd_buf_size & CMD_BUFFER_UNINITIALIZED);
Joerg Roedelda49f6d2008-12-12 14:59:58 +0100954
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200955again:
Joerg Roedel815b33f2011-04-06 17:26:49 +0200956 spin_lock_irqsave(&iommu->lock, flags);
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200957
958 head = readl(iommu->mmio_base + MMIO_CMD_HEAD_OFFSET);
959 tail = readl(iommu->mmio_base + MMIO_CMD_TAIL_OFFSET);
960 next_tail = (tail + sizeof(*cmd)) % iommu->cmd_buf_size;
961 left = (head - next_tail) % iommu->cmd_buf_size;
962
963 if (left <= 2) {
964 struct iommu_cmd sync_cmd;
965 volatile u64 sem = 0;
966 int ret;
967
968 build_completion_wait(&sync_cmd, (u64)&sem);
969 copy_cmd_to_buffer(iommu, &sync_cmd, tail);
970
971 spin_unlock_irqrestore(&iommu->lock, flags);
972
973 if ((ret = wait_on_sem(&sem)) != 0)
974 return ret;
975
976 goto again;
Joerg Roedel136f78a2008-07-11 17:14:27 +0200977 }
978
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200979 copy_cmd_to_buffer(iommu, cmd, tail);
Joerg Roedel519c31b2008-08-14 19:55:15 +0200980
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200981 /* We need to sync now to make sure all commands are processed */
Joerg Roedelf1ca1512011-09-02 14:10:32 +0200982 iommu->need_sync = sync;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +0200983
Joerg Roedela19ae1e2008-06-26 21:27:55 +0200984 spin_unlock_irqrestore(&iommu->lock, flags);
985
Joerg Roedel815b33f2011-04-06 17:26:49 +0200986 return 0;
Joerg Roedel8d201962008-12-02 20:34:41 +0100987}
988
Joerg Roedelf1ca1512011-09-02 14:10:32 +0200989static int iommu_queue_command(struct amd_iommu *iommu, struct iommu_cmd *cmd)
990{
991 return iommu_queue_command_sync(iommu, cmd, true);
992}
993
Joerg Roedel8d201962008-12-02 20:34:41 +0100994/*
995 * This function queues a completion wait command into the command
996 * buffer of an IOMMU
997 */
Joerg Roedel8d201962008-12-02 20:34:41 +0100998static int iommu_completion_wait(struct amd_iommu *iommu)
999{
Joerg Roedel815b33f2011-04-06 17:26:49 +02001000 struct iommu_cmd cmd;
1001 volatile u64 sem = 0;
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001002 int ret;
Joerg Roedel8d201962008-12-02 20:34:41 +01001003
1004 if (!iommu->need_sync)
Joerg Roedel815b33f2011-04-06 17:26:49 +02001005 return 0;
Joerg Roedel8d201962008-12-02 20:34:41 +01001006
Joerg Roedel815b33f2011-04-06 17:26:49 +02001007 build_completion_wait(&cmd, (u64)&sem);
Joerg Roedel8d201962008-12-02 20:34:41 +01001008
Joerg Roedelf1ca1512011-09-02 14:10:32 +02001009 ret = iommu_queue_command_sync(iommu, &cmd, false);
Joerg Roedel8d201962008-12-02 20:34:41 +01001010 if (ret)
Joerg Roedel815b33f2011-04-06 17:26:49 +02001011 return ret;
Joerg Roedel8d201962008-12-02 20:34:41 +01001012
Joerg Roedelac0ea6e2011-04-06 18:38:20 +02001013 return wait_on_sem(&sem);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001014}
1015
Joerg Roedeld8c13082011-04-06 18:51:26 +02001016static int iommu_flush_dte(struct amd_iommu *iommu, u16 devid)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001017{
1018 struct iommu_cmd cmd;
1019
Joerg Roedeld8c13082011-04-06 18:51:26 +02001020 build_inv_dte(&cmd, devid);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001021
Joerg Roedeld8c13082011-04-06 18:51:26 +02001022 return iommu_queue_command(iommu, &cmd);
1023}
1024
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001025static void iommu_flush_dte_all(struct amd_iommu *iommu)
1026{
1027 u32 devid;
1028
1029 for (devid = 0; devid <= 0xffff; ++devid)
1030 iommu_flush_dte(iommu, devid);
1031
1032 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001033}
1034
1035/*
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001036 * This function uses heavy locking and may disable irqs for some time. But
1037 * this is no issue because it is only called during resume.
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001038 */
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001039static void iommu_flush_tlb_all(struct amd_iommu *iommu)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001040{
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001041 u32 dom_id;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001042
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001043 for (dom_id = 0; dom_id <= 0xffff; ++dom_id) {
1044 struct iommu_cmd cmd;
1045 build_inv_iommu_pages(&cmd, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
1046 dom_id, 1);
1047 iommu_queue_command(iommu, &cmd);
1048 }
Joerg Roedel431b2a22008-07-11 17:14:22 +02001049
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001050 iommu_completion_wait(iommu);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001051}
1052
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001053static void iommu_flush_all(struct amd_iommu *iommu)
1054{
1055 struct iommu_cmd cmd;
1056
1057 build_inv_all(&cmd);
1058
1059 iommu_queue_command(iommu, &cmd);
1060 iommu_completion_wait(iommu);
1061}
1062
Joerg Roedel7ef27982012-06-21 16:46:04 +02001063static void iommu_flush_irt(struct amd_iommu *iommu, u16 devid)
1064{
1065 struct iommu_cmd cmd;
1066
1067 build_inv_irt(&cmd, devid);
1068
1069 iommu_queue_command(iommu, &cmd);
1070}
1071
1072static void iommu_flush_irt_all(struct amd_iommu *iommu)
1073{
1074 u32 devid;
1075
1076 for (devid = 0; devid <= MAX_DEV_TABLE_ENTRIES; devid++)
1077 iommu_flush_irt(iommu, devid);
1078
1079 iommu_completion_wait(iommu);
1080}
1081
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001082void iommu_flush_all_caches(struct amd_iommu *iommu)
1083{
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001084 if (iommu_feature(iommu, FEATURE_IA)) {
1085 iommu_flush_all(iommu);
1086 } else {
1087 iommu_flush_dte_all(iommu);
Joerg Roedel7ef27982012-06-21 16:46:04 +02001088 iommu_flush_irt_all(iommu);
Joerg Roedel58fc7f12011-04-11 11:13:24 +02001089 iommu_flush_tlb_all(iommu);
1090 }
Joerg Roedel7d0c5cc2011-04-07 08:16:10 +02001091}
1092
Joerg Roedel431b2a22008-07-11 17:14:22 +02001093/*
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001094 * Command send function for flushing on-device TLB
1095 */
Joerg Roedel6c542042011-06-09 17:07:31 +02001096static int device_flush_iotlb(struct iommu_dev_data *dev_data,
1097 u64 address, size_t size)
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001098{
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001099 struct amd_iommu *iommu;
1100 struct iommu_cmd cmd;
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001101 int qdep;
1102
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001103 qdep = dev_data->ats.qdep;
1104 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001105
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001106 build_inv_iotlb_pages(&cmd, dev_data->devid, qdep, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001107
1108 return iommu_queue_command(iommu, &cmd);
1109}
1110
1111/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001112 * Command send function for invalidating a device table entry
1113 */
Joerg Roedel6c542042011-06-09 17:07:31 +02001114static int device_flush_dte(struct iommu_dev_data *dev_data)
Joerg Roedel3fa43652009-11-26 15:04:38 +01001115{
1116 struct amd_iommu *iommu;
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001117 int ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001118
Joerg Roedel6c542042011-06-09 17:07:31 +02001119 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel3fa43652009-11-26 15:04:38 +01001120
Joerg Roedelf62dda62011-06-09 12:55:35 +02001121 ret = iommu_flush_dte(iommu, dev_data->devid);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001122 if (ret)
1123 return ret;
1124
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001125 if (dev_data->ats.enabled)
Joerg Roedel6c542042011-06-09 17:07:31 +02001126 ret = device_flush_iotlb(dev_data, 0, ~0UL);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001127
1128 return ret;
Joerg Roedel3fa43652009-11-26 15:04:38 +01001129}
1130
Joerg Roedel431b2a22008-07-11 17:14:22 +02001131/*
1132 * TLB invalidation function which is called from the mapping functions.
1133 * It invalidates a single PTE if the range to flush is within a single
1134 * page. Otherwise it flushes the whole TLB of the IOMMU.
1135 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001136static void __domain_flush_pages(struct protection_domain *domain,
1137 u64 address, size_t size, int pde)
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001138{
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001139 struct iommu_dev_data *dev_data;
Joerg Roedel11b64022011-04-06 11:49:28 +02001140 struct iommu_cmd cmd;
1141 int ret = 0, i;
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001142
Joerg Roedel11b64022011-04-06 11:49:28 +02001143 build_inv_iommu_pages(&cmd, address, size, domain->id, pde);
Joerg Roedel999ba412008-07-03 19:35:08 +02001144
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001145 for (i = 0; i < amd_iommus_present; ++i) {
1146 if (!domain->dev_iommu[i])
1147 continue;
1148
1149 /*
1150 * Devices of this domain are behind this IOMMU
1151 * We need a TLB flush
1152 */
Joerg Roedel11b64022011-04-06 11:49:28 +02001153 ret |= iommu_queue_command(amd_iommus[i], &cmd);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001154 }
1155
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001156 list_for_each_entry(dev_data, &domain->dev_list, list) {
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001157
Joerg Roedelea61cdd2011-06-09 12:56:30 +02001158 if (!dev_data->ats.enabled)
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001159 continue;
1160
Joerg Roedel6c542042011-06-09 17:07:31 +02001161 ret |= device_flush_iotlb(dev_data, address, size);
Joerg Roedelcb41ed82011-04-05 11:00:53 +02001162 }
1163
Joerg Roedel11b64022011-04-06 11:49:28 +02001164 WARN_ON(ret);
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001165}
1166
Joerg Roedel17b124b2011-04-06 18:01:35 +02001167static void domain_flush_pages(struct protection_domain *domain,
1168 u64 address, size_t size)
Joerg Roedel6de8ad92009-11-23 18:30:32 +01001169{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001170 __domain_flush_pages(domain, address, size, 0);
Joerg Roedela19ae1e2008-06-26 21:27:55 +02001171}
Joerg Roedelb6c02712008-06-26 21:27:53 +02001172
Joerg Roedel1c655772008-09-04 18:40:05 +02001173/* Flush the whole IO/TLB for a given protection domain */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001174static void domain_flush_tlb(struct protection_domain *domain)
Joerg Roedel1c655772008-09-04 18:40:05 +02001175{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001176 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 0);
Joerg Roedel1c655772008-09-04 18:40:05 +02001177}
1178
Chris Wright42a49f92009-06-15 15:42:00 +02001179/* Flush the whole IO/TLB for a given protection domain - including PDE */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001180static void domain_flush_tlb_pde(struct protection_domain *domain)
Chris Wright42a49f92009-06-15 15:42:00 +02001181{
Joerg Roedel17b124b2011-04-06 18:01:35 +02001182 __domain_flush_pages(domain, 0, CMD_INV_IOMMU_ALL_PAGES_ADDRESS, 1);
1183}
1184
1185static void domain_flush_complete(struct protection_domain *domain)
Joerg Roedelb6c02712008-06-26 21:27:53 +02001186{
1187 int i;
1188
1189 for (i = 0; i < amd_iommus_present; ++i) {
1190 if (!domain->dev_iommu[i])
1191 continue;
1192
1193 /*
1194 * Devices of this domain are behind this IOMMU
1195 * We need to wait for completion of all commands.
1196 */
1197 iommu_completion_wait(amd_iommus[i]);
1198 }
1199}
1200
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001201
Joerg Roedel43f49602008-12-02 21:01:12 +01001202/*
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001203 * This function flushes the DTEs for all devices in domain
Joerg Roedel43f49602008-12-02 21:01:12 +01001204 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02001205static void domain_flush_devices(struct protection_domain *domain)
Joerg Roedelbfd1be12009-05-05 15:33:57 +02001206{
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001207 struct iommu_dev_data *dev_data;
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001208
1209 list_for_each_entry(dev_data, &domain->dev_list, list)
Joerg Roedel6c542042011-06-09 17:07:31 +02001210 device_flush_dte(dev_data);
Joerg Roedelb00d3bc2009-11-26 15:35:33 +01001211}
1212
Joerg Roedel431b2a22008-07-11 17:14:22 +02001213/****************************************************************************
1214 *
1215 * The functions below are used the create the page table mappings for
1216 * unity mapped regions.
1217 *
1218 ****************************************************************************/
1219
1220/*
Joerg Roedel308973d2009-11-24 17:43:32 +01001221 * This function is used to add another level to an IO page table. Adding
1222 * another level increases the size of the address space by 9 bits to a size up
1223 * to 64 bits.
1224 */
1225static bool increase_address_space(struct protection_domain *domain,
1226 gfp_t gfp)
1227{
1228 u64 *pte;
1229
1230 if (domain->mode == PAGE_MODE_6_LEVEL)
1231 /* address space already 64 bit large */
1232 return false;
1233
1234 pte = (void *)get_zeroed_page(gfp);
1235 if (!pte)
1236 return false;
1237
1238 *pte = PM_LEVEL_PDE(domain->mode,
1239 virt_to_phys(domain->pt_root));
1240 domain->pt_root = pte;
1241 domain->mode += 1;
1242 domain->updated = true;
1243
1244 return true;
1245}
1246
1247static u64 *alloc_pte(struct protection_domain *domain,
1248 unsigned long address,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001249 unsigned long page_size,
Joerg Roedel308973d2009-11-24 17:43:32 +01001250 u64 **pte_page,
1251 gfp_t gfp)
1252{
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001253 int level, end_lvl;
Joerg Roedel308973d2009-11-24 17:43:32 +01001254 u64 *pte, *page;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001255
1256 BUG_ON(!is_power_of_2(page_size));
Joerg Roedel308973d2009-11-24 17:43:32 +01001257
1258 while (address > PM_LEVEL_SIZE(domain->mode))
1259 increase_address_space(domain, gfp);
1260
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001261 level = domain->mode - 1;
1262 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1263 address = PAGE_SIZE_ALIGN(address, page_size);
1264 end_lvl = PAGE_SIZE_LEVEL(page_size);
Joerg Roedel308973d2009-11-24 17:43:32 +01001265
1266 while (level > end_lvl) {
1267 if (!IOMMU_PTE_PRESENT(*pte)) {
1268 page = (u64 *)get_zeroed_page(gfp);
1269 if (!page)
1270 return NULL;
1271 *pte = PM_LEVEL_PDE(level, virt_to_phys(page));
1272 }
1273
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001274 /* No level skipping support yet */
1275 if (PM_PTE_LEVEL(*pte) != level)
1276 return NULL;
1277
Joerg Roedel308973d2009-11-24 17:43:32 +01001278 level -= 1;
1279
1280 pte = IOMMU_PTE_PAGE(*pte);
1281
1282 if (pte_page && level == end_lvl)
1283 *pte_page = pte;
1284
1285 pte = &pte[PM_LEVEL_INDEX(level, address)];
1286 }
1287
1288 return pte;
1289}
1290
1291/*
1292 * This function checks if there is a PTE for a given dma address. If
1293 * there is one, it returns the pointer to it.
1294 */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001295static u64 *fetch_pte(struct protection_domain *domain,
1296 unsigned long address,
1297 unsigned long *page_size)
Joerg Roedel308973d2009-11-24 17:43:32 +01001298{
1299 int level;
1300 u64 *pte;
1301
Joerg Roedel24cd7722010-01-19 17:27:39 +01001302 if (address > PM_LEVEL_SIZE(domain->mode))
1303 return NULL;
Joerg Roedel308973d2009-11-24 17:43:32 +01001304
Joerg Roedel3039ca12015-04-01 14:58:48 +02001305 level = domain->mode - 1;
1306 pte = &domain->pt_root[PM_LEVEL_INDEX(level, address)];
1307 *page_size = PTE_LEVEL_PAGE_SIZE(level);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001308
1309 while (level > 0) {
1310
1311 /* Not Present */
Joerg Roedel308973d2009-11-24 17:43:32 +01001312 if (!IOMMU_PTE_PRESENT(*pte))
1313 return NULL;
1314
Joerg Roedel24cd7722010-01-19 17:27:39 +01001315 /* Large PTE */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001316 if (PM_PTE_LEVEL(*pte) == 7 ||
1317 PM_PTE_LEVEL(*pte) == 0)
1318 break;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001319
1320 /* No level skipping support yet */
1321 if (PM_PTE_LEVEL(*pte) != level)
1322 return NULL;
1323
Joerg Roedel308973d2009-11-24 17:43:32 +01001324 level -= 1;
1325
Joerg Roedel24cd7722010-01-19 17:27:39 +01001326 /* Walk to the next level */
Joerg Roedel3039ca12015-04-01 14:58:48 +02001327 pte = IOMMU_PTE_PAGE(*pte);
1328 pte = &pte[PM_LEVEL_INDEX(level, address)];
1329 *page_size = PTE_LEVEL_PAGE_SIZE(level);
1330 }
1331
1332 if (PM_PTE_LEVEL(*pte) == 0x07) {
1333 unsigned long pte_mask;
1334
1335 /*
1336 * If we have a series of large PTEs, make
1337 * sure to return a pointer to the first one.
1338 */
1339 *page_size = pte_mask = PTE_PAGE_SIZE(*pte);
1340 pte_mask = ~((PAGE_SIZE_PTE_COUNT(pte_mask) << 3) - 1);
1341 pte = (u64 *)(((unsigned long)pte) & pte_mask);
Joerg Roedel308973d2009-11-24 17:43:32 +01001342 }
1343
1344 return pte;
1345}
1346
1347/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02001348 * Generic mapping functions. It maps a physical address into a DMA
1349 * address space. It allocates the page table pages if necessary.
1350 * In the future it can be extended to a generic mapping function
1351 * supporting all features of AMD IOMMU page tables like level skipping
1352 * and full 64 bit address spaces.
1353 */
Joerg Roedel38e817f2008-12-02 17:27:52 +01001354static int iommu_map_page(struct protection_domain *dom,
1355 unsigned long bus_addr,
1356 unsigned long phys_addr,
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001357 int prot,
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001358 unsigned long page_size)
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001359{
Joerg Roedel8bda3092009-05-12 12:02:46 +02001360 u64 __pte, *pte;
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001361 int i, count;
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02001362
Joerg Roedeld4b03662015-04-01 14:58:52 +02001363 BUG_ON(!IS_ALIGNED(bus_addr, page_size));
1364 BUG_ON(!IS_ALIGNED(phys_addr, page_size));
1365
Joerg Roedelbad1cac2009-09-02 16:52:23 +02001366 if (!(prot & IOMMU_PROT_MASK))
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001367 return -EINVAL;
1368
Joerg Roedeld4b03662015-04-01 14:58:52 +02001369 count = PAGE_SIZE_PTE_COUNT(page_size);
1370 pte = alloc_pte(dom, bus_addr, page_size, NULL, GFP_KERNEL);
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001371
Maurizio Lombardi63eaa752014-09-11 12:28:03 +02001372 if (!pte)
1373 return -ENOMEM;
1374
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001375 for (i = 0; i < count; ++i)
1376 if (IOMMU_PTE_PRESENT(pte[i]))
1377 return -EBUSY;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001378
Joerg Roedeld4b03662015-04-01 14:58:52 +02001379 if (count > 1) {
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001380 __pte = PAGE_SIZE_PTE(phys_addr, page_size);
1381 __pte |= PM_LEVEL_ENC(7) | IOMMU_PTE_P | IOMMU_PTE_FC;
1382 } else
1383 __pte = phys_addr | IOMMU_PTE_P | IOMMU_PTE_FC;
1384
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001385 if (prot & IOMMU_PROT_IR)
1386 __pte |= IOMMU_PTE_IR;
1387 if (prot & IOMMU_PROT_IW)
1388 __pte |= IOMMU_PTE_IW;
1389
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001390 for (i = 0; i < count; ++i)
1391 pte[i] = __pte;
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001392
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001393 update_domain(dom);
1394
Joerg Roedelbd0e5212008-06-26 21:27:56 +02001395 return 0;
1396}
1397
Joerg Roedel24cd7722010-01-19 17:27:39 +01001398static unsigned long iommu_unmap_page(struct protection_domain *dom,
1399 unsigned long bus_addr,
1400 unsigned long page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001401{
Joerg Roedel71b390e2015-04-01 14:58:49 +02001402 unsigned long long unmapped;
1403 unsigned long unmap_size;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001404 u64 *pte;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001405
Joerg Roedel24cd7722010-01-19 17:27:39 +01001406 BUG_ON(!is_power_of_2(page_size));
1407
1408 unmapped = 0;
1409
1410 while (unmapped < page_size) {
1411
Joerg Roedel71b390e2015-04-01 14:58:49 +02001412 pte = fetch_pte(dom, bus_addr, &unmap_size);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001413
Joerg Roedel71b390e2015-04-01 14:58:49 +02001414 if (pte) {
1415 int i, count;
Joerg Roedel24cd7722010-01-19 17:27:39 +01001416
Joerg Roedel71b390e2015-04-01 14:58:49 +02001417 count = PAGE_SIZE_PTE_COUNT(unmap_size);
Joerg Roedel24cd7722010-01-19 17:27:39 +01001418 for (i = 0; i < count; i++)
1419 pte[i] = 0ULL;
1420 }
1421
1422 bus_addr = (bus_addr & ~(unmap_size - 1)) + unmap_size;
1423 unmapped += unmap_size;
1424 }
1425
Alex Williamson60d0ca32013-06-21 14:33:19 -06001426 BUG_ON(unmapped && !is_power_of_2(unmapped));
Joerg Roedel24cd7722010-01-19 17:27:39 +01001427
1428 return unmapped;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001429}
Joerg Roedeleb74ff62008-12-02 19:59:10 +01001430
Joerg Roedel431b2a22008-07-11 17:14:22 +02001431/****************************************************************************
1432 *
1433 * The next functions belong to the address allocator for the dma_ops
1434 * interface functions. They work like the allocators in the other IOMMU
1435 * drivers. Its basically a bitmap which marks the allocated pages in
1436 * the aperture. Maybe it could be enhanced in the future to a more
1437 * efficient allocator.
1438 *
1439 ****************************************************************************/
Joerg Roedeld3086442008-06-26 21:27:57 +02001440
Joerg Roedel431b2a22008-07-11 17:14:22 +02001441/*
Joerg Roedel384de722009-05-15 12:30:05 +02001442 * The address allocator core functions.
Joerg Roedel431b2a22008-07-11 17:14:22 +02001443 *
1444 * called with domain->lock held
1445 */
Joerg Roedel384de722009-05-15 12:30:05 +02001446
Joerg Roedel9cabe892009-05-18 16:38:55 +02001447/*
Joerg Roedel171e7b32009-11-24 17:47:56 +01001448 * Used to reserve address ranges in the aperture (e.g. for exclusion
1449 * ranges.
1450 */
1451static void dma_ops_reserve_addresses(struct dma_ops_domain *dom,
1452 unsigned long start_page,
1453 unsigned int pages)
1454{
1455 unsigned int i, last_page = dom->aperture_size >> PAGE_SHIFT;
1456
1457 if (start_page + pages > last_page)
1458 pages = last_page - start_page;
1459
1460 for (i = start_page; i < start_page + pages; ++i) {
1461 int index = i / APERTURE_RANGE_PAGES;
1462 int page = i % APERTURE_RANGE_PAGES;
1463 __set_bit(page, dom->aperture[index]->bitmap);
1464 }
1465}
1466
1467/*
Joerg Roedel9cabe892009-05-18 16:38:55 +02001468 * This function is used to add a new aperture range to an existing
1469 * aperture in case of dma_ops domain allocation or address allocation
1470 * failure.
1471 */
Joerg Roedel576175c2009-11-23 19:08:46 +01001472static int alloc_new_range(struct dma_ops_domain *dma_dom,
Joerg Roedel9cabe892009-05-18 16:38:55 +02001473 bool populate, gfp_t gfp)
1474{
1475 int index = dma_dom->aperture_size >> APERTURE_RANGE_SHIFT;
Joerg Roedel576175c2009-11-23 19:08:46 +01001476 struct amd_iommu *iommu;
Joerg Roedel5d7c94c2015-04-01 14:58:50 +02001477 unsigned long i, old_size, pte_pgsize;
Joerg Roedel9cabe892009-05-18 16:38:55 +02001478
Joerg Roedelf5e97052009-05-22 12:31:53 +02001479#ifdef CONFIG_IOMMU_STRESS
1480 populate = false;
1481#endif
1482
Joerg Roedel9cabe892009-05-18 16:38:55 +02001483 if (index >= APERTURE_MAX_RANGES)
1484 return -ENOMEM;
1485
1486 dma_dom->aperture[index] = kzalloc(sizeof(struct aperture_range), gfp);
1487 if (!dma_dom->aperture[index])
1488 return -ENOMEM;
1489
1490 dma_dom->aperture[index]->bitmap = (void *)get_zeroed_page(gfp);
1491 if (!dma_dom->aperture[index]->bitmap)
1492 goto out_free;
1493
1494 dma_dom->aperture[index]->offset = dma_dom->aperture_size;
1495
1496 if (populate) {
1497 unsigned long address = dma_dom->aperture_size;
1498 int i, num_ptes = APERTURE_RANGE_PAGES / 512;
1499 u64 *pte, *pte_page;
1500
1501 for (i = 0; i < num_ptes; ++i) {
Joerg Roedelcbb9d722010-01-15 14:41:15 +01001502 pte = alloc_pte(&dma_dom->domain, address, PAGE_SIZE,
Joerg Roedel9cabe892009-05-18 16:38:55 +02001503 &pte_page, gfp);
1504 if (!pte)
1505 goto out_free;
1506
1507 dma_dom->aperture[index]->pte_pages[i] = pte_page;
1508
1509 address += APERTURE_RANGE_SIZE / 64;
1510 }
1511 }
1512
Joerg Roedel17f5b562011-07-06 17:14:44 +02001513 old_size = dma_dom->aperture_size;
Joerg Roedel9cabe892009-05-18 16:38:55 +02001514 dma_dom->aperture_size += APERTURE_RANGE_SIZE;
1515
Joerg Roedel17f5b562011-07-06 17:14:44 +02001516 /* Reserve address range used for MSI messages */
1517 if (old_size < MSI_ADDR_BASE_LO &&
1518 dma_dom->aperture_size > MSI_ADDR_BASE_LO) {
1519 unsigned long spage;
1520 int pages;
1521
1522 pages = iommu_num_pages(MSI_ADDR_BASE_LO, 0x10000, PAGE_SIZE);
1523 spage = MSI_ADDR_BASE_LO >> PAGE_SHIFT;
1524
1525 dma_ops_reserve_addresses(dma_dom, spage, pages);
1526 }
1527
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001528 /* Initialize the exclusion range if necessary */
Joerg Roedel576175c2009-11-23 19:08:46 +01001529 for_each_iommu(iommu) {
1530 if (iommu->exclusion_start &&
1531 iommu->exclusion_start >= dma_dom->aperture[index]->offset
1532 && iommu->exclusion_start < dma_dom->aperture_size) {
1533 unsigned long startpage;
1534 int pages = iommu_num_pages(iommu->exclusion_start,
1535 iommu->exclusion_length,
1536 PAGE_SIZE);
1537 startpage = iommu->exclusion_start >> PAGE_SHIFT;
1538 dma_ops_reserve_addresses(dma_dom, startpage, pages);
1539 }
Joerg Roedel00cd1222009-05-19 09:52:40 +02001540 }
1541
1542 /*
1543 * Check for areas already mapped as present in the new aperture
1544 * range and mark those pages as reserved in the allocator. Such
1545 * mappings may already exist as a result of requested unity
1546 * mappings for devices.
1547 */
1548 for (i = dma_dom->aperture[index]->offset;
1549 i < dma_dom->aperture_size;
Joerg Roedel5d7c94c2015-04-01 14:58:50 +02001550 i += pte_pgsize) {
Joerg Roedel3039ca12015-04-01 14:58:48 +02001551 u64 *pte = fetch_pte(&dma_dom->domain, i, &pte_pgsize);
Joerg Roedel00cd1222009-05-19 09:52:40 +02001552 if (!pte || !IOMMU_PTE_PRESENT(*pte))
1553 continue;
1554
Joerg Roedel5d7c94c2015-04-01 14:58:50 +02001555 dma_ops_reserve_addresses(dma_dom, i >> PAGE_SHIFT,
1556 pte_pgsize >> 12);
Joerg Roedel00cd1222009-05-19 09:52:40 +02001557 }
1558
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001559 update_domain(&dma_dom->domain);
1560
Joerg Roedel9cabe892009-05-18 16:38:55 +02001561 return 0;
1562
1563out_free:
Joerg Roedel04bfdd82009-09-02 16:00:23 +02001564 update_domain(&dma_dom->domain);
1565
Joerg Roedel9cabe892009-05-18 16:38:55 +02001566 free_page((unsigned long)dma_dom->aperture[index]->bitmap);
1567
1568 kfree(dma_dom->aperture[index]);
1569 dma_dom->aperture[index] = NULL;
1570
1571 return -ENOMEM;
1572}
1573
Joerg Roedel384de722009-05-15 12:30:05 +02001574static unsigned long dma_ops_area_alloc(struct device *dev,
1575 struct dma_ops_domain *dom,
1576 unsigned int pages,
1577 unsigned long align_mask,
1578 u64 dma_mask,
1579 unsigned long start)
1580{
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001581 unsigned long next_bit = dom->next_address % APERTURE_RANGE_SIZE;
Joerg Roedel384de722009-05-15 12:30:05 +02001582 int max_index = dom->aperture_size >> APERTURE_RANGE_SHIFT;
1583 int i = start >> APERTURE_RANGE_SHIFT;
Joerg Roedele6aabee2015-05-27 09:26:09 +02001584 unsigned long boundary_size, mask;
Joerg Roedel384de722009-05-15 12:30:05 +02001585 unsigned long address = -1;
1586 unsigned long limit;
1587
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001588 next_bit >>= PAGE_SHIFT;
1589
Joerg Roedele6aabee2015-05-27 09:26:09 +02001590 mask = dma_get_seg_boundary(dev);
1591
1592 boundary_size = mask + 1 ? ALIGN(mask + 1, PAGE_SIZE) >> PAGE_SHIFT :
1593 1UL << (BITS_PER_LONG - PAGE_SHIFT);
Joerg Roedel384de722009-05-15 12:30:05 +02001594
1595 for (;i < max_index; ++i) {
1596 unsigned long offset = dom->aperture[i]->offset >> PAGE_SHIFT;
1597
1598 if (dom->aperture[i]->offset >= dma_mask)
1599 break;
1600
1601 limit = iommu_device_max_index(APERTURE_RANGE_PAGES, offset,
1602 dma_mask >> PAGE_SHIFT);
1603
1604 address = iommu_area_alloc(dom->aperture[i]->bitmap,
1605 limit, next_bit, pages, 0,
1606 boundary_size, align_mask);
1607 if (address != -1) {
1608 address = dom->aperture[i]->offset +
1609 (address << PAGE_SHIFT);
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001610 dom->next_address = address + (pages << PAGE_SHIFT);
Joerg Roedel384de722009-05-15 12:30:05 +02001611 break;
1612 }
1613
1614 next_bit = 0;
1615 }
1616
1617 return address;
1618}
1619
Joerg Roedeld3086442008-06-26 21:27:57 +02001620static unsigned long dma_ops_alloc_addresses(struct device *dev,
1621 struct dma_ops_domain *dom,
Joerg Roedel6d4f3432008-09-04 19:18:02 +02001622 unsigned int pages,
Joerg Roedel832a90c2008-09-18 15:54:23 +02001623 unsigned long align_mask,
1624 u64 dma_mask)
Joerg Roedeld3086442008-06-26 21:27:57 +02001625{
Joerg Roedeld3086442008-06-26 21:27:57 +02001626 unsigned long address;
Joerg Roedeld3086442008-06-26 21:27:57 +02001627
Joerg Roedelfe16f082009-05-22 12:27:53 +02001628#ifdef CONFIG_IOMMU_STRESS
1629 dom->next_address = 0;
1630 dom->need_flush = true;
1631#endif
Joerg Roedeld3086442008-06-26 21:27:57 +02001632
Joerg Roedel384de722009-05-15 12:30:05 +02001633 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001634 dma_mask, dom->next_address);
Joerg Roedeld3086442008-06-26 21:27:57 +02001635
Joerg Roedel1c655772008-09-04 18:40:05 +02001636 if (address == -1) {
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001637 dom->next_address = 0;
Joerg Roedel384de722009-05-15 12:30:05 +02001638 address = dma_ops_area_alloc(dev, dom, pages, align_mask,
1639 dma_mask, 0);
Joerg Roedel1c655772008-09-04 18:40:05 +02001640 dom->need_flush = true;
1641 }
Joerg Roedeld3086442008-06-26 21:27:57 +02001642
Joerg Roedel384de722009-05-15 12:30:05 +02001643 if (unlikely(address == -1))
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09001644 address = DMA_ERROR_CODE;
Joerg Roedeld3086442008-06-26 21:27:57 +02001645
1646 WARN_ON((address + (PAGE_SIZE*pages)) > dom->aperture_size);
1647
1648 return address;
1649}
1650
Joerg Roedel431b2a22008-07-11 17:14:22 +02001651/*
1652 * The address free function.
1653 *
1654 * called with domain->lock held
1655 */
Joerg Roedeld3086442008-06-26 21:27:57 +02001656static void dma_ops_free_addresses(struct dma_ops_domain *dom,
1657 unsigned long address,
1658 unsigned int pages)
1659{
Joerg Roedel384de722009-05-15 12:30:05 +02001660 unsigned i = address >> APERTURE_RANGE_SHIFT;
1661 struct aperture_range *range = dom->aperture[i];
Joerg Roedel80be3082008-11-06 14:59:05 +01001662
Joerg Roedel384de722009-05-15 12:30:05 +02001663 BUG_ON(i >= APERTURE_MAX_RANGES || range == NULL);
1664
Joerg Roedel47bccd62009-05-22 12:40:54 +02001665#ifdef CONFIG_IOMMU_STRESS
1666 if (i < 4)
1667 return;
1668#endif
1669
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001670 if (address >= dom->next_address)
Joerg Roedel80be3082008-11-06 14:59:05 +01001671 dom->need_flush = true;
Joerg Roedel384de722009-05-15 12:30:05 +02001672
1673 address = (address % APERTURE_RANGE_SIZE) >> PAGE_SHIFT;
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001674
Akinobu Mitaa66022c2009-12-15 16:48:28 -08001675 bitmap_clear(range->bitmap, address, pages);
Joerg Roedel384de722009-05-15 12:30:05 +02001676
Joerg Roedeld3086442008-06-26 21:27:57 +02001677}
1678
Joerg Roedel431b2a22008-07-11 17:14:22 +02001679/****************************************************************************
1680 *
1681 * The next functions belong to the domain allocation. A domain is
1682 * allocated for every IOMMU as the default domain. If device isolation
1683 * is enabled, every device get its own domain. The most important thing
1684 * about domains is the page table mapping the DMA address space they
1685 * contain.
1686 *
1687 ****************************************************************************/
1688
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001689/*
1690 * This function adds a protection domain to the global protection domain list
1691 */
1692static void add_domain_to_list(struct protection_domain *domain)
1693{
1694 unsigned long flags;
1695
1696 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1697 list_add(&domain->list, &amd_iommu_pd_list);
1698 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1699}
1700
1701/*
1702 * This function removes a protection domain to the global
1703 * protection domain list
1704 */
1705static void del_domain_from_list(struct protection_domain *domain)
1706{
1707 unsigned long flags;
1708
1709 spin_lock_irqsave(&amd_iommu_pd_lock, flags);
1710 list_del(&domain->list);
1711 spin_unlock_irqrestore(&amd_iommu_pd_lock, flags);
1712}
1713
Joerg Roedelec487d12008-06-26 21:27:58 +02001714static u16 domain_id_alloc(void)
1715{
1716 unsigned long flags;
1717 int id;
1718
1719 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1720 id = find_first_zero_bit(amd_iommu_pd_alloc_bitmap, MAX_DOMAIN_ID);
1721 BUG_ON(id == 0);
1722 if (id > 0 && id < MAX_DOMAIN_ID)
1723 __set_bit(id, amd_iommu_pd_alloc_bitmap);
1724 else
1725 id = 0;
1726 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1727
1728 return id;
1729}
1730
Joerg Roedela2acfb72008-12-02 18:28:53 +01001731static void domain_id_free(int id)
1732{
1733 unsigned long flags;
1734
1735 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
1736 if (id > 0 && id < MAX_DOMAIN_ID)
1737 __clear_bit(id, amd_iommu_pd_alloc_bitmap);
1738 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
1739}
Joerg Roedela2acfb72008-12-02 18:28:53 +01001740
Joerg Roedel5c34c402013-06-20 20:22:58 +02001741#define DEFINE_FREE_PT_FN(LVL, FN) \
1742static void free_pt_##LVL (unsigned long __pt) \
1743{ \
1744 unsigned long p; \
1745 u64 *pt; \
1746 int i; \
1747 \
1748 pt = (u64 *)__pt; \
1749 \
1750 for (i = 0; i < 512; ++i) { \
Joerg Roedel0b3fff52015-06-18 10:48:34 +02001751 /* PTE present? */ \
Joerg Roedel5c34c402013-06-20 20:22:58 +02001752 if (!IOMMU_PTE_PRESENT(pt[i])) \
1753 continue; \
1754 \
Joerg Roedel0b3fff52015-06-18 10:48:34 +02001755 /* Large PTE? */ \
1756 if (PM_PTE_LEVEL(pt[i]) == 0 || \
1757 PM_PTE_LEVEL(pt[i]) == 7) \
1758 continue; \
1759 \
Joerg Roedel5c34c402013-06-20 20:22:58 +02001760 p = (unsigned long)IOMMU_PTE_PAGE(pt[i]); \
1761 FN(p); \
1762 } \
1763 free_page((unsigned long)pt); \
1764}
1765
1766DEFINE_FREE_PT_FN(l2, free_page)
1767DEFINE_FREE_PT_FN(l3, free_pt_l2)
1768DEFINE_FREE_PT_FN(l4, free_pt_l3)
1769DEFINE_FREE_PT_FN(l5, free_pt_l4)
1770DEFINE_FREE_PT_FN(l6, free_pt_l5)
1771
Joerg Roedel86db2e52008-12-02 18:20:21 +01001772static void free_pagetable(struct protection_domain *domain)
Joerg Roedelec487d12008-06-26 21:27:58 +02001773{
Joerg Roedel5c34c402013-06-20 20:22:58 +02001774 unsigned long root = (unsigned long)domain->pt_root;
Joerg Roedelec487d12008-06-26 21:27:58 +02001775
Joerg Roedel5c34c402013-06-20 20:22:58 +02001776 switch (domain->mode) {
1777 case PAGE_MODE_NONE:
1778 break;
1779 case PAGE_MODE_1_LEVEL:
1780 free_page(root);
1781 break;
1782 case PAGE_MODE_2_LEVEL:
1783 free_pt_l2(root);
1784 break;
1785 case PAGE_MODE_3_LEVEL:
1786 free_pt_l3(root);
1787 break;
1788 case PAGE_MODE_4_LEVEL:
1789 free_pt_l4(root);
1790 break;
1791 case PAGE_MODE_5_LEVEL:
1792 free_pt_l5(root);
1793 break;
1794 case PAGE_MODE_6_LEVEL:
1795 free_pt_l6(root);
1796 break;
1797 default:
1798 BUG();
Joerg Roedelec487d12008-06-26 21:27:58 +02001799 }
Joerg Roedelec487d12008-06-26 21:27:58 +02001800}
1801
Joerg Roedelb16137b2011-11-21 16:50:23 +01001802static void free_gcr3_tbl_level1(u64 *tbl)
1803{
1804 u64 *ptr;
1805 int i;
1806
1807 for (i = 0; i < 512; ++i) {
1808 if (!(tbl[i] & GCR3_VALID))
1809 continue;
1810
1811 ptr = __va(tbl[i] & PAGE_MASK);
1812
1813 free_page((unsigned long)ptr);
1814 }
1815}
1816
1817static void free_gcr3_tbl_level2(u64 *tbl)
1818{
1819 u64 *ptr;
1820 int i;
1821
1822 for (i = 0; i < 512; ++i) {
1823 if (!(tbl[i] & GCR3_VALID))
1824 continue;
1825
1826 ptr = __va(tbl[i] & PAGE_MASK);
1827
1828 free_gcr3_tbl_level1(ptr);
1829 }
1830}
1831
Joerg Roedel52815b72011-11-17 17:24:28 +01001832static void free_gcr3_table(struct protection_domain *domain)
1833{
Joerg Roedelb16137b2011-11-21 16:50:23 +01001834 if (domain->glx == 2)
1835 free_gcr3_tbl_level2(domain->gcr3_tbl);
1836 else if (domain->glx == 1)
1837 free_gcr3_tbl_level1(domain->gcr3_tbl);
Joerg Roedel23d3a982015-08-13 11:15:13 +02001838 else
1839 BUG_ON(domain->glx != 0);
Joerg Roedelb16137b2011-11-21 16:50:23 +01001840
Joerg Roedel52815b72011-11-17 17:24:28 +01001841 free_page((unsigned long)domain->gcr3_tbl);
1842}
1843
Joerg Roedel431b2a22008-07-11 17:14:22 +02001844/*
1845 * Free a domain, only used if something went wrong in the
1846 * allocation path and we need to free an already allocated page table
1847 */
Joerg Roedelec487d12008-06-26 21:27:58 +02001848static void dma_ops_domain_free(struct dma_ops_domain *dom)
1849{
Joerg Roedel384de722009-05-15 12:30:05 +02001850 int i;
1851
Joerg Roedelec487d12008-06-26 21:27:58 +02001852 if (!dom)
1853 return;
1854
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001855 del_domain_from_list(&dom->domain);
1856
Joerg Roedel86db2e52008-12-02 18:20:21 +01001857 free_pagetable(&dom->domain);
Joerg Roedelec487d12008-06-26 21:27:58 +02001858
Joerg Roedel384de722009-05-15 12:30:05 +02001859 for (i = 0; i < APERTURE_MAX_RANGES; ++i) {
1860 if (!dom->aperture[i])
1861 continue;
1862 free_page((unsigned long)dom->aperture[i]->bitmap);
1863 kfree(dom->aperture[i]);
1864 }
Joerg Roedelec487d12008-06-26 21:27:58 +02001865
1866 kfree(dom);
1867}
1868
Joerg Roedel431b2a22008-07-11 17:14:22 +02001869/*
1870 * Allocates a new protection domain usable for the dma_ops functions.
Uwe Kleine-Königb5950762010-11-01 15:38:34 -04001871 * It also initializes the page table and the address allocator data
Joerg Roedel431b2a22008-07-11 17:14:22 +02001872 * structures required for the dma_ops interface
1873 */
Joerg Roedel87a64d52009-11-24 17:26:43 +01001874static struct dma_ops_domain *dma_ops_domain_alloc(void)
Joerg Roedelec487d12008-06-26 21:27:58 +02001875{
1876 struct dma_ops_domain *dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001877
1878 dma_dom = kzalloc(sizeof(struct dma_ops_domain), GFP_KERNEL);
1879 if (!dma_dom)
1880 return NULL;
1881
Joerg Roedel7a5a5662015-06-30 08:56:11 +02001882 if (protection_domain_init(&dma_dom->domain))
Joerg Roedelec487d12008-06-26 21:27:58 +02001883 goto free_dma_dom;
Joerg Roedel7a5a5662015-06-30 08:56:11 +02001884
Joerg Roedel8f7a0172009-09-02 16:55:24 +02001885 dma_dom->domain.mode = PAGE_MODE_2_LEVEL;
Joerg Roedelec487d12008-06-26 21:27:58 +02001886 dma_dom->domain.pt_root = (void *)get_zeroed_page(GFP_KERNEL);
Joerg Roedel9fdb19d2008-12-02 17:46:25 +01001887 dma_dom->domain.flags = PD_DMA_OPS_MASK;
Joerg Roedelec487d12008-06-26 21:27:58 +02001888 dma_dom->domain.priv = dma_dom;
1889 if (!dma_dom->domain.pt_root)
1890 goto free_dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001891
Joerg Roedel1c655772008-09-04 18:40:05 +02001892 dma_dom->need_flush = false;
1893
Joerg Roedelaeb26f52009-11-20 16:44:01 +01001894 add_domain_to_list(&dma_dom->domain);
1895
Joerg Roedel576175c2009-11-23 19:08:46 +01001896 if (alloc_new_range(dma_dom, true, GFP_KERNEL))
Joerg Roedelec487d12008-06-26 21:27:58 +02001897 goto free_dma_dom;
Joerg Roedelec487d12008-06-26 21:27:58 +02001898
Joerg Roedel431b2a22008-07-11 17:14:22 +02001899 /*
Joerg Roedelec487d12008-06-26 21:27:58 +02001900 * mark the first page as allocated so we never return 0 as
1901 * a valid dma-address. So we can use 0 as error value
Joerg Roedel431b2a22008-07-11 17:14:22 +02001902 */
Joerg Roedel384de722009-05-15 12:30:05 +02001903 dma_dom->aperture[0]->bitmap[0] = 1;
Joerg Roedel803b8cb2009-05-18 15:32:48 +02001904 dma_dom->next_address = 0;
Joerg Roedelec487d12008-06-26 21:27:58 +02001905
Joerg Roedelec487d12008-06-26 21:27:58 +02001906
1907 return dma_dom;
1908
1909free_dma_dom:
1910 dma_ops_domain_free(dma_dom);
1911
1912 return NULL;
1913}
1914
Joerg Roedel431b2a22008-07-11 17:14:22 +02001915/*
Joerg Roedel5b28df62008-12-02 17:49:42 +01001916 * little helper function to check whether a given protection domain is a
1917 * dma_ops domain
1918 */
1919static bool dma_ops_domain(struct protection_domain *domain)
1920{
1921 return domain->flags & PD_DMA_OPS_MASK;
1922}
1923
Joerg Roedelfd7b5532011-04-05 15:31:08 +02001924static void set_dte_entry(u16 devid, struct protection_domain *domain, bool ats)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001925{
Joerg Roedel132bd682011-11-17 14:18:46 +01001926 u64 pte_root = 0;
Joerg Roedelee6c2862011-11-09 12:06:03 +01001927 u64 flags = 0;
Joerg Roedel863c74e2008-12-02 17:56:36 +01001928
Joerg Roedel132bd682011-11-17 14:18:46 +01001929 if (domain->mode != PAGE_MODE_NONE)
1930 pte_root = virt_to_phys(domain->pt_root);
1931
Joerg Roedel38ddf412008-09-11 10:38:32 +02001932 pte_root |= (domain->mode & DEV_ENTRY_MODE_MASK)
1933 << DEV_ENTRY_MODE_SHIFT;
1934 pte_root |= IOMMU_PTE_IR | IOMMU_PTE_IW | IOMMU_PTE_P | IOMMU_PTE_TV;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001935
Joerg Roedelee6c2862011-11-09 12:06:03 +01001936 flags = amd_iommu_dev_table[devid].data[1];
1937
Joerg Roedelfd7b5532011-04-05 15:31:08 +02001938 if (ats)
1939 flags |= DTE_FLAG_IOTLB;
1940
Joerg Roedel52815b72011-11-17 17:24:28 +01001941 if (domain->flags & PD_IOMMUV2_MASK) {
1942 u64 gcr3 = __pa(domain->gcr3_tbl);
1943 u64 glx = domain->glx;
1944 u64 tmp;
1945
1946 pte_root |= DTE_FLAG_GV;
1947 pte_root |= (glx & DTE_GLX_MASK) << DTE_GLX_SHIFT;
1948
1949 /* First mask out possible old values for GCR3 table */
1950 tmp = DTE_GCR3_VAL_B(~0ULL) << DTE_GCR3_SHIFT_B;
1951 flags &= ~tmp;
1952
1953 tmp = DTE_GCR3_VAL_C(~0ULL) << DTE_GCR3_SHIFT_C;
1954 flags &= ~tmp;
1955
1956 /* Encode GCR3 table into DTE */
1957 tmp = DTE_GCR3_VAL_A(gcr3) << DTE_GCR3_SHIFT_A;
1958 pte_root |= tmp;
1959
1960 tmp = DTE_GCR3_VAL_B(gcr3) << DTE_GCR3_SHIFT_B;
1961 flags |= tmp;
1962
1963 tmp = DTE_GCR3_VAL_C(gcr3) << DTE_GCR3_SHIFT_C;
1964 flags |= tmp;
1965 }
1966
Joerg Roedelee6c2862011-11-09 12:06:03 +01001967 flags &= ~(0xffffUL);
1968 flags |= domain->id;
1969
1970 amd_iommu_dev_table[devid].data[1] = flags;
1971 amd_iommu_dev_table[devid].data[0] = pte_root;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02001972}
1973
Joerg Roedel15898bb2009-11-24 15:39:42 +01001974static void clear_dte_entry(u16 devid)
Joerg Roedel355bf552008-12-08 12:02:41 +01001975{
Joerg Roedel355bf552008-12-08 12:02:41 +01001976 /* remove entry from the device table seen by the hardware */
1977 amd_iommu_dev_table[devid].data[0] = IOMMU_PTE_P | IOMMU_PTE_TV;
1978 amd_iommu_dev_table[devid].data[1] = 0;
Joerg Roedel355bf552008-12-08 12:02:41 +01001979
Joerg Roedelc5cca142009-10-09 18:31:20 +02001980 amd_iommu_apply_erratum_63(devid);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001981}
1982
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001983static void do_attach(struct iommu_dev_data *dev_data,
1984 struct protection_domain *domain)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001985{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001986 struct amd_iommu *iommu;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001987 bool ats;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001988
Joerg Roedelec9e79e2011-06-09 17:25:50 +02001989 iommu = amd_iommu_rlookup_table[dev_data->devid];
1990 ats = dev_data->ats.enabled;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001991
1992 /* Update data structures */
1993 dev_data->domain = domain;
1994 list_add(&dev_data->list, &domain->dev_list);
Joerg Roedelf62dda62011-06-09 12:55:35 +02001995 set_dte_entry(dev_data->devid, domain, ats);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01001996
1997 /* Do reference counting */
1998 domain->dev_iommu[iommu->index] += 1;
1999 domain->dev_cnt += 1;
2000
2001 /* Flush the DTE entry */
Joerg Roedel6c542042011-06-09 17:07:31 +02002002 device_flush_dte(dev_data);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002003}
2004
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002005static void do_detach(struct iommu_dev_data *dev_data)
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002006{
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002007 struct amd_iommu *iommu;
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002008
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002009 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedelc5cca142009-10-09 18:31:20 +02002010
Joerg Roedelc4596112009-11-20 14:57:32 +01002011 /* decrease reference counters */
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002012 dev_data->domain->dev_iommu[iommu->index] -= 1;
2013 dev_data->domain->dev_cnt -= 1;
Joerg Roedel355bf552008-12-08 12:02:41 +01002014
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002015 /* Update data structures */
2016 dev_data->domain = NULL;
2017 list_del(&dev_data->list);
Joerg Roedelf62dda62011-06-09 12:55:35 +02002018 clear_dte_entry(dev_data->devid);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002019
2020 /* Flush the DTE entry */
Joerg Roedel6c542042011-06-09 17:07:31 +02002021 device_flush_dte(dev_data);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002022}
2023
2024/*
2025 * If a device is not yet associated with a domain, this function does
2026 * assigns it visible for the hardware
2027 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002028static int __attach_device(struct iommu_dev_data *dev_data,
Joerg Roedel15898bb2009-11-24 15:39:42 +01002029 struct protection_domain *domain)
2030{
Joerg Roedel397111a2014-08-05 17:31:51 +02002031 struct iommu_dev_data *head, *entry;
Julia Lawall84fe6c12010-05-27 12:31:51 +02002032 int ret;
Joerg Roedel657cbb62009-11-23 15:26:46 +01002033
Joerg Roedel15898bb2009-11-24 15:39:42 +01002034 /* lock domain */
2035 spin_lock(&domain->lock);
2036
Joerg Roedel397111a2014-08-05 17:31:51 +02002037 head = dev_data;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002038
Joerg Roedel397111a2014-08-05 17:31:51 +02002039 if (head->alias_data != NULL)
2040 head = head->alias_data;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002041
Joerg Roedel397111a2014-08-05 17:31:51 +02002042 /* Now we have the root of the alias group, if any */
Joerg Roedel2b02b092011-06-09 17:48:39 +02002043
Joerg Roedel397111a2014-08-05 17:31:51 +02002044 ret = -EBUSY;
2045 if (head->domain != NULL)
2046 goto out_unlock;
Joerg Roedel24100052009-11-25 15:59:57 +01002047
Joerg Roedel397111a2014-08-05 17:31:51 +02002048 /* Attach alias group root */
2049 do_attach(head, domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002050
Joerg Roedel397111a2014-08-05 17:31:51 +02002051 /* Attach other devices in the alias group */
2052 list_for_each_entry(entry, &head->alias_list, alias_list)
2053 do_attach(entry, domain);
Joerg Roedel24100052009-11-25 15:59:57 +01002054
Julia Lawall84fe6c12010-05-27 12:31:51 +02002055 ret = 0;
2056
2057out_unlock:
2058
Joerg Roedel355bf552008-12-08 12:02:41 +01002059 /* ready */
2060 spin_unlock(&domain->lock);
Joerg Roedel21129f72009-09-01 11:59:42 +02002061
Julia Lawall84fe6c12010-05-27 12:31:51 +02002062 return ret;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002063}
2064
Joerg Roedel52815b72011-11-17 17:24:28 +01002065
2066static void pdev_iommuv2_disable(struct pci_dev *pdev)
2067{
2068 pci_disable_ats(pdev);
2069 pci_disable_pri(pdev);
2070 pci_disable_pasid(pdev);
2071}
2072
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002073/* FIXME: Change generic reset-function to do the same */
2074static int pri_reset_while_enabled(struct pci_dev *pdev)
2075{
2076 u16 control;
2077 int pos;
2078
Joerg Roedel46277b72011-12-07 14:34:02 +01002079 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002080 if (!pos)
2081 return -EINVAL;
2082
Joerg Roedel46277b72011-12-07 14:34:02 +01002083 pci_read_config_word(pdev, pos + PCI_PRI_CTRL, &control);
2084 control |= PCI_PRI_CTRL_RESET;
2085 pci_write_config_word(pdev, pos + PCI_PRI_CTRL, control);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002086
2087 return 0;
2088}
2089
Joerg Roedel52815b72011-11-17 17:24:28 +01002090static int pdev_iommuv2_enable(struct pci_dev *pdev)
2091{
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002092 bool reset_enable;
2093 int reqs, ret;
2094
2095 /* FIXME: Hardcode number of outstanding requests for now */
2096 reqs = 32;
2097 if (pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_LIMIT_REQ_ONE))
2098 reqs = 1;
2099 reset_enable = pdev_pri_erratum(pdev, AMD_PRI_DEV_ERRATUM_ENABLE_RESET);
Joerg Roedel52815b72011-11-17 17:24:28 +01002100
2101 /* Only allow access to user-accessible pages */
2102 ret = pci_enable_pasid(pdev, 0);
2103 if (ret)
2104 goto out_err;
2105
2106 /* First reset the PRI state of the device */
2107 ret = pci_reset_pri(pdev);
2108 if (ret)
2109 goto out_err;
2110
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002111 /* Enable PRI */
2112 ret = pci_enable_pri(pdev, reqs);
Joerg Roedel52815b72011-11-17 17:24:28 +01002113 if (ret)
2114 goto out_err;
2115
Joerg Roedel6a113dd2011-12-01 12:04:58 +01002116 if (reset_enable) {
2117 ret = pri_reset_while_enabled(pdev);
2118 if (ret)
2119 goto out_err;
2120 }
2121
Joerg Roedel52815b72011-11-17 17:24:28 +01002122 ret = pci_enable_ats(pdev, PAGE_SHIFT);
2123 if (ret)
2124 goto out_err;
2125
2126 return 0;
2127
2128out_err:
2129 pci_disable_pri(pdev);
2130 pci_disable_pasid(pdev);
2131
2132 return ret;
2133}
2134
Joerg Roedelc99afa22011-11-21 18:19:25 +01002135/* FIXME: Move this to PCI code */
Joerg Roedela3b93122012-04-12 12:49:26 +02002136#define PCI_PRI_TLP_OFF (1 << 15)
Joerg Roedelc99afa22011-11-21 18:19:25 +01002137
Joerg Roedel98f1ad22012-07-06 13:28:37 +02002138static bool pci_pri_tlp_required(struct pci_dev *pdev)
Joerg Roedelc99afa22011-11-21 18:19:25 +01002139{
Joerg Roedela3b93122012-04-12 12:49:26 +02002140 u16 status;
Joerg Roedelc99afa22011-11-21 18:19:25 +01002141 int pos;
2142
Joerg Roedel46277b72011-12-07 14:34:02 +01002143 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002144 if (!pos)
2145 return false;
2146
Joerg Roedela3b93122012-04-12 12:49:26 +02002147 pci_read_config_word(pdev, pos + PCI_PRI_STATUS, &status);
Joerg Roedelc99afa22011-11-21 18:19:25 +01002148
Joerg Roedela3b93122012-04-12 12:49:26 +02002149 return (status & PCI_PRI_TLP_OFF) ? true : false;
Joerg Roedelc99afa22011-11-21 18:19:25 +01002150}
2151
Joerg Roedel15898bb2009-11-24 15:39:42 +01002152/*
Frank Arnolddf805ab2012-08-27 19:21:04 +02002153 * If a device is not yet associated with a domain, this function
Joerg Roedel15898bb2009-11-24 15:39:42 +01002154 * assigns it visible for the hardware
2155 */
2156static int attach_device(struct device *dev,
2157 struct protection_domain *domain)
2158{
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002159 struct pci_dev *pdev = to_pci_dev(dev);
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002160 struct iommu_dev_data *dev_data;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002161 unsigned long flags;
2162 int ret;
2163
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002164 dev_data = get_dev_data(dev);
2165
Joerg Roedel52815b72011-11-17 17:24:28 +01002166 if (domain->flags & PD_IOMMUV2_MASK) {
Joerg Roedel02ca2022015-07-28 16:58:49 +02002167 if (!dev_data->passthrough)
Joerg Roedel52815b72011-11-17 17:24:28 +01002168 return -EINVAL;
2169
Joerg Roedel02ca2022015-07-28 16:58:49 +02002170 if (dev_data->iommu_v2) {
2171 if (pdev_iommuv2_enable(pdev) != 0)
2172 return -EINVAL;
Joerg Roedel52815b72011-11-17 17:24:28 +01002173
Joerg Roedel02ca2022015-07-28 16:58:49 +02002174 dev_data->ats.enabled = true;
2175 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2176 dev_data->pri_tlp = pci_pri_tlp_required(pdev);
2177 }
Joerg Roedel52815b72011-11-17 17:24:28 +01002178 } else if (amd_iommu_iotlb_sup &&
2179 pci_enable_ats(pdev, PAGE_SHIFT) == 0) {
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002180 dev_data->ats.enabled = true;
2181 dev_data->ats.qdep = pci_ats_queue_depth(pdev);
2182 }
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002183
Joerg Roedel15898bb2009-11-24 15:39:42 +01002184 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002185 ret = __attach_device(dev_data, domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002186 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2187
2188 /*
2189 * We might boot into a crash-kernel here. The crashed kernel
2190 * left the caches in the IOMMU dirty. So we have to flush
2191 * here to evict all dirty stuff.
2192 */
Joerg Roedel17b124b2011-04-06 18:01:35 +02002193 domain_flush_tlb_pde(domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002194
2195 return ret;
2196}
2197
2198/*
2199 * Removes a device from a protection domain (unlocked)
2200 */
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002201static void __detach_device(struct iommu_dev_data *dev_data)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002202{
Joerg Roedel397111a2014-08-05 17:31:51 +02002203 struct iommu_dev_data *head, *entry;
Joerg Roedel2ca76272010-01-22 16:45:31 +01002204 struct protection_domain *domain;
Joerg Roedel7c392cb2009-11-26 11:13:32 +01002205 unsigned long flags;
Joerg Roedel15898bb2009-11-24 15:39:42 +01002206
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002207 BUG_ON(!dev_data->domain);
Joerg Roedel15898bb2009-11-24 15:39:42 +01002208
Joerg Roedel2ca76272010-01-22 16:45:31 +01002209 domain = dev_data->domain;
2210
2211 spin_lock_irqsave(&domain->lock, flags);
Joerg Roedel24100052009-11-25 15:59:57 +01002212
Joerg Roedel397111a2014-08-05 17:31:51 +02002213 head = dev_data;
2214 if (head->alias_data != NULL)
2215 head = head->alias_data;
Joerg Roedel71f77582011-06-09 19:03:15 +02002216
Joerg Roedel397111a2014-08-05 17:31:51 +02002217 list_for_each_entry(entry, &head->alias_list, alias_list)
2218 do_detach(entry);
Joerg Roedel24100052009-11-25 15:59:57 +01002219
Joerg Roedel397111a2014-08-05 17:31:51 +02002220 do_detach(head);
Joerg Roedel7f760dd2009-11-26 14:49:59 +01002221
Joerg Roedel2ca76272010-01-22 16:45:31 +01002222 spin_unlock_irqrestore(&domain->lock, flags);
Joerg Roedel355bf552008-12-08 12:02:41 +01002223}
2224
2225/*
2226 * Removes a device from a protection domain (with devtable_lock held)
2227 */
Joerg Roedel15898bb2009-11-24 15:39:42 +01002228static void detach_device(struct device *dev)
Joerg Roedel355bf552008-12-08 12:02:41 +01002229{
Joerg Roedel52815b72011-11-17 17:24:28 +01002230 struct protection_domain *domain;
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002231 struct iommu_dev_data *dev_data;
Joerg Roedel355bf552008-12-08 12:02:41 +01002232 unsigned long flags;
2233
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002234 dev_data = get_dev_data(dev);
Joerg Roedel52815b72011-11-17 17:24:28 +01002235 domain = dev_data->domain;
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002236
Joerg Roedel355bf552008-12-08 12:02:41 +01002237 /* lock device table */
2238 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
Joerg Roedelec9e79e2011-06-09 17:25:50 +02002239 __detach_device(dev_data);
Joerg Roedel355bf552008-12-08 12:02:41 +01002240 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
Joerg Roedelfd7b5532011-04-05 15:31:08 +02002241
Joerg Roedel02ca2022015-07-28 16:58:49 +02002242 if (domain->flags & PD_IOMMUV2_MASK && dev_data->iommu_v2)
Joerg Roedel52815b72011-11-17 17:24:28 +01002243 pdev_iommuv2_disable(to_pci_dev(dev));
2244 else if (dev_data->ats.enabled)
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002245 pci_disable_ats(to_pci_dev(dev));
Joerg Roedel52815b72011-11-17 17:24:28 +01002246
2247 dev_data->ats.enabled = false;
Joerg Roedel355bf552008-12-08 12:02:41 +01002248}
Joerg Roedele275a2a2008-12-10 18:27:25 +01002249
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002250static int amd_iommu_add_device(struct device *dev)
Joerg Roedel15898bb2009-11-24 15:39:42 +01002251{
Joerg Roedel71f77582011-06-09 19:03:15 +02002252 struct iommu_dev_data *dev_data;
Joerg Roedel07ee8692015-05-28 18:41:42 +02002253 struct iommu_domain *domain;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002254 struct amd_iommu *iommu;
Joerg Roedel5abcdba2011-12-01 15:49:45 +01002255 u16 devid;
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002256 int ret;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002257
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002258 if (!check_device(dev) || get_dev_data(dev))
Joerg Roedel98fc5a62009-11-24 17:19:23 +01002259 return 0;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002260
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002261 devid = get_device_id(dev);
2262 iommu = amd_iommu_rlookup_table[devid];
Joerg Roedele275a2a2008-12-10 18:27:25 +01002263
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002264 ret = iommu_init_device(dev);
Joerg Roedel4d58b8a2015-06-11 09:21:39 +02002265 if (ret) {
2266 if (ret != -ENOTSUPP)
2267 pr_err("Failed to initialize device %s - trying to proceed anyway\n",
2268 dev_name(dev));
Joerg Roedel657cbb62009-11-23 15:26:46 +01002269
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002270 iommu_ignore_device(dev);
Joerg Roedel343e9ca2015-05-28 18:41:43 +02002271 dev->archdata.dma_ops = &nommu_dma_ops;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002272 goto out;
2273 }
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002274 init_iommu_group(dev);
Joerg Roedele275a2a2008-12-10 18:27:25 +01002275
Joerg Roedel07ee8692015-05-28 18:41:42 +02002276 dev_data = get_dev_data(dev);
Joerg Roedel4d58b8a2015-06-11 09:21:39 +02002277
2278 BUG_ON(!dev_data);
2279
Joerg Roedel1e6a7b02015-07-28 16:58:48 +02002280 if (iommu_pass_through || dev_data->iommu_v2)
Joerg Roedel07ee8692015-05-28 18:41:42 +02002281 iommu_request_dm_for_dev(dev);
2282
2283 /* Domains are initialized for this device - have a look what we ended up with */
2284 domain = iommu_get_domain_for_dev(dev);
Joerg Roedel32302322015-07-28 16:58:50 +02002285 if (domain->type == IOMMU_DOMAIN_IDENTITY)
Joerg Roedel07ee8692015-05-28 18:41:42 +02002286 dev_data->passthrough = true;
Joerg Roedel32302322015-07-28 16:58:50 +02002287 else
Joerg Roedel07ee8692015-05-28 18:41:42 +02002288 dev->archdata.dma_ops = &amd_iommu_dma_ops;
Joerg Roedele275a2a2008-12-10 18:27:25 +01002289
2290out:
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002291 iommu_completion_wait(iommu);
2292
Joerg Roedele275a2a2008-12-10 18:27:25 +01002293 return 0;
2294}
2295
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002296static void amd_iommu_remove_device(struct device *dev)
Joerg Roedel8638c492009-12-10 11:12:25 +01002297{
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02002298 struct amd_iommu *iommu;
2299 u16 devid;
2300
2301 if (!check_device(dev))
2302 return;
2303
2304 devid = get_device_id(dev);
2305 iommu = amd_iommu_rlookup_table[devid];
2306
2307 iommu_uninit_device(dev);
2308 iommu_completion_wait(iommu);
Joerg Roedel8638c492009-12-10 11:12:25 +01002309}
2310
Joerg Roedel431b2a22008-07-11 17:14:22 +02002311/*****************************************************************************
2312 *
2313 * The next functions belong to the dma_ops mapping/unmapping code.
2314 *
2315 *****************************************************************************/
2316
2317/*
2318 * In the dma_ops path we only have the struct device. This function
2319 * finds the corresponding IOMMU, the protection domain and the
2320 * requestor id for a given device.
2321 * If the device is not yet associated with a domain this is also done
2322 * in this function.
2323 */
Joerg Roedel94f6d192009-11-24 16:40:02 +01002324static struct protection_domain *get_domain(struct device *dev)
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002325{
Joerg Roedel94f6d192009-11-24 16:40:02 +01002326 struct protection_domain *domain;
Joerg Roedel063071d2015-05-28 18:41:38 +02002327 struct iommu_domain *io_domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002328
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002329 if (!check_device(dev))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002330 return ERR_PTR(-EINVAL);
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002331
Joerg Roedel063071d2015-05-28 18:41:38 +02002332 io_domain = iommu_get_domain_for_dev(dev);
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002333 if (!io_domain)
2334 return NULL;
Joerg Roedel063071d2015-05-28 18:41:38 +02002335
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002336 domain = to_pdomain(io_domain);
2337 if (!dma_ops_domain(domain))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002338 return ERR_PTR(-EBUSY);
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002339
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002340 return domain;
Joerg Roedelb20ac0d2008-06-26 21:27:59 +02002341}
2342
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002343static void update_device_table(struct protection_domain *domain)
2344{
Joerg Roedel492667d2009-11-27 13:25:47 +01002345 struct iommu_dev_data *dev_data;
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002346
Joerg Roedelea61cdd2011-06-09 12:56:30 +02002347 list_for_each_entry(dev_data, &domain->dev_list, list)
2348 set_dte_entry(dev_data->devid, domain, dev_data->ats.enabled);
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002349}
2350
2351static void update_domain(struct protection_domain *domain)
2352{
2353 if (!domain->updated)
2354 return;
2355
2356 update_device_table(domain);
Joerg Roedel17b124b2011-04-06 18:01:35 +02002357
2358 domain_flush_devices(domain);
2359 domain_flush_tlb_pde(domain);
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002360
2361 domain->updated = false;
2362}
2363
Joerg Roedel431b2a22008-07-11 17:14:22 +02002364/*
Joerg Roedel8bda3092009-05-12 12:02:46 +02002365 * This function fetches the PTE for a given address in the aperture
2366 */
2367static u64* dma_ops_get_pte(struct dma_ops_domain *dom,
2368 unsigned long address)
2369{
Joerg Roedel384de722009-05-15 12:30:05 +02002370 struct aperture_range *aperture;
Joerg Roedel8bda3092009-05-12 12:02:46 +02002371 u64 *pte, *pte_page;
2372
Joerg Roedel384de722009-05-15 12:30:05 +02002373 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2374 if (!aperture)
2375 return NULL;
2376
2377 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
Joerg Roedel8bda3092009-05-12 12:02:46 +02002378 if (!pte) {
Joerg Roedelcbb9d722010-01-15 14:41:15 +01002379 pte = alloc_pte(&dom->domain, address, PAGE_SIZE, &pte_page,
Joerg Roedelabdc5eb2009-09-03 11:33:51 +02002380 GFP_ATOMIC);
Joerg Roedel384de722009-05-15 12:30:05 +02002381 aperture->pte_pages[APERTURE_PAGE_INDEX(address)] = pte_page;
2382 } else
Joerg Roedel8c8c1432009-09-02 17:30:00 +02002383 pte += PM_LEVEL_INDEX(0, address);
Joerg Roedel8bda3092009-05-12 12:02:46 +02002384
Joerg Roedel04bfdd82009-09-02 16:00:23 +02002385 update_domain(&dom->domain);
Joerg Roedel8bda3092009-05-12 12:02:46 +02002386
2387 return pte;
2388}
2389
2390/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002391 * This is the generic map function. It maps one 4kb page at paddr to
2392 * the given address in the DMA address space for the domain.
2393 */
Joerg Roedel680525e2009-11-23 18:44:42 +01002394static dma_addr_t dma_ops_domain_map(struct dma_ops_domain *dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002395 unsigned long address,
2396 phys_addr_t paddr,
2397 int direction)
2398{
2399 u64 *pte, __pte;
2400
2401 WARN_ON(address > dom->aperture_size);
2402
2403 paddr &= PAGE_MASK;
2404
Joerg Roedel8bda3092009-05-12 12:02:46 +02002405 pte = dma_ops_get_pte(dom, address);
Joerg Roedel53812c12009-05-12 12:17:38 +02002406 if (!pte)
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002407 return DMA_ERROR_CODE;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002408
2409 __pte = paddr | IOMMU_PTE_P | IOMMU_PTE_FC;
2410
2411 if (direction == DMA_TO_DEVICE)
2412 __pte |= IOMMU_PTE_IR;
2413 else if (direction == DMA_FROM_DEVICE)
2414 __pte |= IOMMU_PTE_IW;
2415 else if (direction == DMA_BIDIRECTIONAL)
2416 __pte |= IOMMU_PTE_IR | IOMMU_PTE_IW;
2417
2418 WARN_ON(*pte);
2419
2420 *pte = __pte;
2421
2422 return (dma_addr_t)address;
2423}
2424
Joerg Roedel431b2a22008-07-11 17:14:22 +02002425/*
2426 * The generic unmapping function for on page in the DMA address space.
2427 */
Joerg Roedel680525e2009-11-23 18:44:42 +01002428static void dma_ops_domain_unmap(struct dma_ops_domain *dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002429 unsigned long address)
2430{
Joerg Roedel384de722009-05-15 12:30:05 +02002431 struct aperture_range *aperture;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002432 u64 *pte;
2433
2434 if (address >= dom->aperture_size)
2435 return;
2436
Joerg Roedel384de722009-05-15 12:30:05 +02002437 aperture = dom->aperture[APERTURE_RANGE_INDEX(address)];
2438 if (!aperture)
2439 return;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002440
Joerg Roedel384de722009-05-15 12:30:05 +02002441 pte = aperture->pte_pages[APERTURE_PAGE_INDEX(address)];
2442 if (!pte)
2443 return;
2444
Joerg Roedel8c8c1432009-09-02 17:30:00 +02002445 pte += PM_LEVEL_INDEX(0, address);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002446
2447 WARN_ON(!*pte);
2448
2449 *pte = 0ULL;
2450}
2451
Joerg Roedel431b2a22008-07-11 17:14:22 +02002452/*
2453 * This function contains common code for mapping of a physically
Joerg Roedel24f81162008-12-08 14:25:39 +01002454 * contiguous memory region into DMA address space. It is used by all
2455 * mapping functions provided with this IOMMU driver.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002456 * Must be called with the domain lock held.
2457 */
Joerg Roedelcb76c322008-06-26 21:28:00 +02002458static dma_addr_t __map_single(struct device *dev,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002459 struct dma_ops_domain *dma_dom,
2460 phys_addr_t paddr,
2461 size_t size,
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002462 int dir,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002463 bool align,
2464 u64 dma_mask)
Joerg Roedelcb76c322008-06-26 21:28:00 +02002465{
2466 dma_addr_t offset = paddr & ~PAGE_MASK;
Joerg Roedel53812c12009-05-12 12:17:38 +02002467 dma_addr_t address, start, ret;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002468 unsigned int pages;
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002469 unsigned long align_mask = 0;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002470 int i;
2471
Joerg Roedele3c449f2008-10-15 22:02:11 -07002472 pages = iommu_num_pages(paddr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002473 paddr &= PAGE_MASK;
2474
Joerg Roedel8ecaf8f2008-12-12 16:13:04 +01002475 INC_STATS_COUNTER(total_map_requests);
2476
Joerg Roedelc1858972008-12-12 15:42:39 +01002477 if (pages > 1)
2478 INC_STATS_COUNTER(cross_page);
2479
Joerg Roedel6d4f3432008-09-04 19:18:02 +02002480 if (align)
2481 align_mask = (1UL << get_order(size)) - 1;
2482
Joerg Roedel11b83882009-05-19 10:23:15 +02002483retry:
Joerg Roedel832a90c2008-09-18 15:54:23 +02002484 address = dma_ops_alloc_addresses(dev, dma_dom, pages, align_mask,
2485 dma_mask);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002486 if (unlikely(address == DMA_ERROR_CODE)) {
Joerg Roedel11b83882009-05-19 10:23:15 +02002487 /*
2488 * setting next_address here will let the address
2489 * allocator only scan the new allocated range in the
2490 * first run. This is a small optimization.
2491 */
2492 dma_dom->next_address = dma_dom->aperture_size;
2493
Joerg Roedel576175c2009-11-23 19:08:46 +01002494 if (alloc_new_range(dma_dom, false, GFP_ATOMIC))
Joerg Roedel11b83882009-05-19 10:23:15 +02002495 goto out;
2496
2497 /*
André Goddard Rosaaf901ca2009-11-14 13:09:05 -02002498 * aperture was successfully enlarged by 128 MB, try
Joerg Roedel11b83882009-05-19 10:23:15 +02002499 * allocation again
2500 */
2501 goto retry;
2502 }
Joerg Roedelcb76c322008-06-26 21:28:00 +02002503
2504 start = address;
2505 for (i = 0; i < pages; ++i) {
Joerg Roedel680525e2009-11-23 18:44:42 +01002506 ret = dma_ops_domain_map(dma_dom, start, paddr, dir);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002507 if (ret == DMA_ERROR_CODE)
Joerg Roedel53812c12009-05-12 12:17:38 +02002508 goto out_unmap;
2509
Joerg Roedelcb76c322008-06-26 21:28:00 +02002510 paddr += PAGE_SIZE;
2511 start += PAGE_SIZE;
2512 }
2513 address += offset;
2514
Joerg Roedel5774f7c2008-12-12 15:57:30 +01002515 ADD_STATS_COUNTER(alloced_io_mem, size);
2516
FUJITA Tomonoriafa9fdc2008-09-20 01:23:30 +09002517 if (unlikely(dma_dom->need_flush && !amd_iommu_unmap_flush)) {
Joerg Roedel17b124b2011-04-06 18:01:35 +02002518 domain_flush_tlb(&dma_dom->domain);
Joerg Roedel1c655772008-09-04 18:40:05 +02002519 dma_dom->need_flush = false;
Joerg Roedel318afd42009-11-23 18:32:38 +01002520 } else if (unlikely(amd_iommu_np_cache))
Joerg Roedel17b124b2011-04-06 18:01:35 +02002521 domain_flush_pages(&dma_dom->domain, address, size);
Joerg Roedel270cab242008-09-04 15:49:46 +02002522
Joerg Roedelcb76c322008-06-26 21:28:00 +02002523out:
2524 return address;
Joerg Roedel53812c12009-05-12 12:17:38 +02002525
2526out_unmap:
2527
2528 for (--i; i >= 0; --i) {
2529 start -= PAGE_SIZE;
Joerg Roedel680525e2009-11-23 18:44:42 +01002530 dma_ops_domain_unmap(dma_dom, start);
Joerg Roedel53812c12009-05-12 12:17:38 +02002531 }
2532
2533 dma_ops_free_addresses(dma_dom, address, pages);
2534
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002535 return DMA_ERROR_CODE;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002536}
2537
Joerg Roedel431b2a22008-07-11 17:14:22 +02002538/*
2539 * Does the reverse of the __map_single function. Must be called with
2540 * the domain lock held too
2541 */
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002542static void __unmap_single(struct dma_ops_domain *dma_dom,
Joerg Roedelcb76c322008-06-26 21:28:00 +02002543 dma_addr_t dma_addr,
2544 size_t size,
2545 int dir)
2546{
Joerg Roedel04e04632010-09-23 16:12:48 +02002547 dma_addr_t flush_addr;
Joerg Roedelcb76c322008-06-26 21:28:00 +02002548 dma_addr_t i, start;
2549 unsigned int pages;
2550
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002551 if ((dma_addr == DMA_ERROR_CODE) ||
Joerg Roedelb8d99052008-12-08 14:40:26 +01002552 (dma_addr + size > dma_dom->aperture_size))
Joerg Roedelcb76c322008-06-26 21:28:00 +02002553 return;
2554
Joerg Roedel04e04632010-09-23 16:12:48 +02002555 flush_addr = dma_addr;
Joerg Roedele3c449f2008-10-15 22:02:11 -07002556 pages = iommu_num_pages(dma_addr, size, PAGE_SIZE);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002557 dma_addr &= PAGE_MASK;
2558 start = dma_addr;
2559
2560 for (i = 0; i < pages; ++i) {
Joerg Roedel680525e2009-11-23 18:44:42 +01002561 dma_ops_domain_unmap(dma_dom, start);
Joerg Roedelcb76c322008-06-26 21:28:00 +02002562 start += PAGE_SIZE;
2563 }
2564
Joerg Roedel5774f7c2008-12-12 15:57:30 +01002565 SUB_STATS_COUNTER(alloced_io_mem, size);
2566
Joerg Roedelcb76c322008-06-26 21:28:00 +02002567 dma_ops_free_addresses(dma_dom, dma_addr, pages);
Joerg Roedel270cab242008-09-04 15:49:46 +02002568
Joerg Roedel80be3082008-11-06 14:59:05 +01002569 if (amd_iommu_unmap_flush || dma_dom->need_flush) {
Joerg Roedel17b124b2011-04-06 18:01:35 +02002570 domain_flush_pages(&dma_dom->domain, flush_addr, size);
Joerg Roedel80be3082008-11-06 14:59:05 +01002571 dma_dom->need_flush = false;
2572 }
Joerg Roedelcb76c322008-06-26 21:28:00 +02002573}
2574
Joerg Roedel431b2a22008-07-11 17:14:22 +02002575/*
2576 * The exported map_single function for dma_ops.
2577 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002578static dma_addr_t map_page(struct device *dev, struct page *page,
2579 unsigned long offset, size_t size,
2580 enum dma_data_direction dir,
2581 struct dma_attrs *attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002582{
2583 unsigned long flags;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002584 struct protection_domain *domain;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002585 dma_addr_t addr;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002586 u64 dma_mask;
FUJITA Tomonori51491362009-01-05 23:47:25 +09002587 phys_addr_t paddr = page_to_phys(page) + offset;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002588
Joerg Roedel0f2a86f2008-12-12 15:05:16 +01002589 INC_STATS_COUNTER(cnt_map_single);
2590
Joerg Roedel94f6d192009-11-24 16:40:02 +01002591 domain = get_domain(dev);
2592 if (PTR_ERR(domain) == -EINVAL)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002593 return (dma_addr_t)paddr;
Joerg Roedel94f6d192009-11-24 16:40:02 +01002594 else if (IS_ERR(domain))
2595 return DMA_ERROR_CODE;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002596
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002597 dma_mask = *dev->dma_mask;
2598
Joerg Roedel4da70b92008-06-26 21:28:01 +02002599 spin_lock_irqsave(&domain->lock, flags);
Joerg Roedel94f6d192009-11-24 16:40:02 +01002600
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002601 addr = __map_single(dev, domain->priv, paddr, size, dir, false,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002602 dma_mask);
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002603 if (addr == DMA_ERROR_CODE)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002604 goto out;
2605
Joerg Roedel17b124b2011-04-06 18:01:35 +02002606 domain_flush_complete(domain);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002607
2608out:
2609 spin_unlock_irqrestore(&domain->lock, flags);
2610
2611 return addr;
2612}
2613
Joerg Roedel431b2a22008-07-11 17:14:22 +02002614/*
2615 * The exported unmap_single function for dma_ops.
2616 */
FUJITA Tomonori51491362009-01-05 23:47:25 +09002617static void unmap_page(struct device *dev, dma_addr_t dma_addr, size_t size,
2618 enum dma_data_direction dir, struct dma_attrs *attrs)
Joerg Roedel4da70b92008-06-26 21:28:01 +02002619{
2620 unsigned long flags;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002621 struct protection_domain *domain;
Joerg Roedel4da70b92008-06-26 21:28:01 +02002622
Joerg Roedel146a6912008-12-12 15:07:12 +01002623 INC_STATS_COUNTER(cnt_unmap_single);
2624
Joerg Roedel94f6d192009-11-24 16:40:02 +01002625 domain = get_domain(dev);
2626 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002627 return;
2628
Joerg Roedel4da70b92008-06-26 21:28:01 +02002629 spin_lock_irqsave(&domain->lock, flags);
2630
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002631 __unmap_single(domain->priv, dma_addr, size, dir);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002632
Joerg Roedel17b124b2011-04-06 18:01:35 +02002633 domain_flush_complete(domain);
Joerg Roedel4da70b92008-06-26 21:28:01 +02002634
2635 spin_unlock_irqrestore(&domain->lock, flags);
2636}
2637
Joerg Roedel431b2a22008-07-11 17:14:22 +02002638/*
Joerg Roedel431b2a22008-07-11 17:14:22 +02002639 * The exported map_sg function for dma_ops (handles scatter-gather
2640 * lists).
2641 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002642static int map_sg(struct device *dev, struct scatterlist *sglist,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002643 int nelems, enum dma_data_direction dir,
2644 struct dma_attrs *attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002645{
2646 unsigned long flags;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002647 struct protection_domain *domain;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002648 int i;
2649 struct scatterlist *s;
2650 phys_addr_t paddr;
2651 int mapped_elems = 0;
Joerg Roedel832a90c2008-09-18 15:54:23 +02002652 u64 dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002653
Joerg Roedeld03f067a2008-12-12 15:09:48 +01002654 INC_STATS_COUNTER(cnt_map_sg);
2655
Joerg Roedel94f6d192009-11-24 16:40:02 +01002656 domain = get_domain(dev);
Joerg Roedela0e191b2013-04-09 15:04:36 +02002657 if (IS_ERR(domain))
Joerg Roedel94f6d192009-11-24 16:40:02 +01002658 return 0;
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002659
Joerg Roedel832a90c2008-09-18 15:54:23 +02002660 dma_mask = *dev->dma_mask;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002661
Joerg Roedel65b050a2008-06-26 21:28:02 +02002662 spin_lock_irqsave(&domain->lock, flags);
2663
2664 for_each_sg(sglist, s, nelems, i) {
2665 paddr = sg_phys(s);
2666
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002667 s->dma_address = __map_single(dev, domain->priv,
Joerg Roedel832a90c2008-09-18 15:54:23 +02002668 paddr, s->length, dir, false,
2669 dma_mask);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002670
2671 if (s->dma_address) {
2672 s->dma_length = s->length;
2673 mapped_elems++;
2674 } else
2675 goto unmap;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002676 }
2677
Joerg Roedel17b124b2011-04-06 18:01:35 +02002678 domain_flush_complete(domain);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002679
2680out:
2681 spin_unlock_irqrestore(&domain->lock, flags);
2682
2683 return mapped_elems;
2684unmap:
2685 for_each_sg(sglist, s, mapped_elems, i) {
2686 if (s->dma_address)
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002687 __unmap_single(domain->priv, s->dma_address,
Joerg Roedel65b050a2008-06-26 21:28:02 +02002688 s->dma_length, dir);
2689 s->dma_address = s->dma_length = 0;
2690 }
2691
2692 mapped_elems = 0;
2693
2694 goto out;
2695}
2696
Joerg Roedel431b2a22008-07-11 17:14:22 +02002697/*
2698 * The exported map_sg function for dma_ops (handles scatter-gather
2699 * lists).
2700 */
Joerg Roedel65b050a2008-06-26 21:28:02 +02002701static void unmap_sg(struct device *dev, struct scatterlist *sglist,
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002702 int nelems, enum dma_data_direction dir,
2703 struct dma_attrs *attrs)
Joerg Roedel65b050a2008-06-26 21:28:02 +02002704{
2705 unsigned long flags;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002706 struct protection_domain *domain;
2707 struct scatterlist *s;
Joerg Roedel65b050a2008-06-26 21:28:02 +02002708 int i;
2709
Joerg Roedel55877a62008-12-12 15:12:14 +01002710 INC_STATS_COUNTER(cnt_unmap_sg);
2711
Joerg Roedel94f6d192009-11-24 16:40:02 +01002712 domain = get_domain(dev);
2713 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002714 return;
2715
Joerg Roedel65b050a2008-06-26 21:28:02 +02002716 spin_lock_irqsave(&domain->lock, flags);
2717
2718 for_each_sg(sglist, s, nelems, i) {
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002719 __unmap_single(domain->priv, s->dma_address,
Joerg Roedel65b050a2008-06-26 21:28:02 +02002720 s->dma_length, dir);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002721 s->dma_address = s->dma_length = 0;
2722 }
2723
Joerg Roedel17b124b2011-04-06 18:01:35 +02002724 domain_flush_complete(domain);
Joerg Roedel65b050a2008-06-26 21:28:02 +02002725
2726 spin_unlock_irqrestore(&domain->lock, flags);
2727}
2728
Joerg Roedel431b2a22008-07-11 17:14:22 +02002729/*
2730 * The exported alloc_coherent function for dma_ops.
2731 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002732static void *alloc_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002733 dma_addr_t *dma_addr, gfp_t flag,
2734 struct dma_attrs *attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002735{
Joerg Roedel832a90c2008-09-18 15:54:23 +02002736 u64 dma_mask = dev->coherent_dma_mask;
Joerg Roedel3b839a52015-04-01 14:58:47 +02002737 struct protection_domain *domain;
2738 unsigned long flags;
2739 struct page *page;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002740
Joerg Roedelc8f0fb32008-12-12 15:14:21 +01002741 INC_STATS_COUNTER(cnt_alloc_coherent);
2742
Joerg Roedel94f6d192009-11-24 16:40:02 +01002743 domain = get_domain(dev);
2744 if (PTR_ERR(domain) == -EINVAL) {
Joerg Roedel3b839a52015-04-01 14:58:47 +02002745 page = alloc_pages(flag, get_order(size));
2746 *dma_addr = page_to_phys(page);
2747 return page_address(page);
Joerg Roedel94f6d192009-11-24 16:40:02 +01002748 } else if (IS_ERR(domain))
2749 return NULL;
Joerg Roedeldbcc1122008-09-04 15:04:26 +02002750
Joerg Roedel3b839a52015-04-01 14:58:47 +02002751 size = PAGE_ALIGN(size);
Joerg Roedelf99c0f12009-11-23 16:52:56 +01002752 dma_mask = dev->coherent_dma_mask;
2753 flag &= ~(__GFP_DMA | __GFP_HIGHMEM | __GFP_DMA32);
Joerg Roedel2d0ec7a2015-06-01 17:30:57 +02002754 flag |= __GFP_ZERO;
FUJITA Tomonori13d9fea2008-09-10 20:19:40 +09002755
Joerg Roedel3b839a52015-04-01 14:58:47 +02002756 page = alloc_pages(flag | __GFP_NOWARN, get_order(size));
2757 if (!page) {
2758 if (!(flag & __GFP_WAIT))
2759 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002760
Joerg Roedel3b839a52015-04-01 14:58:47 +02002761 page = dma_alloc_from_contiguous(dev, size >> PAGE_SHIFT,
2762 get_order(size));
2763 if (!page)
2764 return NULL;
2765 }
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002766
Joerg Roedel832a90c2008-09-18 15:54:23 +02002767 if (!dma_mask)
2768 dma_mask = *dev->dma_mask;
2769
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002770 spin_lock_irqsave(&domain->lock, flags);
2771
Joerg Roedel3b839a52015-04-01 14:58:47 +02002772 *dma_addr = __map_single(dev, domain->priv, page_to_phys(page),
Joerg Roedel832a90c2008-09-18 15:54:23 +02002773 size, DMA_BIDIRECTIONAL, true, dma_mask);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002774
FUJITA Tomonori8fd524b2009-11-15 21:19:53 +09002775 if (*dma_addr == DMA_ERROR_CODE) {
Jiri Slaby367d04c2009-05-28 09:54:48 +02002776 spin_unlock_irqrestore(&domain->lock, flags);
Joerg Roedel5b28df62008-12-02 17:49:42 +01002777 goto out_free;
Jiri Slaby367d04c2009-05-28 09:54:48 +02002778 }
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002779
Joerg Roedel17b124b2011-04-06 18:01:35 +02002780 domain_flush_complete(domain);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002781
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002782 spin_unlock_irqrestore(&domain->lock, flags);
2783
Joerg Roedel3b839a52015-04-01 14:58:47 +02002784 return page_address(page);
Joerg Roedel5b28df62008-12-02 17:49:42 +01002785
2786out_free:
2787
Joerg Roedel3b839a52015-04-01 14:58:47 +02002788 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2789 __free_pages(page, get_order(size));
Joerg Roedel5b28df62008-12-02 17:49:42 +01002790
2791 return NULL;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002792}
2793
Joerg Roedel431b2a22008-07-11 17:14:22 +02002794/*
2795 * The exported free_coherent function for dma_ops.
Joerg Roedel431b2a22008-07-11 17:14:22 +02002796 */
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002797static void free_coherent(struct device *dev, size_t size,
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002798 void *virt_addr, dma_addr_t dma_addr,
2799 struct dma_attrs *attrs)
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002800{
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002801 struct protection_domain *domain;
Joerg Roedel3b839a52015-04-01 14:58:47 +02002802 unsigned long flags;
2803 struct page *page;
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002804
Joerg Roedel5d31ee72008-12-12 15:16:38 +01002805 INC_STATS_COUNTER(cnt_free_coherent);
2806
Joerg Roedel3b839a52015-04-01 14:58:47 +02002807 page = virt_to_page(virt_addr);
2808 size = PAGE_ALIGN(size);
2809
Joerg Roedel94f6d192009-11-24 16:40:02 +01002810 domain = get_domain(dev);
2811 if (IS_ERR(domain))
Joerg Roedel5b28df62008-12-02 17:49:42 +01002812 goto free_mem;
2813
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002814 spin_lock_irqsave(&domain->lock, flags);
2815
Joerg Roedelcd8c82e2009-11-23 19:33:56 +01002816 __unmap_single(domain->priv, dma_addr, size, DMA_BIDIRECTIONAL);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002817
Joerg Roedel17b124b2011-04-06 18:01:35 +02002818 domain_flush_complete(domain);
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002819
2820 spin_unlock_irqrestore(&domain->lock, flags);
2821
2822free_mem:
Joerg Roedel3b839a52015-04-01 14:58:47 +02002823 if (!dma_release_from_contiguous(dev, page, size >> PAGE_SHIFT))
2824 __free_pages(page, get_order(size));
Joerg Roedel5d8b53c2008-06-26 21:28:03 +02002825}
2826
Joerg Roedelc432f3d2008-06-26 21:28:04 +02002827/*
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002828 * This function is called by the DMA layer to find out if we can handle a
2829 * particular device. It is part of the dma_ops.
2830 */
2831static int amd_iommu_dma_supported(struct device *dev, u64 mask)
2832{
Joerg Roedel420aef82009-11-23 16:14:57 +01002833 return check_device(dev);
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002834}
2835
FUJITA Tomonori160c1d82009-01-05 23:59:02 +09002836static struct dma_map_ops amd_iommu_dma_ops = {
Andrzej Pietrasiewiczbaa676f2012-03-27 14:28:18 +02002837 .alloc = alloc_coherent,
2838 .free = free_coherent,
FUJITA Tomonori51491362009-01-05 23:47:25 +09002839 .map_page = map_page,
2840 .unmap_page = unmap_page,
Joerg Roedel6631ee92008-06-26 21:28:05 +02002841 .map_sg = map_sg,
2842 .unmap_sg = unmap_sg,
Joerg Roedelb39ba6a2008-09-09 18:40:46 +02002843 .dma_supported = amd_iommu_dma_supported,
Joerg Roedel6631ee92008-06-26 21:28:05 +02002844};
2845
Joerg Roedel3a18404c2015-05-28 18:41:45 +02002846int __init amd_iommu_init_api(void)
Joerg Roedel27c21272011-05-30 15:56:24 +02002847{
Joerg Roedel3a18404c2015-05-28 18:41:45 +02002848 return bus_set_iommu(&pci_bus_type, &amd_iommu_ops);
Joerg Roedelf5325092010-01-22 17:44:35 +01002849}
2850
Joerg Roedel6631ee92008-06-26 21:28:05 +02002851int __init amd_iommu_init_dma_ops(void)
2852{
Joerg Roedel32302322015-07-28 16:58:50 +02002853 swiotlb = iommu_pass_through ? 1 : 0;
Joerg Roedel6631ee92008-06-26 21:28:05 +02002854 iommu_detected = 1;
Joerg Roedel6631ee92008-06-26 21:28:05 +02002855
Joerg Roedel52717822015-07-28 16:58:51 +02002856 /*
2857 * In case we don't initialize SWIOTLB (actually the common case
2858 * when AMD IOMMU is enabled), make sure there are global
2859 * dma_ops set as a fall-back for devices not handled by this
2860 * driver (for example non-PCI devices).
2861 */
2862 if (!swiotlb)
2863 dma_ops = &nommu_dma_ops;
2864
Joerg Roedel7f265082008-12-12 13:50:21 +01002865 amd_iommu_stats_init();
2866
Joerg Roedel62410ee2012-06-12 16:42:43 +02002867 if (amd_iommu_unmap_flush)
2868 pr_info("AMD-Vi: IO/TLB flush on unmap enabled\n");
2869 else
2870 pr_info("AMD-Vi: Lazy IO/TLB flushing enabled\n");
2871
Joerg Roedel6631ee92008-06-26 21:28:05 +02002872 return 0;
Joerg Roedel6631ee92008-06-26 21:28:05 +02002873}
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002874
2875/*****************************************************************************
2876 *
2877 * The following functions belong to the exported interface of AMD IOMMU
2878 *
2879 * This interface allows access to lower level functions of the IOMMU
2880 * like protection domain handling and assignement of devices to domains
2881 * which is not possible with the dma_ops interface.
2882 *
2883 *****************************************************************************/
2884
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002885static void cleanup_domain(struct protection_domain *domain)
2886{
Joerg Roedel9b29d3c2014-08-05 17:50:15 +02002887 struct iommu_dev_data *entry;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002888 unsigned long flags;
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002889
2890 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
2891
Joerg Roedel9b29d3c2014-08-05 17:50:15 +02002892 while (!list_empty(&domain->dev_list)) {
2893 entry = list_first_entry(&domain->dev_list,
2894 struct iommu_dev_data, list);
2895 __detach_device(entry);
Joerg Roedel492667d2009-11-27 13:25:47 +01002896 }
Joerg Roedel6d98cd82008-12-08 12:05:55 +01002897
2898 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
2899}
2900
Joerg Roedel26508152009-08-26 16:52:40 +02002901static void protection_domain_free(struct protection_domain *domain)
2902{
2903 if (!domain)
2904 return;
2905
Joerg Roedelaeb26f52009-11-20 16:44:01 +01002906 del_domain_from_list(domain);
2907
Joerg Roedel26508152009-08-26 16:52:40 +02002908 if (domain->id)
2909 domain_id_free(domain->id);
2910
2911 kfree(domain);
2912}
2913
Joerg Roedel7a5a5662015-06-30 08:56:11 +02002914static int protection_domain_init(struct protection_domain *domain)
2915{
2916 spin_lock_init(&domain->lock);
2917 mutex_init(&domain->api_lock);
2918 domain->id = domain_id_alloc();
2919 if (!domain->id)
2920 return -ENOMEM;
2921 INIT_LIST_HEAD(&domain->dev_list);
2922
2923 return 0;
2924}
2925
Joerg Roedel26508152009-08-26 16:52:40 +02002926static struct protection_domain *protection_domain_alloc(void)
Joerg Roedelc156e342008-12-02 18:13:27 +01002927{
2928 struct protection_domain *domain;
2929
2930 domain = kzalloc(sizeof(*domain), GFP_KERNEL);
2931 if (!domain)
Joerg Roedel26508152009-08-26 16:52:40 +02002932 return NULL;
Joerg Roedelc156e342008-12-02 18:13:27 +01002933
Joerg Roedel7a5a5662015-06-30 08:56:11 +02002934 if (protection_domain_init(domain))
Joerg Roedel26508152009-08-26 16:52:40 +02002935 goto out_err;
2936
Joerg Roedelaeb26f52009-11-20 16:44:01 +01002937 add_domain_to_list(domain);
2938
Joerg Roedel26508152009-08-26 16:52:40 +02002939 return domain;
2940
2941out_err:
2942 kfree(domain);
2943
2944 return NULL;
2945}
2946
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002947static struct iommu_domain *amd_iommu_domain_alloc(unsigned type)
2948{
2949 struct protection_domain *pdomain;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002950 struct dma_ops_domain *dma_domain;
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002951
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002952 switch (type) {
2953 case IOMMU_DOMAIN_UNMANAGED:
2954 pdomain = protection_domain_alloc();
2955 if (!pdomain)
2956 return NULL;
2957
2958 pdomain->mode = PAGE_MODE_3_LEVEL;
2959 pdomain->pt_root = (void *)get_zeroed_page(GFP_KERNEL);
2960 if (!pdomain->pt_root) {
2961 protection_domain_free(pdomain);
2962 return NULL;
2963 }
2964
2965 pdomain->domain.geometry.aperture_start = 0;
2966 pdomain->domain.geometry.aperture_end = ~0ULL;
2967 pdomain->domain.geometry.force_aperture = true;
2968
2969 break;
2970 case IOMMU_DOMAIN_DMA:
2971 dma_domain = dma_ops_domain_alloc();
2972 if (!dma_domain) {
2973 pr_err("AMD-Vi: Failed to allocate\n");
2974 return NULL;
2975 }
2976 pdomain = &dma_domain->domain;
2977 break;
Joerg Roedel07f643a2015-05-28 18:41:41 +02002978 case IOMMU_DOMAIN_IDENTITY:
2979 pdomain = protection_domain_alloc();
2980 if (!pdomain)
2981 return NULL;
2982
2983 pdomain->mode = PAGE_MODE_NONE;
2984 break;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002985 default:
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002986 return NULL;
Joerg Roedel0bb6e242015-05-28 18:41:40 +02002987 }
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002988
2989 return &pdomain->domain;
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002990}
2991
2992static void amd_iommu_domain_free(struct iommu_domain *dom)
Joerg Roedel26508152009-08-26 16:52:40 +02002993{
2994 struct protection_domain *domain;
2995
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002996 if (!dom)
Joerg Roedel98383fc2008-12-02 18:34:12 +01002997 return;
2998
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01002999 domain = to_pdomain(dom);
3000
Joerg Roedel98383fc2008-12-02 18:34:12 +01003001 if (domain->dev_cnt > 0)
3002 cleanup_domain(domain);
3003
3004 BUG_ON(domain->dev_cnt != 0);
3005
Joerg Roedel132bd682011-11-17 14:18:46 +01003006 if (domain->mode != PAGE_MODE_NONE)
3007 free_pagetable(domain);
Joerg Roedel98383fc2008-12-02 18:34:12 +01003008
Joerg Roedel52815b72011-11-17 17:24:28 +01003009 if (domain->flags & PD_IOMMUV2_MASK)
3010 free_gcr3_table(domain);
3011
Joerg Roedel8b408fe2010-03-08 14:20:07 +01003012 protection_domain_free(domain);
Joerg Roedel98383fc2008-12-02 18:34:12 +01003013}
3014
Joerg Roedel684f2882008-12-08 12:07:44 +01003015static void amd_iommu_detach_device(struct iommu_domain *dom,
3016 struct device *dev)
3017{
Joerg Roedel657cbb62009-11-23 15:26:46 +01003018 struct iommu_dev_data *dev_data = dev->archdata.iommu;
Joerg Roedel684f2882008-12-08 12:07:44 +01003019 struct amd_iommu *iommu;
Joerg Roedel684f2882008-12-08 12:07:44 +01003020 u16 devid;
3021
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003022 if (!check_device(dev))
Joerg Roedel684f2882008-12-08 12:07:44 +01003023 return;
3024
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003025 devid = get_device_id(dev);
Joerg Roedel684f2882008-12-08 12:07:44 +01003026
Joerg Roedel657cbb62009-11-23 15:26:46 +01003027 if (dev_data->domain != NULL)
Joerg Roedel15898bb2009-11-24 15:39:42 +01003028 detach_device(dev);
Joerg Roedel684f2882008-12-08 12:07:44 +01003029
3030 iommu = amd_iommu_rlookup_table[devid];
3031 if (!iommu)
3032 return;
3033
Joerg Roedel684f2882008-12-08 12:07:44 +01003034 iommu_completion_wait(iommu);
3035}
3036
Joerg Roedel01106062008-12-02 19:34:11 +01003037static int amd_iommu_attach_device(struct iommu_domain *dom,
3038 struct device *dev)
3039{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003040 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel657cbb62009-11-23 15:26:46 +01003041 struct iommu_dev_data *dev_data;
Joerg Roedel01106062008-12-02 19:34:11 +01003042 struct amd_iommu *iommu;
Joerg Roedel15898bb2009-11-24 15:39:42 +01003043 int ret;
Joerg Roedel01106062008-12-02 19:34:11 +01003044
Joerg Roedel98fc5a62009-11-24 17:19:23 +01003045 if (!check_device(dev))
Joerg Roedel01106062008-12-02 19:34:11 +01003046 return -EINVAL;
3047
Joerg Roedel657cbb62009-11-23 15:26:46 +01003048 dev_data = dev->archdata.iommu;
3049
Joerg Roedelf62dda62011-06-09 12:55:35 +02003050 iommu = amd_iommu_rlookup_table[dev_data->devid];
Joerg Roedel01106062008-12-02 19:34:11 +01003051 if (!iommu)
3052 return -EINVAL;
3053
Joerg Roedel657cbb62009-11-23 15:26:46 +01003054 if (dev_data->domain)
Joerg Roedel15898bb2009-11-24 15:39:42 +01003055 detach_device(dev);
Joerg Roedel01106062008-12-02 19:34:11 +01003056
Joerg Roedel15898bb2009-11-24 15:39:42 +01003057 ret = attach_device(dev, domain);
Joerg Roedel01106062008-12-02 19:34:11 +01003058
3059 iommu_completion_wait(iommu);
3060
Joerg Roedel15898bb2009-11-24 15:39:42 +01003061 return ret;
Joerg Roedel01106062008-12-02 19:34:11 +01003062}
3063
Joerg Roedel468e2362010-01-21 16:37:36 +01003064static int amd_iommu_map(struct iommu_domain *dom, unsigned long iova,
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003065 phys_addr_t paddr, size_t page_size, int iommu_prot)
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003066{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003067 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003068 int prot = 0;
3069 int ret;
3070
Joerg Roedel132bd682011-11-17 14:18:46 +01003071 if (domain->mode == PAGE_MODE_NONE)
3072 return -EINVAL;
3073
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003074 if (iommu_prot & IOMMU_READ)
3075 prot |= IOMMU_PROT_IR;
3076 if (iommu_prot & IOMMU_WRITE)
3077 prot |= IOMMU_PROT_IW;
3078
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003079 mutex_lock(&domain->api_lock);
Joerg Roedel795e74f2010-05-11 17:40:57 +02003080 ret = iommu_map_page(domain, iova, paddr, prot, page_size);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003081 mutex_unlock(&domain->api_lock);
3082
Joerg Roedel795e74f2010-05-11 17:40:57 +02003083 return ret;
Joerg Roedelc6229ca2008-12-02 19:48:43 +01003084}
3085
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003086static size_t amd_iommu_unmap(struct iommu_domain *dom, unsigned long iova,
3087 size_t page_size)
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003088{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003089 struct protection_domain *domain = to_pdomain(dom);
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003090 size_t unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003091
Joerg Roedel132bd682011-11-17 14:18:46 +01003092 if (domain->mode == PAGE_MODE_NONE)
3093 return -EINVAL;
3094
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003095 mutex_lock(&domain->api_lock);
Joerg Roedel468e2362010-01-21 16:37:36 +01003096 unmap_size = iommu_unmap_page(domain, iova, page_size);
Joerg Roedel795e74f2010-05-11 17:40:57 +02003097 mutex_unlock(&domain->api_lock);
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003098
Joerg Roedel17b124b2011-04-06 18:01:35 +02003099 domain_flush_tlb_pde(domain);
Joerg Roedel5d214fe2010-02-08 14:44:49 +01003100
Ohad Ben-Cohen50090652011-11-10 11:32:25 +02003101 return unmap_size;
Joerg Roedeleb74ff62008-12-02 19:59:10 +01003102}
3103
Joerg Roedel645c4c82008-12-02 20:05:50 +01003104static phys_addr_t amd_iommu_iova_to_phys(struct iommu_domain *dom,
Varun Sethibb5547ac2013-03-29 01:23:58 +05303105 dma_addr_t iova)
Joerg Roedel645c4c82008-12-02 20:05:50 +01003106{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003107 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel3039ca12015-04-01 14:58:48 +02003108 unsigned long offset_mask, pte_pgsize;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003109 u64 *pte, __pte;
Joerg Roedel645c4c82008-12-02 20:05:50 +01003110
Joerg Roedel132bd682011-11-17 14:18:46 +01003111 if (domain->mode == PAGE_MODE_NONE)
3112 return iova;
3113
Joerg Roedel3039ca12015-04-01 14:58:48 +02003114 pte = fetch_pte(domain, iova, &pte_pgsize);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003115
Joerg Roedela6d41a42009-09-02 17:08:55 +02003116 if (!pte || !IOMMU_PTE_PRESENT(*pte))
Joerg Roedel645c4c82008-12-02 20:05:50 +01003117 return 0;
3118
Joerg Roedelb24b1b62015-04-01 14:58:51 +02003119 offset_mask = pte_pgsize - 1;
3120 __pte = *pte & PM_ADDR_MASK;
Joerg Roedelf03152b2010-01-21 16:15:24 +01003121
Joerg Roedelb24b1b62015-04-01 14:58:51 +02003122 return (__pte & ~offset_mask) | (iova & offset_mask);
Joerg Roedel645c4c82008-12-02 20:05:50 +01003123}
3124
Joerg Roedelab636482014-09-05 10:48:21 +02003125static bool amd_iommu_capable(enum iommu_cap cap)
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003126{
Joerg Roedel80a506b2010-07-27 17:14:24 +02003127 switch (cap) {
3128 case IOMMU_CAP_CACHE_COHERENCY:
Joerg Roedelab636482014-09-05 10:48:21 +02003129 return true;
Joerg Roedelbdddadc2012-07-02 18:38:13 +02003130 case IOMMU_CAP_INTR_REMAP:
Joerg Roedelab636482014-09-05 10:48:21 +02003131 return (irq_remapping_enabled == 1);
Will Deaconcfdeec22014-10-27 11:24:48 +00003132 case IOMMU_CAP_NOEXEC:
3133 return false;
Joerg Roedel80a506b2010-07-27 17:14:24 +02003134 }
3135
Joerg Roedelab636482014-09-05 10:48:21 +02003136 return false;
Sheng Yangdbb9fd82009-03-18 15:33:06 +08003137}
3138
Joerg Roedel35cf2482015-05-28 18:41:37 +02003139static void amd_iommu_get_dm_regions(struct device *dev,
3140 struct list_head *head)
3141{
3142 struct unity_map_entry *entry;
3143 u16 devid;
3144
3145 devid = get_device_id(dev);
3146
3147 list_for_each_entry(entry, &amd_iommu_unity_map, list) {
3148 struct iommu_dm_region *region;
3149
3150 if (devid < entry->devid_start || devid > entry->devid_end)
3151 continue;
3152
3153 region = kzalloc(sizeof(*region), GFP_KERNEL);
3154 if (!region) {
3155 pr_err("Out of memory allocating dm-regions for %s\n",
3156 dev_name(dev));
3157 return;
3158 }
3159
3160 region->start = entry->address_start;
3161 region->length = entry->address_end - entry->address_start;
3162 if (entry->prot & IOMMU_PROT_IR)
3163 region->prot |= IOMMU_READ;
3164 if (entry->prot & IOMMU_PROT_IW)
3165 region->prot |= IOMMU_WRITE;
3166
3167 list_add_tail(&region->list, head);
3168 }
3169}
3170
3171static void amd_iommu_put_dm_regions(struct device *dev,
3172 struct list_head *head)
3173{
3174 struct iommu_dm_region *entry, *next;
3175
3176 list_for_each_entry_safe(entry, next, head, list)
3177 kfree(entry);
3178}
3179
Thierry Redingb22f6432014-06-27 09:03:12 +02003180static const struct iommu_ops amd_iommu_ops = {
Joerg Roedelab636482014-09-05 10:48:21 +02003181 .capable = amd_iommu_capable,
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003182 .domain_alloc = amd_iommu_domain_alloc,
3183 .domain_free = amd_iommu_domain_free,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003184 .attach_dev = amd_iommu_attach_device,
3185 .detach_dev = amd_iommu_detach_device,
Joerg Roedel468e2362010-01-21 16:37:36 +01003186 .map = amd_iommu_map,
3187 .unmap = amd_iommu_unmap,
Olav Haugan315786e2014-10-25 09:55:16 -07003188 .map_sg = default_iommu_map_sg,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003189 .iova_to_phys = amd_iommu_iova_to_phys,
Joerg Roedelaafd8ba2015-05-28 18:41:39 +02003190 .add_device = amd_iommu_add_device,
3191 .remove_device = amd_iommu_remove_device,
Joerg Roedel35cf2482015-05-28 18:41:37 +02003192 .get_dm_regions = amd_iommu_get_dm_regions,
3193 .put_dm_regions = amd_iommu_put_dm_regions,
Ohad Ben-Cohenaa3de9c2011-11-10 11:32:29 +02003194 .pgsize_bitmap = AMD_IOMMU_PGSIZES,
Joerg Roedel26961ef2008-12-03 17:00:17 +01003195};
3196
Joerg Roedel0feae532009-08-26 15:26:30 +02003197/*****************************************************************************
3198 *
3199 * The next functions do a basic initialization of IOMMU for pass through
3200 * mode
3201 *
3202 * In passthrough mode the IOMMU is initialized and enabled but not used for
3203 * DMA-API translation.
3204 *
3205 *****************************************************************************/
3206
Joerg Roedel72e1dcc2011-11-10 19:13:51 +01003207/* IOMMUv2 specific functions */
3208int amd_iommu_register_ppr_notifier(struct notifier_block *nb)
3209{
3210 return atomic_notifier_chain_register(&ppr_notifier, nb);
3211}
3212EXPORT_SYMBOL(amd_iommu_register_ppr_notifier);
3213
3214int amd_iommu_unregister_ppr_notifier(struct notifier_block *nb)
3215{
3216 return atomic_notifier_chain_unregister(&ppr_notifier, nb);
3217}
3218EXPORT_SYMBOL(amd_iommu_unregister_ppr_notifier);
Joerg Roedel132bd682011-11-17 14:18:46 +01003219
3220void amd_iommu_domain_direct_map(struct iommu_domain *dom)
3221{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003222 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel132bd682011-11-17 14:18:46 +01003223 unsigned long flags;
3224
3225 spin_lock_irqsave(&domain->lock, flags);
3226
3227 /* Update data structure */
3228 domain->mode = PAGE_MODE_NONE;
3229 domain->updated = true;
3230
3231 /* Make changes visible to IOMMUs */
3232 update_domain(domain);
3233
3234 /* Page-table is not visible to IOMMU anymore, so free it */
3235 free_pagetable(domain);
3236
3237 spin_unlock_irqrestore(&domain->lock, flags);
3238}
3239EXPORT_SYMBOL(amd_iommu_domain_direct_map);
Joerg Roedel52815b72011-11-17 17:24:28 +01003240
3241int amd_iommu_domain_enable_v2(struct iommu_domain *dom, int pasids)
3242{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003243 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel52815b72011-11-17 17:24:28 +01003244 unsigned long flags;
3245 int levels, ret;
3246
3247 if (pasids <= 0 || pasids > (PASID_MASK + 1))
3248 return -EINVAL;
3249
3250 /* Number of GCR3 table levels required */
3251 for (levels = 0; (pasids - 1) & ~0x1ff; pasids >>= 9)
3252 levels += 1;
3253
3254 if (levels > amd_iommu_max_glx_val)
3255 return -EINVAL;
3256
3257 spin_lock_irqsave(&domain->lock, flags);
3258
3259 /*
3260 * Save us all sanity checks whether devices already in the
3261 * domain support IOMMUv2. Just force that the domain has no
3262 * devices attached when it is switched into IOMMUv2 mode.
3263 */
3264 ret = -EBUSY;
3265 if (domain->dev_cnt > 0 || domain->flags & PD_IOMMUV2_MASK)
3266 goto out;
3267
3268 ret = -ENOMEM;
3269 domain->gcr3_tbl = (void *)get_zeroed_page(GFP_ATOMIC);
3270 if (domain->gcr3_tbl == NULL)
3271 goto out;
3272
3273 domain->glx = levels;
3274 domain->flags |= PD_IOMMUV2_MASK;
3275 domain->updated = true;
3276
3277 update_domain(domain);
3278
3279 ret = 0;
3280
3281out:
3282 spin_unlock_irqrestore(&domain->lock, flags);
3283
3284 return ret;
3285}
3286EXPORT_SYMBOL(amd_iommu_domain_enable_v2);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003287
3288static int __flush_pasid(struct protection_domain *domain, int pasid,
3289 u64 address, bool size)
3290{
3291 struct iommu_dev_data *dev_data;
3292 struct iommu_cmd cmd;
3293 int i, ret;
3294
3295 if (!(domain->flags & PD_IOMMUV2_MASK))
3296 return -EINVAL;
3297
3298 build_inv_iommu_pasid(&cmd, domain->id, pasid, address, size);
3299
3300 /*
3301 * IOMMU TLB needs to be flushed before Device TLB to
3302 * prevent device TLB refill from IOMMU TLB
3303 */
3304 for (i = 0; i < amd_iommus_present; ++i) {
3305 if (domain->dev_iommu[i] == 0)
3306 continue;
3307
3308 ret = iommu_queue_command(amd_iommus[i], &cmd);
3309 if (ret != 0)
3310 goto out;
3311 }
3312
3313 /* Wait until IOMMU TLB flushes are complete */
3314 domain_flush_complete(domain);
3315
3316 /* Now flush device TLBs */
3317 list_for_each_entry(dev_data, &domain->dev_list, list) {
3318 struct amd_iommu *iommu;
3319 int qdep;
3320
Joerg Roedel1c1cc452015-07-30 11:24:45 +02003321 /*
3322 There might be non-IOMMUv2 capable devices in an IOMMUv2
3323 * domain.
3324 */
3325 if (!dev_data->ats.enabled)
3326 continue;
Joerg Roedel22e266c2011-11-21 15:59:08 +01003327
3328 qdep = dev_data->ats.qdep;
3329 iommu = amd_iommu_rlookup_table[dev_data->devid];
3330
3331 build_inv_iotlb_pasid(&cmd, dev_data->devid, pasid,
3332 qdep, address, size);
3333
3334 ret = iommu_queue_command(iommu, &cmd);
3335 if (ret != 0)
3336 goto out;
3337 }
3338
3339 /* Wait until all device TLBs are flushed */
3340 domain_flush_complete(domain);
3341
3342 ret = 0;
3343
3344out:
3345
3346 return ret;
3347}
3348
3349static int __amd_iommu_flush_page(struct protection_domain *domain, int pasid,
3350 u64 address)
3351{
Joerg Roedel399be2f2011-12-01 16:53:47 +01003352 INC_STATS_COUNTER(invalidate_iotlb);
3353
Joerg Roedel22e266c2011-11-21 15:59:08 +01003354 return __flush_pasid(domain, pasid, address, false);
3355}
3356
3357int amd_iommu_flush_page(struct iommu_domain *dom, int pasid,
3358 u64 address)
3359{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003360 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003361 unsigned long flags;
3362 int ret;
3363
3364 spin_lock_irqsave(&domain->lock, flags);
3365 ret = __amd_iommu_flush_page(domain, pasid, address);
3366 spin_unlock_irqrestore(&domain->lock, flags);
3367
3368 return ret;
3369}
3370EXPORT_SYMBOL(amd_iommu_flush_page);
3371
3372static int __amd_iommu_flush_tlb(struct protection_domain *domain, int pasid)
3373{
Joerg Roedel399be2f2011-12-01 16:53:47 +01003374 INC_STATS_COUNTER(invalidate_iotlb_all);
3375
Joerg Roedel22e266c2011-11-21 15:59:08 +01003376 return __flush_pasid(domain, pasid, CMD_INV_IOMMU_ALL_PAGES_ADDRESS,
3377 true);
3378}
3379
3380int amd_iommu_flush_tlb(struct iommu_domain *dom, int pasid)
3381{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003382 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedel22e266c2011-11-21 15:59:08 +01003383 unsigned long flags;
3384 int ret;
3385
3386 spin_lock_irqsave(&domain->lock, flags);
3387 ret = __amd_iommu_flush_tlb(domain, pasid);
3388 spin_unlock_irqrestore(&domain->lock, flags);
3389
3390 return ret;
3391}
3392EXPORT_SYMBOL(amd_iommu_flush_tlb);
3393
Joerg Roedelb16137b2011-11-21 16:50:23 +01003394static u64 *__get_gcr3_pte(u64 *root, int level, int pasid, bool alloc)
3395{
3396 int index;
3397 u64 *pte;
3398
3399 while (true) {
3400
3401 index = (pasid >> (9 * level)) & 0x1ff;
3402 pte = &root[index];
3403
3404 if (level == 0)
3405 break;
3406
3407 if (!(*pte & GCR3_VALID)) {
3408 if (!alloc)
3409 return NULL;
3410
3411 root = (void *)get_zeroed_page(GFP_ATOMIC);
3412 if (root == NULL)
3413 return NULL;
3414
3415 *pte = __pa(root) | GCR3_VALID;
3416 }
3417
3418 root = __va(*pte & PAGE_MASK);
3419
3420 level -= 1;
3421 }
3422
3423 return pte;
3424}
3425
3426static int __set_gcr3(struct protection_domain *domain, int pasid,
3427 unsigned long cr3)
3428{
3429 u64 *pte;
3430
3431 if (domain->mode != PAGE_MODE_NONE)
3432 return -EINVAL;
3433
3434 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, true);
3435 if (pte == NULL)
3436 return -ENOMEM;
3437
3438 *pte = (cr3 & PAGE_MASK) | GCR3_VALID;
3439
3440 return __amd_iommu_flush_tlb(domain, pasid);
3441}
3442
3443static int __clear_gcr3(struct protection_domain *domain, int pasid)
3444{
3445 u64 *pte;
3446
3447 if (domain->mode != PAGE_MODE_NONE)
3448 return -EINVAL;
3449
3450 pte = __get_gcr3_pte(domain->gcr3_tbl, domain->glx, pasid, false);
3451 if (pte == NULL)
3452 return 0;
3453
3454 *pte = 0;
3455
3456 return __amd_iommu_flush_tlb(domain, pasid);
3457}
3458
3459int amd_iommu_domain_set_gcr3(struct iommu_domain *dom, int pasid,
3460 unsigned long cr3)
3461{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003462 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelb16137b2011-11-21 16:50:23 +01003463 unsigned long flags;
3464 int ret;
3465
3466 spin_lock_irqsave(&domain->lock, flags);
3467 ret = __set_gcr3(domain, pasid, cr3);
3468 spin_unlock_irqrestore(&domain->lock, flags);
3469
3470 return ret;
3471}
3472EXPORT_SYMBOL(amd_iommu_domain_set_gcr3);
3473
3474int amd_iommu_domain_clear_gcr3(struct iommu_domain *dom, int pasid)
3475{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003476 struct protection_domain *domain = to_pdomain(dom);
Joerg Roedelb16137b2011-11-21 16:50:23 +01003477 unsigned long flags;
3478 int ret;
3479
3480 spin_lock_irqsave(&domain->lock, flags);
3481 ret = __clear_gcr3(domain, pasid);
3482 spin_unlock_irqrestore(&domain->lock, flags);
3483
3484 return ret;
3485}
3486EXPORT_SYMBOL(amd_iommu_domain_clear_gcr3);
Joerg Roedelc99afa22011-11-21 18:19:25 +01003487
3488int amd_iommu_complete_ppr(struct pci_dev *pdev, int pasid,
3489 int status, int tag)
3490{
3491 struct iommu_dev_data *dev_data;
3492 struct amd_iommu *iommu;
3493 struct iommu_cmd cmd;
3494
Joerg Roedel399be2f2011-12-01 16:53:47 +01003495 INC_STATS_COUNTER(complete_ppr);
3496
Joerg Roedelc99afa22011-11-21 18:19:25 +01003497 dev_data = get_dev_data(&pdev->dev);
3498 iommu = amd_iommu_rlookup_table[dev_data->devid];
3499
3500 build_complete_ppr(&cmd, dev_data->devid, pasid, status,
3501 tag, dev_data->pri_tlp);
3502
3503 return iommu_queue_command(iommu, &cmd);
3504}
3505EXPORT_SYMBOL(amd_iommu_complete_ppr);
Joerg Roedelf3572db2011-11-23 12:36:25 +01003506
3507struct iommu_domain *amd_iommu_get_v2_domain(struct pci_dev *pdev)
3508{
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003509 struct protection_domain *pdomain;
Joerg Roedelf3572db2011-11-23 12:36:25 +01003510
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003511 pdomain = get_domain(&pdev->dev);
3512 if (IS_ERR(pdomain))
Joerg Roedelf3572db2011-11-23 12:36:25 +01003513 return NULL;
3514
3515 /* Only return IOMMUv2 domains */
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003516 if (!(pdomain->flags & PD_IOMMUV2_MASK))
Joerg Roedelf3572db2011-11-23 12:36:25 +01003517 return NULL;
3518
Joerg Roedel3f4b87b2015-03-26 13:43:07 +01003519 return &pdomain->domain;
Joerg Roedelf3572db2011-11-23 12:36:25 +01003520}
3521EXPORT_SYMBOL(amd_iommu_get_v2_domain);
Joerg Roedel6a113dd2011-12-01 12:04:58 +01003522
3523void amd_iommu_enable_device_erratum(struct pci_dev *pdev, u32 erratum)
3524{
3525 struct iommu_dev_data *dev_data;
3526
3527 if (!amd_iommu_v2_supported())
3528 return;
3529
3530 dev_data = get_dev_data(&pdev->dev);
3531 dev_data->errata |= (1 << erratum);
3532}
3533EXPORT_SYMBOL(amd_iommu_enable_device_erratum);
Joerg Roedel52efdb82011-12-07 12:01:36 +01003534
3535int amd_iommu_device_info(struct pci_dev *pdev,
3536 struct amd_iommu_device_info *info)
3537{
3538 int max_pasids;
3539 int pos;
3540
3541 if (pdev == NULL || info == NULL)
3542 return -EINVAL;
3543
3544 if (!amd_iommu_v2_supported())
3545 return -EINVAL;
3546
3547 memset(info, 0, sizeof(*info));
3548
3549 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_ATS);
3550 if (pos)
3551 info->flags |= AMD_IOMMU_DEVICE_FLAG_ATS_SUP;
3552
3553 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PRI);
3554 if (pos)
3555 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRI_SUP;
3556
3557 pos = pci_find_ext_capability(pdev, PCI_EXT_CAP_ID_PASID);
3558 if (pos) {
3559 int features;
3560
3561 max_pasids = 1 << (9 * (amd_iommu_max_glx_val + 1));
3562 max_pasids = min(max_pasids, (1 << 20));
3563
3564 info->flags |= AMD_IOMMU_DEVICE_FLAG_PASID_SUP;
3565 info->max_pasids = min(pci_max_pasids(pdev), max_pasids);
3566
3567 features = pci_pasid_features(pdev);
3568 if (features & PCI_PASID_CAP_EXEC)
3569 info->flags |= AMD_IOMMU_DEVICE_FLAG_EXEC_SUP;
3570 if (features & PCI_PASID_CAP_PRIV)
3571 info->flags |= AMD_IOMMU_DEVICE_FLAG_PRIV_SUP;
3572 }
3573
3574 return 0;
3575}
3576EXPORT_SYMBOL(amd_iommu_device_info);
Joerg Roedel2b324502012-06-21 16:29:10 +02003577
3578#ifdef CONFIG_IRQ_REMAP
3579
3580/*****************************************************************************
3581 *
3582 * Interrupt Remapping Implementation
3583 *
3584 *****************************************************************************/
3585
3586union irte {
3587 u32 val;
3588 struct {
3589 u32 valid : 1,
3590 no_fault : 1,
3591 int_type : 3,
3592 rq_eoi : 1,
3593 dm : 1,
3594 rsvd_1 : 1,
3595 destination : 8,
3596 vector : 8,
3597 rsvd_2 : 8;
3598 } fields;
3599};
3600
Jiang Liu9c724962015-04-14 10:29:52 +08003601struct irq_2_irte {
3602 u16 devid; /* Device ID for IRTE table */
3603 u16 index; /* Index into IRTE table*/
3604};
3605
Jiang Liu7c71d302015-04-13 14:11:33 +08003606struct amd_ir_data {
3607 struct irq_2_irte irq_2_irte;
3608 union irte irte_entry;
3609 union {
3610 struct msi_msg msi_entry;
3611 };
3612};
3613
3614static struct irq_chip amd_ir_chip;
3615
Joerg Roedel2b324502012-06-21 16:29:10 +02003616#define DTE_IRQ_PHYS_ADDR_MASK (((1ULL << 45)-1) << 6)
3617#define DTE_IRQ_REMAP_INTCTL (2ULL << 60)
3618#define DTE_IRQ_TABLE_LEN (8ULL << 1)
3619#define DTE_IRQ_REMAP_ENABLE 1ULL
3620
3621static void set_dte_irq_entry(u16 devid, struct irq_remap_table *table)
3622{
3623 u64 dte;
3624
3625 dte = amd_iommu_dev_table[devid].data[2];
3626 dte &= ~DTE_IRQ_PHYS_ADDR_MASK;
3627 dte |= virt_to_phys(table->table);
3628 dte |= DTE_IRQ_REMAP_INTCTL;
3629 dte |= DTE_IRQ_TABLE_LEN;
3630 dte |= DTE_IRQ_REMAP_ENABLE;
3631
3632 amd_iommu_dev_table[devid].data[2] = dte;
3633}
3634
3635#define IRTE_ALLOCATED (~1U)
3636
3637static struct irq_remap_table *get_irq_table(u16 devid, bool ioapic)
3638{
3639 struct irq_remap_table *table = NULL;
3640 struct amd_iommu *iommu;
3641 unsigned long flags;
3642 u16 alias;
3643
3644 write_lock_irqsave(&amd_iommu_devtable_lock, flags);
3645
3646 iommu = amd_iommu_rlookup_table[devid];
3647 if (!iommu)
3648 goto out_unlock;
3649
3650 table = irq_lookup_table[devid];
3651 if (table)
3652 goto out;
3653
3654 alias = amd_iommu_alias_table[devid];
3655 table = irq_lookup_table[alias];
3656 if (table) {
3657 irq_lookup_table[devid] = table;
3658 set_dte_irq_entry(devid, table);
3659 iommu_flush_dte(iommu, devid);
3660 goto out;
3661 }
3662
3663 /* Nothing there yet, allocate new irq remapping table */
3664 table = kzalloc(sizeof(*table), GFP_ATOMIC);
3665 if (!table)
3666 goto out;
3667
Joerg Roedel197887f2013-04-09 21:14:08 +02003668 /* Initialize table spin-lock */
3669 spin_lock_init(&table->lock);
3670
Joerg Roedel2b324502012-06-21 16:29:10 +02003671 if (ioapic)
3672 /* Keep the first 32 indexes free for IOAPIC interrupts */
3673 table->min_index = 32;
3674
3675 table->table = kmem_cache_alloc(amd_iommu_irq_cache, GFP_ATOMIC);
3676 if (!table->table) {
3677 kfree(table);
Dan Carpenter821f0f62012-10-02 11:34:40 +03003678 table = NULL;
Joerg Roedel2b324502012-06-21 16:29:10 +02003679 goto out;
3680 }
3681
3682 memset(table->table, 0, MAX_IRQS_PER_TABLE * sizeof(u32));
3683
3684 if (ioapic) {
3685 int i;
3686
3687 for (i = 0; i < 32; ++i)
3688 table->table[i] = IRTE_ALLOCATED;
3689 }
3690
3691 irq_lookup_table[devid] = table;
3692 set_dte_irq_entry(devid, table);
3693 iommu_flush_dte(iommu, devid);
3694 if (devid != alias) {
3695 irq_lookup_table[alias] = table;
Alex Williamsone028a9e2014-04-22 10:08:40 -06003696 set_dte_irq_entry(alias, table);
Joerg Roedel2b324502012-06-21 16:29:10 +02003697 iommu_flush_dte(iommu, alias);
3698 }
3699
3700out:
3701 iommu_completion_wait(iommu);
3702
3703out_unlock:
3704 write_unlock_irqrestore(&amd_iommu_devtable_lock, flags);
3705
3706 return table;
3707}
3708
Jiang Liu3c3d4f92015-04-13 14:11:38 +08003709static int alloc_irq_index(u16 devid, int count)
Joerg Roedel2b324502012-06-21 16:29:10 +02003710{
3711 struct irq_remap_table *table;
3712 unsigned long flags;
3713 int index, c;
3714
3715 table = get_irq_table(devid, false);
3716 if (!table)
3717 return -ENODEV;
3718
3719 spin_lock_irqsave(&table->lock, flags);
3720
3721 /* Scan table for free entries */
3722 for (c = 0, index = table->min_index;
3723 index < MAX_IRQS_PER_TABLE;
3724 ++index) {
3725 if (table->table[index] == 0)
3726 c += 1;
3727 else
3728 c = 0;
3729
3730 if (c == count) {
Joerg Roedel2b324502012-06-21 16:29:10 +02003731 for (; c != 0; --c)
3732 table->table[index - c + 1] = IRTE_ALLOCATED;
3733
3734 index -= count - 1;
Joerg Roedel2b324502012-06-21 16:29:10 +02003735 goto out;
3736 }
3737 }
3738
3739 index = -ENOSPC;
3740
3741out:
3742 spin_unlock_irqrestore(&table->lock, flags);
3743
3744 return index;
3745}
3746
Joerg Roedel2b324502012-06-21 16:29:10 +02003747static int modify_irte(u16 devid, int index, union irte irte)
3748{
3749 struct irq_remap_table *table;
3750 struct amd_iommu *iommu;
3751 unsigned long flags;
3752
3753 iommu = amd_iommu_rlookup_table[devid];
3754 if (iommu == NULL)
3755 return -EINVAL;
3756
3757 table = get_irq_table(devid, false);
3758 if (!table)
3759 return -ENOMEM;
3760
3761 spin_lock_irqsave(&table->lock, flags);
3762 table->table[index] = irte.val;
3763 spin_unlock_irqrestore(&table->lock, flags);
3764
3765 iommu_flush_irt(iommu, devid);
3766 iommu_completion_wait(iommu);
3767
3768 return 0;
3769}
3770
3771static void free_irte(u16 devid, int index)
3772{
3773 struct irq_remap_table *table;
3774 struct amd_iommu *iommu;
3775 unsigned long flags;
3776
3777 iommu = amd_iommu_rlookup_table[devid];
3778 if (iommu == NULL)
3779 return;
3780
3781 table = get_irq_table(devid, false);
3782 if (!table)
3783 return;
3784
3785 spin_lock_irqsave(&table->lock, flags);
3786 table->table[index] = 0;
3787 spin_unlock_irqrestore(&table->lock, flags);
3788
3789 iommu_flush_irt(iommu, devid);
3790 iommu_completion_wait(iommu);
3791}
3792
Jiang Liu7c71d302015-04-13 14:11:33 +08003793static int get_devid(struct irq_alloc_info *info)
Joerg Roedel5527de72012-06-26 11:17:32 +02003794{
Jiang Liu7c71d302015-04-13 14:11:33 +08003795 int devid = -1;
Joerg Roedel5527de72012-06-26 11:17:32 +02003796
Jiang Liu7c71d302015-04-13 14:11:33 +08003797 switch (info->type) {
3798 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3799 devid = get_ioapic_devid(info->ioapic_id);
3800 break;
3801 case X86_IRQ_ALLOC_TYPE_HPET:
3802 devid = get_hpet_devid(info->hpet_id);
3803 break;
3804 case X86_IRQ_ALLOC_TYPE_MSI:
3805 case X86_IRQ_ALLOC_TYPE_MSIX:
3806 devid = get_device_id(&info->msi_dev->dev);
3807 break;
3808 default:
3809 BUG_ON(1);
3810 break;
Joerg Roedel5527de72012-06-26 11:17:32 +02003811 }
3812
Jiang Liu7c71d302015-04-13 14:11:33 +08003813 return devid;
Joerg Roedel5527de72012-06-26 11:17:32 +02003814}
3815
Jiang Liu7c71d302015-04-13 14:11:33 +08003816static struct irq_domain *get_ir_irq_domain(struct irq_alloc_info *info)
Joerg Roedel5527de72012-06-26 11:17:32 +02003817{
Jiang Liu7c71d302015-04-13 14:11:33 +08003818 struct amd_iommu *iommu;
3819 int devid;
Joerg Roedel5527de72012-06-26 11:17:32 +02003820
Jiang Liu7c71d302015-04-13 14:11:33 +08003821 if (!info)
3822 return NULL;
Joerg Roedel5527de72012-06-26 11:17:32 +02003823
Jiang Liu7c71d302015-04-13 14:11:33 +08003824 devid = get_devid(info);
3825 if (devid >= 0) {
3826 iommu = amd_iommu_rlookup_table[devid];
3827 if (iommu)
3828 return iommu->ir_domain;
3829 }
Joerg Roedel5527de72012-06-26 11:17:32 +02003830
Jiang Liu7c71d302015-04-13 14:11:33 +08003831 return NULL;
Joerg Roedel5527de72012-06-26 11:17:32 +02003832}
3833
Jiang Liu7c71d302015-04-13 14:11:33 +08003834static struct irq_domain *get_irq_domain(struct irq_alloc_info *info)
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02003835{
Jiang Liu7c71d302015-04-13 14:11:33 +08003836 struct amd_iommu *iommu;
3837 int devid;
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02003838
Jiang Liu7c71d302015-04-13 14:11:33 +08003839 if (!info)
3840 return NULL;
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02003841
Jiang Liu7c71d302015-04-13 14:11:33 +08003842 switch (info->type) {
3843 case X86_IRQ_ALLOC_TYPE_MSI:
3844 case X86_IRQ_ALLOC_TYPE_MSIX:
3845 devid = get_device_id(&info->msi_dev->dev);
3846 if (devid >= 0) {
3847 iommu = amd_iommu_rlookup_table[devid];
3848 if (iommu)
3849 return iommu->msi_domain;
3850 }
3851 break;
3852 default:
3853 break;
3854 }
Joerg Roedel0b4d48c2012-06-26 14:54:17 +02003855
Jiang Liu7c71d302015-04-13 14:11:33 +08003856 return NULL;
Joerg Roedeld9761952012-06-26 16:00:08 +02003857}
3858
Joerg Roedel6b474b82012-06-26 16:46:04 +02003859struct irq_remap_ops amd_iommu_irq_ops = {
Joerg Roedel6b474b82012-06-26 16:46:04 +02003860 .prepare = amd_iommu_prepare,
3861 .enable = amd_iommu_enable,
3862 .disable = amd_iommu_disable,
3863 .reenable = amd_iommu_reenable,
3864 .enable_faulting = amd_iommu_enable_faulting,
Jiang Liu7c71d302015-04-13 14:11:33 +08003865 .get_ir_irq_domain = get_ir_irq_domain,
3866 .get_irq_domain = get_irq_domain,
Joerg Roedel6b474b82012-06-26 16:46:04 +02003867};
Jiang Liu7c71d302015-04-13 14:11:33 +08003868
3869static void irq_remapping_prepare_irte(struct amd_ir_data *data,
3870 struct irq_cfg *irq_cfg,
3871 struct irq_alloc_info *info,
3872 int devid, int index, int sub_handle)
3873{
3874 struct irq_2_irte *irte_info = &data->irq_2_irte;
3875 struct msi_msg *msg = &data->msi_entry;
3876 union irte *irte = &data->irte_entry;
3877 struct IO_APIC_route_entry *entry;
3878
Jiang Liu7c71d302015-04-13 14:11:33 +08003879 data->irq_2_irte.devid = devid;
3880 data->irq_2_irte.index = index + sub_handle;
3881
3882 /* Setup IRTE for IOMMU */
3883 irte->val = 0;
3884 irte->fields.vector = irq_cfg->vector;
3885 irte->fields.int_type = apic->irq_delivery_mode;
3886 irte->fields.destination = irq_cfg->dest_apicid;
3887 irte->fields.dm = apic->irq_dest_mode;
3888 irte->fields.valid = 1;
3889
3890 switch (info->type) {
3891 case X86_IRQ_ALLOC_TYPE_IOAPIC:
3892 /* Setup IOAPIC entry */
3893 entry = info->ioapic_entry;
3894 info->ioapic_entry = NULL;
3895 memset(entry, 0, sizeof(*entry));
3896 entry->vector = index;
3897 entry->mask = 0;
3898 entry->trigger = info->ioapic_trigger;
3899 entry->polarity = info->ioapic_polarity;
3900 /* Mask level triggered irqs. */
3901 if (info->ioapic_trigger)
3902 entry->mask = 1;
3903 break;
3904
3905 case X86_IRQ_ALLOC_TYPE_HPET:
3906 case X86_IRQ_ALLOC_TYPE_MSI:
3907 case X86_IRQ_ALLOC_TYPE_MSIX:
3908 msg->address_hi = MSI_ADDR_BASE_HI;
3909 msg->address_lo = MSI_ADDR_BASE_LO;
3910 msg->data = irte_info->index;
3911 break;
3912
3913 default:
3914 BUG_ON(1);
3915 break;
3916 }
3917}
3918
3919static int irq_remapping_alloc(struct irq_domain *domain, unsigned int virq,
3920 unsigned int nr_irqs, void *arg)
3921{
3922 struct irq_alloc_info *info = arg;
3923 struct irq_data *irq_data;
3924 struct amd_ir_data *data;
3925 struct irq_cfg *cfg;
3926 int i, ret, devid;
3927 int index = -1;
3928
3929 if (!info)
3930 return -EINVAL;
3931 if (nr_irqs > 1 && info->type != X86_IRQ_ALLOC_TYPE_MSI &&
3932 info->type != X86_IRQ_ALLOC_TYPE_MSIX)
3933 return -EINVAL;
3934
3935 /*
3936 * With IRQ remapping enabled, don't need contiguous CPU vectors
3937 * to support multiple MSI interrupts.
3938 */
3939 if (info->type == X86_IRQ_ALLOC_TYPE_MSI)
3940 info->flags &= ~X86_IRQ_ALLOC_CONTIGUOUS_VECTORS;
3941
3942 devid = get_devid(info);
3943 if (devid < 0)
3944 return -EINVAL;
3945
3946 ret = irq_domain_alloc_irqs_parent(domain, virq, nr_irqs, arg);
3947 if (ret < 0)
3948 return ret;
3949
Jiang Liu7c71d302015-04-13 14:11:33 +08003950 if (info->type == X86_IRQ_ALLOC_TYPE_IOAPIC) {
3951 if (get_irq_table(devid, true))
3952 index = info->ioapic_pin;
3953 else
3954 ret = -ENOMEM;
3955 } else {
Jiang Liu3c3d4f92015-04-13 14:11:38 +08003956 index = alloc_irq_index(devid, nr_irqs);
Jiang Liu7c71d302015-04-13 14:11:33 +08003957 }
3958 if (index < 0) {
3959 pr_warn("Failed to allocate IRTE\n");
Jiang Liu7c71d302015-04-13 14:11:33 +08003960 goto out_free_parent;
3961 }
3962
3963 for (i = 0; i < nr_irqs; i++) {
3964 irq_data = irq_domain_get_irq_data(domain, virq + i);
3965 cfg = irqd_cfg(irq_data);
3966 if (!irq_data || !cfg) {
3967 ret = -EINVAL;
3968 goto out_free_data;
3969 }
3970
Joerg Roedela130e692015-08-13 11:07:25 +02003971 ret = -ENOMEM;
3972 data = kzalloc(sizeof(*data), GFP_KERNEL);
3973 if (!data)
3974 goto out_free_data;
3975
Jiang Liu7c71d302015-04-13 14:11:33 +08003976 irq_data->hwirq = (devid << 16) + i;
3977 irq_data->chip_data = data;
3978 irq_data->chip = &amd_ir_chip;
3979 irq_remapping_prepare_irte(data, cfg, info, devid, index, i);
3980 irq_set_status_flags(virq + i, IRQ_MOVE_PCNTXT);
3981 }
Joerg Roedela130e692015-08-13 11:07:25 +02003982
Jiang Liu7c71d302015-04-13 14:11:33 +08003983 return 0;
3984
3985out_free_data:
3986 for (i--; i >= 0; i--) {
3987 irq_data = irq_domain_get_irq_data(domain, virq + i);
3988 if (irq_data)
3989 kfree(irq_data->chip_data);
3990 }
3991 for (i = 0; i < nr_irqs; i++)
3992 free_irte(devid, index + i);
3993out_free_parent:
3994 irq_domain_free_irqs_common(domain, virq, nr_irqs);
3995 return ret;
3996}
3997
3998static void irq_remapping_free(struct irq_domain *domain, unsigned int virq,
3999 unsigned int nr_irqs)
4000{
4001 struct irq_2_irte *irte_info;
4002 struct irq_data *irq_data;
4003 struct amd_ir_data *data;
4004 int i;
4005
4006 for (i = 0; i < nr_irqs; i++) {
4007 irq_data = irq_domain_get_irq_data(domain, virq + i);
4008 if (irq_data && irq_data->chip_data) {
4009 data = irq_data->chip_data;
4010 irte_info = &data->irq_2_irte;
4011 free_irte(irte_info->devid, irte_info->index);
4012 kfree(data);
4013 }
4014 }
4015 irq_domain_free_irqs_common(domain, virq, nr_irqs);
4016}
4017
4018static void irq_remapping_activate(struct irq_domain *domain,
4019 struct irq_data *irq_data)
4020{
4021 struct amd_ir_data *data = irq_data->chip_data;
4022 struct irq_2_irte *irte_info = &data->irq_2_irte;
4023
4024 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4025}
4026
4027static void irq_remapping_deactivate(struct irq_domain *domain,
4028 struct irq_data *irq_data)
4029{
4030 struct amd_ir_data *data = irq_data->chip_data;
4031 struct irq_2_irte *irte_info = &data->irq_2_irte;
4032 union irte entry;
4033
4034 entry.val = 0;
4035 modify_irte(irte_info->devid, irte_info->index, data->irte_entry);
4036}
4037
4038static struct irq_domain_ops amd_ir_domain_ops = {
4039 .alloc = irq_remapping_alloc,
4040 .free = irq_remapping_free,
4041 .activate = irq_remapping_activate,
4042 .deactivate = irq_remapping_deactivate,
4043};
4044
4045static int amd_ir_set_affinity(struct irq_data *data,
4046 const struct cpumask *mask, bool force)
4047{
4048 struct amd_ir_data *ir_data = data->chip_data;
4049 struct irq_2_irte *irte_info = &ir_data->irq_2_irte;
4050 struct irq_cfg *cfg = irqd_cfg(data);
4051 struct irq_data *parent = data->parent_data;
4052 int ret;
4053
4054 ret = parent->chip->irq_set_affinity(parent, mask, force);
4055 if (ret < 0 || ret == IRQ_SET_MASK_OK_DONE)
4056 return ret;
4057
4058 /*
4059 * Atomically updates the IRTE with the new destination, vector
4060 * and flushes the interrupt entry cache.
4061 */
4062 ir_data->irte_entry.fields.vector = cfg->vector;
4063 ir_data->irte_entry.fields.destination = cfg->dest_apicid;
4064 modify_irte(irte_info->devid, irte_info->index, ir_data->irte_entry);
4065
4066 /*
4067 * After this point, all the interrupts will start arriving
4068 * at the new destination. So, time to cleanup the previous
4069 * vector allocation.
4070 */
Jiang Liuc6c20022015-04-14 10:30:02 +08004071 send_cleanup_vector(cfg);
Jiang Liu7c71d302015-04-13 14:11:33 +08004072
4073 return IRQ_SET_MASK_OK_DONE;
4074}
4075
4076static void ir_compose_msi_msg(struct irq_data *irq_data, struct msi_msg *msg)
4077{
4078 struct amd_ir_data *ir_data = irq_data->chip_data;
4079
4080 *msg = ir_data->msi_entry;
4081}
4082
4083static struct irq_chip amd_ir_chip = {
4084 .irq_ack = ir_ack_apic_edge,
4085 .irq_set_affinity = amd_ir_set_affinity,
4086 .irq_compose_msi_msg = ir_compose_msi_msg,
4087};
4088
4089int amd_iommu_create_irq_domain(struct amd_iommu *iommu)
4090{
4091 iommu->ir_domain = irq_domain_add_tree(NULL, &amd_ir_domain_ops, iommu);
4092 if (!iommu->ir_domain)
4093 return -ENOMEM;
4094
4095 iommu->ir_domain->parent = arch_get_ir_parent_domain();
4096 iommu->msi_domain = arch_create_msi_irq_domain(iommu->ir_domain);
4097
4098 return 0;
4099}
Joerg Roedel2b324502012-06-21 16:29:10 +02004100#endif