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gerrit-public.fairphone.software / kernel / msm-4.9 / b001e086c4c8a5e60a2a28d40ded47ab124458f6 / . / drivers / net / wireless / realtek / rtl8xxxu / rtl8xxxu.c
blob: e48815f25c8a3a9d7e3e43df3ea5491cc7140fb9 [file] [log] [blame]
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1/*
2 * RTL8XXXU mac80211 USB driver
3 *
4 * Copyright (c) 2014 - 2015 Jes Sorensen <Jes.Sorensen@redhat.com>
5 *
6 * Portions, notably calibration code:
7 * Copyright(c) 2007 - 2011 Realtek Corporation. All rights reserved.
8 *
9 * This driver was written as a replacement for the vendor provided
10 * rtl8723au driver. As the Realtek 8xxx chips are very similar in
11 * their programming interface, I have started adding support for
12 * additional 8xxx chips like the 8192cu, 8188cus, etc.
13 *
14 * This program is free software; you can redistribute it and/or modify it
15 * under the terms of version 2 of the GNU General Public License as
16 * published by the Free Software Foundation.
17 *
18 * This program is distributed in the hope that it will be useful, but WITHOUT
19 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
20 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
21 * more details.
22 */
23
24#include <linux/init.h>
25#include <linux/kernel.h>
26#include <linux/sched.h>
27#include <linux/errno.h>
28#include <linux/slab.h>
29#include <linux/module.h>
30#include <linux/spinlock.h>
31#include <linux/list.h>
32#include <linux/usb.h>
33#include <linux/netdevice.h>
34#include <linux/etherdevice.h>
35#include <linux/ethtool.h>
36#include <linux/wireless.h>
37#include <linux/firmware.h>
38#include <linux/moduleparam.h>
39#include <net/mac80211.h>
40#include "rtl8xxxu.h"
41#include "rtl8xxxu_regs.h"
42
43#define DRIVER_NAME "rtl8xxxu"
44
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]45static int rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]46static bool rtl8xxxu_ht40_2g;
47
48MODULE_AUTHOR("Jes Sorensen <Jes.Sorensen@redhat.com>");
49MODULE_DESCRIPTION("RTL8XXXu USB mac80211 Wireless LAN Driver");
50MODULE_LICENSE("GPL");
51MODULE_FIRMWARE("rtlwifi/rtl8723aufw_A.bin");
52MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B.bin");
53MODULE_FIRMWARE("rtlwifi/rtl8723aufw_B_NoBT.bin");
54MODULE_FIRMWARE("rtlwifi/rtl8192cufw_A.bin");
55MODULE_FIRMWARE("rtlwifi/rtl8192cufw_B.bin");
56MODULE_FIRMWARE("rtlwifi/rtl8192cufw_TMSC.bin");
Jes Sorensenb001e082016-02-29 17:04:02 -0500[diff] [blame^]57MODULE_FIRMWARE("rtlwifi/rtl8192eu_nic.bin");
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]58
59module_param_named(debug, rtl8xxxu_debug, int, 0600);
60MODULE_PARM_DESC(debug, "Set debug mask");
61module_param_named(ht40_2g, rtl8xxxu_ht40_2g, bool, 0600);
62MODULE_PARM_DESC(ht40_2g, "Enable HT40 support on the 2.4GHz band");
63
64#define USB_VENDOR_ID_REALTEK 0x0bda
65/* Minimum IEEE80211_MAX_FRAME_LEN */
66#define RTL_RX_BUFFER_SIZE IEEE80211_MAX_FRAME_LEN
67#define RTL8XXXU_RX_URBS 32
68#define RTL8XXXU_RX_URB_PENDING_WATER 8
69#define RTL8XXXU_TX_URBS 64
70#define RTL8XXXU_TX_URB_LOW_WATER 25
71#define RTL8XXXU_TX_URB_HIGH_WATER 32
72
73static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
74 struct rtl8xxxu_rx_urb *rx_urb);
75
76static struct ieee80211_rate rtl8xxxu_rates[] = {
77 { .bitrate = 10, .hw_value = DESC_RATE_1M, .flags = 0 },
78 { .bitrate = 20, .hw_value = DESC_RATE_2M, .flags = 0 },
79 { .bitrate = 55, .hw_value = DESC_RATE_5_5M, .flags = 0 },
80 { .bitrate = 110, .hw_value = DESC_RATE_11M, .flags = 0 },
81 { .bitrate = 60, .hw_value = DESC_RATE_6M, .flags = 0 },
82 { .bitrate = 90, .hw_value = DESC_RATE_9M, .flags = 0 },
83 { .bitrate = 120, .hw_value = DESC_RATE_12M, .flags = 0 },
84 { .bitrate = 180, .hw_value = DESC_RATE_18M, .flags = 0 },
85 { .bitrate = 240, .hw_value = DESC_RATE_24M, .flags = 0 },
86 { .bitrate = 360, .hw_value = DESC_RATE_36M, .flags = 0 },
87 { .bitrate = 480, .hw_value = DESC_RATE_48M, .flags = 0 },
88 { .bitrate = 540, .hw_value = DESC_RATE_54M, .flags = 0 },
89};
90
91static struct ieee80211_channel rtl8xxxu_channels_2g[] = {
92 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2412,
93 .hw_value = 1, .max_power = 30 },
94 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2417,
95 .hw_value = 2, .max_power = 30 },
96 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2422,
97 .hw_value = 3, .max_power = 30 },
98 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2427,
99 .hw_value = 4, .max_power = 30 },
100 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2432,
101 .hw_value = 5, .max_power = 30 },
102 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2437,
103 .hw_value = 6, .max_power = 30 },
104 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2442,
105 .hw_value = 7, .max_power = 30 },
106 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2447,
107 .hw_value = 8, .max_power = 30 },
108 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2452,
109 .hw_value = 9, .max_power = 30 },
110 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2457,
111 .hw_value = 10, .max_power = 30 },
112 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2462,
113 .hw_value = 11, .max_power = 30 },
114 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2467,
115 .hw_value = 12, .max_power = 30 },
116 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2472,
117 .hw_value = 13, .max_power = 30 },
118 { .band = IEEE80211_BAND_2GHZ, .center_freq = 2484,
119 .hw_value = 14, .max_power = 30 }
120};
121
122static struct ieee80211_supported_band rtl8xxxu_supported_band = {
123 .channels = rtl8xxxu_channels_2g,
124 .n_channels = ARRAY_SIZE(rtl8xxxu_channels_2g),
125 .bitrates = rtl8xxxu_rates,
126 .n_bitrates = ARRAY_SIZE(rtl8xxxu_rates),
127};
128
129static struct rtl8xxxu_reg8val rtl8723a_mac_init_table[] = {
130 {0x420, 0x80}, {0x423, 0x00}, {0x430, 0x00}, {0x431, 0x00},
131 {0x432, 0x00}, {0x433, 0x01}, {0x434, 0x04}, {0x435, 0x05},
132 {0x436, 0x06}, {0x437, 0x07}, {0x438, 0x00}, {0x439, 0x00},
133 {0x43a, 0x00}, {0x43b, 0x01}, {0x43c, 0x04}, {0x43d, 0x05},
134 {0x43e, 0x06}, {0x43f, 0x07}, {0x440, 0x5d}, {0x441, 0x01},
135 {0x442, 0x00}, {0x444, 0x15}, {0x445, 0xf0}, {0x446, 0x0f},
136 {0x447, 0x00}, {0x458, 0x41}, {0x459, 0xa8}, {0x45a, 0x72},
137 {0x45b, 0xb9}, {0x460, 0x66}, {0x461, 0x66}, {0x462, 0x08},
138 {0x463, 0x03}, {0x4c8, 0xff}, {0x4c9, 0x08}, {0x4cc, 0xff},
139 {0x4cd, 0xff}, {0x4ce, 0x01}, {0x500, 0x26}, {0x501, 0xa2},
140 {0x502, 0x2f}, {0x503, 0x00}, {0x504, 0x28}, {0x505, 0xa3},
141 {0x506, 0x5e}, {0x507, 0x00}, {0x508, 0x2b}, {0x509, 0xa4},
142 {0x50a, 0x5e}, {0x50b, 0x00}, {0x50c, 0x4f}, {0x50d, 0xa4},
143 {0x50e, 0x00}, {0x50f, 0x00}, {0x512, 0x1c}, {0x514, 0x0a},
144 {0x515, 0x10}, {0x516, 0x0a}, {0x517, 0x10}, {0x51a, 0x16},
145 {0x524, 0x0f}, {0x525, 0x4f}, {0x546, 0x40}, {0x547, 0x00},
146 {0x550, 0x10}, {0x551, 0x10}, {0x559, 0x02}, {0x55a, 0x02},
147 {0x55d, 0xff}, {0x605, 0x30}, {0x608, 0x0e}, {0x609, 0x2a},
148 {0x652, 0x20}, {0x63c, 0x0a}, {0x63d, 0x0a}, {0x63e, 0x0e},
149 {0x63f, 0x0e}, {0x66e, 0x05}, {0x700, 0x21}, {0x701, 0x43},
150 {0x702, 0x65}, {0x703, 0x87}, {0x708, 0x21}, {0x709, 0x43},
151 {0x70a, 0x65}, {0x70b, 0x87}, {0xffff, 0xff},
152};
153
154static struct rtl8xxxu_reg32val rtl8723a_phy_1t_init_table[] = {
155 {0x800, 0x80040000}, {0x804, 0x00000003},
156 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
157 {0x810, 0x10001331}, {0x814, 0x020c3d10},
158 {0x818, 0x02200385}, {0x81c, 0x00000000},
159 {0x820, 0x01000100}, {0x824, 0x00390004},
160 {0x828, 0x00000000}, {0x82c, 0x00000000},
161 {0x830, 0x00000000}, {0x834, 0x00000000},
162 {0x838, 0x00000000}, {0x83c, 0x00000000},
163 {0x840, 0x00010000}, {0x844, 0x00000000},
164 {0x848, 0x00000000}, {0x84c, 0x00000000},
165 {0x850, 0x00000000}, {0x854, 0x00000000},
166 {0x858, 0x569a569a}, {0x85c, 0x001b25a4},
167 {0x860, 0x66f60110}, {0x864, 0x061f0130},
168 {0x868, 0x00000000}, {0x86c, 0x32323200},
169 {0x870, 0x07000760}, {0x874, 0x22004000},
170 {0x878, 0x00000808}, {0x87c, 0x00000000},
171 {0x880, 0xc0083070}, {0x884, 0x000004d5},
172 {0x888, 0x00000000}, {0x88c, 0xccc000c0},
173 {0x890, 0x00000800}, {0x894, 0xfffffffe},
174 {0x898, 0x40302010}, {0x89c, 0x00706050},
175 {0x900, 0x00000000}, {0x904, 0x00000023},
176 {0x908, 0x00000000}, {0x90c, 0x81121111},
177 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
178 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
179 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
180 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
181 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
182 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
183 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
184 {0xa78, 0x00000900},
185 {0xc00, 0x48071d40}, {0xc04, 0x03a05611},
186 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
187 {0xc10, 0x08800000}, {0xc14, 0x40000100},
188 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
189 {0xc20, 0x00000000}, {0xc24, 0x00000000},
190 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
191 {0xc30, 0x69e9ac44}, {0xc34, 0x469652af},
192 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
193 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
194 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
195 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
196 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
197 {0xc60, 0x00000000}, {0xc64, 0x7112848b},
198 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
199 {0xc70, 0x2c7f000d}, {0xc74, 0x018610db},
200 {0xc78, 0x0000001f}, {0xc7c, 0x00b91612},
201 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
202 {0xc88, 0x40000100}, {0xc8c, 0x20200000},
203 {0xc90, 0x00121820}, {0xc94, 0x00000000},
204 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
205 {0xca0, 0x00000000}, {0xca4, 0x00000080},
206 {0xca8, 0x00000000}, {0xcac, 0x00000000},
207 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
208 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
209 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
210 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
211 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
212 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
213 {0xce0, 0x00222222}, {0xce4, 0x00000000},
214 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
215 {0xd00, 0x00080740}, {0xd04, 0x00020401},
216 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
217 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
218 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
219 {0xd30, 0x00000000}, {0xd34, 0x80608000},
220 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
221 {0xd40, 0x00000000}, {0xd44, 0x00000000},
222 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
223 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
224 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
225 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
226 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
227 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
228 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
229 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
230 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
231 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
232 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
233 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
234 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
235 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
236 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
237 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
238 {0xe5c, 0x28160d05}, {0xe60, 0x00000008},
239 {0xe68, 0x001b25a4}, {0xe6c, 0x631b25a0},
240 {0xe70, 0x631b25a0}, {0xe74, 0x081b25a0},
241 {0xe78, 0x081b25a0}, {0xe7c, 0x081b25a0},
242 {0xe80, 0x081b25a0}, {0xe84, 0x631b25a0},
243 {0xe88, 0x081b25a0}, {0xe8c, 0x631b25a0},
244 {0xed0, 0x631b25a0}, {0xed4, 0x631b25a0},
245 {0xed8, 0x631b25a0}, {0xedc, 0x001b25a0},
246 {0xee0, 0x001b25a0}, {0xeec, 0x6b1b25a0},
247 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
248 {0xf00, 0x00000300},
249 {0xffff, 0xffffffff},
250};
251
252static struct rtl8xxxu_reg32val rtl8192cu_phy_2t_init_table[] = {
253 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
254 {0x800, 0x80040002}, {0x804, 0x00000003},
255 {0x808, 0x0000fc00}, {0x80c, 0x0000000a},
256 {0x810, 0x10000330}, {0x814, 0x020c3d10},
257 {0x818, 0x02200385}, {0x81c, 0x00000000},
258 {0x820, 0x01000100}, {0x824, 0x00390004},
259 {0x828, 0x01000100}, {0x82c, 0x00390004},
260 {0x830, 0x27272727}, {0x834, 0x27272727},
261 {0x838, 0x27272727}, {0x83c, 0x27272727},
262 {0x840, 0x00010000}, {0x844, 0x00010000},
263 {0x848, 0x27272727}, {0x84c, 0x27272727},
264 {0x850, 0x00000000}, {0x854, 0x00000000},
265 {0x858, 0x569a569a}, {0x85c, 0x0c1b25a4},
266 {0x860, 0x66e60230}, {0x864, 0x061f0130},
267 {0x868, 0x27272727}, {0x86c, 0x2b2b2b27},
268 {0x870, 0x07000700}, {0x874, 0x22184000},
269 {0x878, 0x08080808}, {0x87c, 0x00000000},
270 {0x880, 0xc0083070}, {0x884, 0x000004d5},
271 {0x888, 0x00000000}, {0x88c, 0xcc0000c0},
272 {0x890, 0x00000800}, {0x894, 0xfffffffe},
273 {0x898, 0x40302010}, {0x89c, 0x00706050},
274 {0x900, 0x00000000}, {0x904, 0x00000023},
275 {0x908, 0x00000000}, {0x90c, 0x81121313},
276 {0xa00, 0x00d047c8}, {0xa04, 0x80ff000c},
277 {0xa08, 0x8c838300}, {0xa0c, 0x2e68120f},
278 {0xa10, 0x9500bb78}, {0xa14, 0x11144028},
279 {0xa18, 0x00881117}, {0xa1c, 0x89140f00},
280 {0xa20, 0x1a1b0000}, {0xa24, 0x090e1317},
281 {0xa28, 0x00000204}, {0xa2c, 0x00d30000},
282 {0xa70, 0x101fbf00}, {0xa74, 0x00000007},
283 {0xc00, 0x48071d40}, {0xc04, 0x03a05633},
284 {0xc08, 0x000000e4}, {0xc0c, 0x6c6c6c6c},
285 {0xc10, 0x08800000}, {0xc14, 0x40000100},
286 {0xc18, 0x08800000}, {0xc1c, 0x40000100},
287 {0xc20, 0x00000000}, {0xc24, 0x00000000},
288 {0xc28, 0x00000000}, {0xc2c, 0x00000000},
289 {0xc30, 0x69e9ac44}, {0xc34, 0x469652cf},
290 {0xc38, 0x49795994}, {0xc3c, 0x0a97971c},
291 {0xc40, 0x1f7c403f}, {0xc44, 0x000100b7},
292 {0xc48, 0xec020107}, {0xc4c, 0x007f037f},
293 {0xc50, 0x69543420}, {0xc54, 0x43bc0094},
294 {0xc58, 0x69543420}, {0xc5c, 0x433c0094},
295 {0xc60, 0x00000000}, {0xc64, 0x5116848b},
296 {0xc68, 0x47c00bff}, {0xc6c, 0x00000036},
297 {0xc70, 0x2c7f000d}, {0xc74, 0x2186115b},
298 {0xc78, 0x0000001f}, {0xc7c, 0x00b99612},
299 {0xc80, 0x40000100}, {0xc84, 0x20f60000},
300 {0xc88, 0x40000100}, {0xc8c, 0xa0e40000},
301 {0xc90, 0x00121820}, {0xc94, 0x00000000},
302 {0xc98, 0x00121820}, {0xc9c, 0x00007f7f},
303 {0xca0, 0x00000000}, {0xca4, 0x00000080},
304 {0xca8, 0x00000000}, {0xcac, 0x00000000},
305 {0xcb0, 0x00000000}, {0xcb4, 0x00000000},
306 {0xcb8, 0x00000000}, {0xcbc, 0x28000000},
307 {0xcc0, 0x00000000}, {0xcc4, 0x00000000},
308 {0xcc8, 0x00000000}, {0xccc, 0x00000000},
309 {0xcd0, 0x00000000}, {0xcd4, 0x00000000},
310 {0xcd8, 0x64b22427}, {0xcdc, 0x00766932},
311 {0xce0, 0x00222222}, {0xce4, 0x00000000},
312 {0xce8, 0x37644302}, {0xcec, 0x2f97d40c},
313 {0xd00, 0x00080740}, {0xd04, 0x00020403},
314 {0xd08, 0x0000907f}, {0xd0c, 0x20010201},
315 {0xd10, 0xa0633333}, {0xd14, 0x3333bc43},
316 {0xd18, 0x7a8f5b6b}, {0xd2c, 0xcc979975},
317 {0xd30, 0x00000000}, {0xd34, 0x80608000},
318 {0xd38, 0x00000000}, {0xd3c, 0x00027293},
319 {0xd40, 0x00000000}, {0xd44, 0x00000000},
320 {0xd48, 0x00000000}, {0xd4c, 0x00000000},
321 {0xd50, 0x6437140a}, {0xd54, 0x00000000},
322 {0xd58, 0x00000000}, {0xd5c, 0x30032064},
323 {0xd60, 0x4653de68}, {0xd64, 0x04518a3c},
324 {0xd68, 0x00002101}, {0xd6c, 0x2a201c16},
325 {0xd70, 0x1812362e}, {0xd74, 0x322c2220},
326 {0xd78, 0x000e3c24}, {0xe00, 0x2a2a2a2a},
327 {0xe04, 0x2a2a2a2a}, {0xe08, 0x03902a2a},
328 {0xe10, 0x2a2a2a2a}, {0xe14, 0x2a2a2a2a},
329 {0xe18, 0x2a2a2a2a}, {0xe1c, 0x2a2a2a2a},
330 {0xe28, 0x00000000}, {0xe30, 0x1000dc1f},
331 {0xe34, 0x10008c1f}, {0xe38, 0x02140102},
332 {0xe3c, 0x681604c2}, {0xe40, 0x01007c00},
333 {0xe44, 0x01004800}, {0xe48, 0xfb000000},
334 {0xe4c, 0x000028d1}, {0xe50, 0x1000dc1f},
335 {0xe54, 0x10008c1f}, {0xe58, 0x02140102},
336 {0xe5c, 0x28160d05}, {0xe60, 0x00000010},
337 {0xe68, 0x001b25a4}, {0xe6c, 0x63db25a4},
338 {0xe70, 0x63db25a4}, {0xe74, 0x0c1b25a4},
339 {0xe78, 0x0c1b25a4}, {0xe7c, 0x0c1b25a4},
340 {0xe80, 0x0c1b25a4}, {0xe84, 0x63db25a4},
341 {0xe88, 0x0c1b25a4}, {0xe8c, 0x63db25a4},
342 {0xed0, 0x63db25a4}, {0xed4, 0x63db25a4},
343 {0xed8, 0x63db25a4}, {0xedc, 0x001b25a4},
344 {0xee0, 0x001b25a4}, {0xeec, 0x6fdb25a4},
345 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
346 {0xf00, 0x00000300},
347 {0xffff, 0xffffffff},
348};
349
350static struct rtl8xxxu_reg32val rtl8188ru_phy_1t_highpa_table[] = {
351 {0x024, 0x0011800f}, {0x028, 0x00ffdb83},
352 {0x040, 0x000c0004}, {0x800, 0x80040000},
353 {0x804, 0x00000001}, {0x808, 0x0000fc00},
354 {0x80c, 0x0000000a}, {0x810, 0x10005388},
355 {0x814, 0x020c3d10}, {0x818, 0x02200385},
356 {0x81c, 0x00000000}, {0x820, 0x01000100},
357 {0x824, 0x00390204}, {0x828, 0x00000000},
358 {0x82c, 0x00000000}, {0x830, 0x00000000},
359 {0x834, 0x00000000}, {0x838, 0x00000000},
360 {0x83c, 0x00000000}, {0x840, 0x00010000},
361 {0x844, 0x00000000}, {0x848, 0x00000000},
362 {0x84c, 0x00000000}, {0x850, 0x00000000},
363 {0x854, 0x00000000}, {0x858, 0x569a569a},
364 {0x85c, 0x001b25a4}, {0x860, 0x66e60230},
365 {0x864, 0x061f0130}, {0x868, 0x00000000},
366 {0x86c, 0x20202000}, {0x870, 0x03000300},
367 {0x874, 0x22004000}, {0x878, 0x00000808},
368 {0x87c, 0x00ffc3f1}, {0x880, 0xc0083070},
369 {0x884, 0x000004d5}, {0x888, 0x00000000},
370 {0x88c, 0xccc000c0}, {0x890, 0x00000800},
371 {0x894, 0xfffffffe}, {0x898, 0x40302010},
372 {0x89c, 0x00706050}, {0x900, 0x00000000},
373 {0x904, 0x00000023}, {0x908, 0x00000000},
374 {0x90c, 0x81121111}, {0xa00, 0x00d047c8},
375 {0xa04, 0x80ff000c}, {0xa08, 0x8c838300},
376 {0xa0c, 0x2e68120f}, {0xa10, 0x9500bb78},
377 {0xa14, 0x11144028}, {0xa18, 0x00881117},
378 {0xa1c, 0x89140f00}, {0xa20, 0x15160000},
379 {0xa24, 0x070b0f12}, {0xa28, 0x00000104},
380 {0xa2c, 0x00d30000}, {0xa70, 0x101fbf00},
381 {0xa74, 0x00000007}, {0xc00, 0x48071d40},
382 {0xc04, 0x03a05611}, {0xc08, 0x000000e4},
383 {0xc0c, 0x6c6c6c6c}, {0xc10, 0x08800000},
384 {0xc14, 0x40000100}, {0xc18, 0x08800000},
385 {0xc1c, 0x40000100}, {0xc20, 0x00000000},
386 {0xc24, 0x00000000}, {0xc28, 0x00000000},
387 {0xc2c, 0x00000000}, {0xc30, 0x69e9ac44},
388 {0xc34, 0x469652cf}, {0xc38, 0x49795994},
389 {0xc3c, 0x0a97971c}, {0xc40, 0x1f7c403f},
390 {0xc44, 0x000100b7}, {0xc48, 0xec020107},
391 {0xc4c, 0x007f037f}, {0xc50, 0x6954342e},
392 {0xc54, 0x43bc0094}, {0xc58, 0x6954342f},
393 {0xc5c, 0x433c0094}, {0xc60, 0x00000000},
394 {0xc64, 0x5116848b}, {0xc68, 0x47c00bff},
395 {0xc6c, 0x00000036}, {0xc70, 0x2c46000d},
396 {0xc74, 0x018610db}, {0xc78, 0x0000001f},
397 {0xc7c, 0x00b91612}, {0xc80, 0x24000090},
398 {0xc84, 0x20f60000}, {0xc88, 0x24000090},
399 {0xc8c, 0x20200000}, {0xc90, 0x00121820},
400 {0xc94, 0x00000000}, {0xc98, 0x00121820},
401 {0xc9c, 0x00007f7f}, {0xca0, 0x00000000},
402 {0xca4, 0x00000080}, {0xca8, 0x00000000},
403 {0xcac, 0x00000000}, {0xcb0, 0x00000000},
404 {0xcb4, 0x00000000}, {0xcb8, 0x00000000},
405 {0xcbc, 0x28000000}, {0xcc0, 0x00000000},
406 {0xcc4, 0x00000000}, {0xcc8, 0x00000000},
407 {0xccc, 0x00000000}, {0xcd0, 0x00000000},
408 {0xcd4, 0x00000000}, {0xcd8, 0x64b22427},
409 {0xcdc, 0x00766932}, {0xce0, 0x00222222},
410 {0xce4, 0x00000000}, {0xce8, 0x37644302},
411 {0xcec, 0x2f97d40c}, {0xd00, 0x00080740},
412 {0xd04, 0x00020401}, {0xd08, 0x0000907f},
413 {0xd0c, 0x20010201}, {0xd10, 0xa0633333},
414 {0xd14, 0x3333bc43}, {0xd18, 0x7a8f5b6b},
415 {0xd2c, 0xcc979975}, {0xd30, 0x00000000},
416 {0xd34, 0x80608000}, {0xd38, 0x00000000},
417 {0xd3c, 0x00027293}, {0xd40, 0x00000000},
418 {0xd44, 0x00000000}, {0xd48, 0x00000000},
419 {0xd4c, 0x00000000}, {0xd50, 0x6437140a},
420 {0xd54, 0x00000000}, {0xd58, 0x00000000},
421 {0xd5c, 0x30032064}, {0xd60, 0x4653de68},
422 {0xd64, 0x04518a3c}, {0xd68, 0x00002101},
423 {0xd6c, 0x2a201c16}, {0xd70, 0x1812362e},
424 {0xd74, 0x322c2220}, {0xd78, 0x000e3c24},
425 {0xe00, 0x24242424}, {0xe04, 0x24242424},
426 {0xe08, 0x03902024}, {0xe10, 0x24242424},
427 {0xe14, 0x24242424}, {0xe18, 0x24242424},
428 {0xe1c, 0x24242424}, {0xe28, 0x00000000},
429 {0xe30, 0x1000dc1f}, {0xe34, 0x10008c1f},
430 {0xe38, 0x02140102}, {0xe3c, 0x681604c2},
431 {0xe40, 0x01007c00}, {0xe44, 0x01004800},
432 {0xe48, 0xfb000000}, {0xe4c, 0x000028d1},
433 {0xe50, 0x1000dc1f}, {0xe54, 0x10008c1f},
434 {0xe58, 0x02140102}, {0xe5c, 0x28160d05},
435 {0xe60, 0x00000008}, {0xe68, 0x001b25a4},
436 {0xe6c, 0x631b25a0}, {0xe70, 0x631b25a0},
437 {0xe74, 0x081b25a0}, {0xe78, 0x081b25a0},
438 {0xe7c, 0x081b25a0}, {0xe80, 0x081b25a0},
439 {0xe84, 0x631b25a0}, {0xe88, 0x081b25a0},
440 {0xe8c, 0x631b25a0}, {0xed0, 0x631b25a0},
441 {0xed4, 0x631b25a0}, {0xed8, 0x631b25a0},
442 {0xedc, 0x001b25a0}, {0xee0, 0x001b25a0},
443 {0xeec, 0x6b1b25a0}, {0xee8, 0x31555448},
444 {0xf14, 0x00000003}, {0xf4c, 0x00000000},
445 {0xf00, 0x00000300},
446 {0xffff, 0xffffffff},
447};
448
449static struct rtl8xxxu_reg32val rtl8xxx_agc_standard_table[] = {
450 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
451 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
452 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
453 {0xc78, 0x7a060001}, {0xc78, 0x79070001},
454 {0xc78, 0x78080001}, {0xc78, 0x77090001},
455 {0xc78, 0x760a0001}, {0xc78, 0x750b0001},
456 {0xc78, 0x740c0001}, {0xc78, 0x730d0001},
457 {0xc78, 0x720e0001}, {0xc78, 0x710f0001},
458 {0xc78, 0x70100001}, {0xc78, 0x6f110001},
459 {0xc78, 0x6e120001}, {0xc78, 0x6d130001},
460 {0xc78, 0x6c140001}, {0xc78, 0x6b150001},
461 {0xc78, 0x6a160001}, {0xc78, 0x69170001},
462 {0xc78, 0x68180001}, {0xc78, 0x67190001},
463 {0xc78, 0x661a0001}, {0xc78, 0x651b0001},
464 {0xc78, 0x641c0001}, {0xc78, 0x631d0001},
465 {0xc78, 0x621e0001}, {0xc78, 0x611f0001},
466 {0xc78, 0x60200001}, {0xc78, 0x49210001},
467 {0xc78, 0x48220001}, {0xc78, 0x47230001},
468 {0xc78, 0x46240001}, {0xc78, 0x45250001},
469 {0xc78, 0x44260001}, {0xc78, 0x43270001},
470 {0xc78, 0x42280001}, {0xc78, 0x41290001},
471 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
472 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
473 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
474 {0xc78, 0x21300001}, {0xc78, 0x20310001},
475 {0xc78, 0x06320001}, {0xc78, 0x05330001},
476 {0xc78, 0x04340001}, {0xc78, 0x03350001},
477 {0xc78, 0x02360001}, {0xc78, 0x01370001},
478 {0xc78, 0x00380001}, {0xc78, 0x00390001},
479 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
480 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
481 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
482 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
483 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
484 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
485 {0xc78, 0x7a460001}, {0xc78, 0x79470001},
486 {0xc78, 0x78480001}, {0xc78, 0x77490001},
487 {0xc78, 0x764a0001}, {0xc78, 0x754b0001},
488 {0xc78, 0x744c0001}, {0xc78, 0x734d0001},
489 {0xc78, 0x724e0001}, {0xc78, 0x714f0001},
490 {0xc78, 0x70500001}, {0xc78, 0x6f510001},
491 {0xc78, 0x6e520001}, {0xc78, 0x6d530001},
492 {0xc78, 0x6c540001}, {0xc78, 0x6b550001},
493 {0xc78, 0x6a560001}, {0xc78, 0x69570001},
494 {0xc78, 0x68580001}, {0xc78, 0x67590001},
495 {0xc78, 0x665a0001}, {0xc78, 0x655b0001},
496 {0xc78, 0x645c0001}, {0xc78, 0x635d0001},
497 {0xc78, 0x625e0001}, {0xc78, 0x615f0001},
498 {0xc78, 0x60600001}, {0xc78, 0x49610001},
499 {0xc78, 0x48620001}, {0xc78, 0x47630001},
500 {0xc78, 0x46640001}, {0xc78, 0x45650001},
501 {0xc78, 0x44660001}, {0xc78, 0x43670001},
502 {0xc78, 0x42680001}, {0xc78, 0x41690001},
503 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
504 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
505 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
506 {0xc78, 0x21700001}, {0xc78, 0x20710001},
507 {0xc78, 0x06720001}, {0xc78, 0x05730001},
508 {0xc78, 0x04740001}, {0xc78, 0x03750001},
509 {0xc78, 0x02760001}, {0xc78, 0x01770001},
510 {0xc78, 0x00780001}, {0xc78, 0x00790001},
511 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
512 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
513 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
514 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
515 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
516 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
517 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
518 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
519 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
520 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
521 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
522 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
523 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
524 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
525 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
526 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
527 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
528 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
529 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
530 {0xffff, 0xffffffff}
531};
532
533static struct rtl8xxxu_reg32val rtl8xxx_agc_highpa_table[] = {
534 {0xc78, 0x7b000001}, {0xc78, 0x7b010001},
535 {0xc78, 0x7b020001}, {0xc78, 0x7b030001},
536 {0xc78, 0x7b040001}, {0xc78, 0x7b050001},
537 {0xc78, 0x7b060001}, {0xc78, 0x7b070001},
538 {0xc78, 0x7b080001}, {0xc78, 0x7a090001},
539 {0xc78, 0x790a0001}, {0xc78, 0x780b0001},
540 {0xc78, 0x770c0001}, {0xc78, 0x760d0001},
541 {0xc78, 0x750e0001}, {0xc78, 0x740f0001},
542 {0xc78, 0x73100001}, {0xc78, 0x72110001},
543 {0xc78, 0x71120001}, {0xc78, 0x70130001},
544 {0xc78, 0x6f140001}, {0xc78, 0x6e150001},
545 {0xc78, 0x6d160001}, {0xc78, 0x6c170001},
546 {0xc78, 0x6b180001}, {0xc78, 0x6a190001},
547 {0xc78, 0x691a0001}, {0xc78, 0x681b0001},
548 {0xc78, 0x671c0001}, {0xc78, 0x661d0001},
549 {0xc78, 0x651e0001}, {0xc78, 0x641f0001},
550 {0xc78, 0x63200001}, {0xc78, 0x62210001},
551 {0xc78, 0x61220001}, {0xc78, 0x60230001},
552 {0xc78, 0x46240001}, {0xc78, 0x45250001},
553 {0xc78, 0x44260001}, {0xc78, 0x43270001},
554 {0xc78, 0x42280001}, {0xc78, 0x41290001},
555 {0xc78, 0x402a0001}, {0xc78, 0x262b0001},
556 {0xc78, 0x252c0001}, {0xc78, 0x242d0001},
557 {0xc78, 0x232e0001}, {0xc78, 0x222f0001},
558 {0xc78, 0x21300001}, {0xc78, 0x20310001},
559 {0xc78, 0x06320001}, {0xc78, 0x05330001},
560 {0xc78, 0x04340001}, {0xc78, 0x03350001},
561 {0xc78, 0x02360001}, {0xc78, 0x01370001},
562 {0xc78, 0x00380001}, {0xc78, 0x00390001},
563 {0xc78, 0x003a0001}, {0xc78, 0x003b0001},
564 {0xc78, 0x003c0001}, {0xc78, 0x003d0001},
565 {0xc78, 0x003e0001}, {0xc78, 0x003f0001},
566 {0xc78, 0x7b400001}, {0xc78, 0x7b410001},
567 {0xc78, 0x7b420001}, {0xc78, 0x7b430001},
568 {0xc78, 0x7b440001}, {0xc78, 0x7b450001},
569 {0xc78, 0x7b460001}, {0xc78, 0x7b470001},
570 {0xc78, 0x7b480001}, {0xc78, 0x7a490001},
571 {0xc78, 0x794a0001}, {0xc78, 0x784b0001},
572 {0xc78, 0x774c0001}, {0xc78, 0x764d0001},
573 {0xc78, 0x754e0001}, {0xc78, 0x744f0001},
574 {0xc78, 0x73500001}, {0xc78, 0x72510001},
575 {0xc78, 0x71520001}, {0xc78, 0x70530001},
576 {0xc78, 0x6f540001}, {0xc78, 0x6e550001},
577 {0xc78, 0x6d560001}, {0xc78, 0x6c570001},
578 {0xc78, 0x6b580001}, {0xc78, 0x6a590001},
579 {0xc78, 0x695a0001}, {0xc78, 0x685b0001},
580 {0xc78, 0x675c0001}, {0xc78, 0x665d0001},
581 {0xc78, 0x655e0001}, {0xc78, 0x645f0001},
582 {0xc78, 0x63600001}, {0xc78, 0x62610001},
583 {0xc78, 0x61620001}, {0xc78, 0x60630001},
584 {0xc78, 0x46640001}, {0xc78, 0x45650001},
585 {0xc78, 0x44660001}, {0xc78, 0x43670001},
586 {0xc78, 0x42680001}, {0xc78, 0x41690001},
587 {0xc78, 0x406a0001}, {0xc78, 0x266b0001},
588 {0xc78, 0x256c0001}, {0xc78, 0x246d0001},
589 {0xc78, 0x236e0001}, {0xc78, 0x226f0001},
590 {0xc78, 0x21700001}, {0xc78, 0x20710001},
591 {0xc78, 0x06720001}, {0xc78, 0x05730001},
592 {0xc78, 0x04740001}, {0xc78, 0x03750001},
593 {0xc78, 0x02760001}, {0xc78, 0x01770001},
594 {0xc78, 0x00780001}, {0xc78, 0x00790001},
595 {0xc78, 0x007a0001}, {0xc78, 0x007b0001},
596 {0xc78, 0x007c0001}, {0xc78, 0x007d0001},
597 {0xc78, 0x007e0001}, {0xc78, 0x007f0001},
598 {0xc78, 0x3800001e}, {0xc78, 0x3801001e},
599 {0xc78, 0x3802001e}, {0xc78, 0x3803001e},
600 {0xc78, 0x3804001e}, {0xc78, 0x3805001e},
601 {0xc78, 0x3806001e}, {0xc78, 0x3807001e},
602 {0xc78, 0x3808001e}, {0xc78, 0x3c09001e},
603 {0xc78, 0x3e0a001e}, {0xc78, 0x400b001e},
604 {0xc78, 0x440c001e}, {0xc78, 0x480d001e},
605 {0xc78, 0x4c0e001e}, {0xc78, 0x500f001e},
606 {0xc78, 0x5210001e}, {0xc78, 0x5611001e},
607 {0xc78, 0x5a12001e}, {0xc78, 0x5e13001e},
608 {0xc78, 0x6014001e}, {0xc78, 0x6015001e},
609 {0xc78, 0x6016001e}, {0xc78, 0x6217001e},
610 {0xc78, 0x6218001e}, {0xc78, 0x6219001e},
611 {0xc78, 0x621a001e}, {0xc78, 0x621b001e},
612 {0xc78, 0x621c001e}, {0xc78, 0x621d001e},
613 {0xc78, 0x621e001e}, {0xc78, 0x621f001e},
614 {0xffff, 0xffffffff}
615};
616
617static struct rtl8xxxu_rfregval rtl8723au_radioa_1t_init_table[] = {
618 {0x00, 0x00030159}, {0x01, 0x00031284},
619 {0x02, 0x00098000}, {0x03, 0x00039c63},
620 {0x04, 0x000210e7}, {0x09, 0x0002044f},
621 {0x0a, 0x0001a3f1}, {0x0b, 0x00014787},
622 {0x0c, 0x000896fe}, {0x0d, 0x0000e02c},
623 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
624 {0x19, 0x00000000}, {0x1a, 0x00030355},
625 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
626 {0x1d, 0x000a1250}, {0x1e, 0x0000024f},
627 {0x1f, 0x00000000}, {0x20, 0x0000b614},
628 {0x21, 0x0006c000}, {0x22, 0x00000000},
629 {0x23, 0x00001558}, {0x24, 0x00000060},
630 {0x25, 0x00000483}, {0x26, 0x0004f000},
631 {0x27, 0x000ec7d9}, {0x28, 0x00057730},
632 {0x29, 0x00004783}, {0x2a, 0x00000001},
633 {0x2b, 0x00021334}, {0x2a, 0x00000000},
634 {0x2b, 0x00000054}, {0x2a, 0x00000001},
635 {0x2b, 0x00000808}, {0x2b, 0x00053333},
636 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
637 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
638 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
639 {0x2b, 0x00000808}, {0x2b, 0x00063333},
640 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
641 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
642 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
643 {0x2b, 0x00000808}, {0x2b, 0x00073333},
644 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
645 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
646 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
647 {0x2b, 0x00000709}, {0x2b, 0x00063333},
648 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
649 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
650 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
651 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
652 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
653 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
654 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
655 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
656 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
657 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
658 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
659 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
660 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
661 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
662 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
663 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
664 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
665 {0x10, 0x0002000f}, {0x11, 0x000203f9},
666 {0x10, 0x0003000f}, {0x11, 0x000ff500},
667 {0x10, 0x00000000}, {0x11, 0x00000000},
668 {0x10, 0x0008000f}, {0x11, 0x0003f100},
669 {0x10, 0x0009000f}, {0x11, 0x00023100},
670 {0x12, 0x00032000}, {0x12, 0x00071000},
671 {0x12, 0x000b0000}, {0x12, 0x000fc000},
672 {0x13, 0x000287b3}, {0x13, 0x000244b7},
673 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
674 {0x13, 0x00018493}, {0x13, 0x0001429b},
675 {0x13, 0x00010299}, {0x13, 0x0000c29c},
676 {0x13, 0x000081a0}, {0x13, 0x000040ac},
677 {0x13, 0x00000020}, {0x14, 0x0001944c},
678 {0x14, 0x00059444}, {0x14, 0x0009944c},
679 {0x14, 0x000d9444}, {0x15, 0x0000f474},
680 {0x15, 0x0004f477}, {0x15, 0x0008f455},
681 {0x15, 0x000cf455}, {0x16, 0x00000339},
682 {0x16, 0x00040339}, {0x16, 0x00080339},
683 {0x16, 0x000c0366}, {0x00, 0x00010159},
684 {0x18, 0x0000f401}, {0xfe, 0x00000000},
685 {0xfe, 0x00000000}, {0x1f, 0x00000003},
686 {0xfe, 0x00000000}, {0xfe, 0x00000000},
687 {0x1e, 0x00000247}, {0x1f, 0x00000000},
688 {0x00, 0x00030159},
689 {0xff, 0xffffffff}
690};
691
692static struct rtl8xxxu_rfregval rtl8192cu_radioa_2t_init_table[] = {
693 {0x00, 0x00030159}, {0x01, 0x00031284},
694 {0x02, 0x00098000}, {0x03, 0x00018c63},
695 {0x04, 0x000210e7}, {0x09, 0x0002044f},
696 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
697 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
698 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
699 {0x19, 0x00000000}, {0x1a, 0x00010255},
700 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
701 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
702 {0x1f, 0x00080001}, {0x20, 0x0000b614},
703 {0x21, 0x0006c000}, {0x22, 0x00000000},
704 {0x23, 0x00001558}, {0x24, 0x00000060},
705 {0x25, 0x00000483}, {0x26, 0x0004f000},
706 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
707 {0x29, 0x00004783}, {0x2a, 0x00000001},
708 {0x2b, 0x00021334}, {0x2a, 0x00000000},
709 {0x2b, 0x00000054}, {0x2a, 0x00000001},
710 {0x2b, 0x00000808}, {0x2b, 0x00053333},
711 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
712 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
713 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
714 {0x2b, 0x00000808}, {0x2b, 0x00063333},
715 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
716 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
717 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
718 {0x2b, 0x00000808}, {0x2b, 0x00073333},
719 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
720 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
721 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
722 {0x2b, 0x00000709}, {0x2b, 0x00063333},
723 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
724 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
725 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
726 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
727 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
728 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
729 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
730 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
731 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
732 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
733 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
734 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
735 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
736 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
737 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
738 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
739 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
740 {0x10, 0x0002000f}, {0x11, 0x000203f9},
741 {0x10, 0x0003000f}, {0x11, 0x000ff500},
742 {0x10, 0x00000000}, {0x11, 0x00000000},
743 {0x10, 0x0008000f}, {0x11, 0x0003f100},
744 {0x10, 0x0009000f}, {0x11, 0x00023100},
745 {0x12, 0x00032000}, {0x12, 0x00071000},
746 {0x12, 0x000b0000}, {0x12, 0x000fc000},
747 {0x13, 0x000287b3}, {0x13, 0x000244b7},
748 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
749 {0x13, 0x00018493}, {0x13, 0x0001429b},
750 {0x13, 0x00010299}, {0x13, 0x0000c29c},
751 {0x13, 0x000081a0}, {0x13, 0x000040ac},
752 {0x13, 0x00000020}, {0x14, 0x0001944c},
753 {0x14, 0x00059444}, {0x14, 0x0009944c},
754 {0x14, 0x000d9444}, {0x15, 0x0000f424},
755 {0x15, 0x0004f424}, {0x15, 0x0008f424},
756 {0x15, 0x000cf424}, {0x16, 0x000e0330},
757 {0x16, 0x000a0330}, {0x16, 0x00060330},
758 {0x16, 0x00020330}, {0x00, 0x00010159},
759 {0x18, 0x0000f401}, {0xfe, 0x00000000},
760 {0xfe, 0x00000000}, {0x1f, 0x00080003},
761 {0xfe, 0x00000000}, {0xfe, 0x00000000},
762 {0x1e, 0x00044457}, {0x1f, 0x00080000},
763 {0x00, 0x00030159},
764 {0xff, 0xffffffff}
765};
766
767static struct rtl8xxxu_rfregval rtl8192cu_radiob_2t_init_table[] = {
768 {0x00, 0x00030159}, {0x01, 0x00031284},
769 {0x02, 0x00098000}, {0x03, 0x00018c63},
770 {0x04, 0x000210e7}, {0x09, 0x0002044f},
771 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
772 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
773 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
774 {0x12, 0x00032000}, {0x12, 0x00071000},
775 {0x12, 0x000b0000}, {0x12, 0x000fc000},
776 {0x13, 0x000287af}, {0x13, 0x000244b7},
777 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
778 {0x13, 0x00018493}, {0x13, 0x00014297},
779 {0x13, 0x00010295}, {0x13, 0x0000c298},
780 {0x13, 0x0000819c}, {0x13, 0x000040a8},
781 {0x13, 0x0000001c}, {0x14, 0x0001944c},
782 {0x14, 0x00059444}, {0x14, 0x0009944c},
783 {0x14, 0x000d9444}, {0x15, 0x0000f424},
784 {0x15, 0x0004f424}, {0x15, 0x0008f424},
785 {0x15, 0x000cf424}, {0x16, 0x000e0330},
786 {0x16, 0x000a0330}, {0x16, 0x00060330},
787 {0x16, 0x00020330},
788 {0xff, 0xffffffff}
789};
790
791static struct rtl8xxxu_rfregval rtl8192cu_radioa_1t_init_table[] = {
792 {0x00, 0x00030159}, {0x01, 0x00031284},
793 {0x02, 0x00098000}, {0x03, 0x00018c63},
794 {0x04, 0x000210e7}, {0x09, 0x0002044f},
795 {0x0a, 0x0001adb1}, {0x0b, 0x00054867},
796 {0x0c, 0x0008992e}, {0x0d, 0x0000e52c},
797 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
798 {0x19, 0x00000000}, {0x1a, 0x00010255},
799 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
800 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
801 {0x1f, 0x00080001}, {0x20, 0x0000b614},
802 {0x21, 0x0006c000}, {0x22, 0x00000000},
803 {0x23, 0x00001558}, {0x24, 0x00000060},
804 {0x25, 0x00000483}, {0x26, 0x0004f000},
805 {0x27, 0x000ec7d9}, {0x28, 0x000577c0},
806 {0x29, 0x00004783}, {0x2a, 0x00000001},
807 {0x2b, 0x00021334}, {0x2a, 0x00000000},
808 {0x2b, 0x00000054}, {0x2a, 0x00000001},
809 {0x2b, 0x00000808}, {0x2b, 0x00053333},
810 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
811 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
812 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
813 {0x2b, 0x00000808}, {0x2b, 0x00063333},
814 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
815 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
816 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
817 {0x2b, 0x00000808}, {0x2b, 0x00073333},
818 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
819 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
820 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
821 {0x2b, 0x00000709}, {0x2b, 0x00063333},
822 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
823 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
824 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
825 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
826 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
827 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
828 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
829 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
830 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
831 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
832 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
833 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
834 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
835 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
836 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
837 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
838 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
839 {0x10, 0x0002000f}, {0x11, 0x000203f9},
840 {0x10, 0x0003000f}, {0x11, 0x000ff500},
841 {0x10, 0x00000000}, {0x11, 0x00000000},
842 {0x10, 0x0008000f}, {0x11, 0x0003f100},
843 {0x10, 0x0009000f}, {0x11, 0x00023100},
844 {0x12, 0x00032000}, {0x12, 0x00071000},
845 {0x12, 0x000b0000}, {0x12, 0x000fc000},
846 {0x13, 0x000287b3}, {0x13, 0x000244b7},
847 {0x13, 0x000204ab}, {0x13, 0x0001c49f},
848 {0x13, 0x00018493}, {0x13, 0x0001429b},
849 {0x13, 0x00010299}, {0x13, 0x0000c29c},
850 {0x13, 0x000081a0}, {0x13, 0x000040ac},
851 {0x13, 0x00000020}, {0x14, 0x0001944c},
852 {0x14, 0x00059444}, {0x14, 0x0009944c},
853 {0x14, 0x000d9444}, {0x15, 0x0000f405},
854 {0x15, 0x0004f405}, {0x15, 0x0008f405},
855 {0x15, 0x000cf405}, {0x16, 0x000e0330},
856 {0x16, 0x000a0330}, {0x16, 0x00060330},
857 {0x16, 0x00020330}, {0x00, 0x00010159},
858 {0x18, 0x0000f401}, {0xfe, 0x00000000},
859 {0xfe, 0x00000000}, {0x1f, 0x00080003},
860 {0xfe, 0x00000000}, {0xfe, 0x00000000},
861 {0x1e, 0x00044457}, {0x1f, 0x00080000},
862 {0x00, 0x00030159},
863 {0xff, 0xffffffff}
864};
865
866static struct rtl8xxxu_rfregval rtl8188ru_radioa_1t_highpa_table[] = {
867 {0x00, 0x00030159}, {0x01, 0x00031284},
868 {0x02, 0x00098000}, {0x03, 0x00018c63},
869 {0x04, 0x000210e7}, {0x09, 0x0002044f},
870 {0x0a, 0x0001adb0}, {0x0b, 0x00054867},
871 {0x0c, 0x0008992e}, {0x0d, 0x0000e529},
872 {0x0e, 0x00039ce7}, {0x0f, 0x00000451},
873 {0x19, 0x00000000}, {0x1a, 0x00000255},
874 {0x1b, 0x00060a00}, {0x1c, 0x000fc378},
875 {0x1d, 0x000a1250}, {0x1e, 0x0004445f},
876 {0x1f, 0x00080001}, {0x20, 0x0000b614},
877 {0x21, 0x0006c000}, {0x22, 0x0000083c},
878 {0x23, 0x00001558}, {0x24, 0x00000060},
879 {0x25, 0x00000483}, {0x26, 0x0004f000},
880 {0x27, 0x000ec7d9}, {0x28, 0x000977c0},
881 {0x29, 0x00004783}, {0x2a, 0x00000001},
882 {0x2b, 0x00021334}, {0x2a, 0x00000000},
883 {0x2b, 0x00000054}, {0x2a, 0x00000001},
884 {0x2b, 0x00000808}, {0x2b, 0x00053333},
885 {0x2c, 0x0000000c}, {0x2a, 0x00000002},
886 {0x2b, 0x00000808}, {0x2b, 0x0005b333},
887 {0x2c, 0x0000000d}, {0x2a, 0x00000003},
888 {0x2b, 0x00000808}, {0x2b, 0x00063333},
889 {0x2c, 0x0000000d}, {0x2a, 0x00000004},
890 {0x2b, 0x00000808}, {0x2b, 0x0006b333},
891 {0x2c, 0x0000000d}, {0x2a, 0x00000005},
892 {0x2b, 0x00000808}, {0x2b, 0x00073333},
893 {0x2c, 0x0000000d}, {0x2a, 0x00000006},
894 {0x2b, 0x00000709}, {0x2b, 0x0005b333},
895 {0x2c, 0x0000000d}, {0x2a, 0x00000007},
896 {0x2b, 0x00000709}, {0x2b, 0x00063333},
897 {0x2c, 0x0000000d}, {0x2a, 0x00000008},
898 {0x2b, 0x0000060a}, {0x2b, 0x0004b333},
899 {0x2c, 0x0000000d}, {0x2a, 0x00000009},
900 {0x2b, 0x0000060a}, {0x2b, 0x00053333},
901 {0x2c, 0x0000000d}, {0x2a, 0x0000000a},
902 {0x2b, 0x0000060a}, {0x2b, 0x0005b333},
903 {0x2c, 0x0000000d}, {0x2a, 0x0000000b},
904 {0x2b, 0x0000060a}, {0x2b, 0x00063333},
905 {0x2c, 0x0000000d}, {0x2a, 0x0000000c},
906 {0x2b, 0x0000060a}, {0x2b, 0x0006b333},
907 {0x2c, 0x0000000d}, {0x2a, 0x0000000d},
908 {0x2b, 0x0000060a}, {0x2b, 0x00073333},
909 {0x2c, 0x0000000d}, {0x2a, 0x0000000e},
910 {0x2b, 0x0000050b}, {0x2b, 0x00066666},
911 {0x2c, 0x0000001a}, {0x2a, 0x000e0000},
912 {0x10, 0x0004000f}, {0x11, 0x000e31fc},
913 {0x10, 0x0006000f}, {0x11, 0x000ff9f8},
914 {0x10, 0x0002000f}, {0x11, 0x000203f9},
915 {0x10, 0x0003000f}, {0x11, 0x000ff500},
916 {0x10, 0x00000000}, {0x11, 0x00000000},
917 {0x10, 0x0008000f}, {0x11, 0x0003f100},
918 {0x10, 0x0009000f}, {0x11, 0x00023100},
919 {0x12, 0x000d8000}, {0x12, 0x00090000},
920 {0x12, 0x00051000}, {0x12, 0x00012000},
921 {0x13, 0x00028fb4}, {0x13, 0x00024fa8},
922 {0x13, 0x000207a4}, {0x13, 0x0001c3b0},
923 {0x13, 0x000183a4}, {0x13, 0x00014398},
924 {0x13, 0x000101a4}, {0x13, 0x0000c198},
925 {0x13, 0x000080a4}, {0x13, 0x00004098},
926 {0x13, 0x00000000}, {0x14, 0x0001944c},
927 {0x14, 0x00059444}, {0x14, 0x0009944c},
928 {0x14, 0x000d9444}, {0x15, 0x0000f405},
929 {0x15, 0x0004f405}, {0x15, 0x0008f405},
930 {0x15, 0x000cf405}, {0x16, 0x000e0330},
931 {0x16, 0x000a0330}, {0x16, 0x00060330},
932 {0x16, 0x00020330}, {0x00, 0x00010159},
933 {0x18, 0x0000f401}, {0xfe, 0x00000000},
934 {0xfe, 0x00000000}, {0x1f, 0x00080003},
935 {0xfe, 0x00000000}, {0xfe, 0x00000000},
936 {0x1e, 0x00044457}, {0x1f, 0x00080000},
937 {0x00, 0x00030159},
938 {0xff, 0xffffffff}
939};
940
941static struct rtl8xxxu_rfregs rtl8xxxu_rfregs[] = {
942 { /* RF_A */
943 .hssiparm1 = REG_FPGA0_XA_HSSI_PARM1,
944 .hssiparm2 = REG_FPGA0_XA_HSSI_PARM2,
945 .lssiparm = REG_FPGA0_XA_LSSI_PARM,
946 .hspiread = REG_HSPI_XA_READBACK,
947 .lssiread = REG_FPGA0_XA_LSSI_READBACK,
948 .rf_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL,
949 },
950 { /* RF_B */
951 .hssiparm1 = REG_FPGA0_XB_HSSI_PARM1,
952 .hssiparm2 = REG_FPGA0_XB_HSSI_PARM2,
953 .lssiparm = REG_FPGA0_XB_LSSI_PARM,
954 .hspiread = REG_HSPI_XB_READBACK,
955 .lssiread = REG_FPGA0_XB_LSSI_READBACK,
956 .rf_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL,
957 },
958};
959
960static const u32 rtl8723au_iqk_phy_iq_bb_reg[RTL8XXXU_BB_REGS] = {
961 REG_OFDM0_XA_RX_IQ_IMBALANCE,
962 REG_OFDM0_XB_RX_IQ_IMBALANCE,
963 REG_OFDM0_ENERGY_CCA_THRES,
964 REG_OFDM0_AGCR_SSI_TABLE,
965 REG_OFDM0_XA_TX_IQ_IMBALANCE,
966 REG_OFDM0_XB_TX_IQ_IMBALANCE,
967 REG_OFDM0_XC_TX_AFE,
968 REG_OFDM0_XD_TX_AFE,
969 REG_OFDM0_RX_IQ_EXT_ANTA
970};
971
972static u8 rtl8xxxu_read8(struct rtl8xxxu_priv *priv, u16 addr)
973{
974 struct usb_device *udev = priv->udev;
975 int len;
976 u8 data;
977
978 mutex_lock(&priv->usb_buf_mutex);
979 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
980 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
981 addr, 0, &priv->usb_buf.val8, sizeof(u8),
982 RTW_USB_CONTROL_MSG_TIMEOUT);
983 data = priv->usb_buf.val8;
984 mutex_unlock(&priv->usb_buf_mutex);
985
986 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
987 dev_info(&udev->dev, "%s(%04x) = 0x%02x, len %i\n",
988 __func__, addr, data, len);
989 return data;
990}
991
992static u16 rtl8xxxu_read16(struct rtl8xxxu_priv *priv, u16 addr)
993{
994 struct usb_device *udev = priv->udev;
995 int len;
996 u16 data;
997
998 mutex_lock(&priv->usb_buf_mutex);
999 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1000 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1001 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1002 RTW_USB_CONTROL_MSG_TIMEOUT);
1003 data = le16_to_cpu(priv->usb_buf.val16);
1004 mutex_unlock(&priv->usb_buf_mutex);
1005
1006 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1007 dev_info(&udev->dev, "%s(%04x) = 0x%04x, len %i\n",
1008 __func__, addr, data, len);
1009 return data;
1010}
1011
1012static u32 rtl8xxxu_read32(struct rtl8xxxu_priv *priv, u16 addr)
1013{
1014 struct usb_device *udev = priv->udev;
1015 int len;
1016 u32 data;
1017
1018 mutex_lock(&priv->usb_buf_mutex);
1019 len = usb_control_msg(udev, usb_rcvctrlpipe(udev, 0),
1020 REALTEK_USB_CMD_REQ, REALTEK_USB_READ,
1021 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1022 RTW_USB_CONTROL_MSG_TIMEOUT);
1023 data = le32_to_cpu(priv->usb_buf.val32);
1024 mutex_unlock(&priv->usb_buf_mutex);
1025
1026 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_READ)
1027 dev_info(&udev->dev, "%s(%04x) = 0x%08x, len %i\n",
1028 __func__, addr, data, len);
1029 return data;
1030}
1031
1032static int rtl8xxxu_write8(struct rtl8xxxu_priv *priv, u16 addr, u8 val)
1033{
1034 struct usb_device *udev = priv->udev;
1035 int ret;
1036
1037 mutex_lock(&priv->usb_buf_mutex);
1038 priv->usb_buf.val8 = val;
1039 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1040 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1041 addr, 0, &priv->usb_buf.val8, sizeof(u8),
1042 RTW_USB_CONTROL_MSG_TIMEOUT);
1043
1044 mutex_unlock(&priv->usb_buf_mutex);
1045
1046 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1047 dev_info(&udev->dev, "%s(%04x) = 0x%02x\n",
1048 __func__, addr, val);
1049 return ret;
1050}
1051
1052static int rtl8xxxu_write16(struct rtl8xxxu_priv *priv, u16 addr, u16 val)
1053{
1054 struct usb_device *udev = priv->udev;
1055 int ret;
1056
1057 mutex_lock(&priv->usb_buf_mutex);
1058 priv->usb_buf.val16 = cpu_to_le16(val);
1059 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1060 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1061 addr, 0, &priv->usb_buf.val16, sizeof(u16),
1062 RTW_USB_CONTROL_MSG_TIMEOUT);
1063 mutex_unlock(&priv->usb_buf_mutex);
1064
1065 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1066 dev_info(&udev->dev, "%s(%04x) = 0x%04x\n",
1067 __func__, addr, val);
1068 return ret;
1069}
1070
1071static int rtl8xxxu_write32(struct rtl8xxxu_priv *priv, u16 addr, u32 val)
1072{
1073 struct usb_device *udev = priv->udev;
1074 int ret;
1075
1076 mutex_lock(&priv->usb_buf_mutex);
1077 priv->usb_buf.val32 = cpu_to_le32(val);
1078 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1079 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1080 addr, 0, &priv->usb_buf.val32, sizeof(u32),
1081 RTW_USB_CONTROL_MSG_TIMEOUT);
1082 mutex_unlock(&priv->usb_buf_mutex);
1083
1084 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_REG_WRITE)
1085 dev_info(&udev->dev, "%s(%04x) = 0x%08x\n",
1086 __func__, addr, val);
1087 return ret;
1088}
1089
1090static int
1091rtl8xxxu_writeN(struct rtl8xxxu_priv *priv, u16 addr, u8 *buf, u16 len)
1092{
1093 struct usb_device *udev = priv->udev;
1094 int blocksize = priv->fops->writeN_block_size;
1095 int ret, i, count, remainder;
1096
1097 count = len / blocksize;
1098 remainder = len % blocksize;
1099
1100 for (i = 0; i < count; i++) {
1101 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1102 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1103 addr, 0, buf, blocksize,
1104 RTW_USB_CONTROL_MSG_TIMEOUT);
1105 if (ret != blocksize)
1106 goto write_error;
1107
1108 addr += blocksize;
1109 buf += blocksize;
1110 }
1111
1112 if (remainder) {
1113 ret = usb_control_msg(udev, usb_sndctrlpipe(udev, 0),
1114 REALTEK_USB_CMD_REQ, REALTEK_USB_WRITE,
1115 addr, 0, buf, remainder,
1116 RTW_USB_CONTROL_MSG_TIMEOUT);
1117 if (ret != remainder)
1118 goto write_error;
1119 }
1120
1121 return len;
1122
1123write_error:
1124 dev_info(&udev->dev,
1125 "%s: Failed to write block at addr: %04x size: %04x\n",
1126 __func__, addr, blocksize);
1127 return -EAGAIN;
1128}
1129
1130static u32 rtl8xxxu_read_rfreg(struct rtl8xxxu_priv *priv,
1131 enum rtl8xxxu_rfpath path, u8 reg)
1132{
1133 u32 hssia, val32, retval;
1134
1135 hssia = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
1136 if (path != RF_A)
1137 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm2);
1138 else
1139 val32 = hssia;
1140
1141 val32 &= ~FPGA0_HSSI_PARM2_ADDR_MASK;
1142 val32 |= (reg << FPGA0_HSSI_PARM2_ADDR_SHIFT);
1143 val32 |= FPGA0_HSSI_PARM2_EDGE_READ;
1144 hssia &= ~FPGA0_HSSI_PARM2_EDGE_READ;
1145 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1146
1147 udelay(10);
1148
1149 rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].hssiparm2, val32);
1150 udelay(100);
1151
1152 hssia |= FPGA0_HSSI_PARM2_EDGE_READ;
1153 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM2, hssia);
1154 udelay(10);
1155
1156 val32 = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hssiparm1);
1157 if (val32 & FPGA0_HSSI_PARM1_PI)
1158 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].hspiread);
1159 else
1160 retval = rtl8xxxu_read32(priv, rtl8xxxu_rfregs[path].lssiread);
1161
1162 retval &= 0xfffff;
1163
1164 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_READ)
1165 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1166 __func__, reg, retval);
1167 return retval;
1168}
1169
1170static int rtl8xxxu_write_rfreg(struct rtl8xxxu_priv *priv,
1171 enum rtl8xxxu_rfpath path, u8 reg, u32 data)
1172{
1173 int ret, retval;
1174 u32 dataaddr;
1175
1176 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_RFREG_WRITE)
1177 dev_info(&priv->udev->dev, "%s(%02x) = 0x%06x\n",
1178 __func__, reg, data);
1179
1180 data &= FPGA0_LSSI_PARM_DATA_MASK;
1181 dataaddr = (reg << FPGA0_LSSI_PARM_ADDR_SHIFT) | data;
1182
1183 /* Use XB for path B */
1184 ret = rtl8xxxu_write32(priv, rtl8xxxu_rfregs[path].lssiparm, dataaddr);
1185 if (ret != sizeof(dataaddr))
1186 retval = -EIO;
1187 else
1188 retval = 0;
1189
1190 udelay(1);
1191
1192 return retval;
1193}
1194
1195static int rtl8723a_h2c_cmd(struct rtl8xxxu_priv *priv, struct h2c_cmd *h2c)
1196{
1197 struct device *dev = &priv->udev->dev;
1198 int mbox_nr, retry, retval = 0;
1199 int mbox_reg, mbox_ext_reg;
1200 u8 val8;
1201
1202 mutex_lock(&priv->h2c_mutex);
1203
1204 mbox_nr = priv->next_mbox;
1205 mbox_reg = REG_HMBOX_0 + (mbox_nr * 4);
1206 mbox_ext_reg = REG_HMBOX_EXT_0 + (mbox_nr * 2);
1207
1208 /*
1209 * MBOX ready?
1210 */
1211 retry = 100;
1212 do {
1213 val8 = rtl8xxxu_read8(priv, REG_HMTFR);
1214 if (!(val8 & BIT(mbox_nr)))
1215 break;
1216 } while (retry--);
1217
1218 if (!retry) {
1219 dev_dbg(dev, "%s: Mailbox busy\n", __func__);
1220 retval = -EBUSY;
1221 goto error;
1222 }
1223
1224 /*
1225 * Need to swap as it's being swapped again by rtl8xxxu_write16/32()
1226 */
1227 if (h2c->cmd.cmd & H2C_EXT) {
1228 rtl8xxxu_write16(priv, mbox_ext_reg,
1229 le16_to_cpu(h2c->raw.ext));
1230 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1231 dev_info(dev, "H2C_EXT %04x\n",
1232 le16_to_cpu(h2c->raw.ext));
1233 }
1234 rtl8xxxu_write32(priv, mbox_reg, le32_to_cpu(h2c->raw.data));
1235 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_H2C)
1236 dev_info(dev, "H2C %08x\n", le32_to_cpu(h2c->raw.data));
1237
1238 priv->next_mbox = (mbox_nr + 1) % H2C_MAX_MBOX;
1239
1240error:
1241 mutex_unlock(&priv->h2c_mutex);
1242 return retval;
1243}
1244
1245static void rtl8723a_enable_rf(struct rtl8xxxu_priv *priv)
1246{
1247 u8 val8;
1248 u32 val32;
1249
1250 val8 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1251 val8 |= BIT(0) | BIT(3);
1252 rtl8xxxu_write8(priv, REG_SPS0_CTRL, val8);
1253
1254 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1255 val32 &= ~(BIT(4) | BIT(5));
1256 val32 |= BIT(3);
1257 if (priv->rf_paths == 2) {
1258 val32 &= ~(BIT(20) | BIT(21));
1259 val32 |= BIT(19);
1260 }
1261 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1262
1263 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1264 val32 &= ~OFDM_RF_PATH_TX_MASK;
1265 if (priv->tx_paths == 2)
1266 val32 |= OFDM_RF_PATH_TX_A | OFDM_RF_PATH_TX_B;
1267 else if (priv->rtlchip == 0x8192c || priv->rtlchip == 0x8191c)
1268 val32 |= OFDM_RF_PATH_TX_B;
1269 else
1270 val32 |= OFDM_RF_PATH_TX_A;
1271 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1272
1273 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1274 val32 &= ~FPGA_RF_MODE_JAPAN;
1275 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1276
1277 if (priv->rf_paths == 2)
1278 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x63db25a0);
1279 else
1280 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x631b25a0);
1281
1282 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0x32d95);
1283 if (priv->rf_paths == 2)
1284 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0x32d95);
1285
1286 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
1287}
1288
1289static void rtl8723a_disable_rf(struct rtl8xxxu_priv *priv)
1290{
1291 u8 sps0;
1292 u32 val32;
1293
1294 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
1295
1296 sps0 = rtl8xxxu_read8(priv, REG_SPS0_CTRL);
1297
1298 /* RF RX code for preamble power saving */
1299 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_PARM);
1300 val32 &= ~(BIT(3) | BIT(4) | BIT(5));
1301 if (priv->rf_paths == 2)
1302 val32 &= ~(BIT(19) | BIT(20) | BIT(21));
1303 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_PARM, val32);
1304
1305 /* Disable TX for four paths */
1306 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
1307 val32 &= ~OFDM_RF_PATH_TX_MASK;
1308 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
1309
1310 /* Enable power saving */
1311 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1312 val32 |= FPGA_RF_MODE_JAPAN;
1313 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1314
1315 /* AFE control register to power down bits [30:22] */
1316 if (priv->rf_paths == 2)
1317 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x00db25a0);
1318 else
1319 rtl8xxxu_write32(priv, REG_RX_WAIT_CCA, 0x001b25a0);
1320
1321 /* Power down RF module */
1322 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, 0);
1323 if (priv->rf_paths == 2)
1324 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC, 0);
1325
1326 sps0 &= ~(BIT(0) | BIT(3));
1327 rtl8xxxu_write8(priv, REG_SPS0_CTRL, sps0);
1328}
1329
1330
1331static void rtl8723a_stop_tx_beacon(struct rtl8xxxu_priv *priv)
1332{
1333 u8 val8;
1334
1335 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL + 2);
1336 val8 &= ~BIT(6);
1337 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL + 2, val8);
1338
1339 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 1, 0x64);
1340 val8 = rtl8xxxu_read8(priv, REG_TBTT_PROHIBIT + 2);
1341 val8 &= ~BIT(0);
1342 rtl8xxxu_write8(priv, REG_TBTT_PROHIBIT + 2, val8);
1343}
1344
1345
1346/*
1347 * The rtl8723a has 3 channel groups for it's efuse settings. It only
1348 * supports the 2.4GHz band, so channels 1 - 14:
1349 * group 0: channels 1 - 3
1350 * group 1: channels 4 - 9
1351 * group 2: channels 10 - 14
1352 *
1353 * Note: We index from 0 in the code
1354 */
1355static int rtl8723a_channel_to_group(int channel)
1356{
1357 int group;
1358
1359 if (channel < 4)
1360 group = 0;
1361 else if (channel < 10)
1362 group = 1;
1363 else
1364 group = 2;
1365
1366 return group;
1367}
1368
1369static void rtl8723au_config_channel(struct ieee80211_hw *hw)
1370{
1371 struct rtl8xxxu_priv *priv = hw->priv;
1372 u32 val32, rsr;
1373 u8 val8, opmode;
1374 bool ht = true;
1375 int sec_ch_above, channel;
1376 int i;
1377
1378 opmode = rtl8xxxu_read8(priv, REG_BW_OPMODE);
1379 rsr = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
1380 channel = hw->conf.chandef.chan->hw_value;
1381
1382 switch (hw->conf.chandef.width) {
1383 case NL80211_CHAN_WIDTH_20_NOHT:
1384 ht = false;
1385 case NL80211_CHAN_WIDTH_20:
1386 opmode |= BW_OPMODE_20MHZ;
1387 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1388
1389 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1390 val32 &= ~FPGA_RF_MODE;
1391 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1392
1393 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1394 val32 &= ~FPGA_RF_MODE;
1395 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1396
1397 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1398 val32 |= FPGA0_ANALOG2_20MHZ;
1399 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1400 break;
1401 case NL80211_CHAN_WIDTH_40:
1402 if (hw->conf.chandef.center_freq1 >
1403 hw->conf.chandef.chan->center_freq) {
1404 sec_ch_above = 1;
1405 channel += 2;
1406 } else {
1407 sec_ch_above = 0;
1408 channel -= 2;
1409 }
1410
1411 opmode &= ~BW_OPMODE_20MHZ;
1412 rtl8xxxu_write8(priv, REG_BW_OPMODE, opmode);
1413 rsr &= ~RSR_RSC_BANDWIDTH_40M;
1414 if (sec_ch_above)
1415 rsr |= RSR_RSC_UPPER_SUB_CHANNEL;
1416 else
1417 rsr |= RSR_RSC_LOWER_SUB_CHANNEL;
1418 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, rsr);
1419
1420 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
1421 val32 |= FPGA_RF_MODE;
1422 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
1423
1424 val32 = rtl8xxxu_read32(priv, REG_FPGA1_RF_MODE);
1425 val32 |= FPGA_RF_MODE;
1426 rtl8xxxu_write32(priv, REG_FPGA1_RF_MODE, val32);
1427
1428 /*
1429 * Set Control channel to upper or lower. These settings
1430 * are required only for 40MHz
1431 */
1432 val32 = rtl8xxxu_read32(priv, REG_CCK0_SYSTEM);
1433 val32 &= ~CCK0_SIDEBAND;
1434 if (!sec_ch_above)
1435 val32 |= CCK0_SIDEBAND;
1436 rtl8xxxu_write32(priv, REG_CCK0_SYSTEM, val32);
1437
1438 val32 = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
1439 val32 &= ~OFDM_LSTF_PRIME_CH_MASK; /* 0xc00 */
1440 if (sec_ch_above)
1441 val32 |= OFDM_LSTF_PRIME_CH_LOW;
1442 else
1443 val32 |= OFDM_LSTF_PRIME_CH_HIGH;
1444 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
1445
1446 val32 = rtl8xxxu_read32(priv, REG_FPGA0_ANALOG2);
1447 val32 &= ~FPGA0_ANALOG2_20MHZ;
1448 rtl8xxxu_write32(priv, REG_FPGA0_ANALOG2, val32);
1449
1450 val32 = rtl8xxxu_read32(priv, REG_FPGA0_POWER_SAVE);
1451 val32 &= ~(FPGA0_PS_LOWER_CHANNEL | FPGA0_PS_UPPER_CHANNEL);
1452 if (sec_ch_above)
1453 val32 |= FPGA0_PS_UPPER_CHANNEL;
1454 else
1455 val32 |= FPGA0_PS_LOWER_CHANNEL;
1456 rtl8xxxu_write32(priv, REG_FPGA0_POWER_SAVE, val32);
1457 break;
1458
1459 default:
1460 break;
1461 }
1462
1463 for (i = RF_A; i < priv->rf_paths; i++) {
1464 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1465 val32 &= ~MODE_AG_CHANNEL_MASK;
1466 val32 |= channel;
1467 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1468 }
1469
1470 if (ht)
1471 val8 = 0x0e;
1472 else
1473 val8 = 0x0a;
1474
1475 rtl8xxxu_write8(priv, REG_SIFS_CCK + 1, val8);
1476 rtl8xxxu_write8(priv, REG_SIFS_OFDM + 1, val8);
1477
1478 rtl8xxxu_write16(priv, REG_R2T_SIFS, 0x0808);
1479 rtl8xxxu_write16(priv, REG_T2T_SIFS, 0x0a0a);
1480
1481 for (i = RF_A; i < priv->rf_paths; i++) {
1482 val32 = rtl8xxxu_read_rfreg(priv, i, RF6052_REG_MODE_AG);
1483 if (hw->conf.chandef.width == NL80211_CHAN_WIDTH_40)
1484 val32 &= ~MODE_AG_CHANNEL_20MHZ;
1485 else
1486 val32 |= MODE_AG_CHANNEL_20MHZ;
1487 rtl8xxxu_write_rfreg(priv, i, RF6052_REG_MODE_AG, val32);
1488 }
1489}
1490
1491static void
1492rtl8723a_set_tx_power(struct rtl8xxxu_priv *priv, int channel, bool ht40)
1493{
1494 u8 cck[RTL8723A_MAX_RF_PATHS], ofdm[RTL8723A_MAX_RF_PATHS];
1495 u8 ofdmbase[RTL8723A_MAX_RF_PATHS], mcsbase[RTL8723A_MAX_RF_PATHS];
1496 u32 val32, ofdm_a, ofdm_b, mcs_a, mcs_b;
1497 u8 val8;
1498 int group, i;
1499
1500 group = rtl8723a_channel_to_group(channel);
1501
1502 cck[0] = priv->cck_tx_power_index_A[group];
1503 cck[1] = priv->cck_tx_power_index_B[group];
1504
1505 ofdm[0] = priv->ht40_1s_tx_power_index_A[group];
1506 ofdm[1] = priv->ht40_1s_tx_power_index_B[group];
1507
1508 ofdmbase[0] = ofdm[0] + priv->ofdm_tx_power_index_diff[group].a;
1509 ofdmbase[1] = ofdm[1] + priv->ofdm_tx_power_index_diff[group].b;
1510
1511 mcsbase[0] = ofdm[0];
1512 mcsbase[1] = ofdm[1];
1513 if (!ht40) {
1514 mcsbase[0] += priv->ht20_tx_power_index_diff[group].a;
1515 mcsbase[1] += priv->ht20_tx_power_index_diff[group].b;
1516 }
1517
1518 if (priv->tx_paths > 1) {
1519 if (ofdm[0] > priv->ht40_2s_tx_power_index_diff[group].a)
1520 ofdm[0] -= priv->ht40_2s_tx_power_index_diff[group].a;
1521 if (ofdm[1] > priv->ht40_2s_tx_power_index_diff[group].b)
1522 ofdm[1] -= priv->ht40_2s_tx_power_index_diff[group].b;
1523 }
1524
1525 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
1526 dev_info(&priv->udev->dev,
1527 "%s: Setting TX power CCK A: %02x, "
1528 "CCK B: %02x, OFDM A: %02x, OFDM B: %02x\n",
1529 __func__, cck[0], cck[1], ofdm[0], ofdm[1]);
1530
1531 for (i = 0; i < RTL8723A_MAX_RF_PATHS; i++) {
1532 if (cck[i] > RF6052_MAX_TX_PWR)
1533 cck[i] = RF6052_MAX_TX_PWR;
1534 if (ofdm[i] > RF6052_MAX_TX_PWR)
1535 ofdm[i] = RF6052_MAX_TX_PWR;
1536 }
1537
1538 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_A_CCK1_MCS32);
1539 val32 &= 0xffff00ff;
1540 val32 |= (cck[0] << 8);
1541 rtl8xxxu_write32(priv, REG_TX_AGC_A_CCK1_MCS32, val32);
1542
1543 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1544 val32 &= 0xff;
1545 val32 |= ((cck[0] << 8) | (cck[0] << 16) | (cck[0] << 24));
1546 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1547
1548 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11);
1549 val32 &= 0xffffff00;
1550 val32 |= cck[1];
1551 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK11_A_CCK2_11, val32);
1552
1553 val32 = rtl8xxxu_read32(priv, REG_TX_AGC_B_CCK1_55_MCS32);
1554 val32 &= 0xff;
1555 val32 |= ((cck[1] << 8) | (cck[1] << 16) | (cck[1] << 24));
1556 rtl8xxxu_write32(priv, REG_TX_AGC_B_CCK1_55_MCS32, val32);
1557
1558 ofdm_a = ofdmbase[0] | ofdmbase[0] << 8 |
1559 ofdmbase[0] << 16 | ofdmbase[0] << 24;
1560 ofdm_b = ofdmbase[1] | ofdmbase[1] << 8 |
1561 ofdmbase[1] << 16 | ofdmbase[1] << 24;
1562 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE18_06, ofdm_a);
1563 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE18_06, ofdm_b);
1564
1565 rtl8xxxu_write32(priv, REG_TX_AGC_A_RATE54_24, ofdm_a);
1566 rtl8xxxu_write32(priv, REG_TX_AGC_B_RATE54_24, ofdm_b);
1567
1568 mcs_a = mcsbase[0] | mcsbase[0] << 8 |
1569 mcsbase[0] << 16 | mcsbase[0] << 24;
1570 mcs_b = mcsbase[1] | mcsbase[1] << 8 |
1571 mcsbase[1] << 16 | mcsbase[1] << 24;
1572
1573 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS03_MCS00, mcs_a);
1574 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS03_MCS00, mcs_b);
1575
1576 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS07_MCS04, mcs_a);
1577 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS07_MCS04, mcs_b);
1578
1579 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS11_MCS08, mcs_a);
1580 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS11_MCS08, mcs_b);
1581
1582 rtl8xxxu_write32(priv, REG_TX_AGC_A_MCS15_MCS12, mcs_a);
1583 for (i = 0; i < 3; i++) {
1584 if (i != 2)
1585 val8 = (mcsbase[0] > 8) ? (mcsbase[0] - 8) : 0;
1586 else
1587 val8 = (mcsbase[0] > 6) ? (mcsbase[0] - 6) : 0;
1588 rtl8xxxu_write8(priv, REG_OFDM0_XC_TX_IQ_IMBALANCE + i, val8);
1589 }
1590 rtl8xxxu_write32(priv, REG_TX_AGC_B_MCS15_MCS12, mcs_b);
1591 for (i = 0; i < 3; i++) {
1592 if (i != 2)
1593 val8 = (mcsbase[1] > 8) ? (mcsbase[1] - 8) : 0;
1594 else
1595 val8 = (mcsbase[1] > 6) ? (mcsbase[1] - 6) : 0;
1596 rtl8xxxu_write8(priv, REG_OFDM0_XD_TX_IQ_IMBALANCE + i, val8);
1597 }
1598}
1599
1600static void rtl8xxxu_set_linktype(struct rtl8xxxu_priv *priv,
1601 enum nl80211_iftype linktype)
1602{
Jes Sorensena26703f2016-02-03 13:39:56 -0500[diff] [blame]1603 u8 val8;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1604
Jes Sorensena26703f2016-02-03 13:39:56 -0500[diff] [blame]1605 val8 = rtl8xxxu_read8(priv, REG_MSR);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1606 val8 &= ~MSR_LINKTYPE_MASK;
1607
1608 switch (linktype) {
1609 case NL80211_IFTYPE_UNSPECIFIED:
1610 val8 |= MSR_LINKTYPE_NONE;
1611 break;
1612 case NL80211_IFTYPE_ADHOC:
1613 val8 |= MSR_LINKTYPE_ADHOC;
1614 break;
1615 case NL80211_IFTYPE_STATION:
1616 val8 |= MSR_LINKTYPE_STATION;
1617 break;
1618 case NL80211_IFTYPE_AP:
1619 val8 |= MSR_LINKTYPE_AP;
1620 break;
1621 default:
1622 goto out;
1623 }
1624
1625 rtl8xxxu_write8(priv, REG_MSR, val8);
1626out:
1627 return;
1628}
1629
1630static void
1631rtl8xxxu_set_retry(struct rtl8xxxu_priv *priv, u16 short_retry, u16 long_retry)
1632{
1633 u16 val16;
1634
1635 val16 = ((short_retry << RETRY_LIMIT_SHORT_SHIFT) &
1636 RETRY_LIMIT_SHORT_MASK) |
1637 ((long_retry << RETRY_LIMIT_LONG_SHIFT) &
1638 RETRY_LIMIT_LONG_MASK);
1639
1640 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
1641}
1642
1643static void
1644rtl8xxxu_set_spec_sifs(struct rtl8xxxu_priv *priv, u16 cck, u16 ofdm)
1645{
1646 u16 val16;
1647
1648 val16 = ((cck << SPEC_SIFS_CCK_SHIFT) & SPEC_SIFS_CCK_MASK) |
1649 ((ofdm << SPEC_SIFS_OFDM_SHIFT) & SPEC_SIFS_OFDM_MASK);
1650
1651 rtl8xxxu_write16(priv, REG_SPEC_SIFS, val16);
1652}
1653
1654static void rtl8xxxu_print_chipinfo(struct rtl8xxxu_priv *priv)
1655{
1656 struct device *dev = &priv->udev->dev;
1657 char *cut;
1658
1659 switch (priv->chip_cut) {
1660 case 0:
1661 cut = "A";
1662 break;
1663 case 1:
1664 cut = "B";
1665 break;
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]1666 case 2:
1667 cut = "C";
1668 break;
1669 case 3:
1670 cut = "D";
1671 break;
1672 case 4:
1673 cut = "E";
1674 break;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1675 default:
1676 cut = "unknown";
1677 }
1678
1679 dev_info(dev,
1680 "RTL%s rev %s (%s) %iT%iR, TX queues %i, WiFi=%i, BT=%i, GPS=%i, HI PA=%i\n",
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]1681 priv->chip_name, cut, priv->chip_vendor, priv->tx_paths,
1682 priv->rx_paths, priv->ep_tx_count, priv->has_wifi,
1683 priv->has_bluetooth, priv->has_gps, priv->hi_pa);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1684
1685 dev_info(dev, "RTL%s MAC: %pM\n", priv->chip_name, priv->mac_addr);
1686}
1687
1688static int rtl8xxxu_identify_chip(struct rtl8xxxu_priv *priv)
1689{
1690 struct device *dev = &priv->udev->dev;
1691 u32 val32, bonding;
1692 u16 val16;
1693
1694 val32 = rtl8xxxu_read32(priv, REG_SYS_CFG);
1695 priv->chip_cut = (val32 & SYS_CFG_CHIP_VERSION_MASK) >>
1696 SYS_CFG_CHIP_VERSION_SHIFT;
1697 if (val32 & SYS_CFG_TRP_VAUX_EN) {
1698 dev_info(dev, "Unsupported test chip\n");
1699 return -ENOTSUPP;
1700 }
1701
1702 if (val32 & SYS_CFG_BT_FUNC) {
1703 sprintf(priv->chip_name, "8723AU");
1704 priv->rf_paths = 1;
1705 priv->rx_paths = 1;
1706 priv->tx_paths = 1;
1707 priv->rtlchip = 0x8723a;
1708
1709 val32 = rtl8xxxu_read32(priv, REG_MULTI_FUNC_CTRL);
1710 if (val32 & MULTI_WIFI_FUNC_EN)
1711 priv->has_wifi = 1;
1712 if (val32 & MULTI_BT_FUNC_EN)
1713 priv->has_bluetooth = 1;
1714 if (val32 & MULTI_GPS_FUNC_EN)
1715 priv->has_gps = 1;
Jakub Sitnicki38451992016-02-03 13:39:49 -0500[diff] [blame]1716 priv->is_multi_func = 1;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1717 } else if (val32 & SYS_CFG_TYPE_ID) {
1718 bonding = rtl8xxxu_read32(priv, REG_HPON_FSM);
1719 bonding &= HPON_FSM_BONDING_MASK;
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]1720 if (priv->chip_cut >= 3) {
1721 if (bonding == HPON_FSM_BONDING_1T2R) {
1722 sprintf(priv->chip_name, "8191EU");
1723 priv->rf_paths = 2;
1724 priv->rx_paths = 2;
1725 priv->tx_paths = 1;
1726 priv->rtlchip = 0x8191e;
1727 } else {
1728 sprintf(priv->chip_name, "8192EU");
1729 priv->rf_paths = 2;
1730 priv->rx_paths = 2;
1731 priv->tx_paths = 2;
1732 priv->rtlchip = 0x8192e;
1733 }
1734 } else if (bonding == HPON_FSM_BONDING_1T2R) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1735 sprintf(priv->chip_name, "8191CU");
1736 priv->rf_paths = 2;
1737 priv->rx_paths = 2;
1738 priv->tx_paths = 1;
1739 priv->rtlchip = 0x8191c;
1740 } else {
1741 sprintf(priv->chip_name, "8192CU");
1742 priv->rf_paths = 2;
1743 priv->rx_paths = 2;
1744 priv->tx_paths = 2;
1745 priv->rtlchip = 0x8192c;
1746 }
1747 priv->has_wifi = 1;
1748 } else {
1749 sprintf(priv->chip_name, "8188CU");
1750 priv->rf_paths = 1;
1751 priv->rx_paths = 1;
1752 priv->tx_paths = 1;
1753 priv->rtlchip = 0x8188c;
1754 priv->has_wifi = 1;
1755 }
1756
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]1757 switch (priv->rtlchip) {
1758 case 0x8188e:
1759 case 0x8192e:
1760 case 0x8723b:
1761 switch (val32 & SYS_CFG_VENDOR_EXT_MASK) {
1762 case SYS_CFG_VENDOR_ID_TSMC:
1763 sprintf(priv->chip_vendor, "TSMC");
1764 break;
1765 case SYS_CFG_VENDOR_ID_SMIC:
1766 sprintf(priv->chip_vendor, "SMIC");
1767 priv->vendor_smic = 1;
1768 break;
1769 case SYS_CFG_VENDOR_ID_UMC:
1770 sprintf(priv->chip_vendor, "UMC");
1771 priv->vendor_umc = 1;
1772 break;
1773 default:
1774 sprintf(priv->chip_vendor, "unknown");
1775 }
1776 break;
1777 default:
1778 if (val32 & SYS_CFG_VENDOR_ID) {
1779 sprintf(priv->chip_vendor, "UMC");
1780 priv->vendor_umc = 1;
1781 } else {
1782 sprintf(priv->chip_vendor, "TSMC");
1783 }
1784 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1785
1786 val32 = rtl8xxxu_read32(priv, REG_GPIO_OUTSTS);
1787 priv->rom_rev = (val32 & GPIO_RF_RL_ID) >> 28;
1788
1789 val16 = rtl8xxxu_read16(priv, REG_NORMAL_SIE_EP_TX);
1790 if (val16 & NORMAL_SIE_EP_TX_HIGH_MASK) {
1791 priv->ep_tx_high_queue = 1;
1792 priv->ep_tx_count++;
1793 }
1794
1795 if (val16 & NORMAL_SIE_EP_TX_NORMAL_MASK) {
1796 priv->ep_tx_normal_queue = 1;
1797 priv->ep_tx_count++;
1798 }
1799
1800 if (val16 & NORMAL_SIE_EP_TX_LOW_MASK) {
1801 priv->ep_tx_low_queue = 1;
1802 priv->ep_tx_count++;
1803 }
1804
1805 /*
1806 * Fallback for devices that do not provide REG_NORMAL_SIE_EP_TX
1807 */
1808 if (!priv->ep_tx_count) {
1809 switch (priv->nr_out_eps) {
1810 case 3:
1811 priv->ep_tx_low_queue = 1;
1812 priv->ep_tx_count++;
1813 case 2:
1814 priv->ep_tx_normal_queue = 1;
1815 priv->ep_tx_count++;
1816 case 1:
1817 priv->ep_tx_high_queue = 1;
1818 priv->ep_tx_count++;
1819 break;
1820 default:
1821 dev_info(dev, "Unsupported USB TX end-points\n");
1822 return -ENOTSUPP;
1823 }
1824 }
1825
1826 return 0;
1827}
1828
1829static int rtl8723au_parse_efuse(struct rtl8xxxu_priv *priv)
1830{
1831 if (priv->efuse_wifi.efuse8723.rtl_id != cpu_to_le16(0x8129))
1832 return -EINVAL;
1833
1834 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8723.mac_addr);
1835
1836 memcpy(priv->cck_tx_power_index_A,
1837 priv->efuse_wifi.efuse8723.cck_tx_power_index_A,
1838 sizeof(priv->cck_tx_power_index_A));
1839 memcpy(priv->cck_tx_power_index_B,
1840 priv->efuse_wifi.efuse8723.cck_tx_power_index_B,
1841 sizeof(priv->cck_tx_power_index_B));
1842
1843 memcpy(priv->ht40_1s_tx_power_index_A,
1844 priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_A,
1845 sizeof(priv->ht40_1s_tx_power_index_A));
1846 memcpy(priv->ht40_1s_tx_power_index_B,
1847 priv->efuse_wifi.efuse8723.ht40_1s_tx_power_index_B,
1848 sizeof(priv->ht40_1s_tx_power_index_B));
1849
1850 memcpy(priv->ht20_tx_power_index_diff,
1851 priv->efuse_wifi.efuse8723.ht20_tx_power_index_diff,
1852 sizeof(priv->ht20_tx_power_index_diff));
1853 memcpy(priv->ofdm_tx_power_index_diff,
1854 priv->efuse_wifi.efuse8723.ofdm_tx_power_index_diff,
1855 sizeof(priv->ofdm_tx_power_index_diff));
1856
1857 memcpy(priv->ht40_max_power_offset,
1858 priv->efuse_wifi.efuse8723.ht40_max_power_offset,
1859 sizeof(priv->ht40_max_power_offset));
1860 memcpy(priv->ht20_max_power_offset,
1861 priv->efuse_wifi.efuse8723.ht20_max_power_offset,
1862 sizeof(priv->ht20_max_power_offset));
1863
1864 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1865 priv->efuse_wifi.efuse8723.vendor_name);
1866 dev_info(&priv->udev->dev, "Product: %.41s\n",
1867 priv->efuse_wifi.efuse8723.device_name);
1868 return 0;
1869}
1870
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]1871#ifdef CONFIG_RTL8XXXU_UNTESTED
1872
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1873static int rtl8192cu_parse_efuse(struct rtl8xxxu_priv *priv)
1874{
1875 int i;
1876
1877 if (priv->efuse_wifi.efuse8192.rtl_id != cpu_to_le16(0x8129))
1878 return -EINVAL;
1879
1880 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192.mac_addr);
1881
1882 memcpy(priv->cck_tx_power_index_A,
1883 priv->efuse_wifi.efuse8192.cck_tx_power_index_A,
1884 sizeof(priv->cck_tx_power_index_A));
1885 memcpy(priv->cck_tx_power_index_B,
1886 priv->efuse_wifi.efuse8192.cck_tx_power_index_B,
1887 sizeof(priv->cck_tx_power_index_B));
1888
1889 memcpy(priv->ht40_1s_tx_power_index_A,
1890 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_A,
1891 sizeof(priv->ht40_1s_tx_power_index_A));
1892 memcpy(priv->ht40_1s_tx_power_index_B,
1893 priv->efuse_wifi.efuse8192.ht40_1s_tx_power_index_B,
1894 sizeof(priv->ht40_1s_tx_power_index_B));
1895 memcpy(priv->ht40_2s_tx_power_index_diff,
1896 priv->efuse_wifi.efuse8192.ht40_2s_tx_power_index_diff,
1897 sizeof(priv->ht40_2s_tx_power_index_diff));
1898
1899 memcpy(priv->ht20_tx_power_index_diff,
1900 priv->efuse_wifi.efuse8192.ht20_tx_power_index_diff,
1901 sizeof(priv->ht20_tx_power_index_diff));
1902 memcpy(priv->ofdm_tx_power_index_diff,
1903 priv->efuse_wifi.efuse8192.ofdm_tx_power_index_diff,
1904 sizeof(priv->ofdm_tx_power_index_diff));
1905
1906 memcpy(priv->ht40_max_power_offset,
1907 priv->efuse_wifi.efuse8192.ht40_max_power_offset,
1908 sizeof(priv->ht40_max_power_offset));
1909 memcpy(priv->ht20_max_power_offset,
1910 priv->efuse_wifi.efuse8192.ht20_max_power_offset,
1911 sizeof(priv->ht20_max_power_offset));
1912
1913 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1914 priv->efuse_wifi.efuse8192.vendor_name);
1915 dev_info(&priv->udev->dev, "Product: %.20s\n",
1916 priv->efuse_wifi.efuse8192.device_name);
1917
1918 if (priv->efuse_wifi.efuse8192.rf_regulatory & 0x20) {
1919 sprintf(priv->chip_name, "8188RU");
1920 priv->hi_pa = 1;
1921 }
1922
1923 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1924 unsigned char *raw = priv->efuse_wifi.raw;
1925
1926 dev_info(&priv->udev->dev,
1927 "%s: dumping efuse (0x%02zx bytes):\n",
1928 __func__, sizeof(struct rtl8192cu_efuse));
1929 for (i = 0; i < sizeof(struct rtl8192cu_efuse); i += 8) {
1930 dev_info(&priv->udev->dev, "%02x: "
1931 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1932 raw[i], raw[i + 1], raw[i + 2],
1933 raw[i + 3], raw[i + 4], raw[i + 5],
1934 raw[i + 6], raw[i + 7]);
1935 }
1936 }
1937 return 0;
1938}
1939
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]1940#endif
1941
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]1942static int rtl8192eu_parse_efuse(struct rtl8xxxu_priv *priv)
1943{
1944 int i;
1945
1946 if (priv->efuse_wifi.efuse8192eu.rtl_id != cpu_to_le16(0x8129))
1947 return -EINVAL;
1948
1949 ether_addr_copy(priv->mac_addr, priv->efuse_wifi.efuse8192eu.mac_addr);
1950
1951 memcpy(priv->cck_tx_power_index_A,
1952 priv->efuse_wifi.efuse8192eu.cck_tx_power_index_A,
1953 sizeof(priv->cck_tx_power_index_A));
1954 memcpy(priv->cck_tx_power_index_B,
1955 priv->efuse_wifi.efuse8192eu.cck_tx_power_index_B,
1956 sizeof(priv->cck_tx_power_index_B));
1957
1958 memcpy(priv->ht40_1s_tx_power_index_A,
1959 priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_A,
1960 sizeof(priv->ht40_1s_tx_power_index_A));
1961 memcpy(priv->ht40_1s_tx_power_index_B,
1962 priv->efuse_wifi.efuse8192eu.ht40_1s_tx_power_index_B,
1963 sizeof(priv->ht40_1s_tx_power_index_B));
1964
1965 dev_info(&priv->udev->dev, "Vendor: %.7s\n",
1966 priv->efuse_wifi.efuse8192eu.vendor_name);
1967 dev_info(&priv->udev->dev, "Product: %.11s\n",
1968 priv->efuse_wifi.efuse8192eu.device_name);
1969 dev_info(&priv->udev->dev, "Serial: %.11s\n",
1970 priv->efuse_wifi.efuse8192eu.serial);
1971
1972 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_EFUSE) {
1973 unsigned char *raw = priv->efuse_wifi.raw;
1974
1975 dev_info(&priv->udev->dev,
1976 "%s: dumping efuse (0x%02zx bytes):\n",
1977 __func__, sizeof(struct rtl8192eu_efuse));
1978 for (i = 0; i < sizeof(struct rtl8192eu_efuse); i += 8) {
1979 dev_info(&priv->udev->dev, "%02x: "
1980 "%02x %02x %02x %02x %02x %02x %02x %02x\n", i,
1981 raw[i], raw[i + 1], raw[i + 2],
1982 raw[i + 3], raw[i + 4], raw[i + 5],
1983 raw[i + 6], raw[i + 7]);
1984 }
1985 }
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]1986 return 0;
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]1987}
1988
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]1989static int
1990rtl8xxxu_read_efuse8(struct rtl8xxxu_priv *priv, u16 offset, u8 *data)
1991{
1992 int i;
1993 u8 val8;
1994 u32 val32;
1995
1996 /* Write Address */
1997 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 1, offset & 0xff);
1998 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 2);
1999 val8 &= 0xfc;
2000 val8 |= (offset >> 8) & 0x03;
2001 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 2, val8);
2002
2003 val8 = rtl8xxxu_read8(priv, REG_EFUSE_CTRL + 3);
2004 rtl8xxxu_write8(priv, REG_EFUSE_CTRL + 3, val8 & 0x7f);
2005
2006 /* Poll for data read */
2007 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2008 for (i = 0; i < RTL8XXXU_MAX_REG_POLL; i++) {
2009 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2010 if (val32 & BIT(31))
2011 break;
2012 }
2013
2014 if (i == RTL8XXXU_MAX_REG_POLL)
2015 return -EIO;
2016
2017 udelay(50);
2018 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
2019
2020 *data = val32 & 0xff;
2021 return 0;
2022}
2023
2024static int rtl8xxxu_read_efuse(struct rtl8xxxu_priv *priv)
2025{
2026 struct device *dev = &priv->udev->dev;
2027 int i, ret = 0;
2028 u8 val8, word_mask, header, extheader;
2029 u16 val16, efuse_addr, offset;
2030 u32 val32;
2031
2032 val16 = rtl8xxxu_read16(priv, REG_9346CR);
2033 if (val16 & EEPROM_ENABLE)
2034 priv->has_eeprom = 1;
2035 if (val16 & EEPROM_BOOT)
2036 priv->boot_eeprom = 1;
2037
Jakub Sitnicki38451992016-02-03 13:39:49 -0500[diff] [blame]2038 if (priv->is_multi_func) {
2039 val32 = rtl8xxxu_read32(priv, REG_EFUSE_TEST);
2040 val32 = (val32 & ~EFUSE_SELECT_MASK) | EFUSE_WIFI_SELECT;
2041 rtl8xxxu_write32(priv, REG_EFUSE_TEST, val32);
2042 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2043
2044 dev_dbg(dev, "Booting from %s\n",
2045 priv->boot_eeprom ? "EEPROM" : "EFUSE");
2046
2047 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_ENABLE);
2048
2049 /* 1.2V Power: From VDDON with Power Cut(0x0000[15]), default valid */
2050 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
2051 if (!(val16 & SYS_ISO_PWC_EV12V)) {
2052 val16 |= SYS_ISO_PWC_EV12V;
2053 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
2054 }
2055 /* Reset: 0x0000[28], default valid */
2056 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2057 if (!(val16 & SYS_FUNC_ELDR)) {
2058 val16 |= SYS_FUNC_ELDR;
2059 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2060 }
2061
2062 /*
2063 * Clock: Gated(0x0008[5]) 8M(0x0008[1]) clock from ANA, default valid
2064 */
2065 val16 = rtl8xxxu_read16(priv, REG_SYS_CLKR);
2066 if (!(val16 & SYS_CLK_LOADER_ENABLE) || !(val16 & SYS_CLK_ANA8M)) {
2067 val16 |= (SYS_CLK_LOADER_ENABLE | SYS_CLK_ANA8M);
2068 rtl8xxxu_write16(priv, REG_SYS_CLKR, val16);
2069 }
2070
2071 /* Default value is 0xff */
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]2072 memset(priv->efuse_wifi.raw, 0xff, EFUSE_MAP_LEN);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2073
2074 efuse_addr = 0;
2075 while (efuse_addr < EFUSE_REAL_CONTENT_LEN_8723A) {
2076 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++, &header);
2077 if (ret || header == 0xff)
2078 goto exit;
2079
2080 if ((header & 0x1f) == 0x0f) { /* extended header */
2081 offset = (header & 0xe0) >> 5;
2082
2083 ret = rtl8xxxu_read_efuse8(priv, efuse_addr++,
2084 &extheader);
2085 if (ret)
2086 goto exit;
2087 /* All words disabled */
2088 if ((extheader & 0x0f) == 0x0f)
2089 continue;
2090
2091 offset |= ((extheader & 0xf0) >> 1);
2092 word_mask = extheader & 0x0f;
2093 } else {
2094 offset = (header >> 4) & 0x0f;
2095 word_mask = header & 0x0f;
2096 }
2097
2098 if (offset < EFUSE_MAX_SECTION_8723A) {
2099 u16 map_addr;
2100 /* Get word enable value from PG header */
2101
2102 /* We have 8 bits to indicate validity */
2103 map_addr = offset * 8;
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]2104 if (map_addr >= EFUSE_MAP_LEN) {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2105 dev_warn(dev, "%s: Illegal map_addr (%04x), "
2106 "efuse corrupt!\n",
2107 __func__, map_addr);
2108 ret = -EINVAL;
2109 goto exit;
2110 }
2111 for (i = 0; i < EFUSE_MAX_WORD_UNIT; i++) {
2112 /* Check word enable condition in the section */
2113 if (!(word_mask & BIT(i))) {
2114 ret = rtl8xxxu_read_efuse8(priv,
2115 efuse_addr++,
2116 &val8);
2117 if (ret)
2118 goto exit;
2119 priv->efuse_wifi.raw[map_addr++] = val8;
2120
2121 ret = rtl8xxxu_read_efuse8(priv,
2122 efuse_addr++,
2123 &val8);
2124 if (ret)
2125 goto exit;
2126 priv->efuse_wifi.raw[map_addr++] = val8;
2127 } else
2128 map_addr += 2;
2129 }
2130 } else {
2131 dev_warn(dev,
2132 "%s: Illegal offset (%04x), efuse corrupt!\n",
2133 __func__, offset);
2134 ret = -EINVAL;
2135 goto exit;
2136 }
2137 }
2138
2139exit:
2140 rtl8xxxu_write8(priv, REG_EFUSE_ACCESS, EFUSE_ACCESS_DISABLE);
2141
2142 return ret;
2143}
2144
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2145static void rtl8xxxu_reset_8051(struct rtl8xxxu_priv *priv)
2146{
2147 u8 val8;
2148 u16 sys_func;
2149
2150 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
Jes Sorensen53b381c2016-02-03 13:39:57 -0500[diff] [blame]2151 val8 &= ~BIT(0);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2152 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2153 sys_func = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2154 sys_func &= ~SYS_FUNC_CPU_ENABLE;
2155 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2156 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
Jes Sorensen53b381c2016-02-03 13:39:57 -0500[diff] [blame]2157 val8 |= BIT(0);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2158 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
2159 sys_func |= SYS_FUNC_CPU_ENABLE;
2160 rtl8xxxu_write16(priv, REG_SYS_FUNC, sys_func);
2161}
2162
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2163static int rtl8xxxu_start_firmware(struct rtl8xxxu_priv *priv)
2164{
2165 struct device *dev = &priv->udev->dev;
2166 int ret = 0, i;
2167 u32 val32;
2168
2169 /* Poll checksum report */
2170 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2171 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2172 if (val32 & MCU_FW_DL_CSUM_REPORT)
2173 break;
2174 }
2175
2176 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2177 dev_warn(dev, "Firmware checksum poll timed out\n");
2178 ret = -EAGAIN;
2179 goto exit;
2180 }
2181
2182 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2183 val32 |= MCU_FW_DL_READY;
2184 val32 &= ~MCU_WINT_INIT_READY;
2185 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
2186
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2187 /*
2188 * Reset the 8051 in order for the firmware to start running,
2189 * otherwise it won't come up on the 8192eu
2190 */
2191 rtl8xxxu_reset_8051(priv);
2192
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2193 /* Wait for firmware to become ready */
2194 for (i = 0; i < RTL8XXXU_FIRMWARE_POLL_MAX; i++) {
2195 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
2196 if (val32 & MCU_WINT_INIT_READY)
2197 break;
2198
2199 udelay(100);
2200 }
2201
2202 if (i == RTL8XXXU_FIRMWARE_POLL_MAX) {
2203 dev_warn(dev, "Firmware failed to start\n");
2204 ret = -EAGAIN;
2205 goto exit;
2206 }
2207
2208exit:
2209 return ret;
2210}
2211
2212static int rtl8xxxu_download_firmware(struct rtl8xxxu_priv *priv)
2213{
2214 int pages, remainder, i, ret;
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2215 u8 val8;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2216 u16 val16;
2217 u32 val32;
2218 u8 *fwptr;
2219
2220 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC + 1);
2221 val8 |= 4;
2222 rtl8xxxu_write8(priv, REG_SYS_FUNC + 1, val8);
2223
2224 /* 8051 enable */
2225 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
Jes Sorensen43154f62016-02-03 13:39:35 -0500[diff] [blame]2226 val16 |= SYS_FUNC_CPU_ENABLE;
2227 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2228
Jes Sorensen216202a2016-02-03 13:39:37 -0500[diff] [blame]2229 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
2230 if (val8 & MCU_FW_RAM_SEL) {
2231 pr_info("do the RAM reset\n");
2232 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
Jes Sorensend48fe602016-02-03 13:39:44 -0500[diff] [blame]2233 rtl8xxxu_reset_8051(priv);
Jes Sorensen216202a2016-02-03 13:39:37 -0500[diff] [blame]2234 }
2235
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2236 /* MCU firmware download enable */
2237 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2238 val8 |= MCU_FW_DL_ENABLE;
2239 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2240
2241 /* 8051 reset */
2242 val32 = rtl8xxxu_read32(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2243 val32 &= ~BIT(19);
2244 rtl8xxxu_write32(priv, REG_MCU_FW_DL, val32);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2245
2246 /* Reset firmware download checksum */
2247 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2248 val8 |= MCU_FW_DL_CSUM_REPORT;
2249 rtl8xxxu_write8(priv, REG_MCU_FW_DL, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2250
2251 pages = priv->fw_size / RTL_FW_PAGE_SIZE;
2252 remainder = priv->fw_size % RTL_FW_PAGE_SIZE;
2253
2254 fwptr = priv->fw_data->data;
2255
2256 for (i = 0; i < pages; i++) {
2257 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2258 val8 |= i;
2259 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2260
2261 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2262 fwptr, RTL_FW_PAGE_SIZE);
2263 if (ret != RTL_FW_PAGE_SIZE) {
2264 ret = -EAGAIN;
2265 goto fw_abort;
2266 }
2267
2268 fwptr += RTL_FW_PAGE_SIZE;
2269 }
2270
2271 if (remainder) {
2272 val8 = rtl8xxxu_read8(priv, REG_MCU_FW_DL + 2) & 0xF8;
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2273 val8 |= i;
2274 rtl8xxxu_write8(priv, REG_MCU_FW_DL + 2, val8);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2275 ret = rtl8xxxu_writeN(priv, REG_FW_START_ADDRESS,
2276 fwptr, remainder);
2277 if (ret != remainder) {
2278 ret = -EAGAIN;
2279 goto fw_abort;
2280 }
2281 }
2282
2283 ret = 0;
2284fw_abort:
2285 /* MCU firmware download disable */
2286 val16 = rtl8xxxu_read16(priv, REG_MCU_FW_DL);
Jes Sorensenef1c0492016-02-03 13:39:36 -0500[diff] [blame]2287 val16 &= ~MCU_FW_DL_ENABLE;
2288 rtl8xxxu_write16(priv, REG_MCU_FW_DL, val16);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2289
2290 return ret;
2291}
2292
2293static int rtl8xxxu_load_firmware(struct rtl8xxxu_priv *priv, char *fw_name)
2294{
2295 struct device *dev = &priv->udev->dev;
2296 const struct firmware *fw;
2297 int ret = 0;
2298 u16 signature;
2299
2300 dev_info(dev, "%s: Loading firmware %s\n", DRIVER_NAME, fw_name);
2301 if (request_firmware(&fw, fw_name, &priv->udev->dev)) {
2302 dev_warn(dev, "request_firmware(%s) failed\n", fw_name);
2303 ret = -EAGAIN;
2304 goto exit;
2305 }
2306 if (!fw) {
2307 dev_warn(dev, "Firmware data not available\n");
2308 ret = -EINVAL;
2309 goto exit;
2310 }
2311
2312 priv->fw_data = kmemdup(fw->data, fw->size, GFP_KERNEL);
Tobias Klauser98e27cb2016-02-03 13:39:43 -0500[diff] [blame]2313 if (!priv->fw_data) {
2314 ret = -ENOMEM;
2315 goto exit;
2316 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2317 priv->fw_size = fw->size - sizeof(struct rtl8xxxu_firmware_header);
2318
2319 signature = le16_to_cpu(priv->fw_data->signature);
2320 switch (signature & 0xfff0) {
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2321 case 0x92e0:
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2322 case 0x92c0:
2323 case 0x88c0:
2324 case 0x2300:
2325 break;
2326 default:
2327 ret = -EINVAL;
2328 dev_warn(dev, "%s: Invalid firmware signature: 0x%04x\n",
2329 __func__, signature);
2330 }
2331
2332 dev_info(dev, "Firmware revision %i.%i (signature 0x%04x)\n",
2333 le16_to_cpu(priv->fw_data->major_version),
2334 priv->fw_data->minor_version, signature);
2335
2336exit:
2337 release_firmware(fw);
2338 return ret;
2339}
2340
2341static int rtl8723au_load_firmware(struct rtl8xxxu_priv *priv)
2342{
2343 char *fw_name;
2344 int ret;
2345
2346 switch (priv->chip_cut) {
2347 case 0:
2348 fw_name = "rtlwifi/rtl8723aufw_A.bin";
2349 break;
2350 case 1:
2351 if (priv->enable_bluetooth)
2352 fw_name = "rtlwifi/rtl8723aufw_B.bin";
2353 else
2354 fw_name = "rtlwifi/rtl8723aufw_B_NoBT.bin";
2355
2356 break;
2357 default:
2358 return -EINVAL;
2359 }
2360
2361 ret = rtl8xxxu_load_firmware(priv, fw_name);
2362 return ret;
2363}
2364
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2365#ifdef CONFIG_RTL8XXXU_UNTESTED
2366
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2367static int rtl8192cu_load_firmware(struct rtl8xxxu_priv *priv)
2368{
2369 char *fw_name;
2370 int ret;
2371
2372 if (!priv->vendor_umc)
2373 fw_name = "rtlwifi/rtl8192cufw_TMSC.bin";
2374 else if (priv->chip_cut || priv->rtlchip == 0x8192c)
2375 fw_name = "rtlwifi/rtl8192cufw_B.bin";
2376 else
2377 fw_name = "rtlwifi/rtl8192cufw_A.bin";
2378
2379 ret = rtl8xxxu_load_firmware(priv, fw_name);
2380
2381 return ret;
2382}
2383
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]2384#endif
2385
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]2386static int rtl8192eu_load_firmware(struct rtl8xxxu_priv *priv)
2387{
2388 char *fw_name;
2389 int ret;
2390
Jes Sorensen0e5d4352016-02-29 17:04:00 -0500[diff] [blame]2391 fw_name = "rtlwifi/rtl8192eu_nic.bin";
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]2392
2393 ret = rtl8xxxu_load_firmware(priv, fw_name);
2394
2395 return ret;
2396}
2397
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2398static void rtl8xxxu_firmware_self_reset(struct rtl8xxxu_priv *priv)
2399{
2400 u16 val16;
2401 int i = 100;
2402
2403 /* Inform 8051 to perform reset */
2404 rtl8xxxu_write8(priv, REG_HMTFR + 3, 0x20);
2405
2406 for (i = 100; i > 0; i--) {
2407 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2408
2409 if (!(val16 & SYS_FUNC_CPU_ENABLE)) {
2410 dev_dbg(&priv->udev->dev,
2411 "%s: Firmware self reset success!\n", __func__);
2412 break;
2413 }
2414 udelay(50);
2415 }
2416
2417 if (!i) {
2418 /* Force firmware reset */
2419 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
2420 val16 &= ~SYS_FUNC_CPU_ENABLE;
2421 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
2422 }
2423}
2424
2425static int
2426rtl8xxxu_init_mac(struct rtl8xxxu_priv *priv, struct rtl8xxxu_reg8val *array)
2427{
2428 int i, ret;
2429 u16 reg;
2430 u8 val;
2431
2432 for (i = 0; ; i++) {
2433 reg = array[i].reg;
2434 val = array[i].val;
2435
2436 if (reg == 0xffff && val == 0xff)
2437 break;
2438
2439 ret = rtl8xxxu_write8(priv, reg, val);
2440 if (ret != 1) {
2441 dev_warn(&priv->udev->dev,
2442 "Failed to initialize MAC\n");
2443 return -EAGAIN;
2444 }
2445 }
2446
2447 rtl8xxxu_write8(priv, REG_MAX_AGGR_NUM, 0x0a);
2448
2449 return 0;
2450}
2451
2452static int rtl8xxxu_init_phy_regs(struct rtl8xxxu_priv *priv,
2453 struct rtl8xxxu_reg32val *array)
2454{
2455 int i, ret;
2456 u16 reg;
2457 u32 val;
2458
2459 for (i = 0; ; i++) {
2460 reg = array[i].reg;
2461 val = array[i].val;
2462
2463 if (reg == 0xffff && val == 0xffffffff)
2464 break;
2465
2466 ret = rtl8xxxu_write32(priv, reg, val);
2467 if (ret != sizeof(val)) {
2468 dev_warn(&priv->udev->dev,
2469 "Failed to initialize PHY\n");
2470 return -EAGAIN;
2471 }
2472 udelay(1);
2473 }
2474
2475 return 0;
2476}
2477
2478/*
2479 * Most of this is black magic retrieved from the old rtl8723au driver
2480 */
2481static int rtl8xxxu_init_phy_bb(struct rtl8xxxu_priv *priv)
2482{
2483 u8 val8, ldoa15, ldov12d, lpldo, ldohci12;
2484 u32 val32;
2485
2486 /*
2487 * Todo: The vendor driver maintains a table of PHY register
2488 * addresses, which is initialized here. Do we need this?
2489 */
2490
2491 val8 = rtl8xxxu_read8(priv, REG_AFE_PLL_CTRL);
2492 udelay(2);
2493 val8 |= AFE_PLL_320_ENABLE;
2494 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL, val8);
2495 udelay(2);
2496
2497 rtl8xxxu_write8(priv, REG_AFE_PLL_CTRL + 1, 0xff);
2498 udelay(2);
2499
2500 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
2501 val8 |= SYS_FUNC_BB_GLB_RSTN | SYS_FUNC_BBRSTB;
2502 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
2503
2504 /* AFE_XTAL_RF_GATE (bit 14) if addressing as 32 bit register */
2505 val32 = rtl8xxxu_read32(priv, REG_AFE_XTAL_CTRL);
2506 val32 &= ~AFE_XTAL_RF_GATE;
2507 if (priv->has_bluetooth)
2508 val32 &= ~AFE_XTAL_BT_GATE;
2509 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, val32);
2510
2511 /* 6. 0x1f[7:0] = 0x07 */
2512 val8 = RF_ENABLE | RF_RSTB | RF_SDMRSTB;
2513 rtl8xxxu_write8(priv, REG_RF_CTRL, val8);
2514
2515 if (priv->hi_pa)
2516 rtl8xxxu_init_phy_regs(priv, rtl8188ru_phy_1t_highpa_table);
2517 else if (priv->tx_paths == 2)
2518 rtl8xxxu_init_phy_regs(priv, rtl8192cu_phy_2t_init_table);
2519 else
2520 rtl8xxxu_init_phy_regs(priv, rtl8723a_phy_1t_init_table);
2521
2522
2523 if (priv->rtlchip == 0x8188c && priv->hi_pa &&
2524 priv->vendor_umc && priv->chip_cut == 1)
2525 rtl8xxxu_write8(priv, REG_OFDM0_AGC_PARM1 + 2, 0x50);
2526
2527 if (priv->tx_paths == 1 && priv->rx_paths == 2) {
2528 /*
2529 * For 1T2R boards, patch the registers.
2530 *
2531 * It looks like 8191/2 1T2R boards use path B for TX
2532 */
2533 val32 = rtl8xxxu_read32(priv, REG_FPGA0_TX_INFO);
2534 val32 &= ~(BIT(0) | BIT(1));
2535 val32 |= BIT(1);
2536 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, val32);
2537
2538 val32 = rtl8xxxu_read32(priv, REG_FPGA1_TX_INFO);
2539 val32 &= ~0x300033;
2540 val32 |= 0x200022;
2541 rtl8xxxu_write32(priv, REG_FPGA1_TX_INFO, val32);
2542
2543 val32 = rtl8xxxu_read32(priv, REG_CCK0_AFE_SETTING);
2544 val32 &= 0xff000000;
2545 val32 |= 0x45000000;
2546 rtl8xxxu_write32(priv, REG_CCK0_AFE_SETTING, val32);
2547
2548 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
2549 val32 &= ~(OFDM_RF_PATH_RX_MASK | OFDM_RF_PATH_TX_MASK);
2550 val32 |= (OFDM_RF_PATH_RX_A | OFDM_RF_PATH_RX_B |
2551 OFDM_RF_PATH_TX_B);
2552 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, val32);
2553
2554 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGC_PARM1);
2555 val32 &= ~(BIT(4) | BIT(5));
2556 val32 |= BIT(4);
2557 rtl8xxxu_write32(priv, REG_OFDM0_AGC_PARM1, val32);
2558
2559 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_RFON);
2560 val32 &= ~(BIT(27) | BIT(26));
2561 val32 |= BIT(27);
2562 rtl8xxxu_write32(priv, REG_TX_CCK_RFON, val32);
2563
2564 val32 = rtl8xxxu_read32(priv, REG_TX_CCK_BBON);
2565 val32 &= ~(BIT(27) | BIT(26));
2566 val32 |= BIT(27);
2567 rtl8xxxu_write32(priv, REG_TX_CCK_BBON, val32);
2568
2569 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_RFON);
2570 val32 &= ~(BIT(27) | BIT(26));
2571 val32 |= BIT(27);
2572 rtl8xxxu_write32(priv, REG_TX_OFDM_RFON, val32);
2573
2574 val32 = rtl8xxxu_read32(priv, REG_TX_OFDM_BBON);
2575 val32 &= ~(BIT(27) | BIT(26));
2576 val32 |= BIT(27);
2577 rtl8xxxu_write32(priv, REG_TX_OFDM_BBON, val32);
2578
2579 val32 = rtl8xxxu_read32(priv, REG_TX_TO_TX);
2580 val32 &= ~(BIT(27) | BIT(26));
2581 val32 |= BIT(27);
2582 rtl8xxxu_write32(priv, REG_TX_TO_TX, val32);
2583 }
2584
2585 if (priv->hi_pa)
2586 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_highpa_table);
2587 else
2588 rtl8xxxu_init_phy_regs(priv, rtl8xxx_agc_standard_table);
2589
2590 if (priv->rtlchip == 0x8723a &&
2591 priv->efuse_wifi.efuse8723.version >= 0x01) {
2592 val32 = rtl8xxxu_read32(priv, REG_MAC_PHY_CTRL);
2593
2594 val8 = priv->efuse_wifi.efuse8723.xtal_k & 0x3f;
2595 val32 &= 0xff000fff;
2596 val32 |= ((val8 | (val8 << 6)) << 12);
2597
2598 rtl8xxxu_write32(priv, REG_MAC_PHY_CTRL, val32);
2599 }
2600
2601 ldoa15 = LDOA15_ENABLE | LDOA15_OBUF;
2602 ldov12d = LDOV12D_ENABLE | BIT(2) | (2 << LDOV12D_VADJ_SHIFT);
2603 ldohci12 = 0x57;
2604 lpldo = 1;
2605 val32 = (lpldo << 24) | (ldohci12 << 16) | (ldov12d << 8) | ldoa15;
2606
2607 rtl8xxxu_write32(priv, REG_LDOA15_CTRL, val32);
2608
2609 return 0;
2610}
2611
2612static int rtl8xxxu_init_rf_regs(struct rtl8xxxu_priv *priv,
2613 struct rtl8xxxu_rfregval *array,
2614 enum rtl8xxxu_rfpath path)
2615{
2616 int i, ret;
2617 u8 reg;
2618 u32 val;
2619
2620 for (i = 0; ; i++) {
2621 reg = array[i].reg;
2622 val = array[i].val;
2623
2624 if (reg == 0xff && val == 0xffffffff)
2625 break;
2626
2627 switch (reg) {
2628 case 0xfe:
2629 msleep(50);
2630 continue;
2631 case 0xfd:
2632 mdelay(5);
2633 continue;
2634 case 0xfc:
2635 mdelay(1);
2636 continue;
2637 case 0xfb:
2638 udelay(50);
2639 continue;
2640 case 0xfa:
2641 udelay(5);
2642 continue;
2643 case 0xf9:
2644 udelay(1);
2645 continue;
2646 }
2647
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]2648 ret = rtl8xxxu_write_rfreg(priv, path, reg, val);
2649 if (ret) {
2650 dev_warn(&priv->udev->dev,
2651 "Failed to initialize RF\n");
2652 return -EAGAIN;
2653 }
2654 udelay(1);
2655 }
2656
2657 return 0;
2658}
2659
2660static int rtl8xxxu_init_phy_rf(struct rtl8xxxu_priv *priv,
2661 struct rtl8xxxu_rfregval *table,
2662 enum rtl8xxxu_rfpath path)
2663{
2664 u32 val32;
2665 u16 val16, rfsi_rfenv;
2666 u16 reg_sw_ctrl, reg_int_oe, reg_hssi_parm2;
2667
2668 switch (path) {
2669 case RF_A:
2670 reg_sw_ctrl = REG_FPGA0_XA_RF_SW_CTRL;
2671 reg_int_oe = REG_FPGA0_XA_RF_INT_OE;
2672 reg_hssi_parm2 = REG_FPGA0_XA_HSSI_PARM2;
2673 break;
2674 case RF_B:
2675 reg_sw_ctrl = REG_FPGA0_XB_RF_SW_CTRL;
2676 reg_int_oe = REG_FPGA0_XB_RF_INT_OE;
2677 reg_hssi_parm2 = REG_FPGA0_XB_HSSI_PARM2;
2678 break;
2679 default:
2680 dev_err(&priv->udev->dev, "%s:Unsupported RF path %c\n",
2681 __func__, path + 'A');
2682 return -EINVAL;
2683 }
2684 /* For path B, use XB */
2685 rfsi_rfenv = rtl8xxxu_read16(priv, reg_sw_ctrl);
2686 rfsi_rfenv &= FPGA0_RF_RFENV;
2687
2688 /*
2689 * These two we might be able to optimize into one
2690 */
2691 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2692 val32 |= BIT(20); /* 0x10 << 16 */
2693 rtl8xxxu_write32(priv, reg_int_oe, val32);
2694 udelay(1);
2695
2696 val32 = rtl8xxxu_read32(priv, reg_int_oe);
2697 val32 |= BIT(4);
2698 rtl8xxxu_write32(priv, reg_int_oe, val32);
2699 udelay(1);
2700
2701 /*
2702 * These two we might be able to optimize into one
2703 */
2704 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2705 val32 &= ~FPGA0_HSSI_3WIRE_ADDR_LEN;
2706 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2707 udelay(1);
2708
2709 val32 = rtl8xxxu_read32(priv, reg_hssi_parm2);
2710 val32 &= ~FPGA0_HSSI_3WIRE_DATA_LEN;
2711 rtl8xxxu_write32(priv, reg_hssi_parm2, val32);
2712 udelay(1);
2713
2714 rtl8xxxu_init_rf_regs(priv, table, path);
2715
2716 /* For path B, use XB */
2717 val16 = rtl8xxxu_read16(priv, reg_sw_ctrl);
2718 val16 &= ~FPGA0_RF_RFENV;
2719 val16 |= rfsi_rfenv;
2720 rtl8xxxu_write16(priv, reg_sw_ctrl, val16);
2721
2722 return 0;
2723}
2724
2725static int rtl8xxxu_llt_write(struct rtl8xxxu_priv *priv, u8 address, u8 data)
2726{
2727 int ret = -EBUSY;
2728 int count = 0;
2729 u32 value;
2730
2731 value = LLT_OP_WRITE | address << 8 | data;
2732
2733 rtl8xxxu_write32(priv, REG_LLT_INIT, value);
2734
2735 do {
2736 value = rtl8xxxu_read32(priv, REG_LLT_INIT);
2737 if ((value & LLT_OP_MASK) == LLT_OP_INACTIVE) {
2738 ret = 0;
2739 break;
2740 }
2741 } while (count++ < 20);
2742
2743 return ret;
2744}
2745
2746static int rtl8xxxu_init_llt_table(struct rtl8xxxu_priv *priv, u8 last_tx_page)
2747{
2748 int ret;
2749 int i;
2750
2751 for (i = 0; i < last_tx_page; i++) {
2752 ret = rtl8xxxu_llt_write(priv, i, i + 1);
2753 if (ret)
2754 goto exit;
2755 }
2756
2757 ret = rtl8xxxu_llt_write(priv, last_tx_page, 0xff);
2758 if (ret)
2759 goto exit;
2760
2761 /* Mark remaining pages as a ring buffer */
2762 for (i = last_tx_page + 1; i < 0xff; i++) {
2763 ret = rtl8xxxu_llt_write(priv, i, (i + 1));
2764 if (ret)
2765 goto exit;
2766 }
2767
2768 /* Let last entry point to the start entry of ring buffer */
2769 ret = rtl8xxxu_llt_write(priv, 0xff, last_tx_page + 1);
2770 if (ret)
2771 goto exit;
2772
2773exit:
2774 return ret;
2775}
2776
2777static int rtl8xxxu_init_queue_priority(struct rtl8xxxu_priv *priv)
2778{
2779 u16 val16, hi, lo;
2780 u16 hiq, mgq, bkq, beq, viq, voq;
2781 int hip, mgp, bkp, bep, vip, vop;
2782 int ret = 0;
2783
2784 switch (priv->ep_tx_count) {
2785 case 1:
2786 if (priv->ep_tx_high_queue) {
2787 hi = TRXDMA_QUEUE_HIGH;
2788 } else if (priv->ep_tx_low_queue) {
2789 hi = TRXDMA_QUEUE_LOW;
2790 } else if (priv->ep_tx_normal_queue) {
2791 hi = TRXDMA_QUEUE_NORMAL;
2792 } else {
2793 hi = 0;
2794 ret = -EINVAL;
2795 }
2796
2797 hiq = hi;
2798 mgq = hi;
2799 bkq = hi;
2800 beq = hi;
2801 viq = hi;
2802 voq = hi;
2803
2804 hip = 0;
2805 mgp = 0;
2806 bkp = 0;
2807 bep = 0;
2808 vip = 0;
2809 vop = 0;
2810 break;
2811 case 2:
2812 if (priv->ep_tx_high_queue && priv->ep_tx_low_queue) {
2813 hi = TRXDMA_QUEUE_HIGH;
2814 lo = TRXDMA_QUEUE_LOW;
2815 } else if (priv->ep_tx_normal_queue && priv->ep_tx_low_queue) {
2816 hi = TRXDMA_QUEUE_NORMAL;
2817 lo = TRXDMA_QUEUE_LOW;
2818 } else if (priv->ep_tx_high_queue && priv->ep_tx_normal_queue) {
2819 hi = TRXDMA_QUEUE_HIGH;
2820 lo = TRXDMA_QUEUE_NORMAL;
2821 } else {
2822 ret = -EINVAL;
2823 hi = 0;
2824 lo = 0;
2825 }
2826
2827 hiq = hi;
2828 mgq = hi;
2829 bkq = lo;
2830 beq = lo;
2831 viq = hi;
2832 voq = hi;
2833
2834 hip = 0;
2835 mgp = 0;
2836 bkp = 1;
2837 bep = 1;
2838 vip = 0;
2839 vop = 0;
2840 break;
2841 case 3:
2842 beq = TRXDMA_QUEUE_LOW;
2843 bkq = TRXDMA_QUEUE_LOW;
2844 viq = TRXDMA_QUEUE_NORMAL;
2845 voq = TRXDMA_QUEUE_HIGH;
2846 mgq = TRXDMA_QUEUE_HIGH;
2847 hiq = TRXDMA_QUEUE_HIGH;
2848
2849 hip = hiq ^ 3;
2850 mgp = mgq ^ 3;
2851 bkp = bkq ^ 3;
2852 bep = beq ^ 3;
2853 vip = viq ^ 3;
2854 vop = viq ^ 3;
2855 break;
2856 default:
2857 ret = -EINVAL;
2858 }
2859
2860 /*
2861 * None of the vendor drivers are configuring the beacon
2862 * queue here .... why?
2863 */
2864 if (!ret) {
2865 val16 = rtl8xxxu_read16(priv, REG_TRXDMA_CTRL);
2866 val16 &= 0x7;
2867 val16 |= (voq << TRXDMA_CTRL_VOQ_SHIFT) |
2868 (viq << TRXDMA_CTRL_VIQ_SHIFT) |
2869 (beq << TRXDMA_CTRL_BEQ_SHIFT) |
2870 (bkq << TRXDMA_CTRL_BKQ_SHIFT) |
2871 (mgq << TRXDMA_CTRL_MGQ_SHIFT) |
2872 (hiq << TRXDMA_CTRL_HIQ_SHIFT);
2873 rtl8xxxu_write16(priv, REG_TRXDMA_CTRL, val16);
2874
2875 priv->pipe_out[TXDESC_QUEUE_VO] =
2876 usb_sndbulkpipe(priv->udev, priv->out_ep[vop]);
2877 priv->pipe_out[TXDESC_QUEUE_VI] =
2878 usb_sndbulkpipe(priv->udev, priv->out_ep[vip]);
2879 priv->pipe_out[TXDESC_QUEUE_BE] =
2880 usb_sndbulkpipe(priv->udev, priv->out_ep[bep]);
2881 priv->pipe_out[TXDESC_QUEUE_BK] =
2882 usb_sndbulkpipe(priv->udev, priv->out_ep[bkp]);
2883 priv->pipe_out[TXDESC_QUEUE_BEACON] =
2884 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2885 priv->pipe_out[TXDESC_QUEUE_MGNT] =
2886 usb_sndbulkpipe(priv->udev, priv->out_ep[mgp]);
2887 priv->pipe_out[TXDESC_QUEUE_HIGH] =
2888 usb_sndbulkpipe(priv->udev, priv->out_ep[hip]);
2889 priv->pipe_out[TXDESC_QUEUE_CMD] =
2890 usb_sndbulkpipe(priv->udev, priv->out_ep[0]);
2891 }
2892
2893 return ret;
2894}
2895
2896static void rtl8xxxu_fill_iqk_matrix_a(struct rtl8xxxu_priv *priv,
2897 bool iqk_ok, int result[][8],
2898 int candidate, bool tx_only)
2899{
2900 u32 oldval, x, tx0_a, reg;
2901 int y, tx0_c;
2902 u32 val32;
2903
2904 if (!iqk_ok)
2905 return;
2906
2907 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2908 oldval = val32 >> 22;
2909
2910 x = result[candidate][0];
2911 if ((x & 0x00000200) != 0)
2912 x = x | 0xfffffc00;
2913 tx0_a = (x * oldval) >> 8;
2914
2915 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2916 val32 &= ~0x3ff;
2917 val32 |= tx0_a;
2918 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2919
2920 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2921 val32 &= ~BIT(31);
2922 if ((x * oldval >> 7) & 0x1)
2923 val32 |= BIT(31);
2924 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2925
2926 y = result[candidate][1];
2927 if ((y & 0x00000200) != 0)
2928 y = y | 0xfffffc00;
2929 tx0_c = (y * oldval) >> 8;
2930
2931 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XC_TX_AFE);
2932 val32 &= ~0xf0000000;
2933 val32 |= (((tx0_c & 0x3c0) >> 6) << 28);
2934 rtl8xxxu_write32(priv, REG_OFDM0_XC_TX_AFE, val32);
2935
2936 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE);
2937 val32 &= ~0x003f0000;
2938 val32 |= ((tx0_c & 0x3f) << 16);
2939 rtl8xxxu_write32(priv, REG_OFDM0_XA_TX_IQ_IMBALANCE, val32);
2940
2941 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2942 val32 &= ~BIT(29);
2943 if ((y * oldval >> 7) & 0x1)
2944 val32 |= BIT(29);
2945 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
2946
2947 if (tx_only) {
2948 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
2949 return;
2950 }
2951
2952 reg = result[candidate][2];
2953
2954 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2955 val32 &= ~0x3ff;
2956 val32 |= (reg & 0x3ff);
2957 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2958
2959 reg = result[candidate][3] & 0x3F;
2960
2961 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE);
2962 val32 &= ~0xfc00;
2963 val32 |= ((reg << 10) & 0xfc00);
2964 rtl8xxxu_write32(priv, REG_OFDM0_XA_RX_IQ_IMBALANCE, val32);
2965
2966 reg = (result[candidate][3] >> 6) & 0xF;
2967
2968 val32 = rtl8xxxu_read32(priv, REG_OFDM0_RX_IQ_EXT_ANTA);
2969 val32 &= ~0xf0000000;
2970 val32 |= (reg << 28);
2971 rtl8xxxu_write32(priv, REG_OFDM0_RX_IQ_EXT_ANTA, val32);
2972}
2973
2974static void rtl8xxxu_fill_iqk_matrix_b(struct rtl8xxxu_priv *priv,
2975 bool iqk_ok, int result[][8],
2976 int candidate, bool tx_only)
2977{
2978 u32 oldval, x, tx1_a, reg;
2979 int y, tx1_c;
2980 u32 val32;
2981
2982 if (!iqk_ok)
2983 return;
2984
2985 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2986 oldval = val32 >> 22;
2987
2988 x = result[candidate][4];
2989 if ((x & 0x00000200) != 0)
2990 x = x | 0xfffffc00;
2991 tx1_a = (x * oldval) >> 8;
2992
2993 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
2994 val32 &= ~0x3ff;
2995 val32 |= tx1_a;
2996 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
2997
2998 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
2999 val32 &= ~BIT(27);
3000 if ((x * oldval >> 7) & 0x1)
3001 val32 |= BIT(27);
3002 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3003
3004 y = result[candidate][5];
3005 if ((y & 0x00000200) != 0)
3006 y = y | 0xfffffc00;
3007 tx1_c = (y * oldval) >> 8;
3008
3009 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XD_TX_AFE);
3010 val32 &= ~0xf0000000;
3011 val32 |= (((tx1_c & 0x3c0) >> 6) << 28);
3012 rtl8xxxu_write32(priv, REG_OFDM0_XD_TX_AFE, val32);
3013
3014 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE);
3015 val32 &= ~0x003f0000;
3016 val32 |= ((tx1_c & 0x3f) << 16);
3017 rtl8xxxu_write32(priv, REG_OFDM0_XB_TX_IQ_IMBALANCE, val32);
3018
3019 val32 = rtl8xxxu_read32(priv, REG_OFDM0_ENERGY_CCA_THRES);
3020 val32 &= ~BIT(25);
3021 if ((y * oldval >> 7) & 0x1)
3022 val32 |= BIT(25);
3023 rtl8xxxu_write32(priv, REG_OFDM0_ENERGY_CCA_THRES, val32);
3024
3025 if (tx_only) {
3026 dev_dbg(&priv->udev->dev, "%s: only TX\n", __func__);
3027 return;
3028 }
3029
3030 reg = result[candidate][6];
3031
3032 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3033 val32 &= ~0x3ff;
3034 val32 |= (reg & 0x3ff);
3035 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3036
3037 reg = result[candidate][7] & 0x3f;
3038
3039 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE);
3040 val32 &= ~0xfc00;
3041 val32 |= ((reg << 10) & 0xfc00);
3042 rtl8xxxu_write32(priv, REG_OFDM0_XB_RX_IQ_IMBALANCE, val32);
3043
3044 reg = (result[candidate][7] >> 6) & 0xf;
3045
3046 val32 = rtl8xxxu_read32(priv, REG_OFDM0_AGCR_SSI_TABLE);
3047 val32 &= ~0x0000f000;
3048 val32 |= (reg << 12);
3049 rtl8xxxu_write32(priv, REG_OFDM0_AGCR_SSI_TABLE, val32);
3050}
3051
3052#define MAX_TOLERANCE 5
3053
3054static bool rtl8xxxu_simularity_compare(struct rtl8xxxu_priv *priv,
3055 int result[][8], int c1, int c2)
3056{
3057 u32 i, j, diff, simubitmap, bound = 0;
3058 int candidate[2] = {-1, -1}; /* for path A and path B */
3059 bool retval = true;
3060
3061 if (priv->tx_paths > 1)
3062 bound = 8;
3063 else
3064 bound = 4;
3065
3066 simubitmap = 0;
3067
3068 for (i = 0; i < bound; i++) {
3069 diff = (result[c1][i] > result[c2][i]) ?
3070 (result[c1][i] - result[c2][i]) :
3071 (result[c2][i] - result[c1][i]);
3072 if (diff > MAX_TOLERANCE) {
3073 if ((i == 2 || i == 6) && !simubitmap) {
3074 if (result[c1][i] + result[c1][i + 1] == 0)
3075 candidate[(i / 4)] = c2;
3076 else if (result[c2][i] + result[c2][i + 1] == 0)
3077 candidate[(i / 4)] = c1;
3078 else
3079 simubitmap = simubitmap | (1 << i);
3080 } else {
3081 simubitmap = simubitmap | (1 << i);
3082 }
3083 }
3084 }
3085
3086 if (simubitmap == 0) {
3087 for (i = 0; i < (bound / 4); i++) {
3088 if (candidate[i] >= 0) {
3089 for (j = i * 4; j < (i + 1) * 4 - 2; j++)
3090 result[3][j] = result[candidate[i]][j];
3091 retval = false;
3092 }
3093 }
3094 return retval;
3095 } else if (!(simubitmap & 0x0f)) {
3096 /* path A OK */
3097 for (i = 0; i < 4; i++)
3098 result[3][i] = result[c1][i];
3099 } else if (!(simubitmap & 0xf0) && priv->tx_paths > 1) {
3100 /* path B OK */
3101 for (i = 4; i < 8; i++)
3102 result[3][i] = result[c1][i];
3103 }
3104
3105 return false;
3106}
3107
3108static void
3109rtl8xxxu_save_mac_regs(struct rtl8xxxu_priv *priv, const u32 *reg, u32 *backup)
3110{
3111 int i;
3112
3113 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3114 backup[i] = rtl8xxxu_read8(priv, reg[i]);
3115
3116 backup[i] = rtl8xxxu_read32(priv, reg[i]);
3117}
3118
3119static void rtl8xxxu_restore_mac_regs(struct rtl8xxxu_priv *priv,
3120 const u32 *reg, u32 *backup)
3121{
3122 int i;
3123
3124 for (i = 0; i < (RTL8XXXU_MAC_REGS - 1); i++)
3125 rtl8xxxu_write8(priv, reg[i], backup[i]);
3126
3127 rtl8xxxu_write32(priv, reg[i], backup[i]);
3128}
3129
3130static void rtl8xxxu_save_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3131 u32 *backup, int count)
3132{
3133 int i;
3134
3135 for (i = 0; i < count; i++)
3136 backup[i] = rtl8xxxu_read32(priv, regs[i]);
3137}
3138
3139static void rtl8xxxu_restore_regs(struct rtl8xxxu_priv *priv, const u32 *regs,
3140 u32 *backup, int count)
3141{
3142 int i;
3143
3144 for (i = 0; i < count; i++)
3145 rtl8xxxu_write32(priv, regs[i], backup[i]);
3146}
3147
3148
3149static void rtl8xxxu_path_adda_on(struct rtl8xxxu_priv *priv, const u32 *regs,
3150 bool path_a_on)
3151{
3152 u32 path_on;
3153 int i;
3154
3155 path_on = path_a_on ? 0x04db25a4 : 0x0b1b25a4;
3156 if (priv->tx_paths == 1) {
3157 path_on = 0x0bdb25a0;
3158 rtl8xxxu_write32(priv, regs[0], 0x0b1b25a0);
3159 } else {
3160 rtl8xxxu_write32(priv, regs[0], path_on);
3161 }
3162
3163 for (i = 1 ; i < RTL8XXXU_ADDA_REGS ; i++)
3164 rtl8xxxu_write32(priv, regs[i], path_on);
3165}
3166
3167static void rtl8xxxu_mac_calibration(struct rtl8xxxu_priv *priv,
3168 const u32 *regs, u32 *backup)
3169{
3170 int i = 0;
3171
3172 rtl8xxxu_write8(priv, regs[i], 0x3f);
3173
3174 for (i = 1 ; i < (RTL8XXXU_MAC_REGS - 1); i++)
3175 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(3)));
3176
3177 rtl8xxxu_write8(priv, regs[i], (u8)(backup[i] & ~BIT(5)));
3178}
3179
3180static int rtl8xxxu_iqk_path_a(struct rtl8xxxu_priv *priv)
3181{
3182 u32 reg_eac, reg_e94, reg_e9c, reg_ea4, val32;
3183 int result = 0;
3184
3185 /* path-A IQK setting */
3186 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x10008c1f);
3187 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x10008c1f);
3188 rtl8xxxu_write32(priv, REG_TX_IQK_PI_A, 0x82140102);
3189
3190 val32 = (priv->rf_paths > 1) ? 0x28160202 :
3191 /*IS_81xxC_VENDOR_UMC_B_CUT(pHalData->VersionID)?0x28160202: */
3192 0x28160502;
3193 rtl8xxxu_write32(priv, REG_RX_IQK_PI_A, val32);
3194
3195 /* path-B IQK setting */
3196 if (priv->rf_paths > 1) {
3197 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_B, 0x10008c22);
3198 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_B, 0x10008c22);
3199 rtl8xxxu_write32(priv, REG_TX_IQK_PI_B, 0x82140102);
3200 rtl8xxxu_write32(priv, REG_RX_IQK_PI_B, 0x28160202);
3201 }
3202
3203 /* LO calibration setting */
3204 rtl8xxxu_write32(priv, REG_IQK_AGC_RSP, 0x001028d1);
3205
3206 /* One shot, path A LOK & IQK */
3207 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf9000000);
3208 rtl8xxxu_write32(priv, REG_IQK_AGC_PTS, 0xf8000000);
3209
3210 mdelay(1);
3211
3212 /* Check failed */
3213 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3214 reg_e94 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_A);
3215 reg_e9c = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_A);
3216 reg_ea4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_A_2);
3217
3218 if (!(reg_eac & BIT(28)) &&
3219 ((reg_e94 & 0x03ff0000) != 0x01420000) &&
3220 ((reg_e9c & 0x03ff0000) != 0x00420000))
3221 result |= 0x01;
3222 else /* If TX not OK, ignore RX */
3223 goto out;
3224
3225 /* If TX is OK, check whether RX is OK */
3226 if (!(reg_eac & BIT(27)) &&
3227 ((reg_ea4 & 0x03ff0000) != 0x01320000) &&
3228 ((reg_eac & 0x03ff0000) != 0x00360000))
3229 result |= 0x02;
3230 else
3231 dev_warn(&priv->udev->dev, "%s: Path A RX IQK failed!\n",
3232 __func__);
3233out:
3234 return result;
3235}
3236
3237static int rtl8xxxu_iqk_path_b(struct rtl8xxxu_priv *priv)
3238{
3239 u32 reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3240 int result = 0;
3241
3242 /* One shot, path B LOK & IQK */
3243 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000002);
3244 rtl8xxxu_write32(priv, REG_IQK_AGC_CONT, 0x00000000);
3245
3246 mdelay(1);
3247
3248 /* Check failed */
3249 reg_eac = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_A_2);
3250 reg_eb4 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3251 reg_ebc = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3252 reg_ec4 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3253 reg_ecc = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3254
3255 if (!(reg_eac & BIT(31)) &&
3256 ((reg_eb4 & 0x03ff0000) != 0x01420000) &&
3257 ((reg_ebc & 0x03ff0000) != 0x00420000))
3258 result |= 0x01;
3259 else
3260 goto out;
3261
3262 if (!(reg_eac & BIT(30)) &&
3263 (((reg_ec4 & 0x03ff0000) >> 16) != 0x132) &&
3264 (((reg_ecc & 0x03ff0000) >> 16) != 0x36))
3265 result |= 0x02;
3266 else
3267 dev_warn(&priv->udev->dev, "%s: Path B RX IQK failed!\n",
3268 __func__);
3269out:
3270 return result;
3271}
3272
3273static void rtl8xxxu_phy_iqcalibrate(struct rtl8xxxu_priv *priv,
3274 int result[][8], int t)
3275{
3276 struct device *dev = &priv->udev->dev;
3277 u32 i, val32;
3278 int path_a_ok, path_b_ok;
3279 int retry = 2;
3280 const u32 adda_regs[RTL8XXXU_ADDA_REGS] = {
3281 REG_FPGA0_XCD_SWITCH_CTRL, REG_BLUETOOTH,
3282 REG_RX_WAIT_CCA, REG_TX_CCK_RFON,
3283 REG_TX_CCK_BBON, REG_TX_OFDM_RFON,
3284 REG_TX_OFDM_BBON, REG_TX_TO_RX,
3285 REG_TX_TO_TX, REG_RX_CCK,
3286 REG_RX_OFDM, REG_RX_WAIT_RIFS,
3287 REG_RX_TO_RX, REG_STANDBY,
3288 REG_SLEEP, REG_PMPD_ANAEN
3289 };
3290 const u32 iqk_mac_regs[RTL8XXXU_MAC_REGS] = {
3291 REG_TXPAUSE, REG_BEACON_CTRL,
3292 REG_BEACON_CTRL_1, REG_GPIO_MUXCFG
3293 };
3294 const u32 iqk_bb_regs[RTL8XXXU_BB_REGS] = {
3295 REG_OFDM0_TRX_PATH_ENABLE, REG_OFDM0_TR_MUX_PAR,
3296 REG_FPGA0_XCD_RF_SW_CTRL, REG_CONFIG_ANT_A, REG_CONFIG_ANT_B,
3297 REG_FPGA0_XAB_RF_SW_CTRL, REG_FPGA0_XA_RF_INT_OE,
3298 REG_FPGA0_XB_RF_INT_OE, REG_FPGA0_RF_MODE
3299 };
3300
3301 /*
3302 * Note: IQ calibration must be performed after loading
3303 * PHY_REG.txt , and radio_a, radio_b.txt
3304 */
3305
3306 if (t == 0) {
3307 /* Save ADDA parameters, turn Path A ADDA on */
3308 rtl8xxxu_save_regs(priv, adda_regs, priv->adda_backup,
3309 RTL8XXXU_ADDA_REGS);
3310 rtl8xxxu_save_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3311 rtl8xxxu_save_regs(priv, iqk_bb_regs,
3312 priv->bb_backup, RTL8XXXU_BB_REGS);
3313 }
3314
3315 rtl8xxxu_path_adda_on(priv, adda_regs, true);
3316
3317 if (t == 0) {
3318 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM1);
3319 if (val32 & FPGA0_HSSI_PARM1_PI)
3320 priv->pi_enabled = 1;
3321 }
3322
3323 if (!priv->pi_enabled) {
3324 /* Switch BB to PI mode to do IQ Calibration. */
3325 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, 0x01000100);
3326 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, 0x01000100);
3327 }
3328
3329 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3330 val32 &= ~FPGA_RF_MODE_CCK;
3331 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
3332
3333 rtl8xxxu_write32(priv, REG_OFDM0_TRX_PATH_ENABLE, 0x03a05600);
3334 rtl8xxxu_write32(priv, REG_OFDM0_TR_MUX_PAR, 0x000800e4);
3335 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_SW_CTRL, 0x22204000);
3336
3337 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XAB_RF_SW_CTRL);
3338 val32 |= (FPGA0_RF_PAPE | (FPGA0_RF_PAPE << FPGA0_RF_BD_CTRL_SHIFT));
3339 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
3340
3341 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_RF_INT_OE);
3342 val32 &= ~BIT(10);
3343 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, val32);
3344 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XB_RF_INT_OE);
3345 val32 &= ~BIT(10);
3346 rtl8xxxu_write32(priv, REG_FPGA0_XB_RF_INT_OE, val32);
3347
3348 if (priv->tx_paths > 1) {
3349 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3350 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM, 0x00010000);
3351 }
3352
3353 /* MAC settings */
3354 rtl8xxxu_mac_calibration(priv, iqk_mac_regs, priv->mac_backup);
3355
3356 /* Page B init */
3357 rtl8xxxu_write32(priv, REG_CONFIG_ANT_A, 0x00080000);
3358
3359 if (priv->tx_paths > 1)
3360 rtl8xxxu_write32(priv, REG_CONFIG_ANT_B, 0x00080000);
3361
3362 /* IQ calibration setting */
3363 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3364 rtl8xxxu_write32(priv, REG_TX_IQK, 0x01007c00);
3365 rtl8xxxu_write32(priv, REG_RX_IQK, 0x01004800);
3366
3367 for (i = 0; i < retry; i++) {
3368 path_a_ok = rtl8xxxu_iqk_path_a(priv);
3369 if (path_a_ok == 0x03) {
3370 val32 = rtl8xxxu_read32(priv,
3371 REG_TX_POWER_BEFORE_IQK_A);
3372 result[t][0] = (val32 >> 16) & 0x3ff;
3373 val32 = rtl8xxxu_read32(priv,
3374 REG_TX_POWER_AFTER_IQK_A);
3375 result[t][1] = (val32 >> 16) & 0x3ff;
3376 val32 = rtl8xxxu_read32(priv,
3377 REG_RX_POWER_BEFORE_IQK_A_2);
3378 result[t][2] = (val32 >> 16) & 0x3ff;
3379 val32 = rtl8xxxu_read32(priv,
3380 REG_RX_POWER_AFTER_IQK_A_2);
3381 result[t][3] = (val32 >> 16) & 0x3ff;
3382 break;
3383 } else if (i == (retry - 1) && path_a_ok == 0x01) {
3384 /* TX IQK OK */
3385 dev_dbg(dev, "%s: Path A IQK Only Tx Success!!\n",
3386 __func__);
3387
3388 val32 = rtl8xxxu_read32(priv,
3389 REG_TX_POWER_BEFORE_IQK_A);
3390 result[t][0] = (val32 >> 16) & 0x3ff;
3391 val32 = rtl8xxxu_read32(priv,
3392 REG_TX_POWER_AFTER_IQK_A);
3393 result[t][1] = (val32 >> 16) & 0x3ff;
3394 }
3395 }
3396
3397 if (!path_a_ok)
3398 dev_dbg(dev, "%s: Path A IQK failed!\n", __func__);
3399
3400 if (priv->tx_paths > 1) {
3401 /*
3402 * Path A into standby
3403 */
3404 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x0);
3405 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00010000);
3406 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0x80800000);
3407
3408 /* Turn Path B ADDA on */
3409 rtl8xxxu_path_adda_on(priv, adda_regs, false);
3410
3411 for (i = 0; i < retry; i++) {
3412 path_b_ok = rtl8xxxu_iqk_path_b(priv);
3413 if (path_b_ok == 0x03) {
3414 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3415 result[t][4] = (val32 >> 16) & 0x3ff;
3416 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3417 result[t][5] = (val32 >> 16) & 0x3ff;
3418 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_BEFORE_IQK_B_2);
3419 result[t][6] = (val32 >> 16) & 0x3ff;
3420 val32 = rtl8xxxu_read32(priv, REG_RX_POWER_AFTER_IQK_B_2);
3421 result[t][7] = (val32 >> 16) & 0x3ff;
3422 break;
3423 } else if (i == (retry - 1) && path_b_ok == 0x01) {
3424 /* TX IQK OK */
3425 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_BEFORE_IQK_B);
3426 result[t][4] = (val32 >> 16) & 0x3ff;
3427 val32 = rtl8xxxu_read32(priv, REG_TX_POWER_AFTER_IQK_B);
3428 result[t][5] = (val32 >> 16) & 0x3ff;
3429 }
3430 }
3431
3432 if (!path_b_ok)
3433 dev_dbg(dev, "%s: Path B IQK failed!\n", __func__);
3434 }
3435
3436 /* Back to BB mode, load original value */
3437 rtl8xxxu_write32(priv, REG_FPGA0_IQK, 0);
3438
3439 if (t) {
3440 if (!priv->pi_enabled) {
3441 /*
3442 * Switch back BB to SI mode after finishing
3443 * IQ Calibration
3444 */
3445 val32 = 0x01000000;
3446 rtl8xxxu_write32(priv, REG_FPGA0_XA_HSSI_PARM1, val32);
3447 rtl8xxxu_write32(priv, REG_FPGA0_XB_HSSI_PARM1, val32);
3448 }
3449
3450 /* Reload ADDA power saving parameters */
3451 rtl8xxxu_restore_regs(priv, adda_regs, priv->adda_backup,
3452 RTL8XXXU_ADDA_REGS);
3453
3454 /* Reload MAC parameters */
3455 rtl8xxxu_restore_mac_regs(priv, iqk_mac_regs, priv->mac_backup);
3456
3457 /* Reload BB parameters */
3458 rtl8xxxu_restore_regs(priv, iqk_bb_regs,
3459 priv->bb_backup, RTL8XXXU_BB_REGS);
3460
3461 /* Restore RX initial gain */
3462 rtl8xxxu_write32(priv, REG_FPGA0_XA_LSSI_PARM, 0x00032ed3);
3463
3464 if (priv->tx_paths > 1) {
3465 rtl8xxxu_write32(priv, REG_FPGA0_XB_LSSI_PARM,
3466 0x00032ed3);
3467 }
3468
3469 /* Load 0xe30 IQC default value */
3470 rtl8xxxu_write32(priv, REG_TX_IQK_TONE_A, 0x01008c00);
3471 rtl8xxxu_write32(priv, REG_RX_IQK_TONE_A, 0x01008c00);
3472 }
3473}
3474
3475static void rtl8723a_phy_iq_calibrate(struct rtl8xxxu_priv *priv)
3476{
3477 struct device *dev = &priv->udev->dev;
3478 int result[4][8]; /* last is final result */
3479 int i, candidate;
3480 bool path_a_ok, path_b_ok;
3481 u32 reg_e94, reg_e9c, reg_ea4, reg_eac;
3482 u32 reg_eb4, reg_ebc, reg_ec4, reg_ecc;
3483 s32 reg_tmp = 0;
3484 bool simu;
3485
3486 memset(result, 0, sizeof(result));
3487 candidate = -1;
3488
3489 path_a_ok = false;
3490 path_b_ok = false;
3491
3492 rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
3493
3494 for (i = 0; i < 3; i++) {
3495 rtl8xxxu_phy_iqcalibrate(priv, result, i);
3496
3497 if (i == 1) {
3498 simu = rtl8xxxu_simularity_compare(priv, result, 0, 1);
3499 if (simu) {
3500 candidate = 0;
3501 break;
3502 }
3503 }
3504
3505 if (i == 2) {
3506 simu = rtl8xxxu_simularity_compare(priv, result, 0, 2);
3507 if (simu) {
3508 candidate = 0;
3509 break;
3510 }
3511
3512 simu = rtl8xxxu_simularity_compare(priv, result, 1, 2);
3513 if (simu) {
3514 candidate = 1;
3515 } else {
3516 for (i = 0; i < 8; i++)
3517 reg_tmp += result[3][i];
3518
3519 if (reg_tmp)
3520 candidate = 3;
3521 else
3522 candidate = -1;
3523 }
3524 }
3525 }
3526
3527 for (i = 0; i < 4; i++) {
3528 reg_e94 = result[i][0];
3529 reg_e9c = result[i][1];
3530 reg_ea4 = result[i][2];
3531 reg_eac = result[i][3];
3532 reg_eb4 = result[i][4];
3533 reg_ebc = result[i][5];
3534 reg_ec4 = result[i][6];
3535 reg_ecc = result[i][7];
3536 }
3537
3538 if (candidate >= 0) {
3539 reg_e94 = result[candidate][0];
3540 priv->rege94 = reg_e94;
3541 reg_e9c = result[candidate][1];
3542 priv->rege9c = reg_e9c;
3543 reg_ea4 = result[candidate][2];
3544 reg_eac = result[candidate][3];
3545 reg_eb4 = result[candidate][4];
3546 priv->regeb4 = reg_eb4;
3547 reg_ebc = result[candidate][5];
3548 priv->regebc = reg_ebc;
3549 reg_ec4 = result[candidate][6];
3550 reg_ecc = result[candidate][7];
3551 dev_dbg(dev, "%s: candidate is %x\n", __func__, candidate);
3552 dev_dbg(dev,
3553 "%s: e94 =%x e9c=%x ea4=%x eac=%x eb4=%x ebc=%x ec4=%x "
3554 "ecc=%x\n ", __func__, reg_e94, reg_e9c,
3555 reg_ea4, reg_eac, reg_eb4, reg_ebc, reg_ec4, reg_ecc);
3556 path_a_ok = true;
3557 path_b_ok = true;
3558 } else {
3559 reg_e94 = reg_eb4 = priv->rege94 = priv->regeb4 = 0x100;
3560 reg_e9c = reg_ebc = priv->rege9c = priv->regebc = 0x0;
3561 }
3562
3563 if (reg_e94 && candidate >= 0)
3564 rtl8xxxu_fill_iqk_matrix_a(priv, path_a_ok, result,
3565 candidate, (reg_ea4 == 0));
3566
3567 if (priv->tx_paths > 1 && reg_eb4)
3568 rtl8xxxu_fill_iqk_matrix_b(priv, path_b_ok, result,
3569 candidate, (reg_ec4 == 0));
3570
3571 rtl8xxxu_save_regs(priv, rtl8723au_iqk_phy_iq_bb_reg,
3572 priv->bb_recovery_backup, RTL8XXXU_BB_REGS);
3573}
3574
3575static void rtl8723a_phy_lc_calibrate(struct rtl8xxxu_priv *priv)
3576{
3577 u32 val32;
3578 u32 rf_amode, rf_bmode = 0, lstf;
3579
3580 /* Check continuous TX and Packet TX */
3581 lstf = rtl8xxxu_read32(priv, REG_OFDM1_LSTF);
3582
3583 if (lstf & OFDM_LSTF_MASK) {
3584 /* Disable all continuous TX */
3585 val32 = lstf & ~OFDM_LSTF_MASK;
3586 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, val32);
3587
3588 /* Read original RF mode Path A */
3589 rf_amode = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_AC);
3590
3591 /* Set RF mode to standby Path A */
3592 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC,
3593 (rf_amode & 0x8ffff) | 0x10000);
3594
3595 /* Path-B */
3596 if (priv->tx_paths > 1) {
3597 rf_bmode = rtl8xxxu_read_rfreg(priv, RF_B,
3598 RF6052_REG_AC);
3599
3600 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3601 (rf_bmode & 0x8ffff) | 0x10000);
3602 }
3603 } else {
3604 /* Deal with Packet TX case */
3605 /* block all queues */
3606 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3607 }
3608
3609 /* Start LC calibration */
3610 val32 = rtl8xxxu_read_rfreg(priv, RF_A, RF6052_REG_MODE_AG);
3611 val32 |= 0x08000;
3612 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_MODE_AG, val32);
3613
3614 msleep(100);
3615
3616 /* Restore original parameters */
3617 if (lstf & OFDM_LSTF_MASK) {
3618 /* Path-A */
3619 rtl8xxxu_write32(priv, REG_OFDM1_LSTF, lstf);
3620 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_AC, rf_amode);
3621
3622 /* Path-B */
3623 if (priv->tx_paths > 1)
3624 rtl8xxxu_write_rfreg(priv, RF_B, RF6052_REG_AC,
3625 rf_bmode);
3626 } else /* Deal with Packet TX case */
3627 rtl8xxxu_write8(priv, REG_TXPAUSE, 0x00);
3628}
3629
3630static int rtl8xxxu_set_mac(struct rtl8xxxu_priv *priv)
3631{
3632 int i;
3633 u16 reg;
3634
3635 reg = REG_MACID;
3636
3637 for (i = 0; i < ETH_ALEN; i++)
3638 rtl8xxxu_write8(priv, reg + i, priv->mac_addr[i]);
3639
3640 return 0;
3641}
3642
3643static int rtl8xxxu_set_bssid(struct rtl8xxxu_priv *priv, const u8 *bssid)
3644{
3645 int i;
3646 u16 reg;
3647
3648 dev_dbg(&priv->udev->dev, "%s: (%pM)\n", __func__, bssid);
3649
3650 reg = REG_BSSID;
3651
3652 for (i = 0; i < ETH_ALEN; i++)
3653 rtl8xxxu_write8(priv, reg + i, bssid[i]);
3654
3655 return 0;
3656}
3657
3658static void
3659rtl8xxxu_set_ampdu_factor(struct rtl8xxxu_priv *priv, u8 ampdu_factor)
3660{
3661 u8 vals[4] = { 0x41, 0xa8, 0x72, 0xb9 };
3662 u8 max_agg = 0xf;
3663 int i;
3664
3665 ampdu_factor = 1 << (ampdu_factor + 2);
3666 if (ampdu_factor > max_agg)
3667 ampdu_factor = max_agg;
3668
3669 for (i = 0; i < 4; i++) {
3670 if ((vals[i] & 0xf0) > (ampdu_factor << 4))
3671 vals[i] = (vals[i] & 0x0f) | (ampdu_factor << 4);
3672
3673 if ((vals[i] & 0x0f) > ampdu_factor)
3674 vals[i] = (vals[i] & 0xf0) | ampdu_factor;
3675
3676 rtl8xxxu_write8(priv, REG_AGGLEN_LMT + i, vals[i]);
3677 }
3678}
3679
3680static void rtl8xxxu_set_ampdu_min_space(struct rtl8xxxu_priv *priv, u8 density)
3681{
3682 u8 val8;
3683
3684 val8 = rtl8xxxu_read8(priv, REG_AMPDU_MIN_SPACE);
3685 val8 &= 0xf8;
3686 val8 |= density;
3687 rtl8xxxu_write8(priv, REG_AMPDU_MIN_SPACE, val8);
3688}
3689
3690static int rtl8xxxu_active_to_emu(struct rtl8xxxu_priv *priv)
3691{
3692 u8 val8;
3693 int count, ret;
3694
3695 /* Start of rtl8723AU_card_enable_flow */
3696 /* Act to Cardemu sequence*/
3697 /* Turn off RF */
3698 rtl8xxxu_write8(priv, REG_RF_CTRL, 0);
3699
3700 /* 0x004E[7] = 0, switch DPDT_SEL_P output from register 0x0065[2] */
3701 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3702 val8 &= ~LEDCFG2_DPDT_SELECT;
3703 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3704
3705 /* 0x0005[1] = 1 turn off MAC by HW state machine*/
3706 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3707 val8 |= BIT(1);
3708 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3709
3710 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3711 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3712 if ((val8 & BIT(1)) == 0)
3713 break;
3714 udelay(10);
3715 }
3716
3717 if (!count) {
3718 dev_warn(&priv->udev->dev, "%s: Disabling MAC timed out\n",
3719 __func__);
3720 ret = -EBUSY;
3721 goto exit;
3722 }
3723
3724 /* 0x0000[5] = 1 analog Ips to digital, 1:isolation */
3725 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3726 val8 |= SYS_ISO_ANALOG_IPS;
3727 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3728
3729 /* 0x0020[0] = 0 disable LDOA12 MACRO block*/
3730 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3731 val8 &= ~LDOA15_ENABLE;
3732 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3733
3734exit:
3735 return ret;
3736}
3737
3738static int rtl8xxxu_active_to_lps(struct rtl8xxxu_priv *priv)
3739{
3740 u8 val8;
3741 u8 val32;
3742 int count, ret;
3743
3744 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
3745
3746 /*
3747 * Poll - wait for RX packet to complete
3748 */
3749 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3750 val32 = rtl8xxxu_read32(priv, 0x5f8);
3751 if (!val32)
3752 break;
3753 udelay(10);
3754 }
3755
3756 if (!count) {
3757 dev_warn(&priv->udev->dev,
3758 "%s: RX poll timed out (0x05f8)\n", __func__);
3759 ret = -EBUSY;
3760 goto exit;
3761 }
3762
3763 /* Disable CCK and OFDM, clock gated */
3764 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3765 val8 &= ~SYS_FUNC_BBRSTB;
3766 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3767
3768 udelay(2);
3769
3770 /* Reset baseband */
3771 val8 = rtl8xxxu_read8(priv, REG_SYS_FUNC);
3772 val8 &= ~SYS_FUNC_BB_GLB_RSTN;
3773 rtl8xxxu_write8(priv, REG_SYS_FUNC, val8);
3774
3775 /* Reset MAC TRX */
3776 val8 = rtl8xxxu_read8(priv, REG_CR);
3777 val8 = CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE;
3778 rtl8xxxu_write8(priv, REG_CR, val8);
3779
3780 /* Reset MAC TRX */
3781 val8 = rtl8xxxu_read8(priv, REG_CR + 1);
3782 val8 &= ~BIT(1); /* CR_SECURITY_ENABLE */
3783 rtl8xxxu_write8(priv, REG_CR + 1, val8);
3784
3785 /* Respond TX OK to scheduler */
3786 val8 = rtl8xxxu_read8(priv, REG_DUAL_TSF_RST);
3787 val8 |= DUAL_TSF_TX_OK;
3788 rtl8xxxu_write8(priv, REG_DUAL_TSF_RST, val8);
3789
3790exit:
3791 return ret;
3792}
3793
3794static void rtl8xxxu_disabled_to_emu(struct rtl8xxxu_priv *priv)
3795{
3796 u8 val8;
3797
3798 /* Clear suspend enable and power down enable*/
3799 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3800 val8 &= ~(BIT(3) | BIT(7));
3801 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3802
3803 /* 0x48[16] = 0 to disable GPIO9 as EXT WAKEUP*/
3804 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3805 val8 &= ~BIT(0);
3806 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3807
3808 /* 0x04[12:11] = 11 enable WL suspend*/
3809 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3810 val8 &= ~(BIT(3) | BIT(4));
3811 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3812}
3813
3814static int rtl8xxxu_emu_to_active(struct rtl8xxxu_priv *priv)
3815{
3816 u8 val8;
3817 u32 val32;
3818 int count, ret = 0;
3819
3820 /* 0x20[0] = 1 enable LDOA12 MACRO block for all interface*/
3821 val8 = rtl8xxxu_read8(priv, REG_LDOA15_CTRL);
3822 val8 |= LDOA15_ENABLE;
3823 rtl8xxxu_write8(priv, REG_LDOA15_CTRL, val8);
3824
3825 /* 0x67[0] = 0 to disable BT_GPS_SEL pins*/
3826 val8 = rtl8xxxu_read8(priv, 0x0067);
3827 val8 &= ~BIT(4);
3828 rtl8xxxu_write8(priv, 0x0067, val8);
3829
3830 mdelay(1);
3831
3832 /* 0x00[5] = 0 release analog Ips to digital, 1:isolation */
3833 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
3834 val8 &= ~SYS_ISO_ANALOG_IPS;
3835 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
3836
3837 /* disable SW LPS 0x04[10]= 0 */
3838 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3839 val8 &= ~BIT(2);
3840 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3841
3842 /* wait till 0x04[17] = 1 power ready*/
3843 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3844 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3845 if (val32 & BIT(17))
3846 break;
3847
3848 udelay(10);
3849 }
3850
3851 if (!count) {
3852 ret = -EBUSY;
3853 goto exit;
3854 }
3855
3856 /* We should be able to optimize the following three entries into one */
3857
3858 /* release WLON reset 0x04[16]= 1*/
3859 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3860 val8 |= BIT(0);
3861 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3862
3863 /* disable HWPDN 0x04[15]= 0*/
3864 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3865 val8 &= ~BIT(7);
3866 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3867
3868 /* disable WL suspend*/
3869 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3870 val8 &= ~(BIT(3) | BIT(4));
3871 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3872
3873 /* set, then poll until 0 */
3874 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3875 val32 |= APS_FSMCO_MAC_ENABLE;
3876 rtl8xxxu_write32(priv, REG_APS_FSMCO, val32);
3877
3878 for (count = RTL8XXXU_MAX_REG_POLL; count; count--) {
3879 val32 = rtl8xxxu_read32(priv, REG_APS_FSMCO);
3880 if ((val32 & APS_FSMCO_MAC_ENABLE) == 0) {
3881 ret = 0;
3882 break;
3883 }
3884 udelay(10);
3885 }
3886
3887 if (!count) {
3888 ret = -EBUSY;
3889 goto exit;
3890 }
3891
3892 /* 0x4C[23] = 0x4E[7] = 1, switch DPDT_SEL_P output from WL BB */
3893 /*
3894 * Note: Vendor driver actually clears this bit, despite the
3895 * documentation claims it's being set!
3896 */
3897 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
3898 val8 |= LEDCFG2_DPDT_SELECT;
3899 val8 &= ~LEDCFG2_DPDT_SELECT;
3900 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
3901
3902exit:
3903 return ret;
3904}
3905
3906static int rtl8xxxu_emu_to_disabled(struct rtl8xxxu_priv *priv)
3907{
3908 u8 val8;
3909
3910 /* 0x0007[7:0] = 0x20 SOP option to disable BG/MB */
3911 rtl8xxxu_write8(priv, REG_APS_FSMCO + 3, 0x20);
3912
3913 /* 0x04[12:11] = 01 enable WL suspend */
3914 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3915 val8 &= ~BIT(4);
3916 val8 |= BIT(3);
3917 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3918
3919 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 1);
3920 val8 |= BIT(7);
3921 rtl8xxxu_write8(priv, REG_APS_FSMCO + 1, val8);
3922
3923 /* 0x48[16] = 1 to enable GPIO9 as EXT wakeup */
3924 val8 = rtl8xxxu_read8(priv, REG_GPIO_INTM + 2);
3925 val8 |= BIT(0);
3926 rtl8xxxu_write8(priv, REG_GPIO_INTM + 2, val8);
3927
3928 return 0;
3929}
3930
3931static int rtl8723au_power_on(struct rtl8xxxu_priv *priv)
3932{
3933 u8 val8;
3934 u16 val16;
3935 u32 val32;
3936 int ret;
3937
3938 /*
3939 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3940 */
3941 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
3942
3943 rtl8xxxu_disabled_to_emu(priv);
3944
3945 ret = rtl8xxxu_emu_to_active(priv);
3946 if (ret)
3947 goto exit;
3948
3949 /*
3950 * 0x0004[19] = 1, reset 8051
3951 */
3952 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO + 2);
3953 val8 |= BIT(3);
3954 rtl8xxxu_write8(priv, REG_APS_FSMCO + 2, val8);
3955
3956 /*
3957 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
3958 * Set CR bit10 to enable 32k calibration.
3959 */
3960 val16 = rtl8xxxu_read16(priv, REG_CR);
3961 val16 |= (CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
3962 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE |
3963 CR_PROTOCOL_ENABLE | CR_SCHEDULE_ENABLE |
3964 CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE |
3965 CR_SECURITY_ENABLE | CR_CALTIMER_ENABLE);
3966 rtl8xxxu_write16(priv, REG_CR, val16);
3967
3968 /* For EFuse PG */
3969 val32 = rtl8xxxu_read32(priv, REG_EFUSE_CTRL);
3970 val32 &= ~(BIT(28) | BIT(29) | BIT(30));
3971 val32 |= (0x06 << 28);
3972 rtl8xxxu_write32(priv, REG_EFUSE_CTRL, val32);
3973exit:
3974 return ret;
3975}
3976
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]3977#ifdef CONFIG_RTL8XXXU_UNTESTED
3978
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]3979static int rtl8192cu_power_on(struct rtl8xxxu_priv *priv)
3980{
3981 u8 val8;
3982 u16 val16;
3983 u32 val32;
3984 int i;
3985
3986 for (i = 100; i; i--) {
3987 val8 = rtl8xxxu_read8(priv, REG_APS_FSMCO);
3988 if (val8 & APS_FSMCO_PFM_ALDN)
3989 break;
3990 }
3991
3992 if (!i) {
3993 pr_info("%s: Poll failed\n", __func__);
3994 return -ENODEV;
3995 }
3996
3997 /*
3998 * RSV_CTRL 0x001C[7:0] = 0x00, unlock ISO/CLK/Power control register
3999 */
4000 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0);
4001 rtl8xxxu_write8(priv, REG_SPS0_CTRL, 0x2b);
4002 udelay(100);
4003
4004 val8 = rtl8xxxu_read8(priv, REG_LDOV12D_CTRL);
4005 if (!(val8 & LDOV12D_ENABLE)) {
4006 pr_info("%s: Enabling LDOV12D (%02x)\n", __func__, val8);
4007 val8 |= LDOV12D_ENABLE;
4008 rtl8xxxu_write8(priv, REG_LDOV12D_CTRL, val8);
4009
4010 udelay(100);
4011
4012 val8 = rtl8xxxu_read8(priv, REG_SYS_ISO_CTRL);
4013 val8 &= ~SYS_ISO_MD2PP;
4014 rtl8xxxu_write8(priv, REG_SYS_ISO_CTRL, val8);
4015 }
4016
4017 /*
4018 * Auto enable WLAN
4019 */
4020 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4021 val16 |= APS_FSMCO_MAC_ENABLE;
4022 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4023
4024 for (i = 1000; i; i--) {
4025 val16 = rtl8xxxu_read16(priv, REG_APS_FSMCO);
4026 if (!(val16 & APS_FSMCO_MAC_ENABLE))
4027 break;
4028 }
4029 if (!i) {
4030 pr_info("%s: FSMCO_MAC_ENABLE poll failed\n", __func__);
4031 return -EBUSY;
4032 }
4033
4034 /*
4035 * Enable radio, GPIO, LED
4036 */
4037 val16 = APS_FSMCO_HW_SUSPEND | APS_FSMCO_ENABLE_POWERDOWN |
4038 APS_FSMCO_PFM_ALDN;
4039 rtl8xxxu_write16(priv, REG_APS_FSMCO, val16);
4040
4041 /*
4042 * Release RF digital isolation
4043 */
4044 val16 = rtl8xxxu_read16(priv, REG_SYS_ISO_CTRL);
4045 val16 &= ~SYS_ISO_DIOR;
4046 rtl8xxxu_write16(priv, REG_SYS_ISO_CTRL, val16);
4047
4048 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4049 val8 &= ~APSD_CTRL_OFF;
4050 rtl8xxxu_write8(priv, REG_APSD_CTRL, val8);
4051 for (i = 200; i; i--) {
4052 val8 = rtl8xxxu_read8(priv, REG_APSD_CTRL);
4053 if (!(val8 & APSD_CTRL_OFF_STATUS))
4054 break;
4055 }
4056
4057 if (!i) {
4058 pr_info("%s: APSD_CTRL poll failed\n", __func__);
4059 return -EBUSY;
4060 }
4061
4062 /*
4063 * Enable MAC DMA/WMAC/SCHEDULE/SEC block
4064 */
4065 val16 = rtl8xxxu_read16(priv, REG_CR);
4066 val16 |= CR_HCI_TXDMA_ENABLE | CR_HCI_RXDMA_ENABLE |
4067 CR_TXDMA_ENABLE | CR_RXDMA_ENABLE | CR_PROTOCOL_ENABLE |
4068 CR_SCHEDULE_ENABLE | CR_MAC_TX_ENABLE | CR_MAC_RX_ENABLE;
4069 rtl8xxxu_write16(priv, REG_CR, val16);
4070
4071 /*
4072 * Workaround for 8188RU LNA power leakage problem.
4073 */
4074 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4075 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4076 val32 &= ~BIT(1);
4077 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4078 }
4079 return 0;
4080}
4081
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]4082#endif
4083
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4084static void rtl8xxxu_power_off(struct rtl8xxxu_priv *priv)
4085{
4086 u8 val8;
4087 u16 val16;
4088 u32 val32;
4089
4090 /*
4091 * Workaround for 8188RU LNA power leakage problem.
4092 */
4093 if (priv->rtlchip == 0x8188c && priv->hi_pa) {
4094 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XCD_RF_PARM);
4095 val32 |= BIT(1);
4096 rtl8xxxu_write32(priv, REG_FPGA0_XCD_RF_PARM, val32);
4097 }
4098
4099 rtl8xxxu_active_to_lps(priv);
4100
4101 /* Turn off RF */
4102 rtl8xxxu_write8(priv, REG_RF_CTRL, 0x00);
4103
4104 /* Reset Firmware if running in RAM */
4105 if (rtl8xxxu_read8(priv, REG_MCU_FW_DL) & MCU_FW_RAM_SEL)
4106 rtl8xxxu_firmware_self_reset(priv);
4107
4108 /* Reset MCU */
4109 val16 = rtl8xxxu_read16(priv, REG_SYS_FUNC);
4110 val16 &= ~SYS_FUNC_CPU_ENABLE;
4111 rtl8xxxu_write16(priv, REG_SYS_FUNC, val16);
4112
4113 /* Reset MCU ready status */
4114 rtl8xxxu_write8(priv, REG_MCU_FW_DL, 0x00);
4115
4116 rtl8xxxu_active_to_emu(priv);
4117 rtl8xxxu_emu_to_disabled(priv);
4118
4119 /* Reset MCU IO Wrapper */
4120 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4121 val8 &= ~BIT(0);
4122 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4123
4124 val8 = rtl8xxxu_read8(priv, REG_RSV_CTRL + 1);
4125 val8 |= BIT(0);
4126 rtl8xxxu_write8(priv, REG_RSV_CTRL + 1, val8);
4127
4128 /* RSV_CTRL 0x1C[7:0] = 0x0e lock ISO/CLK/Power control register */
4129 rtl8xxxu_write8(priv, REG_RSV_CTRL, 0x0e);
4130}
4131
4132static void rtl8xxxu_init_bt(struct rtl8xxxu_priv *priv)
4133{
4134 if (!priv->has_bluetooth)
4135 return;
4136}
4137
4138static int rtl8xxxu_init_device(struct ieee80211_hw *hw)
4139{
4140 struct rtl8xxxu_priv *priv = hw->priv;
4141 struct device *dev = &priv->udev->dev;
4142 struct rtl8xxxu_rfregval *rftable;
4143 bool macpower;
4144 int ret;
4145 u8 val8;
4146 u16 val16;
4147 u32 val32;
4148
4149 /* Check if MAC is already powered on */
4150 val8 = rtl8xxxu_read8(priv, REG_CR);
4151
4152 /*
4153 * Fix 92DU-VC S3 hang with the reason is that secondary mac is not
4154 * initialized. First MAC returns 0xea, second MAC returns 0x00
4155 */
4156 if (val8 == 0xea)
4157 macpower = false;
4158 else
4159 macpower = true;
4160
4161 ret = priv->fops->power_on(priv);
4162 if (ret < 0) {
4163 dev_warn(dev, "%s: Failed power on\n", __func__);
4164 goto exit;
4165 }
4166
4167 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4168 if (!macpower) {
4169 ret = rtl8xxxu_init_llt_table(priv, TX_TOTAL_PAGE_NUM);
4170 if (ret) {
4171 dev_warn(dev, "%s: LLT table init failed\n", __func__);
4172 goto exit;
4173 }
4174 }
4175
4176 ret = rtl8xxxu_download_firmware(priv);
4177 dev_dbg(dev, "%s: download_fiwmare %i\n", __func__, ret);
4178 if (ret)
4179 goto exit;
4180 ret = rtl8xxxu_start_firmware(priv);
4181 dev_dbg(dev, "%s: start_fiwmare %i\n", __func__, ret);
4182 if (ret)
4183 goto exit;
4184
4185 ret = rtl8xxxu_init_mac(priv, rtl8723a_mac_init_table);
4186 dev_dbg(dev, "%s: init_mac %i\n", __func__, ret);
4187 if (ret)
4188 goto exit;
4189
4190 ret = rtl8xxxu_init_phy_bb(priv);
4191 dev_dbg(dev, "%s: init_phy_bb %i\n", __func__, ret);
4192 if (ret)
4193 goto exit;
4194
4195 switch(priv->rtlchip) {
4196 case 0x8723a:
4197 rftable = rtl8723au_radioa_1t_init_table;
4198 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4199 break;
4200 case 0x8188c:
4201 if (priv->hi_pa)
4202 rftable = rtl8188ru_radioa_1t_highpa_table;
4203 else
4204 rftable = rtl8192cu_radioa_1t_init_table;
4205 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4206 break;
4207 case 0x8191c:
4208 rftable = rtl8192cu_radioa_1t_init_table;
4209 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4210 break;
4211 case 0x8192c:
4212 rftable = rtl8192cu_radioa_2t_init_table;
4213 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_A);
4214 if (ret)
4215 break;
4216 rftable = rtl8192cu_radiob_2t_init_table;
4217 ret = rtl8xxxu_init_phy_rf(priv, rftable, RF_B);
4218 break;
4219 default:
4220 ret = -EINVAL;
4221 }
4222
4223 if (ret)
4224 goto exit;
4225
4226 /* Reduce 80M spur */
4227 rtl8xxxu_write32(priv, REG_AFE_XTAL_CTRL, 0x0381808d);
4228 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4229 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff82);
4230 rtl8xxxu_write32(priv, REG_AFE_PLL_CTRL, 0xf0ffff83);
4231
4232 /* RFSW Control - clear bit 14 ?? */
4233 rtl8xxxu_write32(priv, REG_FPGA0_TX_INFO, 0x00000003);
4234 /* 0x07000760 */
4235 val32 = FPGA0_RF_TRSW | FPGA0_RF_TRSWB | FPGA0_RF_ANTSW |
4236 FPGA0_RF_ANTSWB | FPGA0_RF_PAPE |
4237 ((FPGA0_RF_ANTSW | FPGA0_RF_ANTSWB | FPGA0_RF_PAPE) <<
4238 FPGA0_RF_BD_CTRL_SHIFT);
4239 rtl8xxxu_write32(priv, REG_FPGA0_XAB_RF_SW_CTRL, val32);
4240 /* 0x860[6:5]= 00 - why? - this sets antenna B */
4241 rtl8xxxu_write32(priv, REG_FPGA0_XA_RF_INT_OE, 0x66F60210);
4242
4243 priv->rf_mode_ag[0] = rtl8xxxu_read_rfreg(priv, RF_A,
4244 RF6052_REG_MODE_AG);
4245
4246 dev_dbg(dev, "%s: macpower %i\n", __func__, macpower);
4247 if (!macpower) {
4248 if (priv->ep_tx_normal_queue)
4249 val8 = TX_PAGE_NUM_NORM_PQ;
4250 else
4251 val8 = 0;
4252
4253 rtl8xxxu_write8(priv, REG_RQPN_NPQ, val8);
4254
4255 val32 = (TX_PAGE_NUM_PUBQ << RQPN_NORM_PQ_SHIFT) | RQPN_LOAD;
4256
4257 if (priv->ep_tx_high_queue)
4258 val32 |= (TX_PAGE_NUM_HI_PQ << RQPN_HI_PQ_SHIFT);
4259 if (priv->ep_tx_low_queue)
4260 val32 |= (TX_PAGE_NUM_LO_PQ << RQPN_LO_PQ_SHIFT);
4261
4262 rtl8xxxu_write32(priv, REG_RQPN, val32);
4263
4264 /*
4265 * Set TX buffer boundary
4266 */
4267 val8 = TX_TOTAL_PAGE_NUM + 1;
4268 rtl8xxxu_write8(priv, REG_TXPKTBUF_BCNQ_BDNY, val8);
4269 rtl8xxxu_write8(priv, REG_TXPKTBUF_MGQ_BDNY, val8);
4270 rtl8xxxu_write8(priv, REG_TXPKTBUF_WMAC_LBK_BF_HD, val8);
4271 rtl8xxxu_write8(priv, REG_TRXFF_BNDY, val8);
4272 rtl8xxxu_write8(priv, REG_TDECTRL + 1, val8);
4273 }
4274
4275 ret = rtl8xxxu_init_queue_priority(priv);
4276 dev_dbg(dev, "%s: init_queue_priority %i\n", __func__, ret);
4277 if (ret)
4278 goto exit;
4279
4280 /*
4281 * Set RX page boundary
4282 */
4283 rtl8xxxu_write16(priv, REG_TRXFF_BNDY + 2, 0x27ff);
4284 /*
4285 * Transfer page size is always 128
4286 */
4287 val8 = (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_RX_SHIFT) |
4288 (PBP_PAGE_SIZE_128 << PBP_PAGE_SIZE_TX_SHIFT);
4289 rtl8xxxu_write8(priv, REG_PBP, val8);
4290
4291 /*
4292 * Unit in 8 bytes, not obvious what it is used for
4293 */
4294 rtl8xxxu_write8(priv, REG_RX_DRVINFO_SZ, 4);
4295
4296 /*
4297 * Enable all interrupts - not obvious USB needs to do this
4298 */
4299 rtl8xxxu_write32(priv, REG_HISR, 0xffffffff);
4300 rtl8xxxu_write32(priv, REG_HIMR, 0xffffffff);
4301
4302 rtl8xxxu_set_mac(priv);
4303 rtl8xxxu_set_linktype(priv, NL80211_IFTYPE_STATION);
4304
4305 /*
4306 * Configure initial WMAC settings
4307 */
4308 val32 = RCR_ACCEPT_PHYS_MATCH | RCR_ACCEPT_MCAST | RCR_ACCEPT_BCAST |
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4309 RCR_ACCEPT_MGMT_FRAME | RCR_HTC_LOC_CTRL |
4310 RCR_APPEND_PHYSTAT | RCR_APPEND_ICV | RCR_APPEND_MIC;
4311 rtl8xxxu_write32(priv, REG_RCR, val32);
4312
4313 /*
4314 * Accept all multicast
4315 */
4316 rtl8xxxu_write32(priv, REG_MAR, 0xffffffff);
4317 rtl8xxxu_write32(priv, REG_MAR + 4, 0xffffffff);
4318
4319 /*
4320 * Init adaptive controls
4321 */
4322 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4323 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4324 val32 |= RESPONSE_RATE_RRSR_CCK_ONLY_1M;
4325 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4326
4327 /* CCK = 0x0a, OFDM = 0x10 */
4328 rtl8xxxu_set_spec_sifs(priv, 0x10, 0x10);
4329 rtl8xxxu_set_retry(priv, 0x30, 0x30);
4330 rtl8xxxu_set_spec_sifs(priv, 0x0a, 0x10);
4331
4332 /*
4333 * Init EDCA
4334 */
4335 rtl8xxxu_write16(priv, REG_MAC_SPEC_SIFS, 0x100a);
4336
4337 /* Set CCK SIFS */
4338 rtl8xxxu_write16(priv, REG_SIFS_CCK, 0x100a);
4339
4340 /* Set OFDM SIFS */
4341 rtl8xxxu_write16(priv, REG_SIFS_OFDM, 0x100a);
4342
4343 /* TXOP */
4344 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, 0x005ea42b);
4345 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, 0x0000a44f);
4346 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, 0x005ea324);
4347 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, 0x002fa226);
4348
4349 /* Set data auto rate fallback retry count */
4350 rtl8xxxu_write32(priv, REG_DARFRC, 0x00000000);
4351 rtl8xxxu_write32(priv, REG_DARFRC + 4, 0x10080404);
4352 rtl8xxxu_write32(priv, REG_RARFRC, 0x04030201);
4353 rtl8xxxu_write32(priv, REG_RARFRC + 4, 0x08070605);
4354
4355 val8 = rtl8xxxu_read8(priv, REG_FWHW_TXQ_CTRL);
4356 val8 |= FWHW_TXQ_CTRL_AMPDU_RETRY;
4357 rtl8xxxu_write8(priv, REG_FWHW_TXQ_CTRL, val8);
4358
4359 /* Set ACK timeout */
4360 rtl8xxxu_write8(priv, REG_ACKTO, 0x40);
4361
4362 /*
4363 * Initialize beacon parameters
4364 */
4365 val16 = BEACON_DISABLE_TSF_UPDATE | (BEACON_DISABLE_TSF_UPDATE << 8);
4366 rtl8xxxu_write16(priv, REG_BEACON_CTRL, val16);
4367 rtl8xxxu_write16(priv, REG_TBTT_PROHIBIT, 0x6404);
4368 rtl8xxxu_write8(priv, REG_DRIVER_EARLY_INT, DRIVER_EARLY_INT_TIME);
4369 rtl8xxxu_write8(priv, REG_BEACON_DMA_TIME, BEACON_DMA_ATIME_INT_TIME);
4370 rtl8xxxu_write16(priv, REG_BEACON_TCFG, 0x660F);
4371
4372 /*
4373 * Enable CCK and OFDM block
4374 */
4375 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4376 val32 |= (FPGA_RF_MODE_CCK | FPGA_RF_MODE_OFDM);
4377 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4378
4379 /*
4380 * Invalidate all CAM entries - bit 30 is undocumented
4381 */
4382 rtl8xxxu_write32(priv, REG_CAM_CMD, CAM_CMD_POLLING | BIT(30));
4383
4384 /*
4385 * Start out with default power levels for channel 6, 20MHz
4386 */
4387 rtl8723a_set_tx_power(priv, 1, false);
4388
4389 /* Let the 8051 take control of antenna setting */
4390 val8 = rtl8xxxu_read8(priv, REG_LEDCFG2);
4391 val8 |= LEDCFG2_DPDT_SELECT;
4392 rtl8xxxu_write8(priv, REG_LEDCFG2, val8);
4393
4394 rtl8xxxu_write8(priv, REG_HWSEQ_CTRL, 0xff);
4395
4396 /* Disable BAR - not sure if this has any effect on USB */
4397 rtl8xxxu_write32(priv, REG_BAR_MODE_CTRL, 0x0201ffff);
4398
4399 rtl8xxxu_write16(priv, REG_FAST_EDCA_CTRL, 0);
4400
Jes Sorensene5c447c2016-02-03 13:39:48 -0500[diff] [blame]4401 rtl8723a_phy_iq_calibrate(priv);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4402
4403 /*
4404 * This should enable thermal meter
4405 */
4406 rtl8xxxu_write_rfreg(priv, RF_A, RF6052_REG_T_METER, 0x60);
4407
4408 rtl8723a_phy_lc_calibrate(priv);
4409
4410 /* fix USB interface interference issue */
4411 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4412 rtl8xxxu_write8(priv, 0xfe41, 0x8d);
4413 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4414 rtl8xxxu_write32(priv, REG_TXDMA_OFFSET_CHK, 0xfd0320);
4415
4416 /* Solve too many protocol error on USB bus */
4417 /* Can't do this for 8188/8192 UMC A cut parts */
4418 rtl8xxxu_write8(priv, 0xfe40, 0xe6);
4419 rtl8xxxu_write8(priv, 0xfe41, 0x94);
4420 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4421
4422 rtl8xxxu_write8(priv, 0xfe40, 0xe0);
4423 rtl8xxxu_write8(priv, 0xfe41, 0x19);
4424 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4425
4426 rtl8xxxu_write8(priv, 0xfe40, 0xe5);
4427 rtl8xxxu_write8(priv, 0xfe41, 0x91);
4428 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4429
4430 rtl8xxxu_write8(priv, 0xfe40, 0xe2);
4431 rtl8xxxu_write8(priv, 0xfe41, 0x81);
4432 rtl8xxxu_write8(priv, 0xfe42, 0x80);
4433
4434 /* Init BT hw config. */
4435 rtl8xxxu_init_bt(priv);
4436
4437 /*
4438 * Not sure if we really need to save these parameters, but the
4439 * vendor driver does
4440 */
4441 val32 = rtl8xxxu_read32(priv, REG_FPGA0_XA_HSSI_PARM2);
4442 if (val32 & FPGA0_HSSI_PARM2_CCK_HIGH_PWR)
4443 priv->path_a_hi_power = 1;
4444
4445 val32 = rtl8xxxu_read32(priv, REG_OFDM0_TRX_PATH_ENABLE);
4446 priv->path_a_rf_paths = val32 & OFDM_RF_PATH_RX_MASK;
4447
4448 val32 = rtl8xxxu_read32(priv, REG_OFDM0_XA_AGC_CORE1);
4449 priv->path_a_ig_value = val32 & OFDM0_X_AGC_CORE1_IGI_MASK;
4450
4451 /* Set NAV_UPPER to 30000us */
4452 val8 = ((30000 + NAV_UPPER_UNIT - 1) / NAV_UPPER_UNIT);
4453 rtl8xxxu_write8(priv, REG_NAV_UPPER, val8);
4454
Jes Sorensen4042e612016-02-03 13:40:01 -0500[diff] [blame]4455 if (priv->rtlchip == 0x8723a) {
4456 /*
4457 * 2011/03/09 MH debug only, UMC-B cut pass 2500 S5 test,
4458 * but we need to find root cause.
4459 * This is 8723au only.
4460 */
4461 val32 = rtl8xxxu_read32(priv, REG_FPGA0_RF_MODE);
4462 if ((val32 & 0xff000000) != 0x83000000) {
4463 val32 |= FPGA_RF_MODE_CCK;
4464 rtl8xxxu_write32(priv, REG_FPGA0_RF_MODE, val32);
4465 }
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4466 }
4467
4468 val32 = rtl8xxxu_read32(priv, REG_FWHW_TXQ_CTRL);
4469 val32 |= FWHW_TXQ_CTRL_XMIT_MGMT_ACK;
4470 /* ack for xmit mgmt frames. */
4471 rtl8xxxu_write32(priv, REG_FWHW_TXQ_CTRL, val32);
4472
4473exit:
4474 return ret;
4475}
4476
4477static void rtl8xxxu_disable_device(struct ieee80211_hw *hw)
4478{
4479 struct rtl8xxxu_priv *priv = hw->priv;
4480
4481 rtl8xxxu_power_off(priv);
4482}
4483
4484static void rtl8xxxu_cam_write(struct rtl8xxxu_priv *priv,
4485 struct ieee80211_key_conf *key, const u8 *mac)
4486{
4487 u32 cmd, val32, addr, ctrl;
4488 int j, i, tmp_debug;
4489
4490 tmp_debug = rtl8xxxu_debug;
4491 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_KEY)
4492 rtl8xxxu_debug |= RTL8XXXU_DEBUG_REG_WRITE;
4493
4494 /*
4495 * This is a bit of a hack - the lower bits of the cipher
4496 * suite selector happens to match the cipher index in the CAM
4497 */
4498 addr = key->keyidx << CAM_CMD_KEY_SHIFT;
4499 ctrl = (key->cipher & 0x0f) << 2 | key->keyidx | CAM_WRITE_VALID;
4500
4501 for (j = 5; j >= 0; j--) {
4502 switch (j) {
4503 case 0:
4504 val32 = ctrl | (mac[0] << 16) | (mac[1] << 24);
4505 break;
4506 case 1:
4507 val32 = mac[2] | (mac[3] << 8) |
4508 (mac[4] << 16) | (mac[5] << 24);
4509 break;
4510 default:
4511 i = (j - 2) << 2;
4512 val32 = key->key[i] | (key->key[i + 1] << 8) |
4513 key->key[i + 2] << 16 | key->key[i + 3] << 24;
4514 break;
4515 }
4516
4517 rtl8xxxu_write32(priv, REG_CAM_WRITE, val32);
4518 cmd = CAM_CMD_POLLING | CAM_CMD_WRITE | (addr + j);
4519 rtl8xxxu_write32(priv, REG_CAM_CMD, cmd);
4520 udelay(100);
4521 }
4522
4523 rtl8xxxu_debug = tmp_debug;
4524}
4525
4526static void rtl8xxxu_sw_scan_start(struct ieee80211_hw *hw,
Jes Sorensen56e43742016-02-03 13:39:50 -0500[diff] [blame]4527 struct ieee80211_vif *vif, const u8 *mac)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4528{
4529 struct rtl8xxxu_priv *priv = hw->priv;
4530 u8 val8;
4531
4532 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4533 val8 |= BEACON_DISABLE_TSF_UPDATE;
4534 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4535}
4536
4537static void rtl8xxxu_sw_scan_complete(struct ieee80211_hw *hw,
4538 struct ieee80211_vif *vif)
4539{
4540 struct rtl8xxxu_priv *priv = hw->priv;
4541 u8 val8;
4542
4543 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4544 val8 &= ~BEACON_DISABLE_TSF_UPDATE;
4545 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4546}
4547
4548static void rtl8xxxu_update_rate_mask(struct rtl8xxxu_priv *priv,
4549 u32 ramask, int sgi)
4550{
4551 struct h2c_cmd h2c;
4552
4553 h2c.ramask.cmd = H2C_SET_RATE_MASK;
4554 h2c.ramask.mask_lo = cpu_to_le16(ramask & 0xffff);
4555 h2c.ramask.mask_hi = cpu_to_le16(ramask >> 16);
4556
4557 h2c.ramask.arg = 0x80;
4558 if (sgi)
4559 h2c.ramask.arg |= 0x20;
4560
4561 dev_dbg(&priv->udev->dev, "%s: rate mask %08x, arg %02x\n", __func__,
4562 ramask, h2c.ramask.arg);
4563 rtl8723a_h2c_cmd(priv, &h2c);
4564}
4565
4566static void rtl8xxxu_set_basic_rates(struct rtl8xxxu_priv *priv, u32 rate_cfg)
4567{
4568 u32 val32;
4569 u8 rate_idx = 0;
4570
4571 rate_cfg &= RESPONSE_RATE_BITMAP_ALL;
4572
4573 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4574 val32 &= ~RESPONSE_RATE_BITMAP_ALL;
4575 val32 |= rate_cfg;
4576 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4577
4578 dev_dbg(&priv->udev->dev, "%s: rates %08x\n", __func__, rate_cfg);
4579
4580 while (rate_cfg) {
4581 rate_cfg = (rate_cfg >> 1);
4582 rate_idx++;
4583 }
4584 rtl8xxxu_write8(priv, REG_INIRTS_RATE_SEL, rate_idx);
4585}
4586
4587static void
4588rtl8xxxu_bss_info_changed(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
4589 struct ieee80211_bss_conf *bss_conf, u32 changed)
4590{
4591 struct rtl8xxxu_priv *priv = hw->priv;
4592 struct device *dev = &priv->udev->dev;
4593 struct ieee80211_sta *sta;
4594 u32 val32;
4595 u8 val8;
4596
4597 if (changed & BSS_CHANGED_ASSOC) {
4598 struct h2c_cmd h2c;
4599
4600 dev_dbg(dev, "Changed ASSOC: %i!\n", bss_conf->assoc);
4601
4602 memset(&h2c, 0, sizeof(struct h2c_cmd));
4603 rtl8xxxu_set_linktype(priv, vif->type);
4604
4605 if (bss_conf->assoc) {
4606 u32 ramask;
4607 int sgi = 0;
4608
4609 rcu_read_lock();
4610 sta = ieee80211_find_sta(vif, bss_conf->bssid);
4611 if (!sta) {
4612 dev_info(dev, "%s: ASSOC no sta found\n",
4613 __func__);
4614 rcu_read_unlock();
4615 goto error;
4616 }
4617
4618 if (sta->ht_cap.ht_supported)
4619 dev_info(dev, "%s: HT supported\n", __func__);
4620 if (sta->vht_cap.vht_supported)
4621 dev_info(dev, "%s: VHT supported\n", __func__);
4622
4623 /* TODO: Set bits 28-31 for rate adaptive id */
4624 ramask = (sta->supp_rates[0] & 0xfff) |
4625 sta->ht_cap.mcs.rx_mask[0] << 12 |
4626 sta->ht_cap.mcs.rx_mask[1] << 20;
4627 if (sta->ht_cap.cap &
4628 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))
4629 sgi = 1;
4630 rcu_read_unlock();
4631
4632 rtl8xxxu_update_rate_mask(priv, ramask, sgi);
4633
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4634 rtl8xxxu_write8(priv, REG_BCN_MAX_ERR, 0xff);
4635
4636 rtl8723a_stop_tx_beacon(priv);
4637
4638 /* joinbss sequence */
4639 rtl8xxxu_write16(priv, REG_BCN_PSR_RPT,
4640 0xc000 | bss_conf->aid);
4641
4642 h2c.joinbss.data = H2C_JOIN_BSS_CONNECT;
4643 } else {
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4644 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
4645 val8 |= BEACON_DISABLE_TSF_UPDATE;
4646 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
4647
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]4648 h2c.joinbss.data = H2C_JOIN_BSS_DISCONNECT;
4649 }
4650 h2c.joinbss.cmd = H2C_JOIN_BSS_REPORT;
4651 rtl8723a_h2c_cmd(priv, &h2c);
4652 }
4653
4654 if (changed & BSS_CHANGED_ERP_PREAMBLE) {
4655 dev_dbg(dev, "Changed ERP_PREAMBLE: Use short preamble %i\n",
4656 bss_conf->use_short_preamble);
4657 val32 = rtl8xxxu_read32(priv, REG_RESPONSE_RATE_SET);
4658 if (bss_conf->use_short_preamble)
4659 val32 |= RSR_ACK_SHORT_PREAMBLE;
4660 else
4661 val32 &= ~RSR_ACK_SHORT_PREAMBLE;
4662 rtl8xxxu_write32(priv, REG_RESPONSE_RATE_SET, val32);
4663 }
4664
4665 if (changed & BSS_CHANGED_ERP_SLOT) {
4666 dev_dbg(dev, "Changed ERP_SLOT: short_slot_time %i\n",
4667 bss_conf->use_short_slot);
4668
4669 if (bss_conf->use_short_slot)
4670 val8 = 9;
4671 else
4672 val8 = 20;
4673 rtl8xxxu_write8(priv, REG_SLOT, val8);
4674 }
4675
4676 if (changed & BSS_CHANGED_BSSID) {
4677 dev_dbg(dev, "Changed BSSID!\n");
4678 rtl8xxxu_set_bssid(priv, bss_conf->bssid);
4679 }
4680
4681 if (changed & BSS_CHANGED_BASIC_RATES) {
4682 dev_dbg(dev, "Changed BASIC_RATES!\n");
4683 rtl8xxxu_set_basic_rates(priv, bss_conf->basic_rates);
4684 }
4685error:
4686 return;
4687}
4688
4689static u32 rtl8xxxu_80211_to_rtl_queue(u32 queue)
4690{
4691 u32 rtlqueue;
4692
4693 switch (queue) {
4694 case IEEE80211_AC_VO:
4695 rtlqueue = TXDESC_QUEUE_VO;
4696 break;
4697 case IEEE80211_AC_VI:
4698 rtlqueue = TXDESC_QUEUE_VI;
4699 break;
4700 case IEEE80211_AC_BE:
4701 rtlqueue = TXDESC_QUEUE_BE;
4702 break;
4703 case IEEE80211_AC_BK:
4704 rtlqueue = TXDESC_QUEUE_BK;
4705 break;
4706 default:
4707 rtlqueue = TXDESC_QUEUE_BE;
4708 }
4709
4710 return rtlqueue;
4711}
4712
4713static u32 rtl8xxxu_queue_select(struct ieee80211_hw *hw, struct sk_buff *skb)
4714{
4715 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4716 u32 queue;
4717
4718 if (ieee80211_is_mgmt(hdr->frame_control))
4719 queue = TXDESC_QUEUE_MGNT;
4720 else
4721 queue = rtl8xxxu_80211_to_rtl_queue(skb_get_queue_mapping(skb));
4722
4723 return queue;
4724}
4725
4726static void rtl8xxxu_calc_tx_desc_csum(struct rtl8xxxu_tx_desc *tx_desc)
4727{
4728 __le16 *ptr = (__le16 *)tx_desc;
4729 u16 csum = 0;
4730 int i;
4731
4732 /*
4733 * Clear csum field before calculation, as the csum field is
4734 * in the middle of the struct.
4735 */
4736 tx_desc->csum = cpu_to_le16(0);
4737
4738 for (i = 0; i < (sizeof(struct rtl8xxxu_tx_desc) / sizeof(u16)); i++)
4739 csum = csum ^ le16_to_cpu(ptr[i]);
4740
4741 tx_desc->csum |= cpu_to_le16(csum);
4742}
4743
4744static void rtl8xxxu_free_tx_resources(struct rtl8xxxu_priv *priv)
4745{
4746 struct rtl8xxxu_tx_urb *tx_urb, *tmp;
4747 unsigned long flags;
4748
4749 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4750 list_for_each_entry_safe(tx_urb, tmp, &priv->tx_urb_free_list, list) {
4751 list_del(&tx_urb->list);
4752 priv->tx_urb_free_count--;
4753 usb_free_urb(&tx_urb->urb);
4754 }
4755 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4756}
4757
4758static struct rtl8xxxu_tx_urb *
4759rtl8xxxu_alloc_tx_urb(struct rtl8xxxu_priv *priv)
4760{
4761 struct rtl8xxxu_tx_urb *tx_urb;
4762 unsigned long flags;
4763
4764 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4765 tx_urb = list_first_entry_or_null(&priv->tx_urb_free_list,
4766 struct rtl8xxxu_tx_urb, list);
4767 if (tx_urb) {
4768 list_del(&tx_urb->list);
4769 priv->tx_urb_free_count--;
4770 if (priv->tx_urb_free_count < RTL8XXXU_TX_URB_LOW_WATER &&
4771 !priv->tx_stopped) {
4772 priv->tx_stopped = true;
4773 ieee80211_stop_queues(priv->hw);
4774 }
4775 }
4776
4777 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4778
4779 return tx_urb;
4780}
4781
4782static void rtl8xxxu_free_tx_urb(struct rtl8xxxu_priv *priv,
4783 struct rtl8xxxu_tx_urb *tx_urb)
4784{
4785 unsigned long flags;
4786
4787 INIT_LIST_HEAD(&tx_urb->list);
4788
4789 spin_lock_irqsave(&priv->tx_urb_lock, flags);
4790
4791 list_add(&tx_urb->list, &priv->tx_urb_free_list);
4792 priv->tx_urb_free_count++;
4793 if (priv->tx_urb_free_count > RTL8XXXU_TX_URB_HIGH_WATER &&
4794 priv->tx_stopped) {
4795 priv->tx_stopped = false;
4796 ieee80211_wake_queues(priv->hw);
4797 }
4798
4799 spin_unlock_irqrestore(&priv->tx_urb_lock, flags);
4800}
4801
4802static void rtl8xxxu_tx_complete(struct urb *urb)
4803{
4804 struct sk_buff *skb = (struct sk_buff *)urb->context;
4805 struct ieee80211_tx_info *tx_info;
4806 struct ieee80211_hw *hw;
4807 struct rtl8xxxu_tx_urb *tx_urb =
4808 container_of(urb, struct rtl8xxxu_tx_urb, urb);
4809
4810 tx_info = IEEE80211_SKB_CB(skb);
4811 hw = tx_info->rate_driver_data[0];
4812
4813 skb_pull(skb, sizeof(struct rtl8xxxu_tx_desc));
4814
4815 ieee80211_tx_info_clear_status(tx_info);
4816 tx_info->status.rates[0].idx = -1;
4817 tx_info->status.rates[0].count = 0;
4818
4819 if (!urb->status)
4820 tx_info->flags |= IEEE80211_TX_STAT_ACK;
4821
4822 ieee80211_tx_status_irqsafe(hw, skb);
4823
4824 rtl8xxxu_free_tx_urb(hw->priv, tx_urb);
4825}
4826
4827static void rtl8xxxu_dump_action(struct device *dev,
4828 struct ieee80211_hdr *hdr)
4829{
4830 struct ieee80211_mgmt *mgmt = (struct ieee80211_mgmt *)hdr;
4831 u16 cap, timeout;
4832
4833 if (!(rtl8xxxu_debug & RTL8XXXU_DEBUG_ACTION))
4834 return;
4835
4836 switch (mgmt->u.action.u.addba_resp.action_code) {
4837 case WLAN_ACTION_ADDBA_RESP:
4838 cap = le16_to_cpu(mgmt->u.action.u.addba_resp.capab);
4839 timeout = le16_to_cpu(mgmt->u.action.u.addba_resp.timeout);
4840 dev_info(dev, "WLAN_ACTION_ADDBA_RESP: "
4841 "timeout %i, tid %02x, buf_size %02x, policy %02x, "
4842 "status %02x\n",
4843 timeout,
4844 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4845 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4846 (cap >> 1) & 0x1,
4847 le16_to_cpu(mgmt->u.action.u.addba_resp.status));
4848 break;
4849 case WLAN_ACTION_ADDBA_REQ:
4850 cap = le16_to_cpu(mgmt->u.action.u.addba_req.capab);
4851 timeout = le16_to_cpu(mgmt->u.action.u.addba_req.timeout);
4852 dev_info(dev, "WLAN_ACTION_ADDBA_REQ: "
4853 "timeout %i, tid %02x, buf_size %02x, policy %02x\n",
4854 timeout,
4855 (cap & IEEE80211_ADDBA_PARAM_TID_MASK) >> 2,
4856 (cap & IEEE80211_ADDBA_PARAM_BUF_SIZE_MASK) >> 6,
4857 (cap >> 1) & 0x1);
4858 break;
4859 default:
4860 dev_info(dev, "action frame %02x\n",
4861 mgmt->u.action.u.addba_resp.action_code);
4862 break;
4863 }
4864}
4865
4866static void rtl8xxxu_tx(struct ieee80211_hw *hw,
4867 struct ieee80211_tx_control *control,
4868 struct sk_buff *skb)
4869{
4870 struct ieee80211_hdr *hdr = (struct ieee80211_hdr *)skb->data;
4871 struct ieee80211_tx_info *tx_info = IEEE80211_SKB_CB(skb);
4872 struct ieee80211_rate *tx_rate = ieee80211_get_tx_rate(hw, tx_info);
4873 struct rtl8xxxu_priv *priv = hw->priv;
4874 struct rtl8xxxu_tx_desc *tx_desc;
4875 struct rtl8xxxu_tx_urb *tx_urb;
4876 struct ieee80211_sta *sta = NULL;
4877 struct ieee80211_vif *vif = tx_info->control.vif;
4878 struct device *dev = &priv->udev->dev;
4879 u32 queue, rate;
4880 u16 pktlen = skb->len;
4881 u16 seq_number;
4882 u16 rate_flag = tx_info->control.rates[0].flags;
4883 int ret;
4884
4885 if (skb_headroom(skb) < sizeof(struct rtl8xxxu_tx_desc)) {
4886 dev_warn(dev,
4887 "%s: Not enough headroom (%i) for tx descriptor\n",
4888 __func__, skb_headroom(skb));
4889 goto error;
4890 }
4891
4892 if (unlikely(skb->len > (65535 - sizeof(struct rtl8xxxu_tx_desc)))) {
4893 dev_warn(dev, "%s: Trying to send over-sized skb (%i)\n",
4894 __func__, skb->len);
4895 goto error;
4896 }
4897
4898 tx_urb = rtl8xxxu_alloc_tx_urb(priv);
4899 if (!tx_urb) {
4900 dev_warn(dev, "%s: Unable to allocate tx urb\n", __func__);
4901 goto error;
4902 }
4903
4904 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_TX)
4905 dev_info(dev, "%s: TX rate: %d (%d), pkt size %d\n",
4906 __func__, tx_rate->bitrate, tx_rate->hw_value, pktlen);
4907
4908 if (ieee80211_is_action(hdr->frame_control))
4909 rtl8xxxu_dump_action(dev, hdr);
4910
4911 tx_info->rate_driver_data[0] = hw;
4912
4913 if (control && control->sta)
4914 sta = control->sta;
4915
4916 tx_desc = (struct rtl8xxxu_tx_desc *)
4917 skb_push(skb, sizeof(struct rtl8xxxu_tx_desc));
4918
4919 memset(tx_desc, 0, sizeof(struct rtl8xxxu_tx_desc));
4920 tx_desc->pkt_size = cpu_to_le16(pktlen);
4921 tx_desc->pkt_offset = sizeof(struct rtl8xxxu_tx_desc);
4922
4923 tx_desc->txdw0 =
4924 TXDESC_OWN | TXDESC_FIRST_SEGMENT | TXDESC_LAST_SEGMENT;
4925 if (is_multicast_ether_addr(ieee80211_get_DA(hdr)) ||
4926 is_broadcast_ether_addr(ieee80211_get_DA(hdr)))
4927 tx_desc->txdw0 |= TXDESC_BROADMULTICAST;
4928
4929 queue = rtl8xxxu_queue_select(hw, skb);
4930 tx_desc->txdw1 = cpu_to_le32(queue << TXDESC_QUEUE_SHIFT);
4931
4932 if (tx_info->control.hw_key) {
4933 switch (tx_info->control.hw_key->cipher) {
4934 case WLAN_CIPHER_SUITE_WEP40:
4935 case WLAN_CIPHER_SUITE_WEP104:
4936 case WLAN_CIPHER_SUITE_TKIP:
4937 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_RC4);
4938 break;
4939 case WLAN_CIPHER_SUITE_CCMP:
4940 tx_desc->txdw1 |= cpu_to_le32(TXDESC_SEC_AES);
4941 break;
4942 default:
4943 break;
4944 }
4945 }
4946
4947 seq_number = IEEE80211_SEQ_TO_SN(le16_to_cpu(hdr->seq_ctrl));
4948 tx_desc->txdw3 = cpu_to_le32((u32)seq_number << TXDESC_SEQ_SHIFT);
4949
4950 if (rate_flag & IEEE80211_TX_RC_MCS)
4951 rate = tx_info->control.rates[0].idx + DESC_RATE_MCS0;
4952 else
4953 rate = tx_rate->hw_value;
4954 tx_desc->txdw5 = cpu_to_le32(rate);
4955
4956 if (ieee80211_is_data(hdr->frame_control))
4957 tx_desc->txdw5 |= cpu_to_le32(0x0001ff00);
4958
4959 /* (tx_info->flags & IEEE80211_TX_CTL_AMPDU) && */
4960 if (ieee80211_is_data_qos(hdr->frame_control) && sta) {
4961 if (sta->ht_cap.ht_supported) {
4962 u32 ampdu, val32;
4963
4964 ampdu = (u32)sta->ht_cap.ampdu_density;
4965 val32 = ampdu << TXDESC_AMPDU_DENSITY_SHIFT;
4966 tx_desc->txdw2 |= cpu_to_le32(val32);
4967 tx_desc->txdw1 |= cpu_to_le32(TXDESC_AGG_ENABLE);
4968 } else
4969 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4970 } else
4971 tx_desc->txdw1 |= cpu_to_le32(TXDESC_BK);
4972
4973 if (ieee80211_is_data_qos(hdr->frame_control))
4974 tx_desc->txdw4 |= cpu_to_le32(TXDESC_QOS);
4975 if (rate_flag & IEEE80211_TX_RC_USE_SHORT_PREAMBLE ||
4976 (sta && vif && vif->bss_conf.use_short_preamble))
4977 tx_desc->txdw4 |= cpu_to_le32(TXDESC_SHORT_PREAMBLE);
4978 if (rate_flag & IEEE80211_TX_RC_SHORT_GI ||
4979 (ieee80211_is_data_qos(hdr->frame_control) &&
4980 sta && sta->ht_cap.cap &
4981 (IEEE80211_HT_CAP_SGI_40 | IEEE80211_HT_CAP_SGI_20))) {
4982 tx_desc->txdw5 |= cpu_to_le32(TXDESC_SHORT_GI);
4983 }
4984 if (ieee80211_is_mgmt(hdr->frame_control)) {
4985 tx_desc->txdw5 = cpu_to_le32(tx_rate->hw_value);
4986 tx_desc->txdw4 |= cpu_to_le32(TXDESC_USE_DRIVER_RATE);
4987 tx_desc->txdw5 |= cpu_to_le32(6 << TXDESC_RETRY_LIMIT_SHIFT);
4988 tx_desc->txdw5 |= cpu_to_le32(TXDESC_RETRY_LIMIT_ENABLE);
4989 }
4990
4991 if (rate_flag & IEEE80211_TX_RC_USE_RTS_CTS) {
4992 /* Use RTS rate 24M - does the mac80211 tell us which to use? */
4993 tx_desc->txdw4 |= cpu_to_le32(DESC_RATE_24M);
4994 tx_desc->txdw4 |= cpu_to_le32(TXDESC_RTS_CTS_ENABLE);
4995 tx_desc->txdw4 |= cpu_to_le32(TXDESC_HW_RTS_ENABLE);
4996 }
4997
4998 rtl8xxxu_calc_tx_desc_csum(tx_desc);
4999
5000 usb_fill_bulk_urb(&tx_urb->urb, priv->udev, priv->pipe_out[queue],
5001 skb->data, skb->len, rtl8xxxu_tx_complete, skb);
5002
5003 usb_anchor_urb(&tx_urb->urb, &priv->tx_anchor);
5004 ret = usb_submit_urb(&tx_urb->urb, GFP_ATOMIC);
5005 if (ret) {
5006 usb_unanchor_urb(&tx_urb->urb);
5007 rtl8xxxu_free_tx_urb(priv, tx_urb);
5008 goto error;
5009 }
5010 return;
5011error:
5012 dev_kfree_skb(skb);
5013}
5014
5015static void rtl8xxxu_rx_parse_phystats(struct rtl8xxxu_priv *priv,
5016 struct ieee80211_rx_status *rx_status,
5017 struct rtl8xxxu_rx_desc *rx_desc,
5018 struct rtl8723au_phy_stats *phy_stats)
5019{
5020 if (phy_stats->sgi_en)
5021 rx_status->flag |= RX_FLAG_SHORT_GI;
5022
5023 if (rx_desc->rxmcs < DESC_RATE_6M) {
5024 /*
5025 * Handle PHY stats for CCK rates
5026 */
5027 u8 cck_agc_rpt = phy_stats->cck_agc_rpt_ofdm_cfosho_a;
5028
5029 switch (cck_agc_rpt & 0xc0) {
5030 case 0xc0:
5031 rx_status->signal = -46 - (cck_agc_rpt & 0x3e);
5032 break;
5033 case 0x80:
5034 rx_status->signal = -26 - (cck_agc_rpt & 0x3e);
5035 break;
5036 case 0x40:
5037 rx_status->signal = -12 - (cck_agc_rpt & 0x3e);
5038 break;
5039 case 0x00:
5040 rx_status->signal = 16 - (cck_agc_rpt & 0x3e);
5041 break;
5042 }
5043 } else {
5044 rx_status->signal =
5045 (phy_stats->cck_sig_qual_ofdm_pwdb_all >> 1) - 110;
5046 }
5047}
5048
5049static void rtl8xxxu_free_rx_resources(struct rtl8xxxu_priv *priv)
5050{
5051 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5052 unsigned long flags;
5053
5054 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5055
5056 list_for_each_entry_safe(rx_urb, tmp,
5057 &priv->rx_urb_pending_list, list) {
5058 list_del(&rx_urb->list);
5059 priv->rx_urb_pending_count--;
5060 usb_free_urb(&rx_urb->urb);
5061 }
5062
5063 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5064}
5065
5066static void rtl8xxxu_queue_rx_urb(struct rtl8xxxu_priv *priv,
5067 struct rtl8xxxu_rx_urb *rx_urb)
5068{
5069 struct sk_buff *skb;
5070 unsigned long flags;
5071 int pending = 0;
5072
5073 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5074
5075 if (!priv->shutdown) {
5076 list_add_tail(&rx_urb->list, &priv->rx_urb_pending_list);
5077 priv->rx_urb_pending_count++;
5078 pending = priv->rx_urb_pending_count;
5079 } else {
5080 skb = (struct sk_buff *)rx_urb->urb.context;
5081 dev_kfree_skb(skb);
5082 usb_free_urb(&rx_urb->urb);
5083 }
5084
5085 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5086
5087 if (pending > RTL8XXXU_RX_URB_PENDING_WATER)
5088 schedule_work(&priv->rx_urb_wq);
5089}
5090
5091static void rtl8xxxu_rx_urb_work(struct work_struct *work)
5092{
5093 struct rtl8xxxu_priv *priv;
5094 struct rtl8xxxu_rx_urb *rx_urb, *tmp;
5095 struct list_head local;
5096 struct sk_buff *skb;
5097 unsigned long flags;
5098 int ret;
5099
5100 priv = container_of(work, struct rtl8xxxu_priv, rx_urb_wq);
5101 INIT_LIST_HEAD(&local);
5102
5103 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5104
5105 list_splice_init(&priv->rx_urb_pending_list, &local);
5106 priv->rx_urb_pending_count = 0;
5107
5108 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5109
5110 list_for_each_entry_safe(rx_urb, tmp, &local, list) {
5111 list_del_init(&rx_urb->list);
5112 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5113 /*
5114 * If out of memory or temporary error, put it back on the
5115 * queue and try again. Otherwise the device is dead/gone
5116 * and we should drop it.
5117 */
5118 switch (ret) {
5119 case 0:
5120 break;
5121 case -ENOMEM:
5122 case -EAGAIN:
5123 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5124 break;
5125 default:
5126 pr_info("failed to requeue urb %i\n", ret);
5127 skb = (struct sk_buff *)rx_urb->urb.context;
5128 dev_kfree_skb(skb);
5129 usb_free_urb(&rx_urb->urb);
5130 }
5131 }
5132}
5133
5134static void rtl8xxxu_rx_complete(struct urb *urb)
5135{
5136 struct rtl8xxxu_rx_urb *rx_urb =
5137 container_of(urb, struct rtl8xxxu_rx_urb, urb);
5138 struct ieee80211_hw *hw = rx_urb->hw;
5139 struct rtl8xxxu_priv *priv = hw->priv;
5140 struct sk_buff *skb = (struct sk_buff *)urb->context;
5141 struct rtl8xxxu_rx_desc *rx_desc = (struct rtl8xxxu_rx_desc *)skb->data;
5142 struct rtl8723au_phy_stats *phy_stats;
5143 struct ieee80211_rx_status *rx_status = IEEE80211_SKB_RXCB(skb);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5144 struct device *dev = &priv->udev->dev;
5145 __le32 *_rx_desc_le = (__le32 *)skb->data;
5146 u32 *_rx_desc = (u32 *)skb->data;
Jes Sorensena9ffa612016-02-03 13:39:59 -0500[diff] [blame]5147 int drvinfo_sz, desc_shift, i;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5148
5149 for (i = 0; i < (sizeof(struct rtl8xxxu_rx_desc) / sizeof(u32)); i++)
5150 _rx_desc[i] = le32_to_cpu(_rx_desc_le[i]);
5151
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5152 drvinfo_sz = rx_desc->drvinfo_sz * 8;
5153 desc_shift = rx_desc->shift;
5154 skb_put(skb, urb->actual_length);
5155
5156 if (urb->status == 0) {
5157 skb_pull(skb, sizeof(struct rtl8xxxu_rx_desc));
5158 phy_stats = (struct rtl8723au_phy_stats *)skb->data;
5159
5160 skb_pull(skb, drvinfo_sz + desc_shift);
5161
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5162 memset(rx_status, 0, sizeof(struct ieee80211_rx_status));
5163
5164 if (rx_desc->phy_stats)
5165 rtl8xxxu_rx_parse_phystats(priv, rx_status,
5166 rx_desc, phy_stats);
5167
5168 rx_status->freq = hw->conf.chandef.chan->center_freq;
5169 rx_status->band = hw->conf.chandef.chan->band;
5170
5171 rx_status->mactime = le32_to_cpu(rx_desc->tsfl);
5172 rx_status->flag |= RX_FLAG_MACTIME_START;
5173
5174 if (!rx_desc->swdec)
5175 rx_status->flag |= RX_FLAG_DECRYPTED;
5176 if (rx_desc->crc32)
5177 rx_status->flag |= RX_FLAG_FAILED_FCS_CRC;
5178 if (rx_desc->bw)
5179 rx_status->flag |= RX_FLAG_40MHZ;
5180
5181 if (rx_desc->rxht) {
5182 rx_status->flag |= RX_FLAG_HT;
5183 rx_status->rate_idx = rx_desc->rxmcs - DESC_RATE_MCS0;
5184 } else {
5185 rx_status->rate_idx = rx_desc->rxmcs;
5186 }
5187
5188 ieee80211_rx_irqsafe(hw, skb);
5189 skb = NULL;
5190 rx_urb->urb.context = NULL;
5191 rtl8xxxu_queue_rx_urb(priv, rx_urb);
5192 } else {
5193 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5194 goto cleanup;
5195 }
5196 return;
5197
5198cleanup:
5199 usb_free_urb(urb);
5200 dev_kfree_skb(skb);
5201 return;
5202}
5203
5204static int rtl8xxxu_submit_rx_urb(struct rtl8xxxu_priv *priv,
5205 struct rtl8xxxu_rx_urb *rx_urb)
5206{
5207 struct sk_buff *skb;
5208 int skb_size;
5209 int ret;
5210
5211 skb_size = sizeof(struct rtl8xxxu_rx_desc) + RTL_RX_BUFFER_SIZE;
5212 skb = __netdev_alloc_skb(NULL, skb_size, GFP_KERNEL);
5213 if (!skb)
5214 return -ENOMEM;
5215
5216 memset(skb->data, 0, sizeof(struct rtl8xxxu_rx_desc));
5217 usb_fill_bulk_urb(&rx_urb->urb, priv->udev, priv->pipe_in, skb->data,
5218 skb_size, rtl8xxxu_rx_complete, skb);
5219 usb_anchor_urb(&rx_urb->urb, &priv->rx_anchor);
5220 ret = usb_submit_urb(&rx_urb->urb, GFP_ATOMIC);
5221 if (ret)
5222 usb_unanchor_urb(&rx_urb->urb);
5223 return ret;
5224}
5225
5226static void rtl8xxxu_int_complete(struct urb *urb)
5227{
5228 struct rtl8xxxu_priv *priv = (struct rtl8xxxu_priv *)urb->context;
5229 struct device *dev = &priv->udev->dev;
5230 int ret;
5231
5232 dev_dbg(dev, "%s: status %i\n", __func__, urb->status);
5233 if (urb->status == 0) {
5234 usb_anchor_urb(urb, &priv->int_anchor);
5235 ret = usb_submit_urb(urb, GFP_ATOMIC);
5236 if (ret)
5237 usb_unanchor_urb(urb);
5238 } else {
5239 dev_info(dev, "%s: Error %i\n", __func__, urb->status);
5240 }
5241}
5242
5243
5244static int rtl8xxxu_submit_int_urb(struct ieee80211_hw *hw)
5245{
5246 struct rtl8xxxu_priv *priv = hw->priv;
5247 struct urb *urb;
5248 u32 val32;
5249 int ret;
5250
5251 urb = usb_alloc_urb(0, GFP_KERNEL);
5252 if (!urb)
5253 return -ENOMEM;
5254
5255 usb_fill_int_urb(urb, priv->udev, priv->pipe_interrupt,
5256 priv->int_buf, USB_INTR_CONTENT_LENGTH,
5257 rtl8xxxu_int_complete, priv, 1);
5258 usb_anchor_urb(urb, &priv->int_anchor);
5259 ret = usb_submit_urb(urb, GFP_KERNEL);
5260 if (ret) {
5261 usb_unanchor_urb(urb);
5262 goto error;
5263 }
5264
5265 val32 = rtl8xxxu_read32(priv, REG_USB_HIMR);
5266 val32 |= USB_HIMR_CPWM;
5267 rtl8xxxu_write32(priv, REG_USB_HIMR, val32);
5268
5269error:
5270 return ret;
5271}
5272
5273static int rtl8xxxu_add_interface(struct ieee80211_hw *hw,
5274 struct ieee80211_vif *vif)
5275{
5276 struct rtl8xxxu_priv *priv = hw->priv;
5277 int ret;
5278 u8 val8;
5279
5280 switch (vif->type) {
5281 case NL80211_IFTYPE_STATION:
5282 rtl8723a_stop_tx_beacon(priv);
5283
5284 val8 = rtl8xxxu_read8(priv, REG_BEACON_CTRL);
5285 val8 |= BEACON_ATIM | BEACON_FUNCTION_ENABLE |
5286 BEACON_DISABLE_TSF_UPDATE;
5287 rtl8xxxu_write8(priv, REG_BEACON_CTRL, val8);
5288 ret = 0;
5289 break;
5290 default:
5291 ret = -EOPNOTSUPP;
5292 }
5293
5294 rtl8xxxu_set_linktype(priv, vif->type);
5295
5296 return ret;
5297}
5298
5299static void rtl8xxxu_remove_interface(struct ieee80211_hw *hw,
5300 struct ieee80211_vif *vif)
5301{
5302 struct rtl8xxxu_priv *priv = hw->priv;
5303
5304 dev_dbg(&priv->udev->dev, "%s\n", __func__);
5305}
5306
5307static int rtl8xxxu_config(struct ieee80211_hw *hw, u32 changed)
5308{
5309 struct rtl8xxxu_priv *priv = hw->priv;
5310 struct device *dev = &priv->udev->dev;
5311 u16 val16;
5312 int ret = 0, channel;
5313 bool ht40;
5314
5315 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_CHANNEL)
5316 dev_info(dev,
5317 "%s: channel: %i (changed %08x chandef.width %02x)\n",
5318 __func__, hw->conf.chandef.chan->hw_value,
5319 changed, hw->conf.chandef.width);
5320
5321 if (changed & IEEE80211_CONF_CHANGE_RETRY_LIMITS) {
5322 val16 = ((hw->conf.long_frame_max_tx_count <<
5323 RETRY_LIMIT_LONG_SHIFT) & RETRY_LIMIT_LONG_MASK) |
5324 ((hw->conf.short_frame_max_tx_count <<
5325 RETRY_LIMIT_SHORT_SHIFT) & RETRY_LIMIT_SHORT_MASK);
5326 rtl8xxxu_write16(priv, REG_RETRY_LIMIT, val16);
5327 }
5328
5329 if (changed & IEEE80211_CONF_CHANGE_CHANNEL) {
5330 switch (hw->conf.chandef.width) {
5331 case NL80211_CHAN_WIDTH_20_NOHT:
5332 case NL80211_CHAN_WIDTH_20:
5333 ht40 = false;
5334 break;
5335 case NL80211_CHAN_WIDTH_40:
5336 ht40 = true;
5337 break;
5338 default:
5339 ret = -ENOTSUPP;
5340 goto exit;
5341 }
5342
5343 channel = hw->conf.chandef.chan->hw_value;
5344
5345 rtl8723a_set_tx_power(priv, channel, ht40);
5346
5347 rtl8723au_config_channel(hw);
5348 }
5349
5350exit:
5351 return ret;
5352}
5353
5354static int rtl8xxxu_conf_tx(struct ieee80211_hw *hw,
5355 struct ieee80211_vif *vif, u16 queue,
5356 const struct ieee80211_tx_queue_params *param)
5357{
5358 struct rtl8xxxu_priv *priv = hw->priv;
5359 struct device *dev = &priv->udev->dev;
5360 u32 val32;
5361 u8 aifs, acm_ctrl, acm_bit;
5362
5363 aifs = param->aifs;
5364
5365 val32 = aifs |
5366 fls(param->cw_min) << EDCA_PARAM_ECW_MIN_SHIFT |
5367 fls(param->cw_max) << EDCA_PARAM_ECW_MAX_SHIFT |
5368 (u32)param->txop << EDCA_PARAM_TXOP_SHIFT;
5369
5370 acm_ctrl = rtl8xxxu_read8(priv, REG_ACM_HW_CTRL);
5371 dev_dbg(dev,
5372 "%s: IEEE80211 queue %02x val %08x, acm %i, acm_ctrl %02x\n",
5373 __func__, queue, val32, param->acm, acm_ctrl);
5374
5375 switch (queue) {
5376 case IEEE80211_AC_VO:
5377 acm_bit = ACM_HW_CTRL_VO;
5378 rtl8xxxu_write32(priv, REG_EDCA_VO_PARAM, val32);
5379 break;
5380 case IEEE80211_AC_VI:
5381 acm_bit = ACM_HW_CTRL_VI;
5382 rtl8xxxu_write32(priv, REG_EDCA_VI_PARAM, val32);
5383 break;
5384 case IEEE80211_AC_BE:
5385 acm_bit = ACM_HW_CTRL_BE;
5386 rtl8xxxu_write32(priv, REG_EDCA_BE_PARAM, val32);
5387 break;
5388 case IEEE80211_AC_BK:
5389 acm_bit = ACM_HW_CTRL_BK;
5390 rtl8xxxu_write32(priv, REG_EDCA_BK_PARAM, val32);
5391 break;
5392 default:
5393 acm_bit = 0;
5394 break;
5395 }
5396
5397 if (param->acm)
5398 acm_ctrl |= acm_bit;
5399 else
5400 acm_ctrl &= ~acm_bit;
5401 rtl8xxxu_write8(priv, REG_ACM_HW_CTRL, acm_ctrl);
5402
5403 return 0;
5404}
5405
5406static void rtl8xxxu_configure_filter(struct ieee80211_hw *hw,
5407 unsigned int changed_flags,
5408 unsigned int *total_flags, u64 multicast)
5409{
5410 struct rtl8xxxu_priv *priv = hw->priv;
Bruno Randolf3bed4bf2016-02-03 13:39:51 -0500[diff] [blame]5411 u32 rcr = rtl8xxxu_read32(priv, REG_RCR);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5412
5413 dev_dbg(&priv->udev->dev, "%s: changed_flags %08x, total_flags %08x\n",
5414 __func__, changed_flags, *total_flags);
5415
Bruno Randolf3bed4bf2016-02-03 13:39:51 -0500[diff] [blame]5416 /*
5417 * FIF_ALLMULTI ignored as all multicast frames are accepted (REG_MAR)
5418 */
5419
5420 if (*total_flags & FIF_FCSFAIL)
5421 rcr |= RCR_ACCEPT_CRC32;
5422 else
5423 rcr &= ~RCR_ACCEPT_CRC32;
5424
5425 /*
5426 * FIF_PLCPFAIL not supported?
5427 */
5428
5429 if (*total_flags & FIF_BCN_PRBRESP_PROMISC)
5430 rcr &= ~RCR_CHECK_BSSID_BEACON;
5431 else
5432 rcr |= RCR_CHECK_BSSID_BEACON;
5433
5434 if (*total_flags & FIF_CONTROL)
5435 rcr |= RCR_ACCEPT_CTRL_FRAME;
5436 else
5437 rcr &= ~RCR_ACCEPT_CTRL_FRAME;
5438
5439 if (*total_flags & FIF_OTHER_BSS) {
5440 rcr |= RCR_ACCEPT_AP;
5441 rcr &= ~RCR_CHECK_BSSID_MATCH;
5442 } else {
5443 rcr &= ~RCR_ACCEPT_AP;
5444 rcr |= RCR_CHECK_BSSID_MATCH;
5445 }
5446
5447 if (*total_flags & FIF_PSPOLL)
5448 rcr |= RCR_ACCEPT_PM;
5449 else
5450 rcr &= ~RCR_ACCEPT_PM;
5451
5452 /*
5453 * FIF_PROBE_REQ ignored as probe requests always seem to be accepted
5454 */
5455
5456 rtl8xxxu_write32(priv, REG_RCR, rcr);
5457
Jes Sorensen755bda12016-02-03 13:39:54 -0500[diff] [blame]5458 *total_flags &= (FIF_ALLMULTI | FIF_FCSFAIL | FIF_BCN_PRBRESP_PROMISC |
5459 FIF_CONTROL | FIF_OTHER_BSS | FIF_PSPOLL |
5460 FIF_PROBE_REQ);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5461}
5462
5463static int rtl8xxxu_set_rts_threshold(struct ieee80211_hw *hw, u32 rts)
5464{
5465 if (rts > 2347)
5466 return -EINVAL;
5467
5468 return 0;
5469}
5470
5471static int rtl8xxxu_set_key(struct ieee80211_hw *hw, enum set_key_cmd cmd,
5472 struct ieee80211_vif *vif,
5473 struct ieee80211_sta *sta,
5474 struct ieee80211_key_conf *key)
5475{
5476 struct rtl8xxxu_priv *priv = hw->priv;
5477 struct device *dev = &priv->udev->dev;
5478 u8 mac_addr[ETH_ALEN];
5479 u8 val8;
5480 u16 val16;
5481 u32 val32;
5482 int retval = -EOPNOTSUPP;
5483
5484 dev_dbg(dev, "%s: cmd %02x, cipher %08x, index %i\n",
5485 __func__, cmd, key->cipher, key->keyidx);
5486
5487 if (vif->type != NL80211_IFTYPE_STATION)
5488 return -EOPNOTSUPP;
5489
5490 if (key->keyidx > 3)
5491 return -EOPNOTSUPP;
5492
5493 switch (key->cipher) {
5494 case WLAN_CIPHER_SUITE_WEP40:
5495 case WLAN_CIPHER_SUITE_WEP104:
5496
5497 break;
5498 case WLAN_CIPHER_SUITE_CCMP:
5499 key->flags |= IEEE80211_KEY_FLAG_SW_MGMT_TX;
5500 break;
5501 case WLAN_CIPHER_SUITE_TKIP:
5502 key->flags |= IEEE80211_KEY_FLAG_GENERATE_MMIC;
5503 default:
5504 return -EOPNOTSUPP;
5505 }
5506
5507 if (key->flags & IEEE80211_KEY_FLAG_PAIRWISE) {
5508 dev_dbg(dev, "%s: pairwise key\n", __func__);
5509 ether_addr_copy(mac_addr, sta->addr);
5510 } else {
5511 dev_dbg(dev, "%s: group key\n", __func__);
5512 eth_broadcast_addr(mac_addr);
5513 }
5514
5515 val16 = rtl8xxxu_read16(priv, REG_CR);
5516 val16 |= CR_SECURITY_ENABLE;
5517 rtl8xxxu_write16(priv, REG_CR, val16);
5518
5519 val8 = SEC_CFG_TX_SEC_ENABLE | SEC_CFG_TXBC_USE_DEFKEY |
5520 SEC_CFG_RX_SEC_ENABLE | SEC_CFG_RXBC_USE_DEFKEY;
5521 val8 |= SEC_CFG_TX_USE_DEFKEY | SEC_CFG_RX_USE_DEFKEY;
5522 rtl8xxxu_write8(priv, REG_SECURITY_CFG, val8);
5523
5524 switch (cmd) {
5525 case SET_KEY:
5526 key->hw_key_idx = key->keyidx;
5527 key->flags |= IEEE80211_KEY_FLAG_GENERATE_IV;
5528 rtl8xxxu_cam_write(priv, key, mac_addr);
5529 retval = 0;
5530 break;
5531 case DISABLE_KEY:
5532 rtl8xxxu_write32(priv, REG_CAM_WRITE, 0x00000000);
5533 val32 = CAM_CMD_POLLING | CAM_CMD_WRITE |
5534 key->keyidx << CAM_CMD_KEY_SHIFT;
5535 rtl8xxxu_write32(priv, REG_CAM_CMD, val32);
5536 retval = 0;
5537 break;
5538 default:
5539 dev_warn(dev, "%s: Unsupported command %02x\n", __func__, cmd);
5540 }
5541
5542 return retval;
5543}
5544
5545static int
5546rtl8xxxu_ampdu_action(struct ieee80211_hw *hw, struct ieee80211_vif *vif,
Sara Sharon50ea05e2015-12-30 16:06:04 +0200[diff] [blame]5547 struct ieee80211_ampdu_params *params)
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5548{
5549 struct rtl8xxxu_priv *priv = hw->priv;
5550 struct device *dev = &priv->udev->dev;
5551 u8 ampdu_factor, ampdu_density;
Sara Sharon50ea05e2015-12-30 16:06:04 +0200[diff] [blame]5552 struct ieee80211_sta *sta = params->sta;
5553 enum ieee80211_ampdu_mlme_action action = params->action;
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5554
5555 switch (action) {
5556 case IEEE80211_AMPDU_TX_START:
5557 dev_info(dev, "%s: IEEE80211_AMPDU_TX_START\n", __func__);
5558 ampdu_factor = sta->ht_cap.ampdu_factor;
5559 ampdu_density = sta->ht_cap.ampdu_density;
5560 rtl8xxxu_set_ampdu_factor(priv, ampdu_factor);
5561 rtl8xxxu_set_ampdu_min_space(priv, ampdu_density);
5562 dev_dbg(dev,
5563 "Changed HT: ampdu_factor %02x, ampdu_density %02x\n",
5564 ampdu_factor, ampdu_density);
5565 break;
5566 case IEEE80211_AMPDU_TX_STOP_FLUSH:
5567 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH\n", __func__);
5568 rtl8xxxu_set_ampdu_factor(priv, 0);
5569 rtl8xxxu_set_ampdu_min_space(priv, 0);
5570 break;
5571 case IEEE80211_AMPDU_TX_STOP_FLUSH_CONT:
5572 dev_info(dev, "%s: IEEE80211_AMPDU_TX_STOP_FLUSH_CONT\n",
5573 __func__);
5574 rtl8xxxu_set_ampdu_factor(priv, 0);
5575 rtl8xxxu_set_ampdu_min_space(priv, 0);
5576 break;
5577 case IEEE80211_AMPDU_RX_START:
5578 dev_info(dev, "%s: IEEE80211_AMPDU_RX_START\n", __func__);
5579 break;
5580 case IEEE80211_AMPDU_RX_STOP:
5581 dev_info(dev, "%s: IEEE80211_AMPDU_RX_STOP\n", __func__);
5582 break;
5583 default:
5584 break;
5585 }
5586 return 0;
5587}
5588
5589static int rtl8xxxu_start(struct ieee80211_hw *hw)
5590{
5591 struct rtl8xxxu_priv *priv = hw->priv;
5592 struct rtl8xxxu_rx_urb *rx_urb;
5593 struct rtl8xxxu_tx_urb *tx_urb;
5594 unsigned long flags;
5595 int ret, i;
5596
5597 ret = 0;
5598
5599 init_usb_anchor(&priv->rx_anchor);
5600 init_usb_anchor(&priv->tx_anchor);
5601 init_usb_anchor(&priv->int_anchor);
5602
5603 rtl8723a_enable_rf(priv);
5604 ret = rtl8xxxu_submit_int_urb(hw);
5605 if (ret)
5606 goto exit;
5607
5608 for (i = 0; i < RTL8XXXU_TX_URBS; i++) {
5609 tx_urb = kmalloc(sizeof(struct rtl8xxxu_tx_urb), GFP_KERNEL);
5610 if (!tx_urb) {
5611 if (!i)
5612 ret = -ENOMEM;
5613
5614 goto error_out;
5615 }
5616 usb_init_urb(&tx_urb->urb);
5617 INIT_LIST_HEAD(&tx_urb->list);
5618 tx_urb->hw = hw;
5619 list_add(&tx_urb->list, &priv->tx_urb_free_list);
5620 priv->tx_urb_free_count++;
5621 }
5622
5623 priv->tx_stopped = false;
5624
5625 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5626 priv->shutdown = false;
5627 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5628
5629 for (i = 0; i < RTL8XXXU_RX_URBS; i++) {
5630 rx_urb = kmalloc(sizeof(struct rtl8xxxu_rx_urb), GFP_KERNEL);
5631 if (!rx_urb) {
5632 if (!i)
5633 ret = -ENOMEM;
5634
5635 goto error_out;
5636 }
5637 usb_init_urb(&rx_urb->urb);
5638 INIT_LIST_HEAD(&rx_urb->list);
5639 rx_urb->hw = hw;
5640
5641 ret = rtl8xxxu_submit_rx_urb(priv, rx_urb);
5642 }
5643exit:
5644 /*
Bruno Randolfc85ea112016-02-03 13:39:55 -0500[diff] [blame]5645 * Accept all data and mgmt frames
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5646 */
Bruno Randolfc85ea112016-02-03 13:39:55 -0500[diff] [blame]5647 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0xffff);
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5648 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0xffff);
5649
5650 rtl8xxxu_write32(priv, REG_OFDM0_XA_AGC_CORE1, 0x6954341e);
5651
5652 return ret;
5653
5654error_out:
5655 rtl8xxxu_free_tx_resources(priv);
5656 /*
5657 * Disable all data and mgmt frames
5658 */
5659 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5660 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5661
5662 return ret;
5663}
5664
5665static void rtl8xxxu_stop(struct ieee80211_hw *hw)
5666{
5667 struct rtl8xxxu_priv *priv = hw->priv;
5668 unsigned long flags;
5669
5670 rtl8xxxu_write8(priv, REG_TXPAUSE, 0xff);
5671
5672 rtl8xxxu_write16(priv, REG_RXFLTMAP0, 0x0000);
5673 rtl8xxxu_write16(priv, REG_RXFLTMAP2, 0x0000);
5674
5675 spin_lock_irqsave(&priv->rx_urb_lock, flags);
5676 priv->shutdown = true;
5677 spin_unlock_irqrestore(&priv->rx_urb_lock, flags);
5678
5679 usb_kill_anchored_urbs(&priv->rx_anchor);
5680 usb_kill_anchored_urbs(&priv->tx_anchor);
5681 usb_kill_anchored_urbs(&priv->int_anchor);
5682
5683 rtl8723a_disable_rf(priv);
5684
5685 /*
5686 * Disable interrupts
5687 */
5688 rtl8xxxu_write32(priv, REG_USB_HIMR, 0);
5689
5690 rtl8xxxu_free_rx_resources(priv);
5691 rtl8xxxu_free_tx_resources(priv);
5692}
5693
5694static const struct ieee80211_ops rtl8xxxu_ops = {
5695 .tx = rtl8xxxu_tx,
5696 .add_interface = rtl8xxxu_add_interface,
5697 .remove_interface = rtl8xxxu_remove_interface,
5698 .config = rtl8xxxu_config,
5699 .conf_tx = rtl8xxxu_conf_tx,
5700 .bss_info_changed = rtl8xxxu_bss_info_changed,
5701 .configure_filter = rtl8xxxu_configure_filter,
5702 .set_rts_threshold = rtl8xxxu_set_rts_threshold,
5703 .start = rtl8xxxu_start,
5704 .stop = rtl8xxxu_stop,
5705 .sw_scan_start = rtl8xxxu_sw_scan_start,
5706 .sw_scan_complete = rtl8xxxu_sw_scan_complete,
5707 .set_key = rtl8xxxu_set_key,
5708 .ampdu_action = rtl8xxxu_ampdu_action,
5709};
5710
5711static int rtl8xxxu_parse_usb(struct rtl8xxxu_priv *priv,
5712 struct usb_interface *interface)
5713{
5714 struct usb_interface_descriptor *interface_desc;
5715 struct usb_host_interface *host_interface;
5716 struct usb_endpoint_descriptor *endpoint;
5717 struct device *dev = &priv->udev->dev;
5718 int i, j = 0, endpoints;
5719 u8 dir, xtype, num;
5720 int ret = 0;
5721
5722 host_interface = &interface->altsetting[0];
5723 interface_desc = &host_interface->desc;
5724 endpoints = interface_desc->bNumEndpoints;
5725
5726 for (i = 0; i < endpoints; i++) {
5727 endpoint = &host_interface->endpoint[i].desc;
5728
5729 dir = endpoint->bEndpointAddress & USB_ENDPOINT_DIR_MASK;
5730 num = usb_endpoint_num(endpoint);
5731 xtype = usb_endpoint_type(endpoint);
5732 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5733 dev_dbg(dev,
5734 "%s: endpoint: dir %02x, # %02x, type %02x\n",
5735 __func__, dir, num, xtype);
5736 if (usb_endpoint_dir_in(endpoint) &&
5737 usb_endpoint_xfer_bulk(endpoint)) {
5738 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5739 dev_dbg(dev, "%s: in endpoint num %i\n",
5740 __func__, num);
5741
5742 if (priv->pipe_in) {
5743 dev_warn(dev,
5744 "%s: Too many IN pipes\n", __func__);
5745 ret = -EINVAL;
5746 goto exit;
5747 }
5748
5749 priv->pipe_in = usb_rcvbulkpipe(priv->udev, num);
5750 }
5751
5752 if (usb_endpoint_dir_in(endpoint) &&
5753 usb_endpoint_xfer_int(endpoint)) {
5754 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5755 dev_dbg(dev, "%s: interrupt endpoint num %i\n",
5756 __func__, num);
5757
5758 if (priv->pipe_interrupt) {
5759 dev_warn(dev, "%s: Too many INTERRUPT pipes\n",
5760 __func__);
5761 ret = -EINVAL;
5762 goto exit;
5763 }
5764
5765 priv->pipe_interrupt = usb_rcvintpipe(priv->udev, num);
5766 }
5767
5768 if (usb_endpoint_dir_out(endpoint) &&
5769 usb_endpoint_xfer_bulk(endpoint)) {
5770 if (rtl8xxxu_debug & RTL8XXXU_DEBUG_USB)
5771 dev_dbg(dev, "%s: out endpoint num %i\n",
5772 __func__, num);
5773 if (j >= RTL8XXXU_OUT_ENDPOINTS) {
5774 dev_warn(dev,
5775 "%s: Too many OUT pipes\n", __func__);
5776 ret = -EINVAL;
5777 goto exit;
5778 }
5779 priv->out_ep[j++] = num;
5780 }
5781 }
5782exit:
5783 priv->nr_out_eps = j;
5784 return ret;
5785}
5786
5787static int rtl8xxxu_probe(struct usb_interface *interface,
5788 const struct usb_device_id *id)
5789{
5790 struct rtl8xxxu_priv *priv;
5791 struct ieee80211_hw *hw;
5792 struct usb_device *udev;
5793 struct ieee80211_supported_band *sband;
5794 int ret = 0;
5795 int untested = 1;
5796
5797 udev = usb_get_dev(interface_to_usbdev(interface));
5798
5799 switch (id->idVendor) {
5800 case USB_VENDOR_ID_REALTEK:
5801 switch(id->idProduct) {
5802 case 0x1724:
5803 case 0x8176:
5804 case 0x8178:
5805 case 0x817f:
5806 untested = 0;
5807 break;
5808 }
5809 break;
5810 case 0x7392:
5811 if (id->idProduct == 0x7811)
5812 untested = 0;
5813 break;
5814 default:
5815 break;
5816 }
5817
5818 if (untested) {
5819 rtl8xxxu_debug = RTL8XXXU_DEBUG_EFUSE;
5820 dev_info(&udev->dev,
5821 "This Realtek USB WiFi dongle (0x%04x:0x%04x) is untested!\n",
5822 id->idVendor, id->idProduct);
5823 dev_info(&udev->dev,
5824 "Please report results to Jes.Sorensen@gmail.com\n");
5825 }
5826
5827 hw = ieee80211_alloc_hw(sizeof(struct rtl8xxxu_priv), &rtl8xxxu_ops);
5828 if (!hw) {
5829 ret = -ENOMEM;
5830 goto exit;
5831 }
5832
5833 priv = hw->priv;
5834 priv->hw = hw;
5835 priv->udev = udev;
5836 priv->fops = (struct rtl8xxxu_fileops *)id->driver_info;
5837 mutex_init(&priv->usb_buf_mutex);
5838 mutex_init(&priv->h2c_mutex);
5839 INIT_LIST_HEAD(&priv->tx_urb_free_list);
5840 spin_lock_init(&priv->tx_urb_lock);
5841 INIT_LIST_HEAD(&priv->rx_urb_pending_list);
5842 spin_lock_init(&priv->rx_urb_lock);
5843 INIT_WORK(&priv->rx_urb_wq, rtl8xxxu_rx_urb_work);
5844
5845 usb_set_intfdata(interface, hw);
5846
5847 ret = rtl8xxxu_parse_usb(priv, interface);
5848 if (ret)
5849 goto exit;
5850
5851 ret = rtl8xxxu_identify_chip(priv);
5852 if (ret) {
5853 dev_err(&udev->dev, "Fatal - failed to identify chip\n");
5854 goto exit;
5855 }
5856
5857 ret = rtl8xxxu_read_efuse(priv);
5858 if (ret) {
5859 dev_err(&udev->dev, "Fatal - failed to read EFuse\n");
5860 goto exit;
5861 }
5862
5863 ret = priv->fops->parse_efuse(priv);
5864 if (ret) {
5865 dev_err(&udev->dev, "Fatal - failed to parse EFuse\n");
5866 goto exit;
5867 }
5868
5869 rtl8xxxu_print_chipinfo(priv);
5870
5871 ret = priv->fops->load_firmware(priv);
5872 if (ret) {
5873 dev_err(&udev->dev, "Fatal - failed to load firmware\n");
5874 goto exit;
5875 }
5876
5877 ret = rtl8xxxu_init_device(hw);
5878
5879 hw->wiphy->max_scan_ssids = 1;
5880 hw->wiphy->max_scan_ie_len = IEEE80211_MAX_DATA_LEN;
5881 hw->wiphy->interface_modes = BIT(NL80211_IFTYPE_STATION);
5882 hw->queues = 4;
5883
5884 sband = &rtl8xxxu_supported_band;
5885 sband->ht_cap.ht_supported = true;
5886 sband->ht_cap.ampdu_factor = IEEE80211_HT_MAX_AMPDU_64K;
5887 sband->ht_cap.ampdu_density = IEEE80211_HT_MPDU_DENSITY_16;
5888 sband->ht_cap.cap = IEEE80211_HT_CAP_SGI_20 | IEEE80211_HT_CAP_SGI_40;
5889 memset(&sband->ht_cap.mcs, 0, sizeof(sband->ht_cap.mcs));
5890 sband->ht_cap.mcs.rx_mask[0] = 0xff;
5891 sband->ht_cap.mcs.rx_mask[4] = 0x01;
5892 if (priv->rf_paths > 1) {
5893 sband->ht_cap.mcs.rx_mask[1] = 0xff;
5894 sband->ht_cap.cap |= IEEE80211_HT_CAP_SGI_40;
5895 }
5896 sband->ht_cap.mcs.tx_params = IEEE80211_HT_MCS_TX_DEFINED;
5897 /*
5898 * Some APs will negotiate HT20_40 in a noisy environment leading
5899 * to miserable performance. Rather than defaulting to this, only
5900 * enable it if explicitly requested at module load time.
5901 */
5902 if (rtl8xxxu_ht40_2g) {
5903 dev_info(&udev->dev, "Enabling HT_20_40 on the 2.4GHz band\n");
5904 sband->ht_cap.cap |= IEEE80211_HT_CAP_SUP_WIDTH_20_40;
5905 }
5906 hw->wiphy->bands[IEEE80211_BAND_2GHZ] = sband;
5907
5908 hw->wiphy->rts_threshold = 2347;
5909
5910 SET_IEEE80211_DEV(priv->hw, &interface->dev);
5911 SET_IEEE80211_PERM_ADDR(hw, priv->mac_addr);
5912
5913 hw->extra_tx_headroom = sizeof(struct rtl8xxxu_tx_desc);
5914 ieee80211_hw_set(hw, SIGNAL_DBM);
5915 /*
5916 * The firmware handles rate control
5917 */
5918 ieee80211_hw_set(hw, HAS_RATE_CONTROL);
5919 ieee80211_hw_set(hw, AMPDU_AGGREGATION);
5920
5921 ret = ieee80211_register_hw(priv->hw);
5922 if (ret) {
5923 dev_err(&udev->dev, "%s: Failed to register: %i\n",
5924 __func__, ret);
5925 goto exit;
5926 }
5927
5928exit:
5929 if (ret < 0)
5930 usb_put_dev(udev);
5931 return ret;
5932}
5933
5934static void rtl8xxxu_disconnect(struct usb_interface *interface)
5935{
5936 struct rtl8xxxu_priv *priv;
5937 struct ieee80211_hw *hw;
5938
5939 hw = usb_get_intfdata(interface);
5940 priv = hw->priv;
5941
5942 rtl8xxxu_disable_device(hw);
5943 usb_set_intfdata(interface, NULL);
5944
5945 dev_info(&priv->udev->dev, "disconnecting\n");
5946
5947 ieee80211_unregister_hw(hw);
5948
5949 kfree(priv->fw_data);
5950 mutex_destroy(&priv->usb_buf_mutex);
5951 mutex_destroy(&priv->h2c_mutex);
5952
5953 usb_put_dev(priv->udev);
5954 ieee80211_free_hw(hw);
5955}
5956
5957static struct rtl8xxxu_fileops rtl8723au_fops = {
5958 .parse_efuse = rtl8723au_parse_efuse,
5959 .load_firmware = rtl8723au_load_firmware,
5960 .power_on = rtl8723au_power_on,
5961 .writeN_block_size = 1024,
5962};
5963
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]5964#ifdef CONFIG_RTL8XXXU_UNTESTED
5965
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5966static struct rtl8xxxu_fileops rtl8192cu_fops = {
5967 .parse_efuse = rtl8192cu_parse_efuse,
5968 .load_firmware = rtl8192cu_load_firmware,
5969 .power_on = rtl8192cu_power_on,
5970 .writeN_block_size = 128,
5971};
5972
Kalle Valoc0963772015-10-25 18:24:38 +0200[diff] [blame]5973#endif
5974
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]5975static struct rtl8xxxu_fileops rtl8192eu_fops = {
5976 .parse_efuse = rtl8192eu_parse_efuse,
5977 .load_firmware = rtl8192eu_load_firmware,
5978 .power_on = rtl8192cu_power_on,
Jes Sorensen4a82ffe2016-02-29 17:04:01 -0500[diff] [blame]5979 .writeN_block_size = 1024,
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]5980};
5981
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5982static struct usb_device_id dev_table[] = {
5983{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8724, 0xff, 0xff, 0xff),
5984 .driver_info = (unsigned long)&rtl8723au_fops},
5985{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1724, 0xff, 0xff, 0xff),
5986 .driver_info = (unsigned long)&rtl8723au_fops},
5987{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x0724, 0xff, 0xff, 0xff),
5988 .driver_info = (unsigned long)&rtl8723au_fops},
Jes Sorensen3307d842016-02-29 17:03:59 -0500[diff] [blame]5989{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818b, 0xff, 0xff, 0xff),
5990 .driver_info = (unsigned long)&rtl8192eu_fops},
Kalle Valo033695b2015-10-23 20:27:58 +0300[diff] [blame]5991#ifdef CONFIG_RTL8XXXU_UNTESTED
5992/* Still supported by rtlwifi */
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]5993{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8176, 0xff, 0xff, 0xff),
5994 .driver_info = (unsigned long)&rtl8192cu_fops},
5995{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8178, 0xff, 0xff, 0xff),
5996 .driver_info = (unsigned long)&rtl8192cu_fops},
5997{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817f, 0xff, 0xff, 0xff),
5998 .driver_info = (unsigned long)&rtl8192cu_fops},
5999/* Tested by Larry Finger */
6000{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7811, 0xff, 0xff, 0xff),
6001 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6002/* Currently untested 8188 series devices */
6003{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8191, 0xff, 0xff, 0xff),
6004 .driver_info = (unsigned long)&rtl8192cu_fops},
6005{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8170, 0xff, 0xff, 0xff),
6006 .driver_info = (unsigned long)&rtl8192cu_fops},
6007{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x8177, 0xff, 0xff, 0xff),
6008 .driver_info = (unsigned long)&rtl8192cu_fops},
6009{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817a, 0xff, 0xff, 0xff),
6010 .driver_info = (unsigned long)&rtl8192cu_fops},
6011{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817b, 0xff, 0xff, 0xff),
6012 .driver_info = (unsigned long)&rtl8192cu_fops},
6013{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817d, 0xff, 0xff, 0xff),
6014 .driver_info = (unsigned long)&rtl8192cu_fops},
6015{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x817e, 0xff, 0xff, 0xff),
6016 .driver_info = (unsigned long)&rtl8192cu_fops},
6017{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x818a, 0xff, 0xff, 0xff),
6018 .driver_info = (unsigned long)&rtl8192cu_fops},
6019{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x317f, 0xff, 0xff, 0xff),
6020 .driver_info = (unsigned long)&rtl8192cu_fops},
6021{USB_DEVICE_AND_INTERFACE_INFO(0x1058, 0x0631, 0xff, 0xff, 0xff),
6022 .driver_info = (unsigned long)&rtl8192cu_fops},
6023{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x094c, 0xff, 0xff, 0xff),
6024 .driver_info = (unsigned long)&rtl8192cu_fops},
6025{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1102, 0xff, 0xff, 0xff),
6026 .driver_info = (unsigned long)&rtl8192cu_fops},
6027{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe033, 0xff, 0xff, 0xff),
6028 .driver_info = (unsigned long)&rtl8192cu_fops},
6029{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8189, 0xff, 0xff, 0xff),
6030 .driver_info = (unsigned long)&rtl8192cu_fops},
6031{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9041, 0xff, 0xff, 0xff),
6032 .driver_info = (unsigned long)&rtl8192cu_fops},
6033{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ba, 0xff, 0xff, 0xff),
6034 .driver_info = (unsigned long)&rtl8192cu_fops},
6035{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x1e1e, 0xff, 0xff, 0xff),
6036 .driver_info = (unsigned long)&rtl8192cu_fops},
6037{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x5088, 0xff, 0xff, 0xff),
6038 .driver_info = (unsigned long)&rtl8192cu_fops},
6039{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0052, 0xff, 0xff, 0xff),
6040 .driver_info = (unsigned long)&rtl8192cu_fops},
6041{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x005c, 0xff, 0xff, 0xff),
6042 .driver_info = (unsigned long)&rtl8192cu_fops},
6043{USB_DEVICE_AND_INTERFACE_INFO(0x0eb0, 0x9071, 0xff, 0xff, 0xff),
6044 .driver_info = (unsigned long)&rtl8192cu_fops},
6045{USB_DEVICE_AND_INTERFACE_INFO(0x103c, 0x1629, 0xff, 0xff, 0xff),
6046 .driver_info = (unsigned long)&rtl8192cu_fops},
6047{USB_DEVICE_AND_INTERFACE_INFO(0x13d3, 0x3357, 0xff, 0xff, 0xff),
6048 .driver_info = (unsigned long)&rtl8192cu_fops},
6049{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3308, 0xff, 0xff, 0xff),
6050 .driver_info = (unsigned long)&rtl8192cu_fops},
6051{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330b, 0xff, 0xff, 0xff),
6052 .driver_info = (unsigned long)&rtl8192cu_fops},
6053{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x4902, 0xff, 0xff, 0xff),
6054 .driver_info = (unsigned long)&rtl8192cu_fops},
6055{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2a, 0xff, 0xff, 0xff),
6056 .driver_info = (unsigned long)&rtl8192cu_fops},
6057{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2e, 0xff, 0xff, 0xff),
6058 .driver_info = (unsigned long)&rtl8192cu_fops},
6059{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xed17, 0xff, 0xff, 0xff),
6060 .driver_info = (unsigned long)&rtl8192cu_fops},
6061{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x648b, 0xff, 0xff, 0xff),
6062 .driver_info = (unsigned long)&rtl8192cu_fops},
6063{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0090, 0xff, 0xff, 0xff),
6064 .driver_info = (unsigned long)&rtl8192cu_fops},
6065{USB_DEVICE_AND_INTERFACE_INFO(0x4856, 0x0091, 0xff, 0xff, 0xff),
6066 .driver_info = (unsigned long)&rtl8192cu_fops},
6067{USB_DEVICE_AND_INTERFACE_INFO(0xcdab, 0x8010, 0xff, 0xff, 0xff),
6068 .driver_info = (unsigned long)&rtl8192cu_fops},
Jes Sorensen26f1fad2015-10-14 20:44:51 -0400[diff] [blame]6069{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff7, 0xff, 0xff, 0xff),
6070 .driver_info = (unsigned long)&rtl8192cu_fops},
6071{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff9, 0xff, 0xff, 0xff),
6072 .driver_info = (unsigned long)&rtl8192cu_fops},
6073{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffa, 0xff, 0xff, 0xff),
6074 .driver_info = (unsigned long)&rtl8192cu_fops},
6075{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaff8, 0xff, 0xff, 0xff),
6076 .driver_info = (unsigned long)&rtl8192cu_fops},
6077{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffb, 0xff, 0xff, 0xff),
6078 .driver_info = (unsigned long)&rtl8192cu_fops},
6079{USB_DEVICE_AND_INTERFACE_INFO(0x04f2, 0xaffc, 0xff, 0xff, 0xff),
6080 .driver_info = (unsigned long)&rtl8192cu_fops},
6081{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0x1201, 0xff, 0xff, 0xff),
6082 .driver_info = (unsigned long)&rtl8192cu_fops},
6083/* Currently untested 8192 series devices */
6084{USB_DEVICE_AND_INTERFACE_INFO(0x04bb, 0x0950, 0xff, 0xff, 0xff),
6085 .driver_info = (unsigned long)&rtl8192cu_fops},
6086{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x1004, 0xff, 0xff, 0xff),
6087 .driver_info = (unsigned long)&rtl8192cu_fops},
6088{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2102, 0xff, 0xff, 0xff),
6089 .driver_info = (unsigned long)&rtl8192cu_fops},
6090{USB_DEVICE_AND_INTERFACE_INFO(0x050d, 0x2103, 0xff, 0xff, 0xff),
6091 .driver_info = (unsigned long)&rtl8192cu_fops},
6092{USB_DEVICE_AND_INTERFACE_INFO(0x0586, 0x341f, 0xff, 0xff, 0xff),
6093 .driver_info = (unsigned long)&rtl8192cu_fops},
6094{USB_DEVICE_AND_INTERFACE_INFO(0x06f8, 0xe035, 0xff, 0xff, 0xff),
6095 .driver_info = (unsigned long)&rtl8192cu_fops},
6096{USB_DEVICE_AND_INTERFACE_INFO(0x0b05, 0x17ab, 0xff, 0xff, 0xff),
6097 .driver_info = (unsigned long)&rtl8192cu_fops},
6098{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0061, 0xff, 0xff, 0xff),
6099 .driver_info = (unsigned long)&rtl8192cu_fops},
6100{USB_DEVICE_AND_INTERFACE_INFO(0x0df6, 0x0070, 0xff, 0xff, 0xff),
6101 .driver_info = (unsigned long)&rtl8192cu_fops},
6102{USB_DEVICE_AND_INTERFACE_INFO(0x0789, 0x016d, 0xff, 0xff, 0xff),
6103 .driver_info = (unsigned long)&rtl8192cu_fops},
6104{USB_DEVICE_AND_INTERFACE_INFO(0x07aa, 0x0056, 0xff, 0xff, 0xff),
6105 .driver_info = (unsigned long)&rtl8192cu_fops},
6106{USB_DEVICE_AND_INTERFACE_INFO(0x07b8, 0x8178, 0xff, 0xff, 0xff),
6107 .driver_info = (unsigned long)&rtl8192cu_fops},
6108{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0x9021, 0xff, 0xff, 0xff),
6109 .driver_info = (unsigned long)&rtl8192cu_fops},
6110{USB_DEVICE_AND_INTERFACE_INFO(0x0846, 0xf001, 0xff, 0xff, 0xff),
6111 .driver_info = (unsigned long)&rtl8192cu_fops},
6112{USB_DEVICE_AND_INTERFACE_INFO(USB_VENDOR_ID_REALTEK, 0x2e2e, 0xff, 0xff, 0xff),
6113 .driver_info = (unsigned long)&rtl8192cu_fops},
6114{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0019, 0xff, 0xff, 0xff),
6115 .driver_info = (unsigned long)&rtl8192cu_fops},
6116{USB_DEVICE_AND_INTERFACE_INFO(0x0e66, 0x0020, 0xff, 0xff, 0xff),
6117 .driver_info = (unsigned long)&rtl8192cu_fops},
6118{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3307, 0xff, 0xff, 0xff),
6119 .driver_info = (unsigned long)&rtl8192cu_fops},
6120{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x3309, 0xff, 0xff, 0xff),
6121 .driver_info = (unsigned long)&rtl8192cu_fops},
6122{USB_DEVICE_AND_INTERFACE_INFO(0x2001, 0x330a, 0xff, 0xff, 0xff),
6123 .driver_info = (unsigned long)&rtl8192cu_fops},
6124{USB_DEVICE_AND_INTERFACE_INFO(0x2019, 0xab2b, 0xff, 0xff, 0xff),
6125 .driver_info = (unsigned long)&rtl8192cu_fops},
6126{USB_DEVICE_AND_INTERFACE_INFO(0x20f4, 0x624d, 0xff, 0xff, 0xff),
6127 .driver_info = (unsigned long)&rtl8192cu_fops},
6128{USB_DEVICE_AND_INTERFACE_INFO(0x2357, 0x0100, 0xff, 0xff, 0xff),
6129 .driver_info = (unsigned long)&rtl8192cu_fops},
6130{USB_DEVICE_AND_INTERFACE_INFO(0x4855, 0x0091, 0xff, 0xff, 0xff),
6131 .driver_info = (unsigned long)&rtl8192cu_fops},
6132{USB_DEVICE_AND_INTERFACE_INFO(0x7392, 0x7822, 0xff, 0xff, 0xff),
6133 .driver_info = (unsigned long)&rtl8192cu_fops},
6134#endif
6135{ }
6136};
6137
6138static struct usb_driver rtl8xxxu_driver = {
6139 .name = DRIVER_NAME,
6140 .probe = rtl8xxxu_probe,
6141 .disconnect = rtl8xxxu_disconnect,
6142 .id_table = dev_table,
6143 .disable_hub_initiated_lpm = 1,
6144};
6145
6146static int __init rtl8xxxu_module_init(void)
6147{
6148 int res;
6149
6150 res = usb_register(&rtl8xxxu_driver);
6151 if (res < 0)
6152 pr_err(DRIVER_NAME ": usb_register() failed (%i)\n", res);
6153
6154 return res;
6155}
6156
6157static void __exit rtl8xxxu_module_exit(void)
6158{
6159 usb_deregister(&rtl8xxxu_driver);
6160}
6161
6162
6163MODULE_DEVICE_TABLE(usb, dev_table);
6164
6165module_init(rtl8xxxu_module_init);
6166module_exit(rtl8xxxu_module_exit);