blob: ed7166693e5ff2d2189a09d42a3417b8397582b5 [file] [log] [blame]
Greg Rosed358aa92013-12-21 06:13:11 +00001/*******************************************************************************
2 *
3 * Intel Ethernet Controller XL710 Family Linux Virtual Function Driver
Catherine Sullivane8278452015-02-06 08:52:08 +00004 * Copyright(c) 2013 - 2015 Intel Corporation.
Greg Rosed358aa92013-12-21 06:13:11 +00005 *
6 * This program is free software; you can redistribute it and/or modify it
7 * under the terms and conditions of the GNU General Public License,
8 * version 2, as published by the Free Software Foundation.
9 *
10 * This program is distributed in the hope it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
13 * more details.
14 *
Jesse Brandeburgb8316072014-04-05 07:46:11 +000015 * You should have received a copy of the GNU General Public License along
16 * with this program. If not, see <http://www.gnu.org/licenses/>.
17 *
Greg Rosed358aa92013-12-21 06:13:11 +000018 * The full GNU General Public License is included in this distribution in
19 * the file called "COPYING".
20 *
21 * Contact Information:
22 * e1000-devel Mailing List <e1000-devel@lists.sourceforge.net>
23 * Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
24 *
25 ******************************************************************************/
26
27#ifndef _I40E_TYPE_H_
28#define _I40E_TYPE_H_
29
30#include "i40e_status.h"
31#include "i40e_osdep.h"
32#include "i40e_register.h"
33#include "i40e_adminq.h"
34#include "i40e_hmc.h"
35#include "i40e_lan_hmc.h"
36
37/* Device IDs */
Jesse Brandeburg704599e2014-05-10 04:49:14 +000038#define I40E_DEV_ID_SFP_XL710 0x1572
Shannon Nelsonab600852014-01-17 15:36:39 -080039#define I40E_DEV_ID_QEMU 0x1574
40#define I40E_DEV_ID_KX_A 0x157F
41#define I40E_DEV_ID_KX_B 0x1580
42#define I40E_DEV_ID_KX_C 0x1581
Shannon Nelsonab600852014-01-17 15:36:39 -080043#define I40E_DEV_ID_QSFP_A 0x1583
44#define I40E_DEV_ID_QSFP_B 0x1584
45#define I40E_DEV_ID_QSFP_C 0x1585
Paul M Stillwell Jr1ac1e762014-10-17 03:14:44 +000046#define I40E_DEV_ID_10G_BASE_T 0x1586
Jesse Brandeburgae24b402015-03-27 00:12:09 -070047#define I40E_DEV_ID_20G_KR2 0x1587
48#define I40E_DEV_ID_VF 0x154C
Shannon Nelsonab600852014-01-17 15:36:39 -080049#define I40E_DEV_ID_VF_HV 0x1571
Anjali Singhai Jain87e6c1d2015-06-05 12:20:25 -040050#define I40E_DEV_ID_SFP_X722 0x37D0
51#define I40E_DEV_ID_1G_BASE_T_X722 0x37D1
52#define I40E_DEV_ID_10G_BASE_T_X722 0x37D2
53#define I40E_DEV_ID_X722_VF 0x37CD
54#define I40E_DEV_ID_X722_VF_HV 0x37D9
Greg Rosed358aa92013-12-21 06:13:11 +000055
Shannon Nelsonab600852014-01-17 15:36:39 -080056#define i40e_is_40G_device(d) ((d) == I40E_DEV_ID_QSFP_A || \
57 (d) == I40E_DEV_ID_QSFP_B || \
58 (d) == I40E_DEV_ID_QSFP_C)
Greg Rosed358aa92013-12-21 06:13:11 +000059
Anjali Singhai Jain4c33f832014-06-05 00:18:21 +000060/* I40E_MASK is a macro used on 32 bit registers */
61#define I40E_MASK(mask, shift) (mask << shift)
62
Greg Rosed358aa92013-12-21 06:13:11 +000063#define I40E_MAX_VSI_QP 16
64#define I40E_MAX_VF_VSI 3
65#define I40E_MAX_CHAINED_RX_BUFFERS 5
66#define I40E_MAX_PF_UDP_OFFLOAD_PORTS 16
67
68/* Max default timeout in ms, */
69#define I40E_MAX_NVM_TIMEOUT 18000
70
Kamil Krawczyk4f4e17b2014-04-23 04:50:14 +000071/* Switch from ms to the 1usec global time (this is the GTIME resolution) */
72#define I40E_MS_TO_GTIME(time) ((time) * 1000)
Greg Rosed358aa92013-12-21 06:13:11 +000073
74/* forward declaration */
75struct i40e_hw;
76typedef void (*I40E_ADMINQ_CALLBACK)(struct i40e_hw *, struct i40e_aq_desc *);
77
Greg Rosed358aa92013-12-21 06:13:11 +000078/* Data type manipulation macros. */
79
80#define I40E_DESC_UNUSED(R) \
81 ((((R)->next_to_clean > (R)->next_to_use) ? 0 : (R)->count) + \
82 (R)->next_to_clean - (R)->next_to_use - 1)
83
84/* bitfields for Tx queue mapping in QTX_CTL */
85#define I40E_QTX_CTL_VF_QUEUE 0x0
86#define I40E_QTX_CTL_VM_QUEUE 0x1
87#define I40E_QTX_CTL_PF_QUEUE 0x2
88
89/* debug masks - set these bits in hw->debug_mask to control output */
90enum i40e_debug_mask {
91 I40E_DEBUG_INIT = 0x00000001,
92 I40E_DEBUG_RELEASE = 0x00000002,
93
94 I40E_DEBUG_LINK = 0x00000010,
95 I40E_DEBUG_PHY = 0x00000020,
96 I40E_DEBUG_HMC = 0x00000040,
97 I40E_DEBUG_NVM = 0x00000080,
98 I40E_DEBUG_LAN = 0x00000100,
99 I40E_DEBUG_FLOW = 0x00000200,
100 I40E_DEBUG_DCB = 0x00000400,
101 I40E_DEBUG_DIAG = 0x00000800,
Anjali Singhai Jainc2e1b592014-03-06 09:00:03 +0000102 I40E_DEBUG_FD = 0x00001000,
Greg Rosed358aa92013-12-21 06:13:11 +0000103
104 I40E_DEBUG_AQ_MESSAGE = 0x01000000,
105 I40E_DEBUG_AQ_DESCRIPTOR = 0x02000000,
106 I40E_DEBUG_AQ_DESC_BUFFER = 0x04000000,
107 I40E_DEBUG_AQ_COMMAND = 0x06000000,
108 I40E_DEBUG_AQ = 0x0F000000,
109
110 I40E_DEBUG_USER = 0xF0000000,
111
112 I40E_DEBUG_ALL = 0xFFFFFFFF
113};
114
Greg Rosed358aa92013-12-21 06:13:11 +0000115/* These are structs for managing the hardware information and the operations.
116 * The structures of function pointers are filled out at init time when we
117 * know for sure exactly which hardware we're working with. This gives us the
118 * flexibility of using the same main driver code but adapting to slightly
119 * different hardware needs as new parts are developed. For this architecture,
120 * the Firmware and AdminQ are intended to insulate the driver from most of the
121 * future changes, but these structures will also do part of the job.
122 */
123enum i40e_mac_type {
124 I40E_MAC_UNKNOWN = 0,
125 I40E_MAC_X710,
126 I40E_MAC_XL710,
127 I40E_MAC_VF,
Anjali Singhai Jain87e6c1d2015-06-05 12:20:25 -0400128 I40E_MAC_X722,
129 I40E_MAC_X722_VF,
Greg Rosed358aa92013-12-21 06:13:11 +0000130 I40E_MAC_GENERIC,
131};
132
133enum i40e_media_type {
134 I40E_MEDIA_TYPE_UNKNOWN = 0,
135 I40E_MEDIA_TYPE_FIBER,
136 I40E_MEDIA_TYPE_BASET,
137 I40E_MEDIA_TYPE_BACKPLANE,
138 I40E_MEDIA_TYPE_CX4,
139 I40E_MEDIA_TYPE_DA,
140 I40E_MEDIA_TYPE_VIRTUAL
141};
142
143enum i40e_fc_mode {
144 I40E_FC_NONE = 0,
145 I40E_FC_RX_PAUSE,
146 I40E_FC_TX_PAUSE,
147 I40E_FC_FULL,
148 I40E_FC_PFC,
149 I40E_FC_DEFAULT
150};
151
Catherine Sullivanc56999f2014-06-04 08:45:26 +0000152enum i40e_set_fc_aq_failures {
153 I40E_SET_FC_AQ_FAIL_NONE = 0,
154 I40E_SET_FC_AQ_FAIL_GET = 1,
155 I40E_SET_FC_AQ_FAIL_SET = 2,
156 I40E_SET_FC_AQ_FAIL_UPDATE = 4,
157 I40E_SET_FC_AQ_FAIL_SET_UPDATE = 6
158};
159
Greg Rosed358aa92013-12-21 06:13:11 +0000160enum i40e_vsi_type {
161 I40E_VSI_MAIN = 0,
162 I40E_VSI_VMDQ1,
163 I40E_VSI_VMDQ2,
164 I40E_VSI_CTRL,
165 I40E_VSI_FCOE,
166 I40E_VSI_MIRROR,
167 I40E_VSI_SRIOV,
168 I40E_VSI_FDIR,
169 I40E_VSI_TYPE_UNKNOWN
170};
171
172enum i40e_queue_type {
173 I40E_QUEUE_TYPE_RX = 0,
174 I40E_QUEUE_TYPE_TX,
175 I40E_QUEUE_TYPE_PE_CEQ,
176 I40E_QUEUE_TYPE_UNKNOWN
177};
178
179struct i40e_link_status {
180 enum i40e_aq_phy_type phy_type;
181 enum i40e_aq_link_speed link_speed;
182 u8 link_info;
183 u8 an_info;
184 u8 ext_info;
185 u8 loopback;
186 /* is Link Status Event notification to SW enabled */
187 bool lse_enable;
Neerav Parikh6bb3f232014-04-01 07:11:56 +0000188 u16 max_frame_size;
189 bool crc_enable;
190 u8 pacing;
Catherine Sullivane8278452015-02-06 08:52:08 +0000191 u8 requested_speeds;
Greg Rosed358aa92013-12-21 06:13:11 +0000192};
193
194struct i40e_phy_info {
195 struct i40e_link_status link_info;
196 struct i40e_link_status link_info_old;
197 u32 autoneg_advertised;
198 u32 phy_id;
199 u32 module_type;
200 bool get_link_info;
201 enum i40e_media_type media_type;
202};
203
204#define I40E_HW_CAP_MAX_GPIO 30
205/* Capabilities of a PF or a VF or the whole device */
206struct i40e_hw_capabilities {
207 u32 switch_mode;
208#define I40E_NVM_IMAGE_TYPE_EVB 0x0
209#define I40E_NVM_IMAGE_TYPE_CLOUD 0x2
210#define I40E_NVM_IMAGE_TYPE_UDP_CLOUD 0x3
211
212 u32 management_mode;
213 u32 npar_enable;
214 u32 os2bmc;
215 u32 valid_functions;
216 bool sr_iov_1_1;
217 bool vmdq;
218 bool evb_802_1_qbg; /* Edge Virtual Bridging */
219 bool evb_802_1_qbh; /* Bridge Port Extension */
220 bool dcb;
221 bool fcoe;
Neerav Parikh63d7e5a2014-12-14 01:55:16 +0000222 bool iscsi; /* Indicates iSCSI enabled */
Pawel Orlowskic78b9532015-04-22 19:34:06 -0400223 bool flex10_enable;
224 bool flex10_capable;
225 u32 flex10_mode;
226#define I40E_FLEX10_MODE_UNKNOWN 0x0
227#define I40E_FLEX10_MODE_DCC 0x1
228#define I40E_FLEX10_MODE_DCI 0x2
229
230 u32 flex10_status;
231#define I40E_FLEX10_STATUS_DCC_ERROR 0x1
232#define I40E_FLEX10_STATUS_VC_MODE 0x2
233
Greg Rosed358aa92013-12-21 06:13:11 +0000234 bool mgmt_cem;
235 bool ieee_1588;
236 bool iwarp;
237 bool fd;
238 u32 fd_filters_guaranteed;
239 u32 fd_filters_best_effort;
240 bool rss;
241 u32 rss_table_size;
242 u32 rss_table_entry_width;
243 bool led[I40E_HW_CAP_MAX_GPIO];
244 bool sdp[I40E_HW_CAP_MAX_GPIO];
245 u32 nvm_image_type;
246 u32 num_flow_director_filters;
247 u32 num_vfs;
248 u32 vf_base_id;
249 u32 num_vsis;
250 u32 num_rx_qp;
251 u32 num_tx_qp;
252 u32 base_queue;
253 u32 num_msix_vectors;
254 u32 num_msix_vectors_vf;
255 u32 led_pin_num;
256 u32 sdp_pin_num;
257 u32 mdio_port_num;
258 u32 mdio_port_mode;
259 u8 rx_buf_chain_len;
260 u32 enabled_tcmap;
261 u32 maxtc;
Kevin Scott73b23402015-04-07 19:45:38 -0400262 u64 wr_csr_prot;
Greg Rosed358aa92013-12-21 06:13:11 +0000263};
264
265struct i40e_mac_info {
266 enum i40e_mac_type type;
267 u8 addr[ETH_ALEN];
268 u8 perm_addr[ETH_ALEN];
269 u8 san_addr[ETH_ALEN];
270 u16 max_fcoeq;
271};
272
273enum i40e_aq_resources_ids {
274 I40E_NVM_RESOURCE_ID = 1
275};
276
277enum i40e_aq_resource_access_type {
278 I40E_RESOURCE_READ = 1,
279 I40E_RESOURCE_WRITE
280};
281
282struct i40e_nvm_info {
Shannon Nelsonc509c1d2014-11-13 08:23:19 +0000283 u64 hw_semaphore_timeout; /* usec global time (GTIME resolution) */
Greg Rosed358aa92013-12-21 06:13:11 +0000284 u32 timeout; /* [ms] */
285 u16 sr_size; /* Shadow RAM size in words */
286 bool blank_nvm_mode; /* is NVM empty (no FW present)*/
287 u16 version; /* NVM package version */
288 u32 eetrack; /* NVM data version */
289};
290
Shannon Nelsoncd552cb2014-07-09 07:46:09 +0000291/* definitions used in NVM update support */
292
293enum i40e_nvmupd_cmd {
294 I40E_NVMUPD_INVALID,
295 I40E_NVMUPD_READ_CON,
296 I40E_NVMUPD_READ_SNT,
297 I40E_NVMUPD_READ_LCB,
298 I40E_NVMUPD_READ_SA,
299 I40E_NVMUPD_WRITE_ERA,
300 I40E_NVMUPD_WRITE_CON,
301 I40E_NVMUPD_WRITE_SNT,
302 I40E_NVMUPD_WRITE_LCB,
303 I40E_NVMUPD_WRITE_SA,
304 I40E_NVMUPD_CSUM_CON,
305 I40E_NVMUPD_CSUM_SA,
306 I40E_NVMUPD_CSUM_LCB,
Shannon Nelson0af8e9d2015-08-28 17:55:48 -0400307 I40E_NVMUPD_STATUS,
Shannon Nelsone4c83c22015-08-28 17:55:50 -0400308 I40E_NVMUPD_EXEC_AQ,
Shannon Nelsonb72dc7b2015-08-28 17:55:51 -0400309 I40E_NVMUPD_GET_AQ_RESULT,
Shannon Nelsoncd552cb2014-07-09 07:46:09 +0000310};
311
312enum i40e_nvmupd_state {
313 I40E_NVMUPD_STATE_INIT,
314 I40E_NVMUPD_STATE_READING,
Shannon Nelson2f1b5bc2015-08-28 17:55:49 -0400315 I40E_NVMUPD_STATE_WRITING,
316 I40E_NVMUPD_STATE_INIT_WAIT,
317 I40E_NVMUPD_STATE_WRITE_WAIT,
Shannon Nelsoncd552cb2014-07-09 07:46:09 +0000318};
319
320/* nvm_access definition and its masks/shifts need to be accessible to
321 * application, core driver, and shared code. Where is the right file?
322 */
323#define I40E_NVM_READ 0xB
324#define I40E_NVM_WRITE 0xC
325
326#define I40E_NVM_MOD_PNT_MASK 0xFF
327
328#define I40E_NVM_TRANS_SHIFT 8
329#define I40E_NVM_TRANS_MASK (0xf << I40E_NVM_TRANS_SHIFT)
330#define I40E_NVM_CON 0x0
331#define I40E_NVM_SNT 0x1
332#define I40E_NVM_LCB 0x2
333#define I40E_NVM_SA (I40E_NVM_SNT | I40E_NVM_LCB)
334#define I40E_NVM_ERA 0x4
335#define I40E_NVM_CSUM 0x8
Shannon Nelson0af8e9d2015-08-28 17:55:48 -0400336#define I40E_NVM_EXEC 0xf
Shannon Nelsoncd552cb2014-07-09 07:46:09 +0000337
338#define I40E_NVM_ADAPT_SHIFT 16
339#define I40E_NVM_ADAPT_MASK (0xffff << I40E_NVM_ADAPT_SHIFT)
340
341#define I40E_NVMUPD_MAX_DATA 4096
342#define I40E_NVMUPD_IFACE_TIMEOUT 2 /* seconds */
343
344struct i40e_nvm_access {
345 u32 command;
346 u32 config;
347 u32 offset; /* in bytes */
348 u32 data_size; /* in bytes */
349 u8 data[1];
350};
351
Greg Rosed358aa92013-12-21 06:13:11 +0000352/* PCI bus types */
353enum i40e_bus_type {
354 i40e_bus_type_unknown = 0,
355 i40e_bus_type_pci,
356 i40e_bus_type_pcix,
357 i40e_bus_type_pci_express,
358 i40e_bus_type_reserved
359};
360
361/* PCI bus speeds */
362enum i40e_bus_speed {
363 i40e_bus_speed_unknown = 0,
364 i40e_bus_speed_33 = 33,
365 i40e_bus_speed_66 = 66,
366 i40e_bus_speed_100 = 100,
367 i40e_bus_speed_120 = 120,
368 i40e_bus_speed_133 = 133,
369 i40e_bus_speed_2500 = 2500,
370 i40e_bus_speed_5000 = 5000,
371 i40e_bus_speed_8000 = 8000,
372 i40e_bus_speed_reserved
373};
374
375/* PCI bus widths */
376enum i40e_bus_width {
377 i40e_bus_width_unknown = 0,
378 i40e_bus_width_pcie_x1 = 1,
379 i40e_bus_width_pcie_x2 = 2,
380 i40e_bus_width_pcie_x4 = 4,
381 i40e_bus_width_pcie_x8 = 8,
382 i40e_bus_width_32 = 32,
383 i40e_bus_width_64 = 64,
384 i40e_bus_width_reserved
385};
386
387/* Bus parameters */
388struct i40e_bus_info {
389 enum i40e_bus_speed speed;
390 enum i40e_bus_width width;
391 enum i40e_bus_type type;
392
393 u16 func;
394 u16 device;
395 u16 lan_id;
396};
397
398/* Flow control (FC) parameters */
399struct i40e_fc_info {
400 enum i40e_fc_mode current_mode; /* FC mode in effect */
401 enum i40e_fc_mode requested_mode; /* FC mode requested by caller */
402};
403
404#define I40E_MAX_TRAFFIC_CLASS 8
405#define I40E_MAX_USER_PRIORITY 8
406#define I40E_DCBX_MAX_APPS 32
407#define I40E_LLDPDU_SIZE 1500
408
409/* IEEE 802.1Qaz ETS Configuration data */
410struct i40e_ieee_ets_config {
411 u8 willing;
412 u8 cbs;
413 u8 maxtcs;
414 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
415 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
416 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
417};
418
419/* IEEE 802.1Qaz ETS Recommendation data */
420struct i40e_ieee_ets_recommend {
421 u8 prioritytable[I40E_MAX_TRAFFIC_CLASS];
422 u8 tcbwtable[I40E_MAX_TRAFFIC_CLASS];
423 u8 tsatable[I40E_MAX_TRAFFIC_CLASS];
424};
425
426/* IEEE 802.1Qaz PFC Configuration data */
427struct i40e_ieee_pfc_config {
428 u8 willing;
429 u8 mbc;
430 u8 pfccap;
431 u8 pfcenable;
432};
433
434/* IEEE 802.1Qaz Application Priority data */
435struct i40e_ieee_app_priority_table {
436 u8 priority;
437 u8 selector;
438 u16 protocolid;
439};
440
441struct i40e_dcbx_config {
442 u32 numapps;
Neerav Parikh9fffa3f2015-07-10 19:36:09 -0400443 u32 tlv_status; /* CEE mode TLV status */
Greg Rosed358aa92013-12-21 06:13:11 +0000444 struct i40e_ieee_ets_config etscfg;
445 struct i40e_ieee_ets_recommend etsrec;
446 struct i40e_ieee_pfc_config pfc;
447 struct i40e_ieee_app_priority_table app[I40E_DCBX_MAX_APPS];
448};
449
450/* Port hardware description */
451struct i40e_hw {
452 u8 __iomem *hw_addr;
453 void *back;
454
Shannon Nelson9fee9db2014-12-11 07:06:30 +0000455 /* subsystem structs */
Greg Rosed358aa92013-12-21 06:13:11 +0000456 struct i40e_phy_info phy;
457 struct i40e_mac_info mac;
458 struct i40e_bus_info bus;
459 struct i40e_nvm_info nvm;
460 struct i40e_fc_info fc;
461
462 /* pci info */
463 u16 device_id;
464 u16 vendor_id;
465 u16 subsystem_device_id;
466 u16 subsystem_vendor_id;
467 u8 revision_id;
468 u8 port;
469 bool adapter_stopped;
470
471 /* capabilities for entire device and PCI func */
472 struct i40e_hw_capabilities dev_caps;
473 struct i40e_hw_capabilities func_caps;
474
475 /* Flow Director shared filter space */
476 u16 fdir_shared_filter_count;
477
478 /* device profile info */
479 u8 pf_id;
480 u16 main_vsi_seid;
481
Shannon Nelson9fee9db2014-12-11 07:06:30 +0000482 /* for multi-function MACs */
483 u16 partition_id;
484 u16 num_partitions;
485 u16 num_ports;
486
Greg Rosed358aa92013-12-21 06:13:11 +0000487 /* Closest numa node to the device */
488 u16 numa_node;
489
490 /* Admin Queue info */
491 struct i40e_adminq_info aq;
492
Shannon Nelsoncd552cb2014-07-09 07:46:09 +0000493 /* state of nvm update process */
494 enum i40e_nvmupd_state nvmupd_state;
Shannon Nelson6b5c1b82015-08-28 17:55:47 -0400495 struct i40e_aq_desc nvm_wb_desc;
Shannon Nelsone4c83c22015-08-28 17:55:50 -0400496 struct i40e_virt_mem nvm_buff;
Shannon Nelsoncd552cb2014-07-09 07:46:09 +0000497
Greg Rosed358aa92013-12-21 06:13:11 +0000498 /* HMC info */
499 struct i40e_hmc_info hmc; /* HMC info struct */
500
501 /* LLDP/DCBX Status */
502 u16 dcbx_status;
503
504 /* DCBX info */
505 struct i40e_dcbx_config local_dcbx_config;
506 struct i40e_dcbx_config remote_dcbx_config;
507
508 /* debug mask */
509 u32 debug_mask;
Shannon Nelsonf1c7e722015-06-04 16:24:01 -0400510 char err_str[16];
Greg Rosed358aa92013-12-21 06:13:11 +0000511};
512
Jeff Kirsher4bd145b2014-12-09 02:31:16 -0800513static inline bool i40e_is_vf(struct i40e_hw *hw)
514{
Anjali Singhai Jain87e6c1d2015-06-05 12:20:25 -0400515 return (hw->mac.type == I40E_MAC_VF ||
516 hw->mac.type == I40E_MAC_X722_VF);
Jeff Kirsher4bd145b2014-12-09 02:31:16 -0800517}
Anjali Singhai Jaine7f2e4b2014-11-11 20:06:58 +0000518
Greg Rosed358aa92013-12-21 06:13:11 +0000519struct i40e_driver_version {
520 u8 major_version;
521 u8 minor_version;
522 u8 build_version;
523 u8 subbuild_version;
Shannon Nelsond2466012014-04-01 07:11:45 +0000524 u8 driver_string[32];
Greg Rosed358aa92013-12-21 06:13:11 +0000525};
526
527/* RX Descriptors */
528union i40e_16byte_rx_desc {
529 struct {
530 __le64 pkt_addr; /* Packet buffer address */
531 __le64 hdr_addr; /* Header buffer address */
532 } read;
533 struct {
534 struct {
535 struct {
536 union {
537 __le16 mirroring_status;
538 __le16 fcoe_ctx_id;
539 } mirr_fcoe;
540 __le16 l2tag1;
541 } lo_dword;
542 union {
543 __le32 rss; /* RSS Hash */
544 __le32 fd_id; /* Flow director filter id */
545 __le32 fcoe_param; /* FCoE DDP Context id */
546 } hi_dword;
547 } qword0;
548 struct {
549 /* ext status/error/pktype/length */
550 __le64 status_error_len;
551 } qword1;
552 } wb; /* writeback */
553};
554
555union i40e_32byte_rx_desc {
556 struct {
557 __le64 pkt_addr; /* Packet buffer address */
558 __le64 hdr_addr; /* Header buffer address */
559 /* bit 0 of hdr_buffer_addr is DD bit */
560 __le64 rsvd1;
561 __le64 rsvd2;
562 } read;
563 struct {
564 struct {
565 struct {
566 union {
567 __le16 mirroring_status;
568 __le16 fcoe_ctx_id;
569 } mirr_fcoe;
570 __le16 l2tag1;
571 } lo_dword;
572 union {
573 __le32 rss; /* RSS Hash */
574 __le32 fcoe_param; /* FCoE DDP Context id */
Anjali Singhai Jain77e29bc2014-02-11 08:24:11 +0000575 /* Flow director filter id in case of
576 * Programming status desc WB
577 */
578 __le32 fd_id;
Greg Rosed358aa92013-12-21 06:13:11 +0000579 } hi_dword;
580 } qword0;
581 struct {
582 /* status/error/pktype/length */
583 __le64 status_error_len;
584 } qword1;
585 struct {
586 __le16 ext_status; /* extended status */
587 __le16 rsvd;
588 __le16 l2tag2_1;
589 __le16 l2tag2_2;
590 } qword2;
591 struct {
592 union {
593 __le32 flex_bytes_lo;
594 __le32 pe_status;
595 } lo_dword;
596 union {
597 __le32 flex_bytes_hi;
598 __le32 fd_id;
599 } hi_dword;
600 } qword3;
601 } wb; /* writeback */
602};
603
Greg Rosed358aa92013-12-21 06:13:11 +0000604enum i40e_rx_desc_status_bits {
605 /* Note: These are predefined bit offsets */
606 I40E_RX_DESC_STATUS_DD_SHIFT = 0,
607 I40E_RX_DESC_STATUS_EOF_SHIFT = 1,
608 I40E_RX_DESC_STATUS_L2TAG1P_SHIFT = 2,
609 I40E_RX_DESC_STATUS_L3L4P_SHIFT = 3,
610 I40E_RX_DESC_STATUS_CRCP_SHIFT = 4,
611 I40E_RX_DESC_STATUS_TSYNINDX_SHIFT = 5, /* 2 BITS */
612 I40E_RX_DESC_STATUS_TSYNVALID_SHIFT = 7,
Anjali Singhai Jain527274c2015-06-05 12:20:31 -0400613 /* Note: Bit 8 is reserved in X710 and XL710 */
614 I40E_RX_DESC_STATUS_EXT_UDP_0_SHIFT = 8,
Greg Rosed358aa92013-12-21 06:13:11 +0000615 I40E_RX_DESC_STATUS_UMBCAST_SHIFT = 9, /* 2 BITS */
616 I40E_RX_DESC_STATUS_FLM_SHIFT = 11,
617 I40E_RX_DESC_STATUS_FLTSTAT_SHIFT = 12, /* 2 BITS */
618 I40E_RX_DESC_STATUS_LPBK_SHIFT = 14,
619 I40E_RX_DESC_STATUS_IPV6EXADD_SHIFT = 15,
620 I40E_RX_DESC_STATUS_RESERVED_SHIFT = 16, /* 2 BITS */
Anjali Singhai Jain527274c2015-06-05 12:20:31 -0400621 /* Note: For non-tunnel packets INT_UDP_0 is the right status for
622 * UDP header
623 */
624 I40E_RX_DESC_STATUS_INT_UDP_0_SHIFT = 18,
Jesse Brandeburgc2451d72014-05-10 04:49:01 +0000625 I40E_RX_DESC_STATUS_LAST /* this entry must be last!!! */
Greg Rosed358aa92013-12-21 06:13:11 +0000626};
627
Jesse Brandeburgc2451d72014-05-10 04:49:01 +0000628#define I40E_RXD_QW1_STATUS_SHIFT 0
Jesse Brandeburg41a1d042015-06-04 16:24:02 -0400629#define I40E_RXD_QW1_STATUS_MASK ((BIT(I40E_RX_DESC_STATUS_LAST) - 1) \
Jesse Brandeburgc2451d72014-05-10 04:49:01 +0000630 << I40E_RXD_QW1_STATUS_SHIFT)
631
Greg Rosed358aa92013-12-21 06:13:11 +0000632#define I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT I40E_RX_DESC_STATUS_TSYNINDX_SHIFT
633#define I40E_RXD_QW1_STATUS_TSYNINDX_MASK (0x3UL << \
634 I40E_RXD_QW1_STATUS_TSYNINDX_SHIFT)
635
636#define I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT I40E_RX_DESC_STATUS_TSYNVALID_SHIFT
Jesse Brandeburg41a1d042015-06-04 16:24:02 -0400637#define I40E_RXD_QW1_STATUS_TSYNVALID_MASK \
638 BIT_ULL(I40E_RXD_QW1_STATUS_TSYNVALID_SHIFT)
Greg Rosed358aa92013-12-21 06:13:11 +0000639
640enum i40e_rx_desc_fltstat_values {
641 I40E_RX_DESC_FLTSTAT_NO_DATA = 0,
642 I40E_RX_DESC_FLTSTAT_RSV_FD_ID = 1, /* 16byte desc? FD_ID : RSV */
643 I40E_RX_DESC_FLTSTAT_RSV = 2,
644 I40E_RX_DESC_FLTSTAT_RSS_HASH = 3,
645};
646
647#define I40E_RXD_QW1_ERROR_SHIFT 19
648#define I40E_RXD_QW1_ERROR_MASK (0xFFUL << I40E_RXD_QW1_ERROR_SHIFT)
649
650enum i40e_rx_desc_error_bits {
651 /* Note: These are predefined bit offsets */
652 I40E_RX_DESC_ERROR_RXE_SHIFT = 0,
653 I40E_RX_DESC_ERROR_RECIPE_SHIFT = 1,
654 I40E_RX_DESC_ERROR_HBO_SHIFT = 2,
655 I40E_RX_DESC_ERROR_L3L4E_SHIFT = 3, /* 3 BITS */
656 I40E_RX_DESC_ERROR_IPE_SHIFT = 3,
657 I40E_RX_DESC_ERROR_L4E_SHIFT = 4,
658 I40E_RX_DESC_ERROR_EIPE_SHIFT = 5,
Jesse Brandeburg8a3c91c2014-05-20 08:01:43 +0000659 I40E_RX_DESC_ERROR_OVERSIZE_SHIFT = 6,
660 I40E_RX_DESC_ERROR_PPRS_SHIFT = 7
Greg Rosed358aa92013-12-21 06:13:11 +0000661};
662
663enum i40e_rx_desc_error_l3l4e_fcoe_masks {
664 I40E_RX_DESC_ERROR_L3L4E_NONE = 0,
665 I40E_RX_DESC_ERROR_L3L4E_PROT = 1,
666 I40E_RX_DESC_ERROR_L3L4E_FC = 2,
667 I40E_RX_DESC_ERROR_L3L4E_DMAC_ERR = 3,
668 I40E_RX_DESC_ERROR_L3L4E_DMAC_WARN = 4
669};
670
671#define I40E_RXD_QW1_PTYPE_SHIFT 30
672#define I40E_RXD_QW1_PTYPE_MASK (0xFFULL << I40E_RXD_QW1_PTYPE_SHIFT)
673
674/* Packet type non-ip values */
675enum i40e_rx_l2_ptype {
676 I40E_RX_PTYPE_L2_RESERVED = 0,
677 I40E_RX_PTYPE_L2_MAC_PAY2 = 1,
678 I40E_RX_PTYPE_L2_TIMESYNC_PAY2 = 2,
679 I40E_RX_PTYPE_L2_FIP_PAY2 = 3,
680 I40E_RX_PTYPE_L2_OUI_PAY2 = 4,
681 I40E_RX_PTYPE_L2_MACCNTRL_PAY2 = 5,
682 I40E_RX_PTYPE_L2_LLDP_PAY2 = 6,
683 I40E_RX_PTYPE_L2_ECP_PAY2 = 7,
684 I40E_RX_PTYPE_L2_EVB_PAY2 = 8,
685 I40E_RX_PTYPE_L2_QCN_PAY2 = 9,
686 I40E_RX_PTYPE_L2_EAPOL_PAY2 = 10,
687 I40E_RX_PTYPE_L2_ARP = 11,
688 I40E_RX_PTYPE_L2_FCOE_PAY3 = 12,
689 I40E_RX_PTYPE_L2_FCOE_FCDATA_PAY3 = 13,
690 I40E_RX_PTYPE_L2_FCOE_FCRDY_PAY3 = 14,
691 I40E_RX_PTYPE_L2_FCOE_FCRSP_PAY3 = 15,
692 I40E_RX_PTYPE_L2_FCOE_FCOTHER_PA = 16,
693 I40E_RX_PTYPE_L2_FCOE_VFT_PAY3 = 17,
694 I40E_RX_PTYPE_L2_FCOE_VFT_FCDATA = 18,
695 I40E_RX_PTYPE_L2_FCOE_VFT_FCRDY = 19,
696 I40E_RX_PTYPE_L2_FCOE_VFT_FCRSP = 20,
697 I40E_RX_PTYPE_L2_FCOE_VFT_FCOTHER = 21,
698 I40E_RX_PTYPE_GRENAT4_MAC_PAY3 = 58,
699 I40E_RX_PTYPE_GRENAT4_MACVLAN_IPV6_ICMP_PAY4 = 87,
700 I40E_RX_PTYPE_GRENAT6_MAC_PAY3 = 124,
701 I40E_RX_PTYPE_GRENAT6_MACVLAN_IPV6_ICMP_PAY4 = 153
702};
703
704struct i40e_rx_ptype_decoded {
705 u32 ptype:8;
706 u32 known:1;
707 u32 outer_ip:1;
708 u32 outer_ip_ver:1;
709 u32 outer_frag:1;
710 u32 tunnel_type:3;
711 u32 tunnel_end_prot:2;
712 u32 tunnel_end_frag:1;
713 u32 inner_prot:4;
714 u32 payload_layer:3;
715};
716
717enum i40e_rx_ptype_outer_ip {
718 I40E_RX_PTYPE_OUTER_L2 = 0,
719 I40E_RX_PTYPE_OUTER_IP = 1
720};
721
722enum i40e_rx_ptype_outer_ip_ver {
723 I40E_RX_PTYPE_OUTER_NONE = 0,
724 I40E_RX_PTYPE_OUTER_IPV4 = 0,
725 I40E_RX_PTYPE_OUTER_IPV6 = 1
726};
727
728enum i40e_rx_ptype_outer_fragmented {
729 I40E_RX_PTYPE_NOT_FRAG = 0,
730 I40E_RX_PTYPE_FRAG = 1
731};
732
733enum i40e_rx_ptype_tunnel_type {
734 I40E_RX_PTYPE_TUNNEL_NONE = 0,
735 I40E_RX_PTYPE_TUNNEL_IP_IP = 1,
736 I40E_RX_PTYPE_TUNNEL_IP_GRENAT = 2,
737 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC = 3,
738 I40E_RX_PTYPE_TUNNEL_IP_GRENAT_MAC_VLAN = 4,
739};
740
741enum i40e_rx_ptype_tunnel_end_prot {
742 I40E_RX_PTYPE_TUNNEL_END_NONE = 0,
743 I40E_RX_PTYPE_TUNNEL_END_IPV4 = 1,
744 I40E_RX_PTYPE_TUNNEL_END_IPV6 = 2,
745};
746
747enum i40e_rx_ptype_inner_prot {
748 I40E_RX_PTYPE_INNER_PROT_NONE = 0,
749 I40E_RX_PTYPE_INNER_PROT_UDP = 1,
750 I40E_RX_PTYPE_INNER_PROT_TCP = 2,
751 I40E_RX_PTYPE_INNER_PROT_SCTP = 3,
752 I40E_RX_PTYPE_INNER_PROT_ICMP = 4,
753 I40E_RX_PTYPE_INNER_PROT_TIMESYNC = 5
754};
755
756enum i40e_rx_ptype_payload_layer {
757 I40E_RX_PTYPE_PAYLOAD_LAYER_NONE = 0,
758 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY2 = 1,
759 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY3 = 2,
760 I40E_RX_PTYPE_PAYLOAD_LAYER_PAY4 = 3,
761};
762
763#define I40E_RXD_QW1_LENGTH_PBUF_SHIFT 38
764#define I40E_RXD_QW1_LENGTH_PBUF_MASK (0x3FFFULL << \
765 I40E_RXD_QW1_LENGTH_PBUF_SHIFT)
766
767#define I40E_RXD_QW1_LENGTH_HBUF_SHIFT 52
768#define I40E_RXD_QW1_LENGTH_HBUF_MASK (0x7FFULL << \
769 I40E_RXD_QW1_LENGTH_HBUF_SHIFT)
770
771#define I40E_RXD_QW1_LENGTH_SPH_SHIFT 63
Jesse Brandeburg41a1d042015-06-04 16:24:02 -0400772#define I40E_RXD_QW1_LENGTH_SPH_MASK BIT_ULL(I40E_RXD_QW1_LENGTH_SPH_SHIFT)
Greg Rosed358aa92013-12-21 06:13:11 +0000773
774enum i40e_rx_desc_ext_status_bits {
775 /* Note: These are predefined bit offsets */
776 I40E_RX_DESC_EXT_STATUS_L2TAG2P_SHIFT = 0,
777 I40E_RX_DESC_EXT_STATUS_L2TAG3P_SHIFT = 1,
778 I40E_RX_DESC_EXT_STATUS_FLEXBL_SHIFT = 2, /* 2 BITS */
779 I40E_RX_DESC_EXT_STATUS_FLEXBH_SHIFT = 4, /* 2 BITS */
Greg Rosed358aa92013-12-21 06:13:11 +0000780 I40E_RX_DESC_EXT_STATUS_FDLONGB_SHIFT = 9,
781 I40E_RX_DESC_EXT_STATUS_FCOELONGB_SHIFT = 10,
782 I40E_RX_DESC_EXT_STATUS_PELONGB_SHIFT = 11,
783};
784
785enum i40e_rx_desc_pe_status_bits {
786 /* Note: These are predefined bit offsets */
787 I40E_RX_DESC_PE_STATUS_QPID_SHIFT = 0, /* 18 BITS */
788 I40E_RX_DESC_PE_STATUS_L4PORT_SHIFT = 0, /* 16 BITS */
789 I40E_RX_DESC_PE_STATUS_IPINDEX_SHIFT = 16, /* 8 BITS */
790 I40E_RX_DESC_PE_STATUS_QPIDHIT_SHIFT = 24,
791 I40E_RX_DESC_PE_STATUS_APBVTHIT_SHIFT = 25,
792 I40E_RX_DESC_PE_STATUS_PORTV_SHIFT = 26,
793 I40E_RX_DESC_PE_STATUS_URG_SHIFT = 27,
794 I40E_RX_DESC_PE_STATUS_IPFRAG_SHIFT = 28,
795 I40E_RX_DESC_PE_STATUS_IPOPT_SHIFT = 29
796};
797
798#define I40E_RX_PROG_STATUS_DESC_LENGTH_SHIFT 38
799#define I40E_RX_PROG_STATUS_DESC_LENGTH 0x2000000
800
801#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT 2
802#define I40E_RX_PROG_STATUS_DESC_QW1_PROGID_MASK (0x7UL << \
803 I40E_RX_PROG_STATUS_DESC_QW1_PROGID_SHIFT)
804
805#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT 19
806#define I40E_RX_PROG_STATUS_DESC_QW1_ERROR_MASK (0x3FUL << \
807 I40E_RX_PROG_STATUS_DESC_QW1_ERROR_SHIFT)
808
809enum i40e_rx_prog_status_desc_status_bits {
810 /* Note: These are predefined bit offsets */
811 I40E_RX_PROG_STATUS_DESC_DD_SHIFT = 0,
812 I40E_RX_PROG_STATUS_DESC_PROG_ID_SHIFT = 2 /* 3 BITS */
813};
814
815enum i40e_rx_prog_status_desc_prog_id_masks {
816 I40E_RX_PROG_STATUS_DESC_FD_FILTER_STATUS = 1,
817 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_PROG_STATUS = 2,
818 I40E_RX_PROG_STATUS_DESC_FCOE_CTXT_INVL_STATUS = 4,
819};
820
821enum i40e_rx_prog_status_desc_error_bits {
822 /* Note: These are predefined bit offsets */
823 I40E_RX_PROG_STATUS_DESC_FD_TBL_FULL_SHIFT = 0,
Anjali Singhai Jain77e29bc2014-02-11 08:24:11 +0000824 I40E_RX_PROG_STATUS_DESC_NO_FD_ENTRY_SHIFT = 1,
Greg Rosed358aa92013-12-21 06:13:11 +0000825 I40E_RX_PROG_STATUS_DESC_FCOE_TBL_FULL_SHIFT = 2,
826 I40E_RX_PROG_STATUS_DESC_FCOE_CONFLICT_SHIFT = 3
827};
828
829/* TX Descriptor */
830struct i40e_tx_desc {
831 __le64 buffer_addr; /* Address of descriptor's data buf */
832 __le64 cmd_type_offset_bsz;
833};
834
835#define I40E_TXD_QW1_DTYPE_SHIFT 0
836#define I40E_TXD_QW1_DTYPE_MASK (0xFUL << I40E_TXD_QW1_DTYPE_SHIFT)
837
838enum i40e_tx_desc_dtype_value {
839 I40E_TX_DESC_DTYPE_DATA = 0x0,
840 I40E_TX_DESC_DTYPE_NOP = 0x1, /* same as Context desc */
841 I40E_TX_DESC_DTYPE_CONTEXT = 0x1,
842 I40E_TX_DESC_DTYPE_FCOE_CTX = 0x2,
843 I40E_TX_DESC_DTYPE_FILTER_PROG = 0x8,
844 I40E_TX_DESC_DTYPE_DDP_CTX = 0x9,
845 I40E_TX_DESC_DTYPE_FLEX_DATA = 0xB,
846 I40E_TX_DESC_DTYPE_FLEX_CTX_1 = 0xC,
847 I40E_TX_DESC_DTYPE_FLEX_CTX_2 = 0xD,
848 I40E_TX_DESC_DTYPE_DESC_DONE = 0xF
849};
850
851#define I40E_TXD_QW1_CMD_SHIFT 4
852#define I40E_TXD_QW1_CMD_MASK (0x3FFUL << I40E_TXD_QW1_CMD_SHIFT)
853
854enum i40e_tx_desc_cmd_bits {
855 I40E_TX_DESC_CMD_EOP = 0x0001,
856 I40E_TX_DESC_CMD_RS = 0x0002,
857 I40E_TX_DESC_CMD_ICRC = 0x0004,
858 I40E_TX_DESC_CMD_IL2TAG1 = 0x0008,
859 I40E_TX_DESC_CMD_DUMMY = 0x0010,
860 I40E_TX_DESC_CMD_IIPT_NONIP = 0x0000, /* 2 BITS */
861 I40E_TX_DESC_CMD_IIPT_IPV6 = 0x0020, /* 2 BITS */
862 I40E_TX_DESC_CMD_IIPT_IPV4 = 0x0040, /* 2 BITS */
863 I40E_TX_DESC_CMD_IIPT_IPV4_CSUM = 0x0060, /* 2 BITS */
864 I40E_TX_DESC_CMD_FCOET = 0x0080,
865 I40E_TX_DESC_CMD_L4T_EOFT_UNK = 0x0000, /* 2 BITS */
866 I40E_TX_DESC_CMD_L4T_EOFT_TCP = 0x0100, /* 2 BITS */
867 I40E_TX_DESC_CMD_L4T_EOFT_SCTP = 0x0200, /* 2 BITS */
868 I40E_TX_DESC_CMD_L4T_EOFT_UDP = 0x0300, /* 2 BITS */
869 I40E_TX_DESC_CMD_L4T_EOFT_EOF_N = 0x0000, /* 2 BITS */
870 I40E_TX_DESC_CMD_L4T_EOFT_EOF_T = 0x0100, /* 2 BITS */
871 I40E_TX_DESC_CMD_L4T_EOFT_EOF_NI = 0x0200, /* 2 BITS */
872 I40E_TX_DESC_CMD_L4T_EOFT_EOF_A = 0x0300, /* 2 BITS */
873};
874
875#define I40E_TXD_QW1_OFFSET_SHIFT 16
876#define I40E_TXD_QW1_OFFSET_MASK (0x3FFFFULL << \
877 I40E_TXD_QW1_OFFSET_SHIFT)
878
879enum i40e_tx_desc_length_fields {
880 /* Note: These are predefined bit offsets */
881 I40E_TX_DESC_LENGTH_MACLEN_SHIFT = 0, /* 7 BITS */
882 I40E_TX_DESC_LENGTH_IPLEN_SHIFT = 7, /* 7 BITS */
883 I40E_TX_DESC_LENGTH_L4_FC_LEN_SHIFT = 14 /* 4 BITS */
884};
885
886#define I40E_TXD_QW1_TX_BUF_SZ_SHIFT 34
887#define I40E_TXD_QW1_TX_BUF_SZ_MASK (0x3FFFULL << \
888 I40E_TXD_QW1_TX_BUF_SZ_SHIFT)
889
890#define I40E_TXD_QW1_L2TAG1_SHIFT 48
891#define I40E_TXD_QW1_L2TAG1_MASK (0xFFFFULL << I40E_TXD_QW1_L2TAG1_SHIFT)
892
893/* Context descriptors */
894struct i40e_tx_context_desc {
895 __le32 tunneling_params;
896 __le16 l2tag2;
897 __le16 rsvd;
898 __le64 type_cmd_tso_mss;
899};
900
901#define I40E_TXD_CTX_QW1_DTYPE_SHIFT 0
902#define I40E_TXD_CTX_QW1_DTYPE_MASK (0xFUL << I40E_TXD_CTX_QW1_DTYPE_SHIFT)
903
904#define I40E_TXD_CTX_QW1_CMD_SHIFT 4
905#define I40E_TXD_CTX_QW1_CMD_MASK (0xFFFFUL << I40E_TXD_CTX_QW1_CMD_SHIFT)
906
907enum i40e_tx_ctx_desc_cmd_bits {
908 I40E_TX_CTX_DESC_TSO = 0x01,
909 I40E_TX_CTX_DESC_TSYN = 0x02,
910 I40E_TX_CTX_DESC_IL2TAG2 = 0x04,
911 I40E_TX_CTX_DESC_IL2TAG2_IL2H = 0x08,
912 I40E_TX_CTX_DESC_SWTCH_NOTAG = 0x00,
913 I40E_TX_CTX_DESC_SWTCH_UPLINK = 0x10,
914 I40E_TX_CTX_DESC_SWTCH_LOCAL = 0x20,
915 I40E_TX_CTX_DESC_SWTCH_VSI = 0x30,
916 I40E_TX_CTX_DESC_SWPE = 0x40
917};
918
919#define I40E_TXD_CTX_QW1_TSO_LEN_SHIFT 30
920#define I40E_TXD_CTX_QW1_TSO_LEN_MASK (0x3FFFFULL << \
921 I40E_TXD_CTX_QW1_TSO_LEN_SHIFT)
922
923#define I40E_TXD_CTX_QW1_MSS_SHIFT 50
924#define I40E_TXD_CTX_QW1_MSS_MASK (0x3FFFULL << \
925 I40E_TXD_CTX_QW1_MSS_SHIFT)
926
927#define I40E_TXD_CTX_QW1_VSI_SHIFT 50
928#define I40E_TXD_CTX_QW1_VSI_MASK (0x1FFULL << I40E_TXD_CTX_QW1_VSI_SHIFT)
929
930#define I40E_TXD_CTX_QW0_EXT_IP_SHIFT 0
931#define I40E_TXD_CTX_QW0_EXT_IP_MASK (0x3ULL << \
932 I40E_TXD_CTX_QW0_EXT_IP_SHIFT)
933
934enum i40e_tx_ctx_desc_eipt_offload {
935 I40E_TX_CTX_EXT_IP_NONE = 0x0,
936 I40E_TX_CTX_EXT_IP_IPV6 = 0x1,
937 I40E_TX_CTX_EXT_IP_IPV4_NO_CSUM = 0x2,
938 I40E_TX_CTX_EXT_IP_IPV4 = 0x3
939};
940
941#define I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT 2
942#define I40E_TXD_CTX_QW0_EXT_IPLEN_MASK (0x3FULL << \
943 I40E_TXD_CTX_QW0_EXT_IPLEN_SHIFT)
944
945#define I40E_TXD_CTX_QW0_NATT_SHIFT 9
946#define I40E_TXD_CTX_QW0_NATT_MASK (0x3ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
947
Jesse Brandeburg41a1d042015-06-04 16:24:02 -0400948#define I40E_TXD_CTX_UDP_TUNNELING BIT_ULL(I40E_TXD_CTX_QW0_NATT_SHIFT)
Greg Rosed358aa92013-12-21 06:13:11 +0000949#define I40E_TXD_CTX_GRE_TUNNELING (0x2ULL << I40E_TXD_CTX_QW0_NATT_SHIFT)
950
951#define I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT 11
Jesse Brandeburg41a1d042015-06-04 16:24:02 -0400952#define I40E_TXD_CTX_QW0_EIP_NOINC_MASK \
953 BIT_ULL(I40E_TXD_CTX_QW0_EIP_NOINC_SHIFT)
Greg Rosed358aa92013-12-21 06:13:11 +0000954
955#define I40E_TXD_CTX_EIP_NOINC_IPID_CONST I40E_TXD_CTX_QW0_EIP_NOINC_MASK
956
957#define I40E_TXD_CTX_QW0_NATLEN_SHIFT 12
958#define I40E_TXD_CTX_QW0_NATLEN_MASK (0X7FULL << \
959 I40E_TXD_CTX_QW0_NATLEN_SHIFT)
960
961#define I40E_TXD_CTX_QW0_DECTTL_SHIFT 19
962#define I40E_TXD_CTX_QW0_DECTTL_MASK (0xFULL << \
963 I40E_TXD_CTX_QW0_DECTTL_SHIFT)
964
Anjali Singhai Jain527274c2015-06-05 12:20:31 -0400965#define I40E_TXD_CTX_QW0_L4T_CS_SHIFT 23
966#define I40E_TXD_CTX_QW0_L4T_CS_MASK BIT_ULL(I40E_TXD_CTX_QW0_L4T_CS_SHIFT)
Greg Rosed358aa92013-12-21 06:13:11 +0000967struct i40e_filter_program_desc {
968 __le32 qindex_flex_ptype_vsi;
969 __le32 rsvd;
970 __le32 dtype_cmd_cntindex;
971 __le32 fd_id;
972};
973#define I40E_TXD_FLTR_QW0_QINDEX_SHIFT 0
974#define I40E_TXD_FLTR_QW0_QINDEX_MASK (0x7FFUL << \
975 I40E_TXD_FLTR_QW0_QINDEX_SHIFT)
976#define I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT 11
977#define I40E_TXD_FLTR_QW0_FLEXOFF_MASK (0x7UL << \
978 I40E_TXD_FLTR_QW0_FLEXOFF_SHIFT)
979#define I40E_TXD_FLTR_QW0_PCTYPE_SHIFT 17
980#define I40E_TXD_FLTR_QW0_PCTYPE_MASK (0x3FUL << \
981 I40E_TXD_FLTR_QW0_PCTYPE_SHIFT)
982
983/* Packet Classifier Types for filters */
984enum i40e_filter_pctype {
Anjali Singhai Jaine25d00b2015-06-23 19:00:04 -0400985 /* Note: Values 0-28 are reserved for future use.
986 * Value 29, 30, 32 are not supported on XL710 and X710.
987 */
988 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV4_UDP = 29,
989 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV4_UDP = 30,
Greg Rosed358aa92013-12-21 06:13:11 +0000990 I40E_FILTER_PCTYPE_NONF_IPV4_UDP = 31,
Anjali Singhai Jaine25d00b2015-06-23 19:00:04 -0400991 I40E_FILTER_PCTYPE_NONF_IPV4_TCP_SYN_NO_ACK = 32,
Greg Rosed358aa92013-12-21 06:13:11 +0000992 I40E_FILTER_PCTYPE_NONF_IPV4_TCP = 33,
993 I40E_FILTER_PCTYPE_NONF_IPV4_SCTP = 34,
994 I40E_FILTER_PCTYPE_NONF_IPV4_OTHER = 35,
995 I40E_FILTER_PCTYPE_FRAG_IPV4 = 36,
Anjali Singhai Jaine25d00b2015-06-23 19:00:04 -0400996 /* Note: Values 37-38 are reserved for future use.
997 * Value 39, 40, 42 are not supported on XL710 and X710.
998 */
999 I40E_FILTER_PCTYPE_NONF_UNICAST_IPV6_UDP = 39,
1000 I40E_FILTER_PCTYPE_NONF_MULTICAST_IPV6_UDP = 40,
Greg Rosed358aa92013-12-21 06:13:11 +00001001 I40E_FILTER_PCTYPE_NONF_IPV6_UDP = 41,
Anjali Singhai Jaine25d00b2015-06-23 19:00:04 -04001002 I40E_FILTER_PCTYPE_NONF_IPV6_TCP_SYN_NO_ACK = 42,
Greg Rosed358aa92013-12-21 06:13:11 +00001003 I40E_FILTER_PCTYPE_NONF_IPV6_TCP = 43,
1004 I40E_FILTER_PCTYPE_NONF_IPV6_SCTP = 44,
1005 I40E_FILTER_PCTYPE_NONF_IPV6_OTHER = 45,
1006 I40E_FILTER_PCTYPE_FRAG_IPV6 = 46,
1007 /* Note: Value 47 is reserved for future use */
1008 I40E_FILTER_PCTYPE_FCOE_OX = 48,
1009 I40E_FILTER_PCTYPE_FCOE_RX = 49,
1010 I40E_FILTER_PCTYPE_FCOE_OTHER = 50,
1011 /* Note: Values 51-62 are reserved for future use */
1012 I40E_FILTER_PCTYPE_L2_PAYLOAD = 63,
1013};
1014
1015enum i40e_filter_program_desc_dest {
1016 I40E_FILTER_PROGRAM_DESC_DEST_DROP_PACKET = 0x0,
1017 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_QINDEX = 0x1,
1018 I40E_FILTER_PROGRAM_DESC_DEST_DIRECT_PACKET_OTHER = 0x2,
1019};
1020
1021enum i40e_filter_program_desc_fd_status {
1022 I40E_FILTER_PROGRAM_DESC_FD_STATUS_NONE = 0x0,
1023 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID = 0x1,
1024 I40E_FILTER_PROGRAM_DESC_FD_STATUS_FD_ID_4FLEX_BYTES = 0x2,
1025 I40E_FILTER_PROGRAM_DESC_FD_STATUS_8FLEX_BYTES = 0x3,
1026};
1027
1028#define I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT 23
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001029#define I40E_TXD_FLTR_QW0_DEST_VSI_MASK \
1030 BIT_ULL(I40E_TXD_FLTR_QW0_DEST_VSI_SHIFT)
Greg Rosed358aa92013-12-21 06:13:11 +00001031
1032#define I40E_TXD_FLTR_QW1_CMD_SHIFT 4
1033#define I40E_TXD_FLTR_QW1_CMD_MASK (0xFFFFULL << \
1034 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1035
1036#define I40E_TXD_FLTR_QW1_PCMD_SHIFT (0x0ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1037#define I40E_TXD_FLTR_QW1_PCMD_MASK (0x7ULL << I40E_TXD_FLTR_QW1_PCMD_SHIFT)
1038
1039enum i40e_filter_program_desc_pcmd {
1040 I40E_FILTER_PROGRAM_DESC_PCMD_ADD_UPDATE = 0x1,
1041 I40E_FILTER_PROGRAM_DESC_PCMD_REMOVE = 0x2,
1042};
1043
1044#define I40E_TXD_FLTR_QW1_DEST_SHIFT (0x3ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
1045#define I40E_TXD_FLTR_QW1_DEST_MASK (0x3ULL << I40E_TXD_FLTR_QW1_DEST_SHIFT)
1046
1047#define I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT (0x7ULL + I40E_TXD_FLTR_QW1_CMD_SHIFT)
Jesse Brandeburg41a1d042015-06-04 16:24:02 -04001048#define I40E_TXD_FLTR_QW1_CNT_ENA_MASK BIT_ULL(I40E_TXD_FLTR_QW1_CNT_ENA_SHIFT)
Greg Rosed358aa92013-12-21 06:13:11 +00001049
1050#define I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT (0x9ULL + \
1051 I40E_TXD_FLTR_QW1_CMD_SHIFT)
1052#define I40E_TXD_FLTR_QW1_FD_STATUS_MASK (0x3ULL << \
1053 I40E_TXD_FLTR_QW1_FD_STATUS_SHIFT)
1054
1055#define I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT 20
1056#define I40E_TXD_FLTR_QW1_CNTINDEX_MASK (0x1FFUL << \
1057 I40E_TXD_FLTR_QW1_CNTINDEX_SHIFT)
1058
1059enum i40e_filter_type {
1060 I40E_FLOW_DIRECTOR_FLTR = 0,
1061 I40E_PE_QUAD_HASH_FLTR = 1,
1062 I40E_ETHERTYPE_FLTR,
1063 I40E_FCOE_CTX_FLTR,
1064 I40E_MAC_VLAN_FLTR,
1065 I40E_HASH_FLTR
1066};
1067
1068struct i40e_vsi_context {
1069 u16 seid;
1070 u16 uplink_seid;
1071 u16 vsi_number;
1072 u16 vsis_allocated;
1073 u16 vsis_unallocated;
1074 u16 flags;
1075 u8 pf_num;
1076 u8 vf_num;
1077 u8 connection_type;
1078 struct i40e_aqc_vsi_properties_data info;
1079};
1080
Kamil Krawczyk4f4e17b2014-04-23 04:50:14 +00001081struct i40e_veb_context {
1082 u16 seid;
1083 u16 uplink_seid;
1084 u16 veb_number;
1085 u16 vebs_allocated;
1086 u16 vebs_unallocated;
1087 u16 flags;
1088 struct i40e_aqc_get_veb_parameters_completion info;
1089};
1090
Greg Rosed358aa92013-12-21 06:13:11 +00001091/* Statistics collected by each port, VSI, VEB, and S-channel */
1092struct i40e_eth_stats {
1093 u64 rx_bytes; /* gorc */
1094 u64 rx_unicast; /* uprc */
1095 u64 rx_multicast; /* mprc */
1096 u64 rx_broadcast; /* bprc */
1097 u64 rx_discards; /* rdpc */
Greg Rosed358aa92013-12-21 06:13:11 +00001098 u64 rx_unknown_protocol; /* rupp */
1099 u64 tx_bytes; /* gotc */
1100 u64 tx_unicast; /* uptc */
1101 u64 tx_multicast; /* mptc */
1102 u64 tx_broadcast; /* bptc */
1103 u64 tx_discards; /* tdpc */
1104 u64 tx_errors; /* tepc */
1105};
1106
Neerav Parikhfe860af2015-07-10 19:36:02 -04001107/* Statistics collected per VEB per TC */
1108struct i40e_veb_tc_stats {
1109 u64 tc_rx_packets[I40E_MAX_TRAFFIC_CLASS];
1110 u64 tc_rx_bytes[I40E_MAX_TRAFFIC_CLASS];
1111 u64 tc_tx_packets[I40E_MAX_TRAFFIC_CLASS];
1112 u64 tc_tx_bytes[I40E_MAX_TRAFFIC_CLASS];
1113};
1114
Greg Rosed358aa92013-12-21 06:13:11 +00001115/* Statistics collected by the MAC */
1116struct i40e_hw_port_stats {
1117 /* eth stats collected by the port */
1118 struct i40e_eth_stats eth;
1119
1120 /* additional port specific stats */
1121 u64 tx_dropped_link_down; /* tdold */
1122 u64 crc_errors; /* crcerrs */
1123 u64 illegal_bytes; /* illerrc */
1124 u64 error_bytes; /* errbc */
1125 u64 mac_local_faults; /* mlfc */
1126 u64 mac_remote_faults; /* mrfc */
1127 u64 rx_length_errors; /* rlec */
1128 u64 link_xon_rx; /* lxonrxc */
1129 u64 link_xoff_rx; /* lxoffrxc */
1130 u64 priority_xon_rx[8]; /* pxonrxc[8] */
1131 u64 priority_xoff_rx[8]; /* pxoffrxc[8] */
1132 u64 link_xon_tx; /* lxontxc */
1133 u64 link_xoff_tx; /* lxofftxc */
1134 u64 priority_xon_tx[8]; /* pxontxc[8] */
1135 u64 priority_xoff_tx[8]; /* pxofftxc[8] */
1136 u64 priority_xon_2_xoff[8]; /* pxon2offc[8] */
1137 u64 rx_size_64; /* prc64 */
1138 u64 rx_size_127; /* prc127 */
1139 u64 rx_size_255; /* prc255 */
1140 u64 rx_size_511; /* prc511 */
1141 u64 rx_size_1023; /* prc1023 */
1142 u64 rx_size_1522; /* prc1522 */
1143 u64 rx_size_big; /* prc9522 */
1144 u64 rx_undersize; /* ruc */
1145 u64 rx_fragments; /* rfc */
1146 u64 rx_oversize; /* roc */
1147 u64 rx_jabber; /* rjc */
1148 u64 tx_size_64; /* ptc64 */
1149 u64 tx_size_127; /* ptc127 */
1150 u64 tx_size_255; /* ptc255 */
1151 u64 tx_size_511; /* ptc511 */
1152 u64 tx_size_1023; /* ptc1023 */
1153 u64 tx_size_1522; /* ptc1522 */
1154 u64 tx_size_big; /* ptc9522 */
1155 u64 mac_short_packet_dropped; /* mspdc */
1156 u64 checksum_error; /* xec */
Anjali Singhai Jain433c47d2014-05-22 06:32:17 +00001157 /* flow director stats */
1158 u64 fd_atr_match;
1159 u64 fd_sb_match;
Anjali Singhai Jain60ccd452015-04-16 20:06:01 -04001160 u64 fd_atr_tunnel_match;
Anjali Singhai Jaind0389e52015-04-22 19:34:05 -04001161 u32 fd_atr_status;
1162 u32 fd_sb_status;
Anjali Singhai Jainbee5af72014-03-06 08:59:50 +00001163 /* EEE LPI */
Greg Rose10bc4782014-04-09 05:59:03 +00001164 u32 tx_lpi_status;
1165 u32 rx_lpi_status;
Anjali Singhai Jainbee5af72014-03-06 08:59:50 +00001166 u64 tx_lpi_count; /* etlpic */
1167 u64 rx_lpi_count; /* erlpic */
Greg Rosed358aa92013-12-21 06:13:11 +00001168};
1169
1170/* Checksum and Shadow RAM pointers */
1171#define I40E_SR_NVM_CONTROL_WORD 0x00
1172#define I40E_SR_EMP_MODULE_PTR 0x0F
Shannon Nelson4f651a52015-02-26 16:12:26 +00001173#define I40E_SR_NVM_DEV_STARTER_VERSION 0x18
Greg Rosed358aa92013-12-21 06:13:11 +00001174#define I40E_SR_NVM_WAKE_ON_LAN 0x19
1175#define I40E_SR_ALTERNATE_SAN_MAC_ADDRESS_PTR 0x27
1176#define I40E_SR_NVM_EETRACK_LO 0x2D
1177#define I40E_SR_NVM_EETRACK_HI 0x2E
1178#define I40E_SR_VPD_PTR 0x2F
1179#define I40E_SR_PCIE_ALT_AUTO_LOAD_PTR 0x3E
1180#define I40E_SR_SW_CHECKSUM_WORD 0x3F
1181
1182/* Auxiliary field, mask and shift definition for Shadow RAM and NVM Flash */
1183#define I40E_SR_VPD_MODULE_MAX_SIZE 1024
1184#define I40E_SR_PCIE_ALT_MODULE_MAX_SIZE 1024
1185#define I40E_SR_CONTROL_WORD_1_SHIFT 0x06
1186#define I40E_SR_CONTROL_WORD_1_MASK (0x03 << I40E_SR_CONTROL_WORD_1_SHIFT)
1187
1188/* Shadow RAM related */
1189#define I40E_SR_SECTOR_SIZE_IN_WORDS 0x800
1190#define I40E_SR_WORDS_IN_1KB 512
1191/* Checksum should be calculated such that after adding all the words,
1192 * including the checksum word itself, the sum should be 0xBABA.
1193 */
1194#define I40E_SR_SW_CHECKSUM_BASE 0xBABA
1195
1196#define I40E_SRRD_SRCTL_ATTEMPTS 100000
1197
1198enum i40e_switch_element_types {
1199 I40E_SWITCH_ELEMENT_TYPE_MAC = 1,
1200 I40E_SWITCH_ELEMENT_TYPE_PF = 2,
1201 I40E_SWITCH_ELEMENT_TYPE_VF = 3,
1202 I40E_SWITCH_ELEMENT_TYPE_EMP = 4,
1203 I40E_SWITCH_ELEMENT_TYPE_BMC = 6,
1204 I40E_SWITCH_ELEMENT_TYPE_PE = 16,
1205 I40E_SWITCH_ELEMENT_TYPE_VEB = 17,
1206 I40E_SWITCH_ELEMENT_TYPE_PA = 18,
1207 I40E_SWITCH_ELEMENT_TYPE_VSI = 19,
1208};
1209
1210/* Supported EtherType filters */
1211enum i40e_ether_type_index {
1212 I40E_ETHER_TYPE_1588 = 0,
1213 I40E_ETHER_TYPE_FIP = 1,
1214 I40E_ETHER_TYPE_OUI_EXTENDED = 2,
1215 I40E_ETHER_TYPE_MAC_CONTROL = 3,
1216 I40E_ETHER_TYPE_LLDP = 4,
1217 I40E_ETHER_TYPE_EVB_PROTOCOL1 = 5,
1218 I40E_ETHER_TYPE_EVB_PROTOCOL2 = 6,
1219 I40E_ETHER_TYPE_QCN_CNM = 7,
1220 I40E_ETHER_TYPE_8021X = 8,
1221 I40E_ETHER_TYPE_ARP = 9,
1222 I40E_ETHER_TYPE_RSV1 = 10,
1223 I40E_ETHER_TYPE_RSV2 = 11,
1224};
1225
1226/* Filter context base size is 1K */
1227#define I40E_HASH_FILTER_BASE_SIZE 1024
1228/* Supported Hash filter values */
1229enum i40e_hash_filter_size {
1230 I40E_HASH_FILTER_SIZE_1K = 0,
1231 I40E_HASH_FILTER_SIZE_2K = 1,
1232 I40E_HASH_FILTER_SIZE_4K = 2,
1233 I40E_HASH_FILTER_SIZE_8K = 3,
1234 I40E_HASH_FILTER_SIZE_16K = 4,
1235 I40E_HASH_FILTER_SIZE_32K = 5,
1236 I40E_HASH_FILTER_SIZE_64K = 6,
1237 I40E_HASH_FILTER_SIZE_128K = 7,
1238 I40E_HASH_FILTER_SIZE_256K = 8,
1239 I40E_HASH_FILTER_SIZE_512K = 9,
1240 I40E_HASH_FILTER_SIZE_1M = 10,
1241};
1242
1243/* DMA context base size is 0.5K */
1244#define I40E_DMA_CNTX_BASE_SIZE 512
1245/* Supported DMA context values */
1246enum i40e_dma_cntx_size {
1247 I40E_DMA_CNTX_SIZE_512 = 0,
1248 I40E_DMA_CNTX_SIZE_1K = 1,
1249 I40E_DMA_CNTX_SIZE_2K = 2,
1250 I40E_DMA_CNTX_SIZE_4K = 3,
1251 I40E_DMA_CNTX_SIZE_8K = 4,
1252 I40E_DMA_CNTX_SIZE_16K = 5,
1253 I40E_DMA_CNTX_SIZE_32K = 6,
1254 I40E_DMA_CNTX_SIZE_64K = 7,
1255 I40E_DMA_CNTX_SIZE_128K = 8,
1256 I40E_DMA_CNTX_SIZE_256K = 9,
1257};
1258
1259/* Supported Hash look up table (LUT) sizes */
1260enum i40e_hash_lut_size {
1261 I40E_HASH_LUT_SIZE_128 = 0,
1262 I40E_HASH_LUT_SIZE_512 = 1,
1263};
1264
1265/* Structure to hold a per PF filter control settings */
1266struct i40e_filter_control_settings {
1267 /* number of PE Quad Hash filter buckets */
1268 enum i40e_hash_filter_size pe_filt_num;
1269 /* number of PE Quad Hash contexts */
1270 enum i40e_dma_cntx_size pe_cntx_num;
1271 /* number of FCoE filter buckets */
1272 enum i40e_hash_filter_size fcoe_filt_num;
1273 /* number of FCoE DDP contexts */
1274 enum i40e_dma_cntx_size fcoe_cntx_num;
1275 /* size of the Hash LUT */
1276 enum i40e_hash_lut_size hash_lut_size;
1277 /* enable FDIR filters for PF and its VFs */
1278 bool enable_fdir;
1279 /* enable Ethertype filters for PF and its VFs */
1280 bool enable_ethtype;
1281 /* enable MAC/VLAN filters for PF and its VFs */
1282 bool enable_macvlan;
1283};
1284
1285/* Structure to hold device level control filter counts */
1286struct i40e_control_filter_stats {
1287 u16 mac_etype_used; /* Used perfect match MAC/EtherType filters */
1288 u16 etype_used; /* Used perfect EtherType filters */
1289 u16 mac_etype_free; /* Un-used perfect match MAC/EtherType filters */
1290 u16 etype_free; /* Un-used perfect EtherType filters */
1291};
1292
1293enum i40e_reset_type {
1294 I40E_RESET_POR = 0,
1295 I40E_RESET_CORER = 1,
1296 I40E_RESET_GLOBR = 2,
1297 I40E_RESET_EMPR = 3,
1298};
Carolyn Wybornye157ea32014-06-03 23:50:22 +00001299
1300/* RSS Hash Table Size */
1301#define I40E_PFQF_CTL_0_HASHLUTSIZE_512 0x00010000
Greg Rosed358aa92013-12-21 06:13:11 +00001302#endif /* _I40E_TYPE_H_ */