blob: 88f470f0d820ae5d599f09bf0452351bab203217 [file] [log] [blame]
Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
4 * Copyright (C) 2007 Freescale Semiconductor, Inc. All rights reserved.
5 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
13 * The support for MPC8349 DMA contorller is also added.
14 *
Ira W. Snydera7aea372009-04-23 16:17:54 -070015 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
Zhang Wei173acc72008-03-01 07:42:48 -070020 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Zhang Wei173acc72008-03-01 07:42:48 -070031#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
36#include <linux/of_platform.h>
37
Ira Snyderbbea0b62009-09-08 17:53:04 -070038#include <asm/fsldma.h>
Zhang Wei173acc72008-03-01 07:42:48 -070039#include "fsldma.h"
40
Ira Snydera1c03312010-01-06 13:34:05 +000041static void dma_init(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070042{
43 /* Reset the channel */
Ira Snydera1c03312010-01-06 13:34:05 +000044 DMA_OUT(chan, &chan->regs->mr, 0, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070045
Ira Snydera1c03312010-01-06 13:34:05 +000046 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -070047 case FSL_DMA_IP_85XX:
48 /* Set the channel to below modes:
49 * EIE - Error interrupt enable
50 * EOSIE - End of segments interrupt enable (basic mode)
51 * EOLNIE - End of links interrupt enable
52 */
Ira Snydera1c03312010-01-06 13:34:05 +000053 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EIE
Zhang Wei173acc72008-03-01 07:42:48 -070054 | FSL_DMA_MR_EOLNIE | FSL_DMA_MR_EOSIE, 32);
55 break;
56 case FSL_DMA_IP_83XX:
57 /* Set the channel to below modes:
58 * EOTIE - End-of-transfer interrupt enable
Ira W. Snydera7aea372009-04-23 16:17:54 -070059 * PRC_RM - PCI read multiple
Zhang Wei173acc72008-03-01 07:42:48 -070060 */
Ira Snydera1c03312010-01-06 13:34:05 +000061 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
Ira W. Snydera7aea372009-04-23 16:17:54 -070062 | FSL_DMA_MR_PRC_RM, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070063 break;
64 }
Zhang Wei173acc72008-03-01 07:42:48 -070065}
66
Ira Snydera1c03312010-01-06 13:34:05 +000067static void set_sr(struct fsldma_chan *chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070068{
Ira Snydera1c03312010-01-06 13:34:05 +000069 DMA_OUT(chan, &chan->regs->sr, val, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070070}
71
Ira Snydera1c03312010-01-06 13:34:05 +000072static u32 get_sr(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070073{
Ira Snydera1c03312010-01-06 13:34:05 +000074 return DMA_IN(chan, &chan->regs->sr, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070075}
76
Ira Snydera1c03312010-01-06 13:34:05 +000077static void set_desc_cnt(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -070078 struct fsl_dma_ld_hw *hw, u32 count)
79{
Ira Snydera1c03312010-01-06 13:34:05 +000080 hw->count = CPU_TO_DMA(chan, count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070081}
82
Ira Snydera1c03312010-01-06 13:34:05 +000083static void set_desc_src(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -070084 struct fsl_dma_ld_hw *hw, dma_addr_t src)
85{
86 u64 snoop_bits;
87
Ira Snydera1c03312010-01-06 13:34:05 +000088 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
Zhang Wei173acc72008-03-01 07:42:48 -070089 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
Ira Snydera1c03312010-01-06 13:34:05 +000090 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070091}
92
Ira Snydera1c03312010-01-06 13:34:05 +000093static void set_desc_dst(struct fsldma_chan *chan,
Ira Snyder738f5f72010-01-06 13:34:02 +000094 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
Zhang Wei173acc72008-03-01 07:42:48 -070095{
96 u64 snoop_bits;
97
Ira Snydera1c03312010-01-06 13:34:05 +000098 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
Zhang Wei173acc72008-03-01 07:42:48 -070099 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
Ira Snydera1c03312010-01-06 13:34:05 +0000100 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700101}
102
Ira Snydera1c03312010-01-06 13:34:05 +0000103static void set_desc_next(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -0700104 struct fsl_dma_ld_hw *hw, dma_addr_t next)
105{
106 u64 snoop_bits;
107
Ira Snydera1c03312010-01-06 13:34:05 +0000108 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Zhang Wei173acc72008-03-01 07:42:48 -0700109 ? FSL_DMA_SNEN : 0;
Ira Snydera1c03312010-01-06 13:34:05 +0000110 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700111}
112
Ira Snydera1c03312010-01-06 13:34:05 +0000113static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
Zhang Wei173acc72008-03-01 07:42:48 -0700114{
Ira Snydera1c03312010-01-06 13:34:05 +0000115 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700116}
117
Ira Snydera1c03312010-01-06 13:34:05 +0000118static dma_addr_t get_cdar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700119{
Ira Snydera1c03312010-01-06 13:34:05 +0000120 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
Zhang Wei173acc72008-03-01 07:42:48 -0700121}
122
Ira Snydera1c03312010-01-06 13:34:05 +0000123static dma_addr_t get_ndar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700124{
Ira Snydera1c03312010-01-06 13:34:05 +0000125 return DMA_IN(chan, &chan->regs->ndar, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700126}
127
Ira Snydera1c03312010-01-06 13:34:05 +0000128static u32 get_bcr(struct fsldma_chan *chan)
Zhang Weif79abb62008-03-18 18:45:00 -0700129{
Ira Snydera1c03312010-01-06 13:34:05 +0000130 return DMA_IN(chan, &chan->regs->bcr, 32);
Zhang Weif79abb62008-03-18 18:45:00 -0700131}
132
Ira Snydera1c03312010-01-06 13:34:05 +0000133static int dma_is_idle(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700134{
Ira Snydera1c03312010-01-06 13:34:05 +0000135 u32 sr = get_sr(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700136 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
137}
138
Ira Snydera1c03312010-01-06 13:34:05 +0000139static void dma_start(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700140{
Ira Snyder272ca652010-01-06 13:33:59 +0000141 u32 mode;
Zhang Wei173acc72008-03-01 07:42:48 -0700142
Ira Snydera1c03312010-01-06 13:34:05 +0000143 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000144
Ira Snydera1c03312010-01-06 13:34:05 +0000145 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
146 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
147 DMA_OUT(chan, &chan->regs->bcr, 0, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000148 mode |= FSL_DMA_MR_EMP_EN;
149 } else {
150 mode &= ~FSL_DMA_MR_EMP_EN;
151 }
Ira Snyder43a1a3e2009-05-28 09:26:40 +0000152 }
Zhang Wei173acc72008-03-01 07:42:48 -0700153
Ira Snydera1c03312010-01-06 13:34:05 +0000154 if (chan->feature & FSL_DMA_CHAN_START_EXT)
Ira Snyder272ca652010-01-06 13:33:59 +0000155 mode |= FSL_DMA_MR_EMS_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700156 else
Ira Snyder272ca652010-01-06 13:33:59 +0000157 mode |= FSL_DMA_MR_CS;
Zhang Wei173acc72008-03-01 07:42:48 -0700158
Ira Snydera1c03312010-01-06 13:34:05 +0000159 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700160}
161
Ira Snydera1c03312010-01-06 13:34:05 +0000162static void dma_halt(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700163{
Ira Snyder272ca652010-01-06 13:33:59 +0000164 u32 mode;
Dan Williams900325a2009-03-02 15:33:46 -0700165 int i;
166
Ira Snydera1c03312010-01-06 13:34:05 +0000167 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000168 mode |= FSL_DMA_MR_CA;
Ira Snydera1c03312010-01-06 13:34:05 +0000169 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000170
171 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN | FSL_DMA_MR_CA);
Ira Snydera1c03312010-01-06 13:34:05 +0000172 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700173
Dan Williams900325a2009-03-02 15:33:46 -0700174 for (i = 0; i < 100; i++) {
Ira Snydera1c03312010-01-06 13:34:05 +0000175 if (dma_is_idle(chan))
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000176 return;
177
Zhang Wei173acc72008-03-01 07:42:48 -0700178 udelay(10);
Dan Williams900325a2009-03-02 15:33:46 -0700179 }
Ira Snyder272ca652010-01-06 13:33:59 +0000180
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000181 if (!dma_is_idle(chan))
Ira Snydera1c03312010-01-06 13:34:05 +0000182 dev_err(chan->dev, "DMA halt timeout!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700183}
184
Ira Snydera1c03312010-01-06 13:34:05 +0000185static void set_ld_eol(struct fsldma_chan *chan,
Zhang Wei173acc72008-03-01 07:42:48 -0700186 struct fsl_desc_sw *desc)
187{
Ira Snyder776c8942009-05-15 11:33:20 -0700188 u64 snoop_bits;
189
Ira Snydera1c03312010-01-06 13:34:05 +0000190 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Ira Snyder776c8942009-05-15 11:33:20 -0700191 ? FSL_DMA_SNEN : 0;
192
Ira Snydera1c03312010-01-06 13:34:05 +0000193 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
194 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
Ira Snyder776c8942009-05-15 11:33:20 -0700195 | snoop_bits, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700196}
197
Zhang Wei173acc72008-03-01 07:42:48 -0700198/**
199 * fsl_chan_set_src_loop_size - Set source address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000200 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700201 * @size : Address loop size, 0 for disable loop
202 *
203 * The set source address hold transfer size. The source
204 * address hold or loop transfer size is when the DMA transfer
205 * data from source address (SA), if the loop size is 4, the DMA will
206 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
207 * SA + 1 ... and so on.
208 */
Ira Snydera1c03312010-01-06 13:34:05 +0000209static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700210{
Ira Snyder272ca652010-01-06 13:33:59 +0000211 u32 mode;
212
Ira Snydera1c03312010-01-06 13:34:05 +0000213 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000214
Zhang Wei173acc72008-03-01 07:42:48 -0700215 switch (size) {
216 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000217 mode &= ~FSL_DMA_MR_SAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700218 break;
219 case 1:
220 case 2:
221 case 4:
222 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000223 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
Zhang Wei173acc72008-03-01 07:42:48 -0700224 break;
225 }
Ira Snyder272ca652010-01-06 13:33:59 +0000226
Ira Snydera1c03312010-01-06 13:34:05 +0000227 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700228}
229
230/**
Ira Snyder738f5f72010-01-06 13:34:02 +0000231 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000232 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700233 * @size : Address loop size, 0 for disable loop
234 *
235 * The set destination address hold transfer size. The destination
236 * address hold or loop transfer size is when the DMA transfer
237 * data to destination address (TA), if the loop size is 4, the DMA will
238 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
239 * TA + 1 ... and so on.
240 */
Ira Snydera1c03312010-01-06 13:34:05 +0000241static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700242{
Ira Snyder272ca652010-01-06 13:33:59 +0000243 u32 mode;
244
Ira Snydera1c03312010-01-06 13:34:05 +0000245 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000246
Zhang Wei173acc72008-03-01 07:42:48 -0700247 switch (size) {
248 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000249 mode &= ~FSL_DMA_MR_DAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700250 break;
251 case 1:
252 case 2:
253 case 4:
254 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000255 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
Zhang Wei173acc72008-03-01 07:42:48 -0700256 break;
257 }
Ira Snyder272ca652010-01-06 13:33:59 +0000258
Ira Snydera1c03312010-01-06 13:34:05 +0000259 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700260}
261
262/**
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700263 * fsl_chan_set_request_count - Set DMA Request Count for external control
Ira Snydera1c03312010-01-06 13:34:05 +0000264 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700265 * @size : Number of bytes to transfer in a single request
266 *
267 * The Freescale DMA channel can be controlled by the external signal DREQ#.
268 * The DMA request count is how many bytes are allowed to transfer before
269 * pausing the channel, after which a new assertion of DREQ# resumes channel
270 * operation.
271 *
272 * A size of 0 disables external pause control. The maximum size is 1024.
273 */
Ira Snydera1c03312010-01-06 13:34:05 +0000274static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700275{
Ira Snyder272ca652010-01-06 13:33:59 +0000276 u32 mode;
277
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700278 BUG_ON(size > 1024);
Ira Snyder272ca652010-01-06 13:33:59 +0000279
Ira Snydera1c03312010-01-06 13:34:05 +0000280 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000281 mode |= (__ilog2(size) << 24) & 0x0f000000;
282
Ira Snydera1c03312010-01-06 13:34:05 +0000283 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700284}
285
286/**
Zhang Wei173acc72008-03-01 07:42:48 -0700287 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
Ira Snydera1c03312010-01-06 13:34:05 +0000288 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700289 * @enable : 0 is disabled, 1 is enabled.
Zhang Wei173acc72008-03-01 07:42:48 -0700290 *
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700291 * The Freescale DMA channel can be controlled by the external signal DREQ#.
292 * The DMA Request Count feature should be used in addition to this feature
293 * to set the number of bytes to transfer before pausing the channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700294 */
Ira Snydera1c03312010-01-06 13:34:05 +0000295static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700296{
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700297 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000298 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700299 else
Ira Snydera1c03312010-01-06 13:34:05 +0000300 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700301}
302
303/**
304 * fsl_chan_toggle_ext_start - Toggle channel external start status
Ira Snydera1c03312010-01-06 13:34:05 +0000305 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700306 * @enable : 0 is disabled, 1 is enabled.
307 *
308 * If enable the external start, the channel can be started by an
309 * external DMA start pin. So the dma_start() does not start the
310 * transfer immediately. The DMA channel will wait for the
311 * control pin asserted.
312 */
Ira Snydera1c03312010-01-06 13:34:05 +0000313static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700314{
315 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000316 chan->feature |= FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700317 else
Ira Snydera1c03312010-01-06 13:34:05 +0000318 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700319}
320
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000321static void append_ld_queue(struct fsldma_chan *chan,
322 struct fsl_desc_sw *desc)
323{
324 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
325
326 if (list_empty(&chan->ld_pending))
327 goto out_splice;
328
329 /*
330 * Add the hardware descriptor to the chain of hardware descriptors
331 * that already exists in memory.
332 *
333 * This will un-set the EOL bit of the existing transaction, and the
334 * last link in this transaction will become the EOL descriptor.
335 */
336 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
337
338 /*
339 * Add the software descriptor and all children to the list
340 * of pending transactions
341 */
342out_splice:
343 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
344}
345
Zhang Wei173acc72008-03-01 07:42:48 -0700346static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
347{
Ira Snydera1c03312010-01-06 13:34:05 +0000348 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
Dan Williamseda34232009-09-08 17:53:02 -0700349 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
350 struct fsl_desc_sw *child;
Zhang Wei173acc72008-03-01 07:42:48 -0700351 unsigned long flags;
352 dma_cookie_t cookie;
353
Ira Snydera1c03312010-01-06 13:34:05 +0000354 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700355
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000356 /*
357 * assign cookies to all of the software descriptors
358 * that make up this transaction
359 */
Ira Snydera1c03312010-01-06 13:34:05 +0000360 cookie = chan->common.cookie;
Dan Williamseda34232009-09-08 17:53:02 -0700361 list_for_each_entry(child, &desc->tx_list, node) {
Ira Snyderbcfb7462009-05-15 14:27:16 -0700362 cookie++;
363 if (cookie < 0)
364 cookie = 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700365
Steven J. Magnani6ca3a7a2010-02-25 13:39:30 -0600366 child->async_tx.cookie = cookie;
Ira Snyderbcfb7462009-05-15 14:27:16 -0700367 }
368
Ira Snydera1c03312010-01-06 13:34:05 +0000369 chan->common.cookie = cookie;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000370
371 /* put this transaction onto the tail of the pending queue */
Ira Snydera1c03312010-01-06 13:34:05 +0000372 append_ld_queue(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700373
Ira Snydera1c03312010-01-06 13:34:05 +0000374 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700375
376 return cookie;
377}
378
379/**
380 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
Ira Snydera1c03312010-01-06 13:34:05 +0000381 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700382 *
383 * Return - The descriptor allocated. NULL for failed.
384 */
385static struct fsl_desc_sw *fsl_dma_alloc_descriptor(
Ira Snydera1c03312010-01-06 13:34:05 +0000386 struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700387{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000388 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700389 dma_addr_t pdesc;
Zhang Wei173acc72008-03-01 07:42:48 -0700390
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000391 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
392 if (!desc) {
393 dev_dbg(chan->dev, "out of memory for link desc\n");
394 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700395 }
396
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000397 memset(desc, 0, sizeof(*desc));
398 INIT_LIST_HEAD(&desc->tx_list);
399 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
400 desc->async_tx.tx_submit = fsl_dma_tx_submit;
401 desc->async_tx.phys = pdesc;
402
403 return desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700404}
405
406
407/**
408 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000409 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700410 *
411 * This function will create a dma pool for descriptor allocation.
412 *
413 * Return - The number of descriptors allocated.
414 */
Ira Snydera1c03312010-01-06 13:34:05 +0000415static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700416{
Ira Snydera1c03312010-01-06 13:34:05 +0000417 struct fsldma_chan *chan = to_fsl_chan(dchan);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700418
419 /* Has this channel already been allocated? */
Ira Snydera1c03312010-01-06 13:34:05 +0000420 if (chan->desc_pool)
Timur Tabi77cd62e2008-09-26 17:00:11 -0700421 return 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700422
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000423 /*
424 * We need the descriptor to be aligned to 32bytes
Zhang Wei173acc72008-03-01 07:42:48 -0700425 * for meeting FSL DMA specification requirement.
426 */
Ira Snydera1c03312010-01-06 13:34:05 +0000427 chan->desc_pool = dma_pool_create("fsl_dma_engine_desc_pool",
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000428 chan->dev,
429 sizeof(struct fsl_desc_sw),
430 __alignof__(struct fsl_desc_sw), 0);
Ira Snydera1c03312010-01-06 13:34:05 +0000431 if (!chan->desc_pool) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000432 dev_err(chan->dev, "unable to allocate channel %d "
433 "descriptor pool\n", chan->id);
434 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700435 }
436
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000437 /* there is at least one descriptor free to be allocated */
Zhang Wei173acc72008-03-01 07:42:48 -0700438 return 1;
439}
440
441/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000442 * fsldma_free_desc_list - Free all descriptors in a queue
443 * @chan: Freescae DMA channel
444 * @list: the list to free
445 *
446 * LOCKING: must hold chan->desc_lock
447 */
448static void fsldma_free_desc_list(struct fsldma_chan *chan,
449 struct list_head *list)
450{
451 struct fsl_desc_sw *desc, *_desc;
452
453 list_for_each_entry_safe(desc, _desc, list, node) {
454 list_del(&desc->node);
455 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
456 }
457}
458
459static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
460 struct list_head *list)
461{
462 struct fsl_desc_sw *desc, *_desc;
463
464 list_for_each_entry_safe_reverse(desc, _desc, list, node) {
465 list_del(&desc->node);
466 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
467 }
468}
469
470/**
Zhang Wei173acc72008-03-01 07:42:48 -0700471 * fsl_dma_free_chan_resources - Free all resources of the channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000472 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700473 */
Ira Snydera1c03312010-01-06 13:34:05 +0000474static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700475{
Ira Snydera1c03312010-01-06 13:34:05 +0000476 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700477 unsigned long flags;
478
Ira Snydera1c03312010-01-06 13:34:05 +0000479 dev_dbg(chan->dev, "Free all channel resources.\n");
480 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000481 fsldma_free_desc_list(chan, &chan->ld_pending);
482 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snydera1c03312010-01-06 13:34:05 +0000483 spin_unlock_irqrestore(&chan->desc_lock, flags);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700484
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000485 dma_pool_destroy(chan->desc_pool);
Ira Snydera1c03312010-01-06 13:34:05 +0000486 chan->desc_pool = NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700487}
488
Zhang Wei2187c262008-03-13 17:45:28 -0700489static struct dma_async_tx_descriptor *
Ira Snydera1c03312010-01-06 13:34:05 +0000490fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
Zhang Wei2187c262008-03-13 17:45:28 -0700491{
Ira Snydera1c03312010-01-06 13:34:05 +0000492 struct fsldma_chan *chan;
Zhang Wei2187c262008-03-13 17:45:28 -0700493 struct fsl_desc_sw *new;
494
Ira Snydera1c03312010-01-06 13:34:05 +0000495 if (!dchan)
Zhang Wei2187c262008-03-13 17:45:28 -0700496 return NULL;
497
Ira Snydera1c03312010-01-06 13:34:05 +0000498 chan = to_fsl_chan(dchan);
Zhang Wei2187c262008-03-13 17:45:28 -0700499
Ira Snydera1c03312010-01-06 13:34:05 +0000500 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei2187c262008-03-13 17:45:28 -0700501 if (!new) {
Ira Snydera1c03312010-01-06 13:34:05 +0000502 dev_err(chan->dev, "No free memory for link descriptor\n");
Zhang Wei2187c262008-03-13 17:45:28 -0700503 return NULL;
504 }
505
506 new->async_tx.cookie = -EBUSY;
Dan Williams636bdea2008-04-17 20:17:26 -0700507 new->async_tx.flags = flags;
Zhang Wei2187c262008-03-13 17:45:28 -0700508
Zhang Weif79abb62008-03-18 18:45:00 -0700509 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700510 list_add_tail(&new->node, &new->tx_list);
Zhang Weif79abb62008-03-18 18:45:00 -0700511
Zhang Wei2187c262008-03-13 17:45:28 -0700512 /* Set End-of-link to the last link descriptor of new list*/
Ira Snydera1c03312010-01-06 13:34:05 +0000513 set_ld_eol(chan, new);
Zhang Wei2187c262008-03-13 17:45:28 -0700514
515 return &new->async_tx;
516}
517
Zhang Wei173acc72008-03-01 07:42:48 -0700518static struct dma_async_tx_descriptor *fsl_dma_prep_memcpy(
Ira Snydera1c03312010-01-06 13:34:05 +0000519 struct dma_chan *dchan, dma_addr_t dma_dst, dma_addr_t dma_src,
Zhang Wei173acc72008-03-01 07:42:48 -0700520 size_t len, unsigned long flags)
521{
Ira Snydera1c03312010-01-06 13:34:05 +0000522 struct fsldma_chan *chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700523 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
524 size_t copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700525
Ira Snydera1c03312010-01-06 13:34:05 +0000526 if (!dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700527 return NULL;
528
529 if (!len)
530 return NULL;
531
Ira Snydera1c03312010-01-06 13:34:05 +0000532 chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700533
534 do {
535
536 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000537 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700538 if (!new) {
Ira Snydera1c03312010-01-06 13:34:05 +0000539 dev_err(chan->dev,
Zhang Wei173acc72008-03-01 07:42:48 -0700540 "No free memory for link descriptor\n");
Ira Snyder2e077f82009-05-15 09:59:46 -0700541 goto fail;
Zhang Wei173acc72008-03-01 07:42:48 -0700542 }
543#ifdef FSL_DMA_LD_DEBUG
Ira Snydera1c03312010-01-06 13:34:05 +0000544 dev_dbg(chan->dev, "new link desc alloc %p\n", new);
Zhang Wei173acc72008-03-01 07:42:48 -0700545#endif
546
Zhang Wei56822842008-03-13 10:45:27 -0700547 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700548
Ira Snydera1c03312010-01-06 13:34:05 +0000549 set_desc_cnt(chan, &new->hw, copy);
550 set_desc_src(chan, &new->hw, dma_src);
551 set_desc_dst(chan, &new->hw, dma_dst);
Zhang Wei173acc72008-03-01 07:42:48 -0700552
553 if (!first)
554 first = new;
555 else
Ira Snydera1c03312010-01-06 13:34:05 +0000556 set_desc_next(chan, &prev->hw, new->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700557
558 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700559 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700560
561 prev = new;
562 len -= copy;
563 dma_src += copy;
Ira Snyder738f5f72010-01-06 13:34:02 +0000564 dma_dst += copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700565
566 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700567 list_add_tail(&new->node, &first->tx_list);
Zhang Wei173acc72008-03-01 07:42:48 -0700568 } while (len);
569
Dan Williams636bdea2008-04-17 20:17:26 -0700570 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700571 new->async_tx.cookie = -EBUSY;
572
573 /* Set End-of-link to the last link descriptor of new list*/
Ira Snydera1c03312010-01-06 13:34:05 +0000574 set_ld_eol(chan, new);
Zhang Wei173acc72008-03-01 07:42:48 -0700575
Ira Snyder2e077f82009-05-15 09:59:46 -0700576 return &first->async_tx;
577
578fail:
579 if (!first)
580 return NULL;
581
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000582 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyder2e077f82009-05-15 09:59:46 -0700583 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700584}
585
586/**
Ira Snyderbbea0b62009-09-08 17:53:04 -0700587 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
588 * @chan: DMA channel
589 * @sgl: scatterlist to transfer to/from
590 * @sg_len: number of entries in @scatterlist
591 * @direction: DMA direction
592 * @flags: DMAEngine flags
593 *
594 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
595 * DMA_SLAVE API, this gets the device-specific information from the
596 * chan->private variable.
597 */
598static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
Ira Snydera1c03312010-01-06 13:34:05 +0000599 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
Ira Snyderbbea0b62009-09-08 17:53:04 -0700600 enum dma_data_direction direction, unsigned long flags)
601{
Ira Snydera1c03312010-01-06 13:34:05 +0000602 struct fsldma_chan *chan;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700603 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
604 struct fsl_dma_slave *slave;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700605 size_t copy;
606
607 int i;
608 struct scatterlist *sg;
609 size_t sg_used;
610 size_t hw_used;
611 struct fsl_dma_hw_addr *hw;
612 dma_addr_t dma_dst, dma_src;
613
Ira Snydera1c03312010-01-06 13:34:05 +0000614 if (!dchan)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700615 return NULL;
616
Ira Snydera1c03312010-01-06 13:34:05 +0000617 if (!dchan->private)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700618 return NULL;
619
Ira Snydera1c03312010-01-06 13:34:05 +0000620 chan = to_fsl_chan(dchan);
621 slave = dchan->private;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700622
623 if (list_empty(&slave->addresses))
624 return NULL;
625
626 hw = list_first_entry(&slave->addresses, struct fsl_dma_hw_addr, entry);
627 hw_used = 0;
628
629 /*
630 * Build the hardware transaction to copy from the scatterlist to
631 * the hardware, or from the hardware to the scatterlist
632 *
633 * If you are copying from the hardware to the scatterlist and it
634 * takes two hardware entries to fill an entire page, then both
635 * hardware entries will be coalesced into the same page
636 *
637 * If you are copying from the scatterlist to the hardware and a
638 * single page can fill two hardware entries, then the data will
639 * be read out of the page into the first hardware entry, and so on
640 */
641 for_each_sg(sgl, sg, sg_len, i) {
642 sg_used = 0;
643
644 /* Loop until the entire scatterlist entry is used */
645 while (sg_used < sg_dma_len(sg)) {
646
647 /*
648 * If we've used up the current hardware address/length
649 * pair, we need to load a new one
650 *
651 * This is done in a while loop so that descriptors with
652 * length == 0 will be skipped
653 */
654 while (hw_used >= hw->length) {
655
656 /*
657 * If the current hardware entry is the last
658 * entry in the list, we're finished
659 */
660 if (list_is_last(&hw->entry, &slave->addresses))
661 goto finished;
662
663 /* Get the next hardware address/length pair */
664 hw = list_entry(hw->entry.next,
665 struct fsl_dma_hw_addr, entry);
666 hw_used = 0;
667 }
668
669 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000670 new = fsl_dma_alloc_descriptor(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700671 if (!new) {
Ira Snydera1c03312010-01-06 13:34:05 +0000672 dev_err(chan->dev, "No free memory for "
Ira Snyderbbea0b62009-09-08 17:53:04 -0700673 "link descriptor\n");
674 goto fail;
675 }
676#ifdef FSL_DMA_LD_DEBUG
Ira Snydera1c03312010-01-06 13:34:05 +0000677 dev_dbg(chan->dev, "new link desc alloc %p\n", new);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700678#endif
679
680 /*
681 * Calculate the maximum number of bytes to transfer,
682 * making sure it is less than the DMA controller limit
683 */
684 copy = min_t(size_t, sg_dma_len(sg) - sg_used,
685 hw->length - hw_used);
686 copy = min_t(size_t, copy, FSL_DMA_BCR_MAX_CNT);
687
688 /*
689 * DMA_FROM_DEVICE
690 * from the hardware to the scatterlist
691 *
692 * DMA_TO_DEVICE
693 * from the scatterlist to the hardware
694 */
695 if (direction == DMA_FROM_DEVICE) {
696 dma_src = hw->address + hw_used;
697 dma_dst = sg_dma_address(sg) + sg_used;
698 } else {
699 dma_src = sg_dma_address(sg) + sg_used;
700 dma_dst = hw->address + hw_used;
701 }
702
703 /* Fill in the descriptor */
Ira Snydera1c03312010-01-06 13:34:05 +0000704 set_desc_cnt(chan, &new->hw, copy);
705 set_desc_src(chan, &new->hw, dma_src);
706 set_desc_dst(chan, &new->hw, dma_dst);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700707
708 /*
709 * If this is not the first descriptor, chain the
710 * current descriptor after the previous descriptor
711 */
712 if (!first) {
713 first = new;
714 } else {
Ira Snydera1c03312010-01-06 13:34:05 +0000715 set_desc_next(chan, &prev->hw,
Ira Snyderbbea0b62009-09-08 17:53:04 -0700716 new->async_tx.phys);
717 }
718
719 new->async_tx.cookie = 0;
720 async_tx_ack(&new->async_tx);
721
722 prev = new;
723 sg_used += copy;
724 hw_used += copy;
725
726 /* Insert the link descriptor into the LD ring */
727 list_add_tail(&new->node, &first->tx_list);
728 }
729 }
730
731finished:
732
733 /* All of the hardware address/length pairs had length == 0 */
734 if (!first || !new)
735 return NULL;
736
737 new->async_tx.flags = flags;
738 new->async_tx.cookie = -EBUSY;
739
740 /* Set End-of-link to the last link descriptor of new list */
Ira Snydera1c03312010-01-06 13:34:05 +0000741 set_ld_eol(chan, new);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700742
743 /* Enable extra controller features */
Ira Snydera1c03312010-01-06 13:34:05 +0000744 if (chan->set_src_loop_size)
745 chan->set_src_loop_size(chan, slave->src_loop_size);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700746
Ira Snydera1c03312010-01-06 13:34:05 +0000747 if (chan->set_dst_loop_size)
748 chan->set_dst_loop_size(chan, slave->dst_loop_size);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700749
Ira Snydera1c03312010-01-06 13:34:05 +0000750 if (chan->toggle_ext_start)
751 chan->toggle_ext_start(chan, slave->external_start);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700752
Ira Snydera1c03312010-01-06 13:34:05 +0000753 if (chan->toggle_ext_pause)
754 chan->toggle_ext_pause(chan, slave->external_pause);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700755
Ira Snydera1c03312010-01-06 13:34:05 +0000756 if (chan->set_request_count)
757 chan->set_request_count(chan, slave->request_count);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700758
759 return &first->async_tx;
760
761fail:
762 /* If first was not set, then we failed to allocate the very first
763 * descriptor, and we're done */
764 if (!first)
765 return NULL;
766
767 /*
768 * First is set, so all of the descriptors we allocated have been added
769 * to first->tx_list, INCLUDING "first" itself. Therefore we
770 * must traverse the list backwards freeing each descriptor in turn
771 *
772 * We're re-using variables for the loop, oh well
773 */
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000774 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700775 return NULL;
776}
777
Ira Snydera1c03312010-01-06 13:34:05 +0000778static void fsl_dma_device_terminate_all(struct dma_chan *dchan)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700779{
Ira Snydera1c03312010-01-06 13:34:05 +0000780 struct fsldma_chan *chan;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700781 unsigned long flags;
782
Ira Snydera1c03312010-01-06 13:34:05 +0000783 if (!dchan)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700784 return;
785
Ira Snydera1c03312010-01-06 13:34:05 +0000786 chan = to_fsl_chan(dchan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700787
788 /* Halt the DMA engine */
Ira Snydera1c03312010-01-06 13:34:05 +0000789 dma_halt(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700790
Ira Snydera1c03312010-01-06 13:34:05 +0000791 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700792
793 /* Remove and free all of the descriptors in the LD queue */
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000794 fsldma_free_desc_list(chan, &chan->ld_pending);
795 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700796
Ira Snydera1c03312010-01-06 13:34:05 +0000797 spin_unlock_irqrestore(&chan->desc_lock, flags);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700798}
799
800/**
Zhang Wei173acc72008-03-01 07:42:48 -0700801 * fsl_dma_update_completed_cookie - Update the completed cookie.
Ira Snydera1c03312010-01-06 13:34:05 +0000802 * @chan : Freescale DMA channel
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000803 *
804 * CONTEXT: hardirq
Zhang Wei173acc72008-03-01 07:42:48 -0700805 */
Ira Snydera1c03312010-01-06 13:34:05 +0000806static void fsl_dma_update_completed_cookie(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700807{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000808 struct fsl_desc_sw *desc;
809 unsigned long flags;
810 dma_cookie_t cookie;
Zhang Wei173acc72008-03-01 07:42:48 -0700811
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000812 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700813
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000814 if (list_empty(&chan->ld_running)) {
815 dev_dbg(chan->dev, "no running descriptors\n");
816 goto out_unlock;
Zhang Wei173acc72008-03-01 07:42:48 -0700817 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000818
819 /* Get the last descriptor, update the cookie to that */
820 desc = to_fsl_desc(chan->ld_running.prev);
821 if (dma_is_idle(chan))
822 cookie = desc->async_tx.cookie;
Steven J. Magnani76bd0612010-02-28 22:18:16 -0700823 else {
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000824 cookie = desc->async_tx.cookie - 1;
Steven J. Magnani76bd0612010-02-28 22:18:16 -0700825 if (unlikely(cookie < DMA_MIN_COOKIE))
826 cookie = DMA_MAX_COOKIE;
827 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000828
829 chan->completed_cookie = cookie;
830
831out_unlock:
832 spin_unlock_irqrestore(&chan->desc_lock, flags);
833}
834
835/**
836 * fsldma_desc_status - Check the status of a descriptor
837 * @chan: Freescale DMA channel
838 * @desc: DMA SW descriptor
839 *
840 * This function will return the status of the given descriptor
841 */
842static enum dma_status fsldma_desc_status(struct fsldma_chan *chan,
843 struct fsl_desc_sw *desc)
844{
845 return dma_async_is_complete(desc->async_tx.cookie,
846 chan->completed_cookie,
847 chan->common.cookie);
Zhang Wei173acc72008-03-01 07:42:48 -0700848}
849
850/**
851 * fsl_chan_ld_cleanup - Clean up link descriptors
Ira Snydera1c03312010-01-06 13:34:05 +0000852 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700853 *
854 * This function clean up the ld_queue of DMA channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700855 */
Ira Snydera1c03312010-01-06 13:34:05 +0000856static void fsl_chan_ld_cleanup(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700857{
858 struct fsl_desc_sw *desc, *_desc;
859 unsigned long flags;
860
Ira Snydera1c03312010-01-06 13:34:05 +0000861 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700862
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000863 dev_dbg(chan->dev, "chan completed_cookie = %d\n", chan->completed_cookie);
864 list_for_each_entry_safe(desc, _desc, &chan->ld_running, node) {
Zhang Wei173acc72008-03-01 07:42:48 -0700865 dma_async_tx_callback callback;
866 void *callback_param;
867
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000868 if (fsldma_desc_status(chan, desc) == DMA_IN_PROGRESS)
Zhang Wei173acc72008-03-01 07:42:48 -0700869 break;
870
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000871 /* Remove from the list of running transactions */
Zhang Wei173acc72008-03-01 07:42:48 -0700872 list_del(&desc->node);
873
Zhang Wei173acc72008-03-01 07:42:48 -0700874 /* Run the link descriptor callback function */
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000875 callback = desc->async_tx.callback;
876 callback_param = desc->async_tx.callback_param;
Zhang Wei173acc72008-03-01 07:42:48 -0700877 if (callback) {
Ira Snydera1c03312010-01-06 13:34:05 +0000878 spin_unlock_irqrestore(&chan->desc_lock, flags);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000879 dev_dbg(chan->dev, "LD %p callback\n", desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700880 callback(callback_param);
Ira Snydera1c03312010-01-06 13:34:05 +0000881 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700882 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000883
884 /* Run any dependencies, then free the descriptor */
885 dma_run_dependencies(&desc->async_tx);
886 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700887 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000888
Ira Snydera1c03312010-01-06 13:34:05 +0000889 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700890}
891
892/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000893 * fsl_chan_xfer_ld_queue - transfer any pending transactions
Ira Snydera1c03312010-01-06 13:34:05 +0000894 * @chan : Freescale DMA channel
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000895 *
896 * This will make sure that any pending transactions will be run.
897 * If the DMA controller is idle, it will be started. Otherwise,
898 * the DMA controller's interrupt handler will start any pending
899 * transactions when it becomes idle.
Zhang Wei173acc72008-03-01 07:42:48 -0700900 */
Ira Snydera1c03312010-01-06 13:34:05 +0000901static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700902{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000903 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700904 unsigned long flags;
905
Ira Snydera1c03312010-01-06 13:34:05 +0000906 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder138ef012009-05-19 15:42:13 -0700907
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000908 /*
909 * If the list of pending descriptors is empty, then we
910 * don't need to do any work at all
911 */
912 if (list_empty(&chan->ld_pending)) {
913 dev_dbg(chan->dev, "no pending LDs\n");
Ira Snyder138ef012009-05-19 15:42:13 -0700914 goto out_unlock;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000915 }
Zhang Wei173acc72008-03-01 07:42:48 -0700916
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000917 /*
918 * The DMA controller is not idle, which means the interrupt
919 * handler will start any queued transactions when it runs
920 * at the end of the current transaction
921 */
922 if (!dma_is_idle(chan)) {
923 dev_dbg(chan->dev, "DMA controller still busy\n");
924 goto out_unlock;
925 }
926
927 /*
928 * TODO:
929 * make sure the dma_halt() function really un-wedges the
930 * controller as much as possible
931 */
Ira Snydera1c03312010-01-06 13:34:05 +0000932 dma_halt(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700933
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000934 /*
935 * If there are some link descriptors which have not been
936 * transferred, we need to start the controller
Zhang Wei173acc72008-03-01 07:42:48 -0700937 */
Zhang Wei173acc72008-03-01 07:42:48 -0700938
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000939 /*
940 * Move all elements from the queue of pending transactions
941 * onto the list of running transactions
942 */
943 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
944 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
Zhang Wei173acc72008-03-01 07:42:48 -0700945
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000946 /*
947 * Program the descriptor's address into the DMA controller,
948 * then start the DMA transaction
949 */
950 set_cdar(chan, desc->async_tx.phys);
951 dma_start(chan);
Ira Snyder138ef012009-05-19 15:42:13 -0700952
953out_unlock:
Ira Snydera1c03312010-01-06 13:34:05 +0000954 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700955}
956
957/**
958 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
Ira Snydera1c03312010-01-06 13:34:05 +0000959 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700960 */
Ira Snydera1c03312010-01-06 13:34:05 +0000961static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700962{
Ira Snydera1c03312010-01-06 13:34:05 +0000963 struct fsldma_chan *chan = to_fsl_chan(dchan);
Ira Snydera1c03312010-01-06 13:34:05 +0000964 fsl_chan_xfer_ld_queue(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700965}
966
Zhang Wei173acc72008-03-01 07:42:48 -0700967/**
968 * fsl_dma_is_complete - Determine the DMA status
Ira Snydera1c03312010-01-06 13:34:05 +0000969 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700970 */
Ira Snydera1c03312010-01-06 13:34:05 +0000971static enum dma_status fsl_dma_is_complete(struct dma_chan *dchan,
Zhang Wei173acc72008-03-01 07:42:48 -0700972 dma_cookie_t cookie,
973 dma_cookie_t *done,
974 dma_cookie_t *used)
975{
Ira Snydera1c03312010-01-06 13:34:05 +0000976 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700977 dma_cookie_t last_used;
978 dma_cookie_t last_complete;
979
Ira Snydera1c03312010-01-06 13:34:05 +0000980 fsl_chan_ld_cleanup(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700981
Ira Snydera1c03312010-01-06 13:34:05 +0000982 last_used = dchan->cookie;
983 last_complete = chan->completed_cookie;
Zhang Wei173acc72008-03-01 07:42:48 -0700984
985 if (done)
986 *done = last_complete;
987
988 if (used)
989 *used = last_used;
990
991 return dma_async_is_complete(cookie, last_complete, last_used);
992}
993
Ira Snyderd3f620b2010-01-06 13:34:04 +0000994/*----------------------------------------------------------------------------*/
995/* Interrupt Handling */
996/*----------------------------------------------------------------------------*/
997
Ira Snydere7a29152010-01-06 13:34:03 +0000998static irqreturn_t fsldma_chan_irq(int irq, void *data)
Zhang Wei173acc72008-03-01 07:42:48 -0700999{
Ira Snydera1c03312010-01-06 13:34:05 +00001000 struct fsldma_chan *chan = data;
Zhang Wei1c629792008-04-17 20:17:25 -07001001 int update_cookie = 0;
1002 int xfer_ld_q = 0;
Ira Snydera1c03312010-01-06 13:34:05 +00001003 u32 stat;
Zhang Wei173acc72008-03-01 07:42:48 -07001004
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001005 /* save and clear the status register */
Ira Snydera1c03312010-01-06 13:34:05 +00001006 stat = get_sr(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001007 set_sr(chan, stat);
1008 dev_dbg(chan->dev, "irq: channel %d, stat = 0x%x\n", chan->id, stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001009
1010 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1011 if (!stat)
1012 return IRQ_NONE;
1013
1014 if (stat & FSL_DMA_SR_TE)
Ira Snydera1c03312010-01-06 13:34:05 +00001015 dev_err(chan->dev, "Transfer Error!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001016
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001017 /*
1018 * Programming Error
Zhang Weif79abb62008-03-18 18:45:00 -07001019 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1020 * triger a PE interrupt.
1021 */
1022 if (stat & FSL_DMA_SR_PE) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001023 dev_dbg(chan->dev, "irq: Programming Error INT\n");
Ira Snydera1c03312010-01-06 13:34:05 +00001024 if (get_bcr(chan) == 0) {
Zhang Weif79abb62008-03-18 18:45:00 -07001025 /* BCR register is 0, this is a DMA_INTERRUPT async_tx.
1026 * Now, update the completed cookie, and continue the
1027 * next uncompleted transfer.
1028 */
Zhang Wei1c629792008-04-17 20:17:25 -07001029 update_cookie = 1;
1030 xfer_ld_q = 1;
Zhang Weif79abb62008-03-18 18:45:00 -07001031 }
1032 stat &= ~FSL_DMA_SR_PE;
1033 }
1034
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001035 /*
1036 * If the link descriptor segment transfer finishes,
Zhang Wei173acc72008-03-01 07:42:48 -07001037 * we will recycle the used descriptor.
1038 */
1039 if (stat & FSL_DMA_SR_EOSI) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001040 dev_dbg(chan->dev, "irq: End-of-segments INT\n");
1041 dev_dbg(chan->dev, "irq: clndar 0x%llx, nlndar 0x%llx\n",
Ira Snydera1c03312010-01-06 13:34:05 +00001042 (unsigned long long)get_cdar(chan),
1043 (unsigned long long)get_ndar(chan));
Zhang Wei173acc72008-03-01 07:42:48 -07001044 stat &= ~FSL_DMA_SR_EOSI;
Zhang Wei1c629792008-04-17 20:17:25 -07001045 update_cookie = 1;
1046 }
1047
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001048 /*
1049 * For MPC8349, EOCDI event need to update cookie
Zhang Wei1c629792008-04-17 20:17:25 -07001050 * and start the next transfer if it exist.
1051 */
1052 if (stat & FSL_DMA_SR_EOCDI) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001053 dev_dbg(chan->dev, "irq: End-of-Chain link INT\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001054 stat &= ~FSL_DMA_SR_EOCDI;
1055 update_cookie = 1;
1056 xfer_ld_q = 1;
Zhang Wei173acc72008-03-01 07:42:48 -07001057 }
1058
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001059 /*
1060 * If it current transfer is the end-of-transfer,
Zhang Wei173acc72008-03-01 07:42:48 -07001061 * we should clear the Channel Start bit for
1062 * prepare next transfer.
1063 */
Zhang Wei1c629792008-04-17 20:17:25 -07001064 if (stat & FSL_DMA_SR_EOLNI) {
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001065 dev_dbg(chan->dev, "irq: End-of-link INT\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001066 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei1c629792008-04-17 20:17:25 -07001067 xfer_ld_q = 1;
Zhang Wei173acc72008-03-01 07:42:48 -07001068 }
1069
Zhang Wei1c629792008-04-17 20:17:25 -07001070 if (update_cookie)
Ira Snydera1c03312010-01-06 13:34:05 +00001071 fsl_dma_update_completed_cookie(chan);
Zhang Wei1c629792008-04-17 20:17:25 -07001072 if (xfer_ld_q)
Ira Snydera1c03312010-01-06 13:34:05 +00001073 fsl_chan_xfer_ld_queue(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001074 if (stat)
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001075 dev_dbg(chan->dev, "irq: unhandled sr 0x%02x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001076
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001077 dev_dbg(chan->dev, "irq: Exit\n");
Ira Snydera1c03312010-01-06 13:34:05 +00001078 tasklet_schedule(&chan->tasklet);
Zhang Wei173acc72008-03-01 07:42:48 -07001079 return IRQ_HANDLED;
1080}
1081
Zhang Wei173acc72008-03-01 07:42:48 -07001082static void dma_do_tasklet(unsigned long data)
1083{
Ira Snydera1c03312010-01-06 13:34:05 +00001084 struct fsldma_chan *chan = (struct fsldma_chan *)data;
1085 fsl_chan_ld_cleanup(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001086}
1087
Ira Snyderd3f620b2010-01-06 13:34:04 +00001088static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1089{
1090 struct fsldma_device *fdev = data;
1091 struct fsldma_chan *chan;
1092 unsigned int handled = 0;
1093 u32 gsr, mask;
1094 int i;
1095
1096 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1097 : in_le32(fdev->regs);
1098 mask = 0xff000000;
1099 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1100
1101 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1102 chan = fdev->chan[i];
1103 if (!chan)
1104 continue;
1105
1106 if (gsr & mask) {
1107 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1108 fsldma_chan_irq(irq, chan);
1109 handled++;
1110 }
1111
1112 gsr &= ~mask;
1113 mask >>= 8;
1114 }
1115
1116 return IRQ_RETVAL(handled);
1117}
1118
1119static void fsldma_free_irqs(struct fsldma_device *fdev)
1120{
1121 struct fsldma_chan *chan;
1122 int i;
1123
1124 if (fdev->irq != NO_IRQ) {
1125 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1126 free_irq(fdev->irq, fdev);
1127 return;
1128 }
1129
1130 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1131 chan = fdev->chan[i];
1132 if (chan && chan->irq != NO_IRQ) {
1133 dev_dbg(fdev->dev, "free channel %d IRQ\n", chan->id);
1134 free_irq(chan->irq, chan);
1135 }
1136 }
1137}
1138
1139static int fsldma_request_irqs(struct fsldma_device *fdev)
1140{
1141 struct fsldma_chan *chan;
1142 int ret;
1143 int i;
1144
1145 /* if we have a per-controller IRQ, use that */
1146 if (fdev->irq != NO_IRQ) {
1147 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1148 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1149 "fsldma-controller", fdev);
1150 return ret;
1151 }
1152
1153 /* no per-controller IRQ, use the per-channel IRQs */
1154 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1155 chan = fdev->chan[i];
1156 if (!chan)
1157 continue;
1158
1159 if (chan->irq == NO_IRQ) {
1160 dev_err(fdev->dev, "no interrupts property defined for "
1161 "DMA channel %d. Please fix your "
1162 "device tree\n", chan->id);
1163 ret = -ENODEV;
1164 goto out_unwind;
1165 }
1166
1167 dev_dbg(fdev->dev, "request channel %d IRQ\n", chan->id);
1168 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1169 "fsldma-chan", chan);
1170 if (ret) {
1171 dev_err(fdev->dev, "unable to request IRQ for DMA "
1172 "channel %d\n", chan->id);
1173 goto out_unwind;
1174 }
1175 }
1176
1177 return 0;
1178
1179out_unwind:
1180 for (/* none */; i >= 0; i--) {
1181 chan = fdev->chan[i];
1182 if (!chan)
1183 continue;
1184
1185 if (chan->irq == NO_IRQ)
1186 continue;
1187
1188 free_irq(chan->irq, chan);
1189 }
1190
1191 return ret;
1192}
1193
Ira Snydera4f56d42010-01-06 13:34:01 +00001194/*----------------------------------------------------------------------------*/
1195/* OpenFirmware Subsystem */
1196/*----------------------------------------------------------------------------*/
1197
1198static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
Timur Tabi77cd62e2008-09-26 17:00:11 -07001199 struct device_node *node, u32 feature, const char *compatible)
Zhang Wei173acc72008-03-01 07:42:48 -07001200{
Ira Snydera1c03312010-01-06 13:34:05 +00001201 struct fsldma_chan *chan;
Ira Snyder4ce0e952010-01-06 13:34:00 +00001202 struct resource res;
Zhang Wei173acc72008-03-01 07:42:48 -07001203 int err;
1204
Zhang Wei173acc72008-03-01 07:42:48 -07001205 /* alloc channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001206 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1207 if (!chan) {
Ira Snydere7a29152010-01-06 13:34:03 +00001208 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1209 err = -ENOMEM;
1210 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001211 }
1212
Ira Snydere7a29152010-01-06 13:34:03 +00001213 /* ioremap registers for use */
Ira Snydera1c03312010-01-06 13:34:05 +00001214 chan->regs = of_iomap(node, 0);
1215 if (!chan->regs) {
Ira Snydere7a29152010-01-06 13:34:03 +00001216 dev_err(fdev->dev, "unable to ioremap registers\n");
1217 err = -ENOMEM;
Ira Snydera1c03312010-01-06 13:34:05 +00001218 goto out_free_chan;
Ira Snydere7a29152010-01-06 13:34:03 +00001219 }
1220
Ira Snyder4ce0e952010-01-06 13:34:00 +00001221 err = of_address_to_resource(node, 0, &res);
Zhang Wei173acc72008-03-01 07:42:48 -07001222 if (err) {
Ira Snydere7a29152010-01-06 13:34:03 +00001223 dev_err(fdev->dev, "unable to find 'reg' property\n");
1224 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001225 }
1226
Ira Snydera1c03312010-01-06 13:34:05 +00001227 chan->feature = feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001228 if (!fdev->feature)
Ira Snydera1c03312010-01-06 13:34:05 +00001229 fdev->feature = chan->feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001230
Ira Snydere7a29152010-01-06 13:34:03 +00001231 /*
1232 * If the DMA device's feature is different than the feature
1233 * of its channels, report the bug
Zhang Wei173acc72008-03-01 07:42:48 -07001234 */
Ira Snydera1c03312010-01-06 13:34:05 +00001235 WARN_ON(fdev->feature != chan->feature);
Zhang Wei173acc72008-03-01 07:42:48 -07001236
Ira Snydera1c03312010-01-06 13:34:05 +00001237 chan->dev = fdev->dev;
1238 chan->id = ((res.start - 0x100) & 0xfff) >> 7;
1239 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
Ira Snydere7a29152010-01-06 13:34:03 +00001240 dev_err(fdev->dev, "too many channels for device\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001241 err = -EINVAL;
Ira Snydere7a29152010-01-06 13:34:03 +00001242 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001243 }
Zhang Wei173acc72008-03-01 07:42:48 -07001244
Ira Snydera1c03312010-01-06 13:34:05 +00001245 fdev->chan[chan->id] = chan;
1246 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001247
1248 /* Initialize the channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001249 dma_init(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001250
1251 /* Clear cdar registers */
Ira Snydera1c03312010-01-06 13:34:05 +00001252 set_cdar(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -07001253
Ira Snydera1c03312010-01-06 13:34:05 +00001254 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -07001255 case FSL_DMA_IP_85XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001256 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
Zhang Wei173acc72008-03-01 07:42:48 -07001257 case FSL_DMA_IP_83XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001258 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1259 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1260 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1261 chan->set_request_count = fsl_chan_set_request_count;
Zhang Wei173acc72008-03-01 07:42:48 -07001262 }
1263
Ira Snydera1c03312010-01-06 13:34:05 +00001264 spin_lock_init(&chan->desc_lock);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001265 INIT_LIST_HEAD(&chan->ld_pending);
1266 INIT_LIST_HEAD(&chan->ld_running);
Zhang Wei173acc72008-03-01 07:42:48 -07001267
Ira Snydera1c03312010-01-06 13:34:05 +00001268 chan->common.device = &fdev->common;
Zhang Wei173acc72008-03-01 07:42:48 -07001269
Ira Snyderd3f620b2010-01-06 13:34:04 +00001270 /* find the IRQ line, if it exists in the device tree */
Ira Snydera1c03312010-01-06 13:34:05 +00001271 chan->irq = irq_of_parse_and_map(node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001272
Zhang Wei173acc72008-03-01 07:42:48 -07001273 /* Add the channel to DMA device channel list */
Ira Snydera1c03312010-01-06 13:34:05 +00001274 list_add_tail(&chan->common.device_node, &fdev->common.channels);
Zhang Wei173acc72008-03-01 07:42:48 -07001275 fdev->common.chancnt++;
1276
Ira Snydera1c03312010-01-06 13:34:05 +00001277 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1278 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001279
1280 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001281
Ira Snydere7a29152010-01-06 13:34:03 +00001282out_iounmap_regs:
Ira Snydera1c03312010-01-06 13:34:05 +00001283 iounmap(chan->regs);
1284out_free_chan:
1285 kfree(chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001286out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001287 return err;
1288}
1289
Ira Snydera1c03312010-01-06 13:34:05 +00001290static void fsl_dma_chan_remove(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -07001291{
Ira Snydera1c03312010-01-06 13:34:05 +00001292 irq_dispose_mapping(chan->irq);
1293 list_del(&chan->common.device_node);
1294 iounmap(chan->regs);
1295 kfree(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001296}
1297
Ira Snydere7a29152010-01-06 13:34:03 +00001298static int __devinit fsldma_of_probe(struct of_device *op,
Zhang Wei173acc72008-03-01 07:42:48 -07001299 const struct of_device_id *match)
1300{
Ira Snydera4f56d42010-01-06 13:34:01 +00001301 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001302 struct device_node *child;
Ira Snydere7a29152010-01-06 13:34:03 +00001303 int err;
Zhang Wei173acc72008-03-01 07:42:48 -07001304
Ira Snydera4f56d42010-01-06 13:34:01 +00001305 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
Zhang Wei173acc72008-03-01 07:42:48 -07001306 if (!fdev) {
Ira Snydere7a29152010-01-06 13:34:03 +00001307 dev_err(&op->dev, "No enough memory for 'priv'\n");
1308 err = -ENOMEM;
1309 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001310 }
Ira Snydere7a29152010-01-06 13:34:03 +00001311
1312 fdev->dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001313 INIT_LIST_HEAD(&fdev->common.channels);
1314
Ira Snydere7a29152010-01-06 13:34:03 +00001315 /* ioremap the registers for use */
1316 fdev->regs = of_iomap(op->node, 0);
1317 if (!fdev->regs) {
1318 dev_err(&op->dev, "unable to ioremap registers\n");
1319 err = -ENOMEM;
1320 goto out_free_fdev;
Zhang Wei173acc72008-03-01 07:42:48 -07001321 }
1322
Ira Snyderd3f620b2010-01-06 13:34:04 +00001323 /* map the channel IRQ if it exists, but don't hookup the handler yet */
1324 fdev->irq = irq_of_parse_and_map(op->node, 0);
1325
Zhang Wei173acc72008-03-01 07:42:48 -07001326 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1327 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
Ira Snyderbbea0b62009-09-08 17:53:04 -07001328 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
Zhang Wei173acc72008-03-01 07:42:48 -07001329 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1330 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei2187c262008-03-13 17:45:28 -07001331 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
Zhang Wei173acc72008-03-01 07:42:48 -07001332 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
1333 fdev->common.device_is_tx_complete = fsl_dma_is_complete;
1334 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Ira Snyderbbea0b62009-09-08 17:53:04 -07001335 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
1336 fdev->common.device_terminate_all = fsl_dma_device_terminate_all;
Ira Snydere7a29152010-01-06 13:34:03 +00001337 fdev->common.dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001338
Ira Snydere7a29152010-01-06 13:34:03 +00001339 dev_set_drvdata(&op->dev, fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001340
Ira Snydere7a29152010-01-06 13:34:03 +00001341 /*
1342 * We cannot use of_platform_bus_probe() because there is no
1343 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -07001344 * channel object.
1345 */
Ira Snydere7a29152010-01-06 13:34:03 +00001346 for_each_child_of_node(op->node, child) {
1347 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001348 fsl_dma_chan_probe(fdev, child,
1349 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1350 "fsl,eloplus-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001351 }
1352
1353 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001354 fsl_dma_chan_probe(fdev, child,
1355 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1356 "fsl,elo-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001357 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001358 }
Zhang Wei173acc72008-03-01 07:42:48 -07001359
Ira Snyderd3f620b2010-01-06 13:34:04 +00001360 /*
1361 * Hookup the IRQ handler(s)
1362 *
1363 * If we have a per-controller interrupt, we prefer that to the
1364 * per-channel interrupts to reduce the number of shared interrupt
1365 * handlers on the same IRQ line
1366 */
1367 err = fsldma_request_irqs(fdev);
1368 if (err) {
1369 dev_err(fdev->dev, "unable to request IRQs\n");
1370 goto out_free_fdev;
1371 }
1372
Zhang Wei173acc72008-03-01 07:42:48 -07001373 dma_async_device_register(&fdev->common);
1374 return 0;
1375
Ira Snydere7a29152010-01-06 13:34:03 +00001376out_free_fdev:
Ira Snyderd3f620b2010-01-06 13:34:04 +00001377 irq_dispose_mapping(fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001378 kfree(fdev);
Ira Snydere7a29152010-01-06 13:34:03 +00001379out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001380 return err;
1381}
1382
Ira Snydere7a29152010-01-06 13:34:03 +00001383static int fsldma_of_remove(struct of_device *op)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001384{
Ira Snydera4f56d42010-01-06 13:34:01 +00001385 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001386 unsigned int i;
1387
Ira Snydere7a29152010-01-06 13:34:03 +00001388 fdev = dev_get_drvdata(&op->dev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001389 dma_async_device_unregister(&fdev->common);
1390
Ira Snyderd3f620b2010-01-06 13:34:04 +00001391 fsldma_free_irqs(fdev);
1392
Ira Snydere7a29152010-01-06 13:34:03 +00001393 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001394 if (fdev->chan[i])
1395 fsl_dma_chan_remove(fdev->chan[i]);
Ira Snydere7a29152010-01-06 13:34:03 +00001396 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001397
Ira Snydere7a29152010-01-06 13:34:03 +00001398 iounmap(fdev->regs);
1399 dev_set_drvdata(&op->dev, NULL);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001400 kfree(fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001401
1402 return 0;
1403}
1404
Márton Németh4b1cf1f2010-02-02 23:41:06 -07001405static const struct of_device_id fsldma_of_ids[] = {
Kumar Gala049c9d42008-03-31 11:13:21 -05001406 { .compatible = "fsl,eloplus-dma", },
1407 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001408 {}
1409};
1410
Ira Snydera4f56d42010-01-06 13:34:01 +00001411static struct of_platform_driver fsldma_of_driver = {
1412 .name = "fsl-elo-dma",
1413 .match_table = fsldma_of_ids,
1414 .probe = fsldma_of_probe,
1415 .remove = fsldma_of_remove,
Zhang Wei173acc72008-03-01 07:42:48 -07001416};
1417
Ira Snydera4f56d42010-01-06 13:34:01 +00001418/*----------------------------------------------------------------------------*/
1419/* Module Init / Exit */
1420/*----------------------------------------------------------------------------*/
1421
1422static __init int fsldma_init(void)
Zhang Wei173acc72008-03-01 07:42:48 -07001423{
Timur Tabi77cd62e2008-09-26 17:00:11 -07001424 int ret;
1425
1426 pr_info("Freescale Elo / Elo Plus DMA driver\n");
1427
Ira Snydera4f56d42010-01-06 13:34:01 +00001428 ret = of_register_platform_driver(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001429 if (ret)
1430 pr_err("fsldma: failed to register platform driver\n");
1431
1432 return ret;
Zhang Wei173acc72008-03-01 07:42:48 -07001433}
1434
Ira Snydera4f56d42010-01-06 13:34:01 +00001435static void __exit fsldma_exit(void)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001436{
Ira Snydera4f56d42010-01-06 13:34:01 +00001437 of_unregister_platform_driver(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001438}
1439
Ira Snydera4f56d42010-01-06 13:34:01 +00001440subsys_initcall(fsldma_init);
1441module_exit(fsldma_exit);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001442
1443MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1444MODULE_LICENSE("GPL");