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Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001/*
2 * Driver for DBRI sound chip found on Sparcs.
Martin Habets43388292005-09-10 15:39:00 +02003 * Copyright (C) 2004, 2005 Martin Habets (mhabets@users.sourceforge.net)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02004 *
Krzysztof Helt1be54c82006-08-21 19:30:57 +02005 * Converted to ring buffered version by Krzysztof Helt (krzysztof.h1@wp.pl)
6 *
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02007 * Based entirely upon drivers/sbus/audio/dbri.c which is:
8 * Copyright (C) 1997 Rudolf Koenig (rfkoenig@immd4.informatik.uni-erlangen.de)
9 * Copyright (C) 1998, 1999 Brent Baccala (baccala@freesoft.org)
10 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020011 * This is the low level driver for the DBRI & MMCODEC duo used for ISDN & AUDIO
12 * on Sun SPARCStation 10, 20, LX and Voyager models.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020013 *
14 * - DBRI: AT&T T5900FX Dual Basic Rates ISDN Interface. It is a 32 channel
15 * data time multiplexer with ISDN support (aka T7259)
16 * Interfaces: SBus,ISDN NT & TE, CHI, 4 bits parallel.
17 * CHI: (spelled ki) Concentration Highway Interface (AT&T or Intel bus ?).
18 * Documentation:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020019 * - "STP 4000SBus Dual Basic Rate ISDN (DBRI) Transceiver" from
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020020 * Sparc Technology Business (courtesy of Sun Support)
21 * - Data sheet of the T7903, a newer but very similar ISA bus equivalent
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020022 * available from the Lucent (formerly AT&T microelectronics) home
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020023 * page.
24 * - http://www.freesoft.org/Linux/DBRI/
25 * - MMCODEC: Crystal Semiconductor CS4215 16 bit Multimedia Audio Codec
26 * Interfaces: CHI, Audio In & Out, 2 bits parallel
27 * Documentation: from the Crystal Semiconductor home page.
28 *
29 * The DBRI is a 32 pipe machine, each pipe can transfer some bits between
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020030 * memory and a serial device (long pipes, no. 0-15) or between two serial
31 * devices (short pipes, no. 16-31), or simply send a fixed data to a serial
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020032 * device (short pipes).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020033 * A timeslot defines the bit-offset and no. of bits read from a serial device.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020034 * The timeslots are linked to 6 circular lists, one for each direction for
35 * each serial device (NT,TE,CHI). A timeslot is associated to 1 or 2 pipes
36 * (the second one is a monitor/tee pipe, valid only for serial input).
37 *
38 * The mmcodec is connected via the CHI bus and needs the data & some
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020039 * parameters (volume, output selection) time multiplexed in 8 byte
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020040 * chunks. It also has a control mode, which serves for audio format setting.
41 *
42 * Looking at the CS4215 data sheet it is easy to set up 2 or 4 codecs on
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020043 * the same CHI bus, so I thought perhaps it is possible to use the on-board
44 * & the speakerbox codec simultaneously, giving 2 (not very independent :-)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020045 * audio devices. But the SUN HW group decided against it, at least on my
46 * LX the speakerbox connector has at least 1 pin missing and 1 wrongly
47 * connected.
Martin Habets43388292005-09-10 15:39:00 +020048 *
49 * I've tried to stick to the following function naming conventions:
50 * snd_* ALSA stuff
Adrian Bunkd254c8f2006-06-30 18:29:51 +020051 * cs4215_* CS4215 codec specific stuff
Martin Habets43388292005-09-10 15:39:00 +020052 * dbri_* DBRI high-level stuff
53 * other DBRI low-level stuff
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020054 */
55
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020056#include <linux/interrupt.h>
57#include <linux/delay.h>
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020058#include <linux/irq.h>
59#include <linux/io.h>
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020060
61#include <sound/core.h>
62#include <sound/pcm.h>
63#include <sound/pcm_params.h>
64#include <sound/info.h>
65#include <sound/control.h>
66#include <sound/initval.h>
67
Krzysztof Heltef285fe2007-09-06 15:02:33 +020068#include <linux/of.h>
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020069#include <asm/sbus.h>
70#include <asm/atomic.h>
71
72MODULE_AUTHOR("Rudolf Koenig, Brent Baccala and Martin Habets");
73MODULE_DESCRIPTION("Sun DBRI");
74MODULE_LICENSE("GPL");
75MODULE_SUPPORTED_DEVICE("{{Sun,DBRI}}");
76
77static int index[SNDRV_CARDS] = SNDRV_DEFAULT_IDX; /* Index 0-MAX */
78static char *id[SNDRV_CARDS] = SNDRV_DEFAULT_STR; /* ID for this card */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +020079/* Enable this card */
80static int enable[SNDRV_CARDS] = SNDRV_DEFAULT_ENABLE_PNP;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020081
82module_param_array(index, int, NULL, 0444);
83MODULE_PARM_DESC(index, "Index value for Sun DBRI soundcard.");
84module_param_array(id, charp, NULL, 0444);
85MODULE_PARM_DESC(id, "ID string for Sun DBRI soundcard.");
86module_param_array(enable, bool, NULL, 0444);
87MODULE_PARM_DESC(enable, "Enable Sun DBRI soundcard.");
88
Krzysztof Heltab93c7a2006-08-23 11:37:36 +020089#undef DBRI_DEBUG
Takashi Iwai1bd9deb2005-06-30 18:26:20 +020090
91#define D_INT (1<<0)
92#define D_GEN (1<<1)
93#define D_CMD (1<<2)
94#define D_MM (1<<3)
95#define D_USR (1<<4)
96#define D_DESC (1<<5)
97
Takashi Iwai6581f4e2006-05-17 17:14:51 +020098static int dbri_debug;
Martin Habets43388292005-09-10 15:39:00 +020099module_param(dbri_debug, int, 0644);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200100MODULE_PARM_DESC(dbri_debug, "Debug value for Sun DBRI soundcard.");
101
102#ifdef DBRI_DEBUG
103static char *cmds[] = {
104 "WAIT", "PAUSE", "JUMP", "IIQ", "REX", "SDP", "CDP", "DTS",
105 "SSP", "CHI", "NT", "TE", "CDEC", "TEST", "CDM", "RESRV"
106};
107
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200108#define dprintk(a, x...) if (dbri_debug & a) printk(KERN_DEBUG x)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200109
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200110#else
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200111#define dprintk(a, x...) do { } while (0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200112
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200113#endif /* DBRI_DEBUG */
114
Krzysztof Helt42fe7642006-08-16 12:53:34 +0200115#define DBRI_CMD(cmd, intr, value) ((cmd << 28) | \
116 (intr << 27) | \
117 value)
118
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200119/***************************************************************************
120 CS4215 specific definitions and structures
121****************************************************************************/
122
123struct cs4215 {
124 __u8 data[4]; /* Data mode: Time slots 5-8 */
125 __u8 ctrl[4]; /* Ctrl mode: Time slots 1-4 */
126 __u8 onboard;
127 __u8 offset; /* Bit offset from frame sync to time slot 1 */
128 volatile __u32 status;
129 volatile __u32 version;
130 __u8 precision; /* In bits, either 8 or 16 */
131 __u8 channels; /* 1 or 2 */
132};
133
134/*
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200135 * Control mode first
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200136 */
137
138/* Time Slot 1, Status register */
139#define CS4215_CLB (1<<2) /* Control Latch Bit */
140#define CS4215_OLB (1<<3) /* 1: line: 2.0V, speaker 4V */
141 /* 0: line: 2.8V, speaker 8V */
142#define CS4215_MLB (1<<4) /* 1: Microphone: 20dB gain disabled */
143#define CS4215_RSRVD_1 (1<<5)
144
145/* Time Slot 2, Data Format Register */
146#define CS4215_DFR_LINEAR16 0
147#define CS4215_DFR_ULAW 1
148#define CS4215_DFR_ALAW 2
149#define CS4215_DFR_LINEAR8 3
150#define CS4215_DFR_STEREO (1<<2)
151static struct {
152 unsigned short freq;
153 unsigned char xtal;
154 unsigned char csval;
155} CS4215_FREQ[] = {
156 { 8000, (1 << 4), (0 << 3) },
157 { 16000, (1 << 4), (1 << 3) },
158 { 27429, (1 << 4), (2 << 3) }, /* Actually 24428.57 */
159 { 32000, (1 << 4), (3 << 3) },
160 /* { NA, (1 << 4), (4 << 3) }, */
161 /* { NA, (1 << 4), (5 << 3) }, */
162 { 48000, (1 << 4), (6 << 3) },
163 { 9600, (1 << 4), (7 << 3) },
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200164 { 5512, (2 << 4), (0 << 3) }, /* Actually 5512.5 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200165 { 11025, (2 << 4), (1 << 3) },
166 { 18900, (2 << 4), (2 << 3) },
167 { 22050, (2 << 4), (3 << 3) },
168 { 37800, (2 << 4), (4 << 3) },
169 { 44100, (2 << 4), (5 << 3) },
170 { 33075, (2 << 4), (6 << 3) },
171 { 6615, (2 << 4), (7 << 3) },
172 { 0, 0, 0}
173};
174
175#define CS4215_HPF (1<<7) /* High Pass Filter, 1: Enabled */
176
177#define CS4215_12_MASK 0xfcbf /* Mask off reserved bits in slot 1 & 2 */
178
179/* Time Slot 3, Serial Port Control register */
180#define CS4215_XEN (1<<0) /* 0: Enable serial output */
181#define CS4215_XCLK (1<<1) /* 1: Master mode: Generate SCLK */
182#define CS4215_BSEL_64 (0<<2) /* Bitrate: 64 bits per frame */
183#define CS4215_BSEL_128 (1<<2)
184#define CS4215_BSEL_256 (2<<2)
185#define CS4215_MCK_MAST (0<<4) /* Master clock */
186#define CS4215_MCK_XTL1 (1<<4) /* 24.576 MHz clock source */
187#define CS4215_MCK_XTL2 (2<<4) /* 16.9344 MHz clock source */
188#define CS4215_MCK_CLK1 (3<<4) /* Clockin, 256 x Fs */
189#define CS4215_MCK_CLK2 (4<<4) /* Clockin, see DFR */
190
191/* Time Slot 4, Test Register */
192#define CS4215_DAD (1<<0) /* 0:Digital-Dig loop, 1:Dig-Analog-Dig loop */
193#define CS4215_ENL (1<<1) /* Enable Loopback Testing */
194
195/* Time Slot 5, Parallel Port Register */
196/* Read only here and the same as the in data mode */
197
198/* Time Slot 6, Reserved */
199
200/* Time Slot 7, Version Register */
201#define CS4215_VERSION_MASK 0xf /* Known versions 0/C, 1/D, 2/E */
202
203/* Time Slot 8, Reserved */
204
205/*
206 * Data mode
207 */
208/* Time Slot 1-2: Left Channel Data, 2-3: Right Channel Data */
209
210/* Time Slot 5, Output Setting */
211#define CS4215_LO(v) v /* Left Output Attenuation 0x3f: -94.5 dB */
212#define CS4215_LE (1<<6) /* Line Out Enable */
213#define CS4215_HE (1<<7) /* Headphone Enable */
214
215/* Time Slot 6, Output Setting */
216#define CS4215_RO(v) v /* Right Output Attenuation 0x3f: -94.5 dB */
217#define CS4215_SE (1<<6) /* Speaker Enable */
218#define CS4215_ADI (1<<7) /* A/D Data Invalid: Busy in calibration */
219
220/* Time Slot 7, Input Setting */
221#define CS4215_LG(v) v /* Left Gain Setting 0xf: 22.5 dB */
222#define CS4215_IS (1<<4) /* Input Select: 1=Microphone, 0=Line */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200223#define CS4215_OVR (1<<5) /* 1: Over range condition occurred */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200224#define CS4215_PIO0 (1<<6) /* Parallel I/O 0 */
225#define CS4215_PIO1 (1<<7)
226
227/* Time Slot 8, Input Setting */
228#define CS4215_RG(v) v /* Right Gain Setting 0xf: 22.5 dB */
229#define CS4215_MA(v) (v<<4) /* Monitor Path Attenuation 0xf: mute */
230
231/***************************************************************************
232 DBRI specific definitions and structures
233****************************************************************************/
234
235/* DBRI main registers */
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200236#define REG0 0x00 /* Status and Control */
237#define REG1 0x04 /* Mode and Interrupt */
238#define REG2 0x08 /* Parallel IO */
239#define REG3 0x0c /* Test */
240#define REG8 0x20 /* Command Queue Pointer */
241#define REG9 0x24 /* Interrupt Queue Pointer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200242
243#define DBRI_NO_CMDS 64
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200244#define DBRI_INT_BLK 64
245#define DBRI_NO_DESCS 64
246#define DBRI_NO_PIPES 32
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +0200247#define DBRI_MAX_PIPE (DBRI_NO_PIPES - 1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200248
249#define DBRI_REC 0
250#define DBRI_PLAY 1
251#define DBRI_NO_STREAMS 2
252
253/* One transmit/receive descriptor */
Krzysztof Heltc2735442006-08-21 19:27:35 +0200254/* When ba != 0 descriptor is used */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200255struct dbri_mem {
256 volatile __u32 word1;
Krzysztof Helt16727d92006-08-17 16:59:28 +0200257 __u32 ba; /* Transmit/Receive Buffer Address */
258 __u32 nda; /* Next Descriptor Address */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200259 volatile __u32 word4;
260};
261
262/* This structure is in a DMA region where it can accessed by both
263 * the CPU and the DBRI
264 */
265struct dbri_dma {
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200266 s32 cmd[DBRI_NO_CMDS]; /* Place for commands */
Krzysztof Helt6fb98282006-08-16 12:54:29 +0200267 volatile s32 intr[DBRI_INT_BLK]; /* Interrupt field */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200268 struct dbri_mem desc[DBRI_NO_DESCS]; /* Xmit/receive descriptors */
269};
270
271#define dbri_dma_off(member, elem) \
272 ((u32)(unsigned long) \
273 (&(((struct dbri_dma *)0)->member[elem])))
274
275enum in_or_out { PIPEinput, PIPEoutput };
276
277struct dbri_pipe {
278 u32 sdp; /* SDP command word */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200279 int nextpipe; /* Next pipe in linked list */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200280 int length; /* Length of timeslot (bits) */
281 int first_desc; /* Index of first descriptor */
282 int desc; /* Index of active descriptor */
283 volatile __u32 *recv_fixed_ptr; /* Ptr to receive fixed data */
284};
285
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200286/* Per stream (playback or record) information */
Takashi Iwai475675d2005-11-17 15:11:51 +0100287struct dbri_streaminfo {
288 struct snd_pcm_substream *substream;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200289 u32 dvma_buffer; /* Device view of ALSA DMA buffer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200290 int size; /* Size of DMA buffer */
291 size_t offset; /* offset in user buffer */
292 int pipe; /* Data pipe used */
293 int left_gain; /* mixer elements */
294 int right_gain;
Takashi Iwai475675d2005-11-17 15:11:51 +0100295};
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200296
297/* This structure holds the information for both chips (DBRI & CS4215) */
Takashi Iwai475675d2005-11-17 15:11:51 +0100298struct snd_dbri {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200299 int regs_size, irq; /* Needed for unload */
300 struct sbus_dev *sdev; /* SBUS device info */
301 spinlock_t lock;
302
Krzysztof Helt16727d92006-08-17 16:59:28 +0200303 struct dbri_dma *dma; /* Pointer to our DMA block */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200304 u32 dma_dvma; /* DBRI visible DMA address */
305
306 void __iomem *regs; /* dbri HW regs */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200307 int dbri_irqp; /* intr queue pointer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200308
309 struct dbri_pipe pipes[DBRI_NO_PIPES]; /* DBRI's 32 data pipes */
Krzysztof Heltc2735442006-08-21 19:27:35 +0200310 int next_desc[DBRI_NO_DESCS]; /* Index of next desc, or -1 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200311 spinlock_t cmdlock; /* Protects cmd queue accesses */
312 s32 *cmdptr; /* Pointer to the last queued cmd */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200313
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200314 int chi_bpf;
315
316 struct cs4215 mm; /* mmcodec special info */
317 /* per stream (playback/record) info */
318 struct dbri_streaminfo stream_info[DBRI_NO_STREAMS];
Takashi Iwai475675d2005-11-17 15:11:51 +0100319};
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200320
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200321#define DBRI_MAX_VOLUME 63 /* Output volume */
322#define DBRI_MAX_GAIN 15 /* Input gain */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200323
324/* DBRI Reg0 - Status Control Register - defines. (Page 17) */
325#define D_P (1<<15) /* Program command & queue pointer valid */
326#define D_G (1<<14) /* Allow 4-Word SBus Burst */
327#define D_S (1<<13) /* Allow 16-Word SBus Burst */
328#define D_E (1<<12) /* Allow 8-Word SBus Burst */
329#define D_X (1<<7) /* Sanity Timer Disable */
330#define D_T (1<<6) /* Permit activation of the TE interface */
331#define D_N (1<<5) /* Permit activation of the NT interface */
332#define D_C (1<<4) /* Permit activation of the CHI interface */
333#define D_F (1<<3) /* Force Sanity Timer Time-Out */
334#define D_D (1<<2) /* Disable Master Mode */
335#define D_H (1<<1) /* Halt for Analysis */
336#define D_R (1<<0) /* Soft Reset */
337
338/* DBRI Reg1 - Mode and Interrupt Register - defines. (Page 18) */
339#define D_LITTLE_END (1<<8) /* Byte Order */
340#define D_BIG_END (0<<8) /* Byte Order */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200341#define D_MRR (1<<4) /* Multiple Error Ack on SBus (read only) */
342#define D_MLE (1<<3) /* Multiple Late Error on SBus (read only) */
343#define D_LBG (1<<2) /* Lost Bus Grant on SBus (read only) */
344#define D_MBE (1<<1) /* Burst Error on SBus (read only) */
345#define D_IR (1<<0) /* Interrupt Indicator (read only) */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200346
347/* DBRI Reg2 - Parallel IO Register - defines. (Page 18) */
348#define D_ENPIO3 (1<<7) /* Enable Pin 3 */
349#define D_ENPIO2 (1<<6) /* Enable Pin 2 */
350#define D_ENPIO1 (1<<5) /* Enable Pin 1 */
351#define D_ENPIO0 (1<<4) /* Enable Pin 0 */
352#define D_ENPIO (0xf0) /* Enable all the pins */
353#define D_PIO3 (1<<3) /* Pin 3: 1: Data mode, 0: Ctrl mode */
354#define D_PIO2 (1<<2) /* Pin 2: 1: Onboard PDN */
355#define D_PIO1 (1<<1) /* Pin 1: 0: Reset */
356#define D_PIO0 (1<<0) /* Pin 0: 1: Speakerbox PDN */
357
358/* DBRI Commands (Page 20) */
359#define D_WAIT 0x0 /* Stop execution */
360#define D_PAUSE 0x1 /* Flush long pipes */
361#define D_JUMP 0x2 /* New command queue */
362#define D_IIQ 0x3 /* Initialize Interrupt Queue */
363#define D_REX 0x4 /* Report command execution via interrupt */
364#define D_SDP 0x5 /* Setup Data Pipe */
365#define D_CDP 0x6 /* Continue Data Pipe (reread NULL Pointer) */
366#define D_DTS 0x7 /* Define Time Slot */
367#define D_SSP 0x8 /* Set short Data Pipe */
368#define D_CHI 0x9 /* Set CHI Global Mode */
369#define D_NT 0xa /* NT Command */
370#define D_TE 0xb /* TE Command */
371#define D_CDEC 0xc /* Codec setup */
372#define D_TEST 0xd /* No comment */
373#define D_CDM 0xe /* CHI Data mode command */
374
375/* Special bits for some commands */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200376#define D_PIPE(v) ((v)<<0) /* Pipe No.: 0-15 long, 16-21 short */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200377
378/* Setup Data Pipe */
379/* IRM */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200380#define D_SDP_2SAME (1<<18) /* Report 2nd time in a row value received */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200381#define D_SDP_CHANGE (2<<18) /* Report any changes */
382#define D_SDP_EVERY (3<<18) /* Report any changes */
383#define D_SDP_EOL (1<<17) /* EOL interrupt enable */
384#define D_SDP_IDLE (1<<16) /* HDLC idle interrupt enable */
385
386/* Pipe data MODE */
387#define D_SDP_MEM (0<<13) /* To/from memory */
388#define D_SDP_HDLC (2<<13)
389#define D_SDP_HDLC_D (3<<13) /* D Channel (prio control) */
390#define D_SDP_SER (4<<13) /* Serial to serial */
391#define D_SDP_FIXED (6<<13) /* Short only */
392#define D_SDP_MODE(v) ((v)&(7<<13))
393
394#define D_SDP_TO_SER (1<<12) /* Direction */
395#define D_SDP_FROM_SER (0<<12) /* Direction */
396#define D_SDP_MSB (1<<11) /* Bit order within Byte */
397#define D_SDP_LSB (0<<11) /* Bit order within Byte */
398#define D_SDP_P (1<<10) /* Pointer Valid */
399#define D_SDP_A (1<<8) /* Abort */
400#define D_SDP_C (1<<7) /* Clear */
401
402/* Define Time Slot */
403#define D_DTS_VI (1<<17) /* Valid Input Time-Slot Descriptor */
404#define D_DTS_VO (1<<16) /* Valid Output Time-Slot Descriptor */
405#define D_DTS_INS (1<<15) /* Insert Time Slot */
406#define D_DTS_DEL (0<<15) /* Delete Time Slot */
407#define D_DTS_PRVIN(v) ((v)<<10) /* Previous In Pipe */
408#define D_DTS_PRVOUT(v) ((v)<<5) /* Previous Out Pipe */
409
410/* Time Slot defines */
411#define D_TS_LEN(v) ((v)<<24) /* Number of bits in this time slot */
412#define D_TS_CYCLE(v) ((v)<<14) /* Bit Count at start of TS */
413#define D_TS_DI (1<<13) /* Data Invert */
414#define D_TS_1CHANNEL (0<<10) /* Single Channel / Normal mode */
415#define D_TS_MONITOR (2<<10) /* Monitor pipe */
416#define D_TS_NONCONTIG (3<<10) /* Non contiguous mode */
417#define D_TS_ANCHOR (7<<10) /* Starting short pipes */
418#define D_TS_MON(v) ((v)<<5) /* Monitor Pipe */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200419#define D_TS_NEXT(v) ((v)<<0) /* Pipe no.: 0-15 long, 16-21 short */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200420
421/* Concentration Highway Interface Modes */
422#define D_CHI_CHICM(v) ((v)<<16) /* Clock mode */
423#define D_CHI_IR (1<<15) /* Immediate Interrupt Report */
424#define D_CHI_EN (1<<14) /* CHIL Interrupt enabled */
425#define D_CHI_OD (1<<13) /* Open Drain Enable */
426#define D_CHI_FE (1<<12) /* Sample CHIFS on Rising Frame Edge */
427#define D_CHI_FD (1<<11) /* Frame Drive */
428#define D_CHI_BPF(v) ((v)<<0) /* Bits per Frame */
429
430/* NT: These are here for completeness */
431#define D_NT_FBIT (1<<17) /* Frame Bit */
432#define D_NT_NBF (1<<16) /* Number of bad frames to loose framing */
433#define D_NT_IRM_IMM (1<<15) /* Interrupt Report & Mask: Immediate */
434#define D_NT_IRM_EN (1<<14) /* Interrupt Report & Mask: Enable */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200435#define D_NT_ISNT (1<<13) /* Configure interface as NT */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200436#define D_NT_FT (1<<12) /* Fixed Timing */
437#define D_NT_EZ (1<<11) /* Echo Channel is Zeros */
438#define D_NT_IFA (1<<10) /* Inhibit Final Activation */
439#define D_NT_ACT (1<<9) /* Activate Interface */
440#define D_NT_MFE (1<<8) /* Multiframe Enable */
441#define D_NT_RLB(v) ((v)<<5) /* Remote Loopback */
442#define D_NT_LLB(v) ((v)<<2) /* Local Loopback */
443#define D_NT_FACT (1<<1) /* Force Activation */
444#define D_NT_ABV (1<<0) /* Activate Bipolar Violation */
445
446/* Codec Setup */
447#define D_CDEC_CK(v) ((v)<<24) /* Clock Select */
448#define D_CDEC_FED(v) ((v)<<12) /* FSCOD Falling Edge Delay */
449#define D_CDEC_RED(v) ((v)<<0) /* FSCOD Rising Edge Delay */
450
451/* Test */
452#define D_TEST_RAM(v) ((v)<<16) /* RAM Pointer */
453#define D_TEST_SIZE(v) ((v)<<11) /* */
454#define D_TEST_ROMONOFF 0x5 /* Toggle ROM opcode monitor on/off */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200455#define D_TEST_PROC 0x6 /* Microprocessor test */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200456#define D_TEST_SER 0x7 /* Serial-Controller test */
457#define D_TEST_RAMREAD 0x8 /* Copy from Ram to system memory */
458#define D_TEST_RAMWRITE 0x9 /* Copy into Ram from system memory */
459#define D_TEST_RAMBIST 0xa /* RAM Built-In Self Test */
460#define D_TEST_MCBIST 0xb /* Microcontroller Built-In Self Test */
461#define D_TEST_DUMP 0xe /* ROM Dump */
462
463/* CHI Data Mode */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200464#define D_CDM_THI (1 << 8) /* Transmit Data on CHIDR Pin */
465#define D_CDM_RHI (1 << 7) /* Receive Data on CHIDX Pin */
466#define D_CDM_RCE (1 << 6) /* Receive on Rising Edge of CHICK */
467#define D_CDM_XCE (1 << 2) /* Transmit Data on Rising Edge of CHICK */
468#define D_CDM_XEN (1 << 1) /* Transmit Highway Enable */
469#define D_CDM_REN (1 << 0) /* Receive Highway Enable */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200470
471/* The Interrupts */
472#define D_INTR_BRDY 1 /* Buffer Ready for processing */
473#define D_INTR_MINT 2 /* Marked Interrupt in RD/TD */
474#define D_INTR_IBEG 3 /* Flag to idle transition detected (HDLC) */
475#define D_INTR_IEND 4 /* Idle to flag transition detected (HDLC) */
476#define D_INTR_EOL 5 /* End of List */
477#define D_INTR_CMDI 6 /* Command has bean read */
478#define D_INTR_XCMP 8 /* Transmission of frame complete */
479#define D_INTR_SBRI 9 /* BRI status change info */
480#define D_INTR_FXDT 10 /* Fixed data change */
481#define D_INTR_CHIL 11 /* CHI lost frame sync (channel 36 only) */
482#define D_INTR_COLL 11 /* Unrecoverable D-Channel collision */
483#define D_INTR_DBYT 12 /* Dropped by frame slip */
484#define D_INTR_RBYT 13 /* Repeated by frame slip */
485#define D_INTR_LINT 14 /* Lost Interrupt */
486#define D_INTR_UNDR 15 /* DMA underrun */
487
488#define D_INTR_TE 32
489#define D_INTR_NT 34
490#define D_INTR_CHI 36
491#define D_INTR_CMD 38
492
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200493#define D_INTR_GETCHAN(v) (((v) >> 24) & 0x3f)
494#define D_INTR_GETCODE(v) (((v) >> 20) & 0xf)
495#define D_INTR_GETCMD(v) (((v) >> 16) & 0xf)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200496#define D_INTR_GETVAL(v) ((v) & 0xffff)
497#define D_INTR_GETRVAL(v) ((v) & 0xfffff)
498
499#define D_P_0 0 /* TE receive anchor */
500#define D_P_1 1 /* TE transmit anchor */
501#define D_P_2 2 /* NT transmit anchor */
502#define D_P_3 3 /* NT receive anchor */
503#define D_P_4 4 /* CHI send data */
504#define D_P_5 5 /* CHI receive data */
505#define D_P_6 6 /* */
506#define D_P_7 7 /* */
507#define D_P_8 8 /* */
508#define D_P_9 9 /* */
509#define D_P_10 10 /* */
510#define D_P_11 11 /* */
511#define D_P_12 12 /* */
512#define D_P_13 13 /* */
513#define D_P_14 14 /* */
514#define D_P_15 15 /* */
515#define D_P_16 16 /* CHI anchor pipe */
516#define D_P_17 17 /* CHI send */
517#define D_P_18 18 /* CHI receive */
518#define D_P_19 19 /* CHI receive */
519#define D_P_20 20 /* CHI receive */
520#define D_P_21 21 /* */
521#define D_P_22 22 /* */
522#define D_P_23 23 /* */
523#define D_P_24 24 /* */
524#define D_P_25 25 /* */
525#define D_P_26 26 /* */
526#define D_P_27 27 /* */
527#define D_P_28 28 /* */
528#define D_P_29 29 /* */
529#define D_P_30 30 /* */
530#define D_P_31 31 /* */
531
532/* Transmit descriptor defines */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200533#define DBRI_TD_F (1 << 31) /* End of Frame */
534#define DBRI_TD_D (1 << 30) /* Do not append CRC */
535#define DBRI_TD_CNT(v) ((v) << 16) /* Number of valid bytes in the buffer */
536#define DBRI_TD_B (1 << 15) /* Final interrupt */
537#define DBRI_TD_M (1 << 14) /* Marker interrupt */
538#define DBRI_TD_I (1 << 13) /* Transmit Idle Characters */
539#define DBRI_TD_FCNT(v) (v) /* Flag Count */
540#define DBRI_TD_UNR (1 << 3) /* Underrun: transmitter is out of data */
541#define DBRI_TD_ABT (1 << 2) /* Abort: frame aborted */
542#define DBRI_TD_TBC (1 << 0) /* Transmit buffer Complete */
543#define DBRI_TD_STATUS(v) ((v) & 0xff) /* Transmit status */
544 /* Maximum buffer size per TD: almost 8KB */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200545#define DBRI_TD_MAXCNT ((1 << 13) - 4)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200546
547/* Receive descriptor defines */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200548#define DBRI_RD_F (1 << 31) /* End of Frame */
549#define DBRI_RD_C (1 << 30) /* Completed buffer */
550#define DBRI_RD_B (1 << 15) /* Final interrupt */
551#define DBRI_RD_M (1 << 14) /* Marker interrupt */
552#define DBRI_RD_BCNT(v) (v) /* Buffer size */
553#define DBRI_RD_CRC (1 << 7) /* 0: CRC is correct */
554#define DBRI_RD_BBC (1 << 6) /* 1: Bad Byte received */
555#define DBRI_RD_ABT (1 << 5) /* Abort: frame aborted */
556#define DBRI_RD_OVRN (1 << 3) /* Overrun: data lost */
557#define DBRI_RD_STATUS(v) ((v) & 0xff) /* Receive status */
558#define DBRI_RD_CNT(v) (((v) >> 16) & 0x1fff) /* Valid bytes in the buffer */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200559
560/* stream_info[] access */
561/* Translate the ALSA direction into the array index */
562#define DBRI_STREAMNO(substream) \
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200563 (substream->stream == \
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200564 SNDRV_PCM_STREAM_PLAYBACK ? DBRI_PLAY: DBRI_REC)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200565
566/* Return a pointer to dbri_streaminfo */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200567#define DBRI_STREAM(dbri, substream) \
568 &dbri->stream_info[DBRI_STREAMNO(substream)]
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200569
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200570/*
571 * Short data pipes transmit LSB first. The CS4215 receives MSB first. Grrr.
572 * So we have to reverse the bits. Note: not all bit lengths are supported
573 */
574static __u32 reverse_bytes(__u32 b, int len)
575{
576 switch (len) {
577 case 32:
578 b = ((b & 0xffff0000) >> 16) | ((b & 0x0000ffff) << 16);
579 case 16:
580 b = ((b & 0xff00ff00) >> 8) | ((b & 0x00ff00ff) << 8);
581 case 8:
582 b = ((b & 0xf0f0f0f0) >> 4) | ((b & 0x0f0f0f0f) << 4);
583 case 4:
584 b = ((b & 0xcccccccc) >> 2) | ((b & 0x33333333) << 2);
585 case 2:
586 b = ((b & 0xaaaaaaaa) >> 1) | ((b & 0x55555555) << 1);
587 case 1:
588 case 0:
589 break;
590 default:
591 printk(KERN_ERR "DBRI reverse_bytes: unsupported length\n");
592 };
593
594 return b;
595}
596
597/*
598****************************************************************************
599************** DBRI initialization and command synchronization *************
600****************************************************************************
601
602Commands are sent to the DBRI by building a list of them in memory,
603then writing the address of the first list item to DBRI register 8.
Martin Habets43388292005-09-10 15:39:00 +0200604The list is terminated with a WAIT command, which generates a
605CPU interrupt to signal completion.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200606
607Since the DBRI can run in parallel with the CPU, several means of
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200608synchronization present themselves. The method implemented here uses
609the dbri_cmdwait() to wait for execution of batch of sent commands.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200610
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200611A circular command buffer is used here. A new command is being added
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200612while another can be executed. The scheme works by adding two WAIT commands
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200613after each sent batch of commands. When the next batch is prepared it is
614added after the WAIT commands then the WAITs are replaced with single JUMP
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200615command to the new batch. The the DBRI is forced to reread the last WAIT
616command (replaced by the JUMP by then). If the DBRI is still executing
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200617previous commands the request to reread the WAIT command is ignored.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200618
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200619Every time a routine wants to write commands to the DBRI, it must
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200620first call dbri_cmdlock() and get pointer to a free space in
621dbri->dma->cmd buffer. After this, the commands can be written to
622the buffer, and dbri_cmdsend() is called with the final pointer value
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200623to send them to the DBRI.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200624
625*/
626
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200627#define MAXLOOPS 20
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200628/*
629 * Wait for the current command string to execute
630 */
631static void dbri_cmdwait(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200632{
Martin Habets43388292005-09-10 15:39:00 +0200633 int maxloops = MAXLOOPS;
Krzysztof Heltea543f12006-09-05 20:25:05 +0200634 unsigned long flags;
Martin Habets43388292005-09-10 15:39:00 +0200635
Martin Habets43388292005-09-10 15:39:00 +0200636 /* Delay if previous commands are still being processed */
Krzysztof Heltea543f12006-09-05 20:25:05 +0200637 spin_lock_irqsave(&dbri->lock, flags);
638 while ((--maxloops) > 0 && (sbus_readl(dbri->regs + REG0) & D_P)) {
639 spin_unlock_irqrestore(&dbri->lock, flags);
Martin Habets43388292005-09-10 15:39:00 +0200640 msleep_interruptible(1);
Krzysztof Heltea543f12006-09-05 20:25:05 +0200641 spin_lock_irqsave(&dbri->lock, flags);
642 }
643 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200644
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200645 if (maxloops == 0)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200646 printk(KERN_ERR "DBRI: Chip never completed command buffer\n");
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200647 else
Martin Habets43388292005-09-10 15:39:00 +0200648 dprintk(D_CMD, "Chip completed command buffer (%d)\n",
649 MAXLOOPS - maxloops - 1);
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200650}
651/*
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200652 * Lock the command queue and return pointer to space for len cmd words
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200653 * It locks the cmdlock spinlock.
654 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200655static s32 *dbri_cmdlock(struct snd_dbri *dbri, int len)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200656{
657 /* Space for 2 WAIT cmds (replaced later by 1 JUMP cmd) */
658 len += 2;
659 spin_lock(&dbri->cmdlock);
660 if (dbri->cmdptr - dbri->dma->cmd + len < DBRI_NO_CMDS - 2)
661 return dbri->cmdptr + 2;
662 else if (len < sbus_readl(dbri->regs + REG8) - dbri->dma_dvma)
663 return dbri->dma->cmd;
664 else
665 printk(KERN_ERR "DBRI: no space for commands.");
Martin Habets43388292005-09-10 15:39:00 +0200666
Al Viroae97dd92006-09-24 23:42:57 +0100667 return NULL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200668}
669
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200670/*
Robert P. J. Daybeb7dd82007-05-09 07:14:03 +0200671 * Send prepared cmd string. It works by writing a JUMP cmd into
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200672 * the last WAIT cmd and force DBRI to reread the cmd.
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200673 * The JUMP cmd points to the new cmd string.
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200674 * It also releases the cmdlock spinlock.
Krzysztof Heltea543f12006-09-05 20:25:05 +0200675 *
Krzysztof Heltca405872006-12-18 14:41:03 +0100676 * Lock must be held before calling this.
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200677 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200678static void dbri_cmdsend(struct snd_dbri *dbri, s32 *cmd, int len)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200679{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200680 s32 tmp, addr;
681 static int wait_id = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200682
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200683 wait_id++;
684 wait_id &= 0xffff; /* restrict it to a 16 bit counter. */
685 *(cmd) = DBRI_CMD(D_WAIT, 1, wait_id);
686 *(cmd+1) = DBRI_CMD(D_WAIT, 1, wait_id);
687
688 /* Replace the last command with JUMP */
689 addr = dbri->dma_dvma + (cmd - len - dbri->dma->cmd) * sizeof(s32);
690 *(dbri->cmdptr+1) = addr;
691 *(dbri->cmdptr) = DBRI_CMD(D_JUMP, 0, 0);
692
693#ifdef DBRI_DEBUG
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200694 if (cmd > dbri->cmdptr) {
695 s32 *ptr;
696
Krzysztof Heltaaad3652006-08-28 12:59:23 +0200697 for (ptr = dbri->cmdptr; ptr < cmd+2; ptr++)
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200698 dprintk(D_CMD, "cmd: %lx:%08x\n",
699 (unsigned long)ptr, *ptr);
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200700 } else {
701 s32 *ptr = dbri->cmdptr;
702
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200703 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
Krzysztof Heltab93c7a2006-08-23 11:37:36 +0200704 ptr++;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200705 dprintk(D_CMD, "cmd: %lx:%08x\n", (unsigned long)ptr, *ptr);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200706 for (ptr = dbri->dma->cmd; ptr < cmd+2; ptr++)
707 dprintk(D_CMD, "cmd: %lx:%08x\n",
708 (unsigned long)ptr, *ptr);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200709 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200710#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200711
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200712 /* Reread the last command */
713 tmp = sbus_readl(dbri->regs + REG0);
714 tmp |= D_P;
715 sbus_writel(tmp, dbri->regs + REG0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200716
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200717 dbri->cmdptr = cmd;
718 spin_unlock(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200719}
720
721/* Lock must be held when calling this */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200722static void dbri_reset(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200723{
724 int i;
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200725 u32 tmp;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200726
727 dprintk(D_GEN, "reset 0:%x 2:%x 8:%x 9:%x\n",
728 sbus_readl(dbri->regs + REG0),
729 sbus_readl(dbri->regs + REG2),
730 sbus_readl(dbri->regs + REG8), sbus_readl(dbri->regs + REG9));
731
732 sbus_writel(D_R, dbri->regs + REG0); /* Soft Reset */
733 for (i = 0; (sbus_readl(dbri->regs + REG0) & D_R) && i < 64; i++)
734 udelay(10);
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200735
736 /* A brute approach - DBRI falls back to working burst size by itself
737 * On SS20 D_S does not work, so do not try so high. */
738 tmp = sbus_readl(dbri->regs + REG0);
739 tmp |= D_G | D_E;
740 tmp &= ~D_S;
741 sbus_writel(tmp, dbri->regs + REG0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200742}
743
744/* Lock must not be held before calling this */
Krzysztof Heltafeacfd2007-09-05 15:05:08 +0200745static void __devinit dbri_initialize(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200746{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200747 s32 *cmd;
Krzysztof Heltd1fdf072006-08-21 19:29:18 +0200748 u32 dma_addr;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200749 unsigned long flags;
750 int n;
751
752 spin_lock_irqsave(&dbri->lock, flags);
753
754 dbri_reset(dbri);
755
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200756 /* Initialize pipes */
757 for (n = 0; n < DBRI_NO_PIPES; n++)
758 dbri->pipes[n].desc = dbri->pipes[n].first_desc = -1;
759
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200760 spin_lock_init(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200761 /*
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200762 * Initialize the interrupt ring buffer.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200763 */
764 dma_addr = dbri->dma_dvma + dbri_dma_off(intr, 0);
Krzysztof Helt6fb98282006-08-16 12:54:29 +0200765 dbri->dma->intr[0] = dma_addr;
766 dbri->dbri_irqp = 1;
767 /*
768 * Set up the interrupt queue
769 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200770 spin_lock(&dbri->cmdlock);
771 cmd = dbri->cmdptr = dbri->dma->cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200772 *(cmd++) = DBRI_CMD(D_IIQ, 0, 0);
773 *(cmd++) = dma_addr;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200774 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
775 dbri->cmdptr = cmd;
776 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
777 *(cmd++) = DBRI_CMD(D_WAIT, 1, 0);
778 dma_addr = dbri->dma_dvma + dbri_dma_off(cmd, 0);
779 sbus_writel(dma_addr, dbri->regs + REG8);
780 spin_unlock(&dbri->cmdlock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200781
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200782 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Heltea543f12006-09-05 20:25:05 +0200783 dbri_cmdwait(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200784}
785
786/*
787****************************************************************************
788************************** DBRI data pipe management ***********************
789****************************************************************************
790
791While DBRI control functions use the command and interrupt buffers, the
792main data path takes the form of data pipes, which can be short (command
793and interrupt driven), or long (attached to DMA buffers). These functions
794provide a rudimentary means of setting up and managing the DBRI's pipes,
795but the calling functions have to make sure they respect the pipes' linked
796list ordering, among other things. The transmit and receive functions
797here interface closely with the transmit and receive interrupt code.
798
799*/
Krzysztof Heltcf68d212007-09-04 13:09:20 +0200800static inline int pipe_active(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200801{
802 return ((pipe >= 0) && (dbri->pipes[pipe].desc != -1));
803}
804
805/* reset_pipe(dbri, pipe)
806 *
807 * Called on an in-use pipe to clear anything being transmitted or received
808 * Lock must be held before calling this.
809 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200810static void reset_pipe(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200811{
812 int sdp;
813 int desc;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200814 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200815
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +0200816 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200817 printk(KERN_ERR "DBRI: reset_pipe called with "
818 "illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200819 return;
820 }
821
822 sdp = dbri->pipes[pipe].sdp;
823 if (sdp == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200824 printk(KERN_ERR "DBRI: reset_pipe called "
825 "on uninitialized pipe\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200826 return;
827 }
828
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200829 cmd = dbri_cmdlock(dbri, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200830 *(cmd++) = DBRI_CMD(D_SDP, 0, sdp | D_SDP_C | D_SDP_P);
831 *(cmd++) = 0;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200832 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
833 dbri_cmdsend(dbri, cmd, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200834
835 desc = dbri->pipes[pipe].first_desc;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200836 if (desc >= 0)
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200837 do {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200838 dbri->dma->desc[desc].ba = 0;
839 dbri->dma->desc[desc].nda = 0;
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200840 desc = dbri->next_desc[desc];
841 } while (desc != -1 && desc != dbri->pipes[pipe].first_desc);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200842
843 dbri->pipes[pipe].desc = -1;
844 dbri->pipes[pipe].first_desc = -1;
845}
846
Krzysztof Heltea543f12006-09-05 20:25:05 +0200847/*
848 * Lock must be held before calling this.
849 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200850static void setup_pipe(struct snd_dbri *dbri, int pipe, int sdp)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200851{
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +0200852 if (pipe < 0 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200853 printk(KERN_ERR "DBRI: setup_pipe called "
854 "with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200855 return;
856 }
857
858 if ((sdp & 0xf800) != sdp) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200859 printk(KERN_ERR "DBRI: setup_pipe called "
860 "with strange SDP value\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200861 /* sdp &= 0xf800; */
862 }
863
864 /* If this is a fixed receive pipe, arrange for an interrupt
865 * every time its data changes
866 */
867 if (D_SDP_MODE(sdp) == D_SDP_FIXED && !(sdp & D_SDP_TO_SER))
868 sdp |= D_SDP_CHANGE;
869
870 sdp |= D_PIPE(pipe);
871 dbri->pipes[pipe].sdp = sdp;
872 dbri->pipes[pipe].desc = -1;
873 dbri->pipes[pipe].first_desc = -1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200874
875 reset_pipe(dbri, pipe);
876}
877
Krzysztof Heltea543f12006-09-05 20:25:05 +0200878/*
879 * Lock must be held before calling this.
880 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200881static void link_time_slot(struct snd_dbri *dbri, int pipe,
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200882 int prevpipe, int nextpipe,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200883 int length, int cycle)
884{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200885 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200886 int val;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200887
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200888 if (pipe < 0 || pipe > DBRI_MAX_PIPE
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200889 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
890 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200891 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +0200892 "DBRI: link_time_slot called with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200893 return;
894 }
895
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200896 if (dbri->pipes[pipe].sdp == 0
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200897 || dbri->pipes[prevpipe].sdp == 0
898 || dbri->pipes[nextpipe].sdp == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200899 printk(KERN_ERR "DBRI: link_time_slot called "
900 "on uninitialized pipe\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200901 return;
902 }
903
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200904 dbri->pipes[prevpipe].nextpipe = pipe;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200905 dbri->pipes[pipe].nextpipe = nextpipe;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200906 dbri->pipes[pipe].length = length;
907
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200908 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200909
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200910 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
911 /* Deal with CHI special case:
912 * "If transmission on edges 0 or 1 is desired, then cycle n
913 * (where n = # of bit times per frame...) must be used."
914 * - DBRI data sheet, page 11
915 */
916 if (prevpipe == 16 && cycle == 0)
917 cycle = dbri->chi_bpf;
918
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200919 val = D_DTS_VO | D_DTS_INS | D_DTS_PRVOUT(prevpipe) | pipe;
920 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
921 *(cmd++) = 0;
922 *(cmd++) =
923 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
Krzysztof Helt294a30d2006-08-21 19:29:59 +0200924 } else {
925 val = D_DTS_VI | D_DTS_INS | D_DTS_PRVIN(prevpipe) | pipe;
926 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
927 *(cmd++) =
928 D_TS_LEN(length) | D_TS_CYCLE(cycle) | D_TS_NEXT(nextpipe);
929 *(cmd++) = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200930 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200931 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200932
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200933 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200934}
935
Krzysztof Heltea543f12006-09-05 20:25:05 +0200936#if 0
937/*
938 * Lock must be held before calling this.
939 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200940static void unlink_time_slot(struct snd_dbri *dbri, int pipe,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200941 enum in_or_out direction, int prevpipe,
942 int nextpipe)
943{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200944 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200945 int val;
946
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200947 if (pipe < 0 || pipe > DBRI_MAX_PIPE
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200948 || prevpipe < 0 || prevpipe > DBRI_MAX_PIPE
949 || nextpipe < 0 || nextpipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200950 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +0200951 "DBRI: unlink_time_slot called with illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200952 return;
953 }
954
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200955 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200956
957 if (direction == PIPEinput) {
958 val = D_DTS_VI | D_DTS_DEL | D_DTS_PRVIN(prevpipe) | pipe;
959 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
960 *(cmd++) = D_TS_NEXT(nextpipe);
961 *(cmd++) = 0;
962 } else {
963 val = D_DTS_VO | D_DTS_DEL | D_DTS_PRVOUT(prevpipe) | pipe;
964 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
965 *(cmd++) = 0;
966 *(cmd++) = D_TS_NEXT(nextpipe);
967 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200968 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200969
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200970 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200971}
Krzysztof Heltea543f12006-09-05 20:25:05 +0200972#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200973
974/* xmit_fixed() / recv_fixed()
975 *
976 * Transmit/receive data on a "fixed" pipe - i.e, one whose contents are not
977 * expected to change much, and which we don't need to buffer.
978 * The DBRI only interrupts us when the data changes (receive pipes),
979 * or only changes the data when this function is called (transmit pipes).
980 * Only short pipes (numbers 16-31) can be used in fixed data mode.
981 *
982 * These function operate on a 32-bit field, no matter how large
983 * the actual time slot is. The interrupt handler takes care of bit
984 * ordering and alignment. An 8-bit time slot will always end up
985 * in the low-order 8 bits, filled either MSB-first or LSB-first,
Krzysztof Heltea543f12006-09-05 20:25:05 +0200986 * depending on the settings passed to setup_pipe().
987 *
988 * Lock must not be held before calling it.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200989 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +0200990static void xmit_fixed(struct snd_dbri *dbri, int pipe, unsigned int data)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200991{
Krzysztof Helt1be54c82006-08-21 19:30:57 +0200992 s32 *cmd;
Krzysztof Heltea543f12006-09-05 20:25:05 +0200993 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200994
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +0200995 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
Martin Habets43388292005-09-10 15:39:00 +0200996 printk(KERN_ERR "DBRI: xmit_fixed: Illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +0200997 return;
998 }
999
1000 if (D_SDP_MODE(dbri->pipes[pipe].sdp) == 0) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001001 printk(KERN_ERR "DBRI: xmit_fixed: "
1002 "Uninitialized pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001003 return;
1004 }
1005
1006 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
Martin Habets43388292005-09-10 15:39:00 +02001007 printk(KERN_ERR "DBRI: xmit_fixed: Non-fixed pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001008 return;
1009 }
1010
1011 if (!(dbri->pipes[pipe].sdp & D_SDP_TO_SER)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001012 printk(KERN_ERR "DBRI: xmit_fixed: Called on receive pipe %d\n",
1013 pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001014 return;
1015 }
1016
1017 /* DBRI short pipes always transmit LSB first */
1018
1019 if (dbri->pipes[pipe].sdp & D_SDP_MSB)
1020 data = reverse_bytes(data, dbri->pipes[pipe].length);
1021
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001022 cmd = dbri_cmdlock(dbri, 3);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001023
1024 *(cmd++) = DBRI_CMD(D_SSP, 0, pipe);
1025 *(cmd++) = data;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001026 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001027
Krzysztof Heltea543f12006-09-05 20:25:05 +02001028 spin_lock_irqsave(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001029 dbri_cmdsend(dbri, cmd, 3);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001030 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001031 dbri_cmdwait(dbri);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001032
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001033}
1034
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001035static void recv_fixed(struct snd_dbri *dbri, int pipe, volatile __u32 *ptr)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001036{
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001037 if (pipe < 16 || pipe > DBRI_MAX_PIPE) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001038 printk(KERN_ERR "DBRI: recv_fixed called with "
1039 "illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001040 return;
1041 }
1042
1043 if (D_SDP_MODE(dbri->pipes[pipe].sdp) != D_SDP_FIXED) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001044 printk(KERN_ERR "DBRI: recv_fixed called on "
1045 "non-fixed pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001046 return;
1047 }
1048
1049 if (dbri->pipes[pipe].sdp & D_SDP_TO_SER) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001050 printk(KERN_ERR "DBRI: recv_fixed called on "
1051 "transmit pipe %d\n", pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001052 return;
1053 }
1054
1055 dbri->pipes[pipe].recv_fixed_ptr = ptr;
1056}
1057
1058/* setup_descs()
1059 *
1060 * Setup transmit/receive data on a "long" pipe - i.e, one associated
1061 * with a DMA buffer.
1062 *
1063 * Only pipe numbers 0-15 can be used in this mode.
1064 *
1065 * This function takes a stream number pointing to a data buffer,
1066 * and work by building chains of descriptors which identify the
1067 * data buffers. Buffers too large for a single descriptor will
1068 * be spread across multiple descriptors.
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001069 *
1070 * All descriptors create a ring buffer.
Krzysztof Heltea543f12006-09-05 20:25:05 +02001071 *
1072 * Lock must be held before calling this.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001073 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001074static int setup_descs(struct snd_dbri *dbri, int streamno, unsigned int period)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001075{
Takashi Iwai475675d2005-11-17 15:11:51 +01001076 struct dbri_streaminfo *info = &dbri->stream_info[streamno];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001077 __u32 dvma_buffer;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001078 int desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001079 int len;
1080 int first_desc = -1;
1081 int last_desc = -1;
1082
1083 if (info->pipe < 0 || info->pipe > 15) {
Martin Habets43388292005-09-10 15:39:00 +02001084 printk(KERN_ERR "DBRI: setup_descs: Illegal pipe number\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001085 return -2;
1086 }
1087
1088 if (dbri->pipes[info->pipe].sdp == 0) {
Martin Habets43388292005-09-10 15:39:00 +02001089 printk(KERN_ERR "DBRI: setup_descs: Uninitialized pipe %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001090 info->pipe);
1091 return -2;
1092 }
1093
1094 dvma_buffer = info->dvma_buffer;
1095 len = info->size;
1096
1097 if (streamno == DBRI_PLAY) {
1098 if (!(dbri->pipes[info->pipe].sdp & D_SDP_TO_SER)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001099 printk(KERN_ERR "DBRI: setup_descs: "
1100 "Called on receive pipe %d\n", info->pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001101 return -2;
1102 }
1103 } else {
1104 if (dbri->pipes[info->pipe].sdp & D_SDP_TO_SER) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001105 printk(KERN_ERR
Martin Habets43388292005-09-10 15:39:00 +02001106 "DBRI: setup_descs: Called on transmit pipe %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001107 info->pipe);
1108 return -2;
1109 }
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001110 /* Should be able to queue multiple buffers
1111 * to receive on a pipe
1112 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001113 if (pipe_active(dbri, info->pipe)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001114 printk(KERN_ERR "DBRI: recv_on_pipe: "
1115 "Called on active pipe %d\n", info->pipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001116 return -2;
1117 }
1118
1119 /* Make sure buffer size is multiple of four */
1120 len &= ~3;
1121 }
1122
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001123 /* Free descriptors if pipe has any */
1124 desc = dbri->pipes[info->pipe].first_desc;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001125 if (desc >= 0)
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001126 do {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001127 dbri->dma->desc[desc].ba = 0;
1128 dbri->dma->desc[desc].nda = 0;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001129 desc = dbri->next_desc[desc];
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001130 } while (desc != -1 &&
1131 desc != dbri->pipes[info->pipe].first_desc);
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02001132
1133 dbri->pipes[info->pipe].desc = -1;
1134 dbri->pipes[info->pipe].first_desc = -1;
1135
1136 desc = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001137 while (len > 0) {
1138 int mylen;
1139
1140 for (; desc < DBRI_NO_DESCS; desc++) {
Krzysztof Heltc2735442006-08-21 19:27:35 +02001141 if (!dbri->dma->desc[desc].ba)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001142 break;
1143 }
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001144
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001145 if (desc == DBRI_NO_DESCS) {
Martin Habets43388292005-09-10 15:39:00 +02001146 printk(KERN_ERR "DBRI: setup_descs: No descriptors\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001147 return -1;
1148 }
1149
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001150 if (len > DBRI_TD_MAXCNT)
1151 mylen = DBRI_TD_MAXCNT; /* 8KB - 4 */
1152 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001153 mylen = len;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001154
1155 if (mylen > period)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001156 mylen = period;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001157
Krzysztof Heltc2735442006-08-21 19:27:35 +02001158 dbri->next_desc[desc] = -1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001159 dbri->dma->desc[desc].ba = dvma_buffer;
1160 dbri->dma->desc[desc].nda = 0;
1161
1162 if (streamno == DBRI_PLAY) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001163 dbri->dma->desc[desc].word1 = DBRI_TD_CNT(mylen);
1164 dbri->dma->desc[desc].word4 = 0;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001165 dbri->dma->desc[desc].word1 |= DBRI_TD_F | DBRI_TD_B;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001166 } else {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001167 dbri->dma->desc[desc].word1 = 0;
1168 dbri->dma->desc[desc].word4 =
1169 DBRI_RD_B | DBRI_RD_BCNT(mylen);
1170 }
1171
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001172 if (first_desc == -1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001173 first_desc = desc;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001174 else {
Krzysztof Heltc2735442006-08-21 19:27:35 +02001175 dbri->next_desc[last_desc] = desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001176 dbri->dma->desc[last_desc].nda =
1177 dbri->dma_dvma + dbri_dma_off(desc, desc);
1178 }
1179
1180 last_desc = desc;
1181 dvma_buffer += mylen;
1182 len -= mylen;
1183 }
1184
1185 if (first_desc == -1 || last_desc == -1) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001186 printk(KERN_ERR "DBRI: setup_descs: "
1187 " Not enough descriptors available\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001188 return -1;
1189 }
1190
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001191 dbri->dma->desc[last_desc].nda =
1192 dbri->dma_dvma + dbri_dma_off(desc, first_desc);
1193 dbri->next_desc[last_desc] = first_desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001194 dbri->pipes[info->pipe].first_desc = first_desc;
1195 dbri->pipes[info->pipe].desc = first_desc;
1196
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001197#ifdef DBRI_DEBUG
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001198 for (desc = first_desc; desc != -1;) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001199 dprintk(D_DESC, "DESC %d: %08x %08x %08x %08x\n",
1200 desc,
1201 dbri->dma->desc[desc].word1,
1202 dbri->dma->desc[desc].ba,
1203 dbri->dma->desc[desc].nda, dbri->dma->desc[desc].word4);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001204 desc = dbri->next_desc[desc];
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001205 if (desc == first_desc)
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001206 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001207 }
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001208#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001209 return 0;
1210}
1211
1212/*
1213****************************************************************************
1214************************** DBRI - CHI interface ****************************
1215****************************************************************************
1216
1217The CHI is a four-wire (clock, frame sync, data in, data out) time-division
1218multiplexed serial interface which the DBRI can operate in either master
1219(give clock/frame sync) or slave (take clock/frame sync) mode.
1220
1221*/
1222
1223enum master_or_slave { CHImaster, CHIslave };
1224
Krzysztof Heltea543f12006-09-05 20:25:05 +02001225/*
1226 * Lock must not be held before calling it.
1227 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001228static void reset_chi(struct snd_dbri *dbri,
1229 enum master_or_slave master_or_slave,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001230 int bits_per_frame)
1231{
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001232 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001233 int val;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001234
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001235 /* Set CHI Anchor: Pipe 16 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001236
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001237 cmd = dbri_cmdlock(dbri, 4);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001238 val = D_DTS_VO | D_DTS_VI | D_DTS_INS
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001239 | D_DTS_PRVIN(16) | D_PIPE(16) | D_DTS_PRVOUT(16);
1240 *(cmd++) = DBRI_CMD(D_DTS, 0, val);
1241 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1242 *(cmd++) = D_TS_ANCHOR | D_TS_NEXT(16);
1243 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1244 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001245
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001246 dbri->pipes[16].sdp = 1;
1247 dbri->pipes[16].nextpipe = 16;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001248
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001249 cmd = dbri_cmdlock(dbri, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001250
1251 if (master_or_slave == CHIslave) {
1252 /* Setup DBRI for CHI Slave - receive clock, frame sync (FS)
1253 *
1254 * CHICM = 0 (slave mode, 8 kHz frame rate)
1255 * IR = give immediate CHI status interrupt
1256 * EN = give CHI status interrupt upon change
1257 */
1258 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(0));
1259 } else {
1260 /* Setup DBRI for CHI Master - generate clock, FS
1261 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001262 * BPF = bits per 8 kHz frame
1263 * 12.288 MHz / CHICM_divisor = clock rate
1264 * FD = 1 - drive CHIFS on rising edge of CHICK
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001265 */
1266 int clockrate = bits_per_frame * 8;
1267 int divisor = 12288 / clockrate;
1268
1269 if (divisor > 255 || divisor * clockrate != 12288)
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001270 printk(KERN_ERR "DBRI: illegal bits_per_frame "
1271 "in setup_chi\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001272
1273 *(cmd++) = DBRI_CMD(D_CHI, 0, D_CHI_CHICM(divisor) | D_CHI_FD
1274 | D_CHI_BPF(bits_per_frame));
1275 }
1276
1277 dbri->chi_bpf = bits_per_frame;
1278
1279 /* CHI Data Mode
1280 *
1281 * RCE = 0 - receive on falling edge of CHICK
1282 * XCE = 1 - transmit on rising edge of CHICK
1283 * XEN = 1 - enable transmitter
1284 * REN = 1 - enable receiver
1285 */
1286
1287 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
1288 *(cmd++) = DBRI_CMD(D_CDM, 0, D_CDM_XCE | D_CDM_XEN | D_CDM_REN);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001289 *(cmd++) = DBRI_CMD(D_PAUSE, 0, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001290
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001291 dbri_cmdsend(dbri, cmd, 4);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001292}
1293
1294/*
1295****************************************************************************
1296*********************** CS4215 audio codec management **********************
1297****************************************************************************
1298
1299In the standard SPARC audio configuration, the CS4215 codec is attached
1300to the DBRI via the CHI interface and few of the DBRI's PIO pins.
1301
Krzysztof Heltea543f12006-09-05 20:25:05 +02001302 * Lock must not be held before calling it.
1303
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001304*/
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02001305static __devinit void cs4215_setup_pipes(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001306{
Krzysztof Heltea543f12006-09-05 20:25:05 +02001307 unsigned long flags;
1308
1309 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001310 /*
1311 * Data mode:
1312 * Pipe 4: Send timeslots 1-4 (audio data)
1313 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1314 * Pipe 6: Receive timeslots 1-4 (audio data)
1315 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1316 * interrupt, and the rest of the data (slot 5 and 8) is
1317 * not relevant for us (only for doublechecking).
1318 *
1319 * Control mode:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001320 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001321 * Pipe 18: Receive timeslot 1 (clb).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001322 * Pipe 19: Receive timeslot 7 (version).
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001323 */
1324
1325 setup_pipe(dbri, 4, D_SDP_MEM | D_SDP_TO_SER | D_SDP_MSB);
1326 setup_pipe(dbri, 20, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1327 setup_pipe(dbri, 6, D_SDP_MEM | D_SDP_FROM_SER | D_SDP_MSB);
1328 setup_pipe(dbri, 21, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1329
1330 setup_pipe(dbri, 17, D_SDP_FIXED | D_SDP_TO_SER | D_SDP_MSB);
1331 setup_pipe(dbri, 18, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
1332 setup_pipe(dbri, 19, D_SDP_FIXED | D_SDP_FROM_SER | D_SDP_MSB);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001333 spin_unlock_irqrestore(&dbri->lock, flags);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001334
1335 dbri_cmdwait(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001336}
1337
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02001338static __devinit int cs4215_init_data(struct cs4215 *mm)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001339{
1340 /*
1341 * No action, memory resetting only.
1342 *
1343 * Data Time Slot 5-8
1344 * Speaker,Line and Headphone enable. Gain set to the half.
1345 * Input is mike.
1346 */
1347 mm->data[0] = CS4215_LO(0x20) | CS4215_HE | CS4215_LE;
1348 mm->data[1] = CS4215_RO(0x20) | CS4215_SE;
1349 mm->data[2] = CS4215_LG(0x8) | CS4215_IS | CS4215_PIO0 | CS4215_PIO1;
1350 mm->data[3] = CS4215_RG(0x8) | CS4215_MA(0xf);
1351
1352 /*
1353 * Control Time Slot 1-4
1354 * 0: Default I/O voltage scale
1355 * 1: 8 bit ulaw, 8kHz, mono, high pass filter disabled
1356 * 2: Serial enable, CHI master, 128 bits per frame, clock 1
1357 * 3: Tests disabled
1358 */
1359 mm->ctrl[0] = CS4215_RSRVD_1 | CS4215_MLB;
1360 mm->ctrl[1] = CS4215_DFR_ULAW | CS4215_FREQ[0].csval;
1361 mm->ctrl[2] = CS4215_XCLK | CS4215_BSEL_128 | CS4215_FREQ[0].xtal;
1362 mm->ctrl[3] = 0;
1363
1364 mm->status = 0;
1365 mm->version = 0xff;
1366 mm->precision = 8; /* For ULAW */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001367 mm->channels = 1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001368
1369 return 0;
1370}
1371
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001372static void cs4215_setdata(struct snd_dbri *dbri, int muted)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001373{
1374 if (muted) {
1375 dbri->mm.data[0] |= 63;
1376 dbri->mm.data[1] |= 63;
1377 dbri->mm.data[2] &= ~15;
1378 dbri->mm.data[3] &= ~15;
1379 } else {
1380 /* Start by setting the playback attenuation. */
Takashi Iwai475675d2005-11-17 15:11:51 +01001381 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001382 int left_gain = info->left_gain & 0x3f;
1383 int right_gain = info->right_gain & 0x3f;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001384
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001385 dbri->mm.data[0] &= ~0x3f; /* Reset the volume bits */
1386 dbri->mm.data[1] &= ~0x3f;
1387 dbri->mm.data[0] |= (DBRI_MAX_VOLUME - left_gain);
1388 dbri->mm.data[1] |= (DBRI_MAX_VOLUME - right_gain);
1389
1390 /* Now set the recording gain. */
1391 info = &dbri->stream_info[DBRI_REC];
Krzysztof Helt470f1f1a2006-08-21 19:28:16 +02001392 left_gain = info->left_gain & 0xf;
1393 right_gain = info->right_gain & 0xf;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001394 dbri->mm.data[2] |= CS4215_LG(left_gain);
1395 dbri->mm.data[3] |= CS4215_RG(right_gain);
1396 }
1397
1398 xmit_fixed(dbri, 20, *(int *)dbri->mm.data);
1399}
1400
1401/*
1402 * Set the CS4215 to data mode.
1403 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001404static void cs4215_open(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001405{
1406 int data_width;
1407 u32 tmp;
Krzysztof Heltea543f12006-09-05 20:25:05 +02001408 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001409
1410 dprintk(D_MM, "cs4215_open: %d channels, %d bits\n",
1411 dbri->mm.channels, dbri->mm.precision);
1412
1413 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1414 * to make sure this takes. This avoids clicking noises.
1415 */
1416
1417 cs4215_setdata(dbri, 1);
1418 udelay(125);
1419
1420 /*
1421 * Data mode:
1422 * Pipe 4: Send timeslots 1-4 (audio data)
1423 * Pipe 20: Send timeslots 5-8 (part of ctrl data)
1424 * Pipe 6: Receive timeslots 1-4 (audio data)
1425 * Pipe 21: Receive timeslots 6-7. We can only receive 20 bits via
1426 * interrupt, and the rest of the data (slot 5 and 8) is
1427 * not relevant for us (only for doublechecking).
1428 *
1429 * Just like in control mode, the time slots are all offset by eight
1430 * bits. The CS4215, it seems, observes TSIN (the delayed signal)
1431 * even if it's the CHI master. Don't ask me...
1432 */
Krzysztof Heltea543f12006-09-05 20:25:05 +02001433 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001434 tmp = sbus_readl(dbri->regs + REG0);
1435 tmp &= ~(D_C); /* Disable CHI */
1436 sbus_writel(tmp, dbri->regs + REG0);
1437
1438 /* Switch CS4215 to data mode - set PIO3 to 1 */
1439 sbus_writel(D_ENPIO | D_PIO1 | D_PIO3 |
1440 (dbri->mm.onboard ? D_PIO0 : D_PIO2), dbri->regs + REG2);
1441
1442 reset_chi(dbri, CHIslave, 128);
1443
1444 /* Note: this next doesn't work for 8-bit stereo, because the two
1445 * channels would be on timeslots 1 and 3, with 2 and 4 idle.
1446 * (See CS4215 datasheet Fig 15)
1447 *
1448 * DBRI non-contiguous mode would be required to make this work.
1449 */
1450 data_width = dbri->mm.channels * dbri->mm.precision;
1451
Krzysztof Helt294a30d2006-08-21 19:29:59 +02001452 link_time_slot(dbri, 4, 16, 16, data_width, dbri->mm.offset);
1453 link_time_slot(dbri, 20, 4, 16, 32, dbri->mm.offset + 32);
1454 link_time_slot(dbri, 6, 16, 16, data_width, dbri->mm.offset);
1455 link_time_slot(dbri, 21, 6, 16, 16, dbri->mm.offset + 40);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001456
1457 /* FIXME: enable CHI after _setdata? */
1458 tmp = sbus_readl(dbri->regs + REG0);
1459 tmp |= D_C; /* Enable CHI */
1460 sbus_writel(tmp, dbri->regs + REG0);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001461 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001462
1463 cs4215_setdata(dbri, 0);
1464}
1465
1466/*
1467 * Send the control information (i.e. audio format)
1468 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001469static int cs4215_setctrl(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001470{
1471 int i, val;
1472 u32 tmp;
Krzysztof Heltea543f12006-09-05 20:25:05 +02001473 unsigned long flags;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001474
1475 /* FIXME - let the CPU do something useful during these delays */
1476
1477 /* Temporarily mute outputs, and wait 1/8000 sec (125 us)
1478 * to make sure this takes. This avoids clicking noises.
1479 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001480 cs4215_setdata(dbri, 1);
1481 udelay(125);
1482
1483 /*
1484 * Enable Control mode: Set DBRI's PIO3 (4215's D/~C) to 0, then wait
1485 * 12 cycles <= 12/(5512.5*64) sec = 34.01 usec
1486 */
1487 val = D_ENPIO | D_PIO1 | (dbri->mm.onboard ? D_PIO0 : D_PIO2);
1488 sbus_writel(val, dbri->regs + REG2);
1489 dprintk(D_MM, "cs4215_setctrl: reg2=0x%x\n", val);
1490 udelay(34);
1491
1492 /* In Control mode, the CS4215 is a slave device, so the DBRI must
1493 * operate as CHI master, supplying clocking and frame synchronization.
1494 *
1495 * In Data mode, however, the CS4215 must be CHI master to insure
1496 * that its data stream is synchronous with its codec.
1497 *
1498 * The upshot of all this? We start by putting the DBRI into master
1499 * mode, program the CS4215 in Control mode, then switch the CS4215
1500 * into Data mode and put the DBRI into slave mode. Various timing
1501 * requirements must be observed along the way.
1502 *
1503 * Oh, and one more thing, on a SPARCStation 20 (and maybe
1504 * others?), the addressing of the CS4215's time slots is
1505 * offset by eight bits, so we add eight to all the "cycle"
1506 * values in the Define Time Slot (DTS) commands. This is
1507 * done in hardware by a TI 248 that delays the DBRI->4215
1508 * frame sync signal by eight clock cycles. Anybody know why?
1509 */
Krzysztof Heltea543f12006-09-05 20:25:05 +02001510 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001511 tmp = sbus_readl(dbri->regs + REG0);
1512 tmp &= ~D_C; /* Disable CHI */
1513 sbus_writel(tmp, dbri->regs + REG0);
1514
1515 reset_chi(dbri, CHImaster, 128);
1516
1517 /*
1518 * Control mode:
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001519 * Pipe 17: Send timeslots 1-4 (slots 5-8 are read only)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001520 * Pipe 18: Receive timeslot 1 (clb).
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001521 * Pipe 19: Receive timeslot 7 (version).
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001522 */
1523
Krzysztof Helt294a30d2006-08-21 19:29:59 +02001524 link_time_slot(dbri, 17, 16, 16, 32, dbri->mm.offset);
1525 link_time_slot(dbri, 18, 16, 16, 8, dbri->mm.offset);
1526 link_time_slot(dbri, 19, 18, 16, 8, dbri->mm.offset + 48);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001527 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001528
1529 /* Wait for the chip to echo back CLB (Control Latch Bit) as zero */
1530 dbri->mm.ctrl[0] &= ~CS4215_CLB;
1531 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1532
Krzysztof Heltea543f12006-09-05 20:25:05 +02001533 spin_lock_irqsave(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001534 tmp = sbus_readl(dbri->regs + REG0);
1535 tmp |= D_C; /* Enable CHI */
1536 sbus_writel(tmp, dbri->regs + REG0);
Krzysztof Heltea543f12006-09-05 20:25:05 +02001537 spin_unlock_irqrestore(&dbri->lock, flags);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001538
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001539 for (i = 10; ((dbri->mm.status & 0xe4) != 0x20); --i)
Martin Habets43388292005-09-10 15:39:00 +02001540 msleep_interruptible(1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001541
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001542 if (i == 0) {
1543 dprintk(D_MM, "CS4215 didn't respond to CLB (0x%02x)\n",
1544 dbri->mm.status);
1545 return -1;
1546 }
1547
1548 /* Disable changes to our copy of the version number, as we are about
1549 * to leave control mode.
1550 */
1551 recv_fixed(dbri, 19, NULL);
1552
1553 /* Terminate CS4215 control mode - data sheet says
1554 * "Set CLB=1 and send two more frames of valid control info"
1555 */
1556 dbri->mm.ctrl[0] |= CS4215_CLB;
1557 xmit_fixed(dbri, 17, *(int *)dbri->mm.ctrl);
1558
1559 /* Two frames of control info @ 8kHz frame rate = 250 us delay */
1560 udelay(250);
1561
1562 cs4215_setdata(dbri, 0);
1563
1564 return 0;
1565}
1566
1567/*
1568 * Setup the codec with the sampling rate, audio format and number of
1569 * channels.
1570 * As part of the process we resend the settings for the data
1571 * timeslots as well.
1572 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001573static int cs4215_prepare(struct snd_dbri *dbri, unsigned int rate,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001574 snd_pcm_format_t format, unsigned int channels)
1575{
1576 int freq_idx;
1577 int ret = 0;
1578
1579 /* Lookup index for this rate */
1580 for (freq_idx = 0; CS4215_FREQ[freq_idx].freq != 0; freq_idx++) {
1581 if (CS4215_FREQ[freq_idx].freq == rate)
1582 break;
1583 }
1584 if (CS4215_FREQ[freq_idx].freq != rate) {
1585 printk(KERN_WARNING "DBRI: Unsupported rate %d Hz\n", rate);
1586 return -1;
1587 }
1588
1589 switch (format) {
1590 case SNDRV_PCM_FORMAT_MU_LAW:
1591 dbri->mm.ctrl[1] = CS4215_DFR_ULAW;
1592 dbri->mm.precision = 8;
1593 break;
1594 case SNDRV_PCM_FORMAT_A_LAW:
1595 dbri->mm.ctrl[1] = CS4215_DFR_ALAW;
1596 dbri->mm.precision = 8;
1597 break;
1598 case SNDRV_PCM_FORMAT_U8:
1599 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR8;
1600 dbri->mm.precision = 8;
1601 break;
1602 case SNDRV_PCM_FORMAT_S16_BE:
1603 dbri->mm.ctrl[1] = CS4215_DFR_LINEAR16;
1604 dbri->mm.precision = 16;
1605 break;
1606 default:
1607 printk(KERN_WARNING "DBRI: Unsupported format %d\n", format);
1608 return -1;
1609 }
1610
1611 /* Add rate parameters */
1612 dbri->mm.ctrl[1] |= CS4215_FREQ[freq_idx].csval;
1613 dbri->mm.ctrl[2] = CS4215_XCLK |
1614 CS4215_BSEL_128 | CS4215_FREQ[freq_idx].xtal;
1615
1616 dbri->mm.channels = channels;
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001617 if (channels == 2)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001618 dbri->mm.ctrl[1] |= CS4215_DFR_STEREO;
1619
1620 ret = cs4215_setctrl(dbri);
1621 if (ret == 0)
1622 cs4215_open(dbri); /* set codec to data mode */
1623
1624 return ret;
1625}
1626
1627/*
1628 *
1629 */
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02001630static __devinit int cs4215_init(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001631{
1632 u32 reg2 = sbus_readl(dbri->regs + REG2);
1633 dprintk(D_MM, "cs4215_init: reg2=0x%x\n", reg2);
1634
1635 /* Look for the cs4215 chips */
1636 if (reg2 & D_PIO2) {
1637 dprintk(D_MM, "Onboard CS4215 detected\n");
1638 dbri->mm.onboard = 1;
1639 }
1640 if (reg2 & D_PIO0) {
1641 dprintk(D_MM, "Speakerbox detected\n");
1642 dbri->mm.onboard = 0;
1643
1644 if (reg2 & D_PIO2) {
1645 printk(KERN_INFO "DBRI: Using speakerbox / "
1646 "ignoring onboard mmcodec.\n");
1647 sbus_writel(D_ENPIO2, dbri->regs + REG2);
1648 }
1649 }
1650
1651 if (!(reg2 & (D_PIO0 | D_PIO2))) {
1652 printk(KERN_ERR "DBRI: no mmcodec found.\n");
1653 return -EIO;
1654 }
1655
1656 cs4215_setup_pipes(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001657 cs4215_init_data(&dbri->mm);
1658
1659 /* Enable capture of the status & version timeslots. */
1660 recv_fixed(dbri, 18, &dbri->mm.status);
1661 recv_fixed(dbri, 19, &dbri->mm.version);
1662
1663 dbri->mm.offset = dbri->mm.onboard ? 0 : 8;
1664 if (cs4215_setctrl(dbri) == -1 || dbri->mm.version == 0xff) {
1665 dprintk(D_MM, "CS4215 failed probe at offset %d\n",
1666 dbri->mm.offset);
1667 return -EIO;
1668 }
1669 dprintk(D_MM, "Found CS4215 at offset %d\n", dbri->mm.offset);
1670
1671 return 0;
1672}
1673
1674/*
1675****************************************************************************
1676*************************** DBRI interrupt handler *************************
1677****************************************************************************
1678
1679The DBRI communicates with the CPU mainly via a circular interrupt
1680buffer. When an interrupt is signaled, the CPU walks through the
1681buffer and calls dbri_process_one_interrupt() for each interrupt word.
1682Complicated interrupts are handled by dedicated functions (which
1683appear first in this file). Any pending interrupts can be serviced by
1684calling dbri_process_interrupt_buffer(), which works even if the CPU's
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001685interrupts are disabled.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001686
1687*/
1688
1689/* xmit_descs()
1690 *
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001691 * Starts transmitting the current TD's for recording/playing.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001692 * For playback, ALSA has filled the DMA memory with new data (we hope).
1693 */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001694static void xmit_descs(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001695{
Takashi Iwai475675d2005-11-17 15:11:51 +01001696 struct dbri_streaminfo *info;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001697 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001698 unsigned long flags;
1699 int first_td;
1700
1701 if (dbri == NULL)
1702 return; /* Disabled */
1703
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001704 info = &dbri->stream_info[DBRI_REC];
1705 spin_lock_irqsave(&dbri->lock, flags);
1706
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001707 if (info->pipe >= 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001708 first_td = dbri->pipes[info->pipe].first_desc;
1709
1710 dprintk(D_DESC, "xmit_descs rec @ TD %d\n", first_td);
1711
1712 /* Stream could be closed by the time we run. */
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001713 if (first_td >= 0) {
1714 cmd = dbri_cmdlock(dbri, 2);
1715 *(cmd++) = DBRI_CMD(D_SDP, 0,
1716 dbri->pipes[info->pipe].sdp
1717 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001718 *(cmd++) = dbri->dma_dvma +
1719 dbri_dma_off(desc, first_td);
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001720 dbri_cmdsend(dbri, cmd, 2);
1721
1722 /* Reset our admin of the pipe. */
1723 dbri->pipes[info->pipe].desc = first_td;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001724 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001725 }
1726
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001727 info = &dbri->stream_info[DBRI_PLAY];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001728
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001729 if (info->pipe >= 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001730 first_td = dbri->pipes[info->pipe].first_desc;
1731
1732 dprintk(D_DESC, "xmit_descs play @ TD %d\n", first_td);
1733
1734 /* Stream could be closed by the time we run. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001735 if (first_td >= 0) {
1736 cmd = dbri_cmdlock(dbri, 2);
1737 *(cmd++) = DBRI_CMD(D_SDP, 0,
1738 dbri->pipes[info->pipe].sdp
1739 | D_SDP_P | D_SDP_EVERY | D_SDP_C);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001740 *(cmd++) = dbri->dma_dvma +
1741 dbri_dma_off(desc, first_td);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001742 dbri_cmdsend(dbri, cmd, 2);
1743
Krzysztof Heltaaad3652006-08-28 12:59:23 +02001744 /* Reset our admin of the pipe. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001745 dbri->pipes[info->pipe].desc = first_td;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001746 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001747 }
Krzysztof Heltea543f12006-09-05 20:25:05 +02001748
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001749 spin_unlock_irqrestore(&dbri->lock, flags);
1750}
1751
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001752/* transmission_complete_intr()
1753 *
1754 * Called by main interrupt handler when DBRI signals transmission complete
1755 * on a pipe (interrupt triggered by the B bit in a transmit descriptor).
1756 *
Martin Habets43388292005-09-10 15:39:00 +02001757 * Walks through the pipe's list of transmit buffer descriptors and marks
1758 * them as available. Stops when the first descriptor is found without
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001759 * TBC (Transmit Buffer Complete) set, or we've run through them all.
Martin Habets43388292005-09-10 15:39:00 +02001760 *
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001761 * The DMA buffers are not released. They form a ring buffer and
1762 * they are filled by ALSA while others are transmitted by DMA.
1763 *
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001764 */
1765
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001766static void transmission_complete_intr(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001767{
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001768 struct dbri_streaminfo *info = &dbri->stream_info[DBRI_PLAY];
1769 int td = dbri->pipes[pipe].desc;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001770 int status;
1771
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001772 while (td >= 0) {
1773 if (td >= DBRI_NO_DESCS) {
1774 printk(KERN_ERR "DBRI: invalid td on pipe %d\n", pipe);
1775 return;
1776 }
1777
1778 status = DBRI_TD_STATUS(dbri->dma->desc[td].word4);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001779 if (!(status & DBRI_TD_TBC))
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001780 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001781
1782 dprintk(D_INT, "TD %d, status 0x%02x\n", td, status);
1783
1784 dbri->dma->desc[td].word4 = 0; /* Reset it for next time. */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001785 info->offset += DBRI_RD_CNT(dbri->dma->desc[td].word1);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001786
Krzysztof Heltc2735442006-08-21 19:27:35 +02001787 td = dbri->next_desc[td];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001788 dbri->pipes[pipe].desc = td;
1789 }
1790
1791 /* Notify ALSA */
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001792 spin_unlock(&dbri->lock);
1793 snd_pcm_period_elapsed(info->substream);
1794 spin_lock(&dbri->lock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001795}
1796
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001797static void reception_complete_intr(struct snd_dbri *dbri, int pipe)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001798{
Takashi Iwai475675d2005-11-17 15:11:51 +01001799 struct dbri_streaminfo *info;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001800 int rd = dbri->pipes[pipe].desc;
1801 s32 status;
1802
1803 if (rd < 0 || rd >= DBRI_NO_DESCS) {
1804 printk(KERN_ERR "DBRI: invalid rd on pipe %d\n", pipe);
1805 return;
1806 }
1807
Krzysztof Heltc2735442006-08-21 19:27:35 +02001808 dbri->pipes[pipe].desc = dbri->next_desc[rd];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001809 status = dbri->dma->desc[rd].word1;
1810 dbri->dma->desc[rd].word1 = 0; /* Reset it for next time. */
1811
1812 info = &dbri->stream_info[DBRI_REC];
1813 info->offset += DBRI_RD_CNT(status);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001814
1815 /* FIXME: Check status */
1816
1817 dprintk(D_INT, "Recv RD %d, status 0x%02x, len %d\n",
1818 rd, DBRI_RD_STATUS(status), DBRI_RD_CNT(status));
1819
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001820 /* Notify ALSA */
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001821 spin_unlock(&dbri->lock);
1822 snd_pcm_period_elapsed(info->substream);
1823 spin_lock(&dbri->lock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001824}
1825
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001826static void dbri_process_one_interrupt(struct snd_dbri *dbri, int x)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001827{
1828 int val = D_INTR_GETVAL(x);
1829 int channel = D_INTR_GETCHAN(x);
1830 int command = D_INTR_GETCMD(x);
1831 int code = D_INTR_GETCODE(x);
1832#ifdef DBRI_DEBUG
1833 int rval = D_INTR_GETRVAL(x);
1834#endif
1835
1836 if (channel == D_INTR_CMD) {
1837 dprintk(D_CMD, "INTR: Command: %-5s Value:%d\n",
1838 cmds[command], val);
1839 } else {
1840 dprintk(D_INT, "INTR: Chan:%d Code:%d Val:%#x\n",
1841 channel, code, rval);
1842 }
1843
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001844 switch (code) {
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001845 case D_INTR_CMDI:
1846 if (command != D_WAIT)
1847 printk(KERN_ERR "DBRI: Command read interrupt\n");
1848 break;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001849 case D_INTR_BRDY:
1850 reception_complete_intr(dbri, channel);
1851 break;
1852 case D_INTR_XCMP:
1853 case D_INTR_MINT:
1854 transmission_complete_intr(dbri, channel);
1855 break;
1856 case D_INTR_UNDR:
1857 /* UNDR - Transmission underrun
1858 * resend SDP command with clear pipe bit (C) set
1859 */
1860 {
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001861 /* FIXME: do something useful in case of underrun */
1862 printk(KERN_ERR "DBRI: Underrun error\n");
1863#if 0
1864 s32 *cmd;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001865 int pipe = channel;
1866 int td = dbri->pipes[pipe].desc;
1867
1868 dbri->dma->desc[td].word4 = 0;
1869 cmd = dbri_cmdlock(dbri, NoGetLock);
1870 *(cmd++) = DBRI_CMD(D_SDP, 0,
1871 dbri->pipes[pipe].sdp
1872 | D_SDP_P | D_SDP_C | D_SDP_2SAME);
1873 *(cmd++) = dbri->dma_dvma + dbri_dma_off(desc, td);
1874 dbri_cmdsend(dbri, cmd);
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001875#endif
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001876 }
1877 break;
1878 case D_INTR_FXDT:
1879 /* FXDT - Fixed data change */
1880 if (dbri->pipes[channel].sdp & D_SDP_MSB)
1881 val = reverse_bytes(val, dbri->pipes[channel].length);
1882
1883 if (dbri->pipes[channel].recv_fixed_ptr)
1884 *(dbri->pipes[channel].recv_fixed_ptr) = val;
1885 break;
1886 default:
1887 if (channel != D_INTR_CMD)
1888 printk(KERN_WARNING
1889 "DBRI: Ignored Interrupt: %d (0x%x)\n", code, x);
1890 }
1891}
1892
1893/* dbri_process_interrupt_buffer advances through the DBRI's interrupt
1894 * buffer until it finds a zero word (indicating nothing more to do
1895 * right now). Non-zero words require processing and are handed off
Krzysztof Helt1be54c82006-08-21 19:30:57 +02001896 * to dbri_process_one_interrupt AFTER advancing the pointer.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001897 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001898static void dbri_process_interrupt_buffer(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001899{
1900 s32 x;
1901
1902 while ((x = dbri->dma->intr[dbri->dbri_irqp]) != 0) {
1903 dbri->dma->intr[dbri->dbri_irqp] = 0;
1904 dbri->dbri_irqp++;
Krzysztof Helt6fb98282006-08-16 12:54:29 +02001905 if (dbri->dbri_irqp == DBRI_INT_BLK)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001906 dbri->dbri_irqp = 1;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001907
1908 dbri_process_one_interrupt(dbri, x);
1909 }
1910}
1911
David Howells7d12e782006-10-05 14:55:46 +01001912static irqreturn_t snd_dbri_interrupt(int irq, void *dev_id)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001913{
Takashi Iwai475675d2005-11-17 15:11:51 +01001914 struct snd_dbri *dbri = dev_id;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001915 static int errcnt = 0;
1916 int x;
1917
1918 if (dbri == NULL)
1919 return IRQ_NONE;
1920 spin_lock(&dbri->lock);
1921
1922 /*
1923 * Read it, so the interrupt goes away.
1924 */
1925 x = sbus_readl(dbri->regs + REG1);
1926
1927 if (x & (D_MRR | D_MLE | D_LBG | D_MBE)) {
1928 u32 tmp;
1929
1930 if (x & D_MRR)
1931 printk(KERN_ERR
1932 "DBRI: Multiple Error Ack on SBus reg1=0x%x\n",
1933 x);
1934 if (x & D_MLE)
1935 printk(KERN_ERR
1936 "DBRI: Multiple Late Error on SBus reg1=0x%x\n",
1937 x);
1938 if (x & D_LBG)
1939 printk(KERN_ERR
1940 "DBRI: Lost Bus Grant on SBus reg1=0x%x\n", x);
1941 if (x & D_MBE)
1942 printk(KERN_ERR
1943 "DBRI: Burst Error on SBus reg1=0x%x\n", x);
1944
1945 /* Some of these SBus errors cause the chip's SBus circuitry
1946 * to be disabled, so just re-enable and try to keep going.
1947 *
1948 * The only one I've seen is MRR, which will be triggered
1949 * if you let a transmit pipe underrun, then try to CDP it.
1950 *
Martin Habets43388292005-09-10 15:39:00 +02001951 * If these things persist, we reset the chip.
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001952 */
1953 if ((++errcnt) % 10 == 0) {
1954 dprintk(D_INT, "Interrupt errors exceeded.\n");
1955 dbri_reset(dbri);
1956 } else {
1957 tmp = sbus_readl(dbri->regs + REG0);
1958 tmp &= ~(D_D);
1959 sbus_writel(tmp, dbri->regs + REG0);
1960 }
1961 }
1962
1963 dbri_process_interrupt_buffer(dbri);
1964
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001965 spin_unlock(&dbri->lock);
1966
1967 return IRQ_HANDLED;
1968}
1969
1970/****************************************************************************
1971 PCM Interface
1972****************************************************************************/
Takashi Iwai475675d2005-11-17 15:11:51 +01001973static struct snd_pcm_hardware snd_dbri_pcm_hw = {
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001974 .info = SNDRV_PCM_INFO_MMAP |
1975 SNDRV_PCM_INFO_INTERLEAVED |
1976 SNDRV_PCM_INFO_BLOCK_TRANSFER |
1977 SNDRV_PCM_INFO_MMAP_VALID,
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02001978 .formats = SNDRV_PCM_FMTBIT_MU_LAW |
1979 SNDRV_PCM_FMTBIT_A_LAW |
1980 SNDRV_PCM_FMTBIT_U8 |
1981 SNDRV_PCM_FMTBIT_S16_BE,
1982 .rates = SNDRV_PCM_RATE_8000_48000 | SNDRV_PCM_RATE_5512,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001983 .rate_min = 5512,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001984 .rate_max = 48000,
1985 .channels_min = 1,
1986 .channels_max = 2,
Krzysztof Heltcf68d212007-09-04 13:09:20 +02001987 .buffer_bytes_max = 64 * 1024,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02001988 .period_bytes_min = 1,
1989 .period_bytes_max = DBRI_TD_MAXCNT,
1990 .periods_min = 1,
1991 .periods_max = 1024,
1992};
1993
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02001994static int snd_hw_rule_format(struct snd_pcm_hw_params *params,
1995 struct snd_pcm_hw_rule *rule)
1996{
1997 struct snd_interval *c = hw_param_interval(params,
1998 SNDRV_PCM_HW_PARAM_CHANNELS);
1999 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2000 struct snd_mask fmt;
2001
2002 snd_mask_any(&fmt);
2003 if (c->min > 1) {
2004 fmt.bits[0] &= SNDRV_PCM_FMTBIT_S16_BE;
2005 return snd_mask_refine(f, &fmt);
2006 }
2007 return 0;
2008}
2009
2010static int snd_hw_rule_channels(struct snd_pcm_hw_params *params,
2011 struct snd_pcm_hw_rule *rule)
2012{
2013 struct snd_interval *c = hw_param_interval(params,
2014 SNDRV_PCM_HW_PARAM_CHANNELS);
2015 struct snd_mask *f = hw_param_mask(params, SNDRV_PCM_HW_PARAM_FORMAT);
2016 struct snd_interval ch;
2017
2018 snd_interval_any(&ch);
2019 if (!(f->bits[0] & SNDRV_PCM_FMTBIT_S16_BE)) {
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002020 ch.min = 1;
2021 ch.max = 1;
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002022 ch.integer = 1;
2023 return snd_interval_refine(c, &ch);
2024 }
2025 return 0;
2026}
2027
Takashi Iwai475675d2005-11-17 15:11:51 +01002028static int snd_dbri_open(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002029{
Takashi Iwai475675d2005-11-17 15:11:51 +01002030 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2031 struct snd_pcm_runtime *runtime = substream->runtime;
2032 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002033 unsigned long flags;
2034
2035 dprintk(D_USR, "open audio output.\n");
2036 runtime->hw = snd_dbri_pcm_hw;
2037
2038 spin_lock_irqsave(&dbri->lock, flags);
2039 info->substream = substream;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002040 info->offset = 0;
2041 info->dvma_buffer = 0;
2042 info->pipe = -1;
2043 spin_unlock_irqrestore(&dbri->lock, flags);
2044
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002045 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_CHANNELS,
Al Viroae97dd92006-09-24 23:42:57 +01002046 snd_hw_rule_format, NULL, SNDRV_PCM_HW_PARAM_FORMAT,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002047 -1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002048 snd_pcm_hw_rule_add(runtime, 0, SNDRV_PCM_HW_PARAM_FORMAT,
2049 snd_hw_rule_channels, NULL,
Krzysztof Heltab93c7a2006-08-23 11:37:36 +02002050 SNDRV_PCM_HW_PARAM_CHANNELS,
2051 -1);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002052
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002053 cs4215_open(dbri);
2054
2055 return 0;
2056}
2057
Takashi Iwai475675d2005-11-17 15:11:51 +01002058static int snd_dbri_close(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002059{
Takashi Iwai475675d2005-11-17 15:11:51 +01002060 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2061 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002062
2063 dprintk(D_USR, "close audio output.\n");
2064 info->substream = NULL;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002065 info->offset = 0;
2066
2067 return 0;
2068}
2069
Takashi Iwai475675d2005-11-17 15:11:51 +01002070static int snd_dbri_hw_params(struct snd_pcm_substream *substream,
2071 struct snd_pcm_hw_params *hw_params)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002072{
Takashi Iwai475675d2005-11-17 15:11:51 +01002073 struct snd_pcm_runtime *runtime = substream->runtime;
2074 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2075 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002076 int direction;
2077 int ret;
2078
2079 /* set sampling rate, audio format and number of channels */
2080 ret = cs4215_prepare(dbri, params_rate(hw_params),
2081 params_format(hw_params),
2082 params_channels(hw_params));
2083 if (ret != 0)
2084 return ret;
2085
2086 if ((ret = snd_pcm_lib_malloc_pages(substream,
2087 params_buffer_bytes(hw_params))) < 0) {
Martin Habets43388292005-09-10 15:39:00 +02002088 printk(KERN_ERR "malloc_pages failed with %d\n", ret);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002089 return ret;
2090 }
2091
2092 /* hw_params can get called multiple times. Only map the DMA once.
2093 */
2094 if (info->dvma_buffer == 0) {
2095 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2096 direction = SBUS_DMA_TODEVICE;
2097 else
2098 direction = SBUS_DMA_FROMDEVICE;
2099
2100 info->dvma_buffer = sbus_map_single(dbri->sdev,
2101 runtime->dma_area,
2102 params_buffer_bytes(hw_params),
2103 direction);
2104 }
2105
2106 direction = params_buffer_bytes(hw_params);
2107 dprintk(D_USR, "hw_params: %d bytes, dvma=%x\n",
2108 direction, info->dvma_buffer);
2109 return 0;
2110}
2111
Takashi Iwai475675d2005-11-17 15:11:51 +01002112static int snd_dbri_hw_free(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002113{
Takashi Iwai475675d2005-11-17 15:11:51 +01002114 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2115 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002116 int direction;
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02002117
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002118 dprintk(D_USR, "hw_free.\n");
2119
2120 /* hw_free can get called multiple times. Only unmap the DMA once.
2121 */
2122 if (info->dvma_buffer) {
2123 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2124 direction = SBUS_DMA_TODEVICE;
2125 else
2126 direction = SBUS_DMA_FROMDEVICE;
2127
2128 sbus_unmap_single(dbri->sdev, info->dvma_buffer,
2129 substream->runtime->buffer_size, direction);
2130 info->dvma_buffer = 0;
2131 }
Krzysztof Helt99dabfe2006-08-28 13:00:45 +02002132 if (info->pipe != -1) {
2133 reset_pipe(dbri, info->pipe);
2134 info->pipe = -1;
2135 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002136
2137 return snd_pcm_lib_free_pages(substream);
2138}
2139
Takashi Iwai475675d2005-11-17 15:11:51 +01002140static int snd_dbri_prepare(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002141{
Takashi Iwai475675d2005-11-17 15:11:51 +01002142 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2143 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002144 int ret;
2145
2146 info->size = snd_pcm_lib_buffer_bytes(substream);
2147 if (DBRI_STREAMNO(substream) == DBRI_PLAY)
2148 info->pipe = 4; /* Send pipe */
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002149 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002150 info->pipe = 6; /* Receive pipe */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002151
2152 spin_lock_irq(&dbri->lock);
Krzysztof Heltaaad3652006-08-28 12:59:23 +02002153 info->offset = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002154
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002155 /* Setup the all the transmit/receive descriptors to cover the
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002156 * whole DMA buffer.
2157 */
2158 ret = setup_descs(dbri, DBRI_STREAMNO(substream),
2159 snd_pcm_lib_period_bytes(substream));
2160
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002161 spin_unlock_irq(&dbri->lock);
2162
2163 dprintk(D_USR, "prepare audio output. %d bytes\n", info->size);
2164 return ret;
2165}
2166
Takashi Iwai475675d2005-11-17 15:11:51 +01002167static int snd_dbri_trigger(struct snd_pcm_substream *substream, int cmd)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002168{
Takashi Iwai475675d2005-11-17 15:11:51 +01002169 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2170 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002171 int ret = 0;
2172
2173 switch (cmd) {
2174 case SNDRV_PCM_TRIGGER_START:
2175 dprintk(D_USR, "start audio, period is %d bytes\n",
2176 (int)snd_pcm_lib_period_bytes(substream));
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002177 /* Re-submit the TDs. */
2178 xmit_descs(dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002179 break;
2180 case SNDRV_PCM_TRIGGER_STOP:
2181 dprintk(D_USR, "stop audio.\n");
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002182 reset_pipe(dbri, info->pipe);
2183 break;
2184 default:
2185 ret = -EINVAL;
2186 }
2187
2188 return ret;
2189}
2190
Takashi Iwai475675d2005-11-17 15:11:51 +01002191static snd_pcm_uframes_t snd_dbri_pointer(struct snd_pcm_substream *substream)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002192{
Takashi Iwai475675d2005-11-17 15:11:51 +01002193 struct snd_dbri *dbri = snd_pcm_substream_chip(substream);
2194 struct dbri_streaminfo *info = DBRI_STREAM(dbri, substream);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002195 snd_pcm_uframes_t ret;
2196
2197 ret = bytes_to_frames(substream->runtime, info->offset)
2198 % substream->runtime->buffer_size;
Krzysztof Helt1be54c82006-08-21 19:30:57 +02002199 dprintk(D_USR, "I/O pointer: %ld frames of %ld.\n",
2200 ret, substream->runtime->buffer_size);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002201 return ret;
2202}
2203
Takashi Iwai475675d2005-11-17 15:11:51 +01002204static struct snd_pcm_ops snd_dbri_ops = {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002205 .open = snd_dbri_open,
2206 .close = snd_dbri_close,
2207 .ioctl = snd_pcm_lib_ioctl,
2208 .hw_params = snd_dbri_hw_params,
2209 .hw_free = snd_dbri_hw_free,
2210 .prepare = snd_dbri_prepare,
2211 .trigger = snd_dbri_trigger,
2212 .pointer = snd_dbri_pointer,
2213};
2214
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002215static int __devinit snd_dbri_pcm(struct snd_card *card)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002216{
Takashi Iwai475675d2005-11-17 15:11:51 +01002217 struct snd_pcm *pcm;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002218 int err;
2219
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002220 if ((err = snd_pcm_new(card,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002221 /* ID */ "sun_dbri",
2222 /* device */ 0,
2223 /* playback count */ 1,
2224 /* capture count */ 1, &pcm)) < 0)
2225 return err;
2226 snd_assert(pcm != NULL, return -EINVAL);
2227
2228 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_PLAYBACK, &snd_dbri_ops);
2229 snd_pcm_set_ops(pcm, SNDRV_PCM_STREAM_CAPTURE, &snd_dbri_ops);
2230
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002231 pcm->private_data = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002232 pcm->info_flags = 0;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002233 strcpy(pcm->name, card->shortname);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002234
2235 if ((err = snd_pcm_lib_preallocate_pages_for_all(pcm,
2236 SNDRV_DMA_TYPE_CONTINUOUS,
2237 snd_dma_continuous_data(GFP_KERNEL),
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002238 64 * 1024, 64 * 1024)) < 0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002239 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002240
2241 return 0;
2242}
2243
2244/*****************************************************************************
2245 Mixer interface
2246*****************************************************************************/
2247
Takashi Iwai475675d2005-11-17 15:11:51 +01002248static int snd_cs4215_info_volume(struct snd_kcontrol *kcontrol,
2249 struct snd_ctl_elem_info *uinfo)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002250{
2251 uinfo->type = SNDRV_CTL_ELEM_TYPE_INTEGER;
2252 uinfo->count = 2;
2253 uinfo->value.integer.min = 0;
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002254 if (kcontrol->private_value == DBRI_PLAY)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002255 uinfo->value.integer.max = DBRI_MAX_VOLUME;
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002256 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002257 uinfo->value.integer.max = DBRI_MAX_GAIN;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002258 return 0;
2259}
2260
Takashi Iwai475675d2005-11-17 15:11:51 +01002261static int snd_cs4215_get_volume(struct snd_kcontrol *kcontrol,
2262 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002263{
Takashi Iwai475675d2005-11-17 15:11:51 +01002264 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
2265 struct dbri_streaminfo *info;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002266 snd_assert(dbri != NULL, return -EINVAL);
2267 info = &dbri->stream_info[kcontrol->private_value];
2268 snd_assert(info != NULL, return -EINVAL);
2269
2270 ucontrol->value.integer.value[0] = info->left_gain;
2271 ucontrol->value.integer.value[1] = info->right_gain;
2272 return 0;
2273}
2274
Takashi Iwai475675d2005-11-17 15:11:51 +01002275static int snd_cs4215_put_volume(struct snd_kcontrol *kcontrol,
2276 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002277{
Takashi Iwai475675d2005-11-17 15:11:51 +01002278 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002279 struct dbri_streaminfo *info =
2280 &dbri->stream_info[kcontrol->private_value];
Takashi Iwai3b892462007-11-15 16:17:24 +01002281 unsigned int vol[2];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002282 int changed = 0;
2283
Takashi Iwai3b892462007-11-15 16:17:24 +01002284 vol[0] = ucontrol->value.integer.value[0];
2285 vol[1] = ucontrol->value.integer.value[1];
2286 if (kcontrol->private_value == DBRI_PLAY) {
2287 if (vol[0] > DBRI_MAX_VOLUME || vol[1] > DBRI_MAX_VOLUME)
2288 return -EINVAL;
2289 } else {
2290 if (vol[0] > DBRI_MAX_GAIN || vol[1] > DBRI_MAX_GAIN)
2291 return -EINVAL;
2292 }
2293
Takashi Iwai4581aa32007-11-20 18:31:22 +01002294 if (info->left_gain != vol[0]) {
2295 info->left_gain = vol[0];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002296 changed = 1;
2297 }
Takashi Iwai4581aa32007-11-20 18:31:22 +01002298 if (info->right_gain != vol[1]) {
2299 info->right_gain = vol[1];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002300 changed = 1;
2301 }
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002302 if (changed) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002303 /* First mute outputs, and wait 1/8000 sec (125 us)
2304 * to make sure this takes. This avoids clicking noises.
2305 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002306 cs4215_setdata(dbri, 1);
2307 udelay(125);
2308 cs4215_setdata(dbri, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002309 }
2310 return changed;
2311}
2312
Takashi Iwai475675d2005-11-17 15:11:51 +01002313static int snd_cs4215_info_single(struct snd_kcontrol *kcontrol,
2314 struct snd_ctl_elem_info *uinfo)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002315{
2316 int mask = (kcontrol->private_value >> 16) & 0xff;
2317
2318 uinfo->type = (mask == 1) ?
2319 SNDRV_CTL_ELEM_TYPE_BOOLEAN : SNDRV_CTL_ELEM_TYPE_INTEGER;
2320 uinfo->count = 1;
2321 uinfo->value.integer.min = 0;
2322 uinfo->value.integer.max = mask;
2323 return 0;
2324}
2325
Takashi Iwai475675d2005-11-17 15:11:51 +01002326static int snd_cs4215_get_single(struct snd_kcontrol *kcontrol,
2327 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002328{
Takashi Iwai475675d2005-11-17 15:11:51 +01002329 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002330 int elem = kcontrol->private_value & 0xff;
2331 int shift = (kcontrol->private_value >> 8) & 0xff;
2332 int mask = (kcontrol->private_value >> 16) & 0xff;
2333 int invert = (kcontrol->private_value >> 24) & 1;
2334 snd_assert(dbri != NULL, return -EINVAL);
2335
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002336 if (elem < 4)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002337 ucontrol->value.integer.value[0] =
2338 (dbri->mm.data[elem] >> shift) & mask;
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002339 else
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002340 ucontrol->value.integer.value[0] =
2341 (dbri->mm.ctrl[elem - 4] >> shift) & mask;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002342
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002343 if (invert == 1)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002344 ucontrol->value.integer.value[0] =
2345 mask - ucontrol->value.integer.value[0];
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002346 return 0;
2347}
2348
Takashi Iwai475675d2005-11-17 15:11:51 +01002349static int snd_cs4215_put_single(struct snd_kcontrol *kcontrol,
2350 struct snd_ctl_elem_value *ucontrol)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002351{
Takashi Iwai475675d2005-11-17 15:11:51 +01002352 struct snd_dbri *dbri = snd_kcontrol_chip(kcontrol);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002353 int elem = kcontrol->private_value & 0xff;
2354 int shift = (kcontrol->private_value >> 8) & 0xff;
2355 int mask = (kcontrol->private_value >> 16) & 0xff;
2356 int invert = (kcontrol->private_value >> 24) & 1;
2357 int changed = 0;
2358 unsigned short val;
2359 snd_assert(dbri != NULL, return -EINVAL);
2360
2361 val = (ucontrol->value.integer.value[0] & mask);
2362 if (invert == 1)
2363 val = mask - val;
2364 val <<= shift;
2365
2366 if (elem < 4) {
2367 dbri->mm.data[elem] = (dbri->mm.data[elem] &
2368 ~(mask << shift)) | val;
2369 changed = (val != dbri->mm.data[elem]);
2370 } else {
2371 dbri->mm.ctrl[elem - 4] = (dbri->mm.ctrl[elem - 4] &
2372 ~(mask << shift)) | val;
2373 changed = (val != dbri->mm.ctrl[elem - 4]);
2374 }
2375
2376 dprintk(D_GEN, "put_single: mask=0x%x, changed=%d, "
2377 "mixer-value=%ld, mm-value=0x%x\n",
2378 mask, changed, ucontrol->value.integer.value[0],
2379 dbri->mm.data[elem & 3]);
2380
2381 if (changed) {
2382 /* First mute outputs, and wait 1/8000 sec (125 us)
2383 * to make sure this takes. This avoids clicking noises.
2384 */
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002385 cs4215_setdata(dbri, 1);
2386 udelay(125);
2387 cs4215_setdata(dbri, 0);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002388 }
2389 return changed;
2390}
2391
2392/* Entries 0-3 map to the 4 data timeslots, entries 4-7 map to the 4 control
2393 timeslots. Shift is the bit offset in the timeslot, mask defines the
2394 number of bits. invert is a boolean for use with attenuation.
2395 */
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002396#define CS4215_SINGLE(xname, entry, shift, mask, invert) \
2397{ .iface = SNDRV_CTL_ELEM_IFACE_MIXER, .name = (xname), \
2398 .info = snd_cs4215_info_single, \
2399 .get = snd_cs4215_get_single, .put = snd_cs4215_put_single, \
2400 .private_value = (entry) | ((shift) << 8) | ((mask) << 16) | \
2401 ((invert) << 24) },
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002402
Takashi Iwai475675d2005-11-17 15:11:51 +01002403static struct snd_kcontrol_new dbri_controls[] __devinitdata = {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002404 {
2405 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2406 .name = "Playback Volume",
2407 .info = snd_cs4215_info_volume,
2408 .get = snd_cs4215_get_volume,
2409 .put = snd_cs4215_put_volume,
2410 .private_value = DBRI_PLAY,
2411 },
2412 CS4215_SINGLE("Headphone switch", 0, 7, 1, 0)
2413 CS4215_SINGLE("Line out switch", 0, 6, 1, 0)
2414 CS4215_SINGLE("Speaker switch", 1, 6, 1, 0)
2415 {
2416 .iface = SNDRV_CTL_ELEM_IFACE_MIXER,
2417 .name = "Capture Volume",
2418 .info = snd_cs4215_info_volume,
2419 .get = snd_cs4215_get_volume,
2420 .put = snd_cs4215_put_volume,
2421 .private_value = DBRI_REC,
2422 },
2423 /* FIXME: mic/line switch */
2424 CS4215_SINGLE("Line in switch", 2, 4, 1, 0)
2425 CS4215_SINGLE("High Pass Filter switch", 5, 7, 1, 0)
2426 CS4215_SINGLE("Monitor Volume", 3, 4, 0xf, 1)
2427 CS4215_SINGLE("Mic boost", 4, 4, 1, 1)
2428};
2429
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002430static int __devinit snd_dbri_mixer(struct snd_card *card)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002431{
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002432 int idx, err;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002433 struct snd_dbri *dbri;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002434
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002435 snd_assert(card != NULL && card->private_data != NULL, return -EINVAL);
2436 dbri = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002437
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002438 strcpy(card->mixername, card->shortname);
2439
Tobias Klauser6c2d8b52006-09-29 02:00:21 -07002440 for (idx = 0; idx < ARRAY_SIZE(dbri_controls); idx++) {
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002441 err = snd_ctl_add(card,
2442 snd_ctl_new1(&dbri_controls[idx], dbri));
2443 if (err < 0)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002444 return err;
2445 }
2446
2447 for (idx = DBRI_REC; idx < DBRI_NO_STREAMS; idx++) {
2448 dbri->stream_info[idx].left_gain = 0;
2449 dbri->stream_info[idx].right_gain = 0;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002450 }
2451
2452 return 0;
2453}
2454
2455/****************************************************************************
2456 /proc interface
2457****************************************************************************/
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002458static void dbri_regs_read(struct snd_info_entry *entry,
2459 struct snd_info_buffer *buffer)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002460{
Takashi Iwai475675d2005-11-17 15:11:51 +01002461 struct snd_dbri *dbri = entry->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002462
2463 snd_iprintf(buffer, "REG0: 0x%x\n", sbus_readl(dbri->regs + REG0));
2464 snd_iprintf(buffer, "REG2: 0x%x\n", sbus_readl(dbri->regs + REG2));
2465 snd_iprintf(buffer, "REG8: 0x%x\n", sbus_readl(dbri->regs + REG8));
2466 snd_iprintf(buffer, "REG9: 0x%x\n", sbus_readl(dbri->regs + REG9));
2467}
2468
2469#ifdef DBRI_DEBUG
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002470static void dbri_debug_read(struct snd_info_entry *entry,
Takashi Iwai475675d2005-11-17 15:11:51 +01002471 struct snd_info_buffer *buffer)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002472{
Takashi Iwai475675d2005-11-17 15:11:51 +01002473 struct snd_dbri *dbri = entry->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002474 int pipe;
2475 snd_iprintf(buffer, "debug=%d\n", dbri_debug);
2476
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002477 for (pipe = 0; pipe < 32; pipe++) {
2478 if (pipe_active(dbri, pipe)) {
2479 struct dbri_pipe *pptr = &dbri->pipes[pipe];
2480 snd_iprintf(buffer,
2481 "Pipe %d: %s SDP=0x%x desc=%d, "
Krzysztof Helt294a30d2006-08-21 19:29:59 +02002482 "len=%d next %d\n",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002483 pipe,
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002484 (pptr->sdp & D_SDP_TO_SER) ? "output" :
2485 "input",
Krzysztof Helt5fc3a2b2006-08-17 16:58:45 +02002486 pptr->sdp, pptr->desc,
Krzysztof Helt294a30d2006-08-21 19:29:59 +02002487 pptr->length, pptr->nextpipe);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002488 }
2489 }
2490}
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002491#endif
2492
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002493void __devinit snd_dbri_proc(struct snd_card *card)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002494{
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002495 struct snd_dbri *dbri = card->private_data;
Takashi Iwai475675d2005-11-17 15:11:51 +01002496 struct snd_info_entry *entry;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002497
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002498 if (!snd_card_proc_new(card, "regs", &entry))
Takashi Iwaibf850202006-04-28 15:13:41 +02002499 snd_info_set_text_ops(entry, dbri, dbri_regs_read);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002500
2501#ifdef DBRI_DEBUG
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002502 if (!snd_card_proc_new(card, "debug", &entry)) {
Takashi Iwaibf850202006-04-28 15:13:41 +02002503 snd_info_set_text_ops(entry, dbri, dbri_debug_read);
Takashi Iwai8cb7b632005-12-01 10:48:37 +01002504 entry->mode = S_IFREG | S_IRUGO; /* Readable only. */
2505 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002506#endif
2507}
2508
2509/*
2510****************************************************************************
2511**************************** Initialization ********************************
2512****************************************************************************
2513*/
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002514static void snd_dbri_free(struct snd_dbri *dbri);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002515
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002516static int __devinit snd_dbri_create(struct snd_card *card,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002517 struct sbus_dev *sdev,
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002518 int irq, int dev)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002519{
Takashi Iwai475675d2005-11-17 15:11:51 +01002520 struct snd_dbri *dbri = card->private_data;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002521 int err;
2522
2523 spin_lock_init(&dbri->lock);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002524 dbri->sdev = sdev;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002525 dbri->irq = irq;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002526
2527 dbri->dma = sbus_alloc_consistent(sdev, sizeof(struct dbri_dma),
2528 &dbri->dma_dvma);
2529 memset((void *)dbri->dma, 0, sizeof(struct dbri_dma));
2530
2531 dprintk(D_GEN, "DMA Cmd Block 0x%p (0x%08x)\n",
2532 dbri->dma, dbri->dma_dvma);
2533
2534 /* Map the registers into memory. */
2535 dbri->regs_size = sdev->reg_addrs[0].reg_size;
2536 dbri->regs = sbus_ioremap(&sdev->resource[0], 0,
2537 dbri->regs_size, "DBRI Registers");
2538 if (!dbri->regs) {
2539 printk(KERN_ERR "DBRI: could not allocate registers\n");
2540 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2541 (void *)dbri->dma, dbri->dma_dvma);
2542 return -EIO;
2543 }
2544
Thomas Gleixner65ca68b2006-07-01 19:29:46 -07002545 err = request_irq(dbri->irq, snd_dbri_interrupt, IRQF_SHARED,
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002546 "DBRI audio", dbri);
2547 if (err) {
2548 printk(KERN_ERR "DBRI: Can't get irq %d\n", dbri->irq);
2549 sbus_iounmap(dbri->regs, dbri->regs_size);
2550 sbus_free_consistent(sdev, sizeof(struct dbri_dma),
2551 (void *)dbri->dma, dbri->dma_dvma);
2552 return err;
2553 }
2554
2555 /* Do low level initialization of the DBRI and CS4215 chips */
2556 dbri_initialize(dbri);
2557 err = cs4215_init(dbri);
2558 if (err) {
2559 snd_dbri_free(dbri);
2560 return err;
2561 }
2562
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002563 return 0;
2564}
2565
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002566static void snd_dbri_free(struct snd_dbri *dbri)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002567{
2568 dprintk(D_GEN, "snd_dbri_free\n");
2569 dbri_reset(dbri);
2570
2571 if (dbri->irq)
2572 free_irq(dbri->irq, dbri);
2573
2574 if (dbri->regs)
2575 sbus_iounmap(dbri->regs, dbri->regs_size);
2576
2577 if (dbri->dma)
2578 sbus_free_consistent(dbri->sdev, sizeof(struct dbri_dma),
2579 (void *)dbri->dma, dbri->dma_dvma);
2580}
2581
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002582static int __devinit dbri_probe(struct of_device *of_dev,
2583 const struct of_device_id *match)
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002584{
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002585 struct sbus_dev *sdev = to_sbus_device(&of_dev->dev);
Takashi Iwai475675d2005-11-17 15:11:51 +01002586 struct snd_dbri *dbri;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002587 int irq;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002588 struct resource *rp;
Takashi Iwai475675d2005-11-17 15:11:51 +01002589 struct snd_card *card;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002590 static int dev = 0;
2591 int err;
2592
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002593 dprintk(D_GEN, "DBRI: Found %s in SBUS slot %d\n",
2594 sdev->prom_name, sdev->slot);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002595
2596 if (dev >= SNDRV_CARDS)
2597 return -ENODEV;
2598 if (!enable[dev]) {
2599 dev++;
2600 return -ENOENT;
2601 }
2602
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002603 irq = sdev->irqs[0];
2604 if (irq <= 0) {
2605 printk(KERN_ERR "DBRI-%d: No IRQ.\n", dev);
Martin Habets43388292005-09-10 15:39:00 +02002606 return -ENODEV;
2607 }
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002608
2609 card = snd_card_new(index[dev], id[dev], THIS_MODULE,
Takashi Iwai475675d2005-11-17 15:11:51 +01002610 sizeof(struct snd_dbri));
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002611 if (card == NULL)
2612 return -ENOMEM;
2613
2614 strcpy(card->driver, "DBRI");
2615 strcpy(card->shortname, "Sun DBRI");
2616 rp = &sdev->resource[0];
Andrew Morton5863aa62006-07-03 00:24:22 -07002617 sprintf(card->longname, "%s at 0x%02lx:0x%016Lx, irq %d",
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002618 card->shortname,
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002619 rp->flags & 0xffL, (unsigned long long)rp->start, irq);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002620
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002621 err = snd_dbri_create(card, sdev, irq, dev);
2622 if (err < 0) {
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002623 snd_card_free(card);
2624 return err;
2625 }
2626
Takashi Iwai475675d2005-11-17 15:11:51 +01002627 dbri = card->private_data;
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002628 err = snd_dbri_pcm(card);
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002629 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002630 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002631
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002632 err = snd_dbri_mixer(card);
Krzysztof Heltcf68d212007-09-04 13:09:20 +02002633 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002634 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002635
2636 /* /proc file handling */
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002637 snd_dbri_proc(card);
2638 dev_set_drvdata(&of_dev->dev, card);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002639
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002640 err = snd_card_register(card);
2641 if (err < 0)
Takashi Iwai16dab542005-09-05 17:17:58 +02002642 goto _err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002643
2644 printk(KERN_INFO "audio%d at %p (irq %d) is DBRI(%c)+CS4215(%d)\n",
2645 dev, dbri->regs,
Krzysztof Helt5fc3a2b2006-08-17 16:58:45 +02002646 dbri->irq, sdev->prom_name[9], dbri->mm.version);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002647 dev++;
2648
2649 return 0;
Takashi Iwai16dab542005-09-05 17:17:58 +02002650
Krzysztof Helt098ccbc2007-08-20 12:30:54 +02002651_err:
Takashi Iwai16dab542005-09-05 17:17:58 +02002652 snd_dbri_free(dbri);
2653 snd_card_free(card);
2654 return err;
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002655}
2656
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002657static int __devexit dbri_remove(struct of_device *dev)
2658{
2659 struct snd_card *card = dev_get_drvdata(&dev->dev);
2660
2661 snd_dbri_free(card->private_data);
2662 snd_card_free(card);
2663
2664 dev_set_drvdata(&dev->dev, NULL);
2665
2666 return 0;
2667}
2668
2669static struct of_device_id dbri_match[] = {
2670 {
2671 .name = "SUNW,DBRIe",
2672 },
2673 {
2674 .name = "SUNW,DBRIf",
2675 },
2676 {},
2677};
2678
2679MODULE_DEVICE_TABLE(of, dbri_match);
2680
2681static struct of_platform_driver dbri_sbus_driver = {
2682 .name = "dbri",
2683 .match_table = dbri_match,
2684 .probe = dbri_probe,
2685 .remove = __devexit_p(dbri_remove),
2686};
2687
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002688/* Probe for the dbri chip and then attach the driver. */
2689static int __init dbri_init(void)
2690{
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002691 return of_register_driver(&dbri_sbus_driver, &sbus_bus_type);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002692}
2693
2694static void __exit dbri_exit(void)
2695{
Krzysztof Heltafeacfd2007-09-05 15:05:08 +02002696 of_unregister_driver(&dbri_sbus_driver);
Takashi Iwai1bd9deb2005-06-30 18:26:20 +02002697}
2698
2699module_init(dbri_init);
2700module_exit(dbri_exit);