Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 1 | /* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved. |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | * |
| 12 | */ |
| 13 | #include <linux/firmware.h> |
Carter Cooper | 4a313ae | 2017-02-23 11:11:56 -0700 | [diff] [blame] | 14 | #include <soc/qcom/subsystem_restart.h> |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 15 | #include <linux/pm_opp.h> |
Tarun Karra | 1382e51 | 2017-10-30 19:41:25 -0700 | [diff] [blame] | 16 | #include <linux/jiffies.h> |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 17 | |
| 18 | #include "adreno.h" |
| 19 | #include "a6xx_reg.h" |
Shrenuj Bansal | 4166540 | 2016-12-16 15:25:54 -0800 | [diff] [blame] | 20 | #include "adreno_a6xx.h" |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 21 | #include "adreno_cp_parser.h" |
| 22 | #include "adreno_trace.h" |
| 23 | #include "adreno_pm4types.h" |
| 24 | #include "adreno_perfcounter.h" |
| 25 | #include "adreno_ringbuffer.h" |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 26 | #include "adreno_llc.h" |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 27 | #include "kgsl_sharedmem.h" |
| 28 | #include "kgsl_log.h" |
| 29 | #include "kgsl.h" |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 30 | #include "kgsl_gmu.h" |
| 31 | #include "kgsl_trace.h" |
| 32 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 33 | #define MIN_HBB 13 |
| 34 | |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 35 | #define A6XX_LLC_NUM_GPU_SCIDS 5 |
| 36 | #define A6XX_GPU_LLC_SCID_NUM_BITS 5 |
| 37 | #define A6XX_GPU_LLC_SCID_MASK \ |
| 38 | ((1 << (A6XX_LLC_NUM_GPU_SCIDS * A6XX_GPU_LLC_SCID_NUM_BITS)) - 1) |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 39 | #define A6XX_GPUHTW_LLC_SCID_SHIFT 25 |
| 40 | #define A6XX_GPUHTW_LLC_SCID_MASK \ |
| 41 | (((1 << A6XX_GPU_LLC_SCID_NUM_BITS) - 1) << A6XX_GPUHTW_LLC_SCID_SHIFT) |
| 42 | |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 43 | #define A6XX_GPU_CX_REG_BASE 0x509E000 |
| 44 | #define A6XX_GPU_CX_REG_SIZE 0x1000 |
| 45 | |
Harshdeep Dhatt | 720394d | 2017-09-13 14:25:09 -0600 | [diff] [blame] | 46 | #define GPU_LIMIT_THRESHOLD_ENABLE BIT(31) |
| 47 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 48 | static int _load_gmu_firmware(struct kgsl_device *device); |
| 49 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 50 | static const struct adreno_vbif_data a630_vbif[] = { |
| 51 | {A6XX_VBIF_GATE_OFF_WRREQ_EN, 0x00000009}, |
| 52 | {A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3}, |
| 53 | {0, 0}, |
| 54 | }; |
| 55 | |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 56 | static const struct adreno_vbif_data a615_gbif[] = { |
| 57 | {A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x3}, |
| 58 | {0, 0}, |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 59 | }; |
| 60 | |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 61 | static const struct adreno_vbif_platform a6xx_vbif_platforms[] = { |
| 62 | { adreno_is_a630, a630_vbif }, |
| 63 | { adreno_is_a615, a615_gbif }, |
Deepak Kumar | 5287eea | 2018-03-17 14:33:05 +0530 | [diff] [blame] | 64 | { adreno_is_a616, a615_gbif }, |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 65 | }; |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 66 | |
George Shen | a458dd9 | 2018-01-03 14:20:34 -0800 | [diff] [blame] | 67 | |
| 68 | static unsigned long a6xx_oob_state_bitmask; |
| 69 | |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 70 | struct kgsl_hwcg_reg { |
| 71 | unsigned int off; |
| 72 | unsigned int val; |
| 73 | }; |
| 74 | static const struct kgsl_hwcg_reg a630_hwcg_regs[] = { |
Kyle Piefer | b16c607 | 2017-10-23 16:08:45 -0700 | [diff] [blame] | 75 | {A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, |
| 76 | {A6XX_RBBM_CLOCK_CNTL_SP1, 0x02222222}, |
| 77 | {A6XX_RBBM_CLOCK_CNTL_SP2, 0x02222222}, |
| 78 | {A6XX_RBBM_CLOCK_CNTL_SP3, 0x02222222}, |
George Shen | 60d2ba5 | 2017-06-29 10:45:07 -0700 | [diff] [blame] | 79 | {A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02022220}, |
| 80 | {A6XX_RBBM_CLOCK_CNTL2_SP1, 0x02022220}, |
| 81 | {A6XX_RBBM_CLOCK_CNTL2_SP2, 0x02022220}, |
| 82 | {A6XX_RBBM_CLOCK_CNTL2_SP3, 0x02022220}, |
Kyle Piefer | cc4371f | 2017-10-12 15:43:55 -0700 | [diff] [blame] | 83 | {A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, |
| 84 | {A6XX_RBBM_CLOCK_DELAY_SP1, 0x00000080}, |
| 85 | {A6XX_RBBM_CLOCK_DELAY_SP2, 0x00000080}, |
| 86 | {A6XX_RBBM_CLOCK_DELAY_SP3, 0x00000080}, |
| 87 | {A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, |
| 88 | {A6XX_RBBM_CLOCK_HYST_SP1, 0x0000F3CF}, |
| 89 | {A6XX_RBBM_CLOCK_HYST_SP2, 0x0000F3CF}, |
| 90 | {A6XX_RBBM_CLOCK_HYST_SP3, 0x0000F3CF}, |
George Shen | c34b9e3 | 2017-06-20 11:42:19 -0700 | [diff] [blame] | 91 | {A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, |
| 92 | {A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, |
| 93 | {A6XX_RBBM_CLOCK_CNTL_TP2, 0x02222222}, |
| 94 | {A6XX_RBBM_CLOCK_CNTL_TP3, 0x02222222}, |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 95 | {A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, |
| 96 | {A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, |
| 97 | {A6XX_RBBM_CLOCK_CNTL2_TP2, 0x22222222}, |
| 98 | {A6XX_RBBM_CLOCK_CNTL2_TP3, 0x22222222}, |
| 99 | {A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, |
| 100 | {A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, |
| 101 | {A6XX_RBBM_CLOCK_CNTL3_TP2, 0x22222222}, |
| 102 | {A6XX_RBBM_CLOCK_CNTL3_TP3, 0x22222222}, |
| 103 | {A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, |
| 104 | {A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, |
| 105 | {A6XX_RBBM_CLOCK_CNTL4_TP2, 0x00022222}, |
| 106 | {A6XX_RBBM_CLOCK_CNTL4_TP3, 0x00022222}, |
| 107 | {A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, |
| 108 | {A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, |
| 109 | {A6XX_RBBM_CLOCK_HYST_TP2, 0x77777777}, |
| 110 | {A6XX_RBBM_CLOCK_HYST_TP3, 0x77777777}, |
| 111 | {A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, |
| 112 | {A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, |
| 113 | {A6XX_RBBM_CLOCK_HYST2_TP2, 0x77777777}, |
| 114 | {A6XX_RBBM_CLOCK_HYST2_TP3, 0x77777777}, |
Kyle Piefer | cc4371f | 2017-10-12 15:43:55 -0700 | [diff] [blame] | 115 | {A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, |
| 116 | {A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, |
| 117 | {A6XX_RBBM_CLOCK_HYST3_TP2, 0x77777777}, |
| 118 | {A6XX_RBBM_CLOCK_HYST3_TP3, 0x77777777}, |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 119 | {A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, |
| 120 | {A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, |
| 121 | {A6XX_RBBM_CLOCK_HYST4_TP2, 0x00077777}, |
| 122 | {A6XX_RBBM_CLOCK_HYST4_TP3, 0x00077777}, |
| 123 | {A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, |
| 124 | {A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, |
| 125 | {A6XX_RBBM_CLOCK_DELAY_TP2, 0x11111111}, |
| 126 | {A6XX_RBBM_CLOCK_DELAY_TP3, 0x11111111}, |
| 127 | {A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, |
| 128 | {A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, |
| 129 | {A6XX_RBBM_CLOCK_DELAY2_TP2, 0x11111111}, |
| 130 | {A6XX_RBBM_CLOCK_DELAY2_TP3, 0x11111111}, |
| 131 | {A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, |
| 132 | {A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, |
| 133 | {A6XX_RBBM_CLOCK_DELAY3_TP2, 0x11111111}, |
| 134 | {A6XX_RBBM_CLOCK_DELAY3_TP3, 0x11111111}, |
| 135 | {A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, |
| 136 | {A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, |
| 137 | {A6XX_RBBM_CLOCK_DELAY4_TP2, 0x00011111}, |
| 138 | {A6XX_RBBM_CLOCK_DELAY4_TP3, 0x00011111}, |
| 139 | {A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, |
| 140 | {A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, |
| 141 | {A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, |
| 142 | {A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, |
| 143 | {A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, |
| 144 | {A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, |
| 145 | {A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, |
| 146 | {A6XX_RBBM_CLOCK_CNTL_RB1, 0x22222222}, |
| 147 | {A6XX_RBBM_CLOCK_CNTL_RB2, 0x22222222}, |
| 148 | {A6XX_RBBM_CLOCK_CNTL_RB3, 0x22222222}, |
| 149 | {A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, |
| 150 | {A6XX_RBBM_CLOCK_CNTL2_RB1, 0x00002222}, |
| 151 | {A6XX_RBBM_CLOCK_CNTL2_RB2, 0x00002222}, |
| 152 | {A6XX_RBBM_CLOCK_CNTL2_RB3, 0x00002222}, |
Kyle Piefer | 0c3e752 | 2017-10-23 15:49:49 -0700 | [diff] [blame] | 153 | {A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, |
| 154 | {A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, |
| 155 | {A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, |
| 156 | {A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 157 | {A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, |
| 158 | {A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00}, |
| 159 | {A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00}, |
| 160 | {A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00}, |
Kyle Piefer | 0c3e752 | 2017-10-23 15:49:49 -0700 | [diff] [blame] | 161 | {A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, |
| 162 | {A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, |
Kyle Piefer | cc4371f | 2017-10-12 15:43:55 -0700 | [diff] [blame] | 163 | {A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 164 | {A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, |
Kyle Piefer | 0c3e752 | 2017-10-23 15:49:49 -0700 | [diff] [blame] | 165 | {A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, |
Kyle Piefer | 42d20bf | 2017-10-19 15:35:41 -0700 | [diff] [blame] | 166 | {A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 167 | {A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, |
| 168 | {A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, |
| 169 | {A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, |
| 170 | {A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, |
| 171 | {A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, |
| 172 | {A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, |
| 173 | {A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, |
| 174 | {A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, |
| 175 | {A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, |
| 176 | {A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, |
| 177 | {A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, |
| 178 | {A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, |
| 179 | {A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555} |
| 180 | }; |
| 181 | |
Rajesh Kemisetti | 0420208 | 2017-10-17 14:14:27 +0530 | [diff] [blame] | 182 | static const struct kgsl_hwcg_reg a615_hwcg_regs[] = { |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 183 | {A6XX_RBBM_CLOCK_CNTL_SP0, 0x02222222}, |
Rajesh Kemisetti | 0420208 | 2017-10-17 14:14:27 +0530 | [diff] [blame] | 184 | {A6XX_RBBM_CLOCK_CNTL2_SP0, 0x02222220}, |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 185 | {A6XX_RBBM_CLOCK_DELAY_SP0, 0x00000080}, |
Rajesh Kemisetti | 0420208 | 2017-10-17 14:14:27 +0530 | [diff] [blame] | 186 | {A6XX_RBBM_CLOCK_HYST_SP0, 0x0000F3CF}, |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 187 | {A6XX_RBBM_CLOCK_CNTL_TP0, 0x02222222}, |
| 188 | {A6XX_RBBM_CLOCK_CNTL_TP1, 0x02222222}, |
Rajesh Kemisetti | 0420208 | 2017-10-17 14:14:27 +0530 | [diff] [blame] | 189 | {A6XX_RBBM_CLOCK_CNTL2_TP0, 0x22222222}, |
| 190 | {A6XX_RBBM_CLOCK_CNTL2_TP1, 0x22222222}, |
| 191 | {A6XX_RBBM_CLOCK_CNTL3_TP0, 0x22222222}, |
| 192 | {A6XX_RBBM_CLOCK_CNTL3_TP1, 0x22222222}, |
| 193 | {A6XX_RBBM_CLOCK_CNTL4_TP0, 0x00022222}, |
| 194 | {A6XX_RBBM_CLOCK_CNTL4_TP1, 0x00022222}, |
| 195 | {A6XX_RBBM_CLOCK_HYST_TP0, 0x77777777}, |
| 196 | {A6XX_RBBM_CLOCK_HYST_TP1, 0x77777777}, |
| 197 | {A6XX_RBBM_CLOCK_HYST2_TP0, 0x77777777}, |
| 198 | {A6XX_RBBM_CLOCK_HYST2_TP1, 0x77777777}, |
| 199 | {A6XX_RBBM_CLOCK_HYST3_TP0, 0x77777777}, |
| 200 | {A6XX_RBBM_CLOCK_HYST3_TP1, 0x77777777}, |
| 201 | {A6XX_RBBM_CLOCK_HYST4_TP0, 0x00077777}, |
| 202 | {A6XX_RBBM_CLOCK_HYST4_TP1, 0x00077777}, |
| 203 | {A6XX_RBBM_CLOCK_DELAY_TP0, 0x11111111}, |
| 204 | {A6XX_RBBM_CLOCK_DELAY_TP1, 0x11111111}, |
| 205 | {A6XX_RBBM_CLOCK_DELAY2_TP0, 0x11111111}, |
| 206 | {A6XX_RBBM_CLOCK_DELAY2_TP1, 0x11111111}, |
| 207 | {A6XX_RBBM_CLOCK_DELAY3_TP0, 0x11111111}, |
| 208 | {A6XX_RBBM_CLOCK_DELAY3_TP1, 0x11111111}, |
| 209 | {A6XX_RBBM_CLOCK_DELAY4_TP0, 0x00011111}, |
| 210 | {A6XX_RBBM_CLOCK_DELAY4_TP1, 0x00011111}, |
| 211 | {A6XX_RBBM_CLOCK_CNTL_UCHE, 0x22222222}, |
| 212 | {A6XX_RBBM_CLOCK_CNTL2_UCHE, 0x22222222}, |
| 213 | {A6XX_RBBM_CLOCK_CNTL3_UCHE, 0x22222222}, |
| 214 | {A6XX_RBBM_CLOCK_CNTL4_UCHE, 0x00222222}, |
| 215 | {A6XX_RBBM_CLOCK_HYST_UCHE, 0x00000004}, |
| 216 | {A6XX_RBBM_CLOCK_DELAY_UCHE, 0x00000002}, |
| 217 | {A6XX_RBBM_CLOCK_CNTL_RB0, 0x22222222}, |
| 218 | {A6XX_RBBM_CLOCK_CNTL2_RB0, 0x00002222}, |
| 219 | {A6XX_RBBM_CLOCK_CNTL_CCU0, 0x00002220}, |
| 220 | {A6XX_RBBM_CLOCK_CNTL_CCU1, 0x00002220}, |
| 221 | {A6XX_RBBM_CLOCK_CNTL_CCU2, 0x00002220}, |
| 222 | {A6XX_RBBM_CLOCK_CNTL_CCU3, 0x00002220}, |
| 223 | {A6XX_RBBM_CLOCK_HYST_RB_CCU0, 0x00040F00}, |
| 224 | {A6XX_RBBM_CLOCK_HYST_RB_CCU1, 0x00040F00}, |
| 225 | {A6XX_RBBM_CLOCK_HYST_RB_CCU2, 0x00040F00}, |
| 226 | {A6XX_RBBM_CLOCK_HYST_RB_CCU3, 0x00040F00}, |
| 227 | {A6XX_RBBM_CLOCK_CNTL_RAC, 0x05022022}, |
| 228 | {A6XX_RBBM_CLOCK_CNTL2_RAC, 0x00005555}, |
| 229 | {A6XX_RBBM_CLOCK_DELAY_RAC, 0x00000011}, |
| 230 | {A6XX_RBBM_CLOCK_HYST_RAC, 0x00445044}, |
| 231 | {A6XX_RBBM_CLOCK_CNTL_TSE_RAS_RBBM, 0x04222222}, |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 232 | {A6XX_RBBM_CLOCK_MODE_GPC, 0x00222222}, |
Rajesh Kemisetti | 0420208 | 2017-10-17 14:14:27 +0530 | [diff] [blame] | 233 | {A6XX_RBBM_CLOCK_MODE_VFD, 0x00002222}, |
| 234 | {A6XX_RBBM_CLOCK_HYST_TSE_RAS_RBBM, 0x00000000}, |
| 235 | {A6XX_RBBM_CLOCK_HYST_GPC, 0x04104004}, |
| 236 | {A6XX_RBBM_CLOCK_HYST_VFD, 0x00000000}, |
| 237 | {A6XX_RBBM_CLOCK_DELAY_HLSQ, 0x00000000}, |
| 238 | {A6XX_RBBM_CLOCK_DELAY_TSE_RAS_RBBM, 0x00004000}, |
| 239 | {A6XX_RBBM_CLOCK_DELAY_GPC, 0x00000200}, |
| 240 | {A6XX_RBBM_CLOCK_DELAY_VFD, 0x00002222}, |
| 241 | {A6XX_RBBM_CLOCK_DELAY_HLSQ_2, 0x00000002}, |
| 242 | {A6XX_RBBM_CLOCK_MODE_HLSQ, 0x00002222}, |
| 243 | {A6XX_RBBM_CLOCK_CNTL_GMU_GX, 0x00000222}, |
| 244 | {A6XX_RBBM_CLOCK_DELAY_GMU_GX, 0x00000111}, |
| 245 | {A6XX_RBBM_CLOCK_HYST_GMU_GX, 0x00000555} |
| 246 | }; |
| 247 | |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 248 | static const struct { |
| 249 | int (*devfunc)(struct adreno_device *adreno_dev); |
| 250 | const struct kgsl_hwcg_reg *regs; |
| 251 | unsigned int count; |
| 252 | } a6xx_hwcg_registers[] = { |
Rajesh Kemisetti | 8d5cc6e | 2017-06-06 16:44:17 +0530 | [diff] [blame] | 253 | {adreno_is_a630, a630_hwcg_regs, ARRAY_SIZE(a630_hwcg_regs)}, |
Rajesh Kemisetti | 0420208 | 2017-10-17 14:14:27 +0530 | [diff] [blame] | 254 | {adreno_is_a615, a615_hwcg_regs, ARRAY_SIZE(a615_hwcg_regs)}, |
Deepak Kumar | 5287eea | 2018-03-17 14:33:05 +0530 | [diff] [blame] | 255 | {adreno_is_a616, a615_hwcg_regs, ARRAY_SIZE(a615_hwcg_regs)}, |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 256 | }; |
| 257 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 258 | static struct a6xx_protected_regs { |
| 259 | unsigned int base; |
| 260 | unsigned int count; |
| 261 | int read_protect; |
| 262 | } a6xx_protected_regs_group[] = { |
| 263 | { 0x600, 0x51, 0 }, |
| 264 | { 0xAE50, 0x2, 1 }, |
| 265 | { 0x9624, 0x13, 1 }, |
| 266 | { 0x8630, 0x8, 1 }, |
| 267 | { 0x9E70, 0x1, 1 }, |
| 268 | { 0x9E78, 0x187, 1 }, |
| 269 | { 0xF000, 0x810, 1 }, |
| 270 | { 0xFC00, 0x3, 0 }, |
| 271 | { 0x50E, 0x0, 1 }, |
| 272 | { 0x50F, 0x0, 0 }, |
| 273 | { 0x510, 0x0, 1 }, |
| 274 | { 0x0, 0x4F9, 0 }, |
| 275 | { 0x501, 0xA, 0 }, |
| 276 | { 0x511, 0x44, 0 }, |
Shrenuj Bansal | 932c8ef | 2017-08-07 15:16:15 -0700 | [diff] [blame] | 277 | { 0xE00, 0x1, 1 }, |
| 278 | { 0xE03, 0xB, 1 }, |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 279 | { 0x8E00, 0x0, 1 }, |
| 280 | { 0x8E50, 0xF, 1 }, |
| 281 | { 0xBE02, 0x0, 1 }, |
| 282 | { 0xBE20, 0x11F3, 1 }, |
| 283 | { 0x800, 0x82, 1 }, |
| 284 | { 0x8A0, 0x8, 1 }, |
| 285 | { 0x8AB, 0x19, 1 }, |
| 286 | { 0x900, 0x4D, 1 }, |
| 287 | { 0x98D, 0x76, 1 }, |
| 288 | { 0x8D0, 0x23, 0 }, |
| 289 | { 0x980, 0x4, 0 }, |
| 290 | { 0xA630, 0x0, 1 }, |
| 291 | }; |
| 292 | |
Tarun Karra | 4ea6812 | 2017-11-02 18:10:31 -0700 | [diff] [blame] | 293 | /* IFPC & Preemption static powerup restore list */ |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 294 | static struct reg_list_pair { |
| 295 | uint32_t offset; |
| 296 | uint32_t val; |
| 297 | } a6xx_pwrup_reglist[] = { |
| 298 | { A6XX_VSC_ADDR_MODE_CNTL, 0x0 }, |
| 299 | { A6XX_GRAS_ADDR_MODE_CNTL, 0x0 }, |
| 300 | { A6XX_RB_ADDR_MODE_CNTL, 0x0 }, |
| 301 | { A6XX_PC_ADDR_MODE_CNTL, 0x0 }, |
| 302 | { A6XX_HLSQ_ADDR_MODE_CNTL, 0x0 }, |
| 303 | { A6XX_VFD_ADDR_MODE_CNTL, 0x0 }, |
| 304 | { A6XX_VPC_ADDR_MODE_CNTL, 0x0 }, |
| 305 | { A6XX_UCHE_ADDR_MODE_CNTL, 0x0 }, |
| 306 | { A6XX_SP_ADDR_MODE_CNTL, 0x0 }, |
| 307 | { A6XX_TPL1_ADDR_MODE_CNTL, 0x0 }, |
| 308 | { A6XX_UCHE_WRITE_RANGE_MAX_LO, 0x0 }, |
| 309 | { A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0 }, |
| 310 | { A6XX_UCHE_TRAP_BASE_LO, 0x0 }, |
| 311 | { A6XX_UCHE_TRAP_BASE_HI, 0x0 }, |
| 312 | { A6XX_UCHE_WRITE_THRU_BASE_LO, 0x0 }, |
| 313 | { A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0 }, |
| 314 | { A6XX_UCHE_GMEM_RANGE_MIN_LO, 0x0 }, |
| 315 | { A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x0 }, |
| 316 | { A6XX_UCHE_GMEM_RANGE_MAX_LO, 0x0 }, |
| 317 | { A6XX_UCHE_GMEM_RANGE_MAX_HI, 0x0 }, |
| 318 | { A6XX_UCHE_FILTER_CNTL, 0x0 }, |
| 319 | { A6XX_UCHE_CACHE_WAYS, 0x0 }, |
| 320 | { A6XX_UCHE_MODE_CNTL, 0x0 }, |
| 321 | { A6XX_RB_NC_MODE_CNTL, 0x0 }, |
| 322 | { A6XX_TPL1_NC_MODE_CNTL, 0x0 }, |
| 323 | { A6XX_SP_NC_MODE_CNTL, 0x0 }, |
| 324 | { A6XX_PC_DBG_ECO_CNTL, 0x0 }, |
| 325 | { A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, 0x0 }, |
| 326 | }; |
| 327 | |
Tarun Karra | 4ea6812 | 2017-11-02 18:10:31 -0700 | [diff] [blame] | 328 | /* IFPC only static powerup restore list */ |
| 329 | static struct reg_list_pair a6xx_ifpc_pwrup_reglist[] = { |
| 330 | { A6XX_RBBM_VBIF_CLIENT_QOS_CNTL, 0x0 }, |
| 331 | { A6XX_CP_CHICKEN_DBG, 0x0 }, |
Tarun Karra | 4ea6812 | 2017-11-02 18:10:31 -0700 | [diff] [blame] | 332 | { A6XX_CP_DBG_ECO_CNTL, 0x0 }, |
| 333 | { A6XX_CP_PROTECT_CNTL, 0x0 }, |
| 334 | { A6XX_CP_PROTECT_REG, 0x0 }, |
| 335 | { A6XX_CP_PROTECT_REG+1, 0x0 }, |
| 336 | { A6XX_CP_PROTECT_REG+2, 0x0 }, |
| 337 | { A6XX_CP_PROTECT_REG+3, 0x0 }, |
| 338 | { A6XX_CP_PROTECT_REG+4, 0x0 }, |
| 339 | { A6XX_CP_PROTECT_REG+5, 0x0 }, |
| 340 | { A6XX_CP_PROTECT_REG+6, 0x0 }, |
| 341 | { A6XX_CP_PROTECT_REG+7, 0x0 }, |
| 342 | { A6XX_CP_PROTECT_REG+8, 0x0 }, |
| 343 | { A6XX_CP_PROTECT_REG+9, 0x0 }, |
| 344 | { A6XX_CP_PROTECT_REG+10, 0x0 }, |
| 345 | { A6XX_CP_PROTECT_REG+11, 0x0 }, |
| 346 | { A6XX_CP_PROTECT_REG+12, 0x0 }, |
| 347 | { A6XX_CP_PROTECT_REG+13, 0x0 }, |
| 348 | { A6XX_CP_PROTECT_REG+14, 0x0 }, |
| 349 | { A6XX_CP_PROTECT_REG+15, 0x0 }, |
| 350 | { A6XX_CP_PROTECT_REG+16, 0x0 }, |
| 351 | { A6XX_CP_PROTECT_REG+17, 0x0 }, |
| 352 | { A6XX_CP_PROTECT_REG+18, 0x0 }, |
| 353 | { A6XX_CP_PROTECT_REG+19, 0x0 }, |
| 354 | { A6XX_CP_PROTECT_REG+20, 0x0 }, |
| 355 | { A6XX_CP_PROTECT_REG+21, 0x0 }, |
| 356 | { A6XX_CP_PROTECT_REG+22, 0x0 }, |
| 357 | { A6XX_CP_PROTECT_REG+23, 0x0 }, |
| 358 | { A6XX_CP_PROTECT_REG+24, 0x0 }, |
| 359 | { A6XX_CP_PROTECT_REG+25, 0x0 }, |
| 360 | { A6XX_CP_PROTECT_REG+26, 0x0 }, |
| 361 | { A6XX_CP_PROTECT_REG+27, 0x0 }, |
| 362 | { A6XX_CP_PROTECT_REG+28, 0x0 }, |
| 363 | { A6XX_CP_PROTECT_REG+29, 0x0 }, |
| 364 | { A6XX_CP_PROTECT_REG+30, 0x0 }, |
| 365 | { A6XX_CP_PROTECT_REG+31, 0x0 }, |
| 366 | { A6XX_CP_AHB_CNTL, 0x0 }, |
| 367 | }; |
| 368 | |
Akhil P Oommen | 35dde69 | 2018-01-16 18:01:09 +0530 | [diff] [blame] | 369 | static struct reg_list_pair a615_pwrup_reglist[] = { |
Deepak Kumar | ab6b895 | 2017-12-18 11:18:37 +0530 | [diff] [blame] | 370 | { A6XX_UCHE_GBIF_GX_CONFIG, 0x0 }, |
| 371 | }; |
| 372 | |
Carter Cooper | 6ce0042 | 2017-03-20 11:25:09 -0600 | [diff] [blame] | 373 | static void _update_always_on_regs(struct adreno_device *adreno_dev) |
| 374 | { |
| 375 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 376 | unsigned int *const regs = gpudev->reg_offsets->offsets; |
| 377 | |
| 378 | regs[ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO] = |
| 379 | A6XX_CP_ALWAYS_ON_COUNTER_LO; |
| 380 | regs[ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI] = |
| 381 | A6XX_CP_ALWAYS_ON_COUNTER_HI; |
| 382 | } |
| 383 | |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 384 | static uint64_t read_AO_counter(struct kgsl_device *device) |
| 385 | { |
| 386 | unsigned int l, h, h1; |
| 387 | |
| 388 | kgsl_gmu_regread(device, A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_H, &h); |
| 389 | kgsl_gmu_regread(device, A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_L, &l); |
| 390 | kgsl_gmu_regread(device, A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_H, &h1); |
| 391 | |
| 392 | if (h == h1) |
| 393 | return (uint64_t) l | ((uint64_t) h << 32); |
| 394 | |
| 395 | kgsl_gmu_regread(device, A6XX_GMU_CX_GMU_ALWAYS_ON_COUNTER_L, &l); |
| 396 | return (uint64_t) l | ((uint64_t) h1 << 32); |
| 397 | } |
| 398 | |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 399 | static void a6xx_pwrup_reglist_init(struct adreno_device *adreno_dev) |
| 400 | { |
| 401 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 402 | |
| 403 | if (kgsl_allocate_global(device, &adreno_dev->pwrup_reglist, |
Tarun Karra | a667436 | 2017-10-23 12:57:48 -0700 | [diff] [blame] | 404 | PAGE_SIZE, 0, KGSL_MEMDESC_CONTIG | KGSL_MEMDESC_PRIVILEGED, |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 405 | "powerup_register_list")) { |
| 406 | adreno_dev->pwrup_reglist.gpuaddr = 0; |
| 407 | return; |
| 408 | } |
| 409 | |
| 410 | kgsl_sharedmem_set(device, &adreno_dev->pwrup_reglist, 0, 0, |
| 411 | PAGE_SIZE); |
| 412 | } |
| 413 | |
Shrenuj Bansal | 4166540 | 2016-12-16 15:25:54 -0800 | [diff] [blame] | 414 | static void a6xx_init(struct adreno_device *adreno_dev) |
| 415 | { |
| 416 | a6xx_crashdump_init(adreno_dev); |
Carter Cooper | 6ce0042 | 2017-03-20 11:25:09 -0600 | [diff] [blame] | 417 | |
| 418 | /* |
| 419 | * If the GMU is not enabled, rewrite the offset for the always on |
| 420 | * counters to point to the CP always on instead of GMU always on |
| 421 | */ |
| 422 | if (!kgsl_gmu_isenabled(KGSL_DEVICE(adreno_dev))) |
| 423 | _update_always_on_regs(adreno_dev); |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 424 | |
| 425 | a6xx_pwrup_reglist_init(adreno_dev); |
Shrenuj Bansal | 4166540 | 2016-12-16 15:25:54 -0800 | [diff] [blame] | 426 | } |
| 427 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 428 | /** |
| 429 | * a6xx_protect_init() - Initializes register protection on a6xx |
| 430 | * @device: Pointer to the device structure |
| 431 | * Performs register writes to enable protected access to sensitive |
| 432 | * registers |
| 433 | */ |
| 434 | static void a6xx_protect_init(struct adreno_device *adreno_dev) |
| 435 | { |
| 436 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
Tarun Karra | 9f94550 | 2017-03-23 12:28:03 -0700 | [diff] [blame] | 437 | struct kgsl_protected_registers *mmu_prot = |
| 438 | kgsl_mmu_get_prot_regs(&device->mmu); |
| 439 | int i, num_sets; |
| 440 | int req_sets = ARRAY_SIZE(a6xx_protected_regs_group); |
| 441 | int max_sets = adreno_dev->gpucore->num_protected_regs; |
| 442 | unsigned int mmu_base = 0, mmu_range = 0, cur_range; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 443 | |
| 444 | /* enable access protection to privileged registers */ |
Harshdeep Dhatt | 9fc043e | 2017-04-21 12:06:22 -0600 | [diff] [blame] | 445 | kgsl_regwrite(device, A6XX_CP_PROTECT_CNTL, 0x00000003); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 446 | |
Lynus Vaz | 0955c6c | 2017-02-20 18:59:44 +0530 | [diff] [blame] | 447 | if (mmu_prot) { |
| 448 | mmu_base = mmu_prot->base; |
| 449 | mmu_range = 1 << mmu_prot->range; |
Tarun Karra | 9f94550 | 2017-03-23 12:28:03 -0700 | [diff] [blame] | 450 | req_sets += DIV_ROUND_UP(mmu_range, 0x2000); |
Lynus Vaz | 0955c6c | 2017-02-20 18:59:44 +0530 | [diff] [blame] | 451 | } |
| 452 | |
Tarun Karra | 9f94550 | 2017-03-23 12:28:03 -0700 | [diff] [blame] | 453 | if (req_sets > max_sets) |
Lynus Vaz | 0955c6c | 2017-02-20 18:59:44 +0530 | [diff] [blame] | 454 | WARN(1, "Size exceeds the num of protection regs available\n"); |
Lynus Vaz | 0955c6c | 2017-02-20 18:59:44 +0530 | [diff] [blame] | 455 | |
Tarun Karra | 9f94550 | 2017-03-23 12:28:03 -0700 | [diff] [blame] | 456 | /* Protect GPU registers */ |
| 457 | num_sets = min_t(unsigned int, |
| 458 | ARRAY_SIZE(a6xx_protected_regs_group), max_sets); |
| 459 | for (i = 0; i < num_sets; i++) { |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 460 | struct a6xx_protected_regs *regs = |
| 461 | &a6xx_protected_regs_group[i]; |
| 462 | |
| 463 | kgsl_regwrite(device, A6XX_CP_PROTECT_REG + i, |
| 464 | regs->base | (regs->count << 18) | |
| 465 | (regs->read_protect << 31)); |
| 466 | } |
| 467 | |
Tarun Karra | 9f94550 | 2017-03-23 12:28:03 -0700 | [diff] [blame] | 468 | /* Protect MMU registers */ |
| 469 | if (mmu_prot) { |
| 470 | while ((i < max_sets) && (mmu_range > 0)) { |
| 471 | cur_range = min_t(unsigned int, mmu_range, |
Lynus Vaz | 0955c6c | 2017-02-20 18:59:44 +0530 | [diff] [blame] | 472 | 0x2000); |
Tarun Karra | 9f94550 | 2017-03-23 12:28:03 -0700 | [diff] [blame] | 473 | kgsl_regwrite(device, A6XX_CP_PROTECT_REG + i, |
| 474 | mmu_base | ((cur_range - 1) << 18) | (1 << 31)); |
Lynus Vaz | 0955c6c | 2017-02-20 18:59:44 +0530 | [diff] [blame] | 475 | |
Tarun Karra | 9f94550 | 2017-03-23 12:28:03 -0700 | [diff] [blame] | 476 | mmu_base += cur_range; |
| 477 | mmu_range -= cur_range; |
| 478 | i++; |
| 479 | } |
Lynus Vaz | 0955c6c | 2017-02-20 18:59:44 +0530 | [diff] [blame] | 480 | } |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 481 | } |
| 482 | |
| 483 | static void a6xx_enable_64bit(struct adreno_device *adreno_dev) |
| 484 | { |
| 485 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 486 | |
| 487 | kgsl_regwrite(device, A6XX_CP_ADDR_MODE_CNTL, 0x1); |
| 488 | kgsl_regwrite(device, A6XX_VSC_ADDR_MODE_CNTL, 0x1); |
| 489 | kgsl_regwrite(device, A6XX_GRAS_ADDR_MODE_CNTL, 0x1); |
| 490 | kgsl_regwrite(device, A6XX_RB_ADDR_MODE_CNTL, 0x1); |
| 491 | kgsl_regwrite(device, A6XX_PC_ADDR_MODE_CNTL, 0x1); |
| 492 | kgsl_regwrite(device, A6XX_HLSQ_ADDR_MODE_CNTL, 0x1); |
| 493 | kgsl_regwrite(device, A6XX_VFD_ADDR_MODE_CNTL, 0x1); |
| 494 | kgsl_regwrite(device, A6XX_VPC_ADDR_MODE_CNTL, 0x1); |
| 495 | kgsl_regwrite(device, A6XX_UCHE_ADDR_MODE_CNTL, 0x1); |
| 496 | kgsl_regwrite(device, A6XX_SP_ADDR_MODE_CNTL, 0x1); |
| 497 | kgsl_regwrite(device, A6XX_TPL1_ADDR_MODE_CNTL, 0x1); |
| 498 | kgsl_regwrite(device, A6XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); |
| 499 | } |
| 500 | |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 501 | static inline unsigned int |
| 502 | __get_rbbm_clock_cntl_on(struct adreno_device *adreno_dev) |
| 503 | { |
Deepak Kumar | 5287eea | 2018-03-17 14:33:05 +0530 | [diff] [blame] | 504 | if (adreno_is_a615(adreno_dev) || adreno_is_a616(adreno_dev)) |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 505 | return 0x8AA8AA82; |
| 506 | else |
| 507 | return 0x8AA8AA02; |
| 508 | } |
| 509 | |
| 510 | static inline unsigned int |
| 511 | __get_gmu_ao_cgc_mode_cntl(struct adreno_device *adreno_dev) |
| 512 | { |
Deepak Kumar | 5287eea | 2018-03-17 14:33:05 +0530 | [diff] [blame] | 513 | if (adreno_is_a615(adreno_dev) || adreno_is_a616(adreno_dev)) |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 514 | return 0x00000222; |
| 515 | else |
Oleg Perelet | 5d2d28f | 2018-03-06 17:03:20 -0800 | [diff] [blame] | 516 | return 0x00020202; |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 517 | } |
| 518 | |
| 519 | static inline unsigned int |
| 520 | __get_gmu_ao_cgc_delay_cntl(struct adreno_device *adreno_dev) |
| 521 | { |
Deepak Kumar | 5287eea | 2018-03-17 14:33:05 +0530 | [diff] [blame] | 522 | if (adreno_is_a615(adreno_dev) || adreno_is_a616(adreno_dev)) |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 523 | return 0x00000111; |
| 524 | else |
| 525 | return 0x00010111; |
| 526 | } |
| 527 | |
| 528 | static inline unsigned int |
| 529 | __get_gmu_ao_cgc_hyst_cntl(struct adreno_device *adreno_dev) |
| 530 | { |
Deepak Kumar | 5287eea | 2018-03-17 14:33:05 +0530 | [diff] [blame] | 531 | if (adreno_is_a615(adreno_dev) || adreno_is_a616(adreno_dev)) |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 532 | return 0x00000555; |
| 533 | else |
| 534 | return 0x00005555; |
| 535 | } |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 536 | |
| 537 | static void a6xx_hwcg_set(struct adreno_device *adreno_dev, bool on) |
| 538 | { |
| 539 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 540 | const struct kgsl_hwcg_reg *regs; |
Oleg Perelet | 88e5449 | 2017-09-22 11:10:31 -0700 | [diff] [blame] | 541 | unsigned int value; |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 542 | int i, j; |
| 543 | |
| 544 | if (!test_bit(ADRENO_HWCG_CTRL, &adreno_dev->pwrctrl_flag)) |
Oleg Perelet | 88e5449 | 2017-09-22 11:10:31 -0700 | [diff] [blame] | 545 | on = false; |
| 546 | |
| 547 | if (kgsl_gmu_isenabled(device)) { |
| 548 | kgsl_gmu_regwrite(device, A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL, |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 549 | on ? __get_gmu_ao_cgc_mode_cntl(adreno_dev) : 0); |
Oleg Perelet | 88e5449 | 2017-09-22 11:10:31 -0700 | [diff] [blame] | 550 | kgsl_gmu_regwrite(device, A6XX_GPU_GMU_AO_GMU_CGC_DELAY_CNTL, |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 551 | on ? __get_gmu_ao_cgc_delay_cntl(adreno_dev) : 0); |
Oleg Perelet | 88e5449 | 2017-09-22 11:10:31 -0700 | [diff] [blame] | 552 | kgsl_gmu_regwrite(device, A6XX_GPU_GMU_AO_GMU_CGC_HYST_CNTL, |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 553 | on ? __get_gmu_ao_cgc_hyst_cntl(adreno_dev) : 0); |
Oleg Perelet | 88e5449 | 2017-09-22 11:10:31 -0700 | [diff] [blame] | 554 | } |
| 555 | |
| 556 | kgsl_regread(device, A6XX_RBBM_CLOCK_CNTL, &value); |
| 557 | |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 558 | if (value == __get_rbbm_clock_cntl_on(adreno_dev) && on) |
Oleg Perelet | 88e5449 | 2017-09-22 11:10:31 -0700 | [diff] [blame] | 559 | return; |
| 560 | |
| 561 | if (value == 0 && !on) |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 562 | return; |
| 563 | |
| 564 | for (i = 0; i < ARRAY_SIZE(a6xx_hwcg_registers); i++) { |
| 565 | if (a6xx_hwcg_registers[i].devfunc(adreno_dev)) |
| 566 | break; |
| 567 | } |
| 568 | |
| 569 | if (i == ARRAY_SIZE(a6xx_hwcg_registers)) |
| 570 | return; |
| 571 | |
| 572 | regs = a6xx_hwcg_registers[i].regs; |
| 573 | |
| 574 | /* Disable SP clock before programming HWCG registers */ |
Deepak Kumar | 9892ba1 | 2017-07-07 14:51:11 +0530 | [diff] [blame] | 575 | kgsl_gmu_regrmw(device, A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 1, 0); |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 576 | |
| 577 | for (j = 0; j < a6xx_hwcg_registers[i].count; j++) |
| 578 | kgsl_regwrite(device, regs[j].off, on ? regs[j].val : 0); |
| 579 | |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 580 | /* Enable SP clock */ |
| 581 | kgsl_gmu_regrmw(device, A6XX_GPU_GMU_GX_SPTPRAC_CLOCK_CONTROL, 0, 1); |
| 582 | |
| 583 | /* enable top level HWCG */ |
Oleg Perelet | 88e5449 | 2017-09-22 11:10:31 -0700 | [diff] [blame] | 584 | kgsl_regwrite(device, A6XX_RBBM_CLOCK_CNTL, |
Deepak Kumar | 4a393ff | 2017-11-16 13:35:40 +0530 | [diff] [blame] | 585 | on ? __get_rbbm_clock_cntl_on(adreno_dev) : 0); |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 586 | } |
| 587 | |
Oleg Perelet | c2ab7f7 | 2017-06-22 16:45:57 -0700 | [diff] [blame] | 588 | #define LM_DEFAULT_LIMIT 6000 |
| 589 | |
| 590 | static uint32_t lm_limit(struct adreno_device *adreno_dev) |
| 591 | { |
| 592 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 593 | |
| 594 | if (adreno_dev->lm_limit) |
| 595 | return adreno_dev->lm_limit; |
| 596 | |
| 597 | if (of_property_read_u32(device->pdev->dev.of_node, "qcom,lm-limit", |
| 598 | &adreno_dev->lm_limit)) |
| 599 | adreno_dev->lm_limit = LM_DEFAULT_LIMIT; |
| 600 | |
| 601 | return adreno_dev->lm_limit; |
| 602 | } |
| 603 | |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 604 | static void a6xx_patch_pwrup_reglist(struct adreno_device *adreno_dev) |
| 605 | { |
| 606 | uint32_t i; |
Harshdeep Dhatt | d373aa5 | 2017-08-09 14:13:41 -0600 | [diff] [blame] | 607 | struct cpu_gpu_lock *lock; |
Tarun Karra | 4ea6812 | 2017-11-02 18:10:31 -0700 | [diff] [blame] | 608 | struct reg_list_pair *r; |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 609 | |
| 610 | /* Set up the register values */ |
Tarun Karra | 4ea6812 | 2017-11-02 18:10:31 -0700 | [diff] [blame] | 611 | for (i = 0; i < ARRAY_SIZE(a6xx_ifpc_pwrup_reglist); i++) { |
| 612 | r = &a6xx_ifpc_pwrup_reglist[i]; |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 613 | kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val); |
| 614 | } |
| 615 | |
Tarun Karra | 4ea6812 | 2017-11-02 18:10:31 -0700 | [diff] [blame] | 616 | for (i = 0; i < ARRAY_SIZE(a6xx_pwrup_reglist); i++) { |
| 617 | r = &a6xx_pwrup_reglist[i]; |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 618 | kgsl_regread(KGSL_DEVICE(adreno_dev), r->offset, &r->val); |
| 619 | } |
| 620 | |
Harshdeep Dhatt | d373aa5 | 2017-08-09 14:13:41 -0600 | [diff] [blame] | 621 | lock = (struct cpu_gpu_lock *) adreno_dev->pwrup_reglist.hostptr; |
| 622 | lock->flag_ucode = 0; |
| 623 | lock->flag_kmd = 0; |
| 624 | lock->turn = 0; |
| 625 | |
| 626 | /* |
| 627 | * The overall register list is composed of |
| 628 | * 1. Static IFPC-only registers |
| 629 | * 2. Static IFPC + preemption registers |
| 630 | * 2. Dynamic IFPC + preemption registers (ex: perfcounter selects) |
| 631 | * |
| 632 | * The CP views the second and third entries as one dynamic list |
| 633 | * starting from list_offset. Thus, list_length should be the sum |
| 634 | * of all three lists above (of which the third list will start off |
| 635 | * empty). And list_offset should be specified as the size in dwords |
| 636 | * of the static IFPC-only register list. |
| 637 | */ |
Tarun Karra | 4ea6812 | 2017-11-02 18:10:31 -0700 | [diff] [blame] | 638 | lock->list_length = (sizeof(a6xx_ifpc_pwrup_reglist) + |
Akhil P Oommen | 35dde69 | 2018-01-16 18:01:09 +0530 | [diff] [blame] | 639 | sizeof(a6xx_pwrup_reglist)) >> 2; |
| 640 | lock->list_offset = sizeof(a6xx_ifpc_pwrup_reglist) >> 2; |
Harshdeep Dhatt | d373aa5 | 2017-08-09 14:13:41 -0600 | [diff] [blame] | 641 | |
Akhil P Oommen | 35dde69 | 2018-01-16 18:01:09 +0530 | [diff] [blame] | 642 | memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock), |
Tarun Karra | 4ea6812 | 2017-11-02 18:10:31 -0700 | [diff] [blame] | 643 | a6xx_ifpc_pwrup_reglist, sizeof(a6xx_ifpc_pwrup_reglist)); |
| 644 | memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock) |
Akhil P Oommen | 35dde69 | 2018-01-16 18:01:09 +0530 | [diff] [blame] | 645 | + sizeof(a6xx_ifpc_pwrup_reglist), a6xx_pwrup_reglist, |
| 646 | sizeof(a6xx_pwrup_reglist)); |
| 647 | |
Deepak Kumar | 5287eea | 2018-03-17 14:33:05 +0530 | [diff] [blame] | 648 | if (adreno_is_a615(adreno_dev) || adreno_is_a616(adreno_dev)) { |
Akhil P Oommen | 35dde69 | 2018-01-16 18:01:09 +0530 | [diff] [blame] | 649 | for (i = 0; i < ARRAY_SIZE(a615_pwrup_reglist); i++) { |
| 650 | r = &a615_pwrup_reglist[i]; |
| 651 | kgsl_regread(KGSL_DEVICE(adreno_dev), |
| 652 | r->offset, &r->val); |
| 653 | } |
| 654 | |
| 655 | memcpy(adreno_dev->pwrup_reglist.hostptr + sizeof(*lock) |
| 656 | + sizeof(a6xx_ifpc_pwrup_reglist) |
| 657 | + sizeof(a6xx_pwrup_reglist), a615_pwrup_reglist, |
| 658 | sizeof(a615_pwrup_reglist)); |
| 659 | |
| 660 | lock->list_length += sizeof(a615_pwrup_reglist); |
| 661 | } |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 662 | } |
| 663 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 664 | /* |
| 665 | * a6xx_start() - Device start |
| 666 | * @adreno_dev: Pointer to adreno device |
| 667 | * |
| 668 | * a6xx device start |
| 669 | */ |
| 670 | static void a6xx_start(struct adreno_device *adreno_dev) |
| 671 | { |
| 672 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
Shrenuj Bansal | 397e589 | 2017-03-13 13:38:47 -0700 | [diff] [blame] | 673 | unsigned int bit, mal, mode, glbl_inv; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 674 | unsigned int amsbc = 0; |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 675 | static bool patch_reglist; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 676 | |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 677 | /* runtime adjust callbacks based on feature sets */ |
| 678 | if (!kgsl_gmu_isenabled(device)) |
| 679 | /* Legacy idle management if gmu is disabled */ |
| 680 | ADRENO_GPU_DEVICE(adreno_dev)->hw_isidle = NULL; |
Oleg Perelet | cb9b621 | 2017-03-16 15:38:43 -0700 | [diff] [blame] | 681 | /* enable hardware clockgating */ |
| 682 | a6xx_hwcg_set(adreno_dev, true); |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 683 | |
Oleg Perelet | c2ab7f7 | 2017-06-22 16:45:57 -0700 | [diff] [blame] | 684 | if (ADRENO_FEATURE(adreno_dev, ADRENO_LM)) |
| 685 | adreno_dev->lm_threshold_count = A6XX_GMU_GENERAL_1; |
| 686 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 687 | adreno_vbif_start(adreno_dev, a6xx_vbif_platforms, |
| 688 | ARRAY_SIZE(a6xx_vbif_platforms)); |
Harshdeep Dhatt | 75dbd41 | 2017-05-16 17:12:27 -0600 | [diff] [blame] | 689 | |
Deepak Kumar | 9cd4003 | 2017-12-27 13:02:10 +0530 | [diff] [blame] | 690 | if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_LIMIT_UCHE_GBIF_RW)) |
| 691 | kgsl_regwrite(device, A6XX_UCHE_GBIF_GX_CONFIG, 0x10200F9); |
| 692 | |
Harshdeep Dhatt | 75dbd41 | 2017-05-16 17:12:27 -0600 | [diff] [blame] | 693 | /* Make all blocks contribute to the GPU BUSY perf counter */ |
| 694 | kgsl_regwrite(device, A6XX_RBBM_PERFCTR_GPU_BUSY_MASKED, 0xFFFFFFFF); |
| 695 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 696 | /* |
| 697 | * Set UCHE_WRITE_THRU_BASE to the UCHE_TRAP_BASE effectively |
| 698 | * disabling L2 bypass |
| 699 | */ |
| 700 | kgsl_regwrite(device, A6XX_UCHE_WRITE_RANGE_MAX_LO, 0xffffffc0); |
| 701 | kgsl_regwrite(device, A6XX_UCHE_WRITE_RANGE_MAX_HI, 0x0001ffff); |
| 702 | kgsl_regwrite(device, A6XX_UCHE_TRAP_BASE_LO, 0xfffff000); |
| 703 | kgsl_regwrite(device, A6XX_UCHE_TRAP_BASE_HI, 0x0001ffff); |
| 704 | kgsl_regwrite(device, A6XX_UCHE_WRITE_THRU_BASE_LO, 0xfffff000); |
| 705 | kgsl_regwrite(device, A6XX_UCHE_WRITE_THRU_BASE_HI, 0x0001ffff); |
| 706 | |
| 707 | /* Program the GMEM VA range for the UCHE path */ |
| 708 | kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_LO, |
| 709 | ADRENO_UCHE_GMEM_BASE); |
| 710 | kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MIN_HI, 0x0); |
| 711 | kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_LO, |
| 712 | ADRENO_UCHE_GMEM_BASE + |
| 713 | adreno_dev->gmem_size - 1); |
| 714 | kgsl_regwrite(device, A6XX_UCHE_GMEM_RANGE_MAX_HI, 0x0); |
| 715 | |
| 716 | kgsl_regwrite(device, A6XX_UCHE_FILTER_CNTL, 0x804); |
| 717 | kgsl_regwrite(device, A6XX_UCHE_CACHE_WAYS, 0x4); |
| 718 | |
| 719 | kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x010000C0); |
| 720 | kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C); |
| 721 | |
| 722 | /* Setting the mem pool size */ |
| 723 | kgsl_regwrite(device, A6XX_CP_MEM_POOL_SIZE, 128); |
| 724 | |
| 725 | /* Setting the primFifo thresholds default values */ |
| 726 | kgsl_regwrite(device, A6XX_PC_DBG_ECO_CNTL, (0x300 << 11)); |
| 727 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 728 | /* Set the AHB default slave response to "ERROR" */ |
| 729 | kgsl_regwrite(device, A6XX_CP_AHB_CNTL, 0x1); |
| 730 | |
Harshdeep Dhatt | 859f3d6 | 2017-04-28 17:54:33 -0600 | [diff] [blame] | 731 | /* Turn on performance counters */ |
| 732 | kgsl_regwrite(device, A6XX_RBBM_PERFCTR_CNTL, 0x1); |
| 733 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 734 | if (of_property_read_u32(device->pdev->dev.of_node, |
| 735 | "qcom,highest-bank-bit", &bit)) |
| 736 | bit = MIN_HBB; |
| 737 | |
| 738 | if (of_property_read_u32(device->pdev->dev.of_node, |
| 739 | "qcom,min-access-length", &mal)) |
| 740 | mal = 32; |
| 741 | |
| 742 | if (of_property_read_u32(device->pdev->dev.of_node, |
| 743 | "qcom,ubwc-mode", &mode)) |
| 744 | mode = 0; |
| 745 | |
| 746 | switch (mode) { |
| 747 | case KGSL_UBWC_1_0: |
| 748 | mode = 1; |
| 749 | break; |
| 750 | case KGSL_UBWC_2_0: |
| 751 | mode = 0; |
| 752 | break; |
| 753 | case KGSL_UBWC_3_0: |
| 754 | mode = 0; |
| 755 | amsbc = 1; /* Only valid for A640 and A680 */ |
| 756 | break; |
| 757 | default: |
| 758 | break; |
| 759 | } |
| 760 | |
| 761 | if (bit >= 13 && bit <= 16) |
| 762 | bit = (bit - 13) & 0x03; |
| 763 | else |
| 764 | bit = 0; |
| 765 | |
| 766 | mal = (mal == 64) ? 1 : 0; |
| 767 | |
Shrenuj Bansal | 397e589 | 2017-03-13 13:38:47 -0700 | [diff] [blame] | 768 | /* (1 << 29)globalInvFlushFilterDis bit needs to be set for A630 V1 */ |
| 769 | glbl_inv = (adreno_is_a630v1(adreno_dev)) ? 1 : 0; |
| 770 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 771 | kgsl_regwrite(device, A6XX_RB_NC_MODE_CNTL, (amsbc << 4) | (mal << 3) | |
| 772 | (bit << 1) | mode); |
| 773 | kgsl_regwrite(device, A6XX_TPL1_NC_MODE_CNTL, (mal << 3) | |
| 774 | (bit << 1) | mode); |
| 775 | kgsl_regwrite(device, A6XX_SP_NC_MODE_CNTL, (mal << 3) | (bit << 1) | |
| 776 | mode); |
| 777 | |
Shrenuj Bansal | 397e589 | 2017-03-13 13:38:47 -0700 | [diff] [blame] | 778 | kgsl_regwrite(device, A6XX_UCHE_MODE_CNTL, (glbl_inv << 29) | |
| 779 | (mal << 23) | (bit << 21)); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 780 | |
Carter Cooper | f43f258 | 2017-08-17 17:07:42 -0600 | [diff] [blame] | 781 | /* Set hang detection threshold to 0x1FFFFF * 16 cycles */ |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 782 | kgsl_regwrite(device, A6XX_RBBM_INTERFACE_HANG_INT_CNTL, |
Carter Cooper | f43f258 | 2017-08-17 17:07:42 -0600 | [diff] [blame] | 783 | (1 << 30) | 0x1fffff); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 784 | |
Lynus Vaz | 1fde74d | 2017-03-20 18:02:47 +0530 | [diff] [blame] | 785 | kgsl_regwrite(device, A6XX_UCHE_CLIENT_PF, 1); |
| 786 | |
Lynus Vaz | 85c8cee | 2017-03-07 11:31:02 +0530 | [diff] [blame] | 787 | /* Set TWOPASSUSEWFI in A6XX_PC_DBG_ECO_CNTL if requested */ |
| 788 | if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_TWO_PASS_USE_WFI)) |
| 789 | kgsl_regrmw(device, A6XX_PC_DBG_ECO_CNTL, 0, (1 << 8)); |
| 790 | |
Harshdeep Dhatt | 0cdc899 | 2017-05-31 15:44:05 -0600 | [diff] [blame] | 791 | /* Enable the GMEM save/restore feature for preemption */ |
Harshdeep Dhatt | 7ee8a86 | 2017-11-20 17:51:54 -0700 | [diff] [blame] | 792 | if (adreno_is_preemption_enabled(adreno_dev)) |
Harshdeep Dhatt | 0cdc899 | 2017-05-31 15:44:05 -0600 | [diff] [blame] | 793 | kgsl_regwrite(device, A6XX_RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE, |
| 794 | 0x1); |
| 795 | |
Harshdeep Dhatt | 04d238d | 2018-02-15 10:58:47 -0700 | [diff] [blame] | 796 | a6xx_protect_init(adreno_dev); |
| 797 | |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 798 | if (!patch_reglist && (adreno_dev->pwrup_reglist.gpuaddr != 0)) { |
| 799 | a6xx_patch_pwrup_reglist(adreno_dev); |
| 800 | patch_reglist = true; |
| 801 | } |
| 802 | |
Harshdeep Dhatt | 0cdc899 | 2017-05-31 15:44:05 -0600 | [diff] [blame] | 803 | a6xx_preemption_start(adreno_dev); |
Harshdeep Dhatt | 720394d | 2017-09-13 14:25:09 -0600 | [diff] [blame] | 804 | |
| 805 | /* |
| 806 | * We start LM here because we want all the following to be up |
| 807 | * 1. GX HS |
| 808 | * 2. SPTPRAC |
| 809 | * 3. HFI |
| 810 | * At this point, we are guaranteed all. |
| 811 | */ |
| 812 | if (ADRENO_FEATURE(adreno_dev, ADRENO_LM) && |
| 813 | test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) { |
Harshdeep Dhatt | c116c0f | 2017-09-13 14:45:10 -0600 | [diff] [blame] | 814 | int result; |
| 815 | struct gmu_device *gmu = &device->gmu; |
| 816 | struct device *dev = &gmu->pdev->dev; |
| 817 | |
Harshdeep Dhatt | 720394d | 2017-09-13 14:25:09 -0600 | [diff] [blame] | 818 | kgsl_gmu_regwrite(device, A6XX_GPU_GMU_CX_GMU_PWR_THRESHOLD, |
| 819 | GPU_LIMIT_THRESHOLD_ENABLE | lm_limit(adreno_dev)); |
| 820 | kgsl_gmu_regwrite(device, A6XX_GMU_AO_SPARE_CNTL, 1); |
| 821 | kgsl_gmu_regwrite(device, A6XX_GPU_GMU_CX_GMU_ISENSE_CTRL, 0x1); |
Harshdeep Dhatt | c116c0f | 2017-09-13 14:45:10 -0600 | [diff] [blame] | 822 | |
| 823 | gmu->lm_config.lm_type = 1; |
| 824 | gmu->lm_config.lm_sensor_type = 1; |
| 825 | gmu->lm_config.throttle_config = 1; |
| 826 | gmu->lm_config.idle_throttle_en = 0; |
| 827 | gmu->lm_config.acd_en = 0; |
| 828 | gmu->bcl_config = 0; |
| 829 | gmu->lm_dcvs_level = 0; |
| 830 | |
| 831 | result = hfi_send_lmconfig(gmu); |
| 832 | if (result) |
| 833 | dev_err(dev, "Failure enabling limits management (%d)\n", |
| 834 | result); |
Harshdeep Dhatt | 720394d | 2017-09-13 14:25:09 -0600 | [diff] [blame] | 835 | } |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 836 | } |
| 837 | |
| 838 | /* |
| 839 | * a6xx_microcode_load() - Load microcode |
| 840 | * @adreno_dev: Pointer to adreno device |
| 841 | */ |
| 842 | static int a6xx_microcode_load(struct adreno_device *adreno_dev) |
| 843 | { |
| 844 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 845 | struct adreno_firmware *fw = ADRENO_FW(adreno_dev, ADRENO_FW_SQE); |
| 846 | uint64_t gpuaddr; |
Harshdeep Dhatt | a9e0d76 | 2017-05-10 14:16:42 -0600 | [diff] [blame] | 847 | void *zap; |
Carter Cooper | 4a313ae | 2017-02-23 11:11:56 -0700 | [diff] [blame] | 848 | int ret = 0; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 849 | |
| 850 | gpuaddr = fw->memdesc.gpuaddr; |
| 851 | kgsl_regwrite(device, A6XX_CP_SQE_INSTR_BASE_LO, |
| 852 | lower_32_bits(gpuaddr)); |
| 853 | kgsl_regwrite(device, A6XX_CP_SQE_INSTR_BASE_HI, |
| 854 | upper_32_bits(gpuaddr)); |
| 855 | |
Carter Cooper | 4a313ae | 2017-02-23 11:11:56 -0700 | [diff] [blame] | 856 | /* Load the zap shader firmware through PIL if its available */ |
Harshdeep Dhatt | a9e0d76 | 2017-05-10 14:16:42 -0600 | [diff] [blame] | 857 | if (adreno_dev->gpucore->zap_name && !adreno_dev->zap_loaded) { |
Carter Cooper | 4a313ae | 2017-02-23 11:11:56 -0700 | [diff] [blame] | 858 | zap = subsystem_get(adreno_dev->gpucore->zap_name); |
| 859 | |
| 860 | /* Return error if the zap shader cannot be loaded */ |
| 861 | if (IS_ERR_OR_NULL(zap)) { |
| 862 | ret = (zap == NULL) ? -ENODEV : PTR_ERR(zap); |
| 863 | zap = NULL; |
Harshdeep Dhatt | a9e0d76 | 2017-05-10 14:16:42 -0600 | [diff] [blame] | 864 | } else |
| 865 | adreno_dev->zap_loaded = 1; |
Carter Cooper | 4a313ae | 2017-02-23 11:11:56 -0700 | [diff] [blame] | 866 | } |
| 867 | |
| 868 | return ret; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 869 | } |
| 870 | |
| 871 | |
| 872 | /* |
| 873 | * CP_INIT_MAX_CONTEXT bit tells if the multiple hardware contexts can |
| 874 | * be used at once of if they should be serialized |
| 875 | */ |
| 876 | #define CP_INIT_MAX_CONTEXT BIT(0) |
| 877 | |
| 878 | /* Enables register protection mode */ |
| 879 | #define CP_INIT_ERROR_DETECTION_CONTROL BIT(1) |
| 880 | |
| 881 | /* Header dump information */ |
| 882 | #define CP_INIT_HEADER_DUMP BIT(2) /* Reserved */ |
| 883 | |
| 884 | /* Default Reset states enabled for PFP and ME */ |
| 885 | #define CP_INIT_DEFAULT_RESET_STATE BIT(3) |
| 886 | |
| 887 | /* Drawcall filter range */ |
| 888 | #define CP_INIT_DRAWCALL_FILTER_RANGE BIT(4) |
| 889 | |
| 890 | /* Ucode workaround masks */ |
| 891 | #define CP_INIT_UCODE_WORKAROUND_MASK BIT(5) |
| 892 | |
Jonathan Wicks | 20b1df9 | 2017-07-31 11:38:32 -0600 | [diff] [blame] | 893 | /* |
| 894 | * Operation mode mask |
| 895 | * |
| 896 | * This ordinal provides the option to disable the |
| 897 | * save/restore of performance counters across preemption. |
| 898 | */ |
| 899 | #define CP_INIT_OPERATION_MODE_MASK BIT(6) |
| 900 | |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 901 | /* Register initialization list */ |
| 902 | #define CP_INIT_REGISTER_INIT_LIST BIT(7) |
| 903 | |
Harshdeep Dhatt | d373aa5 | 2017-08-09 14:13:41 -0600 | [diff] [blame] | 904 | /* Register initialization list with spinlock */ |
| 905 | #define CP_INIT_REGISTER_INIT_LIST_WITH_SPINLOCK BIT(8) |
| 906 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 907 | #define CP_INIT_MASK (CP_INIT_MAX_CONTEXT | \ |
| 908 | CP_INIT_ERROR_DETECTION_CONTROL | \ |
| 909 | CP_INIT_HEADER_DUMP | \ |
| 910 | CP_INIT_DEFAULT_RESET_STATE | \ |
Jonathan Wicks | 20b1df9 | 2017-07-31 11:38:32 -0600 | [diff] [blame] | 911 | CP_INIT_UCODE_WORKAROUND_MASK | \ |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 912 | CP_INIT_OPERATION_MODE_MASK | \ |
Harshdeep Dhatt | d373aa5 | 2017-08-09 14:13:41 -0600 | [diff] [blame] | 913 | CP_INIT_REGISTER_INIT_LIST_WITH_SPINLOCK) |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 914 | |
| 915 | static void _set_ordinals(struct adreno_device *adreno_dev, |
| 916 | unsigned int *cmds, unsigned int count) |
| 917 | { |
| 918 | unsigned int *start = cmds; |
| 919 | |
| 920 | /* Enabled ordinal mask */ |
| 921 | *cmds++ = CP_INIT_MASK; |
| 922 | |
| 923 | if (CP_INIT_MASK & CP_INIT_MAX_CONTEXT) |
| 924 | *cmds++ = 0x00000003; |
| 925 | |
| 926 | if (CP_INIT_MASK & CP_INIT_ERROR_DETECTION_CONTROL) |
| 927 | *cmds++ = 0x20000000; |
| 928 | |
| 929 | if (CP_INIT_MASK & CP_INIT_HEADER_DUMP) { |
| 930 | /* Header dump address */ |
| 931 | *cmds++ = 0x00000000; |
| 932 | /* Header dump enable and dump size */ |
| 933 | *cmds++ = 0x00000000; |
| 934 | } |
| 935 | |
| 936 | if (CP_INIT_MASK & CP_INIT_DRAWCALL_FILTER_RANGE) { |
| 937 | /* Start range */ |
| 938 | *cmds++ = 0x00000000; |
| 939 | /* End range (inclusive) */ |
| 940 | *cmds++ = 0x00000000; |
| 941 | } |
| 942 | |
| 943 | if (CP_INIT_MASK & CP_INIT_UCODE_WORKAROUND_MASK) |
| 944 | *cmds++ = 0x00000000; |
| 945 | |
Jonathan Wicks | 20b1df9 | 2017-07-31 11:38:32 -0600 | [diff] [blame] | 946 | if (CP_INIT_MASK & CP_INIT_OPERATION_MODE_MASK) |
| 947 | *cmds++ = 0x00000002; |
| 948 | |
Harshdeep Dhatt | d373aa5 | 2017-08-09 14:13:41 -0600 | [diff] [blame] | 949 | if (CP_INIT_MASK & CP_INIT_REGISTER_INIT_LIST_WITH_SPINLOCK) { |
| 950 | uint64_t gpuaddr = adreno_dev->pwrup_reglist.gpuaddr; |
| 951 | |
| 952 | *cmds++ = lower_32_bits(gpuaddr); |
| 953 | *cmds++ = upper_32_bits(gpuaddr); |
| 954 | *cmds++ = 0; |
| 955 | |
| 956 | } else if (CP_INIT_MASK & CP_INIT_REGISTER_INIT_LIST) { |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 957 | uint64_t gpuaddr = adreno_dev->pwrup_reglist.gpuaddr; |
| 958 | |
| 959 | *cmds++ = lower_32_bits(gpuaddr); |
| 960 | *cmds++ = upper_32_bits(gpuaddr); |
| 961 | /* Size is in dwords */ |
Tarun Karra | 4ea6812 | 2017-11-02 18:10:31 -0700 | [diff] [blame] | 962 | *cmds++ = (sizeof(a6xx_ifpc_pwrup_reglist) + |
| 963 | sizeof(a6xx_pwrup_reglist)) >> 2; |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 964 | } |
| 965 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 966 | /* Pad rest of the cmds with 0's */ |
| 967 | while ((unsigned int)(cmds - start) < count) |
| 968 | *cmds++ = 0x0; |
| 969 | } |
| 970 | |
| 971 | /* |
| 972 | * a6xx_send_cp_init() - Initialize ringbuffer |
| 973 | * @adreno_dev: Pointer to adreno device |
| 974 | * @rb: Pointer to the ringbuffer of device |
| 975 | * |
| 976 | * Submit commands for ME initialization, |
| 977 | */ |
| 978 | static int a6xx_send_cp_init(struct adreno_device *adreno_dev, |
| 979 | struct adreno_ringbuffer *rb) |
| 980 | { |
| 981 | unsigned int *cmds; |
| 982 | int ret; |
| 983 | |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 984 | cmds = adreno_ringbuffer_allocspace(rb, 12); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 985 | if (IS_ERR(cmds)) |
| 986 | return PTR_ERR(cmds); |
| 987 | |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 988 | *cmds++ = cp_type7_packet(CP_ME_INIT, 11); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 989 | |
Harshdeep Dhatt | d0f38f6 | 2017-06-01 12:45:26 -0600 | [diff] [blame] | 990 | _set_ordinals(adreno_dev, cmds, 11); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 991 | |
| 992 | ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000); |
| 993 | if (ret) |
Carter Cooper | 8567af0 | 2017-03-15 14:22:03 -0600 | [diff] [blame] | 994 | adreno_spin_idle_debug(adreno_dev, |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 995 | "CP initialization failed to idle\n"); |
| 996 | |
| 997 | return ret; |
| 998 | } |
| 999 | |
| 1000 | /* |
Harshdeep Dhatt | 0cdc899 | 2017-05-31 15:44:05 -0600 | [diff] [blame] | 1001 | * Follow the ME_INIT sequence with a preemption yield to allow the GPU to move |
| 1002 | * to a different ringbuffer, if desired |
| 1003 | */ |
| 1004 | static int _preemption_init(struct adreno_device *adreno_dev, |
| 1005 | struct adreno_ringbuffer *rb, unsigned int *cmds, |
| 1006 | struct kgsl_context *context) |
| 1007 | { |
| 1008 | unsigned int *cmds_orig = cmds; |
| 1009 | |
| 1010 | /* Turn CP protection OFF */ |
| 1011 | *cmds++ = cp_type7_packet(CP_SET_PROTECTED_MODE, 1); |
| 1012 | *cmds++ = 0; |
| 1013 | |
| 1014 | *cmds++ = cp_type7_packet(CP_SET_PSEUDO_REGISTER, 6); |
| 1015 | *cmds++ = 1; |
| 1016 | cmds += cp_gpuaddr(adreno_dev, cmds, |
| 1017 | rb->preemption_desc.gpuaddr); |
| 1018 | |
| 1019 | *cmds++ = 2; |
Harshdeep Dhatt | 58b70eb | 2017-03-28 09:21:40 -0600 | [diff] [blame] | 1020 | cmds += cp_gpuaddr(adreno_dev, cmds, |
| 1021 | rb->secure_preemption_desc.gpuaddr); |
Harshdeep Dhatt | 0cdc899 | 2017-05-31 15:44:05 -0600 | [diff] [blame] | 1022 | |
| 1023 | /* Turn CP protection ON */ |
| 1024 | *cmds++ = cp_type7_packet(CP_SET_PROTECTED_MODE, 1); |
| 1025 | *cmds++ = 1; |
| 1026 | |
| 1027 | *cmds++ = cp_type7_packet(CP_CONTEXT_SWITCH_YIELD, 4); |
| 1028 | cmds += cp_gpuaddr(adreno_dev, cmds, 0x0); |
| 1029 | *cmds++ = 0; |
| 1030 | /* generate interrupt on preemption completion */ |
| 1031 | *cmds++ = 0; |
| 1032 | |
| 1033 | return cmds - cmds_orig; |
| 1034 | } |
| 1035 | |
| 1036 | static int a6xx_post_start(struct adreno_device *adreno_dev) |
| 1037 | { |
| 1038 | int ret; |
| 1039 | unsigned int *cmds, *start; |
| 1040 | struct adreno_ringbuffer *rb = adreno_dev->cur_rb; |
| 1041 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 1042 | |
Harshdeep Dhatt | 7ee8a86 | 2017-11-20 17:51:54 -0700 | [diff] [blame] | 1043 | if (!adreno_is_preemption_enabled(adreno_dev)) |
Harshdeep Dhatt | 0cdc899 | 2017-05-31 15:44:05 -0600 | [diff] [blame] | 1044 | return 0; |
| 1045 | |
| 1046 | cmds = adreno_ringbuffer_allocspace(rb, 42); |
| 1047 | if (IS_ERR(cmds)) { |
| 1048 | KGSL_DRV_ERR(device, "error allocating preemption init cmds"); |
| 1049 | return PTR_ERR(cmds); |
| 1050 | } |
| 1051 | start = cmds; |
| 1052 | |
| 1053 | cmds += _preemption_init(adreno_dev, rb, cmds, NULL); |
| 1054 | |
| 1055 | rb->_wptr = rb->_wptr - (42 - (cmds - start)); |
| 1056 | |
| 1057 | ret = adreno_ringbuffer_submit_spin(rb, NULL, 2000); |
| 1058 | if (ret) |
| 1059 | adreno_spin_idle_debug(adreno_dev, |
| 1060 | "hw preemption initialization failed to idle\n"); |
| 1061 | |
| 1062 | return ret; |
| 1063 | } |
| 1064 | |
| 1065 | /* |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1066 | * a6xx_rb_start() - Start the ringbuffer |
| 1067 | * @adreno_dev: Pointer to adreno device |
| 1068 | * @start_type: Warm or cold start |
| 1069 | */ |
| 1070 | static int a6xx_rb_start(struct adreno_device *adreno_dev, |
| 1071 | unsigned int start_type) |
| 1072 | { |
| 1073 | struct adreno_ringbuffer *rb = ADRENO_CURRENT_RINGBUFFER(adreno_dev); |
| 1074 | struct kgsl_device *device = &adreno_dev->dev; |
| 1075 | uint64_t addr; |
| 1076 | int ret; |
| 1077 | |
| 1078 | addr = SCRATCH_RPTR_GPU_ADDR(device, rb->id); |
| 1079 | |
| 1080 | adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_RPTR_ADDR_LO, |
| 1081 | ADRENO_REG_CP_RB_RPTR_ADDR_HI, addr); |
| 1082 | |
| 1083 | /* |
| 1084 | * The size of the ringbuffer in the hardware is the log2 |
| 1085 | * representation of the size in quadwords (sizedwords / 2). |
| 1086 | */ |
| 1087 | adreno_writereg(adreno_dev, ADRENO_REG_CP_RB_CNTL, |
| 1088 | A6XX_CP_RB_CNTL_DEFAULT); |
| 1089 | |
Deepak Kumar | 756d6a9 | 2017-11-28 16:58:29 +0530 | [diff] [blame] | 1090 | adreno_writereg64(adreno_dev, ADRENO_REG_CP_RB_BASE, |
| 1091 | ADRENO_REG_CP_RB_BASE_HI, rb->buffer_desc.gpuaddr); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1092 | |
| 1093 | ret = a6xx_microcode_load(adreno_dev); |
| 1094 | if (ret) |
| 1095 | return ret; |
| 1096 | |
| 1097 | /* Clear the SQE_HALT to start the CP engine */ |
| 1098 | kgsl_regwrite(device, A6XX_CP_SQE_CNTL, 1); |
| 1099 | |
Carter Cooper | 4a313ae | 2017-02-23 11:11:56 -0700 | [diff] [blame] | 1100 | ret = a6xx_send_cp_init(adreno_dev, rb); |
| 1101 | if (ret) |
| 1102 | return ret; |
| 1103 | |
| 1104 | /* GPU comes up in secured mode, make it unsecured by default */ |
Harshdeep Dhatt | 0cdc899 | 2017-05-31 15:44:05 -0600 | [diff] [blame] | 1105 | ret = adreno_set_unsecured_mode(adreno_dev, rb); |
| 1106 | if (ret) |
| 1107 | return ret; |
| 1108 | |
| 1109 | return a6xx_post_start(adreno_dev); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1110 | } |
| 1111 | |
Kyle Piefer | edc6c8a | 2017-11-10 14:51:58 -0800 | [diff] [blame] | 1112 | unsigned int a6xx_set_marker( |
| 1113 | unsigned int *cmds, enum adreno_cp_marker_type type) |
| 1114 | { |
| 1115 | unsigned int cmd = 0; |
| 1116 | |
| 1117 | *cmds++ = cp_type7_packet(CP_SET_MARKER, 1); |
| 1118 | |
| 1119 | /* |
| 1120 | * Indicate the beginning and end of the IB1 list with a SET_MARKER. |
| 1121 | * Among other things, this will implicitly enable and disable |
| 1122 | * preemption respectively. IFPC can also be disabled and enabled |
| 1123 | * with a SET_MARKER. Bit 8 tells the CP the marker is for IFPC. |
| 1124 | */ |
| 1125 | switch (type) { |
| 1126 | case IFPC_DISABLE: |
| 1127 | cmd = 0x101; |
| 1128 | break; |
| 1129 | case IFPC_ENABLE: |
| 1130 | cmd = 0x100; |
| 1131 | break; |
| 1132 | case IB1LIST_START: |
| 1133 | cmd = 0xD; |
| 1134 | break; |
| 1135 | case IB1LIST_END: |
| 1136 | cmd = 0xE; |
| 1137 | break; |
| 1138 | } |
| 1139 | |
| 1140 | *cmds++ = cmd; |
| 1141 | return 2; |
| 1142 | } |
| 1143 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1144 | static int _load_firmware(struct kgsl_device *device, const char *fwfile, |
| 1145 | struct adreno_firmware *firmware) |
| 1146 | { |
| 1147 | const struct firmware *fw = NULL; |
| 1148 | int ret; |
| 1149 | |
| 1150 | ret = request_firmware(&fw, fwfile, device->dev); |
| 1151 | |
| 1152 | if (ret) { |
| 1153 | KGSL_DRV_ERR(device, "request_firmware(%s) failed: %d\n", |
| 1154 | fwfile, ret); |
| 1155 | return ret; |
| 1156 | } |
| 1157 | |
| 1158 | ret = kgsl_allocate_global(device, &firmware->memdesc, fw->size - 4, |
| 1159 | KGSL_MEMFLAGS_GPUREADONLY, 0, "ucode"); |
| 1160 | |
| 1161 | if (!ret) { |
| 1162 | memcpy(firmware->memdesc.hostptr, &fw->data[4], fw->size - 4); |
| 1163 | firmware->size = (fw->size - 4) / sizeof(uint32_t); |
| 1164 | firmware->version = *(unsigned int *)&fw->data[4]; |
| 1165 | } |
| 1166 | |
| 1167 | release_firmware(fw); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1168 | return ret; |
| 1169 | } |
| 1170 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1171 | #define RSC_CMD_OFFSET 2 |
| 1172 | #define PDC_CMD_OFFSET 4 |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1173 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1174 | static void _regwrite(void __iomem *regbase, |
| 1175 | unsigned int offsetwords, unsigned int value) |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1176 | { |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1177 | void __iomem *reg; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1178 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1179 | reg = regbase + (offsetwords << 2); |
| 1180 | __raw_writel(value, reg); |
| 1181 | } |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1182 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1183 | /* |
| 1184 | * _load_gmu_rpmh_ucode() - Load the ucode into the GPU PDC/RSC blocks |
| 1185 | * PDC and RSC execute GPU power on/off RPMh sequence |
| 1186 | * @device: Pointer to KGSL device |
| 1187 | */ |
| 1188 | static void _load_gmu_rpmh_ucode(struct kgsl_device *device) |
| 1189 | { |
Kyle Piefer | 8e37717 | 2017-08-10 13:24:09 -0700 | [diff] [blame] | 1190 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1191 | struct gmu_device *gmu = &device->gmu; |
| 1192 | |
Kyle Piefer | 8e37717 | 2017-08-10 13:24:09 -0700 | [diff] [blame] | 1193 | /* Disable SDE clock gating */ |
| 1194 | kgsl_gmu_regwrite(device, A6XX_GPU_RSCC_RSC_STATUS0_DRV0, BIT(24)); |
| 1195 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1196 | /* Setup RSC PDC handshake for sleep and wakeup */ |
| 1197 | kgsl_gmu_regwrite(device, A6XX_RSCC_PDC_SLAVE_ID_DRV0, 1); |
| 1198 | kgsl_gmu_regwrite(device, A6XX_RSCC_HIDDEN_TCS_CMD0_DATA, 0); |
| 1199 | kgsl_gmu_regwrite(device, A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR, 0); |
| 1200 | kgsl_gmu_regwrite(device, |
| 1201 | A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + RSC_CMD_OFFSET, 0); |
| 1202 | kgsl_gmu_regwrite(device, |
| 1203 | A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + RSC_CMD_OFFSET, 0); |
| 1204 | kgsl_gmu_regwrite(device, |
| 1205 | A6XX_RSCC_HIDDEN_TCS_CMD0_DATA + RSC_CMD_OFFSET * 2, |
| 1206 | 0x80000000); |
| 1207 | kgsl_gmu_regwrite(device, |
| 1208 | A6XX_RSCC_HIDDEN_TCS_CMD0_ADDR + RSC_CMD_OFFSET * 2, |
| 1209 | 0); |
| 1210 | kgsl_gmu_regwrite(device, A6XX_RSCC_OVERRIDE_START_ADDR, 0); |
| 1211 | kgsl_gmu_regwrite(device, A6XX_RSCC_PDC_SEQ_START_ADDR, 0x4520); |
| 1212 | kgsl_gmu_regwrite(device, A6XX_RSCC_PDC_MATCH_VALUE_LO, 0x4510); |
| 1213 | kgsl_gmu_regwrite(device, A6XX_RSCC_PDC_MATCH_VALUE_HI, 0x4514); |
| 1214 | |
Kyle Piefer | 8e37717 | 2017-08-10 13:24:09 -0700 | [diff] [blame] | 1215 | /* Enable timestamp event for v1 only */ |
| 1216 | if (adreno_is_a630v1(adreno_dev)) |
| 1217 | kgsl_gmu_regwrite(device, A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0, 1); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1218 | |
| 1219 | /* Load RSC sequencer uCode for sleep and wakeup */ |
| 1220 | kgsl_gmu_regwrite(device, A6XX_RSCC_SEQ_MEM_0_DRV0, 0xA7A506A0); |
| 1221 | kgsl_gmu_regwrite(device, A6XX_RSCC_SEQ_MEM_0_DRV0 + 1, 0xA1E6A6E7); |
| 1222 | kgsl_gmu_regwrite(device, A6XX_RSCC_SEQ_MEM_0_DRV0 + 2, 0xA2E081E1); |
| 1223 | kgsl_gmu_regwrite(device, A6XX_RSCC_SEQ_MEM_0_DRV0 + 3, 0xE9A982E2); |
| 1224 | kgsl_gmu_regwrite(device, A6XX_RSCC_SEQ_MEM_0_DRV0 + 4, 0x0020E8A8); |
| 1225 | |
| 1226 | /* Load PDC sequencer uCode for power up and power down sequence */ |
Kyle Piefer | 8e37717 | 2017-08-10 13:24:09 -0700 | [diff] [blame] | 1227 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0, 0xFEBEA1E1); |
| 1228 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 1, 0xA5A4A3A2); |
| 1229 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 2, 0x8382A6E0); |
| 1230 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 3, 0xBCE3E284); |
| 1231 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_MEM_0 + 4, 0x002081FC); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1232 | |
| 1233 | /* Set TCS commands used by PDC sequence for low power modes */ |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1234 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD_ENABLE_BANK, 7); |
| 1235 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK, 0); |
| 1236 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CONTROL, 0); |
| 1237 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_MSGID, 0x10108); |
| 1238 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_ADDR, 0x30010); |
Kyle Piefer | 8714918 | 2017-10-05 15:01:33 -0700 | [diff] [blame] | 1239 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS1_CMD0_DATA, 1); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1240 | _regwrite(gmu->pdc_reg_virt, |
| 1241 | PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET, 0x10108); |
| 1242 | _regwrite(gmu->pdc_reg_virt, |
| 1243 | PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET, 0x30000); |
| 1244 | _regwrite(gmu->pdc_reg_virt, |
Kyle Piefer | 8714918 | 2017-10-05 15:01:33 -0700 | [diff] [blame] | 1245 | PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET, 0x0); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1246 | _regwrite(gmu->pdc_reg_virt, |
| 1247 | PDC_GPU_TCS1_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108); |
| 1248 | _regwrite(gmu->pdc_reg_virt, |
| 1249 | PDC_GPU_TCS1_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30080); |
| 1250 | _regwrite(gmu->pdc_reg_virt, |
Kyle Piefer | 8714918 | 2017-10-05 15:01:33 -0700 | [diff] [blame] | 1251 | PDC_GPU_TCS1_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x0); |
| 1252 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD_ENABLE_BANK, 7); |
| 1253 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK, 0); |
| 1254 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CONTROL, 0); |
| 1255 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_MSGID, 0x10108); |
| 1256 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_ADDR, 0x30010); |
| 1257 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_TCS3_CMD0_DATA, 2); |
| 1258 | _regwrite(gmu->pdc_reg_virt, |
| 1259 | PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET, 0x10108); |
| 1260 | _regwrite(gmu->pdc_reg_virt, |
| 1261 | PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET, 0x30000); |
| 1262 | _regwrite(gmu->pdc_reg_virt, |
George Shen | fec34f3 | 2018-03-05 11:57:19 -0800 | [diff] [blame] | 1263 | PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET, 0x3); |
Kyle Piefer | 8714918 | 2017-10-05 15:01:33 -0700 | [diff] [blame] | 1264 | _regwrite(gmu->pdc_reg_virt, |
| 1265 | PDC_GPU_TCS3_CMD0_MSGID + PDC_CMD_OFFSET * 2, 0x10108); |
| 1266 | _regwrite(gmu->pdc_reg_virt, |
| 1267 | PDC_GPU_TCS3_CMD0_ADDR + PDC_CMD_OFFSET * 2, 0x30080); |
| 1268 | _regwrite(gmu->pdc_reg_virt, |
| 1269 | PDC_GPU_TCS3_CMD0_DATA + PDC_CMD_OFFSET * 2, 0x3); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1270 | |
| 1271 | /* Setup GPU PDC */ |
| 1272 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_SEQ_START_ADDR, 0); |
| 1273 | _regwrite(gmu->pdc_reg_virt, PDC_GPU_ENABLE_PDC, 0x80000001); |
| 1274 | |
| 1275 | /* ensure no writes happen before the uCode is fully written */ |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1276 | wmb(); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1277 | } |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1278 | |
Oleg Perelet | 3bbc63a | 2018-01-26 10:05:25 -0800 | [diff] [blame] | 1279 | #define GMU_START_TIMEOUT 100 /* ms */ |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1280 | #define GPU_START_TIMEOUT 100 /* ms */ |
| 1281 | #define GPU_RESET_TIMEOUT 1 /* ms */ |
| 1282 | #define GPU_RESET_TIMEOUT_US 10 /* us */ |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1283 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1284 | /* |
| 1285 | * timed_poll_check() - polling *gmu* register at given offset until |
| 1286 | * its value changed to match expected value. The function times |
| 1287 | * out and returns after given duration if register is not updated |
| 1288 | * as expected. |
| 1289 | * |
| 1290 | * @device: Pointer to KGSL device |
| 1291 | * @offset: Register offset |
| 1292 | * @expected_ret: expected register value that stops polling |
| 1293 | * @timout: number of jiffies to abort the polling |
| 1294 | * @mask: bitmask to filter register value to match expected_ret |
| 1295 | */ |
| 1296 | static int timed_poll_check(struct kgsl_device *device, |
| 1297 | unsigned int offset, unsigned int expected_ret, |
| 1298 | unsigned int timeout, unsigned int mask) |
| 1299 | { |
| 1300 | unsigned long t; |
| 1301 | unsigned int value; |
| 1302 | |
| 1303 | t = jiffies + msecs_to_jiffies(timeout); |
| 1304 | |
Kyle Piefer | d9e09dc | 2017-05-19 16:34:43 -0700 | [diff] [blame] | 1305 | do { |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1306 | kgsl_gmu_regread(device, offset, &value); |
| 1307 | if ((value & mask) == expected_ret) |
| 1308 | return 0; |
George Shen | 56c9cdb | 2017-08-25 10:43:32 -0700 | [diff] [blame] | 1309 | /* Wait 100us to reduce unnecessary AHB bus traffic */ |
Oleg Perelet | 7f7f9f5 | 2017-10-31 10:02:45 -0700 | [diff] [blame] | 1310 | usleep_range(10, 100); |
Kyle Piefer | d9e09dc | 2017-05-19 16:34:43 -0700 | [diff] [blame] | 1311 | } while (!time_after(jiffies, t)); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1312 | |
Carter Cooper | 1ee715a | 2017-09-07 16:08:38 -0600 | [diff] [blame] | 1313 | /* Double check one last time */ |
| 1314 | kgsl_gmu_regread(device, offset, &value); |
| 1315 | if ((value & mask) == expected_ret) |
| 1316 | return 0; |
| 1317 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1318 | return -EINVAL; |
| 1319 | } |
| 1320 | |
| 1321 | /* |
Kyle Piefer | 4edfb6b | 2017-08-03 16:42:09 -0700 | [diff] [blame] | 1322 | * The lowest 16 bits of this value are the number of XO clock cycles |
| 1323 | * for main hysteresis. This is the first hysteresis. Here we set it |
Kyle Piefer | bfed916 | 2017-10-13 13:29:00 -0700 | [diff] [blame] | 1324 | * to 0x1680 cycles, or 300 us. The highest 16 bits of this value are |
Kyle Piefer | 4edfb6b | 2017-08-03 16:42:09 -0700 | [diff] [blame] | 1325 | * the number of XO clock cycles for short hysteresis. This happens |
| 1326 | * after main hysteresis. Here we set it to 0xA cycles, or 0.5 us. |
| 1327 | */ |
Kyle Piefer | bfed916 | 2017-10-13 13:29:00 -0700 | [diff] [blame] | 1328 | #define GMU_PWR_COL_HYST 0x000A1680 |
Kyle Piefer | 4edfb6b | 2017-08-03 16:42:09 -0700 | [diff] [blame] | 1329 | |
| 1330 | /* |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1331 | * a6xx_gmu_power_config() - Configure and enable GMU's low power mode |
| 1332 | * setting based on ADRENO feature flags. |
| 1333 | * @device: Pointer to KGSL device |
| 1334 | */ |
| 1335 | static void a6xx_gmu_power_config(struct kgsl_device *device) |
| 1336 | { |
| 1337 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 1338 | struct gmu_device *gmu = &device->gmu; |
| 1339 | |
Kyle Piefer | d396416 | 2017-04-06 15:44:03 -0700 | [diff] [blame] | 1340 | /* Configure registers for idle setting. The setting is cumulative */ |
George Shen | c4c7426 | 2017-05-11 15:37:34 -0700 | [diff] [blame] | 1341 | |
George Shen | 1f312ab | 2017-08-01 10:53:50 -0700 | [diff] [blame] | 1342 | /* Disable GMU WB/RB buffer */ |
| 1343 | kgsl_gmu_regwrite(device, A6XX_GMU_SYS_BUS_CONFIG, 0x1); |
| 1344 | |
George Shen | c4c7426 | 2017-05-11 15:37:34 -0700 | [diff] [blame] | 1345 | kgsl_gmu_regwrite(device, |
| 1346 | A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0x9C40400); |
| 1347 | |
Kyle Piefer | d396416 | 2017-04-06 15:44:03 -0700 | [diff] [blame] | 1348 | switch (gmu->idle_level) { |
| 1349 | case GPU_HW_MIN_VOLT: |
Kyle Piefer | dc0706c | 2017-04-13 13:17:50 -0700 | [diff] [blame] | 1350 | kgsl_gmu_regrmw(device, A6XX_GMU_RPMH_CTRL, 0, |
| 1351 | MIN_BW_ENABLE_MASK); |
| 1352 | kgsl_gmu_regrmw(device, A6XX_GMU_RPMH_HYST_CTRL, 0, |
| 1353 | MIN_BW_HYST); |
Kyle Piefer | d396416 | 2017-04-06 15:44:03 -0700 | [diff] [blame] | 1354 | /* fall through */ |
| 1355 | case GPU_HW_NAP: |
Kyle Piefer | dc0706c | 2017-04-13 13:17:50 -0700 | [diff] [blame] | 1356 | kgsl_gmu_regrmw(device, A6XX_GMU_GPU_NAP_CTRL, 0, |
| 1357 | HW_NAP_ENABLE_MASK); |
Kyle Piefer | d396416 | 2017-04-06 15:44:03 -0700 | [diff] [blame] | 1358 | /* fall through */ |
| 1359 | case GPU_HW_IFPC: |
| 1360 | kgsl_gmu_regwrite(device, A6XX_GMU_PWR_COL_INTER_FRAME_HYST, |
Kyle Piefer | 4edfb6b | 2017-08-03 16:42:09 -0700 | [diff] [blame] | 1361 | GMU_PWR_COL_HYST); |
Kyle Piefer | dc0706c | 2017-04-13 13:17:50 -0700 | [diff] [blame] | 1362 | kgsl_gmu_regrmw(device, A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, |
Kyle Piefer | d396416 | 2017-04-06 15:44:03 -0700 | [diff] [blame] | 1363 | IFPC_ENABLE_MASK); |
| 1364 | /* fall through */ |
| 1365 | case GPU_HW_SPTP_PC: |
| 1366 | kgsl_gmu_regwrite(device, A6XX_GMU_PWR_COL_SPTPRAC_HYST, |
Kyle Piefer | 4edfb6b | 2017-08-03 16:42:09 -0700 | [diff] [blame] | 1367 | GMU_PWR_COL_HYST); |
Kyle Piefer | dc0706c | 2017-04-13 13:17:50 -0700 | [diff] [blame] | 1368 | kgsl_gmu_regrmw(device, A6XX_GMU_PWR_COL_INTER_FRAME_CTRL, 0, |
Kyle Piefer | d396416 | 2017-04-06 15:44:03 -0700 | [diff] [blame] | 1369 | SPTP_ENABLE_MASK); |
| 1370 | /* fall through */ |
| 1371 | default: |
| 1372 | break; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1373 | } |
| 1374 | |
Kyle Piefer | 3a5ac09 | 2017-04-06 16:05:30 -0700 | [diff] [blame] | 1375 | /* ACD feature enablement */ |
Oleg Perelet | c2ab7f7 | 2017-06-22 16:45:57 -0700 | [diff] [blame] | 1376 | if (ADRENO_FEATURE(adreno_dev, ADRENO_LM) && |
| 1377 | test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) |
Kyle Piefer | dc0706c | 2017-04-13 13:17:50 -0700 | [diff] [blame] | 1378 | kgsl_gmu_regrmw(device, A6XX_GMU_BOOT_KMD_LM_HANDSHAKE, 0, |
| 1379 | BIT(10)); |
Kyle Piefer | 3a5ac09 | 2017-04-06 16:05:30 -0700 | [diff] [blame] | 1380 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1381 | /* Enable RPMh GPU client */ |
| 1382 | if (ADRENO_FEATURE(adreno_dev, ADRENO_RPMH)) |
Kyle Piefer | dc0706c | 2017-04-13 13:17:50 -0700 | [diff] [blame] | 1383 | kgsl_gmu_regrmw(device, A6XX_GMU_RPMH_CTRL, 0, |
| 1384 | RPMH_ENABLE_MASK); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1385 | } |
| 1386 | |
| 1387 | /* |
| 1388 | * a6xx_gmu_start() - Start GMU and wait until FW boot up. |
| 1389 | * @device: Pointer to KGSL device |
| 1390 | */ |
| 1391 | static int a6xx_gmu_start(struct kgsl_device *device) |
| 1392 | { |
| 1393 | struct gmu_device *gmu = &device->gmu; |
| 1394 | |
Oleg Perelet | 5d2d28f | 2018-03-06 17:03:20 -0800 | [diff] [blame] | 1395 | kgsl_regwrite(device, A6XX_GMU_CX_GMU_WFI_CONFIG, 0x0); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1396 | /* Write 1 first to make sure the GMU is reset */ |
| 1397 | kgsl_gmu_regwrite(device, A6XX_GMU_CM3_SYSRESET, 1); |
| 1398 | |
| 1399 | /* Make sure putting in reset doesn't happen after clearing */ |
| 1400 | wmb(); |
| 1401 | |
| 1402 | /* Bring GMU out of reset */ |
| 1403 | kgsl_gmu_regwrite(device, A6XX_GMU_CM3_SYSRESET, 0); |
| 1404 | if (timed_poll_check(device, |
| 1405 | A6XX_GMU_CM3_FW_INIT_RESULT, |
| 1406 | 0xBABEFACE, |
| 1407 | GMU_START_TIMEOUT, |
| 1408 | 0xFFFFFFFF)) { |
| 1409 | dev_err(&gmu->pdev->dev, "GMU doesn't boot\n"); |
| 1410 | return -ETIMEDOUT; |
| 1411 | } |
| 1412 | |
| 1413 | return 0; |
| 1414 | } |
| 1415 | |
| 1416 | /* |
| 1417 | * a6xx_gmu_hfi_start() - Write registers and start HFI. |
| 1418 | * @device: Pointer to KGSL device |
| 1419 | */ |
| 1420 | static int a6xx_gmu_hfi_start(struct kgsl_device *device) |
| 1421 | { |
| 1422 | struct gmu_device *gmu = &device->gmu; |
| 1423 | |
Kyle Piefer | e7b06b4 | 2017-04-06 13:53:01 -0700 | [diff] [blame] | 1424 | kgsl_gmu_regrmw(device, A6XX_GMU_GMU2HOST_INTR_MASK, |
| 1425 | HFI_IRQ_MSGQ_MASK, 0); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1426 | kgsl_gmu_regwrite(device, A6XX_GMU_HFI_CTRL_INIT, 1); |
| 1427 | |
| 1428 | if (timed_poll_check(device, |
| 1429 | A6XX_GMU_HFI_CTRL_STATUS, |
| 1430 | BIT(0), |
| 1431 | GMU_START_TIMEOUT, |
| 1432 | BIT(0))) { |
| 1433 | dev_err(&gmu->pdev->dev, "GMU HFI init failed\n"); |
| 1434 | return -ETIMEDOUT; |
| 1435 | } |
| 1436 | |
| 1437 | return 0; |
| 1438 | } |
| 1439 | |
| 1440 | /* |
| 1441 | * a6xx_oob_set() - Set OOB interrupt to GMU. |
| 1442 | * @adreno_dev: Pointer to adreno device |
| 1443 | * @set_mask: set_mask is a bitmask that defines a set of OOB |
| 1444 | * interrupts to trigger. |
| 1445 | * @check_mask: check_mask is a bitmask that provides a set of |
| 1446 | * OOB ACK bits. check_mask usually matches set_mask to |
| 1447 | * ensure OOBs are handled. |
| 1448 | * @clear_mask: After GMU handles a OOB interrupt, GMU driver |
| 1449 | * clears the interrupt. clear_mask is a bitmask defines |
| 1450 | * a set of OOB interrupts to clear. |
| 1451 | */ |
| 1452 | static int a6xx_oob_set(struct adreno_device *adreno_dev, |
| 1453 | unsigned int set_mask, unsigned int check_mask, |
| 1454 | unsigned int clear_mask) |
| 1455 | { |
| 1456 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1457 | int ret = 0; |
| 1458 | |
George Shen | a458dd9 | 2018-01-03 14:20:34 -0800 | [diff] [blame] | 1459 | if (!kgsl_gmu_isenabled(device) || !clear_mask) |
Kyle Piefer | c75922e | 2017-05-18 15:05:07 -0700 | [diff] [blame] | 1460 | return 0; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1461 | |
| 1462 | kgsl_gmu_regwrite(device, A6XX_GMU_HOST2GMU_INTR_SET, set_mask); |
| 1463 | |
| 1464 | if (timed_poll_check(device, |
| 1465 | A6XX_GMU_GMU2HOST_INTR_INFO, |
| 1466 | check_mask, |
| 1467 | GPU_START_TIMEOUT, |
| 1468 | check_mask)) { |
| 1469 | ret = -ETIMEDOUT; |
George Shen | 7201a6d | 2017-11-03 10:39:36 -0700 | [diff] [blame] | 1470 | WARN(1, "OOB set timed out, mask %x\n", set_mask); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1471 | } |
| 1472 | |
| 1473 | kgsl_gmu_regwrite(device, A6XX_GMU_GMU2HOST_INTR_CLR, clear_mask); |
| 1474 | |
George Shen | a458dd9 | 2018-01-03 14:20:34 -0800 | [diff] [blame] | 1475 | set_bit((fls(clear_mask) - 1), &a6xx_oob_state_bitmask); |
| 1476 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1477 | trace_kgsl_gmu_oob_set(set_mask); |
| 1478 | return ret; |
| 1479 | } |
| 1480 | |
| 1481 | /* |
| 1482 | * a6xx_oob_clear() - Clear a previously set OOB request. |
| 1483 | * @adreno_dev: Pointer to the adreno device that has the GMU |
| 1484 | * @clear_mask: Bitmask that provides the OOB bits to clear |
| 1485 | */ |
| 1486 | static inline void a6xx_oob_clear(struct adreno_device *adreno_dev, |
| 1487 | unsigned int clear_mask) |
| 1488 | { |
| 1489 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 1490 | |
George Shen | a458dd9 | 2018-01-03 14:20:34 -0800 | [diff] [blame] | 1491 | if (!kgsl_gmu_isenabled(device) || !clear_mask) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1492 | return; |
| 1493 | |
George Shen | a458dd9 | 2018-01-03 14:20:34 -0800 | [diff] [blame] | 1494 | if (test_and_clear_bit(fls(clear_mask) - 1, |
| 1495 | &a6xx_oob_state_bitmask)) |
| 1496 | kgsl_gmu_regwrite(device, |
| 1497 | A6XX_GMU_HOST2GMU_INTR_SET, |
| 1498 | clear_mask); |
| 1499 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1500 | trace_kgsl_gmu_oob_clear(clear_mask); |
| 1501 | } |
| 1502 | |
Carter Cooper | df7ba70 | 2017-03-20 11:28:04 -0600 | [diff] [blame] | 1503 | /* |
| 1504 | * a6xx_gpu_keepalive() - GMU reg write to request GPU stays on |
| 1505 | * @adreno_dev: Pointer to the adreno device that has the GMU |
| 1506 | * @state: State to set: true is ON, false is OFF |
| 1507 | */ |
| 1508 | static inline void a6xx_gpu_keepalive(struct adreno_device *adreno_dev, |
| 1509 | bool state) |
| 1510 | { |
| 1511 | adreno_write_gmureg(adreno_dev, |
| 1512 | ADRENO_REG_GMU_PWR_COL_KEEPALIVE, state); |
| 1513 | } |
| 1514 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1515 | #define SPTPRAC_POWERON_CTRL_MASK 0x00778000 |
| 1516 | #define SPTPRAC_POWEROFF_CTRL_MASK 0x00778001 |
| 1517 | #define SPTPRAC_POWEROFF_STATUS_MASK BIT(2) |
| 1518 | #define SPTPRAC_POWERON_STATUS_MASK BIT(3) |
| 1519 | #define SPTPRAC_CTRL_TIMEOUT 10 /* ms */ |
Kyle Piefer | fa50d3e | 2017-05-24 12:35:24 -0700 | [diff] [blame] | 1520 | #define A6XX_RETAIN_FF_ENABLE_ENABLE_MASK BIT(11) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1521 | |
| 1522 | /* |
| 1523 | * a6xx_sptprac_enable() - Power on SPTPRAC |
| 1524 | * @adreno_dev: Pointer to Adreno device |
| 1525 | */ |
| 1526 | static int a6xx_sptprac_enable(struct adreno_device *adreno_dev) |
| 1527 | { |
| 1528 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 1529 | struct gmu_device *gmu = &device->gmu; |
| 1530 | |
Kyle Piefer | 51dc014 | 2017-04-14 12:32:49 -0700 | [diff] [blame] | 1531 | if (!gmu->pdev) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1532 | return -EINVAL; |
| 1533 | |
| 1534 | kgsl_gmu_regwrite(device, A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, |
| 1535 | SPTPRAC_POWERON_CTRL_MASK); |
| 1536 | |
| 1537 | if (timed_poll_check(device, |
| 1538 | A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, |
| 1539 | SPTPRAC_POWERON_STATUS_MASK, |
| 1540 | SPTPRAC_CTRL_TIMEOUT, |
| 1541 | SPTPRAC_POWERON_STATUS_MASK)) { |
| 1542 | dev_err(&gmu->pdev->dev, "power on SPTPRAC fail\n"); |
| 1543 | return -EINVAL; |
| 1544 | } |
| 1545 | |
| 1546 | return 0; |
| 1547 | } |
| 1548 | |
| 1549 | /* |
| 1550 | * a6xx_sptprac_disable() - Power of SPTPRAC |
| 1551 | * @adreno_dev: Pointer to Adreno device |
| 1552 | */ |
| 1553 | static void a6xx_sptprac_disable(struct adreno_device *adreno_dev) |
| 1554 | { |
| 1555 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 1556 | struct gmu_device *gmu = &device->gmu; |
| 1557 | |
Kyle Piefer | 51dc014 | 2017-04-14 12:32:49 -0700 | [diff] [blame] | 1558 | if (!gmu->pdev) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1559 | return; |
| 1560 | |
Kyle Piefer | fa50d3e | 2017-05-24 12:35:24 -0700 | [diff] [blame] | 1561 | /* Ensure that retention is on */ |
| 1562 | kgsl_gmu_regrmw(device, A6XX_GPU_CC_GX_GDSCR, 0, |
| 1563 | A6XX_RETAIN_FF_ENABLE_ENABLE_MASK); |
| 1564 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1565 | kgsl_gmu_regwrite(device, A6XX_GMU_GX_SPTPRAC_POWER_CONTROL, |
| 1566 | SPTPRAC_POWEROFF_CTRL_MASK); |
| 1567 | |
| 1568 | if (timed_poll_check(device, |
| 1569 | A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, |
| 1570 | SPTPRAC_POWEROFF_STATUS_MASK, |
| 1571 | SPTPRAC_CTRL_TIMEOUT, |
| 1572 | SPTPRAC_POWEROFF_STATUS_MASK)) |
| 1573 | dev_err(&gmu->pdev->dev, "power off SPTPRAC fail\n"); |
| 1574 | } |
| 1575 | |
Shrenuj Bansal | d197bf6 | 2017-04-07 11:00:09 -0700 | [diff] [blame] | 1576 | #define SPTPRAC_POWER_OFF BIT(2) |
| 1577 | #define SP_CLK_OFF BIT(4) |
| 1578 | #define GX_GDSC_POWER_OFF BIT(6) |
| 1579 | #define GX_CLK_OFF BIT(7) |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 1580 | #define is_on(val) (!(val & (GX_GDSC_POWER_OFF | GX_CLK_OFF))) |
Shrenuj Bansal | d197bf6 | 2017-04-07 11:00:09 -0700 | [diff] [blame] | 1581 | /* |
| 1582 | * a6xx_gx_is_on() - Check if GX is on using pwr status register |
| 1583 | * @adreno_dev - Pointer to adreno_device |
| 1584 | * This check should only be performed if the keepalive bit is set or it |
| 1585 | * can be guaranteed that the power state of the GPU will remain unchanged |
| 1586 | */ |
| 1587 | static bool a6xx_gx_is_on(struct adreno_device *adreno_dev) |
| 1588 | { |
| 1589 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 1590 | unsigned int val; |
Shrenuj Bansal | d197bf6 | 2017-04-07 11:00:09 -0700 | [diff] [blame] | 1591 | |
| 1592 | if (!kgsl_gmu_isenabled(device)) |
| 1593 | return true; |
| 1594 | |
| 1595 | kgsl_gmu_regread(device, A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, &val); |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 1596 | return is_on(val); |
Shrenuj Bansal | d197bf6 | 2017-04-07 11:00:09 -0700 | [diff] [blame] | 1597 | } |
| 1598 | |
| 1599 | /* |
| 1600 | * a6xx_sptprac_is_on() - Check if SPTP is on using pwr status register |
| 1601 | * @adreno_dev - Pointer to adreno_device |
| 1602 | * This check should only be performed if the keepalive bit is set or it |
| 1603 | * can be guaranteed that the power state of the GPU will remain unchanged |
| 1604 | */ |
| 1605 | static bool a6xx_sptprac_is_on(struct adreno_device *adreno_dev) |
| 1606 | { |
| 1607 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 1608 | unsigned int val; |
| 1609 | |
| 1610 | if (!kgsl_gmu_isenabled(device)) |
| 1611 | return true; |
| 1612 | |
| 1613 | kgsl_gmu_regread(device, A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, &val); |
| 1614 | return !(val & (SPTPRAC_POWER_OFF | SP_CLK_OFF)); |
| 1615 | } |
| 1616 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1617 | /* |
| 1618 | * a6xx_gfx_rail_on() - request GMU to power GPU at given OPP. |
| 1619 | * @device: Pointer to KGSL device |
| 1620 | * |
| 1621 | */ |
| 1622 | static int a6xx_gfx_rail_on(struct kgsl_device *device) |
| 1623 | { |
| 1624 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 1625 | struct kgsl_pwrctrl *pwr = &device->pwrctrl; |
| 1626 | struct gmu_device *gmu = &device->gmu; |
| 1627 | struct arc_vote_desc *default_opp; |
| 1628 | unsigned int perf_idx; |
| 1629 | int ret; |
| 1630 | |
| 1631 | perf_idx = pwr->num_pwrlevels - pwr->default_pwrlevel - 1; |
| 1632 | default_opp = &gmu->rpmh_votes.gx_votes[perf_idx]; |
| 1633 | |
| 1634 | kgsl_gmu_regwrite(device, A6XX_GMU_BOOT_SLUMBER_OPTION, |
| 1635 | OOB_BOOT_OPTION); |
| 1636 | kgsl_gmu_regwrite(device, A6XX_GMU_GX_VOTE_IDX, default_opp->pri_idx); |
| 1637 | kgsl_gmu_regwrite(device, A6XX_GMU_MX_VOTE_IDX, default_opp->sec_idx); |
| 1638 | |
| 1639 | ret = a6xx_oob_set(adreno_dev, OOB_BOOT_SLUMBER_SET_MASK, |
| 1640 | OOB_BOOT_SLUMBER_CHECK_MASK, |
| 1641 | OOB_BOOT_SLUMBER_CLEAR_MASK); |
| 1642 | |
| 1643 | if (ret) |
Kyle Piefer | 247e35c | 2017-06-08 11:13:11 -0700 | [diff] [blame] | 1644 | dev_err(&gmu->pdev->dev, "Boot OOB timed out\n"); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1645 | |
| 1646 | return ret; |
| 1647 | } |
| 1648 | |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1649 | #define GMU_POWER_STATE_SLUMBER 15 |
| 1650 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1651 | /* |
| 1652 | * a6xx_notify_slumber() - initiate request to GMU to prepare to slumber |
| 1653 | * @device: Pointer to KGSL device |
| 1654 | */ |
| 1655 | static int a6xx_notify_slumber(struct kgsl_device *device) |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1656 | { |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1657 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 1658 | struct kgsl_pwrctrl *pwr = &device->pwrctrl; |
| 1659 | struct gmu_device *gmu = &device->gmu; |
| 1660 | int bus_level = pwr->pwrlevels[pwr->default_pwrlevel].bus_freq; |
| 1661 | int perf_idx = gmu->num_gpupwrlevels - pwr->default_pwrlevel - 1; |
| 1662 | int ret, state; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1663 | |
Kyle Piefer | 247e35c | 2017-06-08 11:13:11 -0700 | [diff] [blame] | 1664 | /* Disable the power counter so that the GMU is not busy */ |
| 1665 | kgsl_gmu_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0); |
| 1666 | |
Kyle Piefer | f53c187 | 2017-09-11 14:16:43 -0700 | [diff] [blame] | 1667 | /* Turn off SPTPRAC if we own it */ |
| 1668 | if (gmu->idle_level < GPU_HW_SPTP_PC) |
| 1669 | a6xx_sptprac_disable(adreno_dev); |
Kyle Piefer | 68178ef | 2017-06-19 16:46:13 -0700 | [diff] [blame] | 1670 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1671 | if (!ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) { |
| 1672 | ret = hfi_notify_slumber(gmu, perf_idx, bus_level); |
Kyle Piefer | da0fa54 | 2017-08-04 13:39:40 -0700 | [diff] [blame] | 1673 | goto out; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1674 | } |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1675 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1676 | kgsl_gmu_regwrite(device, A6XX_GMU_BOOT_SLUMBER_OPTION, |
| 1677 | OOB_SLUMBER_OPTION); |
Sharat Masetty | 928bc1d | 2017-11-13 15:46:55 +0530 | [diff] [blame] | 1678 | kgsl_gmu_regwrite(device, A6XX_GMU_GX_VOTE_IDX, perf_idx); |
| 1679 | kgsl_gmu_regwrite(device, A6XX_GMU_MX_VOTE_IDX, bus_level); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1680 | |
| 1681 | ret = a6xx_oob_set(adreno_dev, OOB_BOOT_SLUMBER_SET_MASK, |
| 1682 | OOB_BOOT_SLUMBER_CHECK_MASK, |
| 1683 | OOB_BOOT_SLUMBER_CLEAR_MASK); |
| 1684 | a6xx_oob_clear(adreno_dev, OOB_BOOT_SLUMBER_CLEAR_MASK); |
| 1685 | |
| 1686 | if (ret) |
Kyle Piefer | 247e35c | 2017-06-08 11:13:11 -0700 | [diff] [blame] | 1687 | dev_err(&gmu->pdev->dev, "Notify slumber OOB timed out\n"); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1688 | else { |
George Shen | f2d4e05 | 2017-05-11 16:28:23 -0700 | [diff] [blame] | 1689 | kgsl_gmu_regread(device, |
| 1690 | A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE, &state); |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 1691 | if (state != GPU_HW_SLUMBER) { |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1692 | dev_err(&gmu->pdev->dev, |
Kyle Piefer | c96ad95 | 2017-05-02 13:35:45 -0700 | [diff] [blame] | 1693 | "Failed to prepare for slumber: 0x%x\n", |
| 1694 | state); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1695 | ret = -EINVAL; |
| 1696 | } |
| 1697 | } |
| 1698 | |
Kyle Piefer | da0fa54 | 2017-08-04 13:39:40 -0700 | [diff] [blame] | 1699 | out: |
| 1700 | /* Make sure the fence is in ALLOW mode */ |
| 1701 | kgsl_gmu_regwrite(device, A6XX_GMU_AO_AHB_FENCE_CTRL, 0); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1702 | return ret; |
| 1703 | } |
| 1704 | |
| 1705 | static int a6xx_rpmh_power_on_gpu(struct kgsl_device *device) |
| 1706 | { |
| 1707 | struct gmu_device *gmu = &device->gmu; |
| 1708 | struct device *dev = &gmu->pdev->dev; |
George Shen | 6927d8f | 2017-07-19 11:38:10 -0700 | [diff] [blame] | 1709 | int val; |
| 1710 | |
Deepak Kumar | 0eb0a0c | 2018-04-24 14:11:53 +0530 | [diff] [blame] | 1711 | /* Only trigger wakeup sequence if sleep sequence was done earlier */ |
| 1712 | if (!test_bit(GMU_RSCC_SLEEP_SEQ_DONE, &gmu->flags)) |
| 1713 | return 0; |
| 1714 | |
George Shen | 6927d8f | 2017-07-19 11:38:10 -0700 | [diff] [blame] | 1715 | kgsl_gmu_regread(device, A6XX_GPU_CC_GX_DOMAIN_MISC, &val); |
George Shen | 683841f | 2017-10-03 18:12:02 -0700 | [diff] [blame] | 1716 | if (!(val & 0x1)) |
| 1717 | dev_err_ratelimited(&gmu->pdev->dev, |
| 1718 | "GMEM CLAMP IO not set while GFX rail off\n"); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1719 | |
George Shen | cbb18e2 | 2017-05-11 16:04:13 -0700 | [diff] [blame] | 1720 | /* RSC wake sequence */ |
| 1721 | kgsl_gmu_regwrite(device, A6XX_GMU_RSCC_CONTROL_REQ, BIT(1)); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1722 | |
George Shen | cbb18e2 | 2017-05-11 16:04:13 -0700 | [diff] [blame] | 1723 | /* Write request before polling */ |
| 1724 | wmb(); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1725 | |
George Shen | cbb18e2 | 2017-05-11 16:04:13 -0700 | [diff] [blame] | 1726 | if (timed_poll_check(device, |
| 1727 | A6XX_GMU_RSCC_CONTROL_ACK, |
| 1728 | BIT(1), |
| 1729 | GPU_START_TIMEOUT, |
| 1730 | BIT(1))) { |
| 1731 | dev_err(dev, "Failed to do GPU RSC power on\n"); |
| 1732 | return -EINVAL; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1733 | } |
| 1734 | |
George Shen | cbb18e2 | 2017-05-11 16:04:13 -0700 | [diff] [blame] | 1735 | if (timed_poll_check(device, |
| 1736 | A6XX_RSCC_SEQ_BUSY_DRV0, |
| 1737 | 0, |
| 1738 | GPU_START_TIMEOUT, |
| 1739 | 0xFFFFFFFF)) |
| 1740 | goto error_rsc; |
| 1741 | |
| 1742 | kgsl_gmu_regwrite(device, A6XX_GMU_RSCC_CONTROL_REQ, 0); |
| 1743 | |
Deepak Kumar | 0eb0a0c | 2018-04-24 14:11:53 +0530 | [diff] [blame] | 1744 | /* Clear sleep sequence flag as wakeup sequence is successful */ |
| 1745 | clear_bit(GMU_RSCC_SLEEP_SEQ_DONE, &gmu->flags); |
| 1746 | |
Kyle Piefer | 247e35c | 2017-06-08 11:13:11 -0700 | [diff] [blame] | 1747 | /* Enable the power counter because it was disabled before slumber */ |
| 1748 | kgsl_gmu_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 1); |
| 1749 | |
Kyle Piefer | 68178ef | 2017-06-19 16:46:13 -0700 | [diff] [blame] | 1750 | return 0; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1751 | error_rsc: |
| 1752 | dev_err(dev, "GPU RSC sequence stuck in waking up GPU\n"); |
Kyle Piefer | 68178ef | 2017-06-19 16:46:13 -0700 | [diff] [blame] | 1753 | return -EINVAL; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1754 | } |
| 1755 | |
| 1756 | static int a6xx_rpmh_power_off_gpu(struct kgsl_device *device) |
| 1757 | { |
| 1758 | struct gmu_device *gmu = &device->gmu; |
Kyle Piefer | 3e1f6bc | 2017-08-10 11:16:19 -0700 | [diff] [blame] | 1759 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 1760 | int ret; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1761 | |
Deepak Kumar | 0eb0a0c | 2018-04-24 14:11:53 +0530 | [diff] [blame] | 1762 | if (test_bit(GMU_RSCC_SLEEP_SEQ_DONE, &gmu->flags)) |
| 1763 | return 0; |
| 1764 | |
Kyle Piefer | 3e1f6bc | 2017-08-10 11:16:19 -0700 | [diff] [blame] | 1765 | /* RSC sleep sequence is different on v1 */ |
| 1766 | if (adreno_is_a630v1(adreno_dev)) |
| 1767 | kgsl_gmu_regwrite(device, A6XX_RSCC_TIMESTAMP_UNIT1_EN_DRV0, 1); |
| 1768 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1769 | kgsl_gmu_regwrite(device, A6XX_GMU_RSCC_CONTROL_REQ, 1); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 1770 | wmb(); |
| 1771 | |
Kyle Piefer | 3e1f6bc | 2017-08-10 11:16:19 -0700 | [diff] [blame] | 1772 | if (adreno_is_a630v1(adreno_dev)) |
| 1773 | ret = timed_poll_check(device, |
| 1774 | A6XX_RSCC_TIMESTAMP_UNIT1_OUTPUT_DRV0, |
| 1775 | BIT(0), |
| 1776 | GPU_START_TIMEOUT, |
| 1777 | BIT(0)); |
| 1778 | else |
| 1779 | ret = timed_poll_check(device, |
| 1780 | A6XX_GPU_RSCC_RSC_STATUS0_DRV0, |
| 1781 | BIT(16), |
| 1782 | GPU_START_TIMEOUT, |
| 1783 | BIT(16)); |
| 1784 | |
| 1785 | if (ret) { |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1786 | dev_err(&gmu->pdev->dev, "GPU RSC power off fail\n"); |
Kyle Piefer | 3e1f6bc | 2017-08-10 11:16:19 -0700 | [diff] [blame] | 1787 | return -ETIMEDOUT; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1788 | } |
| 1789 | |
Kyle Piefer | 3e1f6bc | 2017-08-10 11:16:19 -0700 | [diff] [blame] | 1790 | /* Read to clear the timestamp valid signal. Don't care what we read. */ |
| 1791 | if (adreno_is_a630v1(adreno_dev)) { |
| 1792 | kgsl_gmu_regread(device, |
| 1793 | A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_L_DRV0, |
| 1794 | &ret); |
| 1795 | kgsl_gmu_regread(device, |
| 1796 | A6XX_RSCC_TIMESTAMP_UNIT0_TIMESTAMP_H_DRV0, |
| 1797 | &ret); |
| 1798 | } |
| 1799 | |
Kyle Piefer | 9e0ac3c | 2017-05-01 16:34:14 -0700 | [diff] [blame] | 1800 | kgsl_gmu_regwrite(device, A6XX_GMU_RSCC_CONTROL_REQ, 0); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1801 | |
Oleg Perelet | c2ab7f7 | 2017-06-22 16:45:57 -0700 | [diff] [blame] | 1802 | if (ADRENO_FEATURE(adreno_dev, ADRENO_LM) && |
Kyle Piefer | 3e1f6bc | 2017-08-10 11:16:19 -0700 | [diff] [blame] | 1803 | test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) |
Oleg Perelet | c2ab7f7 | 2017-06-22 16:45:57 -0700 | [diff] [blame] | 1804 | kgsl_gmu_regwrite(device, A6XX_GMU_AO_SPARE_CNTL, 0); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1805 | |
Deepak Kumar | 0eb0a0c | 2018-04-24 14:11:53 +0530 | [diff] [blame] | 1806 | set_bit(GMU_RSCC_SLEEP_SEQ_DONE, &gmu->flags); |
Kyle Piefer | 68178ef | 2017-06-19 16:46:13 -0700 | [diff] [blame] | 1807 | return 0; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1808 | } |
| 1809 | |
| 1810 | /* |
| 1811 | * a6xx_gmu_fw_start() - set up GMU and start FW |
| 1812 | * @device: Pointer to KGSL device |
| 1813 | * @boot_state: State of the GMU being started |
| 1814 | */ |
| 1815 | static int a6xx_gmu_fw_start(struct kgsl_device *device, |
| 1816 | unsigned int boot_state) |
| 1817 | { |
| 1818 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 1819 | struct gmu_device *gmu = &device->gmu; |
| 1820 | struct gmu_memdesc *mem_addr = gmu->hfi_mem; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1821 | int ret, i; |
George Shen | f453d42 | 2017-08-19 21:12:11 -0700 | [diff] [blame] | 1822 | unsigned int chipid = 0; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1823 | |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1824 | switch (boot_state) { |
| 1825 | case GMU_COLD_BOOT: |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1826 | /* Turn on TCM retention */ |
| 1827 | kgsl_gmu_regwrite(device, A6XX_GMU_GENERAL_7, 1); |
| 1828 | |
Kyle Piefer | 68178ef | 2017-06-19 16:46:13 -0700 | [diff] [blame] | 1829 | if (!test_and_set_bit(GMU_BOOT_INIT_DONE, &gmu->flags)) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1830 | _load_gmu_rpmh_ucode(device); |
Deepak Kumar | 0eb0a0c | 2018-04-24 14:11:53 +0530 | [diff] [blame] | 1831 | else { |
George Shen | cbb18e2 | 2017-05-11 16:04:13 -0700 | [diff] [blame] | 1832 | ret = a6xx_rpmh_power_on_gpu(device); |
| 1833 | if (ret) |
| 1834 | return ret; |
| 1835 | } |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1836 | |
| 1837 | if (gmu->load_mode == TCM_BOOT) { |
| 1838 | /* Load GMU image via AHB bus */ |
| 1839 | for (i = 0; i < MAX_GMUFW_SIZE; i++) |
| 1840 | kgsl_gmu_regwrite(device, |
| 1841 | A6XX_GMU_CM3_ITCM_START + i, |
| 1842 | *((uint32_t *) gmu->fw_image. |
| 1843 | hostptr + i)); |
| 1844 | |
| 1845 | /* Prevent leaving reset before the FW is written */ |
| 1846 | wmb(); |
| 1847 | } else { |
| 1848 | dev_err(&gmu->pdev->dev, "Incorrect GMU load mode %d\n", |
| 1849 | gmu->load_mode); |
| 1850 | return -EINVAL; |
| 1851 | } |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1852 | break; |
| 1853 | case GMU_WARM_BOOT: |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1854 | ret = a6xx_rpmh_power_on_gpu(device); |
| 1855 | if (ret) |
| 1856 | return ret; |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1857 | break; |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1858 | default: |
| 1859 | break; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1860 | } |
| 1861 | |
| 1862 | /* Clear init result to make sure we are getting fresh value */ |
| 1863 | kgsl_gmu_regwrite(device, A6XX_GMU_CM3_FW_INIT_RESULT, 0); |
| 1864 | kgsl_gmu_regwrite(device, A6XX_GMU_CM3_BOOT_CONFIG, gmu->load_mode); |
| 1865 | |
| 1866 | kgsl_gmu_regwrite(device, A6XX_GMU_HFI_QTBL_ADDR, |
| 1867 | mem_addr->gmuaddr); |
| 1868 | kgsl_gmu_regwrite(device, A6XX_GMU_HFI_QTBL_INFO, 1); |
| 1869 | |
| 1870 | kgsl_gmu_regwrite(device, A6XX_GMU_AHB_FENCE_RANGE_0, |
| 1871 | FENCE_RANGE_MASK); |
| 1872 | |
George Shen | f453d42 | 2017-08-19 21:12:11 -0700 | [diff] [blame] | 1873 | /* Pass chipid to GMU FW, must happen before starting GMU */ |
| 1874 | |
| 1875 | /* Keep Core and Major bitfields unchanged */ |
| 1876 | chipid = adreno_dev->chipid & 0xFFFF0000; |
| 1877 | |
| 1878 | /* |
| 1879 | * Compress minor and patch version into 8 bits |
| 1880 | * Bit 15-12: minor version |
| 1881 | * Bit 11-8: patch version |
| 1882 | */ |
| 1883 | chipid = chipid | (ADRENO_CHIPID_MINOR(adreno_dev->chipid) << 12) |
| 1884 | | (ADRENO_CHIPID_PATCH(adreno_dev->chipid) << 8); |
| 1885 | |
| 1886 | kgsl_gmu_regwrite(device, A6XX_GMU_HFI_SFR_ADDR, chipid); |
| 1887 | |
Kyle Piefer | d396416 | 2017-04-06 15:44:03 -0700 | [diff] [blame] | 1888 | /* Configure power control and bring the GMU out of reset */ |
| 1889 | a6xx_gmu_power_config(device); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1890 | ret = a6xx_gmu_start(device); |
| 1891 | if (ret) |
| 1892 | return ret; |
| 1893 | |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1894 | if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) { |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1895 | ret = a6xx_gfx_rail_on(device); |
| 1896 | if (ret) { |
| 1897 | a6xx_oob_clear(adreno_dev, |
| 1898 | OOB_BOOT_SLUMBER_CLEAR_MASK); |
| 1899 | return ret; |
| 1900 | } |
| 1901 | } |
| 1902 | |
Kyle Piefer | 68178ef | 2017-06-19 16:46:13 -0700 | [diff] [blame] | 1903 | if (gmu->idle_level < GPU_HW_SPTP_PC) { |
| 1904 | ret = a6xx_sptprac_enable(adreno_dev); |
| 1905 | if (ret) |
| 1906 | return ret; |
| 1907 | } |
| 1908 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1909 | ret = a6xx_gmu_hfi_start(device); |
| 1910 | if (ret) |
| 1911 | return ret; |
| 1912 | |
| 1913 | /* Make sure the write to start HFI happens before sending a message */ |
| 1914 | wmb(); |
| 1915 | return ret; |
| 1916 | } |
| 1917 | |
| 1918 | /* |
| 1919 | * a6xx_gmu_dcvs_nohfi() - request GMU to do DCVS without using HFI |
| 1920 | * @device: Pointer to KGSL device |
| 1921 | * @perf_idx: Index into GPU performance level table defined in |
| 1922 | * HFI DCVS table message |
| 1923 | * @bw_idx: Index into GPU b/w table defined in HFI b/w table message |
| 1924 | * |
| 1925 | */ |
| 1926 | static int a6xx_gmu_dcvs_nohfi(struct kgsl_device *device, |
| 1927 | unsigned int perf_idx, unsigned int bw_idx) |
| 1928 | { |
| 1929 | struct hfi_dcvs_cmd dcvs_cmd = { |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 1930 | .ack_type = ACK_NONBLOCK, |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1931 | .freq = { |
| 1932 | .perf_idx = perf_idx, |
| 1933 | .clkset_opt = OPTION_AT_LEAST, |
| 1934 | }, |
| 1935 | .bw = { |
| 1936 | .bw_idx = bw_idx, |
| 1937 | }, |
| 1938 | }; |
| 1939 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 1940 | struct gmu_device *gmu = &device->gmu; |
| 1941 | union gpu_perf_vote vote; |
| 1942 | int ret; |
| 1943 | |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1944 | kgsl_gmu_regwrite(device, A6XX_GMU_DCVS_ACK_OPTION, dcvs_cmd.ack_type); |
| 1945 | |
| 1946 | vote.fvote = dcvs_cmd.freq; |
| 1947 | kgsl_gmu_regwrite(device, A6XX_GMU_DCVS_PERF_SETTING, vote.raw); |
| 1948 | |
| 1949 | vote.bvote = dcvs_cmd.bw; |
| 1950 | kgsl_gmu_regwrite(device, A6XX_GMU_DCVS_BW_SETTING, vote.raw); |
| 1951 | |
| 1952 | ret = a6xx_oob_set(adreno_dev, OOB_DCVS_SET_MASK, OOB_DCVS_CHECK_MASK, |
| 1953 | OOB_DCVS_CLEAR_MASK); |
| 1954 | |
| 1955 | if (ret) { |
Kyle Piefer | 247e35c | 2017-06-08 11:13:11 -0700 | [diff] [blame] | 1956 | dev_err(&gmu->pdev->dev, "DCVS OOB timed out\n"); |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 1957 | goto done; |
| 1958 | } |
| 1959 | |
| 1960 | kgsl_gmu_regread(device, A6XX_GMU_DCVS_RETURN, &ret); |
| 1961 | if (ret) |
| 1962 | dev_err(&gmu->pdev->dev, "OOB DCVS error %d\n", ret); |
| 1963 | |
| 1964 | done: |
| 1965 | a6xx_oob_clear(adreno_dev, OOB_DCVS_CLEAR_MASK); |
| 1966 | |
| 1967 | return ret; |
| 1968 | } |
| 1969 | |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 1970 | static bool a6xx_hw_isidle(struct adreno_device *adreno_dev) |
| 1971 | { |
| 1972 | unsigned int reg; |
| 1973 | |
| 1974 | kgsl_gmu_regread(KGSL_DEVICE(adreno_dev), |
| 1975 | A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, ®); |
George Shen | cbb18e2 | 2017-05-11 16:04:13 -0700 | [diff] [blame] | 1976 | if (reg & GPUBUSYIGNAHB) |
| 1977 | return false; |
| 1978 | return true; |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 1979 | } |
| 1980 | |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 1981 | static bool idle_trandition_complete(unsigned int idle_level, |
| 1982 | unsigned int gmu_power_reg, |
| 1983 | unsigned int sptprac_clk_reg) |
| 1984 | { |
| 1985 | if (idle_level != gmu_power_reg) |
| 1986 | return false; |
| 1987 | |
| 1988 | switch (idle_level) { |
| 1989 | case GPU_HW_IFPC: |
| 1990 | if (is_on(sptprac_clk_reg)) |
| 1991 | return false; |
| 1992 | break; |
| 1993 | /* other GMU idle levels can be added here */ |
| 1994 | case GPU_HW_ACTIVE: |
| 1995 | default: |
| 1996 | break; |
| 1997 | } |
| 1998 | return true; |
| 1999 | } |
| 2000 | |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 2001 | static int a6xx_wait_for_lowest_idle(struct adreno_device *adreno_dev) |
| 2002 | { |
| 2003 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 2004 | struct gmu_device *gmu = &device->gmu; |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 2005 | unsigned int reg, reg1; |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 2006 | unsigned long t; |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 2007 | uint64_t ts1, ts2, ts3; |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 2008 | |
| 2009 | if (!kgsl_gmu_isenabled(device)) |
| 2010 | return 0; |
| 2011 | |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 2012 | ts1 = read_AO_counter(device); |
| 2013 | |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 2014 | t = jiffies + msecs_to_jiffies(GMU_IDLE_TIMEOUT); |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 2015 | do { |
| 2016 | kgsl_gmu_regread(device, |
| 2017 | A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE, ®); |
| 2018 | kgsl_gmu_regread(device, |
| 2019 | A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, ®1); |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 2020 | |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 2021 | if (idle_trandition_complete(gmu->idle_level, reg, reg1)) |
| 2022 | return 0; |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 2023 | /* Wait 100us to reduce unnecessary AHB bus traffic */ |
Oleg Perelet | 7f7f9f5 | 2017-10-31 10:02:45 -0700 | [diff] [blame] | 2024 | usleep_range(10, 100); |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 2025 | } while (!time_after(jiffies, t)); |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 2026 | |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 2027 | ts2 = read_AO_counter(device); |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 2028 | /* Check one last time */ |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 2029 | |
Oleg Perelet | 39fead2 | 2018-01-08 14:46:17 -0800 | [diff] [blame] | 2030 | kgsl_gmu_regread(device, A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE, ®); |
| 2031 | kgsl_gmu_regread(device, A6XX_GMU_SPTPRAC_PWR_CLK_STATUS, ®1); |
| 2032 | |
| 2033 | if (idle_trandition_complete(gmu->idle_level, reg, reg1)) |
| 2034 | return 0; |
| 2035 | |
| 2036 | ts3 = read_AO_counter(device); |
| 2037 | WARN(1, "Timeout waiting for lowest idle: %08x %llx %llx %llx %x\n", |
| 2038 | reg, ts1, ts2, ts3, reg1); |
| 2039 | |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 2040 | return -ETIMEDOUT; |
| 2041 | } |
| 2042 | |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 2043 | static int a6xx_wait_for_gmu_idle(struct adreno_device *adreno_dev) |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 2044 | { |
| 2045 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 2046 | struct gmu_device *gmu = &device->gmu; |
Oleg Perelet | 5df700d | 2018-01-26 09:21:47 -0800 | [diff] [blame] | 2047 | unsigned int status2; |
| 2048 | uint64_t ts1; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 2049 | |
Oleg Perelet | 5df700d | 2018-01-26 09:21:47 -0800 | [diff] [blame] | 2050 | ts1 = read_AO_counter(device); |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 2051 | if (timed_poll_check(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS, |
Kyle Piefer | 5c9478c | 2017-04-20 15:12:05 -0700 | [diff] [blame] | 2052 | 0, GMU_START_TIMEOUT, CXGXCPUBUSYIGNAHB)) { |
Kyle Piefer | 247e35c | 2017-06-08 11:13:11 -0700 | [diff] [blame] | 2053 | kgsl_gmu_regread(device, |
Kyle Piefer | 247e35c | 2017-06-08 11:13:11 -0700 | [diff] [blame] | 2054 | A6XX_GPU_GMU_AO_GPU_CX_BUSY_STATUS2, &status2); |
| 2055 | dev_err(&gmu->pdev->dev, |
Oleg Perelet | 5df700d | 2018-01-26 09:21:47 -0800 | [diff] [blame] | 2056 | "GMU not idling: status2=0x%x %llx %llx\n", |
| 2057 | status2, ts1, read_AO_counter(device)); |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 2058 | return -ETIMEDOUT; |
| 2059 | } |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 2060 | |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 2061 | return 0; |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 2062 | } |
| 2063 | |
| 2064 | /* |
| 2065 | * _load_gmu_firmware() - Load the ucode into the GPMU RAM & PDC/RSC |
| 2066 | * @device: Pointer to KGSL device |
| 2067 | */ |
| 2068 | static int _load_gmu_firmware(struct kgsl_device *device) |
| 2069 | { |
| 2070 | const struct firmware *fw = NULL; |
| 2071 | const struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 2072 | struct gmu_device *gmu = &device->gmu; |
| 2073 | const struct adreno_gpu_core *gpucore = adreno_dev->gpucore; |
| 2074 | int image_size, ret = -EINVAL; |
| 2075 | |
| 2076 | /* there is no GMU */ |
| 2077 | if (!kgsl_gmu_isenabled(device)) |
| 2078 | return 0; |
| 2079 | |
| 2080 | /* GMU fw already saved and verified so do nothing new */ |
| 2081 | if (gmu->fw_image.hostptr != 0) |
| 2082 | return 0; |
| 2083 | |
| 2084 | if (gpucore->gpmufw_name == NULL) |
| 2085 | return -EINVAL; |
| 2086 | |
| 2087 | ret = request_firmware(&fw, gpucore->gpmufw_name, device->dev); |
| 2088 | if (ret || fw == NULL) { |
| 2089 | KGSL_CORE_ERR("request_firmware (%s) failed: %d\n", |
| 2090 | gpucore->gpmufw_name, ret); |
| 2091 | return ret; |
| 2092 | } |
| 2093 | |
| 2094 | image_size = PAGE_ALIGN(fw->size); |
| 2095 | |
| 2096 | ret = allocate_gmu_image(gmu, image_size); |
| 2097 | |
| 2098 | /* load into shared memory with GMU */ |
| 2099 | if (!ret) |
| 2100 | memcpy(gmu->fw_image.hostptr, fw->data, fw->size); |
| 2101 | |
| 2102 | release_firmware(fw); |
| 2103 | |
| 2104 | return ret; |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2105 | } |
| 2106 | |
| 2107 | /* |
| 2108 | * a6xx_microcode_read() - Read microcode |
| 2109 | * @adreno_dev: Pointer to adreno device |
| 2110 | */ |
| 2111 | static int a6xx_microcode_read(struct adreno_device *adreno_dev) |
| 2112 | { |
Lynus Vaz | 573e501 | 2017-06-20 20:37:50 +0530 | [diff] [blame] | 2113 | int ret; |
| 2114 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 2115 | struct adreno_firmware *sqe_fw = ADRENO_FW(adreno_dev, ADRENO_FW_SQE); |
| 2116 | |
| 2117 | if (sqe_fw->memdesc.hostptr == NULL) { |
| 2118 | ret = _load_firmware(device, adreno_dev->gpucore->sqefw_name, |
| 2119 | sqe_fw); |
| 2120 | if (ret) |
| 2121 | return ret; |
| 2122 | } |
| 2123 | |
| 2124 | return _load_gmu_firmware(device); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2125 | } |
| 2126 | |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 2127 | #define GBIF_CX_HALT_MASK BIT(1) |
Shrenuj Bansal | 49d0e9f | 2017-05-08 16:10:24 -0700 | [diff] [blame] | 2128 | |
| 2129 | static int a6xx_soft_reset(struct adreno_device *adreno_dev) |
| 2130 | { |
| 2131 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 2132 | unsigned int reg; |
Shrenuj Bansal | 13cae37 | 2017-06-07 13:34:35 -0700 | [diff] [blame] | 2133 | unsigned long time; |
| 2134 | bool vbif_acked = false; |
Shrenuj Bansal | 49d0e9f | 2017-05-08 16:10:24 -0700 | [diff] [blame] | 2135 | |
| 2136 | /* |
| 2137 | * For the soft reset case with GMU enabled this part is done |
| 2138 | * by the GMU firmware |
| 2139 | */ |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 2140 | if (kgsl_gmu_isenabled(device) && |
| 2141 | !test_bit(ADRENO_DEVICE_HARD_RESET, &adreno_dev->priv)) |
Shrenuj Bansal | 49d0e9f | 2017-05-08 16:10:24 -0700 | [diff] [blame] | 2142 | return 0; |
| 2143 | |
| 2144 | |
| 2145 | adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 1); |
| 2146 | /* |
| 2147 | * Do a dummy read to get a brief read cycle delay for the |
| 2148 | * reset to take effect |
| 2149 | */ |
| 2150 | adreno_readreg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, ®); |
| 2151 | adreno_writereg(adreno_dev, ADRENO_REG_RBBM_SW_RESET_CMD, 0); |
| 2152 | |
Shrenuj Bansal | 13cae37 | 2017-06-07 13:34:35 -0700 | [diff] [blame] | 2153 | /* Wait for the VBIF reset ack to complete */ |
| 2154 | time = jiffies + msecs_to_jiffies(VBIF_RESET_ACK_TIMEOUT); |
| 2155 | |
| 2156 | do { |
| 2157 | kgsl_regread(device, A6XX_RBBM_VBIF_GX_RESET_STATUS, ®); |
| 2158 | if ((reg & VBIF_RESET_ACK_MASK) == VBIF_RESET_ACK_MASK) { |
| 2159 | vbif_acked = true; |
| 2160 | break; |
| 2161 | } |
| 2162 | cpu_relax(); |
| 2163 | } while (!time_after(jiffies, time)); |
| 2164 | |
| 2165 | if (!vbif_acked) |
Shrenuj Bansal | 49d0e9f | 2017-05-08 16:10:24 -0700 | [diff] [blame] | 2166 | return -ETIMEDOUT; |
| 2167 | |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 2168 | /* |
| 2169 | * GBIF GX halt will be released automatically by sw_reset. |
| 2170 | * Release GBIF CX halt after sw_reset |
| 2171 | */ |
| 2172 | if (adreno_has_gbif(adreno_dev)) |
| 2173 | kgsl_regrmw(device, A6XX_GBIF_HALT, GBIF_CX_HALT_MASK, 0); |
| 2174 | |
Shrenuj Bansal | 49d0e9f | 2017-05-08 16:10:24 -0700 | [diff] [blame] | 2175 | a6xx_sptprac_enable(adreno_dev); |
| 2176 | |
| 2177 | return 0; |
| 2178 | } |
| 2179 | |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 2180 | #define A6XX_STATE_OF_CHILD (BIT(4) | BIT(5)) |
| 2181 | #define A6XX_IDLE_FULL_LLM BIT(0) |
| 2182 | #define A6XX_WAKEUP_ACK BIT(1) |
| 2183 | #define A6XX_IDLE_FULL_ACK BIT(0) |
| 2184 | #define A6XX_VBIF_XIN_HALT_CTRL1_ACKS (BIT(0) | BIT(1) | BIT(2) | BIT(3)) |
| 2185 | |
| 2186 | static void a6xx_isense_disable(struct kgsl_device *device) |
| 2187 | { |
| 2188 | unsigned int val; |
| 2189 | const struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 2190 | |
Oleg Perelet | c2ab7f7 | 2017-06-22 16:45:57 -0700 | [diff] [blame] | 2191 | if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM) || |
| 2192 | !test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 2193 | return; |
| 2194 | |
| 2195 | kgsl_gmu_regread(device, A6XX_GPU_CS_ENABLE_REG, &val); |
| 2196 | if (val) { |
| 2197 | kgsl_gmu_regwrite(device, A6XX_GPU_CS_ENABLE_REG, 0); |
| 2198 | kgsl_gmu_regwrite(device, A6XX_GMU_ISENSE_CTRL, 0); |
| 2199 | } |
| 2200 | } |
| 2201 | |
| 2202 | static int a6xx_llm_glm_handshake(struct kgsl_device *device) |
| 2203 | { |
| 2204 | unsigned int val; |
| 2205 | const struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 2206 | struct gmu_device *gmu = &device->gmu; |
| 2207 | |
Oleg Perelet | c2ab7f7 | 2017-06-22 16:45:57 -0700 | [diff] [blame] | 2208 | if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM) || |
| 2209 | !test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 2210 | return 0; |
| 2211 | |
| 2212 | kgsl_gmu_regread(device, A6XX_GMU_LLM_GLM_SLEEP_CTRL, &val); |
| 2213 | if (!(val & A6XX_STATE_OF_CHILD)) { |
| 2214 | kgsl_gmu_regrmw(device, A6XX_GMU_LLM_GLM_SLEEP_CTRL, 0, BIT(4)); |
| 2215 | kgsl_gmu_regrmw(device, A6XX_GMU_LLM_GLM_SLEEP_CTRL, 0, |
| 2216 | A6XX_IDLE_FULL_LLM); |
| 2217 | if (timed_poll_check(device, A6XX_GMU_LLM_GLM_SLEEP_STATUS, |
| 2218 | A6XX_IDLE_FULL_ACK, GPU_RESET_TIMEOUT, |
| 2219 | A6XX_IDLE_FULL_ACK)) { |
| 2220 | dev_err(&gmu->pdev->dev, "LLM-GLM handshake failed\n"); |
| 2221 | return -EINVAL; |
| 2222 | } |
| 2223 | } |
| 2224 | |
| 2225 | return 0; |
| 2226 | } |
| 2227 | |
Oleg Perelet | c2ab7f7 | 2017-06-22 16:45:57 -0700 | [diff] [blame] | 2228 | |
| 2229 | static void a6xx_count_throttles(struct adreno_device *adreno_dev, |
| 2230 | uint64_t adj) |
| 2231 | { |
| 2232 | if (!ADRENO_FEATURE(adreno_dev, ADRENO_LM) || |
| 2233 | !test_bit(ADRENO_LM_CTRL, &adreno_dev->pwrctrl_flag)) |
| 2234 | return; |
| 2235 | |
| 2236 | kgsl_gmu_regread(KGSL_DEVICE(adreno_dev), |
| 2237 | adreno_dev->lm_threshold_count, |
| 2238 | &adreno_dev->lm_threshold_cross); |
| 2239 | } |
| 2240 | |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 2241 | static int a6xx_complete_rpmh_votes(struct kgsl_device *device) |
| 2242 | { |
| 2243 | int ret = 0; |
| 2244 | |
| 2245 | if (!kgsl_gmu_isenabled(device)) |
| 2246 | return ret; |
| 2247 | |
| 2248 | ret |= timed_poll_check(device, A6XX_RSCC_TCS0_DRV0_STATUS, BIT(0), |
| 2249 | GPU_RESET_TIMEOUT, BIT(0)); |
| 2250 | ret |= timed_poll_check(device, A6XX_RSCC_TCS1_DRV0_STATUS, BIT(0), |
| 2251 | GPU_RESET_TIMEOUT, BIT(0)); |
| 2252 | ret |= timed_poll_check(device, A6XX_RSCC_TCS2_DRV0_STATUS, BIT(0), |
| 2253 | GPU_RESET_TIMEOUT, BIT(0)); |
| 2254 | ret |= timed_poll_check(device, A6XX_RSCC_TCS3_DRV0_STATUS, BIT(0), |
| 2255 | GPU_RESET_TIMEOUT, BIT(0)); |
| 2256 | |
| 2257 | return ret; |
| 2258 | } |
| 2259 | |
| 2260 | static int a6xx_gmu_suspend(struct kgsl_device *device) |
| 2261 | { |
| 2262 | /* Max GX clients on A6xx is 2: GMU and KMD */ |
| 2263 | int ret = 0, max_client_num = 2; |
| 2264 | struct gmu_device *gmu = &device->gmu; |
| 2265 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 2266 | |
| 2267 | /* do it only if LM feature is enabled */ |
| 2268 | /* Disable ISENSE if it's on */ |
| 2269 | a6xx_isense_disable(device); |
| 2270 | |
| 2271 | /* LLM-GLM handshake sequence */ |
| 2272 | a6xx_llm_glm_handshake(device); |
| 2273 | |
| 2274 | /* If SPTP_RAC is on, turn off SPTP_RAC HS */ |
| 2275 | a6xx_sptprac_disable(adreno_dev); |
| 2276 | |
George Shen | f135a97 | 2017-08-24 16:59:42 -0700 | [diff] [blame] | 2277 | /* Disconnect GPU from BUS is not needed if CX GDSC goes off later */ |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 2278 | |
| 2279 | /* Check no outstanding RPMh voting */ |
| 2280 | a6xx_complete_rpmh_votes(device); |
| 2281 | |
Kyle Piefer | 68178ef | 2017-06-19 16:46:13 -0700 | [diff] [blame] | 2282 | if (gmu->gx_gdsc) { |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 2283 | if (regulator_is_enabled(gmu->gx_gdsc)) { |
| 2284 | /* Switch gx gdsc control from GMU to CPU |
| 2285 | * force non-zero reference count in clk driver |
| 2286 | * so next disable call will turn |
| 2287 | * off the GDSC |
| 2288 | */ |
| 2289 | ret = regulator_enable(gmu->gx_gdsc); |
| 2290 | if (ret) |
| 2291 | dev_err(&gmu->pdev->dev, |
| 2292 | "suspend fail: gx enable\n"); |
| 2293 | |
| 2294 | while ((max_client_num)) { |
| 2295 | ret = regulator_disable(gmu->gx_gdsc); |
| 2296 | if (!regulator_is_enabled(gmu->gx_gdsc)) |
| 2297 | break; |
| 2298 | max_client_num -= 1; |
| 2299 | } |
| 2300 | |
| 2301 | if (!max_client_num) |
| 2302 | dev_err(&gmu->pdev->dev, |
| 2303 | "suspend fail: cannot disable gx\n"); |
| 2304 | } |
| 2305 | } |
| 2306 | |
| 2307 | return ret; |
| 2308 | } |
| 2309 | |
| 2310 | /* |
| 2311 | * a6xx_rpmh_gpu_pwrctrl() - GPU power control via RPMh/GMU interface |
| 2312 | * @adreno_dev: Pointer to adreno device |
| 2313 | * @mode: requested power mode |
| 2314 | * @arg1: first argument for mode control |
| 2315 | * @arg2: second argument for mode control |
| 2316 | */ |
| 2317 | static int a6xx_rpmh_gpu_pwrctrl(struct adreno_device *adreno_dev, |
| 2318 | unsigned int mode, unsigned int arg1, unsigned int arg2) |
| 2319 | { |
| 2320 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 2321 | struct gmu_device *gmu = &device->gmu; |
| 2322 | int ret; |
| 2323 | |
| 2324 | switch (mode) { |
| 2325 | case GMU_FW_START: |
| 2326 | ret = a6xx_gmu_fw_start(device, arg1); |
| 2327 | break; |
| 2328 | case GMU_SUSPEND: |
| 2329 | ret = a6xx_gmu_suspend(device); |
| 2330 | break; |
| 2331 | case GMU_FW_STOP: |
George Shen | a458dd9 | 2018-01-03 14:20:34 -0800 | [diff] [blame] | 2332 | if (ADRENO_QUIRK(adreno_dev, ADRENO_QUIRK_HFI_USE_REG)) |
| 2333 | a6xx_oob_clear(adreno_dev, |
| 2334 | OOB_BOOT_SLUMBER_CLEAR_MASK); |
Kyle Piefer | e923b7a | 2017-03-28 17:31:48 -0700 | [diff] [blame] | 2335 | ret = a6xx_rpmh_power_off_gpu(device); |
| 2336 | break; |
| 2337 | case GMU_DCVS_NOHFI: |
| 2338 | ret = a6xx_gmu_dcvs_nohfi(device, arg1, arg2); |
| 2339 | break; |
| 2340 | case GMU_NOTIFY_SLUMBER: |
| 2341 | ret = a6xx_notify_slumber(device); |
| 2342 | break; |
| 2343 | default: |
| 2344 | dev_err(&gmu->pdev->dev, |
| 2345 | "unsupported GMU power ctrl mode:%d\n", mode); |
| 2346 | ret = -EINVAL; |
| 2347 | break; |
| 2348 | } |
| 2349 | |
| 2350 | return ret; |
| 2351 | } |
| 2352 | |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 2353 | /** |
| 2354 | * a6xx_reset() - Helper function to reset the GPU |
| 2355 | * @device: Pointer to the KGSL device structure for the GPU |
| 2356 | * @fault: Type of fault. Needed to skip soft reset for MMU fault |
| 2357 | * |
| 2358 | * Try to reset the GPU to recover from a fault. First, try to do a low latency |
| 2359 | * soft reset. If the soft reset fails for some reason, then bring out the big |
| 2360 | * guns and toggle the footswitch. |
| 2361 | */ |
| 2362 | static int a6xx_reset(struct kgsl_device *device, int fault) |
| 2363 | { |
| 2364 | struct adreno_device *adreno_dev = ADRENO_DEVICE(device); |
| 2365 | int ret = -EINVAL; |
| 2366 | int i = 0; |
| 2367 | |
| 2368 | /* Use the regular reset sequence for No GMU */ |
| 2369 | if (!kgsl_gmu_isenabled(device)) |
| 2370 | return adreno_reset(device, fault); |
| 2371 | |
| 2372 | /* Transition from ACTIVE to RESET state */ |
| 2373 | kgsl_pwrctrl_change_state(device, KGSL_STATE_RESET); |
| 2374 | |
| 2375 | /* Try soft reset first */ |
| 2376 | if (!(fault & ADRENO_IOMMU_PAGE_FAULT)) { |
| 2377 | int acked; |
| 2378 | |
| 2379 | /* NMI */ |
| 2380 | kgsl_gmu_regwrite(device, A6XX_GMU_NMI_CONTROL_STATUS, 0); |
| 2381 | kgsl_gmu_regwrite(device, A6XX_GMU_CM3_CFG, (1 << 9)); |
| 2382 | |
| 2383 | for (i = 0; i < 10; i++) { |
| 2384 | kgsl_gmu_regread(device, |
| 2385 | A6XX_GMU_NMI_CONTROL_STATUS, &acked); |
| 2386 | |
| 2387 | /* NMI FW ACK recevied */ |
| 2388 | if (acked == 0x1) |
| 2389 | break; |
| 2390 | |
| 2391 | udelay(100); |
| 2392 | } |
| 2393 | |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 2394 | if (acked) { |
| 2395 | /* Make sure VBIF/GBIF is cleared before resetting */ |
| 2396 | ret = adreno_vbif_clear_pending_transactions(device); |
| 2397 | |
| 2398 | if (ret == 0) |
| 2399 | ret = adreno_soft_reset(device); |
| 2400 | } |
| 2401 | |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 2402 | if (ret) |
| 2403 | KGSL_DEV_ERR_ONCE(device, "Device soft reset failed\n"); |
| 2404 | } |
| 2405 | if (ret) { |
| 2406 | /* If soft reset failed/skipped, then pull the power */ |
| 2407 | set_bit(ADRENO_DEVICE_HARD_RESET, &adreno_dev->priv); |
| 2408 | /* since device is officially off now clear start bit */ |
| 2409 | clear_bit(ADRENO_DEVICE_STARTED, &adreno_dev->priv); |
| 2410 | |
| 2411 | /* Keep trying to start the device until it works */ |
| 2412 | for (i = 0; i < NUM_TIMES_RESET_RETRY; i++) { |
| 2413 | ret = adreno_start(device, 0); |
| 2414 | if (!ret) |
| 2415 | break; |
| 2416 | |
| 2417 | msleep(20); |
| 2418 | } |
| 2419 | } |
| 2420 | |
| 2421 | clear_bit(ADRENO_DEVICE_HARD_RESET, &adreno_dev->priv); |
| 2422 | |
| 2423 | if (ret) |
| 2424 | return ret; |
| 2425 | |
| 2426 | if (i != 0) |
| 2427 | KGSL_DRV_WARN(device, "Device hard reset tried %d tries\n", i); |
| 2428 | |
| 2429 | /* |
| 2430 | * If active_cnt is non-zero then the system was active before |
| 2431 | * going into a reset - put it back in that state |
| 2432 | */ |
| 2433 | |
| 2434 | if (atomic_read(&device->active_cnt)) |
| 2435 | kgsl_pwrctrl_change_state(device, KGSL_STATE_ACTIVE); |
| 2436 | else |
| 2437 | kgsl_pwrctrl_change_state(device, KGSL_STATE_NAP); |
| 2438 | |
| 2439 | return ret; |
| 2440 | } |
| 2441 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2442 | static void a6xx_cp_hw_err_callback(struct adreno_device *adreno_dev, int bit) |
| 2443 | { |
| 2444 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 2445 | unsigned int status1, status2; |
| 2446 | |
| 2447 | kgsl_regread(device, A6XX_CP_INTERRUPT_STATUS, &status1); |
| 2448 | |
Shrenuj Bansal | a602c02 | 2017-03-08 10:40:34 -0800 | [diff] [blame] | 2449 | if (status1 & BIT(A6XX_CP_OPCODE_ERROR)) { |
| 2450 | unsigned int opcode; |
| 2451 | |
| 2452 | kgsl_regwrite(device, A6XX_CP_SQE_STAT_ADDR, 1); |
| 2453 | kgsl_regread(device, A6XX_CP_SQE_STAT_DATA, &opcode); |
| 2454 | KGSL_DRV_CRIT_RATELIMIT(device, |
Kyle Piefer | 2ce0616 | 2017-03-15 11:29:08 -0700 | [diff] [blame] | 2455 | "CP opcode error interrupt | opcode=0x%8.8x\n", |
| 2456 | opcode); |
Shrenuj Bansal | a602c02 | 2017-03-08 10:40:34 -0800 | [diff] [blame] | 2457 | } |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2458 | if (status1 & BIT(A6XX_CP_UCODE_ERROR)) |
| 2459 | KGSL_DRV_CRIT_RATELIMIT(device, "CP ucode error interrupt\n"); |
| 2460 | if (status1 & BIT(A6XX_CP_HW_FAULT_ERROR)) { |
| 2461 | kgsl_regread(device, A6XX_CP_HW_FAULT, &status2); |
| 2462 | KGSL_DRV_CRIT_RATELIMIT(device, |
| 2463 | "CP | Ringbuffer HW fault | status=%x\n", |
| 2464 | status2); |
| 2465 | } |
| 2466 | if (status1 & BIT(A6XX_CP_REGISTER_PROTECTION_ERROR)) { |
| 2467 | kgsl_regread(device, A6XX_CP_PROTECT_STATUS, &status2); |
| 2468 | KGSL_DRV_CRIT_RATELIMIT(device, |
| 2469 | "CP | Protected mode error | %s | addr=%x | status=%x\n", |
| 2470 | status2 & (1 << 20) ? "READ" : "WRITE", |
Lynus Vaz | dc80734 | 2017-02-20 18:23:25 +0530 | [diff] [blame] | 2471 | status2 & 0x3FFFF, status2); |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2472 | } |
| 2473 | if (status1 & BIT(A6XX_CP_AHB_ERROR)) |
| 2474 | KGSL_DRV_CRIT_RATELIMIT(device, |
| 2475 | "CP AHB error interrupt\n"); |
| 2476 | if (status1 & BIT(A6XX_CP_VSD_PARITY_ERROR)) |
| 2477 | KGSL_DRV_CRIT_RATELIMIT(device, |
| 2478 | "CP VSD decoder parity error\n"); |
| 2479 | if (status1 & BIT(A6XX_CP_ILLEGAL_INSTR_ERROR)) |
| 2480 | KGSL_DRV_CRIT_RATELIMIT(device, |
| 2481 | "CP Illegal instruction error\n"); |
| 2482 | |
| 2483 | } |
| 2484 | |
| 2485 | static void a6xx_err_callback(struct adreno_device *adreno_dev, int bit) |
| 2486 | { |
| 2487 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 2488 | |
| 2489 | switch (bit) { |
| 2490 | case A6XX_INT_CP_AHB_ERROR: |
| 2491 | KGSL_DRV_CRIT_RATELIMIT(device, "CP: AHB bus error\n"); |
| 2492 | break; |
| 2493 | case A6XX_INT_ATB_ASYNCFIFO_OVERFLOW: |
| 2494 | KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: ATB ASYNC overflow\n"); |
| 2495 | break; |
| 2496 | case A6XX_INT_RBBM_ATB_BUS_OVERFLOW: |
| 2497 | KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: ATB bus overflow\n"); |
| 2498 | break; |
| 2499 | case A6XX_INT_UCHE_OOB_ACCESS: |
| 2500 | KGSL_DRV_CRIT_RATELIMIT(device, "UCHE: Out of bounds access\n"); |
| 2501 | break; |
| 2502 | case A6XX_INT_UCHE_TRAP_INTR: |
| 2503 | KGSL_DRV_CRIT_RATELIMIT(device, "UCHE: Trap interrupt\n"); |
| 2504 | break; |
| 2505 | default: |
| 2506 | KGSL_DRV_CRIT_RATELIMIT(device, "Unknown interrupt %d\n", bit); |
| 2507 | } |
| 2508 | } |
| 2509 | |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 2510 | /* GPU System Cache control registers */ |
| 2511 | #define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0 0x4 |
| 2512 | #define A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1 0x8 |
| 2513 | |
| 2514 | static inline void _reg_rmw(void __iomem *regaddr, |
| 2515 | unsigned int mask, unsigned int bits) |
| 2516 | { |
| 2517 | unsigned int val = 0; |
| 2518 | |
| 2519 | val = __raw_readl(regaddr); |
| 2520 | /* Make sure the above read completes before we proceed */ |
| 2521 | rmb(); |
| 2522 | val &= ~mask; |
| 2523 | __raw_writel(val | bits, regaddr); |
| 2524 | /* Make sure the above write posts before we proceed*/ |
| 2525 | wmb(); |
| 2526 | } |
| 2527 | |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 2528 | /* |
| 2529 | * a6xx_llc_configure_gpu_scid() - Program the sub-cache ID for all GPU blocks |
| 2530 | * @adreno_dev: The adreno device pointer |
| 2531 | */ |
| 2532 | static void a6xx_llc_configure_gpu_scid(struct adreno_device *adreno_dev) |
| 2533 | { |
| 2534 | uint32_t gpu_scid; |
| 2535 | uint32_t gpu_cntl1_val = 0; |
| 2536 | int i; |
| 2537 | void __iomem *gpu_cx_reg; |
| 2538 | |
| 2539 | gpu_scid = adreno_llc_get_scid(adreno_dev->gpu_llc_slice); |
| 2540 | for (i = 0; i < A6XX_LLC_NUM_GPU_SCIDS; i++) |
| 2541 | gpu_cntl1_val = (gpu_cntl1_val << A6XX_GPU_LLC_SCID_NUM_BITS) |
| 2542 | | gpu_scid; |
| 2543 | |
| 2544 | gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE, A6XX_GPU_CX_REG_SIZE); |
| 2545 | _reg_rmw(gpu_cx_reg + A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1, |
| 2546 | A6XX_GPU_LLC_SCID_MASK, gpu_cntl1_val); |
| 2547 | iounmap(gpu_cx_reg); |
| 2548 | } |
| 2549 | |
| 2550 | /* |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 2551 | * a6xx_llc_configure_gpuhtw_scid() - Program the SCID for GPU pagetables |
| 2552 | * @adreno_dev: The adreno device pointer |
| 2553 | */ |
| 2554 | static void a6xx_llc_configure_gpuhtw_scid(struct adreno_device *adreno_dev) |
| 2555 | { |
| 2556 | uint32_t gpuhtw_scid; |
| 2557 | void __iomem *gpu_cx_reg; |
| 2558 | |
| 2559 | gpuhtw_scid = adreno_llc_get_scid(adreno_dev->gpuhtw_llc_slice); |
| 2560 | |
| 2561 | gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE, A6XX_GPU_CX_REG_SIZE); |
Kyle Piefer | 11a48b6 | 2017-03-17 14:53:40 -0700 | [diff] [blame] | 2562 | _reg_rmw(gpu_cx_reg + A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_1, |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 2563 | A6XX_GPUHTW_LLC_SCID_MASK, |
| 2564 | gpuhtw_scid << A6XX_GPUHTW_LLC_SCID_SHIFT); |
| 2565 | iounmap(gpu_cx_reg); |
| 2566 | } |
| 2567 | |
| 2568 | /* |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 2569 | * a6xx_llc_enable_overrides() - Override the page attributes |
| 2570 | * @adreno_dev: The adreno device pointer |
| 2571 | */ |
| 2572 | static void a6xx_llc_enable_overrides(struct adreno_device *adreno_dev) |
| 2573 | { |
| 2574 | void __iomem *gpu_cx_reg; |
| 2575 | |
| 2576 | /* |
| 2577 | * 0x3: readnoallocoverrideen=0 |
| 2578 | * read-no-alloc=0 - Allocate lines on read miss |
| 2579 | * writenoallocoverrideen=1 |
| 2580 | * write-no-alloc=1 - Do not allocates lines on write miss |
| 2581 | */ |
| 2582 | gpu_cx_reg = ioremap(A6XX_GPU_CX_REG_BASE, A6XX_GPU_CX_REG_SIZE); |
| 2583 | __raw_writel(0x3, gpu_cx_reg + A6XX_GPU_CX_MISC_SYSTEM_CACHE_CNTL_0); |
| 2584 | /* Make sure the above write posts before we proceed*/ |
| 2585 | wmb(); |
| 2586 | iounmap(gpu_cx_reg); |
| 2587 | } |
| 2588 | |
Lynus Vaz | 1fde74d | 2017-03-20 18:02:47 +0530 | [diff] [blame] | 2589 | static const char *fault_block[8] = { |
| 2590 | [0] = "CP", |
| 2591 | [1] = "UCHE", |
| 2592 | [2] = "VFD", |
| 2593 | [3] = "UCHE", |
| 2594 | [4] = "CCU", |
| 2595 | [5] = "unknown", |
| 2596 | [6] = "CDP Prefetch", |
| 2597 | [7] = "GPMU", |
| 2598 | }; |
| 2599 | |
| 2600 | static const char *uche_client[8] = { |
| 2601 | [0] = "VFD", |
| 2602 | [1] = "SP", |
| 2603 | [2] = "VSC", |
| 2604 | [3] = "VPC", |
| 2605 | [4] = "HLSQ", |
| 2606 | [5] = "PC", |
| 2607 | [6] = "LRZ", |
| 2608 | [7] = "unknown", |
| 2609 | }; |
| 2610 | |
| 2611 | static const char *a6xx_iommu_fault_block(struct adreno_device *adreno_dev, |
| 2612 | unsigned int fsynr1) |
| 2613 | { |
| 2614 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 2615 | unsigned int client_id; |
| 2616 | unsigned int uche_client_id; |
| 2617 | |
| 2618 | client_id = fsynr1 & 0xff; |
| 2619 | |
| 2620 | if (client_id >= ARRAY_SIZE(fault_block)) |
| 2621 | return "unknown"; |
| 2622 | else if (client_id != 3) |
| 2623 | return fault_block[client_id]; |
| 2624 | |
Harshdeep Dhatt | 3f074a9 | 2017-05-01 12:59:01 -0600 | [diff] [blame] | 2625 | mutex_lock(&device->mutex); |
Lynus Vaz | 1fde74d | 2017-03-20 18:02:47 +0530 | [diff] [blame] | 2626 | kgsl_regread(device, A6XX_UCHE_CLIENT_PF, &uche_client_id); |
Harshdeep Dhatt | 3f074a9 | 2017-05-01 12:59:01 -0600 | [diff] [blame] | 2627 | mutex_unlock(&device->mutex); |
| 2628 | |
Lynus Vaz | 1fde74d | 2017-03-20 18:02:47 +0530 | [diff] [blame] | 2629 | return uche_client[uche_client_id & A6XX_UCHE_CLIENT_PF_CLIENT_ID_MASK]; |
| 2630 | } |
| 2631 | |
Harshdeep Dhatt | d388e52 | 2017-07-06 14:30:06 -0600 | [diff] [blame] | 2632 | static void a6xx_cp_callback(struct adreno_device *adreno_dev, int bit) |
| 2633 | { |
| 2634 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 2635 | |
Harshdeep Dhatt | 7ee8a86 | 2017-11-20 17:51:54 -0700 | [diff] [blame] | 2636 | if (adreno_is_preemption_enabled(adreno_dev)) |
Harshdeep Dhatt | 12a642c | 2017-08-17 12:19:26 -0600 | [diff] [blame] | 2637 | a6xx_preemption_trigger(adreno_dev); |
| 2638 | |
Harshdeep Dhatt | d388e52 | 2017-07-06 14:30:06 -0600 | [diff] [blame] | 2639 | adreno_dispatcher_schedule(device); |
| 2640 | } |
| 2641 | |
Carter Cooper | c8d4864 | 2017-08-18 10:39:57 -0600 | [diff] [blame^] | 2642 | /* |
| 2643 | * a6xx_gpc_err_int_callback() - Isr for GPC error interrupts |
| 2644 | * @adreno_dev: Pointer to device |
| 2645 | * @bit: Interrupt bit |
| 2646 | */ |
| 2647 | static void a6xx_gpc_err_int_callback(struct adreno_device *adreno_dev, int bit) |
| 2648 | { |
| 2649 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 2650 | |
| 2651 | /* |
| 2652 | * GPC error is typically the result of mistake SW programming. |
| 2653 | * Force GPU fault for this interrupt so that we can debug it |
| 2654 | * with help of register dump. |
| 2655 | */ |
| 2656 | |
| 2657 | KGSL_DRV_CRIT_RATELIMIT(device, "RBBM: GPC error\n"); |
| 2658 | adreno_irqctrl(adreno_dev, 0); |
| 2659 | |
| 2660 | /* Trigger a fault in the dispatcher - this will effect a restart */ |
| 2661 | adreno_set_gpu_fault(adreno_dev, ADRENO_SOFT_FAULT); |
| 2662 | adreno_dispatcher_schedule(device); |
| 2663 | } |
| 2664 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2665 | #define A6XX_INT_MASK \ |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 2666 | ((1 << A6XX_INT_CP_AHB_ERROR) | \ |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2667 | (1 << A6XX_INT_ATB_ASYNCFIFO_OVERFLOW) | \ |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 2668 | (1 << A6XX_INT_RBBM_GPC_ERROR) | \ |
| 2669 | (1 << A6XX_INT_CP_SW) | \ |
| 2670 | (1 << A6XX_INT_CP_HW_ERROR) | \ |
| 2671 | (1 << A6XX_INT_CP_IB2) | \ |
| 2672 | (1 << A6XX_INT_CP_IB1) | \ |
| 2673 | (1 << A6XX_INT_CP_RB) | \ |
| 2674 | (1 << A6XX_INT_CP_CACHE_FLUSH_TS) | \ |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2675 | (1 << A6XX_INT_RBBM_ATB_BUS_OVERFLOW) | \ |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 2676 | (1 << A6XX_INT_RBBM_HANG_DETECT) | \ |
| 2677 | (1 << A6XX_INT_UCHE_OOB_ACCESS) | \ |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2678 | (1 << A6XX_INT_UCHE_TRAP_INTR)) |
| 2679 | |
| 2680 | static struct adreno_irq_funcs a6xx_irq_funcs[32] = { |
| 2681 | ADRENO_IRQ_CALLBACK(NULL), /* 0 - RBBM_GPU_IDLE */ |
| 2682 | ADRENO_IRQ_CALLBACK(a6xx_err_callback), /* 1 - RBBM_AHB_ERROR */ |
| 2683 | ADRENO_IRQ_CALLBACK(NULL), /* 2 - UNUSED */ |
| 2684 | ADRENO_IRQ_CALLBACK(NULL), /* 3 - UNUSED */ |
| 2685 | ADRENO_IRQ_CALLBACK(NULL), /* 4 - UNUSED */ |
| 2686 | ADRENO_IRQ_CALLBACK(NULL), /* 5 - UNUSED */ |
| 2687 | /* 6 - RBBM_ATB_ASYNC_OVERFLOW */ |
| 2688 | ADRENO_IRQ_CALLBACK(a6xx_err_callback), |
Carter Cooper | c8d4864 | 2017-08-18 10:39:57 -0600 | [diff] [blame^] | 2689 | ADRENO_IRQ_CALLBACK(a6xx_gpc_err_int_callback), /* 7 - GPC_ERR */ |
Harshdeep Dhatt | 0cdc899 | 2017-05-31 15:44:05 -0600 | [diff] [blame] | 2690 | ADRENO_IRQ_CALLBACK(a6xx_preemption_callback),/* 8 - CP_SW */ |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2691 | ADRENO_IRQ_CALLBACK(a6xx_cp_hw_err_callback), /* 9 - CP_HW_ERROR */ |
| 2692 | ADRENO_IRQ_CALLBACK(NULL), /* 10 - CP_CCU_FLUSH_DEPTH_TS */ |
| 2693 | ADRENO_IRQ_CALLBACK(NULL), /* 11 - CP_CCU_FLUSH_COLOR_TS */ |
| 2694 | ADRENO_IRQ_CALLBACK(NULL), /* 12 - CP_CCU_RESOLVE_TS */ |
| 2695 | ADRENO_IRQ_CALLBACK(adreno_cp_callback), /* 13 - CP_IB2_INT */ |
| 2696 | ADRENO_IRQ_CALLBACK(adreno_cp_callback), /* 14 - CP_IB1_INT */ |
| 2697 | ADRENO_IRQ_CALLBACK(adreno_cp_callback), /* 15 - CP_RB_INT */ |
| 2698 | ADRENO_IRQ_CALLBACK(NULL), /* 16 - UNUSED */ |
| 2699 | ADRENO_IRQ_CALLBACK(NULL), /* 17 - CP_RB_DONE_TS */ |
| 2700 | ADRENO_IRQ_CALLBACK(NULL), /* 18 - CP_WT_DONE_TS */ |
| 2701 | ADRENO_IRQ_CALLBACK(NULL), /* 19 - UNUSED */ |
Harshdeep Dhatt | d388e52 | 2017-07-06 14:30:06 -0600 | [diff] [blame] | 2702 | ADRENO_IRQ_CALLBACK(a6xx_cp_callback), /* 20 - CP_CACHE_FLUSH_TS */ |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 2703 | ADRENO_IRQ_CALLBACK(NULL), /* 21 - UNUSED */ |
| 2704 | ADRENO_IRQ_CALLBACK(a6xx_err_callback), /* 22 - RBBM_ATB_BUS_OVERFLOW */ |
| 2705 | /* 23 - MISC_HANG_DETECT */ |
| 2706 | ADRENO_IRQ_CALLBACK(adreno_hang_int_callback), |
| 2707 | ADRENO_IRQ_CALLBACK(a6xx_err_callback), /* 24 - UCHE_OOB_ACCESS */ |
| 2708 | ADRENO_IRQ_CALLBACK(a6xx_err_callback), /* 25 - UCHE_TRAP_INTR */ |
| 2709 | ADRENO_IRQ_CALLBACK(NULL), /* 26 - DEBBUS_INTR_0 */ |
| 2710 | ADRENO_IRQ_CALLBACK(NULL), /* 27 - DEBBUS_INTR_1 */ |
| 2711 | ADRENO_IRQ_CALLBACK(NULL), /* 28 - UNUSED */ |
| 2712 | ADRENO_IRQ_CALLBACK(NULL), /* 29 - UNUSED */ |
| 2713 | ADRENO_IRQ_CALLBACK(NULL), /* 30 - ISDB_CPU_IRQ */ |
| 2714 | ADRENO_IRQ_CALLBACK(NULL), /* 31 - ISDB_UNDER_DEBUG */ |
| 2715 | }; |
| 2716 | |
| 2717 | static struct adreno_irq a6xx_irq = { |
| 2718 | .funcs = a6xx_irq_funcs, |
| 2719 | .mask = A6XX_INT_MASK, |
| 2720 | }; |
| 2721 | |
Shrenuj Bansal | 4166540 | 2016-12-16 15:25:54 -0800 | [diff] [blame] | 2722 | static struct adreno_snapshot_sizes a6xx_snap_sizes = { |
| 2723 | .cp_pfp = 0x33, |
| 2724 | .roq = 0x400, |
| 2725 | }; |
| 2726 | |
| 2727 | static struct adreno_snapshot_data a6xx_snapshot_data = { |
| 2728 | .sect_sizes = &a6xx_snap_sizes, |
| 2729 | }; |
| 2730 | |
Lokesh Batra | a8300e0 | 2017-05-25 11:17:40 -0700 | [diff] [blame] | 2731 | static struct adreno_coresight_register a6xx_coresight_regs[] = { |
| 2732 | { A6XX_DBGC_CFG_DBGBUS_SEL_A }, |
| 2733 | { A6XX_DBGC_CFG_DBGBUS_SEL_B }, |
| 2734 | { A6XX_DBGC_CFG_DBGBUS_SEL_C }, |
| 2735 | { A6XX_DBGC_CFG_DBGBUS_SEL_D }, |
| 2736 | { A6XX_DBGC_CFG_DBGBUS_CNTLT }, |
| 2737 | { A6XX_DBGC_CFG_DBGBUS_CNTLM }, |
| 2738 | { A6XX_DBGC_CFG_DBGBUS_OPL }, |
| 2739 | { A6XX_DBGC_CFG_DBGBUS_OPE }, |
| 2740 | { A6XX_DBGC_CFG_DBGBUS_IVTL_0 }, |
| 2741 | { A6XX_DBGC_CFG_DBGBUS_IVTL_1 }, |
| 2742 | { A6XX_DBGC_CFG_DBGBUS_IVTL_2 }, |
| 2743 | { A6XX_DBGC_CFG_DBGBUS_IVTL_3 }, |
| 2744 | { A6XX_DBGC_CFG_DBGBUS_MASKL_0 }, |
| 2745 | { A6XX_DBGC_CFG_DBGBUS_MASKL_1 }, |
| 2746 | { A6XX_DBGC_CFG_DBGBUS_MASKL_2 }, |
| 2747 | { A6XX_DBGC_CFG_DBGBUS_MASKL_3 }, |
| 2748 | { A6XX_DBGC_CFG_DBGBUS_BYTEL_0 }, |
| 2749 | { A6XX_DBGC_CFG_DBGBUS_BYTEL_1 }, |
| 2750 | { A6XX_DBGC_CFG_DBGBUS_IVTE_0 }, |
| 2751 | { A6XX_DBGC_CFG_DBGBUS_IVTE_1 }, |
| 2752 | { A6XX_DBGC_CFG_DBGBUS_IVTE_2 }, |
| 2753 | { A6XX_DBGC_CFG_DBGBUS_IVTE_3 }, |
| 2754 | { A6XX_DBGC_CFG_DBGBUS_MASKE_0 }, |
| 2755 | { A6XX_DBGC_CFG_DBGBUS_MASKE_1 }, |
| 2756 | { A6XX_DBGC_CFG_DBGBUS_MASKE_2 }, |
| 2757 | { A6XX_DBGC_CFG_DBGBUS_MASKE_3 }, |
| 2758 | { A6XX_DBGC_CFG_DBGBUS_NIBBLEE }, |
| 2759 | { A6XX_DBGC_CFG_DBGBUS_PTRC0 }, |
| 2760 | { A6XX_DBGC_CFG_DBGBUS_PTRC1 }, |
| 2761 | { A6XX_DBGC_CFG_DBGBUS_LOADREG }, |
| 2762 | { A6XX_DBGC_CFG_DBGBUS_IDX }, |
| 2763 | { A6XX_DBGC_CFG_DBGBUS_CLRC }, |
| 2764 | { A6XX_DBGC_CFG_DBGBUS_LOADIVT }, |
| 2765 | { A6XX_DBGC_VBIF_DBG_CNTL }, |
| 2766 | { A6XX_DBGC_DBG_LO_HI_GPIO }, |
| 2767 | { A6XX_DBGC_EXT_TRACE_BUS_CNTL }, |
| 2768 | { A6XX_DBGC_READ_AHB_THROUGH_DBG }, |
| 2769 | { A6XX_DBGC_CFG_DBGBUS_TRACE_BUF1 }, |
| 2770 | { A6XX_DBGC_CFG_DBGBUS_TRACE_BUF2 }, |
| 2771 | { A6XX_DBGC_EVT_CFG }, |
| 2772 | { A6XX_DBGC_EVT_INTF_SEL_0 }, |
| 2773 | { A6XX_DBGC_EVT_INTF_SEL_1 }, |
| 2774 | { A6XX_DBGC_PERF_ATB_CFG }, |
| 2775 | { A6XX_DBGC_PERF_ATB_COUNTER_SEL_0 }, |
| 2776 | { A6XX_DBGC_PERF_ATB_COUNTER_SEL_1 }, |
| 2777 | { A6XX_DBGC_PERF_ATB_COUNTER_SEL_2 }, |
| 2778 | { A6XX_DBGC_PERF_ATB_COUNTER_SEL_3 }, |
| 2779 | { A6XX_DBGC_PERF_ATB_TRIG_INTF_SEL_0 }, |
| 2780 | { A6XX_DBGC_PERF_ATB_TRIG_INTF_SEL_1 }, |
| 2781 | { A6XX_DBGC_PERF_ATB_DRAIN_CMD }, |
| 2782 | { A6XX_DBGC_ECO_CNTL }, |
| 2783 | { A6XX_DBGC_AHB_DBG_CNTL }, |
| 2784 | }; |
| 2785 | |
| 2786 | static struct adreno_coresight_register a6xx_coresight_regs_cx[] = { |
| 2787 | { A6XX_CX_DBGC_CFG_DBGBUS_SEL_A }, |
| 2788 | { A6XX_CX_DBGC_CFG_DBGBUS_SEL_B }, |
| 2789 | { A6XX_CX_DBGC_CFG_DBGBUS_SEL_C }, |
| 2790 | { A6XX_CX_DBGC_CFG_DBGBUS_SEL_D }, |
| 2791 | { A6XX_CX_DBGC_CFG_DBGBUS_CNTLT }, |
| 2792 | { A6XX_CX_DBGC_CFG_DBGBUS_CNTLM }, |
| 2793 | { A6XX_CX_DBGC_CFG_DBGBUS_OPL }, |
| 2794 | { A6XX_CX_DBGC_CFG_DBGBUS_OPE }, |
| 2795 | { A6XX_CX_DBGC_CFG_DBGBUS_IVTL_0 }, |
| 2796 | { A6XX_CX_DBGC_CFG_DBGBUS_IVTL_1 }, |
| 2797 | { A6XX_CX_DBGC_CFG_DBGBUS_IVTL_2 }, |
| 2798 | { A6XX_CX_DBGC_CFG_DBGBUS_IVTL_3 }, |
| 2799 | { A6XX_CX_DBGC_CFG_DBGBUS_MASKL_0 }, |
| 2800 | { A6XX_CX_DBGC_CFG_DBGBUS_MASKL_1 }, |
| 2801 | { A6XX_CX_DBGC_CFG_DBGBUS_MASKL_2 }, |
| 2802 | { A6XX_CX_DBGC_CFG_DBGBUS_MASKL_3 }, |
| 2803 | { A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_0 }, |
| 2804 | { A6XX_CX_DBGC_CFG_DBGBUS_BYTEL_1 }, |
| 2805 | { A6XX_CX_DBGC_CFG_DBGBUS_IVTE_0 }, |
| 2806 | { A6XX_CX_DBGC_CFG_DBGBUS_IVTE_1 }, |
| 2807 | { A6XX_CX_DBGC_CFG_DBGBUS_IVTE_2 }, |
| 2808 | { A6XX_CX_DBGC_CFG_DBGBUS_IVTE_3 }, |
| 2809 | { A6XX_CX_DBGC_CFG_DBGBUS_MASKE_0 }, |
| 2810 | { A6XX_CX_DBGC_CFG_DBGBUS_MASKE_1 }, |
| 2811 | { A6XX_CX_DBGC_CFG_DBGBUS_MASKE_2 }, |
| 2812 | { A6XX_CX_DBGC_CFG_DBGBUS_MASKE_3 }, |
| 2813 | { A6XX_CX_DBGC_CFG_DBGBUS_NIBBLEE }, |
| 2814 | { A6XX_CX_DBGC_CFG_DBGBUS_PTRC0 }, |
| 2815 | { A6XX_CX_DBGC_CFG_DBGBUS_PTRC1 }, |
| 2816 | { A6XX_CX_DBGC_CFG_DBGBUS_LOADREG }, |
| 2817 | { A6XX_CX_DBGC_CFG_DBGBUS_IDX }, |
| 2818 | { A6XX_CX_DBGC_CFG_DBGBUS_CLRC }, |
| 2819 | { A6XX_CX_DBGC_CFG_DBGBUS_LOADIVT }, |
| 2820 | { A6XX_CX_DBGC_VBIF_DBG_CNTL }, |
| 2821 | { A6XX_CX_DBGC_DBG_LO_HI_GPIO }, |
| 2822 | { A6XX_CX_DBGC_EXT_TRACE_BUS_CNTL }, |
| 2823 | { A6XX_CX_DBGC_READ_AHB_THROUGH_DBG }, |
| 2824 | { A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF1 }, |
| 2825 | { A6XX_CX_DBGC_CFG_DBGBUS_TRACE_BUF2 }, |
| 2826 | { A6XX_CX_DBGC_EVT_CFG }, |
| 2827 | { A6XX_CX_DBGC_EVT_INTF_SEL_0 }, |
| 2828 | { A6XX_CX_DBGC_EVT_INTF_SEL_1 }, |
| 2829 | { A6XX_CX_DBGC_PERF_ATB_CFG }, |
| 2830 | { A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_0 }, |
| 2831 | { A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_1 }, |
| 2832 | { A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_2 }, |
| 2833 | { A6XX_CX_DBGC_PERF_ATB_COUNTER_SEL_3 }, |
| 2834 | { A6XX_CX_DBGC_PERF_ATB_TRIG_INTF_SEL_0 }, |
| 2835 | { A6XX_CX_DBGC_PERF_ATB_TRIG_INTF_SEL_1 }, |
| 2836 | { A6XX_CX_DBGC_PERF_ATB_DRAIN_CMD }, |
| 2837 | { A6XX_CX_DBGC_ECO_CNTL }, |
| 2838 | { A6XX_CX_DBGC_AHB_DBG_CNTL }, |
| 2839 | }; |
| 2840 | |
| 2841 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_sel_a, &a6xx_coresight_regs[0]); |
| 2842 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_sel_b, &a6xx_coresight_regs[1]); |
| 2843 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_sel_c, &a6xx_coresight_regs[2]); |
| 2844 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_sel_d, &a6xx_coresight_regs[3]); |
| 2845 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_cntlt, &a6xx_coresight_regs[4]); |
| 2846 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_cntlm, &a6xx_coresight_regs[5]); |
| 2847 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_opl, &a6xx_coresight_regs[6]); |
| 2848 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ope, &a6xx_coresight_regs[7]); |
| 2849 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ivtl_0, &a6xx_coresight_regs[8]); |
| 2850 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ivtl_1, &a6xx_coresight_regs[9]); |
| 2851 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ivtl_2, &a6xx_coresight_regs[10]); |
| 2852 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ivtl_3, &a6xx_coresight_regs[11]); |
| 2853 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_maskl_0, &a6xx_coresight_regs[12]); |
| 2854 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_maskl_1, &a6xx_coresight_regs[13]); |
| 2855 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_maskl_2, &a6xx_coresight_regs[14]); |
| 2856 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_maskl_3, &a6xx_coresight_regs[15]); |
| 2857 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_bytel_0, &a6xx_coresight_regs[16]); |
| 2858 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_bytel_1, &a6xx_coresight_regs[17]); |
| 2859 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ivte_0, &a6xx_coresight_regs[18]); |
| 2860 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ivte_1, &a6xx_coresight_regs[19]); |
| 2861 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ivte_2, &a6xx_coresight_regs[20]); |
| 2862 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ivte_3, &a6xx_coresight_regs[21]); |
| 2863 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_maske_0, &a6xx_coresight_regs[22]); |
| 2864 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_maske_1, &a6xx_coresight_regs[23]); |
| 2865 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_maske_2, &a6xx_coresight_regs[24]); |
| 2866 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_maske_3, &a6xx_coresight_regs[25]); |
| 2867 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_nibblee, &a6xx_coresight_regs[26]); |
| 2868 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ptrc0, &a6xx_coresight_regs[27]); |
| 2869 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_ptrc1, &a6xx_coresight_regs[28]); |
| 2870 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_loadreg, &a6xx_coresight_regs[29]); |
| 2871 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_idx, &a6xx_coresight_regs[30]); |
| 2872 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_clrc, &a6xx_coresight_regs[31]); |
| 2873 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_loadivt, &a6xx_coresight_regs[32]); |
| 2874 | static ADRENO_CORESIGHT_ATTR(vbif_dbg_cntl, &a6xx_coresight_regs[33]); |
| 2875 | static ADRENO_CORESIGHT_ATTR(dbg_lo_hi_gpio, &a6xx_coresight_regs[34]); |
| 2876 | static ADRENO_CORESIGHT_ATTR(ext_trace_bus_cntl, &a6xx_coresight_regs[35]); |
| 2877 | static ADRENO_CORESIGHT_ATTR(read_ahb_through_dbg, &a6xx_coresight_regs[36]); |
| 2878 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_trace_buf1, &a6xx_coresight_regs[37]); |
| 2879 | static ADRENO_CORESIGHT_ATTR(cfg_dbgbus_trace_buf2, &a6xx_coresight_regs[38]); |
| 2880 | static ADRENO_CORESIGHT_ATTR(evt_cfg, &a6xx_coresight_regs[39]); |
| 2881 | static ADRENO_CORESIGHT_ATTR(evt_intf_sel_0, &a6xx_coresight_regs[40]); |
| 2882 | static ADRENO_CORESIGHT_ATTR(evt_intf_sel_1, &a6xx_coresight_regs[41]); |
| 2883 | static ADRENO_CORESIGHT_ATTR(perf_atb_cfg, &a6xx_coresight_regs[42]); |
| 2884 | static ADRENO_CORESIGHT_ATTR(perf_atb_counter_sel_0, &a6xx_coresight_regs[43]); |
| 2885 | static ADRENO_CORESIGHT_ATTR(perf_atb_counter_sel_1, &a6xx_coresight_regs[44]); |
| 2886 | static ADRENO_CORESIGHT_ATTR(perf_atb_counter_sel_2, &a6xx_coresight_regs[45]); |
| 2887 | static ADRENO_CORESIGHT_ATTR(perf_atb_counter_sel_3, &a6xx_coresight_regs[46]); |
| 2888 | static ADRENO_CORESIGHT_ATTR(perf_atb_trig_intf_sel_0, |
| 2889 | &a6xx_coresight_regs[47]); |
| 2890 | static ADRENO_CORESIGHT_ATTR(perf_atb_trig_intf_sel_1, |
| 2891 | &a6xx_coresight_regs[48]); |
| 2892 | static ADRENO_CORESIGHT_ATTR(perf_atb_drain_cmd, &a6xx_coresight_regs[49]); |
| 2893 | static ADRENO_CORESIGHT_ATTR(eco_cntl, &a6xx_coresight_regs[50]); |
| 2894 | static ADRENO_CORESIGHT_ATTR(ahb_dbg_cntl, &a6xx_coresight_regs[51]); |
| 2895 | |
| 2896 | /*CX debug registers*/ |
| 2897 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_sel_a, |
| 2898 | &a6xx_coresight_regs_cx[0]); |
| 2899 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_sel_b, |
| 2900 | &a6xx_coresight_regs_cx[1]); |
| 2901 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_sel_c, |
| 2902 | &a6xx_coresight_regs_cx[2]); |
| 2903 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_sel_d, |
| 2904 | &a6xx_coresight_regs_cx[3]); |
| 2905 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_cntlt, |
| 2906 | &a6xx_coresight_regs_cx[4]); |
| 2907 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_cntlm, |
| 2908 | &a6xx_coresight_regs_cx[5]); |
| 2909 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_opl, |
| 2910 | &a6xx_coresight_regs_cx[6]); |
| 2911 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ope, |
| 2912 | &a6xx_coresight_regs_cx[7]); |
| 2913 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ivtl_0, |
| 2914 | &a6xx_coresight_regs_cx[8]); |
| 2915 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ivtl_1, |
| 2916 | &a6xx_coresight_regs_cx[9]); |
| 2917 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ivtl_2, |
| 2918 | &a6xx_coresight_regs_cx[10]); |
| 2919 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ivtl_3, |
| 2920 | &a6xx_coresight_regs_cx[11]); |
| 2921 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_maskl_0, |
| 2922 | &a6xx_coresight_regs_cx[12]); |
| 2923 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_maskl_1, |
| 2924 | &a6xx_coresight_regs_cx[13]); |
| 2925 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_maskl_2, |
| 2926 | &a6xx_coresight_regs_cx[14]); |
| 2927 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_maskl_3, |
| 2928 | &a6xx_coresight_regs_cx[15]); |
| 2929 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_bytel_0, |
| 2930 | &a6xx_coresight_regs_cx[16]); |
| 2931 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_bytel_1, |
| 2932 | &a6xx_coresight_regs_cx[17]); |
| 2933 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ivte_0, |
| 2934 | &a6xx_coresight_regs_cx[18]); |
| 2935 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ivte_1, |
| 2936 | &a6xx_coresight_regs_cx[19]); |
| 2937 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ivte_2, |
| 2938 | &a6xx_coresight_regs_cx[20]); |
| 2939 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ivte_3, |
| 2940 | &a6xx_coresight_regs_cx[21]); |
| 2941 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_maske_0, |
| 2942 | &a6xx_coresight_regs_cx[22]); |
| 2943 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_maske_1, |
| 2944 | &a6xx_coresight_regs_cx[23]); |
| 2945 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_maske_2, |
| 2946 | &a6xx_coresight_regs_cx[24]); |
| 2947 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_maske_3, |
| 2948 | &a6xx_coresight_regs_cx[25]); |
| 2949 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_nibblee, |
| 2950 | &a6xx_coresight_regs_cx[26]); |
| 2951 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ptrc0, |
| 2952 | &a6xx_coresight_regs_cx[27]); |
| 2953 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_ptrc1, |
| 2954 | &a6xx_coresight_regs_cx[28]); |
| 2955 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_loadreg, |
| 2956 | &a6xx_coresight_regs_cx[29]); |
| 2957 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_idx, |
| 2958 | &a6xx_coresight_regs_cx[30]); |
| 2959 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_clrc, |
| 2960 | &a6xx_coresight_regs_cx[31]); |
| 2961 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_loadivt, |
| 2962 | &a6xx_coresight_regs_cx[32]); |
| 2963 | static ADRENO_CORESIGHT_ATTR(cx_vbif_dbg_cntl, |
| 2964 | &a6xx_coresight_regs_cx[33]); |
| 2965 | static ADRENO_CORESIGHT_ATTR(cx_dbg_lo_hi_gpio, |
| 2966 | &a6xx_coresight_regs_cx[34]); |
| 2967 | static ADRENO_CORESIGHT_ATTR(cx_ext_trace_bus_cntl, |
| 2968 | &a6xx_coresight_regs_cx[35]); |
| 2969 | static ADRENO_CORESIGHT_ATTR(cx_read_ahb_through_dbg, |
| 2970 | &a6xx_coresight_regs_cx[36]); |
| 2971 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_trace_buf1, |
| 2972 | &a6xx_coresight_regs_cx[37]); |
| 2973 | static ADRENO_CORESIGHT_ATTR(cx_cfg_dbgbus_trace_buf2, |
| 2974 | &a6xx_coresight_regs_cx[38]); |
| 2975 | static ADRENO_CORESIGHT_ATTR(cx_evt_cfg, |
| 2976 | &a6xx_coresight_regs_cx[39]); |
| 2977 | static ADRENO_CORESIGHT_ATTR(cx_evt_intf_sel_0, |
| 2978 | &a6xx_coresight_regs_cx[40]); |
| 2979 | static ADRENO_CORESIGHT_ATTR(cx_evt_intf_sel_1, |
| 2980 | &a6xx_coresight_regs_cx[41]); |
| 2981 | static ADRENO_CORESIGHT_ATTR(cx_perf_atb_cfg, |
| 2982 | &a6xx_coresight_regs_cx[42]); |
| 2983 | static ADRENO_CORESIGHT_ATTR(cx_perf_atb_counter_sel_0, |
| 2984 | &a6xx_coresight_regs_cx[43]); |
| 2985 | static ADRENO_CORESIGHT_ATTR(cx_perf_atb_counter_sel_1, |
| 2986 | &a6xx_coresight_regs_cx[44]); |
| 2987 | static ADRENO_CORESIGHT_ATTR(cx_perf_atb_counter_sel_2, |
| 2988 | &a6xx_coresight_regs_cx[45]); |
| 2989 | static ADRENO_CORESIGHT_ATTR(cx_perf_atb_counter_sel_3, |
| 2990 | &a6xx_coresight_regs_cx[46]); |
| 2991 | static ADRENO_CORESIGHT_ATTR(cx_perf_atb_trig_intf_sel_0, |
| 2992 | &a6xx_coresight_regs_cx[47]); |
| 2993 | static ADRENO_CORESIGHT_ATTR(cx_perf_atb_trig_intf_sel_1, |
| 2994 | &a6xx_coresight_regs_cx[48]); |
| 2995 | static ADRENO_CORESIGHT_ATTR(cx_perf_atb_drain_cmd, |
| 2996 | &a6xx_coresight_regs_cx[49]); |
| 2997 | static ADRENO_CORESIGHT_ATTR(cx_eco_cntl, |
| 2998 | &a6xx_coresight_regs_cx[50]); |
| 2999 | static ADRENO_CORESIGHT_ATTR(cx_ahb_dbg_cntl, |
| 3000 | &a6xx_coresight_regs_cx[51]); |
| 3001 | |
| 3002 | static struct attribute *a6xx_coresight_attrs[] = { |
| 3003 | &coresight_attr_cfg_dbgbus_sel_a.attr.attr, |
| 3004 | &coresight_attr_cfg_dbgbus_sel_b.attr.attr, |
| 3005 | &coresight_attr_cfg_dbgbus_sel_c.attr.attr, |
| 3006 | &coresight_attr_cfg_dbgbus_sel_d.attr.attr, |
| 3007 | &coresight_attr_cfg_dbgbus_cntlt.attr.attr, |
| 3008 | &coresight_attr_cfg_dbgbus_cntlm.attr.attr, |
| 3009 | &coresight_attr_cfg_dbgbus_opl.attr.attr, |
| 3010 | &coresight_attr_cfg_dbgbus_ope.attr.attr, |
| 3011 | &coresight_attr_cfg_dbgbus_ivtl_0.attr.attr, |
| 3012 | &coresight_attr_cfg_dbgbus_ivtl_1.attr.attr, |
| 3013 | &coresight_attr_cfg_dbgbus_ivtl_2.attr.attr, |
| 3014 | &coresight_attr_cfg_dbgbus_ivtl_3.attr.attr, |
| 3015 | &coresight_attr_cfg_dbgbus_maskl_0.attr.attr, |
| 3016 | &coresight_attr_cfg_dbgbus_maskl_1.attr.attr, |
| 3017 | &coresight_attr_cfg_dbgbus_maskl_2.attr.attr, |
| 3018 | &coresight_attr_cfg_dbgbus_maskl_3.attr.attr, |
| 3019 | &coresight_attr_cfg_dbgbus_bytel_0.attr.attr, |
| 3020 | &coresight_attr_cfg_dbgbus_bytel_1.attr.attr, |
| 3021 | &coresight_attr_cfg_dbgbus_ivte_0.attr.attr, |
| 3022 | &coresight_attr_cfg_dbgbus_ivte_1.attr.attr, |
| 3023 | &coresight_attr_cfg_dbgbus_ivte_2.attr.attr, |
| 3024 | &coresight_attr_cfg_dbgbus_ivte_3.attr.attr, |
| 3025 | &coresight_attr_cfg_dbgbus_maske_0.attr.attr, |
| 3026 | &coresight_attr_cfg_dbgbus_maske_1.attr.attr, |
| 3027 | &coresight_attr_cfg_dbgbus_maske_2.attr.attr, |
| 3028 | &coresight_attr_cfg_dbgbus_maske_3.attr.attr, |
| 3029 | &coresight_attr_cfg_dbgbus_nibblee.attr.attr, |
| 3030 | &coresight_attr_cfg_dbgbus_ptrc0.attr.attr, |
| 3031 | &coresight_attr_cfg_dbgbus_ptrc1.attr.attr, |
| 3032 | &coresight_attr_cfg_dbgbus_loadreg.attr.attr, |
| 3033 | &coresight_attr_cfg_dbgbus_idx.attr.attr, |
| 3034 | &coresight_attr_cfg_dbgbus_clrc.attr.attr, |
| 3035 | &coresight_attr_cfg_dbgbus_loadivt.attr.attr, |
| 3036 | &coresight_attr_vbif_dbg_cntl.attr.attr, |
| 3037 | &coresight_attr_dbg_lo_hi_gpio.attr.attr, |
| 3038 | &coresight_attr_ext_trace_bus_cntl.attr.attr, |
| 3039 | &coresight_attr_read_ahb_through_dbg.attr.attr, |
| 3040 | &coresight_attr_cfg_dbgbus_trace_buf1.attr.attr, |
| 3041 | &coresight_attr_cfg_dbgbus_trace_buf2.attr.attr, |
| 3042 | &coresight_attr_evt_cfg.attr.attr, |
| 3043 | &coresight_attr_evt_intf_sel_0.attr.attr, |
| 3044 | &coresight_attr_evt_intf_sel_1.attr.attr, |
| 3045 | &coresight_attr_perf_atb_cfg.attr.attr, |
| 3046 | &coresight_attr_perf_atb_counter_sel_0.attr.attr, |
| 3047 | &coresight_attr_perf_atb_counter_sel_1.attr.attr, |
| 3048 | &coresight_attr_perf_atb_counter_sel_2.attr.attr, |
| 3049 | &coresight_attr_perf_atb_counter_sel_3.attr.attr, |
| 3050 | &coresight_attr_perf_atb_trig_intf_sel_0.attr.attr, |
| 3051 | &coresight_attr_perf_atb_trig_intf_sel_1.attr.attr, |
| 3052 | &coresight_attr_perf_atb_drain_cmd.attr.attr, |
| 3053 | &coresight_attr_eco_cntl.attr.attr, |
| 3054 | &coresight_attr_ahb_dbg_cntl.attr.attr, |
| 3055 | NULL, |
| 3056 | }; |
| 3057 | |
| 3058 | /*cx*/ |
| 3059 | static struct attribute *a6xx_coresight_attrs_cx[] = { |
| 3060 | &coresight_attr_cx_cfg_dbgbus_sel_a.attr.attr, |
| 3061 | &coresight_attr_cx_cfg_dbgbus_sel_b.attr.attr, |
| 3062 | &coresight_attr_cx_cfg_dbgbus_sel_c.attr.attr, |
| 3063 | &coresight_attr_cx_cfg_dbgbus_sel_d.attr.attr, |
| 3064 | &coresight_attr_cx_cfg_dbgbus_cntlt.attr.attr, |
| 3065 | &coresight_attr_cx_cfg_dbgbus_cntlm.attr.attr, |
| 3066 | &coresight_attr_cx_cfg_dbgbus_opl.attr.attr, |
| 3067 | &coresight_attr_cx_cfg_dbgbus_ope.attr.attr, |
| 3068 | &coresight_attr_cx_cfg_dbgbus_ivtl_0.attr.attr, |
| 3069 | &coresight_attr_cx_cfg_dbgbus_ivtl_1.attr.attr, |
| 3070 | &coresight_attr_cx_cfg_dbgbus_ivtl_2.attr.attr, |
| 3071 | &coresight_attr_cx_cfg_dbgbus_ivtl_3.attr.attr, |
| 3072 | &coresight_attr_cx_cfg_dbgbus_maskl_0.attr.attr, |
| 3073 | &coresight_attr_cx_cfg_dbgbus_maskl_1.attr.attr, |
| 3074 | &coresight_attr_cx_cfg_dbgbus_maskl_2.attr.attr, |
| 3075 | &coresight_attr_cx_cfg_dbgbus_maskl_3.attr.attr, |
| 3076 | &coresight_attr_cx_cfg_dbgbus_bytel_0.attr.attr, |
| 3077 | &coresight_attr_cx_cfg_dbgbus_bytel_1.attr.attr, |
| 3078 | &coresight_attr_cx_cfg_dbgbus_ivte_0.attr.attr, |
| 3079 | &coresight_attr_cx_cfg_dbgbus_ivte_1.attr.attr, |
| 3080 | &coresight_attr_cx_cfg_dbgbus_ivte_2.attr.attr, |
| 3081 | &coresight_attr_cx_cfg_dbgbus_ivte_3.attr.attr, |
| 3082 | &coresight_attr_cx_cfg_dbgbus_maske_0.attr.attr, |
| 3083 | &coresight_attr_cx_cfg_dbgbus_maske_1.attr.attr, |
| 3084 | &coresight_attr_cx_cfg_dbgbus_maske_2.attr.attr, |
| 3085 | &coresight_attr_cx_cfg_dbgbus_maske_3.attr.attr, |
| 3086 | &coresight_attr_cx_cfg_dbgbus_nibblee.attr.attr, |
| 3087 | &coresight_attr_cx_cfg_dbgbus_ptrc0.attr.attr, |
| 3088 | &coresight_attr_cx_cfg_dbgbus_ptrc1.attr.attr, |
| 3089 | &coresight_attr_cx_cfg_dbgbus_loadreg.attr.attr, |
| 3090 | &coresight_attr_cx_cfg_dbgbus_idx.attr.attr, |
| 3091 | &coresight_attr_cx_cfg_dbgbus_clrc.attr.attr, |
| 3092 | &coresight_attr_cx_cfg_dbgbus_loadivt.attr.attr, |
| 3093 | &coresight_attr_cx_vbif_dbg_cntl.attr.attr, |
| 3094 | &coresight_attr_cx_dbg_lo_hi_gpio.attr.attr, |
| 3095 | &coresight_attr_cx_ext_trace_bus_cntl.attr.attr, |
| 3096 | &coresight_attr_cx_read_ahb_through_dbg.attr.attr, |
| 3097 | &coresight_attr_cx_cfg_dbgbus_trace_buf1.attr.attr, |
| 3098 | &coresight_attr_cx_cfg_dbgbus_trace_buf2.attr.attr, |
| 3099 | &coresight_attr_cx_evt_cfg.attr.attr, |
| 3100 | &coresight_attr_cx_evt_intf_sel_0.attr.attr, |
| 3101 | &coresight_attr_cx_evt_intf_sel_1.attr.attr, |
| 3102 | &coresight_attr_cx_perf_atb_cfg.attr.attr, |
| 3103 | &coresight_attr_cx_perf_atb_counter_sel_0.attr.attr, |
| 3104 | &coresight_attr_cx_perf_atb_counter_sel_1.attr.attr, |
| 3105 | &coresight_attr_cx_perf_atb_counter_sel_2.attr.attr, |
| 3106 | &coresight_attr_cx_perf_atb_counter_sel_3.attr.attr, |
| 3107 | &coresight_attr_cx_perf_atb_trig_intf_sel_0.attr.attr, |
| 3108 | &coresight_attr_cx_perf_atb_trig_intf_sel_1.attr.attr, |
| 3109 | &coresight_attr_cx_perf_atb_drain_cmd.attr.attr, |
| 3110 | &coresight_attr_cx_eco_cntl.attr.attr, |
| 3111 | &coresight_attr_cx_ahb_dbg_cntl.attr.attr, |
| 3112 | NULL, |
| 3113 | }; |
| 3114 | |
| 3115 | static const struct attribute_group a6xx_coresight_group = { |
| 3116 | .attrs = a6xx_coresight_attrs, |
| 3117 | }; |
| 3118 | |
| 3119 | static const struct attribute_group *a6xx_coresight_groups[] = { |
| 3120 | &a6xx_coresight_group, |
| 3121 | NULL, |
| 3122 | }; |
| 3123 | |
| 3124 | static const struct attribute_group a6xx_coresight_group_cx = { |
| 3125 | .attrs = a6xx_coresight_attrs_cx, |
| 3126 | }; |
| 3127 | |
| 3128 | static const struct attribute_group *a6xx_coresight_groups_cx[] = { |
| 3129 | &a6xx_coresight_group_cx, |
| 3130 | NULL, |
| 3131 | }; |
| 3132 | |
| 3133 | static struct adreno_coresight a6xx_coresight = { |
| 3134 | .registers = a6xx_coresight_regs, |
| 3135 | .count = ARRAY_SIZE(a6xx_coresight_regs), |
| 3136 | .groups = a6xx_coresight_groups, |
| 3137 | }; |
| 3138 | |
| 3139 | static struct adreno_coresight a6xx_coresight_cx = { |
| 3140 | .registers = a6xx_coresight_regs_cx, |
| 3141 | .count = ARRAY_SIZE(a6xx_coresight_regs_cx), |
| 3142 | .groups = a6xx_coresight_groups_cx, |
| 3143 | }; |
| 3144 | |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3145 | static struct adreno_perfcount_register a6xx_perfcounters_cp[] = { |
| 3146 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_0_LO, |
| 3147 | A6XX_RBBM_PERFCTR_CP_0_HI, 0, A6XX_CP_PERFCTR_CP_SEL_0 }, |
| 3148 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_1_LO, |
| 3149 | A6XX_RBBM_PERFCTR_CP_1_HI, 1, A6XX_CP_PERFCTR_CP_SEL_1 }, |
| 3150 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_2_LO, |
| 3151 | A6XX_RBBM_PERFCTR_CP_2_HI, 2, A6XX_CP_PERFCTR_CP_SEL_2 }, |
| 3152 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_3_LO, |
| 3153 | A6XX_RBBM_PERFCTR_CP_3_HI, 3, A6XX_CP_PERFCTR_CP_SEL_3 }, |
| 3154 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_4_LO, |
| 3155 | A6XX_RBBM_PERFCTR_CP_4_HI, 4, A6XX_CP_PERFCTR_CP_SEL_4 }, |
| 3156 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_5_LO, |
| 3157 | A6XX_RBBM_PERFCTR_CP_5_HI, 5, A6XX_CP_PERFCTR_CP_SEL_5 }, |
| 3158 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_6_LO, |
| 3159 | A6XX_RBBM_PERFCTR_CP_6_HI, 6, A6XX_CP_PERFCTR_CP_SEL_6 }, |
| 3160 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_7_LO, |
| 3161 | A6XX_RBBM_PERFCTR_CP_7_HI, 7, A6XX_CP_PERFCTR_CP_SEL_7 }, |
| 3162 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_8_LO, |
| 3163 | A6XX_RBBM_PERFCTR_CP_8_HI, 8, A6XX_CP_PERFCTR_CP_SEL_8 }, |
| 3164 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_9_LO, |
| 3165 | A6XX_RBBM_PERFCTR_CP_9_HI, 9, A6XX_CP_PERFCTR_CP_SEL_9 }, |
| 3166 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_10_LO, |
| 3167 | A6XX_RBBM_PERFCTR_CP_10_HI, 10, A6XX_CP_PERFCTR_CP_SEL_10 }, |
| 3168 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_11_LO, |
| 3169 | A6XX_RBBM_PERFCTR_CP_11_HI, 11, A6XX_CP_PERFCTR_CP_SEL_11 }, |
| 3170 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_12_LO, |
| 3171 | A6XX_RBBM_PERFCTR_CP_12_HI, 12, A6XX_CP_PERFCTR_CP_SEL_12 }, |
| 3172 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CP_13_LO, |
| 3173 | A6XX_RBBM_PERFCTR_CP_13_HI, 13, A6XX_CP_PERFCTR_CP_SEL_13 }, |
| 3174 | }; |
| 3175 | |
| 3176 | static struct adreno_perfcount_register a6xx_perfcounters_rbbm[] = { |
| 3177 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RBBM_0_LO, |
| 3178 | A6XX_RBBM_PERFCTR_RBBM_0_HI, 15, A6XX_RBBM_PERFCTR_RBBM_SEL_0 }, |
| 3179 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RBBM_1_LO, |
| 3180 | A6XX_RBBM_PERFCTR_RBBM_1_HI, 15, A6XX_RBBM_PERFCTR_RBBM_SEL_1 }, |
| 3181 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RBBM_2_LO, |
| 3182 | A6XX_RBBM_PERFCTR_RBBM_2_HI, 16, A6XX_RBBM_PERFCTR_RBBM_SEL_2 }, |
| 3183 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RBBM_3_LO, |
| 3184 | A6XX_RBBM_PERFCTR_RBBM_3_HI, 17, A6XX_RBBM_PERFCTR_RBBM_SEL_3 }, |
| 3185 | }; |
| 3186 | |
| 3187 | static struct adreno_perfcount_register a6xx_perfcounters_pc[] = { |
| 3188 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_PC_0_LO, |
| 3189 | A6XX_RBBM_PERFCTR_PC_0_HI, 18, A6XX_PC_PERFCTR_PC_SEL_0 }, |
| 3190 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_PC_1_LO, |
| 3191 | A6XX_RBBM_PERFCTR_PC_1_HI, 19, A6XX_PC_PERFCTR_PC_SEL_1 }, |
| 3192 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_PC_2_LO, |
| 3193 | A6XX_RBBM_PERFCTR_PC_2_HI, 20, A6XX_PC_PERFCTR_PC_SEL_2 }, |
| 3194 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_PC_3_LO, |
| 3195 | A6XX_RBBM_PERFCTR_PC_3_HI, 21, A6XX_PC_PERFCTR_PC_SEL_3 }, |
| 3196 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_PC_4_LO, |
| 3197 | A6XX_RBBM_PERFCTR_PC_4_HI, 22, A6XX_PC_PERFCTR_PC_SEL_4 }, |
| 3198 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_PC_5_LO, |
| 3199 | A6XX_RBBM_PERFCTR_PC_5_HI, 23, A6XX_PC_PERFCTR_PC_SEL_5 }, |
| 3200 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_PC_6_LO, |
| 3201 | A6XX_RBBM_PERFCTR_PC_6_HI, 24, A6XX_PC_PERFCTR_PC_SEL_6 }, |
| 3202 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_PC_7_LO, |
| 3203 | A6XX_RBBM_PERFCTR_PC_7_HI, 25, A6XX_PC_PERFCTR_PC_SEL_7 }, |
| 3204 | }; |
| 3205 | |
| 3206 | static struct adreno_perfcount_register a6xx_perfcounters_vfd[] = { |
| 3207 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VFD_0_LO, |
| 3208 | A6XX_RBBM_PERFCTR_VFD_0_HI, 26, A6XX_VFD_PERFCTR_VFD_SEL_0 }, |
| 3209 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VFD_1_LO, |
| 3210 | A6XX_RBBM_PERFCTR_VFD_1_HI, 27, A6XX_VFD_PERFCTR_VFD_SEL_1 }, |
| 3211 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VFD_2_LO, |
| 3212 | A6XX_RBBM_PERFCTR_VFD_2_HI, 28, A6XX_VFD_PERFCTR_VFD_SEL_2 }, |
| 3213 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VFD_3_LO, |
| 3214 | A6XX_RBBM_PERFCTR_VFD_3_HI, 29, A6XX_VFD_PERFCTR_VFD_SEL_3 }, |
| 3215 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VFD_4_LO, |
| 3216 | A6XX_RBBM_PERFCTR_VFD_4_HI, 30, A6XX_VFD_PERFCTR_VFD_SEL_4 }, |
| 3217 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VFD_5_LO, |
| 3218 | A6XX_RBBM_PERFCTR_VFD_5_HI, 31, A6XX_VFD_PERFCTR_VFD_SEL_5 }, |
| 3219 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VFD_6_LO, |
| 3220 | A6XX_RBBM_PERFCTR_VFD_6_HI, 32, A6XX_VFD_PERFCTR_VFD_SEL_6 }, |
| 3221 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VFD_7_LO, |
| 3222 | A6XX_RBBM_PERFCTR_VFD_7_HI, 33, A6XX_VFD_PERFCTR_VFD_SEL_7 }, |
| 3223 | }; |
| 3224 | |
| 3225 | static struct adreno_perfcount_register a6xx_perfcounters_hlsq[] = { |
| 3226 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_HLSQ_0_LO, |
| 3227 | A6XX_RBBM_PERFCTR_HLSQ_0_HI, 34, A6XX_HLSQ_PERFCTR_HLSQ_SEL_0 }, |
| 3228 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_HLSQ_1_LO, |
| 3229 | A6XX_RBBM_PERFCTR_HLSQ_1_HI, 35, A6XX_HLSQ_PERFCTR_HLSQ_SEL_1 }, |
| 3230 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_HLSQ_2_LO, |
| 3231 | A6XX_RBBM_PERFCTR_HLSQ_2_HI, 36, A6XX_HLSQ_PERFCTR_HLSQ_SEL_2 }, |
| 3232 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_HLSQ_3_LO, |
| 3233 | A6XX_RBBM_PERFCTR_HLSQ_3_HI, 37, A6XX_HLSQ_PERFCTR_HLSQ_SEL_3 }, |
| 3234 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_HLSQ_4_LO, |
| 3235 | A6XX_RBBM_PERFCTR_HLSQ_4_HI, 38, A6XX_HLSQ_PERFCTR_HLSQ_SEL_4 }, |
| 3236 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_HLSQ_5_LO, |
| 3237 | A6XX_RBBM_PERFCTR_HLSQ_5_HI, 39, A6XX_HLSQ_PERFCTR_HLSQ_SEL_5 }, |
| 3238 | }; |
| 3239 | |
| 3240 | static struct adreno_perfcount_register a6xx_perfcounters_vpc[] = { |
| 3241 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VPC_0_LO, |
| 3242 | A6XX_RBBM_PERFCTR_VPC_0_HI, 40, A6XX_VPC_PERFCTR_VPC_SEL_0 }, |
| 3243 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VPC_1_LO, |
| 3244 | A6XX_RBBM_PERFCTR_VPC_1_HI, 41, A6XX_VPC_PERFCTR_VPC_SEL_1 }, |
| 3245 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VPC_2_LO, |
| 3246 | A6XX_RBBM_PERFCTR_VPC_2_HI, 42, A6XX_VPC_PERFCTR_VPC_SEL_2 }, |
| 3247 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VPC_3_LO, |
| 3248 | A6XX_RBBM_PERFCTR_VPC_3_HI, 43, A6XX_VPC_PERFCTR_VPC_SEL_3 }, |
| 3249 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VPC_4_LO, |
| 3250 | A6XX_RBBM_PERFCTR_VPC_4_HI, 44, A6XX_VPC_PERFCTR_VPC_SEL_4 }, |
| 3251 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VPC_5_LO, |
| 3252 | A6XX_RBBM_PERFCTR_VPC_5_HI, 45, A6XX_VPC_PERFCTR_VPC_SEL_5 }, |
| 3253 | }; |
| 3254 | |
| 3255 | static struct adreno_perfcount_register a6xx_perfcounters_ccu[] = { |
| 3256 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CCU_0_LO, |
| 3257 | A6XX_RBBM_PERFCTR_CCU_0_HI, 46, A6XX_RB_PERFCTR_CCU_SEL_0 }, |
| 3258 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CCU_1_LO, |
| 3259 | A6XX_RBBM_PERFCTR_CCU_1_HI, 47, A6XX_RB_PERFCTR_CCU_SEL_1 }, |
| 3260 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CCU_2_LO, |
| 3261 | A6XX_RBBM_PERFCTR_CCU_2_HI, 48, A6XX_RB_PERFCTR_CCU_SEL_2 }, |
| 3262 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CCU_3_LO, |
| 3263 | A6XX_RBBM_PERFCTR_CCU_3_HI, 49, A6XX_RB_PERFCTR_CCU_SEL_3 }, |
| 3264 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CCU_4_LO, |
| 3265 | A6XX_RBBM_PERFCTR_CCU_4_HI, 50, A6XX_RB_PERFCTR_CCU_SEL_4 }, |
| 3266 | }; |
| 3267 | |
| 3268 | static struct adreno_perfcount_register a6xx_perfcounters_tse[] = { |
| 3269 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TSE_0_LO, |
| 3270 | A6XX_RBBM_PERFCTR_TSE_0_HI, 51, A6XX_GRAS_PERFCTR_TSE_SEL_0 }, |
| 3271 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TSE_1_LO, |
| 3272 | A6XX_RBBM_PERFCTR_TSE_1_HI, 52, A6XX_GRAS_PERFCTR_TSE_SEL_1 }, |
| 3273 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TSE_2_LO, |
| 3274 | A6XX_RBBM_PERFCTR_TSE_2_HI, 53, A6XX_GRAS_PERFCTR_TSE_SEL_2 }, |
| 3275 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TSE_3_LO, |
| 3276 | A6XX_RBBM_PERFCTR_TSE_3_HI, 54, A6XX_GRAS_PERFCTR_TSE_SEL_3 }, |
| 3277 | }; |
| 3278 | |
| 3279 | static struct adreno_perfcount_register a6xx_perfcounters_ras[] = { |
| 3280 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RAS_0_LO, |
| 3281 | A6XX_RBBM_PERFCTR_RAS_0_HI, 55, A6XX_GRAS_PERFCTR_RAS_SEL_0 }, |
| 3282 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RAS_1_LO, |
| 3283 | A6XX_RBBM_PERFCTR_RAS_1_HI, 56, A6XX_GRAS_PERFCTR_RAS_SEL_1 }, |
| 3284 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RAS_2_LO, |
| 3285 | A6XX_RBBM_PERFCTR_RAS_2_HI, 57, A6XX_GRAS_PERFCTR_RAS_SEL_2 }, |
| 3286 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RAS_3_LO, |
| 3287 | A6XX_RBBM_PERFCTR_RAS_3_HI, 58, A6XX_GRAS_PERFCTR_RAS_SEL_3 }, |
| 3288 | }; |
| 3289 | |
| 3290 | static struct adreno_perfcount_register a6xx_perfcounters_uche[] = { |
| 3291 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_0_LO, |
| 3292 | A6XX_RBBM_PERFCTR_UCHE_0_HI, 59, A6XX_UCHE_PERFCTR_UCHE_SEL_0 }, |
| 3293 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_1_LO, |
| 3294 | A6XX_RBBM_PERFCTR_UCHE_1_HI, 60, A6XX_UCHE_PERFCTR_UCHE_SEL_1 }, |
| 3295 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_2_LO, |
| 3296 | A6XX_RBBM_PERFCTR_UCHE_2_HI, 61, A6XX_UCHE_PERFCTR_UCHE_SEL_2 }, |
| 3297 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_3_LO, |
| 3298 | A6XX_RBBM_PERFCTR_UCHE_3_HI, 62, A6XX_UCHE_PERFCTR_UCHE_SEL_3 }, |
| 3299 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_4_LO, |
| 3300 | A6XX_RBBM_PERFCTR_UCHE_4_HI, 63, A6XX_UCHE_PERFCTR_UCHE_SEL_4 }, |
| 3301 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_5_LO, |
| 3302 | A6XX_RBBM_PERFCTR_UCHE_5_HI, 64, A6XX_UCHE_PERFCTR_UCHE_SEL_5 }, |
| 3303 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_6_LO, |
| 3304 | A6XX_RBBM_PERFCTR_UCHE_6_HI, 65, A6XX_UCHE_PERFCTR_UCHE_SEL_6 }, |
| 3305 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_7_LO, |
| 3306 | A6XX_RBBM_PERFCTR_UCHE_7_HI, 66, A6XX_UCHE_PERFCTR_UCHE_SEL_7 }, |
| 3307 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_8_LO, |
| 3308 | A6XX_RBBM_PERFCTR_UCHE_8_HI, 67, A6XX_UCHE_PERFCTR_UCHE_SEL_8 }, |
| 3309 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_9_LO, |
| 3310 | A6XX_RBBM_PERFCTR_UCHE_9_HI, 68, A6XX_UCHE_PERFCTR_UCHE_SEL_9 }, |
| 3311 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_10_LO, |
| 3312 | A6XX_RBBM_PERFCTR_UCHE_10_HI, 69, |
| 3313 | A6XX_UCHE_PERFCTR_UCHE_SEL_10 }, |
| 3314 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_UCHE_11_LO, |
| 3315 | A6XX_RBBM_PERFCTR_UCHE_11_HI, 70, |
| 3316 | A6XX_UCHE_PERFCTR_UCHE_SEL_11 }, |
| 3317 | }; |
| 3318 | |
| 3319 | static struct adreno_perfcount_register a6xx_perfcounters_tp[] = { |
| 3320 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_0_LO, |
| 3321 | A6XX_RBBM_PERFCTR_TP_0_HI, 71, A6XX_TPL1_PERFCTR_TP_SEL_0 }, |
| 3322 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_1_LO, |
| 3323 | A6XX_RBBM_PERFCTR_TP_1_HI, 72, A6XX_TPL1_PERFCTR_TP_SEL_1 }, |
| 3324 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_2_LO, |
| 3325 | A6XX_RBBM_PERFCTR_TP_2_HI, 73, A6XX_TPL1_PERFCTR_TP_SEL_2 }, |
| 3326 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_3_LO, |
| 3327 | A6XX_RBBM_PERFCTR_TP_3_HI, 74, A6XX_TPL1_PERFCTR_TP_SEL_3 }, |
| 3328 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_4_LO, |
| 3329 | A6XX_RBBM_PERFCTR_TP_4_HI, 75, A6XX_TPL1_PERFCTR_TP_SEL_4 }, |
| 3330 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_5_LO, |
| 3331 | A6XX_RBBM_PERFCTR_TP_5_HI, 76, A6XX_TPL1_PERFCTR_TP_SEL_5 }, |
| 3332 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_6_LO, |
| 3333 | A6XX_RBBM_PERFCTR_TP_6_HI, 77, A6XX_TPL1_PERFCTR_TP_SEL_6 }, |
| 3334 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_7_LO, |
| 3335 | A6XX_RBBM_PERFCTR_TP_7_HI, 78, A6XX_TPL1_PERFCTR_TP_SEL_7 }, |
| 3336 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_8_LO, |
| 3337 | A6XX_RBBM_PERFCTR_TP_8_HI, 79, A6XX_TPL1_PERFCTR_TP_SEL_8 }, |
| 3338 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_9_LO, |
| 3339 | A6XX_RBBM_PERFCTR_TP_9_HI, 80, A6XX_TPL1_PERFCTR_TP_SEL_9 }, |
| 3340 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_10_LO, |
| 3341 | A6XX_RBBM_PERFCTR_TP_10_HI, 81, A6XX_TPL1_PERFCTR_TP_SEL_10 }, |
| 3342 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_TP_11_LO, |
| 3343 | A6XX_RBBM_PERFCTR_TP_11_HI, 82, A6XX_TPL1_PERFCTR_TP_SEL_11 }, |
| 3344 | }; |
| 3345 | |
| 3346 | static struct adreno_perfcount_register a6xx_perfcounters_sp[] = { |
| 3347 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_0_LO, |
| 3348 | A6XX_RBBM_PERFCTR_SP_0_HI, 83, A6XX_SP_PERFCTR_SP_SEL_0 }, |
| 3349 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_1_LO, |
| 3350 | A6XX_RBBM_PERFCTR_SP_1_HI, 84, A6XX_SP_PERFCTR_SP_SEL_1 }, |
| 3351 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_2_LO, |
| 3352 | A6XX_RBBM_PERFCTR_SP_2_HI, 85, A6XX_SP_PERFCTR_SP_SEL_2 }, |
| 3353 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_3_LO, |
| 3354 | A6XX_RBBM_PERFCTR_SP_3_HI, 86, A6XX_SP_PERFCTR_SP_SEL_3 }, |
| 3355 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_4_LO, |
| 3356 | A6XX_RBBM_PERFCTR_SP_4_HI, 87, A6XX_SP_PERFCTR_SP_SEL_4 }, |
| 3357 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_5_LO, |
| 3358 | A6XX_RBBM_PERFCTR_SP_5_HI, 88, A6XX_SP_PERFCTR_SP_SEL_5 }, |
| 3359 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_6_LO, |
| 3360 | A6XX_RBBM_PERFCTR_SP_6_HI, 89, A6XX_SP_PERFCTR_SP_SEL_6 }, |
| 3361 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_7_LO, |
| 3362 | A6XX_RBBM_PERFCTR_SP_7_HI, 90, A6XX_SP_PERFCTR_SP_SEL_7 }, |
| 3363 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_8_LO, |
| 3364 | A6XX_RBBM_PERFCTR_SP_8_HI, 91, A6XX_SP_PERFCTR_SP_SEL_8 }, |
| 3365 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_9_LO, |
| 3366 | A6XX_RBBM_PERFCTR_SP_9_HI, 92, A6XX_SP_PERFCTR_SP_SEL_9 }, |
| 3367 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_10_LO, |
| 3368 | A6XX_RBBM_PERFCTR_SP_10_HI, 93, A6XX_SP_PERFCTR_SP_SEL_10 }, |
| 3369 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_11_LO, |
| 3370 | A6XX_RBBM_PERFCTR_SP_11_HI, 94, A6XX_SP_PERFCTR_SP_SEL_11 }, |
| 3371 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_12_LO, |
| 3372 | A6XX_RBBM_PERFCTR_SP_12_HI, 95, A6XX_SP_PERFCTR_SP_SEL_12 }, |
| 3373 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_13_LO, |
| 3374 | A6XX_RBBM_PERFCTR_SP_13_HI, 96, A6XX_SP_PERFCTR_SP_SEL_13 }, |
| 3375 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_14_LO, |
| 3376 | A6XX_RBBM_PERFCTR_SP_14_HI, 97, A6XX_SP_PERFCTR_SP_SEL_14 }, |
| 3377 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_15_LO, |
| 3378 | A6XX_RBBM_PERFCTR_SP_15_HI, 98, A6XX_SP_PERFCTR_SP_SEL_15 }, |
| 3379 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_16_LO, |
| 3380 | A6XX_RBBM_PERFCTR_SP_16_HI, 99, A6XX_SP_PERFCTR_SP_SEL_16 }, |
| 3381 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_17_LO, |
| 3382 | A6XX_RBBM_PERFCTR_SP_17_HI, 100, A6XX_SP_PERFCTR_SP_SEL_17 }, |
| 3383 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_18_LO, |
| 3384 | A6XX_RBBM_PERFCTR_SP_18_HI, 101, A6XX_SP_PERFCTR_SP_SEL_18 }, |
| 3385 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_19_LO, |
| 3386 | A6XX_RBBM_PERFCTR_SP_19_HI, 102, A6XX_SP_PERFCTR_SP_SEL_19 }, |
| 3387 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_20_LO, |
| 3388 | A6XX_RBBM_PERFCTR_SP_20_HI, 103, A6XX_SP_PERFCTR_SP_SEL_20 }, |
| 3389 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_21_LO, |
| 3390 | A6XX_RBBM_PERFCTR_SP_21_HI, 104, A6XX_SP_PERFCTR_SP_SEL_21 }, |
| 3391 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_22_LO, |
| 3392 | A6XX_RBBM_PERFCTR_SP_22_HI, 105, A6XX_SP_PERFCTR_SP_SEL_22 }, |
| 3393 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_SP_23_LO, |
| 3394 | A6XX_RBBM_PERFCTR_SP_23_HI, 106, A6XX_SP_PERFCTR_SP_SEL_23 }, |
| 3395 | }; |
| 3396 | |
| 3397 | static struct adreno_perfcount_register a6xx_perfcounters_rb[] = { |
| 3398 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RB_0_LO, |
| 3399 | A6XX_RBBM_PERFCTR_RB_0_HI, 107, A6XX_RB_PERFCTR_RB_SEL_0 }, |
| 3400 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RB_1_LO, |
| 3401 | A6XX_RBBM_PERFCTR_RB_1_HI, 108, A6XX_RB_PERFCTR_RB_SEL_1 }, |
| 3402 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RB_2_LO, |
| 3403 | A6XX_RBBM_PERFCTR_RB_2_HI, 109, A6XX_RB_PERFCTR_RB_SEL_2 }, |
| 3404 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RB_3_LO, |
| 3405 | A6XX_RBBM_PERFCTR_RB_3_HI, 110, A6XX_RB_PERFCTR_RB_SEL_3 }, |
| 3406 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RB_4_LO, |
| 3407 | A6XX_RBBM_PERFCTR_RB_4_HI, 111, A6XX_RB_PERFCTR_RB_SEL_4 }, |
| 3408 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RB_5_LO, |
| 3409 | A6XX_RBBM_PERFCTR_RB_5_HI, 112, A6XX_RB_PERFCTR_RB_SEL_5 }, |
| 3410 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RB_6_LO, |
| 3411 | A6XX_RBBM_PERFCTR_RB_6_HI, 113, A6XX_RB_PERFCTR_RB_SEL_6 }, |
| 3412 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_RB_7_LO, |
| 3413 | A6XX_RBBM_PERFCTR_RB_7_HI, 114, A6XX_RB_PERFCTR_RB_SEL_7 }, |
| 3414 | }; |
| 3415 | |
| 3416 | static struct adreno_perfcount_register a6xx_perfcounters_vsc[] = { |
| 3417 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VSC_0_LO, |
| 3418 | A6XX_RBBM_PERFCTR_VSC_0_HI, 115, A6XX_VSC_PERFCTR_VSC_SEL_0 }, |
| 3419 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_VSC_1_LO, |
| 3420 | A6XX_RBBM_PERFCTR_VSC_1_HI, 116, A6XX_VSC_PERFCTR_VSC_SEL_1 }, |
| 3421 | }; |
| 3422 | |
| 3423 | static struct adreno_perfcount_register a6xx_perfcounters_lrz[] = { |
| 3424 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_LRZ_0_LO, |
| 3425 | A6XX_RBBM_PERFCTR_LRZ_0_HI, 117, A6XX_GRAS_PERFCTR_LRZ_SEL_0 }, |
| 3426 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_LRZ_1_LO, |
| 3427 | A6XX_RBBM_PERFCTR_LRZ_1_HI, 118, A6XX_GRAS_PERFCTR_LRZ_SEL_1 }, |
| 3428 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_LRZ_2_LO, |
| 3429 | A6XX_RBBM_PERFCTR_LRZ_2_HI, 119, A6XX_GRAS_PERFCTR_LRZ_SEL_2 }, |
| 3430 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_LRZ_3_LO, |
| 3431 | A6XX_RBBM_PERFCTR_LRZ_3_HI, 120, A6XX_GRAS_PERFCTR_LRZ_SEL_3 }, |
| 3432 | }; |
| 3433 | |
| 3434 | static struct adreno_perfcount_register a6xx_perfcounters_cmp[] = { |
| 3435 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CMP_0_LO, |
| 3436 | A6XX_RBBM_PERFCTR_CMP_0_HI, 121, A6XX_RB_PERFCTR_CMP_SEL_0 }, |
| 3437 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CMP_1_LO, |
| 3438 | A6XX_RBBM_PERFCTR_CMP_1_HI, 122, A6XX_RB_PERFCTR_CMP_SEL_1 }, |
| 3439 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CMP_2_LO, |
| 3440 | A6XX_RBBM_PERFCTR_CMP_2_HI, 123, A6XX_RB_PERFCTR_CMP_SEL_2 }, |
| 3441 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_RBBM_PERFCTR_CMP_3_LO, |
| 3442 | A6XX_RBBM_PERFCTR_CMP_3_HI, 124, A6XX_RB_PERFCTR_CMP_SEL_3 }, |
| 3443 | }; |
| 3444 | |
| 3445 | static struct adreno_perfcount_register a6xx_perfcounters_vbif[] = { |
| 3446 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_VBIF_PERF_CNT_LOW0, |
| 3447 | A6XX_VBIF_PERF_CNT_HIGH0, -1, A6XX_VBIF_PERF_CNT_SEL0 }, |
| 3448 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_VBIF_PERF_CNT_LOW1, |
| 3449 | A6XX_VBIF_PERF_CNT_HIGH1, -1, A6XX_VBIF_PERF_CNT_SEL1 }, |
| 3450 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_VBIF_PERF_CNT_LOW2, |
| 3451 | A6XX_VBIF_PERF_CNT_HIGH2, -1, A6XX_VBIF_PERF_CNT_SEL2 }, |
| 3452 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_VBIF_PERF_CNT_LOW3, |
| 3453 | A6XX_VBIF_PERF_CNT_HIGH3, -1, A6XX_VBIF_PERF_CNT_SEL3 }, |
| 3454 | }; |
| 3455 | |
| 3456 | static struct adreno_perfcount_register a6xx_perfcounters_vbif_pwr[] = { |
| 3457 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_VBIF_PERF_PWR_CNT_LOW0, |
| 3458 | A6XX_VBIF_PERF_PWR_CNT_HIGH0, -1, A6XX_VBIF_PERF_PWR_CNT_EN0 }, |
| 3459 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_VBIF_PERF_PWR_CNT_LOW1, |
| 3460 | A6XX_VBIF_PERF_PWR_CNT_HIGH1, -1, A6XX_VBIF_PERF_PWR_CNT_EN1 }, |
| 3461 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_VBIF_PERF_PWR_CNT_LOW2, |
| 3462 | A6XX_VBIF_PERF_PWR_CNT_HIGH2, -1, A6XX_VBIF_PERF_PWR_CNT_EN2 }, |
| 3463 | }; |
| 3464 | |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 3465 | |
| 3466 | static struct adreno_perfcount_register a6xx_perfcounters_gbif[] = { |
| 3467 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_GBIF_PERF_CNT_LOW0, |
| 3468 | A6XX_GBIF_PERF_CNT_HIGH0, -1, A6XX_GBIF_PERF_CNT_SEL }, |
| 3469 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_GBIF_PERF_CNT_LOW1, |
| 3470 | A6XX_GBIF_PERF_CNT_HIGH1, -1, A6XX_GBIF_PERF_CNT_SEL }, |
| 3471 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_GBIF_PERF_CNT_LOW2, |
| 3472 | A6XX_GBIF_PERF_CNT_HIGH2, -1, A6XX_GBIF_PERF_CNT_SEL }, |
| 3473 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_GBIF_PERF_CNT_LOW3, |
| 3474 | A6XX_GBIF_PERF_CNT_HIGH3, -1, A6XX_GBIF_PERF_CNT_SEL }, |
| 3475 | }; |
| 3476 | |
| 3477 | static struct adreno_perfcount_register a6xx_perfcounters_gbif_pwr[] = { |
| 3478 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_GBIF_PWR_CNT_LOW0, |
| 3479 | A6XX_GBIF_PWR_CNT_HIGH0, -1, A6XX_GBIF_PERF_PWR_CNT_EN }, |
| 3480 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_GBIF_PWR_CNT_LOW1, |
| 3481 | A6XX_GBIF_PWR_CNT_HIGH1, -1, A6XX_GBIF_PERF_PWR_CNT_EN }, |
| 3482 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_GBIF_PWR_CNT_LOW2, |
| 3483 | A6XX_GBIF_PWR_CNT_HIGH2, -1, A6XX_GBIF_PERF_PWR_CNT_EN }, |
| 3484 | }; |
| 3485 | |
Lynus Vaz | 856ca60 | 2017-05-24 16:56:36 +0530 | [diff] [blame] | 3486 | static struct adreno_perfcount_register a6xx_perfcounters_pwr[] = { |
| 3487 | { KGSL_PERFCOUNTER_BROKEN, 0, 0, 0, 0, -1, 0 }, |
| 3488 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, |
| 3489 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, |
| 3490 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H, -1, 0 }, |
| 3491 | }; |
| 3492 | |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3493 | static struct adreno_perfcount_register a6xx_perfcounters_alwayson[] = { |
| 3494 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, A6XX_CP_ALWAYS_ON_COUNTER_LO, |
| 3495 | A6XX_CP_ALWAYS_ON_COUNTER_HI, -1 }, |
| 3496 | }; |
| 3497 | |
Lynus Vaz | 4fc97e2 | 2017-06-01 20:03:35 +0530 | [diff] [blame] | 3498 | static struct adreno_perfcount_register a6xx_pwrcounters_gpmu[] = { |
| 3499 | /* |
| 3500 | * A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0 is used for the GPU |
| 3501 | * busy count (see the PWR group above). Mark it as broken |
| 3502 | * so it's not re-used. |
| 3503 | */ |
| 3504 | { KGSL_PERFCOUNTER_BROKEN, 0, 0, |
| 3505 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_L, |
| 3506 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_0_H, -1, |
| 3507 | A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, }, |
| 3508 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, |
| 3509 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_L, |
| 3510 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_1_H, -1, |
| 3511 | A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, }, |
| 3512 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, |
| 3513 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_L, |
| 3514 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_2_H, -1, |
| 3515 | A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, }, |
| 3516 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, |
| 3517 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_L, |
| 3518 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_3_H, -1, |
| 3519 | A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, }, |
| 3520 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, |
| 3521 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_L, |
| 3522 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_4_H, -1, |
| 3523 | A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, }, |
| 3524 | { KGSL_PERFCOUNTER_NOT_USED, 0, 0, |
| 3525 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_L, |
| 3526 | A6XX_GMU_CX_GMU_POWER_COUNTER_XOCLK_5_H, -1, |
| 3527 | A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_1, }, |
| 3528 | }; |
| 3529 | |
Tarun Karra | 1382e51 | 2017-10-30 19:41:25 -0700 | [diff] [blame] | 3530 | /* |
| 3531 | * ADRENO_PERFCOUNTER_GROUP_RESTORE flag is enabled by default |
| 3532 | * because most of the perfcounter groups need to be restored |
| 3533 | * as part of preemption and IFPC. Perfcounter groups that are |
| 3534 | * not restored as part of preemption and IFPC should be defined |
| 3535 | * using A6XX_PERFCOUNTER_GROUP_FLAGS macro |
| 3536 | */ |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3537 | #define A6XX_PERFCOUNTER_GROUP(offset, name) \ |
Tarun Karra | 1382e51 | 2017-10-30 19:41:25 -0700 | [diff] [blame] | 3538 | ADRENO_PERFCOUNTER_GROUP_FLAGS(a6xx, offset, name, \ |
| 3539 | ADRENO_PERFCOUNTER_GROUP_RESTORE) |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3540 | |
| 3541 | #define A6XX_PERFCOUNTER_GROUP_FLAGS(offset, name, flags) \ |
| 3542 | ADRENO_PERFCOUNTER_GROUP_FLAGS(a6xx, offset, name, flags) |
| 3543 | |
Lynus Vaz | 4fc97e2 | 2017-06-01 20:03:35 +0530 | [diff] [blame] | 3544 | #define A6XX_POWER_COUNTER_GROUP(offset, name) \ |
| 3545 | ADRENO_POWER_COUNTER_GROUP(a6xx, offset, name) |
| 3546 | |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3547 | static struct adreno_perfcount_group a6xx_perfcounter_groups |
| 3548 | [KGSL_PERFCOUNTER_GROUP_MAX] = { |
| 3549 | A6XX_PERFCOUNTER_GROUP(CP, cp), |
Tarun Karra | 1382e51 | 2017-10-30 19:41:25 -0700 | [diff] [blame] | 3550 | A6XX_PERFCOUNTER_GROUP_FLAGS(RBBM, rbbm, 0), |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3551 | A6XX_PERFCOUNTER_GROUP(PC, pc), |
| 3552 | A6XX_PERFCOUNTER_GROUP(VFD, vfd), |
| 3553 | A6XX_PERFCOUNTER_GROUP(HLSQ, hlsq), |
| 3554 | A6XX_PERFCOUNTER_GROUP(VPC, vpc), |
| 3555 | A6XX_PERFCOUNTER_GROUP(CCU, ccu), |
| 3556 | A6XX_PERFCOUNTER_GROUP(CMP, cmp), |
| 3557 | A6XX_PERFCOUNTER_GROUP(TSE, tse), |
| 3558 | A6XX_PERFCOUNTER_GROUP(RAS, ras), |
| 3559 | A6XX_PERFCOUNTER_GROUP(LRZ, lrz), |
| 3560 | A6XX_PERFCOUNTER_GROUP(UCHE, uche), |
| 3561 | A6XX_PERFCOUNTER_GROUP(TP, tp), |
| 3562 | A6XX_PERFCOUNTER_GROUP(SP, sp), |
| 3563 | A6XX_PERFCOUNTER_GROUP(RB, rb), |
| 3564 | A6XX_PERFCOUNTER_GROUP(VSC, vsc), |
Tarun Karra | 1382e51 | 2017-10-30 19:41:25 -0700 | [diff] [blame] | 3565 | A6XX_PERFCOUNTER_GROUP_FLAGS(VBIF, vbif, 0), |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3566 | A6XX_PERFCOUNTER_GROUP_FLAGS(VBIF_PWR, vbif_pwr, |
| 3567 | ADRENO_PERFCOUNTER_GROUP_FIXED), |
Lynus Vaz | 856ca60 | 2017-05-24 16:56:36 +0530 | [diff] [blame] | 3568 | A6XX_PERFCOUNTER_GROUP_FLAGS(PWR, pwr, |
| 3569 | ADRENO_PERFCOUNTER_GROUP_FIXED), |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3570 | A6XX_PERFCOUNTER_GROUP_FLAGS(ALWAYSON, alwayson, |
| 3571 | ADRENO_PERFCOUNTER_GROUP_FIXED), |
Lynus Vaz | 4fc97e2 | 2017-06-01 20:03:35 +0530 | [diff] [blame] | 3572 | A6XX_POWER_COUNTER_GROUP(GPMU, gpmu), |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3573 | }; |
| 3574 | |
| 3575 | static struct adreno_perfcounters a6xx_perfcounters = { |
| 3576 | a6xx_perfcounter_groups, |
| 3577 | ARRAY_SIZE(a6xx_perfcounter_groups), |
| 3578 | }; |
| 3579 | |
Lynus Vaz | 856ca60 | 2017-05-24 16:56:36 +0530 | [diff] [blame] | 3580 | /* Program the GMU power counter to count GPU busy cycles */ |
| 3581 | static int a6xx_enable_pwr_counters(struct adreno_device *adreno_dev, |
| 3582 | unsigned int counter) |
| 3583 | { |
| 3584 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 3585 | |
| 3586 | /* |
| 3587 | * We have a limited number of power counters. Since we're not using |
| 3588 | * total GPU cycle count, return error if requested. |
| 3589 | */ |
| 3590 | if (counter == 0) |
| 3591 | return -EINVAL; |
| 3592 | |
| 3593 | if (!device->gmu.pdev) |
| 3594 | return -ENODEV; |
| 3595 | |
Kyle Piefer | 50af7d0 | 2017-07-25 11:00:17 -0700 | [diff] [blame] | 3596 | kgsl_regwrite(device, A6XX_GPU_GMU_AO_GPU_CX_BUSY_MASK, 0xFF000000); |
Lynus Vaz | 856ca60 | 2017-05-24 16:56:36 +0530 | [diff] [blame] | 3597 | kgsl_regrmw(device, |
Kyle Piefer | 50af7d0 | 2017-07-25 11:00:17 -0700 | [diff] [blame] | 3598 | A6XX_GMU_CX_GMU_POWER_COUNTER_SELECT_0, 0xFF, 0x20); |
Lynus Vaz | 856ca60 | 2017-05-24 16:56:36 +0530 | [diff] [blame] | 3599 | kgsl_regwrite(device, A6XX_GMU_CX_GMU_POWER_COUNTER_ENABLE, 0x1); |
| 3600 | |
| 3601 | return 0; |
| 3602 | } |
| 3603 | |
Rajesh Kemisetti | 10bbec9 | 2017-10-20 10:55:58 +0530 | [diff] [blame] | 3604 | static void a6xx_efuse_speed_bin(struct adreno_device *adreno_dev) |
| 3605 | { |
| 3606 | unsigned int val; |
| 3607 | unsigned int speed_bin[3]; |
| 3608 | struct kgsl_device *device = &adreno_dev->dev; |
| 3609 | |
| 3610 | if (of_property_read_u32_array(device->pdev->dev.of_node, |
| 3611 | "qcom,gpu-speed-bin", speed_bin, 3)) |
| 3612 | return; |
| 3613 | |
| 3614 | adreno_efuse_read_u32(adreno_dev, speed_bin[0], &val); |
| 3615 | |
| 3616 | adreno_dev->speed_bin = (val & speed_bin[1]) >> speed_bin[2]; |
| 3617 | } |
| 3618 | |
| 3619 | static const struct { |
| 3620 | int (*check)(struct adreno_device *adreno_dev); |
| 3621 | void (*func)(struct adreno_device *adreno_dev); |
| 3622 | } a6xx_efuse_funcs[] = { |
| 3623 | { adreno_is_a615, a6xx_efuse_speed_bin }, |
Deepak Kumar | 5287eea | 2018-03-17 14:33:05 +0530 | [diff] [blame] | 3624 | { adreno_is_a616, a6xx_efuse_speed_bin }, |
Rajesh Kemisetti | 10bbec9 | 2017-10-20 10:55:58 +0530 | [diff] [blame] | 3625 | }; |
| 3626 | |
| 3627 | static void a6xx_check_features(struct adreno_device *adreno_dev) |
| 3628 | { |
| 3629 | unsigned int i; |
| 3630 | |
| 3631 | if (adreno_efuse_map(adreno_dev)) |
| 3632 | return; |
| 3633 | for (i = 0; i < ARRAY_SIZE(a6xx_efuse_funcs); i++) { |
| 3634 | if (a6xx_efuse_funcs[i].check(adreno_dev)) |
| 3635 | a6xx_efuse_funcs[i].func(adreno_dev); |
| 3636 | } |
| 3637 | |
| 3638 | adreno_efuse_unmap(adreno_dev); |
| 3639 | } |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 3640 | static void a6xx_platform_setup(struct adreno_device *adreno_dev) |
| 3641 | { |
| 3642 | uint64_t addr; |
| 3643 | struct adreno_gpudev *gpudev = ADRENO_GPU_DEVICE(adreno_dev); |
| 3644 | |
| 3645 | /* Calculate SP local and private mem addresses */ |
| 3646 | addr = ALIGN(ADRENO_UCHE_GMEM_BASE + adreno_dev->gmem_size, SZ_64K); |
| 3647 | adreno_dev->sp_local_gpuaddr = addr; |
| 3648 | adreno_dev->sp_pvt_gpuaddr = addr + SZ_64K; |
| 3649 | |
| 3650 | if (adreno_has_gbif(adreno_dev)) { |
| 3651 | a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_VBIF].regs = |
| 3652 | a6xx_perfcounters_gbif; |
| 3653 | a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_VBIF].reg_count |
| 3654 | = ARRAY_SIZE(a6xx_perfcounters_gbif); |
| 3655 | |
| 3656 | a6xx_perfcounter_groups[KGSL_PERFCOUNTER_GROUP_VBIF_PWR].regs = |
| 3657 | a6xx_perfcounters_gbif_pwr; |
Deepak Kumar | 84b9e03 | 2017-11-08 13:08:50 +0530 | [diff] [blame] | 3658 | a6xx_perfcounter_groups[ |
| 3659 | KGSL_PERFCOUNTER_GROUP_VBIF_PWR].reg_count |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 3660 | = ARRAY_SIZE(a6xx_perfcounters_gbif_pwr); |
| 3661 | |
| 3662 | gpudev->vbif_xin_halt_ctrl0_mask = |
| 3663 | A6XX_GBIF_HALT_MASK; |
| 3664 | } else |
| 3665 | gpudev->vbif_xin_halt_ctrl0_mask = |
| 3666 | A6XX_VBIF_XIN_HALT_CTRL0_MASK; |
Rajesh Kemisetti | 10bbec9 | 2017-10-20 10:55:58 +0530 | [diff] [blame] | 3667 | |
| 3668 | /* Check efuse bits for various capabilties */ |
| 3669 | a6xx_check_features(adreno_dev); |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 3670 | } |
| 3671 | |
| 3672 | |
Harshdeep Dhatt | 6ba7a94 | 2017-08-21 17:53:52 -0600 | [diff] [blame] | 3673 | static unsigned int a6xx_ccu_invalidate(struct adreno_device *adreno_dev, |
| 3674 | unsigned int *cmds) |
| 3675 | { |
| 3676 | /* CCU_INVALIDATE_DEPTH */ |
| 3677 | *cmds++ = cp_packet(adreno_dev, CP_EVENT_WRITE, 1); |
| 3678 | *cmds++ = 24; |
| 3679 | |
| 3680 | /* CCU_INVALIDATE_COLOR */ |
| 3681 | *cmds++ = cp_packet(adreno_dev, CP_EVENT_WRITE, 1); |
| 3682 | *cmds++ = 25; |
| 3683 | |
| 3684 | return 4; |
| 3685 | } |
| 3686 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3687 | /* Register offset defines for A6XX, in order of enum adreno_regs */ |
| 3688 | static unsigned int a6xx_register_offsets[ADRENO_REG_REGISTER_MAX] = { |
| 3689 | |
| 3690 | ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE, A6XX_CP_RB_BASE), |
Shrenuj Bansal | 4166540 | 2016-12-16 15:25:54 -0800 | [diff] [blame] | 3691 | ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_BASE_HI, A6XX_CP_RB_BASE_HI), |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3692 | ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR_ADDR_LO, |
| 3693 | A6XX_CP_RB_RPTR_ADDR_LO), |
| 3694 | ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR_ADDR_HI, |
| 3695 | A6XX_CP_RB_RPTR_ADDR_HI), |
| 3696 | ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_RPTR, A6XX_CP_RB_RPTR), |
| 3697 | ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_WPTR, A6XX_CP_RB_WPTR), |
| 3698 | ADRENO_REG_DEFINE(ADRENO_REG_CP_RB_CNTL, A6XX_CP_RB_CNTL), |
Shrenuj Bansal | 4166540 | 2016-12-16 15:25:54 -0800 | [diff] [blame] | 3699 | ADRENO_REG_DEFINE(ADRENO_REG_CP_ME_CNTL, A6XX_CP_SQE_CNTL), |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3700 | ADRENO_REG_DEFINE(ADRENO_REG_CP_CNTL, A6XX_CP_MISC_CNTL), |
Carter Cooper | 8567af0 | 2017-03-15 14:22:03 -0600 | [diff] [blame] | 3701 | ADRENO_REG_DEFINE(ADRENO_REG_CP_HW_FAULT, A6XX_CP_HW_FAULT), |
Shrenuj Bansal | 4166540 | 2016-12-16 15:25:54 -0800 | [diff] [blame] | 3702 | ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BASE, A6XX_CP_IB1_BASE), |
| 3703 | ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BASE_HI, A6XX_CP_IB1_BASE_HI), |
| 3704 | ADRENO_REG_DEFINE(ADRENO_REG_CP_IB1_BUFSZ, A6XX_CP_IB1_REM_SIZE), |
| 3705 | ADRENO_REG_DEFINE(ADRENO_REG_CP_IB2_BASE, A6XX_CP_IB2_BASE), |
| 3706 | ADRENO_REG_DEFINE(ADRENO_REG_CP_IB2_BASE_HI, A6XX_CP_IB2_BASE_HI), |
| 3707 | ADRENO_REG_DEFINE(ADRENO_REG_CP_IB2_BUFSZ, A6XX_CP_IB2_REM_SIZE), |
| 3708 | ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_ADDR, A6XX_CP_ROQ_DBG_ADDR), |
| 3709 | ADRENO_REG_DEFINE(ADRENO_REG_CP_ROQ_DATA, A6XX_CP_ROQ_DBG_DATA), |
Harshdeep Dhatt | 0cdc899 | 2017-05-31 15:44:05 -0600 | [diff] [blame] | 3710 | ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT, A6XX_CP_CONTEXT_SWITCH_CNTL), |
| 3711 | ADRENO_REG_DEFINE(ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_LO, |
| 3712 | A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_LO), |
| 3713 | ADRENO_REG_DEFINE(ADRENO_REG_CP_CONTEXT_SWITCH_SMMU_INFO_HI, |
| 3714 | A6XX_CP_CONTEXT_SWITCH_SMMU_INFO_HI), |
Harshdeep Dhatt | 59a6957 | 2017-11-01 14:46:13 -0600 | [diff] [blame] | 3715 | ADRENO_REG_DEFINE( |
| 3716 | ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO, |
| 3717 | A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO), |
| 3718 | ADRENO_REG_DEFINE( |
| 3719 | ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI, |
| 3720 | A6XX_CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI), |
| 3721 | ADRENO_REG_DEFINE( |
| 3722 | ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO, |
| 3723 | A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO), |
| 3724 | ADRENO_REG_DEFINE( |
| 3725 | ADRENO_REG_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI, |
| 3726 | A6XX_CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI), |
| 3727 | ADRENO_REG_DEFINE(ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO, |
| 3728 | A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO), |
| 3729 | ADRENO_REG_DEFINE(ADRENO_REG_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI, |
| 3730 | A6XX_CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI), |
Harshdeep Dhatt | 003f6cf | 2017-12-14 11:00:22 -0700 | [diff] [blame] | 3731 | ADRENO_REG_DEFINE(ADRENO_REG_CP_PREEMPT_LEVEL_STATUS, |
| 3732 | A6XX_CP_CONTEXT_SWITCH_LEVEL_STATUS), |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3733 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS, A6XX_RBBM_STATUS), |
| 3734 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_STATUS3, A6XX_RBBM_STATUS3), |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3735 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_CTL, A6XX_RBBM_PERFCTR_CNTL), |
| 3736 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD0, |
| 3737 | A6XX_RBBM_PERFCTR_LOAD_CMD0), |
| 3738 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD1, |
| 3739 | A6XX_RBBM_PERFCTR_LOAD_CMD1), |
| 3740 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD2, |
| 3741 | A6XX_RBBM_PERFCTR_LOAD_CMD2), |
| 3742 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_CMD3, |
| 3743 | A6XX_RBBM_PERFCTR_LOAD_CMD3), |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3744 | |
| 3745 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_INT_0_MASK, A6XX_RBBM_INT_0_MASK), |
| 3746 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_INT_0_STATUS, A6XX_RBBM_INT_0_STATUS), |
| 3747 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_CLOCK_CTL, A6XX_RBBM_CLOCK_CNTL), |
| 3748 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_INT_CLEAR_CMD, |
| 3749 | A6XX_RBBM_INT_CLEAR_CMD), |
| 3750 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SW_RESET_CMD, A6XX_RBBM_SW_RESET_CMD), |
| 3751 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD, |
| 3752 | A6XX_RBBM_BLOCK_SW_RESET_CMD), |
| 3753 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_BLOCK_SW_RESET_CMD2, |
| 3754 | A6XX_RBBM_BLOCK_SW_RESET_CMD2), |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3755 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_LO, |
| 3756 | A6XX_RBBM_PERFCTR_LOAD_VALUE_LO), |
| 3757 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_PERFCTR_LOAD_VALUE_HI, |
| 3758 | A6XX_RBBM_PERFCTR_LOAD_VALUE_HI), |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3759 | ADRENO_REG_DEFINE(ADRENO_REG_VBIF_VERSION, A6XX_VBIF_VERSION), |
Carter Cooper | afc8591 | 2017-03-20 09:39:18 -0600 | [diff] [blame] | 3760 | ADRENO_REG_DEFINE(ADRENO_REG_VBIF_XIN_HALT_CTRL0, |
| 3761 | A6XX_VBIF_XIN_HALT_CTRL0), |
| 3762 | ADRENO_REG_DEFINE(ADRENO_REG_VBIF_XIN_HALT_CTRL1, |
| 3763 | A6XX_VBIF_XIN_HALT_CTRL1), |
Rajesh Kemisetti | d1ca954 | 2017-10-18 15:35:41 +0530 | [diff] [blame] | 3764 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_GPR0_CNTL, A6XX_RBBM_GPR0_CNTL), |
| 3765 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_VBIF_GX_RESET_STATUS, |
| 3766 | A6XX_RBBM_VBIF_GX_RESET_STATUS), |
Rajesh Kemisetti | 77b82ed | 2017-09-24 20:42:41 +0530 | [diff] [blame] | 3767 | ADRENO_REG_DEFINE(ADRENO_REG_GBIF_HALT, A6XX_GBIF_HALT), |
| 3768 | ADRENO_REG_DEFINE(ADRENO_REG_GBIF_HALT_ACK, A6XX_GBIF_HALT_ACK), |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 3769 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_LO, |
| 3770 | A6XX_GMU_ALWAYS_ON_COUNTER_L), |
| 3771 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_ALWAYSON_COUNTER_HI, |
| 3772 | A6XX_GMU_ALWAYS_ON_COUNTER_H), |
Kyle Piefer | da0fa54 | 2017-08-04 13:39:40 -0700 | [diff] [blame] | 3773 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_AHB_FENCE_CTRL, |
| 3774 | A6XX_GMU_AO_AHB_FENCE_CTRL), |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 3775 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_INTERRUPT_EN, |
| 3776 | A6XX_GMU_AO_INTERRUPT_EN), |
Kyle Piefer | e7b06b4 | 2017-04-06 13:53:01 -0700 | [diff] [blame] | 3777 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_CLR, |
| 3778 | A6XX_GMU_AO_HOST_INTERRUPT_CLR), |
| 3779 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_STATUS, |
| 3780 | A6XX_GMU_AO_HOST_INTERRUPT_STATUS), |
| 3781 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_AO_HOST_INTERRUPT_MASK, |
| 3782 | A6XX_GMU_AO_HOST_INTERRUPT_MASK), |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 3783 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_PWR_COL_KEEPALIVE, |
| 3784 | A6XX_GMU_GMU_PWR_COL_KEEPALIVE), |
| 3785 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_AHB_FENCE_STATUS, |
| 3786 | A6XX_GMU_AHB_FENCE_STATUS), |
| 3787 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_HFI_CTRL_STATUS, |
| 3788 | A6XX_GMU_HFI_CTRL_STATUS), |
| 3789 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_HFI_VERSION_INFO, |
| 3790 | A6XX_GMU_HFI_VERSION_INFO), |
| 3791 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_HFI_SFR_ADDR, |
| 3792 | A6XX_GMU_HFI_SFR_ADDR), |
| 3793 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_RPMH_POWER_STATE, |
George Shen | f2d4e05 | 2017-05-11 16:28:23 -0700 | [diff] [blame] | 3794 | A6XX_GPU_GMU_CX_GMU_RPMH_POWER_STATE), |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 3795 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_GMU2HOST_INTR_CLR, |
| 3796 | A6XX_GMU_GMU2HOST_INTR_CLR), |
| 3797 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_GMU2HOST_INTR_INFO, |
| 3798 | A6XX_GMU_GMU2HOST_INTR_INFO), |
Kyle Piefer | e7b06b4 | 2017-04-06 13:53:01 -0700 | [diff] [blame] | 3799 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_GMU2HOST_INTR_MASK, |
| 3800 | A6XX_GMU_GMU2HOST_INTR_MASK), |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 3801 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_HOST2GMU_INTR_SET, |
| 3802 | A6XX_GMU_HOST2GMU_INTR_SET), |
| 3803 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_HOST2GMU_INTR_CLR, |
| 3804 | A6XX_GMU_HOST2GMU_INTR_CLR), |
| 3805 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_HOST2GMU_INTR_RAW_INFO, |
| 3806 | A6XX_GMU_HOST2GMU_INTR_RAW_INFO), |
George Shen | 6927d8f | 2017-07-19 11:38:10 -0700 | [diff] [blame] | 3807 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_NMI_CONTROL_STATUS, |
| 3808 | A6XX_GMU_NMI_CONTROL_STATUS), |
| 3809 | ADRENO_REG_DEFINE(ADRENO_REG_GMU_CM3_CFG, |
| 3810 | A6XX_GMU_CM3_CFG), |
Carter Cooper | 4a313ae | 2017-02-23 11:11:56 -0700 | [diff] [blame] | 3811 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TRUST_CONTROL, |
| 3812 | A6XX_RBBM_SECVID_TRUST_CNTL), |
| 3813 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE, |
| 3814 | A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_LO), |
| 3815 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_BASE_HI, |
| 3816 | A6XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI), |
| 3817 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_TRUSTED_SIZE, |
| 3818 | A6XX_RBBM_SECVID_TSB_TRUSTED_SIZE), |
| 3819 | ADRENO_REG_DEFINE(ADRENO_REG_RBBM_SECVID_TSB_CONTROL, |
| 3820 | A6XX_RBBM_SECVID_TSB_CNTL), |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3821 | }; |
| 3822 | |
| 3823 | static const struct adreno_reg_offsets a6xx_reg_offsets = { |
| 3824 | .offsets = a6xx_register_offsets, |
| 3825 | .offset_0 = ADRENO_REG_REGISTER_MAX, |
| 3826 | }; |
| 3827 | |
Tarun Karra | 1382e51 | 2017-10-30 19:41:25 -0700 | [diff] [blame] | 3828 | static int a6xx_perfcounter_update(struct adreno_device *adreno_dev, |
| 3829 | struct adreno_perfcount_register *reg, bool update_reg) |
| 3830 | { |
| 3831 | struct kgsl_device *device = KGSL_DEVICE(adreno_dev); |
| 3832 | struct cpu_gpu_lock *lock = adreno_dev->pwrup_reglist.hostptr; |
| 3833 | struct reg_list_pair *reg_pair = (struct reg_list_pair *)(lock + 1); |
| 3834 | unsigned int i; |
| 3835 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
| 3836 | int ret = 0; |
| 3837 | |
| 3838 | lock->flag_kmd = 1; |
| 3839 | /* Write flag_kmd before turn */ |
| 3840 | wmb(); |
| 3841 | lock->turn = 0; |
| 3842 | /* Write these fields before looping */ |
| 3843 | mb(); |
| 3844 | |
| 3845 | /* |
| 3846 | * Spin here while GPU ucode holds the lock, lock->flag_ucode will |
| 3847 | * be set to 0 after GPU ucode releases the lock. Minimum wait time |
| 3848 | * is 1 second and this should be enough for GPU to release the lock |
| 3849 | */ |
| 3850 | while (lock->flag_ucode == 1 && lock->turn == 0) { |
| 3851 | cpu_relax(); |
| 3852 | /* Get the latest updates from GPU */ |
| 3853 | rmb(); |
| 3854 | /* |
| 3855 | * Make sure we wait at least 1sec for the lock, |
| 3856 | * if we did not get it after 1sec return an error. |
| 3857 | */ |
| 3858 | if (time_after(jiffies, timeout) && |
| 3859 | (lock->flag_ucode == 1 && lock->turn == 0)) { |
| 3860 | ret = -EBUSY; |
| 3861 | goto unlock; |
| 3862 | } |
| 3863 | } |
| 3864 | |
| 3865 | /* Read flag_ucode and turn before list_length */ |
| 3866 | rmb(); |
| 3867 | /* |
| 3868 | * If the perfcounter select register is already present in reglist |
| 3869 | * update it, otherwise append the <select register, value> pair to |
| 3870 | * the end of the list. |
| 3871 | */ |
| 3872 | for (i = 0; i < lock->list_length >> 1; i++) |
| 3873 | if (reg_pair[i].offset == reg->select) |
| 3874 | break; |
| 3875 | |
| 3876 | reg_pair[i].offset = reg->select; |
| 3877 | reg_pair[i].val = reg->countable; |
| 3878 | if (i == lock->list_length >> 1) |
| 3879 | lock->list_length += 2; |
| 3880 | |
| 3881 | if (update_reg) |
| 3882 | kgsl_regwrite(device, reg->select, reg->countable); |
| 3883 | |
| 3884 | unlock: |
| 3885 | /* All writes done before releasing the lock */ |
| 3886 | wmb(); |
| 3887 | lock->flag_kmd = 0; |
| 3888 | return ret; |
| 3889 | } |
| 3890 | |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3891 | struct adreno_gpudev adreno_a6xx_gpudev = { |
| 3892 | .reg_offsets = &a6xx_reg_offsets, |
| 3893 | .start = a6xx_start, |
Shrenuj Bansal | 4166540 | 2016-12-16 15:25:54 -0800 | [diff] [blame] | 3894 | .snapshot = a6xx_snapshot, |
Carter Cooper | b88b708 | 2017-09-14 09:03:26 -0600 | [diff] [blame] | 3895 | .snapshot_gmu = a6xx_snapshot_gmu, |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3896 | .irq = &a6xx_irq, |
Shrenuj Bansal | 4166540 | 2016-12-16 15:25:54 -0800 | [diff] [blame] | 3897 | .snapshot_data = &a6xx_snapshot_data, |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3898 | .irq_trace = trace_kgsl_a5xx_irq_status, |
| 3899 | .num_prio_levels = KGSL_PRIORITY_MAX_RB_LEVELS, |
| 3900 | .platform_setup = a6xx_platform_setup, |
Shrenuj Bansal | 4166540 | 2016-12-16 15:25:54 -0800 | [diff] [blame] | 3901 | .init = a6xx_init, |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3902 | .rb_start = a6xx_rb_start, |
| 3903 | .regulator_enable = a6xx_sptprac_enable, |
| 3904 | .regulator_disable = a6xx_sptprac_disable, |
Lynus Vaz | 107d289 | 2017-03-01 13:48:06 +0530 | [diff] [blame] | 3905 | .perfcounters = &a6xx_perfcounters, |
Lynus Vaz | 856ca60 | 2017-05-24 16:56:36 +0530 | [diff] [blame] | 3906 | .enable_pwr_counters = a6xx_enable_pwr_counters, |
Oleg Perelet | c2ab7f7 | 2017-06-22 16:45:57 -0700 | [diff] [blame] | 3907 | .count_throttles = a6xx_count_throttles, |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3908 | .microcode_read = a6xx_microcode_read, |
| 3909 | .enable_64bit = a6xx_enable_64bit, |
Sushmita Susheelendra | 7f66cf7 | 2016-09-12 11:04:43 -0600 | [diff] [blame] | 3910 | .llc_configure_gpu_scid = a6xx_llc_configure_gpu_scid, |
Sushmita Susheelendra | 906564d | 2017-01-10 15:53:55 -0700 | [diff] [blame] | 3911 | .llc_configure_gpuhtw_scid = a6xx_llc_configure_gpuhtw_scid, |
Kyle Piefer | 11a48b6 | 2017-03-17 14:53:40 -0700 | [diff] [blame] | 3912 | .llc_enable_overrides = a6xx_llc_enable_overrides, |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 3913 | .oob_set = a6xx_oob_set, |
| 3914 | .oob_clear = a6xx_oob_clear, |
Carter Cooper | df7ba70 | 2017-03-20 11:28:04 -0600 | [diff] [blame] | 3915 | .gpu_keepalive = a6xx_gpu_keepalive, |
Kyle Piefer | b1027b0 | 2017-02-10 13:58:58 -0800 | [diff] [blame] | 3916 | .rpmh_gpu_pwrctrl = a6xx_rpmh_gpu_pwrctrl, |
Oleg Perelet | 62d5cec | 2017-03-27 16:14:52 -0700 | [diff] [blame] | 3917 | .hw_isidle = a6xx_hw_isidle, /* Replaced by NULL if GMU is disabled */ |
Kyle Piefer | 4033f56 | 2017-08-16 10:00:48 -0700 | [diff] [blame] | 3918 | .wait_for_lowest_idle = a6xx_wait_for_lowest_idle, |
Lynus Vaz | 1fde74d | 2017-03-20 18:02:47 +0530 | [diff] [blame] | 3919 | .wait_for_gmu_idle = a6xx_wait_for_gmu_idle, |
| 3920 | .iommu_fault_block = a6xx_iommu_fault_block, |
Shrenuj Bansal | d0fe746 | 2017-05-08 16:11:19 -0700 | [diff] [blame] | 3921 | .reset = a6xx_reset, |
Shrenuj Bansal | 49d0e9f | 2017-05-08 16:10:24 -0700 | [diff] [blame] | 3922 | .soft_reset = a6xx_soft_reset, |
Harshdeep Dhatt | 0cdc899 | 2017-05-31 15:44:05 -0600 | [diff] [blame] | 3923 | .preemption_pre_ibsubmit = a6xx_preemption_pre_ibsubmit, |
| 3924 | .preemption_post_ibsubmit = a6xx_preemption_post_ibsubmit, |
| 3925 | .preemption_init = a6xx_preemption_init, |
| 3926 | .preemption_schedule = a6xx_preemption_schedule, |
Harshdeep Dhatt | aae850c | 2017-08-21 17:19:26 -0600 | [diff] [blame] | 3927 | .set_marker = a6xx_set_marker, |
Harshdeep Dhatt | 2e42f12 | 2017-05-31 17:27:19 -0600 | [diff] [blame] | 3928 | .preemption_context_init = a6xx_preemption_context_init, |
| 3929 | .preemption_context_destroy = a6xx_preemption_context_destroy, |
Shrenuj Bansal | d197bf6 | 2017-04-07 11:00:09 -0700 | [diff] [blame] | 3930 | .gx_is_on = a6xx_gx_is_on, |
| 3931 | .sptprac_is_on = a6xx_sptprac_is_on, |
Harshdeep Dhatt | 6ba7a94 | 2017-08-21 17:53:52 -0600 | [diff] [blame] | 3932 | .ccu_invalidate = a6xx_ccu_invalidate, |
Tarun Karra | 1382e51 | 2017-10-30 19:41:25 -0700 | [diff] [blame] | 3933 | .perfcounter_update = a6xx_perfcounter_update, |
Lokesh Batra | a8300e0 | 2017-05-25 11:17:40 -0700 | [diff] [blame] | 3934 | .coresight = {&a6xx_coresight, &a6xx_coresight_cx}, |
Shrenuj Bansal | acf1ef4 | 2016-06-01 11:11:27 -0700 | [diff] [blame] | 3935 | }; |