Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 1 | /* |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 2 | * omap_hwmod_2420_data.c - hardware modules present on the OMAP2420 chips |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 3 | * |
Paul Walmsley | 78183f3 | 2011-07-09 19:14:05 -0600 | [diff] [blame] | 4 | * Copyright (C) 2009-2011 Nokia Corporation |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 5 | * Copyright (C) 2012 Texas Instruments, Inc. |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 6 | * Paul Walmsley |
| 7 | * |
| 8 | * This program is free software; you can redistribute it and/or modify |
| 9 | * it under the terms of the GNU General Public License version 2 as |
| 10 | * published by the Free Software Foundation. |
| 11 | * |
| 12 | * XXX handle crossbar/shared link difference for L3? |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 13 | * XXX these should be marked initdata for multi-OMAP kernels |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 14 | */ |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 15 | #include <plat/omap_hwmod.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 16 | #include <mach/irqs.h> |
Tony Lindgren | ce491cf | 2009-10-20 09:40:47 -0700 | [diff] [blame] | 17 | #include <plat/cpu.h> |
| 18 | #include <plat/dma.h> |
Kevin Hilman | 046465b | 2010-09-27 20:19:30 +0530 | [diff] [blame] | 19 | #include <plat/serial.h> |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 20 | #include <plat/i2c.h> |
Varadarajan, Charulatha | 59c348c | 2010-12-07 16:26:56 -0800 | [diff] [blame] | 21 | #include <plat/gpio.h> |
Charulatha V | 617871d | 2011-02-17 09:53:09 -0800 | [diff] [blame] | 22 | #include <plat/mcspi.h> |
Thara Gopinath | eddb126 | 2011-02-23 00:14:04 -0700 | [diff] [blame] | 23 | #include <plat/dmtimer.h> |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 24 | #include <plat/l3_2xxx.h> |
| 25 | #include <plat/l4_2xxx.h> |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 26 | |
Paul Walmsley | 43b4099 | 2010-02-22 22:09:34 -0700 | [diff] [blame] | 27 | #include "omap_hwmod_common_data.h" |
| 28 | |
Varadarajan, Charulatha | a714b9c | 2010-09-23 20:02:39 +0530 | [diff] [blame] | 29 | #include "cm-regbits-24xx.h" |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 30 | #include "prm-regbits-24xx.h" |
Paul Walmsley | ff2516f | 2010-12-21 15:39:15 -0700 | [diff] [blame] | 31 | #include "wd_timer.h" |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 32 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 33 | /* |
| 34 | * OMAP2420 hardware module integration data |
| 35 | * |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 36 | * All of the data in this section should be autogeneratable from the |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 37 | * TI hardware database or other technical documentation. Data that |
| 38 | * is driver-specific or driver-kernel integration-specific belongs |
| 39 | * elsewhere. |
| 40 | */ |
| 41 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 42 | /* |
| 43 | * IP blocks |
| 44 | */ |
Senthilvadivu Guruswamy | 996746c | 2011-02-22 09:50:36 +0200 | [diff] [blame] | 45 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 46 | /* IVA2 (IVA2) */ |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 47 | static struct omap_hwmod omap2420_iva_hwmod = { |
| 48 | .name = "iva", |
| 49 | .class = &iva_hwmod_class, |
Paul Walmsley | 08072ac | 2010-07-26 16:34:33 -0600 | [diff] [blame] | 50 | }; |
| 51 | |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 52 | /* I2C common */ |
| 53 | static struct omap_hwmod_class_sysconfig i2c_sysc = { |
| 54 | .rev_offs = 0x00, |
| 55 | .sysc_offs = 0x20, |
| 56 | .syss_offs = 0x10, |
Avinash.H.M | d73d65f | 2011-03-03 14:22:46 -0700 | [diff] [blame] | 57 | .sysc_flags = (SYSC_HAS_SOFTRESET | SYSS_HAS_RESET_STATUS), |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 58 | .sysc_fields = &omap_hwmod_sysc_type1, |
| 59 | }; |
| 60 | |
| 61 | static struct omap_hwmod_class i2c_class = { |
| 62 | .name = "i2c", |
| 63 | .sysc = &i2c_sysc, |
Andy Green | db791a7 | 2011-07-10 05:27:15 -0600 | [diff] [blame] | 64 | .rev = OMAP_I2C_IP_VERSION_1, |
Avinash.H.M | 6d3c55f | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 65 | .reset = &omap_i2c_reset, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 66 | }; |
| 67 | |
Andy Green | 4d4441a | 2011-07-10 05:27:16 -0600 | [diff] [blame] | 68 | static struct omap_i2c_dev_attr i2c_dev_attr = { |
| 69 | .flags = OMAP_I2C_FLAG_NO_FIFO | |
| 70 | OMAP_I2C_FLAG_SIMPLE_CLOCK | |
| 71 | OMAP_I2C_FLAG_16BIT_DATA_REG | |
| 72 | OMAP_I2C_FLAG_BUS_SHIFT_2, |
| 73 | }; |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 74 | |
| 75 | /* I2C1 */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 76 | static struct omap_hwmod omap2420_i2c1_hwmod = { |
| 77 | .name = "i2c1", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 78 | .mpu_irqs = omap2_i2c1_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 79 | .sdma_reqs = omap2_i2c1_sdma_reqs, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 80 | .main_clk = "i2c1_fck", |
| 81 | .prcm = { |
| 82 | .omap2 = { |
| 83 | .module_offs = CORE_MOD, |
| 84 | .prcm_reg_id = 1, |
| 85 | .module_bit = OMAP2420_EN_I2C1_SHIFT, |
| 86 | .idlest_reg_id = 1, |
| 87 | .idlest_idle_bit = OMAP2420_ST_I2C1_SHIFT, |
| 88 | }, |
| 89 | }, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 90 | .class = &i2c_class, |
| 91 | .dev_attr = &i2c_dev_attr, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 92 | .flags = HWMOD_16BIT_REG, |
| 93 | }; |
| 94 | |
| 95 | /* I2C2 */ |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 96 | static struct omap_hwmod omap2420_i2c2_hwmod = { |
| 97 | .name = "i2c2", |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 98 | .mpu_irqs = omap2_i2c2_mpu_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 99 | .sdma_reqs = omap2_i2c2_sdma_reqs, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 100 | .main_clk = "i2c2_fck", |
| 101 | .prcm = { |
| 102 | .omap2 = { |
| 103 | .module_offs = CORE_MOD, |
| 104 | .prcm_reg_id = 1, |
| 105 | .module_bit = OMAP2420_EN_I2C2_SHIFT, |
| 106 | .idlest_reg_id = 1, |
| 107 | .idlest_idle_bit = OMAP2420_ST_I2C2_SHIFT, |
| 108 | }, |
| 109 | }, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 110 | .class = &i2c_class, |
| 111 | .dev_attr = &i2c_dev_attr, |
Paul Walmsley | 2004290 | 2010-09-30 02:40:12 +0530 | [diff] [blame] | 112 | .flags = HWMOD_16BIT_REG, |
| 113 | }; |
| 114 | |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 115 | /* dma attributes */ |
| 116 | static struct omap_dma_dev_attr dma_dev_attr = { |
| 117 | .dev_caps = RESERVE_CHANNEL | DMA_LINKED_LCH | GLOBAL_PRIORITY | |
| 118 | IS_CSSA_32 | IS_CDSA_32, |
| 119 | .lch_count = 32, |
| 120 | }; |
| 121 | |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 122 | static struct omap_hwmod omap2420_dma_system_hwmod = { |
| 123 | .name = "dma", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 124 | .class = &omap2xxx_dma_hwmod_class, |
Paul Walmsley | 0d619a8 | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 125 | .mpu_irqs = omap2_dma_system_irqs, |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 126 | .main_clk = "core_l3_ck", |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 127 | .dev_attr = &dma_dev_attr, |
G, Manjunath Kondaiah | 745685df9 | 2010-12-20 18:27:18 -0800 | [diff] [blame] | 128 | .flags = HWMOD_NO_IDLEST, |
| 129 | }; |
| 130 | |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 131 | /* mailbox */ |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 132 | static struct omap_hwmod_irq_info omap2420_mailbox_irqs[] = { |
| 133 | { .name = "dsp", .irq = 26 }, |
| 134 | { .name = "iva", .irq = 34 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 135 | { .irq = -1 } |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 136 | }; |
| 137 | |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 138 | static struct omap_hwmod omap2420_mailbox_hwmod = { |
| 139 | .name = "mailbox", |
Paul Walmsley | 273b946 | 2011-07-09 19:14:08 -0600 | [diff] [blame] | 140 | .class = &omap2xxx_mailbox_hwmod_class, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 141 | .mpu_irqs = omap2420_mailbox_irqs, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 142 | .main_clk = "mailboxes_ick", |
| 143 | .prcm = { |
| 144 | .omap2 = { |
| 145 | .prcm_reg_id = 1, |
| 146 | .module_bit = OMAP24XX_EN_MAILBOXES_SHIFT, |
| 147 | .module_offs = CORE_MOD, |
| 148 | .idlest_reg_id = 1, |
| 149 | .idlest_idle_bit = OMAP24XX_ST_MAILBOXES_SHIFT, |
| 150 | }, |
| 151 | }, |
Omar Ramirez Luna | fca1ab5 | 2011-02-24 12:51:32 -0800 | [diff] [blame] | 152 | }; |
| 153 | |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 154 | /* |
| 155 | * 'mcbsp' class |
| 156 | * multi channel buffered serial port controller |
| 157 | */ |
| 158 | |
| 159 | static struct omap_hwmod_class omap2420_mcbsp_hwmod_class = { |
| 160 | .name = "mcbsp", |
| 161 | }; |
| 162 | |
| 163 | /* mcbsp1 */ |
| 164 | static struct omap_hwmod_irq_info omap2420_mcbsp1_irqs[] = { |
| 165 | { .name = "tx", .irq = 59 }, |
| 166 | { .name = "rx", .irq = 60 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 167 | { .irq = -1 } |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 168 | }; |
| 169 | |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 170 | static struct omap_hwmod omap2420_mcbsp1_hwmod = { |
| 171 | .name = "mcbsp1", |
| 172 | .class = &omap2420_mcbsp_hwmod_class, |
| 173 | .mpu_irqs = omap2420_mcbsp1_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 174 | .sdma_reqs = omap2_mcbsp1_sdma_reqs, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 175 | .main_clk = "mcbsp1_fck", |
| 176 | .prcm = { |
| 177 | .omap2 = { |
| 178 | .prcm_reg_id = 1, |
| 179 | .module_bit = OMAP24XX_EN_MCBSP1_SHIFT, |
| 180 | .module_offs = CORE_MOD, |
| 181 | .idlest_reg_id = 1, |
| 182 | .idlest_idle_bit = OMAP24XX_ST_MCBSP1_SHIFT, |
| 183 | }, |
| 184 | }, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 185 | }; |
| 186 | |
| 187 | /* mcbsp2 */ |
| 188 | static struct omap_hwmod_irq_info omap2420_mcbsp2_irqs[] = { |
| 189 | { .name = "tx", .irq = 62 }, |
| 190 | { .name = "rx", .irq = 63 }, |
Paul Walmsley | 212738a | 2011-07-09 19:14:06 -0600 | [diff] [blame] | 191 | { .irq = -1 } |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 192 | }; |
| 193 | |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 194 | static struct omap_hwmod omap2420_mcbsp2_hwmod = { |
| 195 | .name = "mcbsp2", |
| 196 | .class = &omap2420_mcbsp_hwmod_class, |
| 197 | .mpu_irqs = omap2420_mcbsp2_irqs, |
Paul Walmsley | d826ebf | 2011-07-09 19:14:07 -0600 | [diff] [blame] | 198 | .sdma_reqs = omap2_mcbsp2_sdma_reqs, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 199 | .main_clk = "mcbsp2_fck", |
| 200 | .prcm = { |
| 201 | .omap2 = { |
| 202 | .prcm_reg_id = 1, |
| 203 | .module_bit = OMAP24XX_EN_MCBSP2_SHIFT, |
| 204 | .module_offs = CORE_MOD, |
| 205 | .idlest_reg_id = 1, |
| 206 | .idlest_idle_bit = OMAP24XX_ST_MCBSP2_SHIFT, |
| 207 | }, |
| 208 | }, |
Charulatha V | 3cb72fa | 2011-02-24 12:51:46 -0800 | [diff] [blame] | 209 | }; |
| 210 | |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 211 | /* |
| 212 | * interfaces |
| 213 | */ |
| 214 | |
| 215 | /* L3 -> L4_CORE interface */ |
| 216 | static struct omap_hwmod_ocp_if omap2420_l3_main__l4_core = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 217 | .master = &omap2xxx_l3_main_hwmod, |
| 218 | .slave = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 219 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 220 | }; |
| 221 | |
| 222 | /* MPU -> L3 interface */ |
| 223 | static struct omap_hwmod_ocp_if omap2420_mpu__l3_main = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 224 | .master = &omap2xxx_mpu_hwmod, |
| 225 | .slave = &omap2xxx_l3_main_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 226 | .user = OCP_USER_MPU, |
| 227 | }; |
| 228 | |
| 229 | /* DSS -> l3 */ |
| 230 | static struct omap_hwmod_ocp_if omap2420_dss__l3 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 231 | .master = &omap2xxx_dss_core_hwmod, |
| 232 | .slave = &omap2xxx_l3_main_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 233 | .fw = { |
| 234 | .omap2 = { |
| 235 | .l3_perm_bit = OMAP2_L3_CORE_FW_CONNID_DSS, |
| 236 | .flags = OMAP_FIREWALL_L3, |
| 237 | } |
| 238 | }, |
| 239 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 240 | }; |
| 241 | |
| 242 | /* l4 core -> mcspi1 interface */ |
| 243 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 244 | .master = &omap2xxx_l4_core_hwmod, |
| 245 | .slave = &omap2xxx_mcspi1_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 246 | .clk = "mcspi1_ick", |
| 247 | .addr = omap2_mcspi1_addr_space, |
| 248 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 249 | }; |
| 250 | |
| 251 | /* l4 core -> mcspi2 interface */ |
| 252 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcspi2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 253 | .master = &omap2xxx_l4_core_hwmod, |
| 254 | .slave = &omap2xxx_mcspi2_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 255 | .clk = "mcspi2_ick", |
| 256 | .addr = omap2_mcspi2_addr_space, |
| 257 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 258 | }; |
| 259 | |
| 260 | /* L4_CORE -> L4_WKUP interface */ |
| 261 | static struct omap_hwmod_ocp_if omap2420_l4_core__l4_wkup = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 262 | .master = &omap2xxx_l4_core_hwmod, |
| 263 | .slave = &omap2xxx_l4_wkup_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 264 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 265 | }; |
| 266 | |
| 267 | /* L4 CORE -> UART1 interface */ |
| 268 | static struct omap_hwmod_ocp_if omap2_l4_core__uart1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 269 | .master = &omap2xxx_l4_core_hwmod, |
| 270 | .slave = &omap2xxx_uart1_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 271 | .clk = "uart1_ick", |
| 272 | .addr = omap2xxx_uart1_addr_space, |
| 273 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 274 | }; |
| 275 | |
| 276 | /* L4 CORE -> UART2 interface */ |
| 277 | static struct omap_hwmod_ocp_if omap2_l4_core__uart2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 278 | .master = &omap2xxx_l4_core_hwmod, |
| 279 | .slave = &omap2xxx_uart2_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 280 | .clk = "uart2_ick", |
| 281 | .addr = omap2xxx_uart2_addr_space, |
| 282 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 283 | }; |
| 284 | |
| 285 | /* L4 PER -> UART3 interface */ |
| 286 | static struct omap_hwmod_ocp_if omap2_l4_core__uart3 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 287 | .master = &omap2xxx_l4_core_hwmod, |
| 288 | .slave = &omap2xxx_uart3_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 289 | .clk = "uart3_ick", |
| 290 | .addr = omap2xxx_uart3_addr_space, |
| 291 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 292 | }; |
| 293 | |
| 294 | /* L4 CORE -> I2C1 interface */ |
| 295 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 296 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 297 | .slave = &omap2420_i2c1_hwmod, |
| 298 | .clk = "i2c1_ick", |
| 299 | .addr = omap2_i2c1_addr_space, |
| 300 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 301 | }; |
| 302 | |
| 303 | /* L4 CORE -> I2C2 interface */ |
| 304 | static struct omap_hwmod_ocp_if omap2420_l4_core__i2c2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 305 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 306 | .slave = &omap2420_i2c2_hwmod, |
| 307 | .clk = "i2c2_ick", |
| 308 | .addr = omap2_i2c2_addr_space, |
| 309 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 310 | }; |
| 311 | |
| 312 | /* IVA <- L3 interface */ |
| 313 | static struct omap_hwmod_ocp_if omap2420_l3__iva = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 314 | .master = &omap2xxx_l3_main_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 315 | .slave = &omap2420_iva_hwmod, |
| 316 | .clk = "iva1_ifck", |
| 317 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 318 | }; |
| 319 | |
| 320 | static struct omap_hwmod_addr_space omap2420_timer1_addrs[] = { |
| 321 | { |
| 322 | .pa_start = 0x48028000, |
| 323 | .pa_end = 0x48028000 + SZ_1K - 1, |
| 324 | .flags = ADDR_TYPE_RT |
| 325 | }, |
| 326 | { } |
| 327 | }; |
| 328 | |
| 329 | /* l4_wkup -> timer1 */ |
| 330 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__timer1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 331 | .master = &omap2xxx_l4_wkup_hwmod, |
| 332 | .slave = &omap2xxx_timer1_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 333 | .clk = "gpt1_ick", |
| 334 | .addr = omap2420_timer1_addrs, |
| 335 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 336 | }; |
| 337 | |
| 338 | /* l4_core -> timer2 */ |
| 339 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 340 | .master = &omap2xxx_l4_core_hwmod, |
| 341 | .slave = &omap2xxx_timer2_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 342 | .clk = "gpt2_ick", |
| 343 | .addr = omap2xxx_timer2_addrs, |
| 344 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 345 | }; |
| 346 | |
| 347 | /* l4_core -> timer3 */ |
| 348 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer3 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 349 | .master = &omap2xxx_l4_core_hwmod, |
| 350 | .slave = &omap2xxx_timer3_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 351 | .clk = "gpt3_ick", |
| 352 | .addr = omap2xxx_timer3_addrs, |
| 353 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 354 | }; |
| 355 | |
| 356 | /* l4_core -> timer4 */ |
| 357 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer4 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 358 | .master = &omap2xxx_l4_core_hwmod, |
| 359 | .slave = &omap2xxx_timer4_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 360 | .clk = "gpt4_ick", |
| 361 | .addr = omap2xxx_timer4_addrs, |
| 362 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 363 | }; |
| 364 | |
| 365 | /* l4_core -> timer5 */ |
| 366 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer5 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 367 | .master = &omap2xxx_l4_core_hwmod, |
| 368 | .slave = &omap2xxx_timer5_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 369 | .clk = "gpt5_ick", |
| 370 | .addr = omap2xxx_timer5_addrs, |
| 371 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 372 | }; |
| 373 | |
| 374 | /* l4_core -> timer6 */ |
| 375 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer6 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 376 | .master = &omap2xxx_l4_core_hwmod, |
| 377 | .slave = &omap2xxx_timer6_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 378 | .clk = "gpt6_ick", |
| 379 | .addr = omap2xxx_timer6_addrs, |
| 380 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 381 | }; |
| 382 | |
| 383 | /* l4_core -> timer7 */ |
| 384 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer7 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 385 | .master = &omap2xxx_l4_core_hwmod, |
| 386 | .slave = &omap2xxx_timer7_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 387 | .clk = "gpt7_ick", |
| 388 | .addr = omap2xxx_timer7_addrs, |
| 389 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 390 | }; |
| 391 | |
| 392 | /* l4_core -> timer8 */ |
| 393 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer8 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 394 | .master = &omap2xxx_l4_core_hwmod, |
| 395 | .slave = &omap2xxx_timer8_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 396 | .clk = "gpt8_ick", |
| 397 | .addr = omap2xxx_timer8_addrs, |
| 398 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 399 | }; |
| 400 | |
| 401 | /* l4_core -> timer9 */ |
| 402 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer9 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 403 | .master = &omap2xxx_l4_core_hwmod, |
| 404 | .slave = &omap2xxx_timer9_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 405 | .clk = "gpt9_ick", |
| 406 | .addr = omap2xxx_timer9_addrs, |
| 407 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 408 | }; |
| 409 | |
| 410 | /* l4_core -> timer10 */ |
| 411 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer10 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 412 | .master = &omap2xxx_l4_core_hwmod, |
| 413 | .slave = &omap2xxx_timer10_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 414 | .clk = "gpt10_ick", |
| 415 | .addr = omap2_timer10_addrs, |
| 416 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 417 | }; |
| 418 | |
| 419 | /* l4_core -> timer11 */ |
| 420 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer11 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 421 | .master = &omap2xxx_l4_core_hwmod, |
| 422 | .slave = &omap2xxx_timer11_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 423 | .clk = "gpt11_ick", |
| 424 | .addr = omap2_timer11_addrs, |
| 425 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 426 | }; |
| 427 | |
| 428 | /* l4_core -> timer12 */ |
| 429 | static struct omap_hwmod_ocp_if omap2420_l4_core__timer12 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 430 | .master = &omap2xxx_l4_core_hwmod, |
| 431 | .slave = &omap2xxx_timer12_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 432 | .clk = "gpt12_ick", |
| 433 | .addr = omap2xxx_timer12_addrs, |
| 434 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 435 | }; |
| 436 | |
| 437 | /* l4_wkup -> wd_timer2 */ |
| 438 | static struct omap_hwmod_addr_space omap2420_wd_timer2_addrs[] = { |
| 439 | { |
| 440 | .pa_start = 0x48022000, |
| 441 | .pa_end = 0x4802207f, |
| 442 | .flags = ADDR_TYPE_RT |
| 443 | }, |
| 444 | { } |
| 445 | }; |
| 446 | |
| 447 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__wd_timer2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 448 | .master = &omap2xxx_l4_wkup_hwmod, |
| 449 | .slave = &omap2xxx_wd_timer2_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 450 | .clk = "mpu_wdt_ick", |
| 451 | .addr = omap2420_wd_timer2_addrs, |
| 452 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 453 | }; |
| 454 | |
| 455 | /* l4_core -> dss */ |
| 456 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 457 | .master = &omap2xxx_l4_core_hwmod, |
| 458 | .slave = &omap2xxx_dss_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 459 | .clk = "dss_ick", |
| 460 | .addr = omap2_dss_addrs, |
| 461 | .fw = { |
| 462 | .omap2 = { |
| 463 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 464 | .flags = OMAP_FIREWALL_L4, |
| 465 | } |
| 466 | }, |
| 467 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 468 | }; |
| 469 | |
| 470 | /* l4_core -> dss_dispc */ |
| 471 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_dispc = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 472 | .master = &omap2xxx_l4_core_hwmod, |
| 473 | .slave = &omap2xxx_dss_dispc_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 474 | .clk = "dss_ick", |
| 475 | .addr = omap2_dss_dispc_addrs, |
| 476 | .fw = { |
| 477 | .omap2 = { |
| 478 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_DISPC_REGION, |
| 479 | .flags = OMAP_FIREWALL_L4, |
| 480 | } |
| 481 | }, |
| 482 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 483 | }; |
| 484 | |
| 485 | /* l4_core -> dss_rfbi */ |
| 486 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_rfbi = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 487 | .master = &omap2xxx_l4_core_hwmod, |
| 488 | .slave = &omap2xxx_dss_rfbi_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 489 | .clk = "dss_ick", |
| 490 | .addr = omap2_dss_rfbi_addrs, |
| 491 | .fw = { |
| 492 | .omap2 = { |
| 493 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_CORE_REGION, |
| 494 | .flags = OMAP_FIREWALL_L4, |
| 495 | } |
| 496 | }, |
| 497 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 498 | }; |
| 499 | |
| 500 | /* l4_core -> dss_venc */ |
| 501 | static struct omap_hwmod_ocp_if omap2420_l4_core__dss_venc = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 502 | .master = &omap2xxx_l4_core_hwmod, |
| 503 | .slave = &omap2xxx_dss_venc_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 504 | .clk = "dss_ick", |
| 505 | .addr = omap2_dss_venc_addrs, |
| 506 | .fw = { |
| 507 | .omap2 = { |
| 508 | .l4_fw_region = OMAP2420_L4_CORE_FW_DSS_VENC_REGION, |
| 509 | .flags = OMAP_FIREWALL_L4, |
| 510 | } |
| 511 | }, |
| 512 | .flags = OCPIF_SWSUP_IDLE, |
| 513 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 514 | }; |
| 515 | |
| 516 | /* l4_wkup -> gpio1 */ |
| 517 | static struct omap_hwmod_addr_space omap2420_gpio1_addr_space[] = { |
| 518 | { |
| 519 | .pa_start = 0x48018000, |
| 520 | .pa_end = 0x480181ff, |
| 521 | .flags = ADDR_TYPE_RT |
| 522 | }, |
| 523 | { } |
| 524 | }; |
| 525 | |
| 526 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 527 | .master = &omap2xxx_l4_wkup_hwmod, |
| 528 | .slave = &omap2xxx_gpio1_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 529 | .clk = "gpios_ick", |
| 530 | .addr = omap2420_gpio1_addr_space, |
| 531 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 532 | }; |
| 533 | |
| 534 | /* l4_wkup -> gpio2 */ |
| 535 | static struct omap_hwmod_addr_space omap2420_gpio2_addr_space[] = { |
| 536 | { |
| 537 | .pa_start = 0x4801a000, |
| 538 | .pa_end = 0x4801a1ff, |
| 539 | .flags = ADDR_TYPE_RT |
| 540 | }, |
| 541 | { } |
| 542 | }; |
| 543 | |
| 544 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 545 | .master = &omap2xxx_l4_wkup_hwmod, |
| 546 | .slave = &omap2xxx_gpio2_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 547 | .clk = "gpios_ick", |
| 548 | .addr = omap2420_gpio2_addr_space, |
| 549 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 550 | }; |
| 551 | |
| 552 | /* l4_wkup -> gpio3 */ |
| 553 | static struct omap_hwmod_addr_space omap2420_gpio3_addr_space[] = { |
| 554 | { |
| 555 | .pa_start = 0x4801c000, |
| 556 | .pa_end = 0x4801c1ff, |
| 557 | .flags = ADDR_TYPE_RT |
| 558 | }, |
| 559 | { } |
| 560 | }; |
| 561 | |
| 562 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio3 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 563 | .master = &omap2xxx_l4_wkup_hwmod, |
| 564 | .slave = &omap2xxx_gpio3_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 565 | .clk = "gpios_ick", |
| 566 | .addr = omap2420_gpio3_addr_space, |
| 567 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 568 | }; |
| 569 | |
| 570 | /* l4_wkup -> gpio4 */ |
| 571 | static struct omap_hwmod_addr_space omap2420_gpio4_addr_space[] = { |
| 572 | { |
| 573 | .pa_start = 0x4801e000, |
| 574 | .pa_end = 0x4801e1ff, |
| 575 | .flags = ADDR_TYPE_RT |
| 576 | }, |
| 577 | { } |
| 578 | }; |
| 579 | |
| 580 | static struct omap_hwmod_ocp_if omap2420_l4_wkup__gpio4 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 581 | .master = &omap2xxx_l4_wkup_hwmod, |
| 582 | .slave = &omap2xxx_gpio4_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 583 | .clk = "gpios_ick", |
| 584 | .addr = omap2420_gpio4_addr_space, |
| 585 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 586 | }; |
| 587 | |
| 588 | /* dma_system -> L3 */ |
| 589 | static struct omap_hwmod_ocp_if omap2420_dma_system__l3 = { |
| 590 | .master = &omap2420_dma_system_hwmod, |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 591 | .slave = &omap2xxx_l3_main_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 592 | .clk = "core_l3_ck", |
| 593 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 594 | }; |
| 595 | |
| 596 | /* l4_core -> dma_system */ |
| 597 | static struct omap_hwmod_ocp_if omap2420_l4_core__dma_system = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 598 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 599 | .slave = &omap2420_dma_system_hwmod, |
| 600 | .clk = "sdma_ick", |
| 601 | .addr = omap2_dma_system_addrs, |
| 602 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 603 | }; |
| 604 | |
| 605 | /* l4_core -> mailbox */ |
| 606 | static struct omap_hwmod_ocp_if omap2420_l4_core__mailbox = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 607 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 608 | .slave = &omap2420_mailbox_hwmod, |
| 609 | .addr = omap2_mailbox_addrs, |
| 610 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 611 | }; |
| 612 | |
| 613 | /* l4_core -> mcbsp1 */ |
| 614 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp1 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 615 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 616 | .slave = &omap2420_mcbsp1_hwmod, |
| 617 | .clk = "mcbsp1_ick", |
| 618 | .addr = omap2_mcbsp1_addrs, |
| 619 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 620 | }; |
| 621 | |
| 622 | /* l4_core -> mcbsp2 */ |
| 623 | static struct omap_hwmod_ocp_if omap2420_l4_core__mcbsp2 = { |
Paul Walmsley | cb48427 | 2012-04-19 04:04:33 -0600 | [diff] [blame^] | 624 | .master = &omap2xxx_l4_core_hwmod, |
Paul Walmsley | 844a3b6 | 2012-04-19 04:04:33 -0600 | [diff] [blame] | 625 | .slave = &omap2420_mcbsp2_hwmod, |
| 626 | .clk = "mcbsp2_ick", |
| 627 | .addr = omap2xxx_mcbsp2_addrs, |
| 628 | .user = OCP_USER_MPU | OCP_USER_SDMA, |
| 629 | }; |
| 630 | |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 631 | static struct omap_hwmod_ocp_if *omap2420_hwmod_ocp_ifs[] __initdata = { |
| 632 | &omap2420_l3_main__l4_core, |
| 633 | &omap2420_mpu__l3_main, |
| 634 | &omap2420_dss__l3, |
| 635 | &omap2420_l4_core__mcspi1, |
| 636 | &omap2420_l4_core__mcspi2, |
| 637 | &omap2420_l4_core__l4_wkup, |
| 638 | &omap2_l4_core__uart1, |
| 639 | &omap2_l4_core__uart2, |
| 640 | &omap2_l4_core__uart3, |
| 641 | &omap2420_l4_core__i2c1, |
| 642 | &omap2420_l4_core__i2c2, |
| 643 | &omap2420_l3__iva, |
| 644 | &omap2420_l4_wkup__timer1, |
| 645 | &omap2420_l4_core__timer2, |
| 646 | &omap2420_l4_core__timer3, |
| 647 | &omap2420_l4_core__timer4, |
| 648 | &omap2420_l4_core__timer5, |
| 649 | &omap2420_l4_core__timer6, |
| 650 | &omap2420_l4_core__timer7, |
| 651 | &omap2420_l4_core__timer8, |
| 652 | &omap2420_l4_core__timer9, |
| 653 | &omap2420_l4_core__timer10, |
| 654 | &omap2420_l4_core__timer11, |
| 655 | &omap2420_l4_core__timer12, |
| 656 | &omap2420_l4_wkup__wd_timer2, |
| 657 | &omap2420_l4_core__dss, |
| 658 | &omap2420_l4_core__dss_dispc, |
| 659 | &omap2420_l4_core__dss_rfbi, |
| 660 | &omap2420_l4_core__dss_venc, |
| 661 | &omap2420_l4_wkup__gpio1, |
| 662 | &omap2420_l4_wkup__gpio2, |
| 663 | &omap2420_l4_wkup__gpio3, |
| 664 | &omap2420_l4_wkup__gpio4, |
| 665 | &omap2420_dma_system__l3, |
| 666 | &omap2420_l4_core__dma_system, |
| 667 | &omap2420_l4_core__mailbox, |
| 668 | &omap2420_l4_core__mcbsp1, |
| 669 | &omap2420_l4_core__mcbsp2, |
Paul Walmsley | 02bfc03 | 2009-09-03 20:14:05 +0300 | [diff] [blame] | 670 | NULL, |
| 671 | }; |
| 672 | |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 673 | int __init omap2420_hwmod_init(void) |
| 674 | { |
Paul Walmsley | 0a78c5c | 2012-04-19 04:04:31 -0600 | [diff] [blame] | 675 | return omap_hwmod_register_links(omap2420_hwmod_ocp_ifs); |
Paul Walmsley | 7359154 | 2010-02-22 22:09:32 -0700 | [diff] [blame] | 676 | } |