Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 1 | /* |
Robert Richter | 6852fd9 | 2008-07-22 21:09:08 +0200 | [diff] [blame] | 2 | * @file op_model_amd.c |
Barry Kasindorf | bd87f1f | 2007-12-18 18:05:58 +0100 | [diff] [blame] | 3 | * athlon / K7 / K8 / Family 10h model-specific MSR operations |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 4 | * |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 5 | * @remark Copyright 2002-2009 OProfile authors |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 6 | * @remark Read the file COPYING |
| 7 | * |
| 8 | * @author John Levon |
| 9 | * @author Philippe Elie |
| 10 | * @author Graydon Hoare |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 11 | * @author Robert Richter <robert.richter@amd.com> |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 12 | * @author Barry Kasindorf <barry.kasindorf@amd.com> |
| 13 | * @author Jason Yeh <jason.yeh@amd.com> |
| 14 | * @author Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> |
Robert Richter | ae735e9 | 2008-12-25 17:26:07 +0100 | [diff] [blame] | 15 | */ |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 16 | |
| 17 | #include <linux/oprofile.h> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 18 | #include <linux/device.h> |
| 19 | #include <linux/pci.h> |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 20 | #include <linux/percpu.h> |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 21 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 22 | #include <asm/ptrace.h> |
| 23 | #include <asm/msr.h> |
Don Zickus | 3e4ff11 | 2006-06-26 13:57:01 +0200 | [diff] [blame] | 24 | #include <asm/nmi.h> |
Robert Richter | 013cfc5 | 2010-01-28 18:05:26 +0100 | [diff] [blame] | 25 | #include <asm/apic.h> |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 26 | #include <asm/processor.h> |
| 27 | #include <asm/cpufeature.h> |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 28 | |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 29 | #include "op_x86_model.h" |
| 30 | #include "op_counter.h" |
| 31 | |
Robert Richter | 4c168ea | 2008-09-24 11:08:52 +0200 | [diff] [blame] | 32 | #define NUM_COUNTERS 4 |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 33 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
| 34 | #define NUM_VIRT_COUNTERS 32 |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 35 | #else |
| 36 | #define NUM_VIRT_COUNTERS NUM_COUNTERS |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 37 | #endif |
| 38 | |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 39 | #define OP_EVENT_MASK 0x0FFF |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 40 | #define OP_CTR_OVERFLOW (1ULL<<31) |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 41 | |
| 42 | #define MSR_AMD_EVENTSEL_RESERVED ((0xFFFFFCF0ULL<<32)|(1ULL<<21)) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 43 | |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 44 | static unsigned long reset_value[NUM_VIRT_COUNTERS]; |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 45 | |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 46 | #define IBS_FETCH_SIZE 6 |
| 47 | #define IBS_OP_SIZE 12 |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 48 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 49 | static u32 ibs_caps; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 50 | |
| 51 | struct op_ibs_config { |
| 52 | unsigned long op_enabled; |
| 53 | unsigned long fetch_enabled; |
| 54 | unsigned long max_cnt_fetch; |
| 55 | unsigned long max_cnt_op; |
| 56 | unsigned long rand_en; |
| 57 | unsigned long dispatched_ops; |
| 58 | }; |
| 59 | |
| 60 | static struct op_ibs_config ibs_config; |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 61 | static u64 ibs_op_ctl; |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 62 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 63 | /* |
| 64 | * IBS cpuid feature detection |
| 65 | */ |
| 66 | |
| 67 | #define IBS_CPUID_FEATURES 0x8000001b |
| 68 | |
| 69 | /* |
| 70 | * Same bit mask as for IBS cpuid feature flags (Fn8000_001B_EAX), but |
| 71 | * bit 0 is used to indicate the existence of IBS. |
| 72 | */ |
| 73 | #define IBS_CAPS_AVAIL (1LL<<0) |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 74 | #define IBS_CAPS_RDWROPCNT (1LL<<3) |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 75 | #define IBS_CAPS_OPCNT (1LL<<4) |
| 76 | |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 77 | /* |
| 78 | * IBS randomization macros |
| 79 | */ |
| 80 | #define IBS_RANDOM_BITS 12 |
| 81 | #define IBS_RANDOM_MASK ((1ULL << IBS_RANDOM_BITS) - 1) |
| 82 | #define IBS_RANDOM_MAXCNT_OFFSET (1ULL << (IBS_RANDOM_BITS - 5)) |
| 83 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 84 | static u32 get_ibs_caps(void) |
| 85 | { |
| 86 | u32 ibs_caps; |
| 87 | unsigned int max_level; |
| 88 | |
| 89 | if (!boot_cpu_has(X86_FEATURE_IBS)) |
| 90 | return 0; |
| 91 | |
| 92 | /* check IBS cpuid feature flags */ |
| 93 | max_level = cpuid_eax(0x80000000); |
| 94 | if (max_level < IBS_CPUID_FEATURES) |
| 95 | return IBS_CAPS_AVAIL; |
| 96 | |
| 97 | ibs_caps = cpuid_eax(IBS_CPUID_FEATURES); |
| 98 | if (!(ibs_caps & IBS_CAPS_AVAIL)) |
| 99 | /* cpuid flags not valid */ |
| 100 | return IBS_CAPS_AVAIL; |
| 101 | |
| 102 | return ibs_caps; |
| 103 | } |
| 104 | |
Suravee Suthikulpanit | f125be1 | 2010-01-18 11:25:45 -0600 | [diff] [blame] | 105 | /* |
| 106 | * 16-bit Linear Feedback Shift Register (LFSR) |
| 107 | * |
| 108 | * 16 14 13 11 |
| 109 | * Feedback polynomial = X + X + X + X + 1 |
| 110 | */ |
| 111 | static unsigned int lfsr_random(void) |
| 112 | { |
| 113 | static unsigned int lfsr_value = 0xF00D; |
| 114 | unsigned int bit; |
| 115 | |
| 116 | /* Compute next bit to shift in */ |
| 117 | bit = ((lfsr_value >> 0) ^ |
| 118 | (lfsr_value >> 2) ^ |
| 119 | (lfsr_value >> 3) ^ |
| 120 | (lfsr_value >> 5)) & 0x0001; |
| 121 | |
| 122 | /* Advance to next register value */ |
| 123 | lfsr_value = (lfsr_value >> 1) | (bit << 15); |
| 124 | |
| 125 | return lfsr_value; |
| 126 | } |
| 127 | |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 128 | /* |
| 129 | * IBS software randomization |
| 130 | * |
| 131 | * The IBS periodic op counter is randomized in software. The lower 12 |
| 132 | * bits of the 20 bit counter are randomized. IbsOpCurCnt is |
| 133 | * initialized with a 12 bit random value. |
| 134 | */ |
| 135 | static inline u64 op_amd_randomize_ibs_op(u64 val) |
| 136 | { |
| 137 | unsigned int random = lfsr_random(); |
| 138 | |
| 139 | if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) |
| 140 | /* |
| 141 | * Work around if the hw can not write to IbsOpCurCnt |
| 142 | * |
| 143 | * Randomize the lower 8 bits of the 16 bit |
| 144 | * IbsOpMaxCnt [15:0] value in the range of -128 to |
| 145 | * +127 by adding/subtracting an offset to the |
| 146 | * maximum count (IbsOpMaxCnt). |
| 147 | * |
| 148 | * To avoid over or underflows and protect upper bits |
| 149 | * starting at bit 16, the initial value for |
| 150 | * IbsOpMaxCnt must fit in the range from 0x0081 to |
| 151 | * 0xff80. |
| 152 | */ |
| 153 | val += (s8)(random >> 4); |
| 154 | else |
| 155 | val |= (u64)(random & IBS_RANDOM_MASK) << 32; |
| 156 | |
| 157 | return val; |
| 158 | } |
| 159 | |
Andrew Morton | 4680e64 | 2009-06-23 12:36:08 -0700 | [diff] [blame] | 160 | static inline void |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 161 | op_amd_handle_ibs(struct pt_regs * const regs, |
| 162 | struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 163 | { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 164 | u64 val, ctl; |
Robert Richter | 1acda87 | 2009-01-05 10:35:31 +0100 | [diff] [blame] | 165 | struct op_entry entry; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 166 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 167 | if (!ibs_caps) |
Andrew Morton | 4680e64 | 2009-06-23 12:36:08 -0700 | [diff] [blame] | 168 | return; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 169 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 170 | if (ibs_config.fetch_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 171 | rdmsrl(MSR_AMD64_IBSFETCHCTL, ctl); |
| 172 | if (ctl & IBS_FETCH_VAL) { |
| 173 | rdmsrl(MSR_AMD64_IBSFETCHLINAD, val); |
| 174 | oprofile_write_reserve(&entry, regs, val, |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 175 | IBS_FETCH_CODE, IBS_FETCH_SIZE); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 176 | oprofile_add_data64(&entry, val); |
| 177 | oprofile_add_data64(&entry, ctl); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 178 | rdmsrl(MSR_AMD64_IBSFETCHPHYSAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 179 | oprofile_add_data64(&entry, val); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 180 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 181 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 182 | /* reenable the IRQ */ |
Robert Richter | a163b10 | 2010-02-25 19:43:07 +0100 | [diff] [blame] | 183 | ctl &= ~(IBS_FETCH_VAL | IBS_FETCH_CNT); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 184 | ctl |= IBS_FETCH_ENABLE; |
| 185 | wrmsrl(MSR_AMD64_IBSFETCHCTL, ctl); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 186 | } |
| 187 | } |
| 188 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 189 | if (ibs_config.op_enabled) { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 190 | rdmsrl(MSR_AMD64_IBSOPCTL, ctl); |
| 191 | if (ctl & IBS_OP_VAL) { |
| 192 | rdmsrl(MSR_AMD64_IBSOPRIP, val); |
| 193 | oprofile_write_reserve(&entry, regs, val, |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 194 | IBS_OP_CODE, IBS_OP_SIZE); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 195 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 196 | rdmsrl(MSR_AMD64_IBSOPDATA, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 197 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 198 | rdmsrl(MSR_AMD64_IBSOPDATA2, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 199 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 200 | rdmsrl(MSR_AMD64_IBSOPDATA3, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 201 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 202 | rdmsrl(MSR_AMD64_IBSDCLINAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 203 | oprofile_add_data64(&entry, val); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 204 | rdmsrl(MSR_AMD64_IBSDCPHYSAD, val); |
Robert Richter | 51563a0 | 2009-06-03 20:54:56 +0200 | [diff] [blame] | 205 | oprofile_add_data64(&entry, val); |
Robert Richter | 14f0ca8 | 2009-01-07 21:50:22 +0100 | [diff] [blame] | 206 | oprofile_write_commit(&entry); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 207 | |
| 208 | /* reenable the IRQ */ |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 209 | ctl = op_amd_randomize_ibs_op(ibs_op_ctl); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 210 | wrmsrl(MSR_AMD64_IBSOPCTL, ctl); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 211 | } |
| 212 | } |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 213 | } |
| 214 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 215 | static inline void op_amd_start_ibs(void) |
| 216 | { |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 217 | u64 val; |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 218 | |
| 219 | if (!ibs_caps) |
| 220 | return; |
| 221 | |
| 222 | if (ibs_config.fetch_enabled) { |
Robert Richter | a163b10 | 2010-02-25 19:43:07 +0100 | [diff] [blame] | 223 | val = (ibs_config.max_cnt_fetch >> 4) & IBS_FETCH_MAX_CNT; |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 224 | val |= ibs_config.rand_en ? IBS_FETCH_RAND_EN : 0; |
| 225 | val |= IBS_FETCH_ENABLE; |
| 226 | wrmsrl(MSR_AMD64_IBSFETCHCTL, val); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 227 | } |
| 228 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 229 | if (ibs_config.op_enabled) { |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 230 | ibs_op_ctl = ibs_config.max_cnt_op >> 4; |
| 231 | if (!(ibs_caps & IBS_CAPS_RDWROPCNT)) { |
| 232 | /* |
| 233 | * IbsOpCurCnt not supported. See |
| 234 | * op_amd_randomize_ibs_op() for details. |
| 235 | */ |
| 236 | ibs_op_ctl = clamp(ibs_op_ctl, 0x0081ULL, 0xFF80ULL); |
| 237 | } else { |
| 238 | /* |
| 239 | * The start value is randomized with a |
| 240 | * positive offset, we need to compensate it |
| 241 | * with the half of the randomized range. Also |
| 242 | * avoid underflows. |
| 243 | */ |
| 244 | ibs_op_ctl = min(ibs_op_ctl + IBS_RANDOM_MAXCNT_OFFSET, |
Robert Richter | a163b10 | 2010-02-25 19:43:07 +0100 | [diff] [blame] | 245 | IBS_OP_MAX_CNT); |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 246 | } |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 247 | if (ibs_caps & IBS_CAPS_OPCNT && ibs_config.dispatched_ops) |
Robert Richter | ba52078 | 2010-02-23 15:46:49 +0100 | [diff] [blame] | 248 | ibs_op_ctl |= IBS_OP_CNT_CTL; |
| 249 | ibs_op_ctl |= IBS_OP_ENABLE; |
| 250 | val = op_amd_randomize_ibs_op(ibs_op_ctl); |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 251 | wrmsrl(MSR_AMD64_IBSOPCTL, val); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 252 | } |
| 253 | } |
| 254 | |
| 255 | static void op_amd_stop_ibs(void) |
| 256 | { |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 257 | if (!ibs_caps) |
| 258 | return; |
| 259 | |
| 260 | if (ibs_config.fetch_enabled) |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 261 | /* clear max count and enable */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 262 | wrmsrl(MSR_AMD64_IBSFETCHCTL, 0); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 263 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 264 | if (ibs_config.op_enabled) |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 265 | /* clear max count and enable */ |
Robert Richter | c572ae4 | 2009-06-03 20:10:39 +0200 | [diff] [blame] | 266 | wrmsrl(MSR_AMD64_IBSOPCTL, 0); |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 267 | } |
| 268 | |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 269 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
| 270 | |
| 271 | static void op_mux_switch_ctrl(struct op_x86_model_spec const *model, |
| 272 | struct op_msrs const * const msrs) |
| 273 | { |
| 274 | u64 val; |
| 275 | int i; |
| 276 | |
| 277 | /* enable active counters */ |
| 278 | for (i = 0; i < NUM_COUNTERS; ++i) { |
| 279 | int virt = op_x86_phys_to_virt(i); |
| 280 | if (!reset_value[virt]) |
| 281 | continue; |
| 282 | rdmsrl(msrs->controls[i].addr, val); |
| 283 | val &= model->reserved; |
| 284 | val |= op_x86_get_ctrl(model, &counter_config[virt]); |
| 285 | wrmsrl(msrs->controls[i].addr, val); |
| 286 | } |
| 287 | } |
| 288 | |
| 289 | #endif |
| 290 | |
| 291 | /* functions for op_amd_spec */ |
| 292 | |
| 293 | static void op_amd_shutdown(struct op_msrs const * const msrs) |
| 294 | { |
| 295 | int i; |
| 296 | |
| 297 | for (i = 0; i < NUM_COUNTERS; ++i) { |
| 298 | if (!msrs->counters[i].addr) |
| 299 | continue; |
| 300 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); |
| 301 | release_evntsel_nmi(MSR_K7_EVNTSEL0 + i); |
| 302 | } |
| 303 | } |
| 304 | |
| 305 | static int op_amd_fill_in_addresses(struct op_msrs * const msrs) |
| 306 | { |
| 307 | int i; |
| 308 | |
| 309 | for (i = 0; i < NUM_COUNTERS; i++) { |
| 310 | if (!reserve_perfctr_nmi(MSR_K7_PERFCTR0 + i)) |
| 311 | goto fail; |
| 312 | if (!reserve_evntsel_nmi(MSR_K7_EVNTSEL0 + i)) { |
| 313 | release_perfctr_nmi(MSR_K7_PERFCTR0 + i); |
| 314 | goto fail; |
| 315 | } |
| 316 | /* both registers must be reserved */ |
| 317 | msrs->counters[i].addr = MSR_K7_PERFCTR0 + i; |
| 318 | msrs->controls[i].addr = MSR_K7_EVNTSEL0 + i; |
| 319 | continue; |
| 320 | fail: |
| 321 | if (!counter_config[i].enabled) |
| 322 | continue; |
| 323 | op_x86_warn_reserved(i); |
| 324 | op_amd_shutdown(msrs); |
| 325 | return -EBUSY; |
| 326 | } |
| 327 | |
| 328 | return 0; |
| 329 | } |
| 330 | |
| 331 | static void op_amd_setup_ctrs(struct op_x86_model_spec const *model, |
| 332 | struct op_msrs const * const msrs) |
| 333 | { |
| 334 | u64 val; |
| 335 | int i; |
| 336 | |
| 337 | /* setup reset_value */ |
| 338 | for (i = 0; i < NUM_VIRT_COUNTERS; ++i) { |
| 339 | if (counter_config[i].enabled |
| 340 | && msrs->counters[op_x86_virt_to_phys(i)].addr) |
| 341 | reset_value[i] = counter_config[i].count; |
| 342 | else |
| 343 | reset_value[i] = 0; |
| 344 | } |
| 345 | |
| 346 | /* clear all counters */ |
| 347 | for (i = 0; i < NUM_COUNTERS; ++i) { |
| 348 | if (!msrs->controls[i].addr) |
| 349 | continue; |
| 350 | rdmsrl(msrs->controls[i].addr, val); |
| 351 | if (val & ARCH_PERFMON_EVENTSEL_ENABLE) |
| 352 | op_x86_warn_in_use(i); |
| 353 | val &= model->reserved; |
| 354 | wrmsrl(msrs->controls[i].addr, val); |
| 355 | /* |
| 356 | * avoid a false detection of ctr overflows in NMI |
| 357 | * handler |
| 358 | */ |
| 359 | wrmsrl(msrs->counters[i].addr, -1LL); |
| 360 | } |
| 361 | |
| 362 | /* enable active counters */ |
| 363 | for (i = 0; i < NUM_COUNTERS; ++i) { |
| 364 | int virt = op_x86_phys_to_virt(i); |
| 365 | if (!reset_value[virt]) |
| 366 | continue; |
| 367 | |
| 368 | /* setup counter registers */ |
| 369 | wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); |
| 370 | |
| 371 | /* setup control registers */ |
| 372 | rdmsrl(msrs->controls[i].addr, val); |
| 373 | val &= model->reserved; |
| 374 | val |= op_x86_get_ctrl(model, &counter_config[virt]); |
| 375 | wrmsrl(msrs->controls[i].addr, val); |
| 376 | } |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 377 | |
| 378 | if (ibs_caps) |
| 379 | setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_NMI, 0); |
| 380 | } |
| 381 | |
| 382 | static void op_amd_cpu_shutdown(void) |
| 383 | { |
| 384 | if (ibs_caps) |
| 385 | setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1); |
Robert Richter | da759fe | 2010-02-26 10:54:56 +0100 | [diff] [blame] | 386 | } |
| 387 | |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 388 | static int op_amd_check_ctrs(struct pt_regs * const regs, |
| 389 | struct op_msrs const * const msrs) |
| 390 | { |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 391 | u64 val; |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 392 | int i; |
| 393 | |
Robert Richter | 6e63ea4 | 2009-07-07 19:25:39 +0200 | [diff] [blame] | 394 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 395 | int virt = op_x86_phys_to_virt(i); |
| 396 | if (!reset_value[virt]) |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 397 | continue; |
Robert Richter | 42399ad | 2009-05-25 17:59:06 +0200 | [diff] [blame] | 398 | rdmsrl(msrs->counters[i].addr, val); |
| 399 | /* bit is clear if overflowed: */ |
| 400 | if (val & OP_CTR_OVERFLOW) |
| 401 | continue; |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 402 | oprofile_add_sample(regs, virt); |
| 403 | wrmsrl(msrs->counters[i].addr, -(u64)reset_value[virt]); |
Robert Richter | 7939d2b | 2008-07-22 21:08:56 +0200 | [diff] [blame] | 404 | } |
| 405 | |
| 406 | op_amd_handle_ibs(regs, msrs); |
| 407 | |
| 408 | /* See op_model_ppro.c */ |
| 409 | return 1; |
| 410 | } |
Paolo Ciarrocchi | d441373 | 2008-02-19 23:51:27 +0100 | [diff] [blame] | 411 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 412 | static void op_amd_start(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 413 | { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 414 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 415 | int i; |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 416 | |
Robert Richter | 6e63ea4 | 2009-07-07 19:25:39 +0200 | [diff] [blame] | 417 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 418 | if (!reset_value[op_x86_phys_to_virt(i)]) |
| 419 | continue; |
| 420 | rdmsrl(msrs->controls[i].addr, val); |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 421 | val |= ARCH_PERFMON_EVENTSEL_ENABLE; |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 422 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 423 | } |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 424 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 425 | op_amd_start_ibs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 426 | } |
| 427 | |
Robert Richter | 6657fe4 | 2008-07-22 21:08:50 +0200 | [diff] [blame] | 428 | static void op_amd_stop(struct op_msrs const * const msrs) |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 429 | { |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 430 | u64 val; |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 431 | int i; |
| 432 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 433 | /* |
| 434 | * Subtle: stop on all counters to avoid race with setting our |
| 435 | * pm callback |
| 436 | */ |
Robert Richter | 6e63ea4 | 2009-07-07 19:25:39 +0200 | [diff] [blame] | 437 | for (i = 0; i < NUM_COUNTERS; ++i) { |
Robert Richter | d8471ad | 2009-07-16 13:04:43 +0200 | [diff] [blame] | 438 | if (!reset_value[op_x86_phys_to_virt(i)]) |
Don Zickus | cb9c448 | 2006-09-26 10:52:26 +0200 | [diff] [blame] | 439 | continue; |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 440 | rdmsrl(msrs->controls[i].addr, val); |
Robert Richter | bb1165d | 2010-03-01 14:21:23 +0100 | [diff] [blame] | 441 | val &= ~ARCH_PERFMON_EVENTSEL_ENABLE; |
Robert Richter | dea3766 | 2009-05-25 18:11:52 +0200 | [diff] [blame] | 442 | wrmsrl(msrs->controls[i].addr, val); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 443 | } |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 444 | |
Robert Richter | 9063759 | 2009-03-10 19:15:57 +0100 | [diff] [blame] | 445 | op_amd_stop_ibs(); |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 446 | } |
| 447 | |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 448 | static int __init_ibs_nmi(void) |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 449 | { |
| 450 | #define IBSCTL_LVTOFFSETVAL (1 << 8) |
| 451 | #define IBSCTL 0x1cc |
| 452 | struct pci_dev *cpu_cfg; |
| 453 | int nodes; |
| 454 | u32 value = 0; |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 455 | u8 ibs_eilvt_off; |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 456 | |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 457 | ibs_eilvt_off = setup_APIC_eilvt_ibs(0, APIC_EILVT_MSG_FIX, 1); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 458 | |
| 459 | nodes = 0; |
| 460 | cpu_cfg = NULL; |
| 461 | do { |
| 462 | cpu_cfg = pci_get_device(PCI_VENDOR_ID_AMD, |
| 463 | PCI_DEVICE_ID_AMD_10H_NB_MISC, |
| 464 | cpu_cfg); |
| 465 | if (!cpu_cfg) |
| 466 | break; |
| 467 | ++nodes; |
| 468 | pci_write_config_dword(cpu_cfg, IBSCTL, ibs_eilvt_off |
| 469 | | IBSCTL_LVTOFFSETVAL); |
| 470 | pci_read_config_dword(cpu_cfg, IBSCTL, &value); |
| 471 | if (value != (ibs_eilvt_off | IBSCTL_LVTOFFSETVAL)) { |
Robert Richter | 83bd924 | 2008-12-15 15:09:50 +0100 | [diff] [blame] | 472 | pci_dev_put(cpu_cfg); |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 473 | printk(KERN_DEBUG "Failed to setup IBS LVT offset, " |
| 474 | "IBSCTL = 0x%08x", value); |
| 475 | return 1; |
| 476 | } |
| 477 | } while (1); |
| 478 | |
| 479 | if (!nodes) { |
| 480 | printk(KERN_DEBUG "No CPU node configured for IBS"); |
| 481 | return 1; |
| 482 | } |
| 483 | |
Robert Richter | 7d77f2d | 2008-07-22 21:08:57 +0200 | [diff] [blame] | 484 | return 0; |
| 485 | } |
| 486 | |
Robert Richter | fd13f6c | 2008-10-19 21:00:09 +0200 | [diff] [blame] | 487 | /* initialize the APIC for the IBS interrupts if available */ |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 488 | static void init_ibs(void) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 489 | { |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 490 | ibs_caps = get_ibs_caps(); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 491 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 492 | if (!ibs_caps) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 493 | return; |
| 494 | |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 495 | if (__init_ibs_nmi()) { |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 496 | ibs_caps = 0; |
Robert Richter | 852402c | 2008-07-22 21:09:06 +0200 | [diff] [blame] | 497 | return; |
| 498 | } |
| 499 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 500 | printk(KERN_INFO "oprofile: AMD IBS detected (0x%08x)\n", |
| 501 | (unsigned)ibs_caps); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 502 | } |
| 503 | |
Robert Richter | 25ad2913 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 504 | static int (*create_arch_files)(struct super_block *sb, struct dentry *root); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 505 | |
Robert Richter | 25ad2913 | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 506 | static int setup_ibs_files(struct super_block *sb, struct dentry *root) |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 507 | { |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 508 | struct dentry *dir; |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 509 | int ret = 0; |
| 510 | |
| 511 | /* architecture specific files */ |
| 512 | if (create_arch_files) |
| 513 | ret = create_arch_files(sb, root); |
| 514 | |
| 515 | if (ret) |
| 516 | return ret; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 517 | |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 518 | if (!ibs_caps) |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 519 | return ret; |
| 520 | |
| 521 | /* model specific files */ |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 522 | |
| 523 | /* setup some reasonable defaults */ |
| 524 | ibs_config.max_cnt_fetch = 250000; |
| 525 | ibs_config.fetch_enabled = 0; |
| 526 | ibs_config.max_cnt_op = 250000; |
| 527 | ibs_config.op_enabled = 0; |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 528 | ibs_config.dispatched_ops = 0; |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 529 | |
| 530 | dir = oprofilefs_mkdir(sb, root, "ibs_fetch"); |
| 531 | oprofilefs_create_ulong(sb, dir, "enable", |
| 532 | &ibs_config.fetch_enabled); |
| 533 | oprofilefs_create_ulong(sb, dir, "max_count", |
| 534 | &ibs_config.max_cnt_fetch); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 535 | oprofilefs_create_ulong(sb, dir, "rand_enable", |
| 536 | &ibs_config.rand_en); |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 537 | |
Robert Richter | ccd755c | 2008-07-29 16:57:10 +0200 | [diff] [blame] | 538 | dir = oprofilefs_mkdir(sb, root, "ibs_op"); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 539 | oprofilefs_create_ulong(sb, dir, "enable", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 540 | &ibs_config.op_enabled); |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 541 | oprofilefs_create_ulong(sb, dir, "max_count", |
Robert Richter | 2d55a47 | 2008-07-18 17:56:05 +0200 | [diff] [blame] | 542 | &ibs_config.max_cnt_op); |
Robert Richter | 64683da | 2010-02-04 10:57:23 +0100 | [diff] [blame] | 543 | if (ibs_caps & IBS_CAPS_OPCNT) |
| 544 | oprofilefs_create_ulong(sb, dir, "dispatched_ops", |
| 545 | &ibs_config.dispatched_ops); |
Robert Richter | fc2bd73 | 2008-07-22 21:09:00 +0200 | [diff] [blame] | 546 | |
| 547 | return 0; |
Barry Kasindorf | 56784f1 | 2008-07-22 21:08:55 +0200 | [diff] [blame] | 548 | } |
| 549 | |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 550 | static int op_amd_init(struct oprofile_operations *ops) |
| 551 | { |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 552 | init_ibs(); |
Robert Richter | 270d3e1 | 2008-07-22 21:09:01 +0200 | [diff] [blame] | 553 | create_arch_files = ops->create_files; |
| 554 | ops->create_files = setup_ibs_files; |
Robert Richter | adf5ec0 | 2008-07-22 21:08:48 +0200 | [diff] [blame] | 555 | return 0; |
| 556 | } |
| 557 | |
Robert Richter | 259a83a | 2009-07-09 15:12:35 +0200 | [diff] [blame] | 558 | struct op_x86_model_spec op_amd_spec = { |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 559 | .num_counters = NUM_COUNTERS, |
Robert Richter | d0e4120 | 2010-03-23 19:33:21 +0100 | [diff] [blame] | 560 | .num_controls = NUM_COUNTERS, |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 561 | .num_virt_counters = NUM_VIRT_COUNTERS, |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 562 | .reserved = MSR_AMD_EVENTSEL_RESERVED, |
| 563 | .event_mask = OP_EVENT_MASK, |
| 564 | .init = op_amd_init, |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 565 | .fill_in_addresses = &op_amd_fill_in_addresses, |
| 566 | .setup_ctrs = &op_amd_setup_ctrs, |
Robert Richter | bae663b | 2010-05-05 17:47:17 +0200 | [diff] [blame] | 567 | .cpu_down = &op_amd_cpu_shutdown, |
Robert Richter | c92960f | 2008-09-05 17:12:36 +0200 | [diff] [blame] | 568 | .check_ctrs = &op_amd_check_ctrs, |
| 569 | .start = &op_amd_start, |
| 570 | .stop = &op_amd_stop, |
Robert Richter | 3370d35 | 2009-05-25 15:10:32 +0200 | [diff] [blame] | 571 | .shutdown = &op_amd_shutdown, |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 572 | #ifdef CONFIG_OPROFILE_EVENT_MULTIPLEX |
Robert Richter | 7e7478c | 2009-07-16 13:09:53 +0200 | [diff] [blame] | 573 | .switch_ctrl = &op_mux_switch_ctrl, |
Jason Yeh | 4d4036e | 2009-07-08 13:49:38 +0200 | [diff] [blame] | 574 | #endif |
Linus Torvalds | 1da177e | 2005-04-16 15:20:36 -0700 | [diff] [blame] | 575 | }; |