H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 1 | #ifndef _ASM_X86_IRQ_VECTORS_H |
| 2 | #define _ASM_X86_IRQ_VECTORS_H |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 3 | |
Shaohua Li | 60f6e65 | 2011-01-17 10:52:02 +0800 | [diff] [blame] | 4 | #include <linux/threads.h> |
Ingo Molnar | 9fc2e79 | 2009-01-31 02:48:17 +0100 | [diff] [blame] | 5 | /* |
| 6 | * Linux IRQ vector layout. |
| 7 | * |
| 8 | * There are 256 IDT entries (per CPU - each entry is 8 bytes) which can |
| 9 | * be defined by Linux. They are used as a jump table by the CPU when a |
| 10 | * given vector is triggered - by a CPU-external, CPU-internal or |
| 11 | * software-triggered event. |
| 12 | * |
| 13 | * Linux sets the kernel code address each entry jumps to early during |
| 14 | * bootup, and never changes them. This is the general layout of the |
| 15 | * IDT entries: |
| 16 | * |
| 17 | * Vectors 0 ... 31 : system traps and exceptions - hardcoded events |
| 18 | * Vectors 32 ... 127 : device interrupts |
| 19 | * Vector 128 : legacy int80 syscall interface |
Shaohua Li | 70e4a36 | 2011-01-17 10:52:07 +0800 | [diff] [blame] | 20 | * Vectors 129 ... INVALIDATE_TLB_VECTOR_START-1 : device interrupts |
| 21 | * Vectors INVALIDATE_TLB_VECTOR_START ... 255 : special interrupts |
Ingo Molnar | 9fc2e79 | 2009-01-31 02:48:17 +0100 | [diff] [blame] | 22 | * |
| 23 | * 64-bit x86 has per CPU IDT tables, 32-bit has one shared IDT table. |
| 24 | * |
| 25 | * This file enumerates the exact layout of them: |
| 26 | */ |
| 27 | |
| 28 | #define NMI_VECTOR 0x02 |
Andi Kleen | 8fa8dd9 | 2009-05-27 21:56:58 +0200 | [diff] [blame] | 29 | #define MCE_VECTOR 0x12 |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 30 | |
| 31 | /* |
Suresh Siddha | 6579b47 | 2010-01-13 16:19:11 -0800 | [diff] [blame] | 32 | * IDT vectors usable for external interrupt sources start at 0x20. |
| 33 | * (0x80 is the syscall vector, 0x30-0x3f are for ISA) |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 34 | */ |
Suresh Siddha | 6579b47 | 2010-01-13 16:19:11 -0800 | [diff] [blame] | 35 | #define FIRST_EXTERNAL_VECTOR 0x20 |
| 36 | /* |
| 37 | * We start allocating at 0x21 to spread out vectors evenly between |
| 38 | * priority levels. (0x80 is the syscall vector) |
| 39 | */ |
| 40 | #define VECTOR_OFFSET_START 1 |
| 41 | |
| 42 | /* |
| 43 | * Reserve the lowest usable vector (and hence lowest priority) 0x20 for |
| 44 | * triggering cleanup after irq migration. 0x21-0x2f will still be used |
| 45 | * for device interrupts. |
| 46 | */ |
| 47 | #define IRQ_MOVE_CLEANUP_VECTOR FIRST_EXTERNAL_VECTOR |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 48 | |
H. Peter Anvin | 99d113b | 2010-01-04 16:16:06 -0800 | [diff] [blame] | 49 | #define IA32_SYSCALL_VECTOR 0x80 |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 50 | #ifdef CONFIG_X86_32 |
Ingo Molnar | 9fc2e79 | 2009-01-31 02:48:17 +0100 | [diff] [blame] | 51 | # define SYSCALL_VECTOR 0x80 |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 52 | #endif |
| 53 | |
| 54 | /* |
Suresh Siddha | 6579b47 | 2010-01-13 16:19:11 -0800 | [diff] [blame] | 55 | * Vectors 0x30-0x3f are used for ISA interrupts. |
H. Peter Anvin | 99d113b | 2010-01-04 16:16:06 -0800 | [diff] [blame] | 56 | * round up to the next 16-vector boundary |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 57 | */ |
H. Peter Anvin | 99d113b | 2010-01-04 16:16:06 -0800 | [diff] [blame] | 58 | #define IRQ0_VECTOR ((FIRST_EXTERNAL_VECTOR + 16) & ~15) |
Ingo Molnar | 9fc2e79 | 2009-01-31 02:48:17 +0100 | [diff] [blame] | 59 | |
| 60 | #define IRQ1_VECTOR (IRQ0_VECTOR + 1) |
| 61 | #define IRQ2_VECTOR (IRQ0_VECTOR + 2) |
| 62 | #define IRQ3_VECTOR (IRQ0_VECTOR + 3) |
| 63 | #define IRQ4_VECTOR (IRQ0_VECTOR + 4) |
| 64 | #define IRQ5_VECTOR (IRQ0_VECTOR + 5) |
| 65 | #define IRQ6_VECTOR (IRQ0_VECTOR + 6) |
| 66 | #define IRQ7_VECTOR (IRQ0_VECTOR + 7) |
| 67 | #define IRQ8_VECTOR (IRQ0_VECTOR + 8) |
| 68 | #define IRQ9_VECTOR (IRQ0_VECTOR + 9) |
| 69 | #define IRQ10_VECTOR (IRQ0_VECTOR + 10) |
| 70 | #define IRQ11_VECTOR (IRQ0_VECTOR + 11) |
| 71 | #define IRQ12_VECTOR (IRQ0_VECTOR + 12) |
| 72 | #define IRQ13_VECTOR (IRQ0_VECTOR + 13) |
| 73 | #define IRQ14_VECTOR (IRQ0_VECTOR + 14) |
| 74 | #define IRQ15_VECTOR (IRQ0_VECTOR + 15) |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 75 | |
| 76 | /* |
| 77 | * Special IRQ vectors used by the SMP architecture, 0xf0-0xff |
| 78 | * |
| 79 | * some of the following vectors are 'rare', they are merged |
| 80 | * into a single vector (CALL_FUNCTION_VECTOR) to save vector space. |
| 81 | * TLB, reschedule and local APIC vectors are performance-critical. |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 82 | */ |
Ingo Molnar | 5da690d | 2009-01-31 02:10:03 +0100 | [diff] [blame] | 83 | |
| 84 | #define SPURIOUS_APIC_VECTOR 0xff |
Ingo Molnar | 647ad94 | 2009-01-31 02:06:50 +0100 | [diff] [blame] | 85 | /* |
| 86 | * Sanity check |
| 87 | */ |
| 88 | #if ((SPURIOUS_APIC_VECTOR & 0x0F) != 0x0F) |
| 89 | # error SPURIOUS_APIC_VECTOR definition error |
| 90 | #endif |
| 91 | |
Ingo Molnar | 5da690d | 2009-01-31 02:10:03 +0100 | [diff] [blame] | 92 | #define ERROR_APIC_VECTOR 0xfe |
| 93 | #define RESCHEDULE_VECTOR 0xfd |
| 94 | #define CALL_FUNCTION_VECTOR 0xfc |
| 95 | #define CALL_FUNCTION_SINGLE_VECTOR 0xfb |
| 96 | #define THERMAL_APIC_VECTOR 0xfa |
Andi Kleen | 7856f6c | 2009-04-28 23:32:56 +0200 | [diff] [blame] | 97 | #define THRESHOLD_APIC_VECTOR 0xf9 |
Andi Kleen | 4ef702c | 2009-05-27 21:56:52 +0200 | [diff] [blame] | 98 | #define REBOOT_VECTOR 0xf8 |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 99 | |
Shaohua Li | 60f6e65 | 2011-01-17 10:52:02 +0800 | [diff] [blame] | 100 | /* |
| 101 | * Generic system vector for platform specific use |
| 102 | */ |
| 103 | #define X86_PLATFORM_IPI_VECTOR 0xf7 |
| 104 | |
| 105 | /* |
| 106 | * IRQ work vector: |
| 107 | */ |
| 108 | #define IRQ_WORK_VECTOR 0xf6 |
| 109 | |
| 110 | #define UV_BAU_MESSAGE 0xf5 |
| 111 | |
| 112 | /* |
| 113 | * Self IPI vector for machine checks |
| 114 | */ |
| 115 | #define MCE_SELF_VECTOR 0xf4 |
| 116 | |
| 117 | /* Xen vector callback to receive events in a HVM domain */ |
| 118 | #define XEN_HVM_EVTCHN_CALLBACK 0xf3 |
Ingo Molnar | 5da690d | 2009-01-31 02:10:03 +0100 | [diff] [blame] | 119 | |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 120 | /* |
| 121 | * Local APIC timer IRQ vector is on a different priority level, |
| 122 | * to work around the 'lost local interrupt if more than 2 IRQ |
| 123 | * sources per level' errata. |
| 124 | */ |
Ingo Molnar | 9fc2e79 | 2009-01-31 02:48:17 +0100 | [diff] [blame] | 125 | #define LOCAL_TIMER_VECTOR 0xef |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 126 | |
Shaohua Li | 70e4a36 | 2011-01-17 10:52:07 +0800 | [diff] [blame] | 127 | /* up to 32 vectors used for spreading out TLB flushes: */ |
| 128 | #if NR_CPUS <= 32 |
Jan Beulich | d04c579 | 2011-03-03 10:55:29 +0000 | [diff] [blame] | 129 | # define NUM_INVALIDATE_TLB_VECTORS (NR_CPUS) |
Shaohua Li | 70e4a36 | 2011-01-17 10:52:07 +0800 | [diff] [blame] | 130 | #else |
Jan Beulich | d04c579 | 2011-03-03 10:55:29 +0000 | [diff] [blame] | 131 | # define NUM_INVALIDATE_TLB_VECTORS (32) |
Shaohua Li | 70e4a36 | 2011-01-17 10:52:07 +0800 | [diff] [blame] | 132 | #endif |
| 133 | |
Jan Beulich | d04c579 | 2011-03-03 10:55:29 +0000 | [diff] [blame] | 134 | #define INVALIDATE_TLB_VECTOR_END (0xee) |
Shaohua Li | 60f6e65 | 2011-01-17 10:52:02 +0800 | [diff] [blame] | 135 | #define INVALIDATE_TLB_VECTOR_START \ |
Jan Beulich | d04c579 | 2011-03-03 10:55:29 +0000 | [diff] [blame] | 136 | (INVALIDATE_TLB_VECTOR_END-NUM_INVALIDATE_TLB_VECTORS+1) |
Sheng Yang | 38e20b0 | 2010-05-14 12:40:51 +0100 | [diff] [blame] | 137 | |
Ingo Molnar | 9fc2e79 | 2009-01-31 02:48:17 +0100 | [diff] [blame] | 138 | #define NR_VECTORS 256 |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 139 | |
Ingo Molnar | 9fc2e79 | 2009-01-31 02:48:17 +0100 | [diff] [blame] | 140 | #define FPU_IRQ 13 |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 141 | |
Ingo Molnar | 9fc2e79 | 2009-01-31 02:48:17 +0100 | [diff] [blame] | 142 | #define FIRST_VM86_IRQ 3 |
| 143 | #define LAST_VM86_IRQ 15 |
Ingo Molnar | d8106d2 | 2009-01-31 03:06:17 +0100 | [diff] [blame] | 144 | |
| 145 | #ifndef __ASSEMBLY__ |
| 146 | static inline int invalid_vm86_irq(int irq) |
| 147 | { |
Cyrill Gorcunov | 57e3729 | 2009-02-23 22:56:59 +0300 | [diff] [blame] | 148 | return irq < FIRST_VM86_IRQ || irq > LAST_VM86_IRQ; |
Ingo Molnar | d8106d2 | 2009-01-31 03:06:17 +0100 | [diff] [blame] | 149 | } |
| 150 | #endif |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 151 | |
Ingo Molnar | 009eb3f | 2009-01-31 02:56:44 +0100 | [diff] [blame] | 152 | /* |
| 153 | * Size the maximum number of interrupts. |
| 154 | * |
| 155 | * If the irq_desc[] array has a sparse layout, we can size things |
| 156 | * generously - it scales up linearly with the maximum number of CPUs, |
| 157 | * and the maximum number of IO-APICs, whichever is higher. |
| 158 | * |
| 159 | * In other cases we size more conservatively, to not create too large |
| 160 | * static arrays. |
| 161 | */ |
| 162 | |
Ingo Molnar | 9fc2e79 | 2009-01-31 02:48:17 +0100 | [diff] [blame] | 163 | #define NR_IRQS_LEGACY 16 |
Yinghai Lu | 99d093d | 2008-12-05 18:58:32 -0800 | [diff] [blame] | 164 | |
Ingo Molnar | 009eb3f | 2009-01-31 02:56:44 +0100 | [diff] [blame] | 165 | #define IO_APIC_VECTOR_LIMIT ( 32 * MAX_IO_APICS ) |
| 166 | |
Ingo Molnar | 3e92ab3 | 2009-01-31 02:21:42 +0100 | [diff] [blame] | 167 | #ifdef CONFIG_X86_IO_APIC |
Ingo Molnar | 009eb3f | 2009-01-31 02:56:44 +0100 | [diff] [blame] | 168 | # ifdef CONFIG_SPARSE_IRQ |
Yinghai Lu | 9959c88 | 2009-12-28 21:08:29 -0800 | [diff] [blame] | 169 | # define CPU_VECTOR_LIMIT (64 * NR_CPUS) |
Ingo Molnar | c379698 | 2009-01-31 02:50:46 +0100 | [diff] [blame] | 170 | # define NR_IRQS \ |
Ingo Molnar | 009eb3f | 2009-01-31 02:56:44 +0100 | [diff] [blame] | 171 | (CPU_VECTOR_LIMIT > IO_APIC_VECTOR_LIMIT ? \ |
| 172 | (NR_VECTORS + CPU_VECTOR_LIMIT) : \ |
| 173 | (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) |
| 174 | # else |
Yinghai Lu | 9959c88 | 2009-12-28 21:08:29 -0800 | [diff] [blame] | 175 | # define CPU_VECTOR_LIMIT (32 * NR_CPUS) |
| 176 | # define NR_IRQS \ |
| 177 | (CPU_VECTOR_LIMIT < IO_APIC_VECTOR_LIMIT ? \ |
| 178 | (NR_VECTORS + CPU_VECTOR_LIMIT) : \ |
| 179 | (NR_VECTORS + IO_APIC_VECTOR_LIMIT)) |
Ingo Molnar | c379698 | 2009-01-31 02:50:46 +0100 | [diff] [blame] | 180 | # endif |
Ingo Molnar | 3e92ab3 | 2009-01-31 02:21:42 +0100 | [diff] [blame] | 181 | #else /* !CONFIG_X86_IO_APIC: */ |
Ingo Molnar | 009eb3f | 2009-01-31 02:56:44 +0100 | [diff] [blame] | 182 | # define NR_IRQS NR_IRQS_LEGACY |
Yinghai Lu | 1b48976 | 2008-11-04 14:10:13 -0800 | [diff] [blame] | 183 | #endif |
Thomas Gleixner | 9b7dc56 | 2008-05-02 20:10:09 +0200 | [diff] [blame] | 184 | |
H. Peter Anvin | 1965aae | 2008-10-22 22:26:29 -0700 | [diff] [blame] | 185 | #endif /* _ASM_X86_IRQ_VECTORS_H */ |