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gerrit-public.fairphone.software / kernel / msm-4.9 / d6b9c591940cd7c03724999c72f31fd92c0dee59 / . / arch / arm / boot / dts / imx6q.dtsi
blob: ddc78de6a0bece453c561ecf2250eea3d48a0af1 [file] [log] [blame]
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1/*
2 * Copyright 2011 Freescale Semiconductor, Inc.
3 * Copyright 2011 Linaro Ltd.
4 *
5 * The code contained herein is licensed under the GNU General Public
6 * License. You may obtain a copy of the GNU General Public License
7 * Version 2 or later at the following locations:
8 *
9 * http://www.opensource.org/licenses/gpl-license.html
10 * http://www.gnu.org/copyleft/gpl.html
11 */
12
13/include/ "skeleton.dtsi"
14
15/ {
16 aliases {
Richard Zhao8f9ffec2011-12-14 09:26:45 +0800[diff] [blame]17 serial0 = &uart1;
18 serial1 = &uart2;
19 serial2 = &uart3;
20 serial3 = &uart4;
21 serial4 = &uart5;
Shawn Guo5230f8f2012-08-05 14:01:28 +0800[diff] [blame]22 gpio0 = &gpio1;
23 gpio1 = &gpio2;
24 gpio2 = &gpio3;
25 gpio3 = &gpio4;
26 gpio4 = &gpio5;
27 gpio5 = &gpio6;
28 gpio6 = &gpio7;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]29 };
30
31 cpus {
32 #address-cells = <1>;
33 #size-cells = <0>;
34
35 cpu@0 {
36 compatible = "arm,cortex-a9";
37 reg = <0>;
38 next-level-cache = <&L2>;
Shawn Guod90df972012-07-19 23:16:30 +0800[diff] [blame]39 operating-points = <
40 /* kHz uV */
41 792000 1100000
42 396000 950000
43 198000 850000
44 >;
45 clock-latency = <61036>; /* two CLK32 periods */
46 cpu0-supply = <&reg_cpu>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]47 };
48
49 cpu@1 {
50 compatible = "arm,cortex-a9";
51 reg = <1>;
52 next-level-cache = <&L2>;
53 };
54
55 cpu@2 {
56 compatible = "arm,cortex-a9";
57 reg = <2>;
58 next-level-cache = <&L2>;
59 };
60
61 cpu@3 {
62 compatible = "arm,cortex-a9";
63 reg = <3>;
64 next-level-cache = <&L2>;
65 };
66 };
67
68 intc: interrupt-controller@00a01000 {
69 compatible = "arm,cortex-a9-gic";
70 #interrupt-cells = <3>;
71 #address-cells = <1>;
72 #size-cells = <1>;
73 interrupt-controller;
74 reg = <0x00a01000 0x1000>,
75 <0x00a00100 0x100>;
76 };
77
78 clocks {
79 #address-cells = <1>;
80 #size-cells = <0>;
81
82 ckil {
83 compatible = "fsl,imx-ckil", "fixed-clock";
84 clock-frequency = <32768>;
85 };
86
87 ckih1 {
88 compatible = "fsl,imx-ckih1", "fixed-clock";
89 clock-frequency = <0>;
90 };
91
92 osc {
93 compatible = "fsl,imx-osc", "fixed-clock";
94 clock-frequency = <24000000>;
95 };
96 };
97
98 soc {
99 #address-cells = <1>;
100 #size-cells = <1>;
101 compatible = "simple-bus";
102 interrupt-parent = <&intc>;
103 ranges;
104
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]105 dma-apbh@00110000 {
106 compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
107 reg = <0x00110000 0x2000>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]108 clocks = <&clks 106>;
Huang Shijiee5d0f9f2012-06-06 21:22:57 -0400[diff] [blame]109 };
110
Shawn Guobe4ccfc2012-12-31 11:32:48 +0800[diff] [blame]111 gpmi: gpmi-nand@00112000 {
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]112 compatible = "fsl,imx6q-gpmi-nand";
113 #address-cells = <1>;
114 #size-cells = <1>;
115 reg = <0x00112000 0x2000>, <0x00114000 0x2000>;
116 reg-names = "gpmi-nand", "bch";
117 interrupts = <0 13 0x04>, <0 15 0x04>;
118 interrupt-names = "gpmi-dma", "bch";
119 clocks = <&clks 152>, <&clks 153>, <&clks 151>,
120 <&clks 150>, <&clks 149>;
121 clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
122 "gpmi_bch_apb", "per1_bch";
123 fsl,gpmi-dma-channel = <0>;
124 status = "disabled";
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]125 };
126
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]127 timer@00a00600 {
Marc Zyngier58458e02012-01-10 19:44:19 +0000[diff] [blame]128 compatible = "arm,cortex-a9-twd-timer";
129 reg = <0x00a00600 0x20>;
130 interrupts = <1 13 0xf01>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]131 };
132
133 L2: l2-cache@00a02000 {
134 compatible = "arm,pl310-cache";
135 reg = <0x00a02000 0x1000>;
136 interrupts = <0 92 0x04>;
137 cache-unified;
138 cache-level = <2>;
139 };
140
141 aips-bus@02000000 { /* AIPS1 */
142 compatible = "fsl,aips-bus", "simple-bus";
143 #address-cells = <1>;
144 #size-cells = <1>;
145 reg = <0x02000000 0x100000>;
146 ranges;
147
148 spba-bus@02000000 {
149 compatible = "fsl,spba-bus", "simple-bus";
150 #address-cells = <1>;
151 #size-cells = <1>;
152 reg = <0x02000000 0x40000>;
153 ranges;
154
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]155 spdif: spdif@02004000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]156 reg = <0x02004000 0x4000>;
157 interrupts = <0 52 0x04>;
158 };
159
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]160 ecspi1: ecspi@02008000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]161 #address-cells = <1>;
162 #size-cells = <0>;
163 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
164 reg = <0x02008000 0x4000>;
165 interrupts = <0 31 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]166 clocks = <&clks 112>, <&clks 112>;
167 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]168 status = "disabled";
169 };
170
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]171 ecspi2: ecspi@0200c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]172 #address-cells = <1>;
173 #size-cells = <0>;
174 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
175 reg = <0x0200c000 0x4000>;
176 interrupts = <0 32 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]177 clocks = <&clks 113>, <&clks 113>;
178 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]179 status = "disabled";
180 };
181
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]182 ecspi3: ecspi@02010000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]183 #address-cells = <1>;
184 #size-cells = <0>;
185 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
186 reg = <0x02010000 0x4000>;
187 interrupts = <0 33 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]188 clocks = <&clks 114>, <&clks 114>;
189 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]190 status = "disabled";
191 };
192
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]193 ecspi4: ecspi@02014000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]194 #address-cells = <1>;
195 #size-cells = <0>;
196 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
197 reg = <0x02014000 0x4000>;
198 interrupts = <0 34 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]199 clocks = <&clks 115>, <&clks 115>;
200 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]201 status = "disabled";
202 };
203
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]204 ecspi5: ecspi@02018000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]205 #address-cells = <1>;
206 #size-cells = <0>;
207 compatible = "fsl,imx6q-ecspi", "fsl,imx51-ecspi";
208 reg = <0x02018000 0x4000>;
209 interrupts = <0 35 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]210 clocks = <&clks 116>, <&clks 116>;
211 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]212 status = "disabled";
213 };
214
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]215 uart1: serial@02020000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]216 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
217 reg = <0x02020000 0x4000>;
218 interrupts = <0 26 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]219 clocks = <&clks 160>, <&clks 161>;
220 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]221 status = "disabled";
222 };
223
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]224 esai: esai@02024000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]225 reg = <0x02024000 0x4000>;
226 interrupts = <0 51 0x04>;
227 };
228
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]229 ssi1: ssi@02028000 {
230 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]231 reg = <0x02028000 0x4000>;
232 interrupts = <0 46 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]233 clocks = <&clks 178>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]234 fsl,fifo-depth = <15>;
235 fsl,ssi-dma-events = <38 37>;
236 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]237 };
238
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]239 ssi2: ssi@0202c000 {
240 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]241 reg = <0x0202c000 0x4000>;
242 interrupts = <0 47 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]243 clocks = <&clks 179>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]244 fsl,fifo-depth = <15>;
245 fsl,ssi-dma-events = <42 41>;
246 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]247 };
248
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]249 ssi3: ssi@02030000 {
250 compatible = "fsl,imx6q-ssi","fsl,imx21-ssi";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]251 reg = <0x02030000 0x4000>;
252 interrupts = <0 48 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]253 clocks = <&clks 180>;
Richard Zhaob1a5da82012-05-02 10:29:10 +0800[diff] [blame]254 fsl,fifo-depth = <15>;
255 fsl,ssi-dma-events = <46 45>;
256 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]257 };
258
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]259 asrc: asrc@02034000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]260 reg = <0x02034000 0x4000>;
261 interrupts = <0 50 0x04>;
262 };
263
264 spba@0203c000 {
265 reg = <0x0203c000 0x4000>;
266 };
267 };
268
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]269 vpu: vpu@02040000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]270 reg = <0x02040000 0x3c000>;
271 interrupts = <0 3 0x04 0 12 0x04>;
272 };
273
274 aipstz@0207c000 { /* AIPSTZ1 */
275 reg = <0x0207c000 0x4000>;
276 };
277
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]278 pwm1: pwm@02080000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]279 #pwm-cells = <2>;
280 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]281 reg = <0x02080000 0x4000>;
282 interrupts = <0 83 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]283 clocks = <&clks 62>, <&clks 145>;
284 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]285 };
286
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]287 pwm2: pwm@02084000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]288 #pwm-cells = <2>;
289 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]290 reg = <0x02084000 0x4000>;
291 interrupts = <0 84 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]292 clocks = <&clks 62>, <&clks 146>;
293 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]294 };
295
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]296 pwm3: pwm@02088000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]297 #pwm-cells = <2>;
298 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]299 reg = <0x02088000 0x4000>;
300 interrupts = <0 85 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]301 clocks = <&clks 62>, <&clks 147>;
302 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]303 };
304
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]305 pwm4: pwm@0208c000 {
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]306 #pwm-cells = <2>;
307 compatible = "fsl,imx6q-pwm", "fsl,imx27-pwm";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]308 reg = <0x0208c000 0x4000>;
309 interrupts = <0 86 0x04>;
Sascha Hauer33b38582012-11-21 12:18:28 +0100[diff] [blame]310 clocks = <&clks 62>, <&clks 148>;
311 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]312 };
313
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]314 can1: flexcan@02090000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]315 reg = <0x02090000 0x4000>;
316 interrupts = <0 110 0x04>;
317 };
318
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]319 can2: flexcan@02094000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]320 reg = <0x02094000 0x4000>;
321 interrupts = <0 111 0x04>;
322 };
323
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]324 gpt: gpt@02098000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]325 compatible = "fsl,imx6q-gpt";
326 reg = <0x02098000 0x4000>;
327 interrupts = <0 55 0x04>;
328 };
329
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]330 gpio1: gpio@0209c000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]331 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]332 reg = <0x0209c000 0x4000>;
333 interrupts = <0 66 0x04 0 67 0x04>;
334 gpio-controller;
335 #gpio-cells = <2>;
336 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]337 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]338 };
339
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]340 gpio2: gpio@020a0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]341 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]342 reg = <0x020a0000 0x4000>;
343 interrupts = <0 68 0x04 0 69 0x04>;
344 gpio-controller;
345 #gpio-cells = <2>;
346 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]347 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]348 };
349
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]350 gpio3: gpio@020a4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]351 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]352 reg = <0x020a4000 0x4000>;
353 interrupts = <0 70 0x04 0 71 0x04>;
354 gpio-controller;
355 #gpio-cells = <2>;
356 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]357 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]358 };
359
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]360 gpio4: gpio@020a8000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]361 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]362 reg = <0x020a8000 0x4000>;
363 interrupts = <0 72 0x04 0 73 0x04>;
364 gpio-controller;
365 #gpio-cells = <2>;
366 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]367 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]368 };
369
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]370 gpio5: gpio@020ac000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]371 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]372 reg = <0x020ac000 0x4000>;
373 interrupts = <0 74 0x04 0 75 0x04>;
374 gpio-controller;
375 #gpio-cells = <2>;
376 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]377 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]378 };
379
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]380 gpio6: gpio@020b0000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]381 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]382 reg = <0x020b0000 0x4000>;
383 interrupts = <0 76 0x04 0 77 0x04>;
384 gpio-controller;
385 #gpio-cells = <2>;
386 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]387 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]388 };
389
Richard Zhao4d191862011-12-14 09:26:44 +0800[diff] [blame]390 gpio7: gpio@020b4000 {
Benoît Thébaudeauaeb27742012-06-22 21:04:06 +0200[diff] [blame]391 compatible = "fsl,imx6q-gpio", "fsl,imx35-gpio";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]392 reg = <0x020b4000 0x4000>;
393 interrupts = <0 78 0x04 0 79 0x04>;
394 gpio-controller;
395 #gpio-cells = <2>;
396 interrupt-controller;
Shawn Guo88cde8b2012-07-06 20:03:37 +0800[diff] [blame]397 #interrupt-cells = <2>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]398 };
399
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]400 kpp: kpp@020b8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]401 reg = <0x020b8000 0x4000>;
402 interrupts = <0 82 0x04>;
403 };
404
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]405 wdog1: wdog@020bc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]406 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
407 reg = <0x020bc000 0x4000>;
408 interrupts = <0 80 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]409 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]410 };
411
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]412 wdog2: wdog@020c0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]413 compatible = "fsl,imx6q-wdt", "fsl,imx21-wdt";
414 reg = <0x020c0000 0x4000>;
415 interrupts = <0 81 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]416 clocks = <&clks 0>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]417 status = "disabled";
418 };
419
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]420 clks: ccm@020c4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]421 compatible = "fsl,imx6q-ccm";
422 reg = <0x020c4000 0x4000>;
423 interrupts = <0 87 0x04 0 88 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]424 #clock-cells = <1>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]425 };
426
Dong Aishengbaa64152012-09-05 10:57:15 +0800[diff] [blame]427 anatop: anatop@020c8000 {
428 compatible = "fsl,imx6q-anatop", "syscon", "simple-bus";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]429 reg = <0x020c8000 0x1000>;
430 interrupts = <0 49 0x04 0 54 0x04 0 127 0x04>;
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]431
432 regulator-1p1@110 {
433 compatible = "fsl,anatop-regulator";
434 regulator-name = "vdd1p1";
435 regulator-min-microvolt = <800000>;
436 regulator-max-microvolt = <1375000>;
437 regulator-always-on;
438 anatop-reg-offset = <0x110>;
439 anatop-vol-bit-shift = <8>;
440 anatop-vol-bit-width = <5>;
441 anatop-min-bit-val = <4>;
442 anatop-min-voltage = <800000>;
443 anatop-max-voltage = <1375000>;
444 };
445
446 regulator-3p0@120 {
447 compatible = "fsl,anatop-regulator";
448 regulator-name = "vdd3p0";
449 regulator-min-microvolt = <2800000>;
450 regulator-max-microvolt = <3150000>;
451 regulator-always-on;
452 anatop-reg-offset = <0x120>;
453 anatop-vol-bit-shift = <8>;
454 anatop-vol-bit-width = <5>;
455 anatop-min-bit-val = <0>;
456 anatop-min-voltage = <2625000>;
457 anatop-max-voltage = <3400000>;
458 };
459
460 regulator-2p5@130 {
461 compatible = "fsl,anatop-regulator";
462 regulator-name = "vdd2p5";
463 regulator-min-microvolt = <2000000>;
464 regulator-max-microvolt = <2750000>;
465 regulator-always-on;
466 anatop-reg-offset = <0x130>;
467 anatop-vol-bit-shift = <8>;
468 anatop-vol-bit-width = <5>;
469 anatop-min-bit-val = <0>;
470 anatop-min-voltage = <2000000>;
471 anatop-max-voltage = <2750000>;
472 };
473
Shawn Guod90df972012-07-19 23:16:30 +0800[diff] [blame]474 reg_cpu: regulator-vddcore@140 {
Ying-Chun Liu (PaulLiu)a1e327e2012-03-30 21:46:53 +0800[diff] [blame]475 compatible = "fsl,anatop-regulator";
476 regulator-name = "cpu";
477 regulator-min-microvolt = <725000>;
478 regulator-max-microvolt = <1450000>;
479 regulator-always-on;
480 anatop-reg-offset = <0x140>;
481 anatop-vol-bit-shift = <0>;
482 anatop-vol-bit-width = <5>;
483 anatop-min-bit-val = <1>;
484 anatop-min-voltage = <725000>;
485 anatop-max-voltage = <1450000>;
486 };
487
488 regulator-vddpu@140 {
489 compatible = "fsl,anatop-regulator";
490 regulator-name = "vddpu";
491 regulator-min-microvolt = <725000>;
492 regulator-max-microvolt = <1450000>;
493 regulator-always-on;
494 anatop-reg-offset = <0x140>;
495 anatop-vol-bit-shift = <9>;
496 anatop-vol-bit-width = <5>;
497 anatop-min-bit-val = <1>;
498 anatop-min-voltage = <725000>;
499 anatop-max-voltage = <1450000>;
500 };
501
502 regulator-vddsoc@140 {
503 compatible = "fsl,anatop-regulator";
504 regulator-name = "vddsoc";
505 regulator-min-microvolt = <725000>;
506 regulator-max-microvolt = <1450000>;
507 regulator-always-on;
508 anatop-reg-offset = <0x140>;
509 anatop-vol-bit-shift = <18>;
510 anatop-vol-bit-width = <5>;
511 anatop-min-bit-val = <1>;
512 anatop-min-voltage = <725000>;
513 anatop-max-voltage = <1450000>;
514 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]515 };
516
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]517 usbphy1: usbphy@020c9000 {
518 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]519 reg = <0x020c9000 0x1000>;
520 interrupts = <0 44 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]521 clocks = <&clks 182>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]522 };
523
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]524 usbphy2: usbphy@020ca000 {
525 compatible = "fsl,imx6q-usbphy", "fsl,imx23-usbphy";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]526 reg = <0x020ca000 0x1000>;
527 interrupts = <0 45 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]528 clocks = <&clks 183>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]529 };
530
531 snvs@020cc000 {
Shawn Guoc9250382012-07-02 20:13:03 +0800[diff] [blame]532 compatible = "fsl,sec-v4.0-mon", "simple-bus";
533 #address-cells = <1>;
534 #size-cells = <1>;
535 ranges = <0 0x020cc000 0x4000>;
536
537 snvs-rtc-lp@34 {
538 compatible = "fsl,sec-v4.0-mon-rtc-lp";
539 reg = <0x34 0x58>;
540 interrupts = <0 19 0x04 0 20 0x04>;
541 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]542 };
543
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]544 epit1: epit@020d0000 { /* EPIT1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]545 reg = <0x020d0000 0x4000>;
546 interrupts = <0 56 0x04>;
547 };
548
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]549 epit2: epit@020d4000 { /* EPIT2 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]550 reg = <0x020d4000 0x4000>;
551 interrupts = <0 57 0x04>;
552 };
553
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]554 src: src@020d8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]555 compatible = "fsl,imx6q-src";
556 reg = <0x020d8000 0x4000>;
557 interrupts = <0 91 0x04 0 96 0x04>;
558 };
559
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]560 gpc: gpc@020dc000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]561 compatible = "fsl,imx6q-gpc";
562 reg = <0x020dc000 0x4000>;
563 interrupts = <0 89 0x04 0 90 0x04>;
564 };
565
Dong Aishengdf37e0c2012-09-05 10:57:14 +0800[diff] [blame]566 gpr: iomuxc-gpr@020e0000 {
567 compatible = "fsl,imx6q-iomuxc-gpr", "syscon";
568 reg = <0x020e0000 0x38>;
569 };
570
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]571 iomuxc: iomuxc@020e0000 {
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]572 compatible = "fsl,imx6q-iomuxc";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]573 reg = <0x020e0000 0x4000>;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]574
575 /* shared pinctrl settings */
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]576 audmux {
577 pinctrl_audmux_1: audmux-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]578 fsl,pins = <
579 18 0x80000000 /* MX6Q_PAD_SD2_DAT0__AUDMUX_AUD4_RXD */
580 1586 0x80000000 /* MX6Q_PAD_SD2_DAT3__AUDMUX_AUD4_TXC */
581 11 0x80000000 /* MX6Q_PAD_SD2_DAT2__AUDMUX_AUD4_TXD */
582 3 0x80000000 /* MX6Q_PAD_SD2_DAT1__AUDMUX_AUD4_TXFS */
583 >;
Richard Zhao5ca65c12012-05-09 11:21:11 +0800[diff] [blame]584 };
585 };
586
Shawn Guo52ccd492012-08-11 11:17:42 +0800[diff] [blame]587 ecspi1 {
588 pinctrl_ecspi1_1: ecspi1grp-1 {
589 fsl,pins = <
590 101 0x100b1 /* MX6Q_PAD_EIM_D17__ECSPI1_MISO */
591 109 0x100b1 /* MX6Q_PAD_EIM_D18__ECSPI1_MOSI */
592 94 0x100b1 /* MX6Q_PAD_EIM_D16__ECSPI1_SCLK */
593 >;
594 };
595 };
596
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]597 enet {
598 pinctrl_enet_1: enetgrp-1 {
599 fsl,pins = <
600 695 0x1b0b0 /* MX6Q_PAD_ENET_MDIO__ENET_MDIO */
601 756 0x1b0b0 /* MX6Q_PAD_ENET_MDC__ENET_MDC */
602 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
603 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
604 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
605 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
606 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
607 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
608 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
609 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
610 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
611 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
612 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
613 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
614 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame]615 1033 0x4001b0a8 /* MX6Q_PAD_GPIO_16__ENET_ANATOP_ETHERNET_REF_OUT*/
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]616 >;
617 };
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]618
619 pinctrl_enet_2: enetgrp-2 {
620 fsl,pins = <
621 890 0x1b0b0 /* MX6Q_PAD_KEY_COL1__ENET_MDIO */
622 909 0x1b0b0 /* MX6Q_PAD_KEY_COL2__ENET_MDC */
623 24 0x1b0b0 /* MX6Q_PAD_RGMII_TXC__ENET_RGMII_TXC */
624 30 0x1b0b0 /* MX6Q_PAD_RGMII_TD0__ENET_RGMII_TD0 */
625 34 0x1b0b0 /* MX6Q_PAD_RGMII_TD1__ENET_RGMII_TD1 */
626 39 0x1b0b0 /* MX6Q_PAD_RGMII_TD2__ENET_RGMII_TD2 */
627 44 0x1b0b0 /* MX6Q_PAD_RGMII_TD3__ENET_RGMII_TD3 */
628 56 0x1b0b0 /* MX6Q_PAD_RGMII_TX_CTL__RGMII_TX_CTL */
629 702 0x1b0b0 /* MX6Q_PAD_ENET_REF_CLK__ENET_TX_CLK */
630 74 0x1b0b0 /* MX6Q_PAD_RGMII_RXC__ENET_RGMII_RXC */
631 52 0x1b0b0 /* MX6Q_PAD_RGMII_RD0__ENET_RGMII_RD0 */
632 61 0x1b0b0 /* MX6Q_PAD_RGMII_RD1__ENET_RGMII_RD1 */
633 66 0x1b0b0 /* MX6Q_PAD_RGMII_RD2__ENET_RGMII_RD2 */
634 70 0x1b0b0 /* MX6Q_PAD_RGMII_RD3__ENET_RGMII_RD3 */
635 48 0x1b0b0 /* MX6Q_PAD_RGMII_RX_CTL__RGMII_RX_CTL */
636 >;
637 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]638 };
639
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]640 gpmi-nand {
641 pinctrl_gpmi_nand_1: gpmi-nand-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]642 fsl,pins = <
643 1328 0xb0b1 /* MX6Q_PAD_NANDF_CLE__RAWNAND_CLE */
644 1336 0xb0b1 /* MX6Q_PAD_NANDF_ALE__RAWNAND_ALE */
645 1344 0xb0b1 /* MX6Q_PAD_NANDF_WP_B__RAWNAND_RESETN */
646 1352 0xb000 /* MX6Q_PAD_NANDF_RB0__RAWNAND_READY0 */
647 1360 0xb0b1 /* MX6Q_PAD_NANDF_CS0__RAWNAND_CE0N */
648 1365 0xb0b1 /* MX6Q_PAD_NANDF_CS1__RAWNAND_CE1N */
649 1371 0xb0b1 /* MX6Q_PAD_NANDF_CS2__RAWNAND_CE2N */
650 1378 0xb0b1 /* MX6Q_PAD_NANDF_CS3__RAWNAND_CE3N */
651 1387 0xb0b1 /* MX6Q_PAD_SD4_CMD__RAWNAND_RDN */
652 1393 0xb0b1 /* MX6Q_PAD_SD4_CLK__RAWNAND_WRN */
653 1397 0xb0b1 /* MX6Q_PAD_NANDF_D0__RAWNAND_D0 */
654 1405 0xb0b1 /* MX6Q_PAD_NANDF_D1__RAWNAND_D1 */
655 1413 0xb0b1 /* MX6Q_PAD_NANDF_D2__RAWNAND_D2 */
656 1421 0xb0b1 /* MX6Q_PAD_NANDF_D3__RAWNAND_D3 */
657 1429 0xb0b1 /* MX6Q_PAD_NANDF_D4__RAWNAND_D4 */
658 1437 0xb0b1 /* MX6Q_PAD_NANDF_D5__RAWNAND_D5 */
659 1445 0xb0b1 /* MX6Q_PAD_NANDF_D6__RAWNAND_D6 */
660 1453 0xb0b1 /* MX6Q_PAD_NANDF_D7__RAWNAND_D7 */
661 1463 0x00b1 /* MX6Q_PAD_SD4_DAT0__RAWNAND_DQS */
662 >;
Huang Shijiecf922fa2012-07-01 23:38:46 -0400[diff] [blame]663 };
664 };
665
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]666 i2c1 {
667 pinctrl_i2c1_1: i2c1grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]668 fsl,pins = <
669 137 0x4001b8b1 /* MX6Q_PAD_EIM_D21__I2C1_SCL */
670 196 0x4001b8b1 /* MX6Q_PAD_EIM_D28__I2C1_SDA */
671 >;
Richard Zhaod99a79f2012-05-09 10:47:20 +0800[diff] [blame]672 };
673 };
674
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame]675 uart1 {
676 pinctrl_uart1_1: uart1grp-1 {
677 fsl,pins = <
678 1140 0x1b0b1 /* MX6Q_PAD_CSI0_DAT10__UART1_TXD */
679 1148 0x1b0b1 /* MX6Q_PAD_CSI0_DAT11__UART1_RXD */
680 >;
681 };
682 };
683
Shawn Guoe30ba892012-08-11 12:33:51 +0800[diff] [blame]684 uart2 {
685 pinctrl_uart2_1: uart2grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]686 fsl,pins = <
687 183 0x1b0b1 /* MX6Q_PAD_EIM_D26__UART2_TXD */
688 191 0x1b0b1 /* MX6Q_PAD_EIM_D27__UART2_RXD */
689 >;
Richard Zhaoc3001b22012-05-09 14:44:47 +0800[diff] [blame]690 };
691 };
692
Shawn Guo9e3c0062012-08-11 12:49:11 +0800[diff] [blame]693 uart4 {
694 pinctrl_uart4_1: uart4grp-1 {
695 fsl,pins = <
696 877 0x1b0b1 /* MX6Q_PAD_KEY_COL0__UART4_TXD */
697 885 0x1b0b1 /* MX6Q_PAD_KEY_ROW0__UART4_RXD */
698 >;
699 };
700 };
701
Richard Zhao97a53092012-09-19 11:25:16 +0800[diff] [blame]702 usbotg {
703 pinctrl_usbotg_1: usbotggrp-1 {
704 fsl,pins = <
705 1592 0x17059 /* MX6Q_PAD_GPIO_1__ANATOP_USBOTG_ID */
706 >;
707 };
708 };
709
Shawn Guo497ae172012-08-11 22:06:26 +0800[diff] [blame]710 usdhc2 {
711 pinctrl_usdhc2_1: usdhc2grp-1 {
712 fsl,pins = <
713 1577 0x17059 /* MX6Q_PAD_SD2_CMD__USDHC2_CMD */
714 1569 0x10059 /* MX6Q_PAD_SD2_CLK__USDHC2_CLK */
715 16 0x17059 /* MX6Q_PAD_SD2_DAT0__USDHC2_DAT0 */
716 0 0x17059 /* MX6Q_PAD_SD2_DAT1__USDHC2_DAT1 */
717 8 0x17059 /* MX6Q_PAD_SD2_DAT2__USDHC2_DAT2 */
718 1583 0x17059 /* MX6Q_PAD_SD2_DAT3__USDHC2_DAT3 */
719 1430 0x17059 /* MX6Q_PAD_NANDF_D4__USDHC2_DAT4 */
720 1438 0x17059 /* MX6Q_PAD_NANDF_D5__USDHC2_DAT5 */
721 1446 0x17059 /* MX6Q_PAD_NANDF_D6__USDHC2_DAT6 */
722 1454 0x17059 /* MX6Q_PAD_NANDF_D7__USDHC2_DAT7 */
723 >;
724 };
725 };
726
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]727 usdhc3 {
728 pinctrl_usdhc3_1: usdhc3grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]729 fsl,pins = <
730 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
731 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
732 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
733 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
734 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
735 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
736 1265 0x17059 /* MX6Q_PAD_SD3_DAT4__USDHC3_DAT4 */
737 1257 0x17059 /* MX6Q_PAD_SD3_DAT5__USDHC3_DAT5 */
738 1249 0x17059 /* MX6Q_PAD_SD3_DAT6__USDHC3_DAT6 */
739 1241 0x17059 /* MX6Q_PAD_SD3_DAT7__USDHC3_DAT7 */
740 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]741 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]742
743 pinctrl_usdhc3_2: usdhc3grp-2 {
744 fsl,pins = <
745 1273 0x17059 /* MX6Q_PAD_SD3_CMD__USDHC3_CMD */
746 1281 0x10059 /* MX6Q_PAD_SD3_CLK__USDHC3_CLK */
747 1289 0x17059 /* MX6Q_PAD_SD3_DAT0__USDHC3_DAT0 */
748 1297 0x17059 /* MX6Q_PAD_SD3_DAT1__USDHC3_DAT1 */
749 1305 0x17059 /* MX6Q_PAD_SD3_DAT2__USDHC3_DAT2 */
750 1312 0x17059 /* MX6Q_PAD_SD3_DAT3__USDHC3_DAT3 */
751 >;
752 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]753 };
754
755 usdhc4 {
756 pinctrl_usdhc4_1: usdhc4grp-1 {
Shawn Guo44a509f2012-08-10 17:17:56 +0800[diff] [blame]757 fsl,pins = <
758 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
759 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
760 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
761 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
762 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
763 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
764 1493 0x17059 /* MX6Q_PAD_SD4_DAT4__USDHC4_DAT4 */
765 1501 0x17059 /* MX6Q_PAD_SD4_DAT5__USDHC4_DAT5 */
766 1509 0x17059 /* MX6Q_PAD_SD4_DAT6__USDHC4_DAT6 */
767 1517 0x17059 /* MX6Q_PAD_SD4_DAT7__USDHC4_DAT7 */
768 >;
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]769 };
Shawn Guo99d5f0c2012-08-11 10:47:14 +0800[diff] [blame]770
771 pinctrl_usdhc4_2: usdhc4grp-2 {
772 fsl,pins = <
773 1386 0x17059 /* MX6Q_PAD_SD4_CMD__USDHC4_CMD */
774 1392 0x10059 /* MX6Q_PAD_SD4_CLK__USDHC4_CLK */
775 1462 0x17059 /* MX6Q_PAD_SD4_DAT0__USDHC4_DAT0 */
776 1470 0x17059 /* MX6Q_PAD_SD4_DAT1__USDHC4_DAT1 */
777 1478 0x17059 /* MX6Q_PAD_SD4_DAT2__USDHC4_DAT2 */
778 1486 0x17059 /* MX6Q_PAD_SD4_DAT3__USDHC4_DAT3 */
779 >;
780 };
Dong Aisheng551fd202012-05-11 14:58:00 +0800[diff] [blame]781 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]782 };
783
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]784 dcic1: dcic@020e4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]785 reg = <0x020e4000 0x4000>;
786 interrupts = <0 124 0x04>;
787 };
788
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]789 dcic2: dcic@020e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]790 reg = <0x020e8000 0x4000>;
791 interrupts = <0 125 0x04>;
792 };
793
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]794 sdma: sdma@020ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]795 compatible = "fsl,imx6q-sdma", "fsl,imx35-sdma";
796 reg = <0x020ec000 0x4000>;
797 interrupts = <0 2 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]798 clocks = <&clks 155>, <&clks 155>;
799 clock-names = "ipg", "ahb";
Fabio Estevamd6b9c592013-01-17 12:13:25 -0200[diff] [blame^]800 fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]801 };
802 };
803
804 aips-bus@02100000 { /* AIPS2 */
805 compatible = "fsl,aips-bus", "simple-bus";
806 #address-cells = <1>;
807 #size-cells = <1>;
808 reg = <0x02100000 0x100000>;
809 ranges;
810
811 caam@02100000 {
812 reg = <0x02100000 0x40000>;
813 interrupts = <0 105 0x04 0 106 0x04>;
814 };
815
816 aipstz@0217c000 { /* AIPSTZ2 */
817 reg = <0x0217c000 0x4000>;
818 };
819
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]820 usbotg: usb@02184000 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]821 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
822 reg = <0x02184000 0x200>;
823 interrupts = <0 43 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]824 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]825 fsl,usbphy = <&usbphy1>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]826 fsl,usbmisc = <&usbmisc 0>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]827 status = "disabled";
828 };
829
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]830 usbh1: usb@02184200 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]831 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
832 reg = <0x02184200 0x200>;
833 interrupts = <0 40 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]834 clocks = <&clks 162>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]835 fsl,usbphy = <&usbphy2>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]836 fsl,usbmisc = <&usbmisc 1>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]837 status = "disabled";
838 };
839
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]840 usbh2: usb@02184400 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]841 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
842 reg = <0x02184400 0x200>;
843 interrupts = <0 41 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]844 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]845 fsl,usbmisc = <&usbmisc 2>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]846 status = "disabled";
847 };
848
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]849 usbh3: usb@02184600 {
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]850 compatible = "fsl,imx6q-usb", "fsl,imx27-usb";
851 reg = <0x02184600 0x200>;
852 interrupts = <0 42 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]853 clocks = <&clks 162>;
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]854 fsl,usbmisc = <&usbmisc 3>;
Richard Zhao74bd88f2012-07-12 14:21:41 +0800[diff] [blame]855 status = "disabled";
856 };
857
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]858 usbmisc: usbmisc: usbmisc@02184800 {
Richard Zhao28342c62012-09-14 14:42:45 +0800[diff] [blame]859 #index-cells = <1>;
860 compatible = "fsl,imx6q-usbmisc";
861 reg = <0x02184800 0x200>;
862 clocks = <&clks 162>;
863 };
864
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]865 fec: ethernet@02188000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]866 compatible = "fsl,imx6q-fec";
867 reg = <0x02188000 0x4000>;
868 interrupts = <0 118 0x04 0 119 0x04>;
Frank Li8dd5c662013-02-05 14:21:06 +0800[diff] [blame]869 clocks = <&clks 117>, <&clks 117>, <&clks 190>;
Frank Li76298382012-10-30 18:24:57 +0000[diff] [blame]870 clock-names = "ipg", "ahb", "ptp";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]871 status = "disabled";
872 };
873
874 mlb@0218c000 {
875 reg = <0x0218c000 0x4000>;
876 interrupts = <0 53 0x04 0 117 0x04 0 126 0x04>;
877 };
878
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]879 usdhc1: usdhc@02190000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]880 compatible = "fsl,imx6q-usdhc";
881 reg = <0x02190000 0x4000>;
882 interrupts = <0 22 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]883 clocks = <&clks 163>, <&clks 163>, <&clks 163>;
884 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]885 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]886 status = "disabled";
887 };
888
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]889 usdhc2: usdhc@02194000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]890 compatible = "fsl,imx6q-usdhc";
891 reg = <0x02194000 0x4000>;
892 interrupts = <0 23 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]893 clocks = <&clks 164>, <&clks 164>, <&clks 164>;
894 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]895 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]896 status = "disabled";
897 };
898
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]899 usdhc3: usdhc@02198000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]900 compatible = "fsl,imx6q-usdhc";
901 reg = <0x02198000 0x4000>;
902 interrupts = <0 24 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]903 clocks = <&clks 165>, <&clks 165>, <&clks 165>;
904 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]905 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]906 status = "disabled";
907 };
908
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]909 usdhc4: usdhc@0219c000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]910 compatible = "fsl,imx6q-usdhc";
911 reg = <0x0219c000 0x4000>;
912 interrupts = <0 25 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]913 clocks = <&clks 166>, <&clks 166>, <&clks 166>;
914 clock-names = "ipg", "ahb", "per";
Sascha Hauerc104b6a2012-09-25 11:49:33 +0200[diff] [blame]915 bus-width = <4>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]916 status = "disabled";
917 };
918
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]919 i2c1: i2c@021a0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]920 #address-cells = <1>;
921 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]922 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]923 reg = <0x021a0000 0x4000>;
924 interrupts = <0 36 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]925 clocks = <&clks 125>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]926 status = "disabled";
927 };
928
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]929 i2c2: i2c@021a4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]930 #address-cells = <1>;
931 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]932 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]933 reg = <0x021a4000 0x4000>;
934 interrupts = <0 37 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]935 clocks = <&clks 126>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]936 status = "disabled";
937 };
938
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]939 i2c3: i2c@021a8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]940 #address-cells = <1>;
941 #size-cells = <0>;
Shawn Guo5bdfba22012-09-14 15:19:00 +0800[diff] [blame]942 compatible = "fsl,imx6q-i2c", "fsl,imx21-i2c";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]943 reg = <0x021a8000 0x4000>;
944 interrupts = <0 38 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]945 clocks = <&clks 127>;
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]946 status = "disabled";
947 };
948
949 romcp@021ac000 {
950 reg = <0x021ac000 0x4000>;
951 };
952
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]953 mmdc0: mmdc@021b0000 { /* MMDC0 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]954 compatible = "fsl,imx6q-mmdc";
955 reg = <0x021b0000 0x4000>;
956 };
957
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]958 mmdc1: mmdc@021b4000 { /* MMDC1 */
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]959 reg = <0x021b4000 0x4000>;
960 };
961
962 weim@021b8000 {
963 reg = <0x021b8000 0x4000>;
964 interrupts = <0 14 0x04>;
965 };
966
967 ocotp@021bc000 {
968 reg = <0x021bc000 0x4000>;
969 };
970
971 ocotp@021c0000 {
972 reg = <0x021c0000 0x4000>;
973 interrupts = <0 21 0x04>;
974 };
975
976 tzasc@021d0000 { /* TZASC1 */
977 reg = <0x021d0000 0x4000>;
978 interrupts = <0 108 0x04>;
979 };
980
981 tzasc@021d4000 { /* TZASC2 */
982 reg = <0x021d4000 0x4000>;
983 interrupts = <0 109 0x04>;
984 };
985
Sascha Hauer7b7d6722012-11-15 09:31:52 +0100[diff] [blame]986 audmux: audmux@021d8000 {
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]987 compatible = "fsl,imx6q-audmux", "fsl,imx31-audmux";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]988 reg = <0x021d8000 0x4000>;
Richard Zhaof965cd52012-05-02 10:32:26 +0800[diff] [blame]989 status = "disabled";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]990 };
991
992 mipi@021dc000 { /* MIPI-CSI */
993 reg = <0x021dc000 0x4000>;
994 };
995
996 mipi@021e0000 { /* MIPI-DSI */
997 reg = <0x021e0000 0x4000>;
998 };
999
1000 vdoa@021e4000 {
1001 reg = <0x021e4000 0x4000>;
1002 interrupts = <0 18 0x04>;
1003 };
1004
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1005 uart2: serial@021e8000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1006 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1007 reg = <0x021e8000 0x4000>;
1008 interrupts = <0 27 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1009 clocks = <&clks 160>, <&clks 161>;
1010 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1011 status = "disabled";
1012 };
1013
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1014 uart3: serial@021ec000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1015 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1016 reg = <0x021ec000 0x4000>;
1017 interrupts = <0 28 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1018 clocks = <&clks 160>, <&clks 161>;
1019 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1020 status = "disabled";
1021 };
1022
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1023 uart4: serial@021f0000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1024 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1025 reg = <0x021f0000 0x4000>;
1026 interrupts = <0 29 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1027 clocks = <&clks 160>, <&clks 161>;
1028 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1029 status = "disabled";
1030 };
1031
Shawn Guo0c456cf2012-04-02 14:39:26 +0800[diff] [blame]1032 uart5: serial@021f4000 {
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1033 compatible = "fsl,imx6q-uart", "fsl,imx21-uart";
1034 reg = <0x021f4000 0x4000>;
1035 interrupts = <0 30 0x04>;
Shawn Guo0e87e042012-08-22 21:36:28 +0800[diff] [blame]1036 clocks = <&clks 160>, <&clks 161>;
1037 clock-names = "ipg", "per";
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1038 status = "disabled";
1039 };
1040 };
Sascha Hauer91660d72012-11-12 15:52:21 +0100[diff] [blame]1041
1042 ipu1: ipu@02400000 {
1043 #crtc-cells = <1>;
1044 compatible = "fsl,imx6q-ipu";
1045 reg = <0x02400000 0x400000>;
1046 interrupts = <0 6 0x4 0 5 0x4>;
1047 clocks = <&clks 130>, <&clks 131>, <&clks 132>;
1048 clock-names = "bus", "di0", "di1";
1049 };
1050
1051 ipu2: ipu@02800000 {
1052 #crtc-cells = <1>;
1053 compatible = "fsl,imx6q-ipu";
1054 reg = <0x02800000 0x400000>;
1055 interrupts = <0 8 0x4 0 7 0x4>;
1056 clocks = <&clks 133>, <&clks 134>, <&clks 137>;
1057 clock-names = "bus", "di0", "di1";
1058 };
Shawn Guo7d740f82011-09-06 13:53:26 +0800[diff] [blame]1059 };
1060};