Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 1 | /* |
| 2 | * SuperH Timer Support - MTU2 |
| 3 | * |
| 4 | * Copyright (C) 2009 Magnus Damm |
| 5 | * |
| 6 | * This program is free software; you can redistribute it and/or modify |
| 7 | * it under the terms of the GNU General Public License as published by |
| 8 | * the Free Software Foundation; either version 2 of the License |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | * You should have received a copy of the GNU General Public License |
| 16 | * along with this program; if not, write to the Free Software |
| 17 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
| 18 | */ |
| 19 | |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/platform_device.h> |
| 22 | #include <linux/spinlock.h> |
| 23 | #include <linux/interrupt.h> |
| 24 | #include <linux/ioport.h> |
| 25 | #include <linux/delay.h> |
| 26 | #include <linux/io.h> |
| 27 | #include <linux/clk.h> |
| 28 | #include <linux/irq.h> |
| 29 | #include <linux/err.h> |
| 30 | #include <linux/clockchips.h> |
Paul Mundt | 46a12f7 | 2009-05-03 17:57:17 +0900 | [diff] [blame] | 31 | #include <linux/sh_timer.h> |
Tejun Heo | 5a0e3ad | 2010-03-24 17:04:11 +0900 | [diff] [blame] | 32 | #include <linux/slab.h> |
Paul Gortmaker | 7deeab5 | 2011-07-03 13:36:22 -0400 | [diff] [blame] | 33 | #include <linux/module.h> |
Rafael J. Wysocki | 57d1337 | 2012-03-13 22:40:14 +0100 | [diff] [blame] | 34 | #include <linux/pm_domain.h> |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 35 | #include <linux/pm_runtime.h> |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 36 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 37 | struct sh_mtu2_device; |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 38 | |
| 39 | struct sh_mtu2_channel { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 40 | struct sh_mtu2_device *mtu; |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 41 | |
| 42 | void __iomem *base; |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 43 | int irq; |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 44 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 45 | struct clock_event_device ced; |
| 46 | }; |
| 47 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 48 | struct sh_mtu2_device { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 49 | struct platform_device *pdev; |
| 50 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 51 | void __iomem *mapbase; |
| 52 | struct clk *clk; |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 53 | |
| 54 | struct sh_mtu2_channel channel; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 55 | }; |
| 56 | |
Paul Mundt | 50393a9 | 2012-05-25 13:38:54 +0900 | [diff] [blame] | 57 | static DEFINE_RAW_SPINLOCK(sh_mtu2_lock); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 58 | |
| 59 | #define TSTR -1 /* shared register */ |
| 60 | #define TCR 0 /* channel register */ |
| 61 | #define TMDR 1 /* channel register */ |
| 62 | #define TIOR 2 /* channel register */ |
| 63 | #define TIER 3 /* channel register */ |
| 64 | #define TSR 4 /* channel register */ |
| 65 | #define TCNT 5 /* channel register */ |
| 66 | #define TGR 6 /* channel register */ |
| 67 | |
| 68 | static unsigned long mtu2_reg_offs[] = { |
| 69 | [TCR] = 0, |
| 70 | [TMDR] = 1, |
| 71 | [TIOR] = 2, |
| 72 | [TIER] = 4, |
| 73 | [TSR] = 5, |
| 74 | [TCNT] = 6, |
| 75 | [TGR] = 8, |
| 76 | }; |
| 77 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 78 | static inline unsigned long sh_mtu2_read(struct sh_mtu2_channel *ch, int reg_nr) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 79 | { |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 80 | unsigned long offs; |
| 81 | |
| 82 | if (reg_nr == TSTR) |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 83 | return ioread8(ch->mtu->mapbase); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 84 | |
| 85 | offs = mtu2_reg_offs[reg_nr]; |
| 86 | |
| 87 | if ((reg_nr == TCNT) || (reg_nr == TGR)) |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 88 | return ioread16(ch->base + offs); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 89 | else |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 90 | return ioread8(ch->base + offs); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 91 | } |
| 92 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 93 | static inline void sh_mtu2_write(struct sh_mtu2_channel *ch, int reg_nr, |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 94 | unsigned long value) |
| 95 | { |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 96 | unsigned long offs; |
| 97 | |
| 98 | if (reg_nr == TSTR) { |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 99 | iowrite8(value, ch->mtu->mapbase); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 100 | return; |
| 101 | } |
| 102 | |
| 103 | offs = mtu2_reg_offs[reg_nr]; |
| 104 | |
| 105 | if ((reg_nr == TCNT) || (reg_nr == TGR)) |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 106 | iowrite16(value, ch->base + offs); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 107 | else |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 108 | iowrite8(value, ch->base + offs); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 109 | } |
| 110 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 111 | static void sh_mtu2_start_stop_ch(struct sh_mtu2_channel *ch, int start) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 112 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 113 | struct sh_timer_config *cfg = ch->mtu->pdev->dev.platform_data; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 114 | unsigned long flags, value; |
| 115 | |
| 116 | /* start stop register shared by multiple timer channels */ |
Paul Mundt | 50393a9 | 2012-05-25 13:38:54 +0900 | [diff] [blame] | 117 | raw_spin_lock_irqsave(&sh_mtu2_lock, flags); |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 118 | value = sh_mtu2_read(ch, TSTR); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 119 | |
| 120 | if (start) |
| 121 | value |= 1 << cfg->timer_bit; |
| 122 | else |
| 123 | value &= ~(1 << cfg->timer_bit); |
| 124 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 125 | sh_mtu2_write(ch, TSTR, value); |
Paul Mundt | 50393a9 | 2012-05-25 13:38:54 +0900 | [diff] [blame] | 126 | raw_spin_unlock_irqrestore(&sh_mtu2_lock, flags); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 127 | } |
| 128 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 129 | static int sh_mtu2_enable(struct sh_mtu2_channel *ch) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 130 | { |
Laurent Pinchart | f92d62f5 | 2014-03-04 12:59:54 +0100 | [diff] [blame] | 131 | unsigned long periodic; |
| 132 | unsigned long rate; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 133 | int ret; |
| 134 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 135 | pm_runtime_get_sync(&ch->mtu->pdev->dev); |
| 136 | dev_pm_syscore_device(&ch->mtu->pdev->dev, true); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 137 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 138 | /* enable clock */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 139 | ret = clk_enable(ch->mtu->clk); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 140 | if (ret) { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 141 | dev_err(&ch->mtu->pdev->dev, "cannot enable clock\n"); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 142 | return ret; |
| 143 | } |
| 144 | |
| 145 | /* make sure channel is disabled */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 146 | sh_mtu2_start_stop_ch(ch, 0); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 147 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 148 | rate = clk_get_rate(ch->mtu->clk) / 64; |
Laurent Pinchart | f92d62f5 | 2014-03-04 12:59:54 +0100 | [diff] [blame] | 149 | periodic = (rate + HZ/2) / HZ; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 150 | |
| 151 | /* "Periodic Counter Operation" */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 152 | sh_mtu2_write(ch, TCR, 0x23); /* TGRA clear, divide clock by 64 */ |
| 153 | sh_mtu2_write(ch, TIOR, 0); |
| 154 | sh_mtu2_write(ch, TGR, periodic); |
| 155 | sh_mtu2_write(ch, TCNT, 0); |
| 156 | sh_mtu2_write(ch, TMDR, 0); |
| 157 | sh_mtu2_write(ch, TIER, 0x01); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 158 | |
| 159 | /* enable channel */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 160 | sh_mtu2_start_stop_ch(ch, 1); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 161 | |
| 162 | return 0; |
| 163 | } |
| 164 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 165 | static void sh_mtu2_disable(struct sh_mtu2_channel *ch) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 166 | { |
| 167 | /* disable channel */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 168 | sh_mtu2_start_stop_ch(ch, 0); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 169 | |
| 170 | /* stop clock */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 171 | clk_disable(ch->mtu->clk); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 172 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 173 | dev_pm_syscore_device(&ch->mtu->pdev->dev, false); |
| 174 | pm_runtime_put(&ch->mtu->pdev->dev); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 175 | } |
| 176 | |
| 177 | static irqreturn_t sh_mtu2_interrupt(int irq, void *dev_id) |
| 178 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 179 | struct sh_mtu2_channel *ch = dev_id; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 180 | |
| 181 | /* acknowledge interrupt */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 182 | sh_mtu2_read(ch, TSR); |
| 183 | sh_mtu2_write(ch, TSR, 0xfe); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 184 | |
| 185 | /* notify clockevent layer */ |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 186 | ch->ced.event_handler(&ch->ced); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 187 | return IRQ_HANDLED; |
| 188 | } |
| 189 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 190 | static struct sh_mtu2_channel *ced_to_sh_mtu2(struct clock_event_device *ced) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 191 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 192 | return container_of(ced, struct sh_mtu2_channel, ced); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 193 | } |
| 194 | |
| 195 | static void sh_mtu2_clock_event_mode(enum clock_event_mode mode, |
| 196 | struct clock_event_device *ced) |
| 197 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 198 | struct sh_mtu2_channel *ch = ced_to_sh_mtu2(ced); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 199 | int disabled = 0; |
| 200 | |
| 201 | /* deal with old setting first */ |
| 202 | switch (ced->mode) { |
| 203 | case CLOCK_EVT_MODE_PERIODIC: |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 204 | sh_mtu2_disable(ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 205 | disabled = 1; |
| 206 | break; |
| 207 | default: |
| 208 | break; |
| 209 | } |
| 210 | |
| 211 | switch (mode) { |
| 212 | case CLOCK_EVT_MODE_PERIODIC: |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 213 | dev_info(&ch->mtu->pdev->dev, |
| 214 | "used for periodic clock events\n"); |
| 215 | sh_mtu2_enable(ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 216 | break; |
| 217 | case CLOCK_EVT_MODE_UNUSED: |
| 218 | if (!disabled) |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 219 | sh_mtu2_disable(ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 220 | break; |
| 221 | case CLOCK_EVT_MODE_SHUTDOWN: |
| 222 | default: |
| 223 | break; |
| 224 | } |
| 225 | } |
| 226 | |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 227 | static void sh_mtu2_clock_event_suspend(struct clock_event_device *ced) |
| 228 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 229 | pm_genpd_syscore_poweroff(&ced_to_sh_mtu2(ced)->mtu->pdev->dev); |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 230 | } |
| 231 | |
| 232 | static void sh_mtu2_clock_event_resume(struct clock_event_device *ced) |
| 233 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 234 | pm_genpd_syscore_poweron(&ced_to_sh_mtu2(ced)->mtu->pdev->dev); |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 235 | } |
| 236 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 237 | static void sh_mtu2_register_clockevent(struct sh_mtu2_channel *ch, |
Laurent Pinchart | aa83804 | 2014-03-04 13:57:14 +0100 | [diff] [blame] | 238 | const char *name, unsigned long rating) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 239 | { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 240 | struct clock_event_device *ced = &ch->ced; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 241 | int ret; |
| 242 | |
| 243 | memset(ced, 0, sizeof(*ced)); |
| 244 | |
| 245 | ced->name = name; |
| 246 | ced->features = CLOCK_EVT_FEAT_PERIODIC; |
| 247 | ced->rating = rating; |
| 248 | ced->cpumask = cpumask_of(0); |
| 249 | ced->set_mode = sh_mtu2_clock_event_mode; |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 250 | ced->suspend = sh_mtu2_clock_event_suspend; |
| 251 | ced->resume = sh_mtu2_clock_event_resume; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 252 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 253 | dev_info(&ch->mtu->pdev->dev, "used for clock events\n"); |
Paul Mundt | da64c2a | 2010-02-25 16:37:46 +0900 | [diff] [blame] | 254 | clockevents_register_device(ced); |
| 255 | |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 256 | ret = request_irq(ch->irq, sh_mtu2_interrupt, |
Laurent Pinchart | 276bee0 | 2014-02-17 11:27:49 +0100 | [diff] [blame] | 257 | IRQF_TIMER | IRQF_IRQPOLL | IRQF_NOBALANCING, |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 258 | dev_name(&ch->mtu->pdev->dev), ch); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 259 | if (ret) { |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 260 | dev_err(&ch->mtu->pdev->dev, "failed to request irq %d\n", |
| 261 | ch->irq); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 262 | return; |
| 263 | } |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 264 | } |
| 265 | |
Laurent Pinchart | aa83804 | 2014-03-04 13:57:14 +0100 | [diff] [blame] | 266 | static int sh_mtu2_register(struct sh_mtu2_channel *ch, const char *name, |
Paul Mundt | d1fcc0a | 2009-05-03 18:05:42 +0900 | [diff] [blame] | 267 | unsigned long clockevent_rating) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 268 | { |
| 269 | if (clockevent_rating) |
Laurent Pinchart | 42752cc | 2014-03-04 12:58:30 +0100 | [diff] [blame] | 270 | sh_mtu2_register_clockevent(ch, name, clockevent_rating); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 271 | |
| 272 | return 0; |
| 273 | } |
| 274 | |
Laurent Pinchart | 2e1a532 | 2014-03-04 13:11:23 +0100 | [diff] [blame] | 275 | static int sh_mtu2_setup_channel(struct sh_mtu2_channel *ch, |
| 276 | struct sh_mtu2_device *mtu) |
| 277 | { |
| 278 | struct sh_timer_config *cfg = mtu->pdev->dev.platform_data; |
| 279 | |
| 280 | memset(ch, 0, sizeof(*ch)); |
| 281 | ch->mtu = mtu; |
| 282 | |
| 283 | ch->irq = platform_get_irq(mtu->pdev, 0); |
| 284 | if (ch->irq < 0) { |
| 285 | dev_err(&mtu->pdev->dev, "failed to get irq\n"); |
| 286 | return ch->irq; |
| 287 | } |
| 288 | |
Laurent Pinchart | aa83804 | 2014-03-04 13:57:14 +0100 | [diff] [blame] | 289 | return sh_mtu2_register(ch, dev_name(&mtu->pdev->dev), |
Laurent Pinchart | 2e1a532 | 2014-03-04 13:11:23 +0100 | [diff] [blame] | 290 | cfg->clockevent_rating); |
| 291 | } |
| 292 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 293 | static int sh_mtu2_setup(struct sh_mtu2_device *mtu, |
| 294 | struct platform_device *pdev) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 295 | { |
Paul Mundt | 46a12f7 | 2009-05-03 17:57:17 +0900 | [diff] [blame] | 296 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 297 | struct resource *res; |
Laurent Pinchart | 276bee0 | 2014-02-17 11:27:49 +0100 | [diff] [blame] | 298 | int ret; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 299 | ret = -ENXIO; |
| 300 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 301 | memset(mtu, 0, sizeof(*mtu)); |
| 302 | mtu->pdev = pdev; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 303 | |
| 304 | if (!cfg) { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 305 | dev_err(&mtu->pdev->dev, "missing platform data\n"); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 306 | goto err0; |
| 307 | } |
| 308 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 309 | platform_set_drvdata(pdev, mtu); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 310 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 311 | res = platform_get_resource(mtu->pdev, IORESOURCE_MEM, 0); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 312 | if (!res) { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 313 | dev_err(&mtu->pdev->dev, "failed to get I/O memory\n"); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 314 | goto err0; |
| 315 | } |
| 316 | |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 317 | /* |
| 318 | * Map memory, let channel.base point to our channel and mapbase to the |
| 319 | * start/stop shared register. |
| 320 | */ |
| 321 | mtu->channel.base = ioremap_nocache(res->start, resource_size(res)); |
| 322 | if (mtu->channel.base == NULL) { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 323 | dev_err(&mtu->pdev->dev, "failed to remap I/O memory\n"); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 324 | goto err0; |
| 325 | } |
| 326 | |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 327 | mtu->mapbase = mtu->channel.base + cfg->channel_offset; |
| 328 | |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 329 | /* get hold of clock */ |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 330 | mtu->clk = clk_get(&mtu->pdev->dev, "mtu2_fck"); |
| 331 | if (IS_ERR(mtu->clk)) { |
| 332 | dev_err(&mtu->pdev->dev, "cannot get clock\n"); |
| 333 | ret = PTR_ERR(mtu->clk); |
Magnus Damm | 03ff858 | 2010-10-13 07:36:38 +0000 | [diff] [blame] | 334 | goto err1; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 335 | } |
| 336 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 337 | ret = clk_prepare(mtu->clk); |
Laurent Pinchart | a4a5fc3 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 338 | if (ret < 0) |
| 339 | goto err2; |
| 340 | |
Laurent Pinchart | 2e1a532 | 2014-03-04 13:11:23 +0100 | [diff] [blame] | 341 | ret = sh_mtu2_setup_channel(&mtu->channel, mtu); |
Laurent Pinchart | bd75493 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 342 | if (ret < 0) |
| 343 | goto err3; |
Laurent Pinchart | a4a5fc3 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 344 | |
Laurent Pinchart | bd75493 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 345 | return 0; |
| 346 | err3: |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 347 | clk_unprepare(mtu->clk); |
Laurent Pinchart | a4a5fc3 | 2013-11-08 11:07:59 +0100 | [diff] [blame] | 348 | err2: |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 349 | clk_put(mtu->clk); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 350 | err1: |
Laurent Pinchart | da90a1c | 2014-03-04 14:04:24 +0100 | [diff] [blame^] | 351 | iounmap(mtu->channel.base); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 352 | err0: |
| 353 | return ret; |
| 354 | } |
| 355 | |
Greg Kroah-Hartman | 1850514 | 2012-12-21 15:11:38 -0800 | [diff] [blame] | 356 | static int sh_mtu2_probe(struct platform_device *pdev) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 357 | { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 358 | struct sh_mtu2_device *mtu = platform_get_drvdata(pdev); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 359 | struct sh_timer_config *cfg = pdev->dev.platform_data; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 360 | int ret; |
| 361 | |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 362 | if (!is_early_platform_device(pdev)) { |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 363 | pm_runtime_set_active(&pdev->dev); |
| 364 | pm_runtime_enable(&pdev->dev); |
Rafael J. Wysocki | cc7ad45 | 2012-08-06 01:43:41 +0200 | [diff] [blame] | 365 | } |
Rafael J. Wysocki | 57d1337 | 2012-03-13 22:40:14 +0100 | [diff] [blame] | 366 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 367 | if (mtu) { |
Paul Mundt | 214a607 | 2010-03-10 16:26:25 +0900 | [diff] [blame] | 368 | dev_info(&pdev->dev, "kept as earlytimer\n"); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 369 | goto out; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 370 | } |
| 371 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 372 | mtu = kmalloc(sizeof(*mtu), GFP_KERNEL); |
| 373 | if (mtu == NULL) { |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 374 | dev_err(&pdev->dev, "failed to allocate driver data\n"); |
| 375 | return -ENOMEM; |
| 376 | } |
| 377 | |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 378 | ret = sh_mtu2_setup(mtu, pdev); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 379 | if (ret) { |
Laurent Pinchart | 7dad72d | 2014-03-04 13:04:48 +0100 | [diff] [blame] | 380 | kfree(mtu); |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 381 | pm_runtime_idle(&pdev->dev); |
| 382 | return ret; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 383 | } |
Rafael J. Wysocki | 3cb6f10 | 2012-08-13 14:00:16 +0200 | [diff] [blame] | 384 | if (is_early_platform_device(pdev)) |
| 385 | return 0; |
| 386 | |
| 387 | out: |
| 388 | if (cfg->clockevent_rating) |
| 389 | pm_runtime_irq_safe(&pdev->dev); |
| 390 | else |
| 391 | pm_runtime_idle(&pdev->dev); |
| 392 | |
| 393 | return 0; |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 394 | } |
| 395 | |
Greg Kroah-Hartman | 1850514 | 2012-12-21 15:11:38 -0800 | [diff] [blame] | 396 | static int sh_mtu2_remove(struct platform_device *pdev) |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 397 | { |
| 398 | return -EBUSY; /* cannot unregister clockevent */ |
| 399 | } |
| 400 | |
| 401 | static struct platform_driver sh_mtu2_device_driver = { |
| 402 | .probe = sh_mtu2_probe, |
Greg Kroah-Hartman | 1850514 | 2012-12-21 15:11:38 -0800 | [diff] [blame] | 403 | .remove = sh_mtu2_remove, |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 404 | .driver = { |
| 405 | .name = "sh_mtu2", |
| 406 | } |
| 407 | }; |
| 408 | |
| 409 | static int __init sh_mtu2_init(void) |
| 410 | { |
| 411 | return platform_driver_register(&sh_mtu2_device_driver); |
| 412 | } |
| 413 | |
| 414 | static void __exit sh_mtu2_exit(void) |
| 415 | { |
| 416 | platform_driver_unregister(&sh_mtu2_device_driver); |
| 417 | } |
| 418 | |
| 419 | early_platform_init("earlytimer", &sh_mtu2_device_driver); |
Simon Horman | 342896a | 2013-03-05 15:40:42 +0900 | [diff] [blame] | 420 | subsys_initcall(sh_mtu2_init); |
Magnus Damm | d5ed4c2 | 2009-04-30 07:02:49 +0000 | [diff] [blame] | 421 | module_exit(sh_mtu2_exit); |
| 422 | |
| 423 | MODULE_AUTHOR("Magnus Damm"); |
| 424 | MODULE_DESCRIPTION("SuperH MTU2 Timer Driver"); |
| 425 | MODULE_LICENSE("GPL v2"); |