blob: b98070c33ca9d3b8aa42d1fb5085da9772957733 [file] [log] [blame]
Zhang Wei173acc72008-03-01 07:42:48 -07001/*
2 * Freescale MPC85xx, MPC83xx DMA Engine support
3 *
Li Yange2c8e4252010-11-11 20:16:29 +08004 * Copyright (C) 2007-2010 Freescale Semiconductor, Inc. All rights reserved.
Zhang Wei173acc72008-03-01 07:42:48 -07005 *
6 * Author:
7 * Zhang Wei <wei.zhang@freescale.com>, Jul 2007
8 * Ebony Zhu <ebony.zhu@freescale.com>, May 2007
9 *
10 * Description:
11 * DMA engine driver for Freescale MPC8540 DMA controller, which is
12 * also fit for MPC8560, MPC8555, MPC8548, MPC8641, and etc.
Stefan Weilc2e07b32010-08-03 19:44:52 +020013 * The support for MPC8349 DMA controller is also added.
Zhang Wei173acc72008-03-01 07:42:48 -070014 *
Ira W. Snydera7aea372009-04-23 16:17:54 -070015 * This driver instructs the DMA controller to issue the PCI Read Multiple
16 * command for PCI read operations, instead of using the default PCI Read Line
17 * command. Please be aware that this setting may result in read pre-fetching
18 * on some platforms.
19 *
Zhang Wei173acc72008-03-01 07:42:48 -070020 * This is free software; you can redistribute it and/or modify
21 * it under the terms of the GNU General Public License as published by
22 * the Free Software Foundation; either version 2 of the License, or
23 * (at your option) any later version.
24 *
25 */
26
27#include <linux/init.h>
28#include <linux/module.h>
29#include <linux/pci.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090030#include <linux/slab.h>
Zhang Wei173acc72008-03-01 07:42:48 -070031#include <linux/interrupt.h>
32#include <linux/dmaengine.h>
33#include <linux/delay.h>
34#include <linux/dma-mapping.h>
35#include <linux/dmapool.h>
36#include <linux/of_platform.h>
37
38#include "fsldma.h"
39
Ira Snyderb1584712011-03-03 07:54:55 +000040#define chan_dbg(chan, fmt, arg...) \
41 dev_dbg(chan->dev, "%s: " fmt, chan->name, ##arg)
42#define chan_err(chan, fmt, arg...) \
43 dev_err(chan->dev, "%s: " fmt, chan->name, ##arg)
Ira Snyderc14330412010-09-30 11:46:45 +000044
Ira Snyderb1584712011-03-03 07:54:55 +000045static const char msg_ld_oom[] = "No free memory for link descriptor";
Zhang Wei173acc72008-03-01 07:42:48 -070046
Ira Snydere8bd84d2011-03-03 07:54:54 +000047/*
48 * Register Helpers
49 */
Zhang Wei173acc72008-03-01 07:42:48 -070050
Ira Snydera1c03312010-01-06 13:34:05 +000051static void set_sr(struct fsldma_chan *chan, u32 val)
Zhang Wei173acc72008-03-01 07:42:48 -070052{
Ira Snydera1c03312010-01-06 13:34:05 +000053 DMA_OUT(chan, &chan->regs->sr, val, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070054}
55
Ira Snydera1c03312010-01-06 13:34:05 +000056static u32 get_sr(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070057{
Ira Snydera1c03312010-01-06 13:34:05 +000058 return DMA_IN(chan, &chan->regs->sr, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070059}
60
Ira Snydera1c03312010-01-06 13:34:05 +000061static void set_cdar(struct fsldma_chan *chan, dma_addr_t addr)
Zhang Wei173acc72008-03-01 07:42:48 -070062{
Ira Snydera1c03312010-01-06 13:34:05 +000063 DMA_OUT(chan, &chan->regs->cdar, addr | FSL_DMA_SNEN, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070064}
65
Ira Snydera1c03312010-01-06 13:34:05 +000066static dma_addr_t get_cdar(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -070067{
Ira Snydera1c03312010-01-06 13:34:05 +000068 return DMA_IN(chan, &chan->regs->cdar, 64) & ~FSL_DMA_SNEN;
Zhang Wei173acc72008-03-01 07:42:48 -070069}
70
Ira Snydera1c03312010-01-06 13:34:05 +000071static u32 get_bcr(struct fsldma_chan *chan)
Zhang Weif79abb62008-03-18 18:45:00 -070072{
Ira Snydera1c03312010-01-06 13:34:05 +000073 return DMA_IN(chan, &chan->regs->bcr, 32);
Zhang Weif79abb62008-03-18 18:45:00 -070074}
75
Ira Snydere8bd84d2011-03-03 07:54:54 +000076/*
77 * Descriptor Helpers
78 */
79
Zhang Wei173acc72008-03-01 07:42:48 -070080static void set_desc_cnt(struct fsldma_chan *chan,
81 struct fsl_dma_ld_hw *hw, u32 count)
Zhang Wei173acc72008-03-01 07:42:48 -070082{
Zhang Wei173acc72008-03-01 07:42:48 -070083 hw->count = CPU_TO_DMA(chan, count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070084}
85
Ira Snyder9c4d1e72011-03-03 07:54:59 +000086static u32 get_desc_cnt(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Zhang Wei173acc72008-03-01 07:42:48 -070087{
Ira Snyder9c4d1e72011-03-03 07:54:59 +000088 return DMA_TO_CPU(chan, desc->hw.count, 32);
Zhang Wei173acc72008-03-01 07:42:48 -070089}
90
Zhang Wei173acc72008-03-01 07:42:48 -070091static void set_desc_src(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +000092 struct fsl_dma_ld_hw *hw, dma_addr_t src)
Zhang Wei173acc72008-03-01 07:42:48 -070093{
Zhang Wei173acc72008-03-01 07:42:48 -070094 u64 snoop_bits;
Dan Williams900325a2009-03-02 15:33:46 -070095
Zhang Wei173acc72008-03-01 07:42:48 -070096 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
97 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
98 hw->src_addr = CPU_TO_DMA(chan, snoop_bits | src, 64);
Zhang Wei173acc72008-03-01 07:42:48 -070099}
100
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000101static dma_addr_t get_desc_src(struct fsldma_chan *chan,
102 struct fsl_desc_sw *desc)
103{
104 u64 snoop_bits;
105
106 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
107 ? ((u64)FSL_DMA_SATR_SREADTYPE_SNOOP_READ << 32) : 0;
108 return DMA_TO_CPU(chan, desc->hw.src_addr, 64) & ~snoop_bits;
109}
110
Zhang Wei173acc72008-03-01 07:42:48 -0700111static void set_desc_dst(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000112 struct fsl_dma_ld_hw *hw, dma_addr_t dst)
Zhang Wei173acc72008-03-01 07:42:48 -0700113{
114 u64 snoop_bits;
115
116 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
117 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
118 hw->dst_addr = CPU_TO_DMA(chan, snoop_bits | dst, 64);
119}
120
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000121static dma_addr_t get_desc_dst(struct fsldma_chan *chan,
122 struct fsl_desc_sw *desc)
123{
124 u64 snoop_bits;
125
126 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX)
127 ? ((u64)FSL_DMA_DATR_DWRITETYPE_SNOOP_WRITE << 32) : 0;
128 return DMA_TO_CPU(chan, desc->hw.dst_addr, 64) & ~snoop_bits;
129}
130
Zhang Wei173acc72008-03-01 07:42:48 -0700131static void set_desc_next(struct fsldma_chan *chan,
Ira Snyder31f43062011-03-03 07:54:57 +0000132 struct fsl_dma_ld_hw *hw, dma_addr_t next)
Zhang Wei173acc72008-03-01 07:42:48 -0700133{
134 u64 snoop_bits;
135
136 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
137 ? FSL_DMA_SNEN : 0;
138 hw->next_ln_addr = CPU_TO_DMA(chan, snoop_bits | next, 64);
139}
140
Ira Snyder31f43062011-03-03 07:54:57 +0000141static void set_ld_eol(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Zhang Wei173acc72008-03-01 07:42:48 -0700142{
Ira Snyder776c8942009-05-15 11:33:20 -0700143 u64 snoop_bits;
144
Ira Snydera1c03312010-01-06 13:34:05 +0000145 snoop_bits = ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_83XX)
Ira Snyder776c8942009-05-15 11:33:20 -0700146 ? FSL_DMA_SNEN : 0;
147
Ira Snydera1c03312010-01-06 13:34:05 +0000148 desc->hw.next_ln_addr = CPU_TO_DMA(chan,
149 DMA_TO_CPU(chan, desc->hw.next_ln_addr, 64) | FSL_DMA_EOL
Ira Snyder776c8942009-05-15 11:33:20 -0700150 | snoop_bits, 64);
Zhang Wei173acc72008-03-01 07:42:48 -0700151}
152
Ira Snydere8bd84d2011-03-03 07:54:54 +0000153/*
154 * DMA Engine Hardware Control Helpers
155 */
Zhang Wei173acc72008-03-01 07:42:48 -0700156
Ira Snydere8bd84d2011-03-03 07:54:54 +0000157static void dma_init(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700158{
Ira Snydere8bd84d2011-03-03 07:54:54 +0000159 /* Reset the channel */
160 DMA_OUT(chan, &chan->regs->mr, 0, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700161
Ira Snydere8bd84d2011-03-03 07:54:54 +0000162 switch (chan->feature & FSL_DMA_IP_MASK) {
163 case FSL_DMA_IP_85XX:
164 /* Set the channel to below modes:
165 * EIE - Error interrupt enable
Ira Snydere8bd84d2011-03-03 07:54:54 +0000166 * EOLNIE - End of links interrupt enable
167 * BWC - Bandwidth sharing among channels
168 */
169 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_BWC
Ira Snyderf04cd402011-03-03 07:54:58 +0000170 | FSL_DMA_MR_EIE | FSL_DMA_MR_EOLNIE, 32);
Ira Snydere8bd84d2011-03-03 07:54:54 +0000171 break;
172 case FSL_DMA_IP_83XX:
173 /* Set the channel to below modes:
174 * EOTIE - End-of-transfer interrupt enable
175 * PRC_RM - PCI read multiple
176 */
177 DMA_OUT(chan, &chan->regs->mr, FSL_DMA_MR_EOTIE
178 | FSL_DMA_MR_PRC_RM, 32);
179 break;
180 }
Zhang Wei173acc72008-03-01 07:42:48 -0700181}
182
183static int dma_is_idle(struct fsldma_chan *chan)
184{
185 u32 sr = get_sr(chan);
186 return (!(sr & FSL_DMA_SR_CB)) || (sr & FSL_DMA_SR_CH);
187}
188
Ira Snyderf04cd402011-03-03 07:54:58 +0000189/*
190 * Start the DMA controller
191 *
192 * Preconditions:
193 * - the CDAR register must point to the start descriptor
194 * - the MRn[CS] bit must be cleared
195 */
Zhang Wei173acc72008-03-01 07:42:48 -0700196static void dma_start(struct fsldma_chan *chan)
197{
198 u32 mode;
199
200 mode = DMA_IN(chan, &chan->regs->mr, 32);
201
Ira Snyderf04cd402011-03-03 07:54:58 +0000202 if (chan->feature & FSL_DMA_CHAN_PAUSE_EXT) {
203 DMA_OUT(chan, &chan->regs->bcr, 0, 32);
204 mode |= FSL_DMA_MR_EMP_EN;
205 } else {
206 mode &= ~FSL_DMA_MR_EMP_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700207 }
208
Ira Snyderf04cd402011-03-03 07:54:58 +0000209 if (chan->feature & FSL_DMA_CHAN_START_EXT) {
Zhang Wei173acc72008-03-01 07:42:48 -0700210 mode |= FSL_DMA_MR_EMS_EN;
Ira Snyderf04cd402011-03-03 07:54:58 +0000211 } else {
212 mode &= ~FSL_DMA_MR_EMS_EN;
Zhang Wei173acc72008-03-01 07:42:48 -0700213 mode |= FSL_DMA_MR_CS;
Ira Snyderf04cd402011-03-03 07:54:58 +0000214 }
Zhang Wei173acc72008-03-01 07:42:48 -0700215
216 DMA_OUT(chan, &chan->regs->mr, mode, 32);
217}
218
219static void dma_halt(struct fsldma_chan *chan)
220{
221 u32 mode;
222 int i;
223
Ira Snydera00ae342011-03-03 07:55:01 +0000224 /* read the mode register */
Zhang Wei173acc72008-03-01 07:42:48 -0700225 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snydera00ae342011-03-03 07:55:01 +0000226
227 /*
228 * The 85xx controller supports channel abort, which will stop
229 * the current transfer. On 83xx, this bit is the transfer error
230 * mask bit, which should not be changed.
231 */
232 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
233 mode |= FSL_DMA_MR_CA;
234 DMA_OUT(chan, &chan->regs->mr, mode, 32);
235
236 mode &= ~FSL_DMA_MR_CA;
237 }
238
239 /* stop the DMA controller */
240 mode &= ~(FSL_DMA_MR_CS | FSL_DMA_MR_EMS_EN);
Zhang Wei173acc72008-03-01 07:42:48 -0700241 DMA_OUT(chan, &chan->regs->mr, mode, 32);
242
Ira Snydera00ae342011-03-03 07:55:01 +0000243 /* wait for the DMA controller to become idle */
Zhang Wei173acc72008-03-01 07:42:48 -0700244 for (i = 0; i < 100; i++) {
245 if (dma_is_idle(chan))
246 return;
247
248 udelay(10);
249 }
250
251 if (!dma_is_idle(chan))
Ira Snyderb1584712011-03-03 07:54:55 +0000252 chan_err(chan, "DMA halt timeout!\n");
Zhang Wei173acc72008-03-01 07:42:48 -0700253}
254
Zhang Wei173acc72008-03-01 07:42:48 -0700255/**
256 * fsl_chan_set_src_loop_size - Set source address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000257 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700258 * @size : Address loop size, 0 for disable loop
259 *
260 * The set source address hold transfer size. The source
261 * address hold or loop transfer size is when the DMA transfer
262 * data from source address (SA), if the loop size is 4, the DMA will
263 * read data from SA, SA + 1, SA + 2, SA + 3, then loop back to SA,
264 * SA + 1 ... and so on.
265 */
Ira Snydera1c03312010-01-06 13:34:05 +0000266static void fsl_chan_set_src_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700267{
Ira Snyder272ca652010-01-06 13:33:59 +0000268 u32 mode;
269
Ira Snydera1c03312010-01-06 13:34:05 +0000270 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000271
Zhang Wei173acc72008-03-01 07:42:48 -0700272 switch (size) {
273 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000274 mode &= ~FSL_DMA_MR_SAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700275 break;
276 case 1:
277 case 2:
278 case 4:
279 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000280 mode |= FSL_DMA_MR_SAHE | (__ilog2(size) << 14);
Zhang Wei173acc72008-03-01 07:42:48 -0700281 break;
282 }
Ira Snyder272ca652010-01-06 13:33:59 +0000283
Ira Snydera1c03312010-01-06 13:34:05 +0000284 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700285}
286
287/**
Ira Snyder738f5f72010-01-06 13:34:02 +0000288 * fsl_chan_set_dst_loop_size - Set destination address hold transfer size
Ira Snydera1c03312010-01-06 13:34:05 +0000289 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700290 * @size : Address loop size, 0 for disable loop
291 *
292 * The set destination address hold transfer size. The destination
293 * address hold or loop transfer size is when the DMA transfer
294 * data to destination address (TA), if the loop size is 4, the DMA will
295 * write data to TA, TA + 1, TA + 2, TA + 3, then loop back to TA,
296 * TA + 1 ... and so on.
297 */
Ira Snydera1c03312010-01-06 13:34:05 +0000298static void fsl_chan_set_dst_loop_size(struct fsldma_chan *chan, int size)
Zhang Wei173acc72008-03-01 07:42:48 -0700299{
Ira Snyder272ca652010-01-06 13:33:59 +0000300 u32 mode;
301
Ira Snydera1c03312010-01-06 13:34:05 +0000302 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000303
Zhang Wei173acc72008-03-01 07:42:48 -0700304 switch (size) {
305 case 0:
Ira Snyder272ca652010-01-06 13:33:59 +0000306 mode &= ~FSL_DMA_MR_DAHE;
Zhang Wei173acc72008-03-01 07:42:48 -0700307 break;
308 case 1:
309 case 2:
310 case 4:
311 case 8:
Ira Snyder272ca652010-01-06 13:33:59 +0000312 mode |= FSL_DMA_MR_DAHE | (__ilog2(size) << 16);
Zhang Wei173acc72008-03-01 07:42:48 -0700313 break;
314 }
Ira Snyder272ca652010-01-06 13:33:59 +0000315
Ira Snydera1c03312010-01-06 13:34:05 +0000316 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Zhang Wei173acc72008-03-01 07:42:48 -0700317}
318
319/**
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700320 * fsl_chan_set_request_count - Set DMA Request Count for external control
Ira Snydera1c03312010-01-06 13:34:05 +0000321 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700322 * @size : Number of bytes to transfer in a single request
323 *
324 * The Freescale DMA channel can be controlled by the external signal DREQ#.
325 * The DMA request count is how many bytes are allowed to transfer before
326 * pausing the channel, after which a new assertion of DREQ# resumes channel
327 * operation.
328 *
329 * A size of 0 disables external pause control. The maximum size is 1024.
330 */
Ira Snydera1c03312010-01-06 13:34:05 +0000331static void fsl_chan_set_request_count(struct fsldma_chan *chan, int size)
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700332{
Ira Snyder272ca652010-01-06 13:33:59 +0000333 u32 mode;
334
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700335 BUG_ON(size > 1024);
Ira Snyder272ca652010-01-06 13:33:59 +0000336
Ira Snydera1c03312010-01-06 13:34:05 +0000337 mode = DMA_IN(chan, &chan->regs->mr, 32);
Ira Snyder272ca652010-01-06 13:33:59 +0000338 mode |= (__ilog2(size) << 24) & 0x0f000000;
339
Ira Snydera1c03312010-01-06 13:34:05 +0000340 DMA_OUT(chan, &chan->regs->mr, mode, 32);
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700341}
342
343/**
Zhang Wei173acc72008-03-01 07:42:48 -0700344 * fsl_chan_toggle_ext_pause - Toggle channel external pause status
Ira Snydera1c03312010-01-06 13:34:05 +0000345 * @chan : Freescale DMA channel
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700346 * @enable : 0 is disabled, 1 is enabled.
Zhang Wei173acc72008-03-01 07:42:48 -0700347 *
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700348 * The Freescale DMA channel can be controlled by the external signal DREQ#.
349 * The DMA Request Count feature should be used in addition to this feature
350 * to set the number of bytes to transfer before pausing the channel.
Zhang Wei173acc72008-03-01 07:42:48 -0700351 */
Ira Snydera1c03312010-01-06 13:34:05 +0000352static void fsl_chan_toggle_ext_pause(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700353{
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700354 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000355 chan->feature |= FSL_DMA_CHAN_PAUSE_EXT;
Ira Snydere6c7ecb2009-09-08 17:53:04 -0700356 else
Ira Snydera1c03312010-01-06 13:34:05 +0000357 chan->feature &= ~FSL_DMA_CHAN_PAUSE_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700358}
359
360/**
361 * fsl_chan_toggle_ext_start - Toggle channel external start status
Ira Snydera1c03312010-01-06 13:34:05 +0000362 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700363 * @enable : 0 is disabled, 1 is enabled.
364 *
365 * If enable the external start, the channel can be started by an
366 * external DMA start pin. So the dma_start() does not start the
367 * transfer immediately. The DMA channel will wait for the
368 * control pin asserted.
369 */
Ira Snydera1c03312010-01-06 13:34:05 +0000370static void fsl_chan_toggle_ext_start(struct fsldma_chan *chan, int enable)
Zhang Wei173acc72008-03-01 07:42:48 -0700371{
372 if (enable)
Ira Snydera1c03312010-01-06 13:34:05 +0000373 chan->feature |= FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700374 else
Ira Snydera1c03312010-01-06 13:34:05 +0000375 chan->feature &= ~FSL_DMA_CHAN_START_EXT;
Zhang Wei173acc72008-03-01 07:42:48 -0700376}
377
Ira Snyder31f43062011-03-03 07:54:57 +0000378static void append_ld_queue(struct fsldma_chan *chan, struct fsl_desc_sw *desc)
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000379{
380 struct fsl_desc_sw *tail = to_fsl_desc(chan->ld_pending.prev);
381
382 if (list_empty(&chan->ld_pending))
383 goto out_splice;
384
385 /*
386 * Add the hardware descriptor to the chain of hardware descriptors
387 * that already exists in memory.
388 *
389 * This will un-set the EOL bit of the existing transaction, and the
390 * last link in this transaction will become the EOL descriptor.
391 */
392 set_desc_next(chan, &tail->hw, desc->async_tx.phys);
393
394 /*
395 * Add the software descriptor and all children to the list
396 * of pending transactions
397 */
398out_splice:
399 list_splice_tail_init(&desc->tx_list, &chan->ld_pending);
400}
401
Zhang Wei173acc72008-03-01 07:42:48 -0700402static dma_cookie_t fsl_dma_tx_submit(struct dma_async_tx_descriptor *tx)
403{
Ira Snydera1c03312010-01-06 13:34:05 +0000404 struct fsldma_chan *chan = to_fsl_chan(tx->chan);
Dan Williamseda34232009-09-08 17:53:02 -0700405 struct fsl_desc_sw *desc = tx_to_fsl_desc(tx);
406 struct fsl_desc_sw *child;
Zhang Wei173acc72008-03-01 07:42:48 -0700407 unsigned long flags;
408 dma_cookie_t cookie;
409
Ira Snydera1c03312010-01-06 13:34:05 +0000410 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700411
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000412 /*
413 * assign cookies to all of the software descriptors
414 * that make up this transaction
415 */
Ira Snydera1c03312010-01-06 13:34:05 +0000416 cookie = chan->common.cookie;
Dan Williamseda34232009-09-08 17:53:02 -0700417 list_for_each_entry(child, &desc->tx_list, node) {
Ira Snyderbcfb7462009-05-15 14:27:16 -0700418 cookie++;
Ira Snyder31f43062011-03-03 07:54:57 +0000419 if (cookie < DMA_MIN_COOKIE)
420 cookie = DMA_MIN_COOKIE;
Zhang Wei173acc72008-03-01 07:42:48 -0700421
Steven J. Magnani6ca3a7a2010-02-25 13:39:30 -0600422 child->async_tx.cookie = cookie;
Ira Snyderbcfb7462009-05-15 14:27:16 -0700423 }
424
Ira Snydera1c03312010-01-06 13:34:05 +0000425 chan->common.cookie = cookie;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000426
427 /* put this transaction onto the tail of the pending queue */
Ira Snydera1c03312010-01-06 13:34:05 +0000428 append_ld_queue(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700429
Ira Snydera1c03312010-01-06 13:34:05 +0000430 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700431
432 return cookie;
433}
434
435/**
436 * fsl_dma_alloc_descriptor - Allocate descriptor from channel's DMA pool.
Ira Snydera1c03312010-01-06 13:34:05 +0000437 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700438 *
439 * Return - The descriptor allocated. NULL for failed.
440 */
Ira Snyder31f43062011-03-03 07:54:57 +0000441static struct fsl_desc_sw *fsl_dma_alloc_descriptor(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700442{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000443 struct fsl_desc_sw *desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700444 dma_addr_t pdesc;
Zhang Wei173acc72008-03-01 07:42:48 -0700445
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000446 desc = dma_pool_alloc(chan->desc_pool, GFP_ATOMIC, &pdesc);
447 if (!desc) {
Ira Snyderb1584712011-03-03 07:54:55 +0000448 chan_dbg(chan, "out of memory for link descriptor\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000449 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700450 }
451
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000452 memset(desc, 0, sizeof(*desc));
453 INIT_LIST_HEAD(&desc->tx_list);
454 dma_async_tx_descriptor_init(&desc->async_tx, &chan->common);
455 desc->async_tx.tx_submit = fsl_dma_tx_submit;
456 desc->async_tx.phys = pdesc;
457
Ira Snyder0ab09c32011-03-03 07:54:56 +0000458#ifdef FSL_DMA_LD_DEBUG
459 chan_dbg(chan, "LD %p allocated\n", desc);
460#endif
461
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000462 return desc;
Zhang Wei173acc72008-03-01 07:42:48 -0700463}
464
Zhang Wei173acc72008-03-01 07:42:48 -0700465/**
466 * fsl_dma_alloc_chan_resources - Allocate resources for DMA channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000467 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700468 *
469 * This function will create a dma pool for descriptor allocation.
470 *
471 * Return - The number of descriptors allocated.
472 */
Ira Snydera1c03312010-01-06 13:34:05 +0000473static int fsl_dma_alloc_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700474{
Ira Snydera1c03312010-01-06 13:34:05 +0000475 struct fsldma_chan *chan = to_fsl_chan(dchan);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700476
477 /* Has this channel already been allocated? */
Ira Snydera1c03312010-01-06 13:34:05 +0000478 if (chan->desc_pool)
Timur Tabi77cd62e2008-09-26 17:00:11 -0700479 return 1;
Zhang Wei173acc72008-03-01 07:42:48 -0700480
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000481 /*
482 * We need the descriptor to be aligned to 32bytes
Zhang Wei173acc72008-03-01 07:42:48 -0700483 * for meeting FSL DMA specification requirement.
484 */
Ira Snyderb1584712011-03-03 07:54:55 +0000485 chan->desc_pool = dma_pool_create(chan->name, chan->dev,
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000486 sizeof(struct fsl_desc_sw),
487 __alignof__(struct fsl_desc_sw), 0);
Ira Snydera1c03312010-01-06 13:34:05 +0000488 if (!chan->desc_pool) {
Ira Snyderb1584712011-03-03 07:54:55 +0000489 chan_err(chan, "unable to allocate descriptor pool\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000490 return -ENOMEM;
Zhang Wei173acc72008-03-01 07:42:48 -0700491 }
492
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000493 /* there is at least one descriptor free to be allocated */
Zhang Wei173acc72008-03-01 07:42:48 -0700494 return 1;
495}
496
497/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000498 * fsldma_free_desc_list - Free all descriptors in a queue
499 * @chan: Freescae DMA channel
500 * @list: the list to free
501 *
502 * LOCKING: must hold chan->desc_lock
503 */
504static void fsldma_free_desc_list(struct fsldma_chan *chan,
505 struct list_head *list)
506{
507 struct fsl_desc_sw *desc, *_desc;
508
509 list_for_each_entry_safe(desc, _desc, list, node) {
510 list_del(&desc->node);
Ira Snyder0ab09c32011-03-03 07:54:56 +0000511#ifdef FSL_DMA_LD_DEBUG
512 chan_dbg(chan, "LD %p free\n", desc);
513#endif
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000514 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
515 }
516}
517
518static void fsldma_free_desc_list_reverse(struct fsldma_chan *chan,
519 struct list_head *list)
520{
521 struct fsl_desc_sw *desc, *_desc;
522
523 list_for_each_entry_safe_reverse(desc, _desc, list, node) {
524 list_del(&desc->node);
Ira Snyder0ab09c32011-03-03 07:54:56 +0000525#ifdef FSL_DMA_LD_DEBUG
526 chan_dbg(chan, "LD %p free\n", desc);
527#endif
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000528 dma_pool_free(chan->desc_pool, desc, desc->async_tx.phys);
529 }
530}
531
532/**
Zhang Wei173acc72008-03-01 07:42:48 -0700533 * fsl_dma_free_chan_resources - Free all resources of the channel.
Ira Snydera1c03312010-01-06 13:34:05 +0000534 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700535 */
Ira Snydera1c03312010-01-06 13:34:05 +0000536static void fsl_dma_free_chan_resources(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700537{
Ira Snydera1c03312010-01-06 13:34:05 +0000538 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700539 unsigned long flags;
540
Ira Snyderb1584712011-03-03 07:54:55 +0000541 chan_dbg(chan, "free all channel resources\n");
Ira Snydera1c03312010-01-06 13:34:05 +0000542 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000543 fsldma_free_desc_list(chan, &chan->ld_pending);
544 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snydera1c03312010-01-06 13:34:05 +0000545 spin_unlock_irqrestore(&chan->desc_lock, flags);
Timur Tabi77cd62e2008-09-26 17:00:11 -0700546
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000547 dma_pool_destroy(chan->desc_pool);
Ira Snydera1c03312010-01-06 13:34:05 +0000548 chan->desc_pool = NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700549}
550
Zhang Wei2187c262008-03-13 17:45:28 -0700551static struct dma_async_tx_descriptor *
Ira Snydera1c03312010-01-06 13:34:05 +0000552fsl_dma_prep_interrupt(struct dma_chan *dchan, unsigned long flags)
Zhang Wei2187c262008-03-13 17:45:28 -0700553{
Ira Snydera1c03312010-01-06 13:34:05 +0000554 struct fsldma_chan *chan;
Zhang Wei2187c262008-03-13 17:45:28 -0700555 struct fsl_desc_sw *new;
556
Ira Snydera1c03312010-01-06 13:34:05 +0000557 if (!dchan)
Zhang Wei2187c262008-03-13 17:45:28 -0700558 return NULL;
559
Ira Snydera1c03312010-01-06 13:34:05 +0000560 chan = to_fsl_chan(dchan);
Zhang Wei2187c262008-03-13 17:45:28 -0700561
Ira Snydera1c03312010-01-06 13:34:05 +0000562 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei2187c262008-03-13 17:45:28 -0700563 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000564 chan_err(chan, "%s\n", msg_ld_oom);
Zhang Wei2187c262008-03-13 17:45:28 -0700565 return NULL;
566 }
567
568 new->async_tx.cookie = -EBUSY;
Dan Williams636bdea2008-04-17 20:17:26 -0700569 new->async_tx.flags = flags;
Zhang Wei2187c262008-03-13 17:45:28 -0700570
Zhang Weif79abb62008-03-18 18:45:00 -0700571 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700572 list_add_tail(&new->node, &new->tx_list);
Zhang Weif79abb62008-03-18 18:45:00 -0700573
Ira Snyder31f43062011-03-03 07:54:57 +0000574 /* Set End-of-link to the last link descriptor of new list */
Ira Snydera1c03312010-01-06 13:34:05 +0000575 set_ld_eol(chan, new);
Zhang Wei2187c262008-03-13 17:45:28 -0700576
577 return &new->async_tx;
578}
579
Ira Snyder31f43062011-03-03 07:54:57 +0000580static struct dma_async_tx_descriptor *
581fsl_dma_prep_memcpy(struct dma_chan *dchan,
582 dma_addr_t dma_dst, dma_addr_t dma_src,
Zhang Wei173acc72008-03-01 07:42:48 -0700583 size_t len, unsigned long flags)
584{
Ira Snydera1c03312010-01-06 13:34:05 +0000585 struct fsldma_chan *chan;
Zhang Wei173acc72008-03-01 07:42:48 -0700586 struct fsl_desc_sw *first = NULL, *prev = NULL, *new;
587 size_t copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700588
Ira Snydera1c03312010-01-06 13:34:05 +0000589 if (!dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700590 return NULL;
591
592 if (!len)
593 return NULL;
594
Ira Snydera1c03312010-01-06 13:34:05 +0000595 chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700596
597 do {
598
599 /* Allocate the link descriptor from DMA pool */
Ira Snydera1c03312010-01-06 13:34:05 +0000600 new = fsl_dma_alloc_descriptor(chan);
Zhang Wei173acc72008-03-01 07:42:48 -0700601 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000602 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyder2e077f82009-05-15 09:59:46 -0700603 goto fail;
Zhang Wei173acc72008-03-01 07:42:48 -0700604 }
Zhang Wei173acc72008-03-01 07:42:48 -0700605
Zhang Wei56822842008-03-13 10:45:27 -0700606 copy = min(len, (size_t)FSL_DMA_BCR_MAX_CNT);
Zhang Wei173acc72008-03-01 07:42:48 -0700607
Ira Snydera1c03312010-01-06 13:34:05 +0000608 set_desc_cnt(chan, &new->hw, copy);
609 set_desc_src(chan, &new->hw, dma_src);
610 set_desc_dst(chan, &new->hw, dma_dst);
Zhang Wei173acc72008-03-01 07:42:48 -0700611
612 if (!first)
613 first = new;
614 else
Ira Snydera1c03312010-01-06 13:34:05 +0000615 set_desc_next(chan, &prev->hw, new->async_tx.phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700616
617 new->async_tx.cookie = 0;
Dan Williams636bdea2008-04-17 20:17:26 -0700618 async_tx_ack(&new->async_tx);
Zhang Wei173acc72008-03-01 07:42:48 -0700619
620 prev = new;
621 len -= copy;
622 dma_src += copy;
Ira Snyder738f5f72010-01-06 13:34:02 +0000623 dma_dst += copy;
Zhang Wei173acc72008-03-01 07:42:48 -0700624
625 /* Insert the link descriptor to the LD ring */
Dan Williamseda34232009-09-08 17:53:02 -0700626 list_add_tail(&new->node, &first->tx_list);
Zhang Wei173acc72008-03-01 07:42:48 -0700627 } while (len);
628
Dan Williams636bdea2008-04-17 20:17:26 -0700629 new->async_tx.flags = flags; /* client is in control of this ack */
Zhang Wei173acc72008-03-01 07:42:48 -0700630 new->async_tx.cookie = -EBUSY;
631
Ira Snyder31f43062011-03-03 07:54:57 +0000632 /* Set End-of-link to the last link descriptor of new list */
Ira Snydera1c03312010-01-06 13:34:05 +0000633 set_ld_eol(chan, new);
Zhang Wei173acc72008-03-01 07:42:48 -0700634
Ira Snyder2e077f82009-05-15 09:59:46 -0700635 return &first->async_tx;
636
637fail:
638 if (!first)
639 return NULL;
640
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000641 fsldma_free_desc_list_reverse(chan, &first->tx_list);
Ira Snyder2e077f82009-05-15 09:59:46 -0700642 return NULL;
Zhang Wei173acc72008-03-01 07:42:48 -0700643}
644
Ira Snyderc14330412010-09-30 11:46:45 +0000645static struct dma_async_tx_descriptor *fsl_dma_prep_sg(struct dma_chan *dchan,
646 struct scatterlist *dst_sg, unsigned int dst_nents,
647 struct scatterlist *src_sg, unsigned int src_nents,
648 unsigned long flags)
649{
650 struct fsl_desc_sw *first = NULL, *prev = NULL, *new = NULL;
651 struct fsldma_chan *chan = to_fsl_chan(dchan);
652 size_t dst_avail, src_avail;
653 dma_addr_t dst, src;
654 size_t len;
655
656 /* basic sanity checks */
657 if (dst_nents == 0 || src_nents == 0)
658 return NULL;
659
660 if (dst_sg == NULL || src_sg == NULL)
661 return NULL;
662
663 /*
664 * TODO: should we check that both scatterlists have the same
665 * TODO: number of bytes in total? Is that really an error?
666 */
667
668 /* get prepared for the loop */
669 dst_avail = sg_dma_len(dst_sg);
670 src_avail = sg_dma_len(src_sg);
671
672 /* run until we are out of scatterlist entries */
673 while (true) {
674
675 /* create the largest transaction possible */
676 len = min_t(size_t, src_avail, dst_avail);
677 len = min_t(size_t, len, FSL_DMA_BCR_MAX_CNT);
678 if (len == 0)
679 goto fetch;
680
681 dst = sg_dma_address(dst_sg) + sg_dma_len(dst_sg) - dst_avail;
682 src = sg_dma_address(src_sg) + sg_dma_len(src_sg) - src_avail;
683
684 /* allocate and populate the descriptor */
685 new = fsl_dma_alloc_descriptor(chan);
686 if (!new) {
Ira Snyderb1584712011-03-03 07:54:55 +0000687 chan_err(chan, "%s\n", msg_ld_oom);
Ira Snyderc14330412010-09-30 11:46:45 +0000688 goto fail;
689 }
Ira Snyderc14330412010-09-30 11:46:45 +0000690
691 set_desc_cnt(chan, &new->hw, len);
692 set_desc_src(chan, &new->hw, src);
693 set_desc_dst(chan, &new->hw, dst);
694
695 if (!first)
696 first = new;
697 else
698 set_desc_next(chan, &prev->hw, new->async_tx.phys);
699
700 new->async_tx.cookie = 0;
701 async_tx_ack(&new->async_tx);
702 prev = new;
703
704 /* Insert the link descriptor to the LD ring */
705 list_add_tail(&new->node, &first->tx_list);
706
707 /* update metadata */
708 dst_avail -= len;
709 src_avail -= len;
710
711fetch:
712 /* fetch the next dst scatterlist entry */
713 if (dst_avail == 0) {
714
715 /* no more entries: we're done */
716 if (dst_nents == 0)
717 break;
718
719 /* fetch the next entry: if there are no more: done */
720 dst_sg = sg_next(dst_sg);
721 if (dst_sg == NULL)
722 break;
723
724 dst_nents--;
725 dst_avail = sg_dma_len(dst_sg);
726 }
727
728 /* fetch the next src scatterlist entry */
729 if (src_avail == 0) {
730
731 /* no more entries: we're done */
732 if (src_nents == 0)
733 break;
734
735 /* fetch the next entry: if there are no more: done */
736 src_sg = sg_next(src_sg);
737 if (src_sg == NULL)
738 break;
739
740 src_nents--;
741 src_avail = sg_dma_len(src_sg);
742 }
743 }
744
745 new->async_tx.flags = flags; /* client is in control of this ack */
746 new->async_tx.cookie = -EBUSY;
747
748 /* Set End-of-link to the last link descriptor of new list */
749 set_ld_eol(chan, new);
750
751 return &first->async_tx;
752
753fail:
754 if (!first)
755 return NULL;
756
757 fsldma_free_desc_list_reverse(chan, &first->tx_list);
758 return NULL;
759}
760
Zhang Wei173acc72008-03-01 07:42:48 -0700761/**
Ira Snyderbbea0b62009-09-08 17:53:04 -0700762 * fsl_dma_prep_slave_sg - prepare descriptors for a DMA_SLAVE transaction
763 * @chan: DMA channel
764 * @sgl: scatterlist to transfer to/from
765 * @sg_len: number of entries in @scatterlist
766 * @direction: DMA direction
767 * @flags: DMAEngine flags
768 *
769 * Prepare a set of descriptors for a DMA_SLAVE transaction. Following the
770 * DMA_SLAVE API, this gets the device-specific information from the
771 * chan->private variable.
772 */
773static struct dma_async_tx_descriptor *fsl_dma_prep_slave_sg(
Ira Snydera1c03312010-01-06 13:34:05 +0000774 struct dma_chan *dchan, struct scatterlist *sgl, unsigned int sg_len,
Vinod Kouldb8196d2011-10-13 22:34:23 +0530775 enum dma_transfer_direction direction, unsigned long flags)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700776{
Ira Snyderbbea0b62009-09-08 17:53:04 -0700777 /*
Ira Snyder968f19a2010-09-30 11:46:46 +0000778 * This operation is not supported on the Freescale DMA controller
Ira Snyderbbea0b62009-09-08 17:53:04 -0700779 *
Ira Snyder968f19a2010-09-30 11:46:46 +0000780 * However, we need to provide the function pointer to allow the
781 * device_control() method to work.
Ira Snyderbbea0b62009-09-08 17:53:04 -0700782 */
Ira Snyderbbea0b62009-09-08 17:53:04 -0700783 return NULL;
784}
785
Linus Walleijc3635c72010-03-26 16:44:01 -0700786static int fsl_dma_device_control(struct dma_chan *dchan,
Linus Walleij05827632010-05-17 16:30:42 -0700787 enum dma_ctrl_cmd cmd, unsigned long arg)
Ira Snyderbbea0b62009-09-08 17:53:04 -0700788{
Ira Snyder968f19a2010-09-30 11:46:46 +0000789 struct dma_slave_config *config;
Ira Snydera1c03312010-01-06 13:34:05 +0000790 struct fsldma_chan *chan;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700791 unsigned long flags;
Ira Snyder968f19a2010-09-30 11:46:46 +0000792 int size;
Linus Walleijc3635c72010-03-26 16:44:01 -0700793
Ira Snydera1c03312010-01-06 13:34:05 +0000794 if (!dchan)
Linus Walleijc3635c72010-03-26 16:44:01 -0700795 return -EINVAL;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700796
Ira Snydera1c03312010-01-06 13:34:05 +0000797 chan = to_fsl_chan(dchan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700798
Ira Snyder968f19a2010-09-30 11:46:46 +0000799 switch (cmd) {
800 case DMA_TERMINATE_ALL:
Ira Snyderf04cd402011-03-03 07:54:58 +0000801 spin_lock_irqsave(&chan->desc_lock, flags);
802
Ira Snyder968f19a2010-09-30 11:46:46 +0000803 /* Halt the DMA engine */
804 dma_halt(chan);
Ira Snyderbbea0b62009-09-08 17:53:04 -0700805
Ira Snyder968f19a2010-09-30 11:46:46 +0000806 /* Remove and free all of the descriptors in the LD queue */
807 fsldma_free_desc_list(chan, &chan->ld_pending);
808 fsldma_free_desc_list(chan, &chan->ld_running);
Ira Snyderf04cd402011-03-03 07:54:58 +0000809 chan->idle = true;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700810
Ira Snyder968f19a2010-09-30 11:46:46 +0000811 spin_unlock_irqrestore(&chan->desc_lock, flags);
812 return 0;
813
814 case DMA_SLAVE_CONFIG:
815 config = (struct dma_slave_config *)arg;
816
817 /* make sure the channel supports setting burst size */
818 if (!chan->set_request_count)
819 return -ENXIO;
820
821 /* we set the controller burst size depending on direction */
Vinod Kouldb8196d2011-10-13 22:34:23 +0530822 if (config->direction == DMA_MEM_TO_DEV)
Ira Snyder968f19a2010-09-30 11:46:46 +0000823 size = config->dst_addr_width * config->dst_maxburst;
824 else
825 size = config->src_addr_width * config->src_maxburst;
826
827 chan->set_request_count(chan, size);
828 return 0;
829
830 case FSLDMA_EXTERNAL_START:
831
832 /* make sure the channel supports external start */
833 if (!chan->toggle_ext_start)
834 return -ENXIO;
835
836 chan->toggle_ext_start(chan, arg);
837 return 0;
838
839 default:
840 return -ENXIO;
841 }
Linus Walleijc3635c72010-03-26 16:44:01 -0700842
843 return 0;
Ira Snyderbbea0b62009-09-08 17:53:04 -0700844}
845
846/**
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000847 * fsldma_cleanup_descriptor - cleanup and free a single link descriptor
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000848 * @chan: Freescale DMA channel
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000849 * @desc: descriptor to cleanup and free
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000850 *
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000851 * This function is used on a descriptor which has been executed by the DMA
852 * controller. It will run any callbacks, submit any dependencies, and then
853 * free the descriptor.
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000854 */
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000855static void fsldma_cleanup_descriptor(struct fsldma_chan *chan,
856 struct fsl_desc_sw *desc)
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000857{
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000858 struct dma_async_tx_descriptor *txd = &desc->async_tx;
859 struct device *dev = chan->common.device->dev;
860 dma_addr_t src = get_desc_src(chan, desc);
861 dma_addr_t dst = get_desc_dst(chan, desc);
862 u32 len = get_desc_cnt(chan, desc);
Zhang Wei173acc72008-03-01 07:42:48 -0700863
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000864 /* Run the link descriptor callback function */
865 if (txd->callback) {
866#ifdef FSL_DMA_LD_DEBUG
867 chan_dbg(chan, "LD %p callback\n", desc);
868#endif
869 txd->callback(txd->callback_param);
Zhang Wei173acc72008-03-01 07:42:48 -0700870 }
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000871
Ira Snyder9c4d1e72011-03-03 07:54:59 +0000872 /* Run any dependencies */
873 dma_run_dependencies(txd);
874
875 /* Unmap the dst buffer, if requested */
876 if (!(txd->flags & DMA_COMPL_SKIP_DEST_UNMAP)) {
877 if (txd->flags & DMA_COMPL_DEST_UNMAP_SINGLE)
878 dma_unmap_single(dev, dst, len, DMA_FROM_DEVICE);
879 else
880 dma_unmap_page(dev, dst, len, DMA_FROM_DEVICE);
881 }
882
883 /* Unmap the src buffer, if requested */
884 if (!(txd->flags & DMA_COMPL_SKIP_SRC_UNMAP)) {
885 if (txd->flags & DMA_COMPL_SRC_UNMAP_SINGLE)
886 dma_unmap_single(dev, src, len, DMA_TO_DEVICE);
887 else
888 dma_unmap_page(dev, src, len, DMA_TO_DEVICE);
889 }
890
891#ifdef FSL_DMA_LD_DEBUG
892 chan_dbg(chan, "LD %p free\n", desc);
893#endif
894 dma_pool_free(chan->desc_pool, desc, txd->phys);
Zhang Wei173acc72008-03-01 07:42:48 -0700895}
896
897/**
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000898 * fsl_chan_xfer_ld_queue - transfer any pending transactions
Ira Snydera1c03312010-01-06 13:34:05 +0000899 * @chan : Freescale DMA channel
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000900 *
Ira Snyderf04cd402011-03-03 07:54:58 +0000901 * HARDWARE STATE: idle
Ira Snyderdc8d4092011-03-03 07:55:00 +0000902 * LOCKING: must hold chan->desc_lock
Zhang Wei173acc72008-03-01 07:42:48 -0700903 */
Ira Snydera1c03312010-01-06 13:34:05 +0000904static void fsl_chan_xfer_ld_queue(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -0700905{
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000906 struct fsl_desc_sw *desc;
Ira Snyder138ef012009-05-19 15:42:13 -0700907
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000908 /*
909 * If the list of pending descriptors is empty, then we
910 * don't need to do any work at all
911 */
912 if (list_empty(&chan->ld_pending)) {
Ira Snyderb1584712011-03-03 07:54:55 +0000913 chan_dbg(chan, "no pending LDs\n");
Ira Snyderdc8d4092011-03-03 07:55:00 +0000914 return;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000915 }
Zhang Wei173acc72008-03-01 07:42:48 -0700916
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000917 /*
Ira Snyderf04cd402011-03-03 07:54:58 +0000918 * The DMA controller is not idle, which means that the interrupt
919 * handler will start any queued transactions when it runs after
920 * this transaction finishes
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000921 */
Ira Snyderf04cd402011-03-03 07:54:58 +0000922 if (!chan->idle) {
Ira Snyderb1584712011-03-03 07:54:55 +0000923 chan_dbg(chan, "DMA controller still busy\n");
Ira Snyderdc8d4092011-03-03 07:55:00 +0000924 return;
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000925 }
926
927 /*
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000928 * If there are some link descriptors which have not been
929 * transferred, we need to start the controller
Zhang Wei173acc72008-03-01 07:42:48 -0700930 */
Zhang Wei173acc72008-03-01 07:42:48 -0700931
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000932 /*
933 * Move all elements from the queue of pending transactions
934 * onto the list of running transactions
935 */
Ira Snyderf04cd402011-03-03 07:54:58 +0000936 chan_dbg(chan, "idle, starting controller\n");
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000937 desc = list_first_entry(&chan->ld_pending, struct fsl_desc_sw, node);
938 list_splice_tail_init(&chan->ld_pending, &chan->ld_running);
Zhang Wei173acc72008-03-01 07:42:48 -0700939
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000940 /*
Ira Snyderf04cd402011-03-03 07:54:58 +0000941 * The 85xx DMA controller doesn't clear the channel start bit
942 * automatically at the end of a transfer. Therefore we must clear
943 * it in software before starting the transfer.
944 */
945 if ((chan->feature & FSL_DMA_IP_MASK) == FSL_DMA_IP_85XX) {
946 u32 mode;
947
948 mode = DMA_IN(chan, &chan->regs->mr, 32);
949 mode &= ~FSL_DMA_MR_CS;
950 DMA_OUT(chan, &chan->regs->mr, mode, 32);
951 }
952
953 /*
Ira Snyder9c3a50b2010-01-06 13:34:06 +0000954 * Program the descriptor's address into the DMA controller,
955 * then start the DMA transaction
956 */
957 set_cdar(chan, desc->async_tx.phys);
Ira Snyderf04cd402011-03-03 07:54:58 +0000958 get_cdar(chan);
Ira Snyder138ef012009-05-19 15:42:13 -0700959
Zhang Wei173acc72008-03-01 07:42:48 -0700960 dma_start(chan);
Ira Snyderf04cd402011-03-03 07:54:58 +0000961 chan->idle = false;
Zhang Wei173acc72008-03-01 07:42:48 -0700962}
963
964/**
965 * fsl_dma_memcpy_issue_pending - Issue the DMA start command
Ira Snydera1c03312010-01-06 13:34:05 +0000966 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700967 */
Ira Snydera1c03312010-01-06 13:34:05 +0000968static void fsl_dma_memcpy_issue_pending(struct dma_chan *dchan)
Zhang Wei173acc72008-03-01 07:42:48 -0700969{
Ira Snydera1c03312010-01-06 13:34:05 +0000970 struct fsldma_chan *chan = to_fsl_chan(dchan);
Ira Snyderdc8d4092011-03-03 07:55:00 +0000971 unsigned long flags;
972
973 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snydera1c03312010-01-06 13:34:05 +0000974 fsl_chan_xfer_ld_queue(chan);
Ira Snyderdc8d4092011-03-03 07:55:00 +0000975 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700976}
977
Zhang Wei173acc72008-03-01 07:42:48 -0700978/**
Linus Walleij07934482010-03-26 16:50:49 -0700979 * fsl_tx_status - Determine the DMA status
Ira Snydera1c03312010-01-06 13:34:05 +0000980 * @chan : Freescale DMA channel
Zhang Wei173acc72008-03-01 07:42:48 -0700981 */
Linus Walleij07934482010-03-26 16:50:49 -0700982static enum dma_status fsl_tx_status(struct dma_chan *dchan,
Zhang Wei173acc72008-03-01 07:42:48 -0700983 dma_cookie_t cookie,
Linus Walleij07934482010-03-26 16:50:49 -0700984 struct dma_tx_state *txstate)
Zhang Wei173acc72008-03-01 07:42:48 -0700985{
Ira Snydera1c03312010-01-06 13:34:05 +0000986 struct fsldma_chan *chan = to_fsl_chan(dchan);
Zhang Wei173acc72008-03-01 07:42:48 -0700987 dma_cookie_t last_complete;
Ira Snyderf04cd402011-03-03 07:54:58 +0000988 dma_cookie_t last_used;
989 unsigned long flags;
Zhang Wei173acc72008-03-01 07:42:48 -0700990
Ira Snyderf04cd402011-03-03 07:54:58 +0000991 spin_lock_irqsave(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700992
Ira Snydera1c03312010-01-06 13:34:05 +0000993 last_complete = chan->completed_cookie;
Ira Snyderf04cd402011-03-03 07:54:58 +0000994 last_used = dchan->cookie;
995
996 spin_unlock_irqrestore(&chan->desc_lock, flags);
Zhang Wei173acc72008-03-01 07:42:48 -0700997
Dan Williamsbca34692010-03-26 16:52:10 -0700998 dma_set_tx_state(txstate, last_complete, last_used, 0);
Zhang Wei173acc72008-03-01 07:42:48 -0700999 return dma_async_is_complete(cookie, last_complete, last_used);
1000}
1001
Ira Snyderd3f620b2010-01-06 13:34:04 +00001002/*----------------------------------------------------------------------------*/
1003/* Interrupt Handling */
1004/*----------------------------------------------------------------------------*/
1005
Ira Snydere7a29152010-01-06 13:34:03 +00001006static irqreturn_t fsldma_chan_irq(int irq, void *data)
Zhang Wei173acc72008-03-01 07:42:48 -07001007{
Ira Snydera1c03312010-01-06 13:34:05 +00001008 struct fsldma_chan *chan = data;
Ira Snydera1c03312010-01-06 13:34:05 +00001009 u32 stat;
Zhang Wei173acc72008-03-01 07:42:48 -07001010
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001011 /* save and clear the status register */
Ira Snydera1c03312010-01-06 13:34:05 +00001012 stat = get_sr(chan);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001013 set_sr(chan, stat);
Ira Snyderb1584712011-03-03 07:54:55 +00001014 chan_dbg(chan, "irq: stat = 0x%x\n", stat);
Zhang Wei173acc72008-03-01 07:42:48 -07001015
Ira Snyderf04cd402011-03-03 07:54:58 +00001016 /* check that this was really our device */
Zhang Wei173acc72008-03-01 07:42:48 -07001017 stat &= ~(FSL_DMA_SR_CB | FSL_DMA_SR_CH);
1018 if (!stat)
1019 return IRQ_NONE;
1020
1021 if (stat & FSL_DMA_SR_TE)
Ira Snyderb1584712011-03-03 07:54:55 +00001022 chan_err(chan, "Transfer Error!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001023
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001024 /*
1025 * Programming Error
Zhang Weif79abb62008-03-18 18:45:00 -07001026 * The DMA_INTERRUPT async_tx is a NULL transfer, which will
1027 * triger a PE interrupt.
1028 */
1029 if (stat & FSL_DMA_SR_PE) {
Ira Snyderb1584712011-03-03 07:54:55 +00001030 chan_dbg(chan, "irq: Programming Error INT\n");
Zhang Weif79abb62008-03-18 18:45:00 -07001031 stat &= ~FSL_DMA_SR_PE;
Ira Snyderf04cd402011-03-03 07:54:58 +00001032 if (get_bcr(chan) != 0)
1033 chan_err(chan, "Programming Error!\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001034 }
1035
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001036 /*
1037 * For MPC8349, EOCDI event need to update cookie
Zhang Wei1c629792008-04-17 20:17:25 -07001038 * and start the next transfer if it exist.
1039 */
1040 if (stat & FSL_DMA_SR_EOCDI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001041 chan_dbg(chan, "irq: End-of-Chain link INT\n");
Zhang Wei1c629792008-04-17 20:17:25 -07001042 stat &= ~FSL_DMA_SR_EOCDI;
Zhang Wei173acc72008-03-01 07:42:48 -07001043 }
1044
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001045 /*
1046 * If it current transfer is the end-of-transfer,
Zhang Wei173acc72008-03-01 07:42:48 -07001047 * we should clear the Channel Start bit for
1048 * prepare next transfer.
1049 */
Zhang Wei1c629792008-04-17 20:17:25 -07001050 if (stat & FSL_DMA_SR_EOLNI) {
Ira Snyderb1584712011-03-03 07:54:55 +00001051 chan_dbg(chan, "irq: End-of-link INT\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001052 stat &= ~FSL_DMA_SR_EOLNI;
Zhang Wei173acc72008-03-01 07:42:48 -07001053 }
1054
Ira Snyderf04cd402011-03-03 07:54:58 +00001055 /* check that the DMA controller is really idle */
1056 if (!dma_is_idle(chan))
1057 chan_err(chan, "irq: controller not idle!\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001058
Ira Snyderf04cd402011-03-03 07:54:58 +00001059 /* check that we handled all of the bits */
1060 if (stat)
1061 chan_err(chan, "irq: unhandled sr 0x%08x\n", stat);
1062
1063 /*
1064 * Schedule the tasklet to handle all cleanup of the current
1065 * transaction. It will start a new transaction if there is
1066 * one pending.
1067 */
Ira Snydera1c03312010-01-06 13:34:05 +00001068 tasklet_schedule(&chan->tasklet);
Ira Snyderf04cd402011-03-03 07:54:58 +00001069 chan_dbg(chan, "irq: Exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001070 return IRQ_HANDLED;
1071}
1072
Zhang Wei173acc72008-03-01 07:42:48 -07001073static void dma_do_tasklet(unsigned long data)
1074{
Ira Snydera1c03312010-01-06 13:34:05 +00001075 struct fsldma_chan *chan = (struct fsldma_chan *)data;
Ira Snyderdc8d4092011-03-03 07:55:00 +00001076 struct fsl_desc_sw *desc, *_desc;
1077 LIST_HEAD(ld_cleanup);
Ira Snyderf04cd402011-03-03 07:54:58 +00001078 unsigned long flags;
1079
1080 chan_dbg(chan, "tasklet entry\n");
1081
Ira Snyderf04cd402011-03-03 07:54:58 +00001082 spin_lock_irqsave(&chan->desc_lock, flags);
Ira Snyderdc8d4092011-03-03 07:55:00 +00001083
1084 /* update the cookie if we have some descriptors to cleanup */
1085 if (!list_empty(&chan->ld_running)) {
1086 dma_cookie_t cookie;
1087
1088 desc = to_fsl_desc(chan->ld_running.prev);
1089 cookie = desc->async_tx.cookie;
1090
1091 chan->completed_cookie = cookie;
1092 chan_dbg(chan, "completed_cookie=%d\n", cookie);
1093 }
1094
1095 /*
1096 * move the descriptors to a temporary list so we can drop the lock
1097 * during the entire cleanup operation
1098 */
1099 list_splice_tail_init(&chan->ld_running, &ld_cleanup);
1100
1101 /* the hardware is now idle and ready for more */
Ira Snyderf04cd402011-03-03 07:54:58 +00001102 chan->idle = true;
Ira Snyderdc8d4092011-03-03 07:55:00 +00001103
1104 /*
1105 * Start any pending transactions automatically
1106 *
1107 * In the ideal case, we keep the DMA controller busy while we go
1108 * ahead and free the descriptors below.
1109 */
1110 fsl_chan_xfer_ld_queue(chan);
Ira Snyderf04cd402011-03-03 07:54:58 +00001111 spin_unlock_irqrestore(&chan->desc_lock, flags);
1112
Ira Snyderdc8d4092011-03-03 07:55:00 +00001113 /* Run the callback for each descriptor, in order */
1114 list_for_each_entry_safe(desc, _desc, &ld_cleanup, node) {
1115
1116 /* Remove from the list of transactions */
1117 list_del(&desc->node);
1118
1119 /* Run all cleanup for this descriptor */
1120 fsldma_cleanup_descriptor(chan, desc);
1121 }
1122
Ira Snyderf04cd402011-03-03 07:54:58 +00001123 chan_dbg(chan, "tasklet exit\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001124}
1125
Ira Snyderd3f620b2010-01-06 13:34:04 +00001126static irqreturn_t fsldma_ctrl_irq(int irq, void *data)
1127{
1128 struct fsldma_device *fdev = data;
1129 struct fsldma_chan *chan;
1130 unsigned int handled = 0;
1131 u32 gsr, mask;
1132 int i;
1133
1134 gsr = (fdev->feature & FSL_DMA_BIG_ENDIAN) ? in_be32(fdev->regs)
1135 : in_le32(fdev->regs);
1136 mask = 0xff000000;
1137 dev_dbg(fdev->dev, "IRQ: gsr 0x%.8x\n", gsr);
1138
1139 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1140 chan = fdev->chan[i];
1141 if (!chan)
1142 continue;
1143
1144 if (gsr & mask) {
1145 dev_dbg(fdev->dev, "IRQ: chan %d\n", chan->id);
1146 fsldma_chan_irq(irq, chan);
1147 handled++;
1148 }
1149
1150 gsr &= ~mask;
1151 mask >>= 8;
1152 }
1153
1154 return IRQ_RETVAL(handled);
1155}
1156
1157static void fsldma_free_irqs(struct fsldma_device *fdev)
1158{
1159 struct fsldma_chan *chan;
1160 int i;
1161
1162 if (fdev->irq != NO_IRQ) {
1163 dev_dbg(fdev->dev, "free per-controller IRQ\n");
1164 free_irq(fdev->irq, fdev);
1165 return;
1166 }
1167
1168 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1169 chan = fdev->chan[i];
1170 if (chan && chan->irq != NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001171 chan_dbg(chan, "free per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001172 free_irq(chan->irq, chan);
1173 }
1174 }
1175}
1176
1177static int fsldma_request_irqs(struct fsldma_device *fdev)
1178{
1179 struct fsldma_chan *chan;
1180 int ret;
1181 int i;
1182
1183 /* if we have a per-controller IRQ, use that */
1184 if (fdev->irq != NO_IRQ) {
1185 dev_dbg(fdev->dev, "request per-controller IRQ\n");
1186 ret = request_irq(fdev->irq, fsldma_ctrl_irq, IRQF_SHARED,
1187 "fsldma-controller", fdev);
1188 return ret;
1189 }
1190
1191 /* no per-controller IRQ, use the per-channel IRQs */
1192 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
1193 chan = fdev->chan[i];
1194 if (!chan)
1195 continue;
1196
1197 if (chan->irq == NO_IRQ) {
Ira Snyderb1584712011-03-03 07:54:55 +00001198 chan_err(chan, "interrupts property missing in device tree\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001199 ret = -ENODEV;
1200 goto out_unwind;
1201 }
1202
Ira Snyderb1584712011-03-03 07:54:55 +00001203 chan_dbg(chan, "request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001204 ret = request_irq(chan->irq, fsldma_chan_irq, IRQF_SHARED,
1205 "fsldma-chan", chan);
1206 if (ret) {
Ira Snyderb1584712011-03-03 07:54:55 +00001207 chan_err(chan, "unable to request per-channel IRQ\n");
Ira Snyderd3f620b2010-01-06 13:34:04 +00001208 goto out_unwind;
1209 }
1210 }
1211
1212 return 0;
1213
1214out_unwind:
1215 for (/* none */; i >= 0; i--) {
1216 chan = fdev->chan[i];
1217 if (!chan)
1218 continue;
1219
1220 if (chan->irq == NO_IRQ)
1221 continue;
1222
1223 free_irq(chan->irq, chan);
1224 }
1225
1226 return ret;
1227}
1228
Ira Snydera4f56d42010-01-06 13:34:01 +00001229/*----------------------------------------------------------------------------*/
1230/* OpenFirmware Subsystem */
1231/*----------------------------------------------------------------------------*/
1232
1233static int __devinit fsl_dma_chan_probe(struct fsldma_device *fdev,
Timur Tabi77cd62e2008-09-26 17:00:11 -07001234 struct device_node *node, u32 feature, const char *compatible)
Zhang Wei173acc72008-03-01 07:42:48 -07001235{
Ira Snydera1c03312010-01-06 13:34:05 +00001236 struct fsldma_chan *chan;
Ira Snyder4ce0e952010-01-06 13:34:00 +00001237 struct resource res;
Zhang Wei173acc72008-03-01 07:42:48 -07001238 int err;
1239
Zhang Wei173acc72008-03-01 07:42:48 -07001240 /* alloc channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001241 chan = kzalloc(sizeof(*chan), GFP_KERNEL);
1242 if (!chan) {
Ira Snydere7a29152010-01-06 13:34:03 +00001243 dev_err(fdev->dev, "no free memory for DMA channels!\n");
1244 err = -ENOMEM;
1245 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001246 }
1247
Ira Snydere7a29152010-01-06 13:34:03 +00001248 /* ioremap registers for use */
Ira Snydera1c03312010-01-06 13:34:05 +00001249 chan->regs = of_iomap(node, 0);
1250 if (!chan->regs) {
Ira Snydere7a29152010-01-06 13:34:03 +00001251 dev_err(fdev->dev, "unable to ioremap registers\n");
1252 err = -ENOMEM;
Ira Snydera1c03312010-01-06 13:34:05 +00001253 goto out_free_chan;
Ira Snydere7a29152010-01-06 13:34:03 +00001254 }
1255
Ira Snyder4ce0e952010-01-06 13:34:00 +00001256 err = of_address_to_resource(node, 0, &res);
Zhang Wei173acc72008-03-01 07:42:48 -07001257 if (err) {
Ira Snydere7a29152010-01-06 13:34:03 +00001258 dev_err(fdev->dev, "unable to find 'reg' property\n");
1259 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001260 }
1261
Ira Snydera1c03312010-01-06 13:34:05 +00001262 chan->feature = feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001263 if (!fdev->feature)
Ira Snydera1c03312010-01-06 13:34:05 +00001264 fdev->feature = chan->feature;
Zhang Wei173acc72008-03-01 07:42:48 -07001265
Ira Snydere7a29152010-01-06 13:34:03 +00001266 /*
1267 * If the DMA device's feature is different than the feature
1268 * of its channels, report the bug
Zhang Wei173acc72008-03-01 07:42:48 -07001269 */
Ira Snydera1c03312010-01-06 13:34:05 +00001270 WARN_ON(fdev->feature != chan->feature);
Zhang Wei173acc72008-03-01 07:42:48 -07001271
Ira Snydera1c03312010-01-06 13:34:05 +00001272 chan->dev = fdev->dev;
1273 chan->id = ((res.start - 0x100) & 0xfff) >> 7;
1274 if (chan->id >= FSL_DMA_MAX_CHANS_PER_DEVICE) {
Ira Snydere7a29152010-01-06 13:34:03 +00001275 dev_err(fdev->dev, "too many channels for device\n");
Zhang Wei173acc72008-03-01 07:42:48 -07001276 err = -EINVAL;
Ira Snydere7a29152010-01-06 13:34:03 +00001277 goto out_iounmap_regs;
Zhang Wei173acc72008-03-01 07:42:48 -07001278 }
Zhang Wei173acc72008-03-01 07:42:48 -07001279
Ira Snydera1c03312010-01-06 13:34:05 +00001280 fdev->chan[chan->id] = chan;
1281 tasklet_init(&chan->tasklet, dma_do_tasklet, (unsigned long)chan);
Ira Snyderb1584712011-03-03 07:54:55 +00001282 snprintf(chan->name, sizeof(chan->name), "chan%d", chan->id);
Ira Snydere7a29152010-01-06 13:34:03 +00001283
1284 /* Initialize the channel */
Ira Snydera1c03312010-01-06 13:34:05 +00001285 dma_init(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001286
1287 /* Clear cdar registers */
Ira Snydera1c03312010-01-06 13:34:05 +00001288 set_cdar(chan, 0);
Zhang Wei173acc72008-03-01 07:42:48 -07001289
Ira Snydera1c03312010-01-06 13:34:05 +00001290 switch (chan->feature & FSL_DMA_IP_MASK) {
Zhang Wei173acc72008-03-01 07:42:48 -07001291 case FSL_DMA_IP_85XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001292 chan->toggle_ext_pause = fsl_chan_toggle_ext_pause;
Zhang Wei173acc72008-03-01 07:42:48 -07001293 case FSL_DMA_IP_83XX:
Ira Snydera1c03312010-01-06 13:34:05 +00001294 chan->toggle_ext_start = fsl_chan_toggle_ext_start;
1295 chan->set_src_loop_size = fsl_chan_set_src_loop_size;
1296 chan->set_dst_loop_size = fsl_chan_set_dst_loop_size;
1297 chan->set_request_count = fsl_chan_set_request_count;
Zhang Wei173acc72008-03-01 07:42:48 -07001298 }
1299
Ira Snydera1c03312010-01-06 13:34:05 +00001300 spin_lock_init(&chan->desc_lock);
Ira Snyder9c3a50b2010-01-06 13:34:06 +00001301 INIT_LIST_HEAD(&chan->ld_pending);
1302 INIT_LIST_HEAD(&chan->ld_running);
Ira Snyderf04cd402011-03-03 07:54:58 +00001303 chan->idle = true;
Zhang Wei173acc72008-03-01 07:42:48 -07001304
Ira Snydera1c03312010-01-06 13:34:05 +00001305 chan->common.device = &fdev->common;
Zhang Wei173acc72008-03-01 07:42:48 -07001306
Ira Snyderd3f620b2010-01-06 13:34:04 +00001307 /* find the IRQ line, if it exists in the device tree */
Ira Snydera1c03312010-01-06 13:34:05 +00001308 chan->irq = irq_of_parse_and_map(node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001309
Zhang Wei173acc72008-03-01 07:42:48 -07001310 /* Add the channel to DMA device channel list */
Ira Snydera1c03312010-01-06 13:34:05 +00001311 list_add_tail(&chan->common.device_node, &fdev->common.channels);
Zhang Wei173acc72008-03-01 07:42:48 -07001312 fdev->common.chancnt++;
1313
Ira Snydera1c03312010-01-06 13:34:05 +00001314 dev_info(fdev->dev, "#%d (%s), irq %d\n", chan->id, compatible,
1315 chan->irq != NO_IRQ ? chan->irq : fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001316
1317 return 0;
Li Yang51ee87f2008-05-29 23:25:45 -07001318
Ira Snydere7a29152010-01-06 13:34:03 +00001319out_iounmap_regs:
Ira Snydera1c03312010-01-06 13:34:05 +00001320 iounmap(chan->regs);
1321out_free_chan:
1322 kfree(chan);
Ira Snydere7a29152010-01-06 13:34:03 +00001323out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001324 return err;
1325}
1326
Ira Snydera1c03312010-01-06 13:34:05 +00001327static void fsl_dma_chan_remove(struct fsldma_chan *chan)
Zhang Wei173acc72008-03-01 07:42:48 -07001328{
Ira Snydera1c03312010-01-06 13:34:05 +00001329 irq_dispose_mapping(chan->irq);
1330 list_del(&chan->common.device_node);
1331 iounmap(chan->regs);
1332 kfree(chan);
Zhang Wei173acc72008-03-01 07:42:48 -07001333}
1334
Grant Likely00006122011-02-22 19:59:54 -07001335static int __devinit fsldma_of_probe(struct platform_device *op)
Zhang Wei173acc72008-03-01 07:42:48 -07001336{
Ira Snydera4f56d42010-01-06 13:34:01 +00001337 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001338 struct device_node *child;
Ira Snydere7a29152010-01-06 13:34:03 +00001339 int err;
Zhang Wei173acc72008-03-01 07:42:48 -07001340
Ira Snydera4f56d42010-01-06 13:34:01 +00001341 fdev = kzalloc(sizeof(*fdev), GFP_KERNEL);
Zhang Wei173acc72008-03-01 07:42:48 -07001342 if (!fdev) {
Ira Snydere7a29152010-01-06 13:34:03 +00001343 dev_err(&op->dev, "No enough memory for 'priv'\n");
1344 err = -ENOMEM;
1345 goto out_return;
Zhang Wei173acc72008-03-01 07:42:48 -07001346 }
Ira Snydere7a29152010-01-06 13:34:03 +00001347
1348 fdev->dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001349 INIT_LIST_HEAD(&fdev->common.channels);
1350
Ira Snydere7a29152010-01-06 13:34:03 +00001351 /* ioremap the registers for use */
Grant Likely61c7a082010-04-13 16:12:29 -07001352 fdev->regs = of_iomap(op->dev.of_node, 0);
Ira Snydere7a29152010-01-06 13:34:03 +00001353 if (!fdev->regs) {
1354 dev_err(&op->dev, "unable to ioremap registers\n");
1355 err = -ENOMEM;
1356 goto out_free_fdev;
Zhang Wei173acc72008-03-01 07:42:48 -07001357 }
1358
Ira Snyderd3f620b2010-01-06 13:34:04 +00001359 /* map the channel IRQ if it exists, but don't hookup the handler yet */
Grant Likely61c7a082010-04-13 16:12:29 -07001360 fdev->irq = irq_of_parse_and_map(op->dev.of_node, 0);
Ira Snyderd3f620b2010-01-06 13:34:04 +00001361
Zhang Wei173acc72008-03-01 07:42:48 -07001362 dma_cap_set(DMA_MEMCPY, fdev->common.cap_mask);
1363 dma_cap_set(DMA_INTERRUPT, fdev->common.cap_mask);
Ira Snyderc14330412010-09-30 11:46:45 +00001364 dma_cap_set(DMA_SG, fdev->common.cap_mask);
Ira Snyderbbea0b62009-09-08 17:53:04 -07001365 dma_cap_set(DMA_SLAVE, fdev->common.cap_mask);
Zhang Wei173acc72008-03-01 07:42:48 -07001366 fdev->common.device_alloc_chan_resources = fsl_dma_alloc_chan_resources;
1367 fdev->common.device_free_chan_resources = fsl_dma_free_chan_resources;
Zhang Wei2187c262008-03-13 17:45:28 -07001368 fdev->common.device_prep_dma_interrupt = fsl_dma_prep_interrupt;
Zhang Wei173acc72008-03-01 07:42:48 -07001369 fdev->common.device_prep_dma_memcpy = fsl_dma_prep_memcpy;
Ira Snyderc14330412010-09-30 11:46:45 +00001370 fdev->common.device_prep_dma_sg = fsl_dma_prep_sg;
Linus Walleij07934482010-03-26 16:50:49 -07001371 fdev->common.device_tx_status = fsl_tx_status;
Zhang Wei173acc72008-03-01 07:42:48 -07001372 fdev->common.device_issue_pending = fsl_dma_memcpy_issue_pending;
Ira Snyderbbea0b62009-09-08 17:53:04 -07001373 fdev->common.device_prep_slave_sg = fsl_dma_prep_slave_sg;
Linus Walleijc3635c72010-03-26 16:44:01 -07001374 fdev->common.device_control = fsl_dma_device_control;
Ira Snydere7a29152010-01-06 13:34:03 +00001375 fdev->common.dev = &op->dev;
Zhang Wei173acc72008-03-01 07:42:48 -07001376
Li Yange2c8e4252010-11-11 20:16:29 +08001377 dma_set_mask(&(op->dev), DMA_BIT_MASK(36));
1378
Ira Snydere7a29152010-01-06 13:34:03 +00001379 dev_set_drvdata(&op->dev, fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001380
Ira Snydere7a29152010-01-06 13:34:03 +00001381 /*
1382 * We cannot use of_platform_bus_probe() because there is no
1383 * of_platform_bus_remove(). Instead, we manually instantiate every DMA
Timur Tabi77cd62e2008-09-26 17:00:11 -07001384 * channel object.
1385 */
Grant Likely61c7a082010-04-13 16:12:29 -07001386 for_each_child_of_node(op->dev.of_node, child) {
Ira Snydere7a29152010-01-06 13:34:03 +00001387 if (of_device_is_compatible(child, "fsl,eloplus-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001388 fsl_dma_chan_probe(fdev, child,
1389 FSL_DMA_IP_85XX | FSL_DMA_BIG_ENDIAN,
1390 "fsl,eloplus-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001391 }
1392
1393 if (of_device_is_compatible(child, "fsl,elo-dma-channel")) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001394 fsl_dma_chan_probe(fdev, child,
1395 FSL_DMA_IP_83XX | FSL_DMA_LITTLE_ENDIAN,
1396 "fsl,elo-dma-channel");
Ira Snydere7a29152010-01-06 13:34:03 +00001397 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001398 }
Zhang Wei173acc72008-03-01 07:42:48 -07001399
Ira Snyderd3f620b2010-01-06 13:34:04 +00001400 /*
1401 * Hookup the IRQ handler(s)
1402 *
1403 * If we have a per-controller interrupt, we prefer that to the
1404 * per-channel interrupts to reduce the number of shared interrupt
1405 * handlers on the same IRQ line
1406 */
1407 err = fsldma_request_irqs(fdev);
1408 if (err) {
1409 dev_err(fdev->dev, "unable to request IRQs\n");
1410 goto out_free_fdev;
1411 }
1412
Zhang Wei173acc72008-03-01 07:42:48 -07001413 dma_async_device_register(&fdev->common);
1414 return 0;
1415
Ira Snydere7a29152010-01-06 13:34:03 +00001416out_free_fdev:
Ira Snyderd3f620b2010-01-06 13:34:04 +00001417 irq_dispose_mapping(fdev->irq);
Zhang Wei173acc72008-03-01 07:42:48 -07001418 kfree(fdev);
Ira Snydere7a29152010-01-06 13:34:03 +00001419out_return:
Zhang Wei173acc72008-03-01 07:42:48 -07001420 return err;
1421}
1422
Grant Likely2dc11582010-08-06 09:25:50 -06001423static int fsldma_of_remove(struct platform_device *op)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001424{
Ira Snydera4f56d42010-01-06 13:34:01 +00001425 struct fsldma_device *fdev;
Timur Tabi77cd62e2008-09-26 17:00:11 -07001426 unsigned int i;
1427
Ira Snydere7a29152010-01-06 13:34:03 +00001428 fdev = dev_get_drvdata(&op->dev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001429 dma_async_device_unregister(&fdev->common);
1430
Ira Snyderd3f620b2010-01-06 13:34:04 +00001431 fsldma_free_irqs(fdev);
1432
Ira Snydere7a29152010-01-06 13:34:03 +00001433 for (i = 0; i < FSL_DMA_MAX_CHANS_PER_DEVICE; i++) {
Timur Tabi77cd62e2008-09-26 17:00:11 -07001434 if (fdev->chan[i])
1435 fsl_dma_chan_remove(fdev->chan[i]);
Ira Snydere7a29152010-01-06 13:34:03 +00001436 }
Timur Tabi77cd62e2008-09-26 17:00:11 -07001437
Ira Snydere7a29152010-01-06 13:34:03 +00001438 iounmap(fdev->regs);
1439 dev_set_drvdata(&op->dev, NULL);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001440 kfree(fdev);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001441
1442 return 0;
1443}
1444
Márton Németh4b1cf1f2010-02-02 23:41:06 -07001445static const struct of_device_id fsldma_of_ids[] = {
Kumar Gala049c9d42008-03-31 11:13:21 -05001446 { .compatible = "fsl,eloplus-dma", },
1447 { .compatible = "fsl,elo-dma", },
Zhang Wei173acc72008-03-01 07:42:48 -07001448 {}
1449};
1450
Ira W. Snyder8faa7cf2011-04-07 10:33:03 -07001451static struct platform_driver fsldma_of_driver = {
Grant Likely40182942010-04-13 16:13:02 -07001452 .driver = {
1453 .name = "fsl-elo-dma",
1454 .owner = THIS_MODULE,
1455 .of_match_table = fsldma_of_ids,
1456 },
1457 .probe = fsldma_of_probe,
1458 .remove = fsldma_of_remove,
Zhang Wei173acc72008-03-01 07:42:48 -07001459};
1460
Ira Snydera4f56d42010-01-06 13:34:01 +00001461/*----------------------------------------------------------------------------*/
1462/* Module Init / Exit */
1463/*----------------------------------------------------------------------------*/
1464
1465static __init int fsldma_init(void)
Zhang Wei173acc72008-03-01 07:42:48 -07001466{
Timur Tabi77cd62e2008-09-26 17:00:11 -07001467 pr_info("Freescale Elo / Elo Plus DMA driver\n");
Grant Likely00006122011-02-22 19:59:54 -07001468 return platform_driver_register(&fsldma_of_driver);
Zhang Wei173acc72008-03-01 07:42:48 -07001469}
1470
Ira Snydera4f56d42010-01-06 13:34:01 +00001471static void __exit fsldma_exit(void)
Timur Tabi77cd62e2008-09-26 17:00:11 -07001472{
Grant Likely00006122011-02-22 19:59:54 -07001473 platform_driver_unregister(&fsldma_of_driver);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001474}
1475
Ira Snydera4f56d42010-01-06 13:34:01 +00001476subsys_initcall(fsldma_init);
1477module_exit(fsldma_exit);
Timur Tabi77cd62e2008-09-26 17:00:11 -07001478
1479MODULE_DESCRIPTION("Freescale Elo / Elo Plus DMA driver");
1480MODULE_LICENSE("GPL");