Vinu Deokaran | dc3ce96 | 2014-12-01 14:56:28 -0800 | [diff] [blame^] | 1 | /* Copyright (c) 2013-2015, The Linux Foundation. All rights reserved. |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 2 | * |
| 3 | * This program is free software; you can redistribute it and/or modify |
| 4 | * it under the terms of the GNU General Public License version 2 and |
| 5 | * only version 2 as published by the Free Software Foundation. |
| 6 | * |
| 7 | * This program is distributed in the hope that it will be useful, |
| 8 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 9 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 10 | * GNU General Public License for more details. |
| 11 | */ |
| 12 | |
| 13 | #ifndef __MDSS_PLL_H |
| 14 | #define __MDSS_PLL_H |
| 15 | |
| 16 | #include <linux/mdss_io_util.h> |
| 17 | #include <linux/io.h> |
| 18 | |
| 19 | #define MDSS_PLL_REG_W(base, offset, data) \ |
| 20 | writel_relaxed((data), (base) + (offset)) |
Jeevan Shriram | 3287bab | 2014-08-19 09:07:48 -0700 | [diff] [blame] | 21 | #define MDSS_PLL_REG_R(base, offset) readl_relaxed((base) + (offset)) |
| 22 | |
| 23 | #define PLL_CALC_DATA(addr0, addr1, data0, data1) \ |
| 24 | (((data1) << 24) | (((addr1)/4) << 16) | ((data0) << 8) | ((addr0)/4)) |
| 25 | |
| 26 | #define MDSS_DYN_PLL_REG_W(base, offset, addr0, addr1, data0, data1) \ |
| 27 | writel_relaxed(PLL_CALC_DATA(addr0, addr1, data0, data1), \ |
| 28 | (base) + (offset)) |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 29 | |
| 30 | enum { |
Padmanabhan Komanduru | a7b90d1 | 2014-03-27 20:03:11 +0530 | [diff] [blame] | 31 | MDSS_DSI_PLL_LPM, |
| 32 | MDSS_DSI_PLL_HPM, |
Chandan Uddaraju | c2dae7e | 2014-05-19 12:23:43 -0700 | [diff] [blame] | 33 | MDSS_DSI_PLL_20NM, |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 34 | MDSS_EDP_PLL, |
| 35 | MDSS_HDMI_PLL, |
Casey Piper | 27b5830 | 2014-06-12 21:30:41 -0700 | [diff] [blame] | 36 | MDSS_HDMI_PLL_20NM, |
Vinu Deokaran | dc3ce96 | 2014-12-01 14:56:28 -0800 | [diff] [blame^] | 37 | MDSS_HDMI_PLL_14NM, |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 38 | MDSS_UNKNOWN_PLL, |
| 39 | }; |
| 40 | |
Padmanabhan Komanduru | a7b90d1 | 2014-03-27 20:03:11 +0530 | [diff] [blame] | 41 | enum { |
| 42 | MDSS_PLL_TARGET_8974, |
Chandan Uddaraju | c2dae7e | 2014-05-19 12:23:43 -0700 | [diff] [blame] | 43 | MDSS_PLL_TARGET_8994, |
Jeykumar Sankaran | cb2cd1f | 2014-11-22 10:26:00 -0800 | [diff] [blame] | 44 | MDSS_PLL_TARGET_8992, |
Padmanabhan Komanduru | a7b90d1 | 2014-03-27 20:03:11 +0530 | [diff] [blame] | 45 | MDSS_PLL_TARGET_8916, |
Padmanabhan Komanduru | 5a8e1ec | 2014-05-21 12:41:32 +0530 | [diff] [blame] | 46 | MDSS_PLL_TARGET_8939, |
Shivaraj Shetty | aaeeb49 | 2014-09-26 12:08:01 +0530 | [diff] [blame] | 47 | MDSS_PLL_TARGET_8909, |
Padmanabhan Komanduru | a7b90d1 | 2014-03-27 20:03:11 +0530 | [diff] [blame] | 48 | }; |
| 49 | |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 50 | struct mdss_pll_resources { |
| 51 | |
| 52 | /* Pll specific resources like GPIO, power supply, clocks, etc*/ |
| 53 | struct dss_module_power mp; |
| 54 | |
Jeevan Shriram | 6dd6b97 | 2014-08-19 22:43:46 -0700 | [diff] [blame] | 55 | /* |
Veera Sundaram Sankaran | 23775f1 | 2014-11-13 14:28:25 -0800 | [diff] [blame] | 56 | * dsi/edp/hmdi plls' base register, phy, gdsc and dynamic refresh |
Jeevan Shriram | 6dd6b97 | 2014-08-19 22:43:46 -0700 | [diff] [blame] | 57 | * register mapping |
| 58 | */ |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 59 | void __iomem *pll_base; |
Siddhartha Agrawal | a91de84 | 2014-08-25 10:41:10 -0700 | [diff] [blame] | 60 | void __iomem *pll_1_base; |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 61 | void __iomem *phy_base; |
Veera Sundaram Sankaran | 23775f1 | 2014-11-13 14:28:25 -0800 | [diff] [blame] | 62 | void __iomem *gdsc_base; |
Jeevan Shriram | 6dd6b97 | 2014-08-19 22:43:46 -0700 | [diff] [blame] | 63 | void __iomem *dyn_pll_base; |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 64 | |
Huaibin Yang | c5c6ad4 | 2014-11-26 15:18:39 -0800 | [diff] [blame] | 65 | s64 vco_current_rate; |
| 66 | s64 vco_ref_clk_rate; |
| 67 | |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 68 | /* |
| 69 | * Certain pll's needs to update the same vco rate after resume in |
| 70 | * suspend/resume scenario. Cached the vco rate for such plls. |
| 71 | */ |
| 72 | unsigned long vco_cached_rate; |
| 73 | |
| 74 | /* dsi/edp/hmdi pll interface type */ |
| 75 | u32 pll_interface_type; |
| 76 | |
| 77 | /* |
Padmanabhan Komanduru | a7b90d1 | 2014-03-27 20:03:11 +0530 | [diff] [blame] | 78 | * Target ID. Used in pll_register API for valid target check before |
| 79 | * registering the PLL clocks. |
| 80 | */ |
| 81 | u32 target_id; |
| 82 | |
| 83 | /* HW recommended delay during configuration of vco clock rate */ |
| 84 | u32 vco_delay; |
| 85 | |
Padmanabhan Komanduru | 99fa0d7 | 2014-05-05 19:48:23 +0530 | [diff] [blame] | 86 | /* Ref-count of the PLL resources */ |
| 87 | u32 resource_ref_cnt; |
| 88 | |
Padmanabhan Komanduru | a7b90d1 | 2014-03-27 20:03:11 +0530 | [diff] [blame] | 89 | /* |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 90 | * Keep track to resource status to avoid updating same status for the |
| 91 | * pll from different paths |
| 92 | */ |
| 93 | bool resource_enable; |
| 94 | |
| 95 | /* |
| 96 | * Certain plls' do not allow vco rate update if it is on. Keep track of |
| 97 | * status for them to turn on/off after set rate success. |
| 98 | */ |
| 99 | bool pll_on; |
| 100 | |
| 101 | /* |
| 102 | * handoff_status is true of pll is already enabled by bootloader with |
| 103 | * continuous splash enable case. Clock API will call the handoff API |
| 104 | * to enable the status. It is disabled if continuous splash |
| 105 | * feature is disabled. |
| 106 | */ |
| 107 | bool handoff_resources; |
Jeevan Shriram | 3287bab | 2014-08-19 09:07:48 -0700 | [diff] [blame] | 108 | |
| 109 | /* |
| 110 | * caching the pll trim codes in the case of dynamic refresh |
| 111 | */ |
Huaibin Yang | c5c6ad4 | 2014-11-26 15:18:39 -0800 | [diff] [blame] | 112 | int cache_pll_trim_codes[2]; |
Jeevan Shriram | 3287bab | 2014-08-19 09:07:48 -0700 | [diff] [blame] | 113 | |
| 114 | /* |
| 115 | * for maintaining the status of saving trim codes |
| 116 | */ |
| 117 | bool reg_upd; |
Siddhartha Agrawal | a91de84 | 2014-08-25 10:41:10 -0700 | [diff] [blame] | 118 | |
| 119 | /* |
| 120 | * Notifier callback for MDSS gdsc regulator events |
| 121 | */ |
| 122 | struct notifier_block gdsc_cb; |
| 123 | |
| 124 | /* |
| 125 | * Worker function to call PLL off event |
| 126 | */ |
| 127 | struct work_struct pll_off; |
| 128 | |
Siddhartha Agrawal | 174bbb3 | 2014-09-05 10:44:54 -0700 | [diff] [blame] | 129 | /* |
| 130 | * PLL index if multiple index are available. Eg. in case of |
| 131 | * DSI we have 2 plls. |
| 132 | */ |
| 133 | uint32_t index; |
| 134 | |
Jeevan Shriram | 3287bab | 2014-08-19 09:07:48 -0700 | [diff] [blame] | 135 | }; |
| 136 | |
| 137 | struct mdss_pll_vco_calc { |
| 138 | s32 div_frac_start1; |
| 139 | s32 div_frac_start2; |
| 140 | s32 div_frac_start3; |
| 141 | s64 dec_start1; |
| 142 | s64 dec_start2; |
| 143 | s64 pll_plllock_cmp1; |
| 144 | s64 pll_plllock_cmp2; |
| 145 | s64 pll_plllock_cmp3; |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 146 | }; |
| 147 | |
Veera Sundaram Sankaran | 23775f1 | 2014-11-13 14:28:25 -0800 | [diff] [blame] | 148 | static inline bool is_gdsc_disabled(struct mdss_pll_resources *pll_res) |
| 149 | { |
| 150 | if (!pll_res->gdsc_base) { |
| 151 | WARN(1, "gdsc_base register is not defined\n"); |
| 152 | return true; |
| 153 | } |
| 154 | |
| 155 | return ((readl_relaxed(pll_res->gdsc_base + 0x4) & BIT(31)) && |
| 156 | (!(readl_relaxed(pll_res->gdsc_base) & BIT(0)))) ? false : true; |
| 157 | } |
| 158 | |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 159 | int mdss_pll_resource_enable(struct mdss_pll_resources *pll_res, bool enable); |
| 160 | int mdss_pll_util_resource_init(struct platform_device *pdev, |
| 161 | struct mdss_pll_resources *pll_res); |
| 162 | void mdss_pll_util_resource_deinit(struct platform_device *pdev, |
| 163 | struct mdss_pll_resources *pll_res); |
| 164 | void mdss_pll_util_resource_release(struct platform_device *pdev, |
| 165 | struct mdss_pll_resources *pll_res); |
| 166 | int mdss_pll_util_resource_enable(struct mdss_pll_resources *pll_res, |
| 167 | bool enable); |
| 168 | int mdss_pll_util_resource_parse(struct platform_device *pdev, |
| 169 | struct mdss_pll_resources *pll_res); |
Siddhartha Agrawal | a91de84 | 2014-08-25 10:41:10 -0700 | [diff] [blame] | 170 | struct dss_vreg *mdss_pll_get_mp_by_reg_name(struct mdss_pll_resources *pll_res |
| 171 | , char *name); |
Dhaval Patel | 83e27fc | 2013-12-19 14:52:24 -0800 | [diff] [blame] | 172 | #endif |