Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Intel Low Power Subsystem PWM controller driver |
| 3 | * |
| 4 | * Copyright (C) 2014, Intel Corporation |
| 5 | * Author: Mika Westerberg <mika.westerberg@linux.intel.com> |
| 6 | * Author: Chew Kean Ho <kean.ho.chew@intel.com> |
| 7 | * Author: Chang Rebecca Swee Fun <rebecca.swee.fun.chang@intel.com> |
| 8 | * Author: Chew Chiau Ee <chiau.ee.chew@intel.com> |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 9 | * Author: Alan Cox <alan@linux.intel.com> |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 10 | * |
| 11 | * This program is free software; you can redistribute it and/or modify |
| 12 | * it under the terms of the GNU General Public License version 2 as |
| 13 | * published by the Free Software Foundation. |
| 14 | */ |
| 15 | |
Mika Westerberg | 3767067 | 2015-11-18 13:25:18 +0200 | [diff] [blame] | 16 | #include <linux/delay.h> |
Thierry Reding | e0c86a3 | 2014-08-23 00:22:45 +0200 | [diff] [blame] | 17 | #include <linux/io.h> |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 18 | #include <linux/kernel.h> |
| 19 | #include <linux/module.h> |
Qipeng Zha | f080be2 | 2015-10-26 12:58:27 +0200 | [diff] [blame] | 20 | #include <linux/pm_runtime.h> |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame] | 21 | #include <linux/time.h> |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 22 | |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 23 | #include "pwm-lpss.h" |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 24 | |
| 25 | #define PWM 0x00000000 |
| 26 | #define PWM_ENABLE BIT(31) |
| 27 | #define PWM_SW_UPDATE BIT(30) |
| 28 | #define PWM_BASE_UNIT_SHIFT 8 |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 29 | #define PWM_ON_TIME_DIV_MASK 0x000000ff |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 30 | |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 31 | /* Size of each PWM register space if multiple */ |
| 32 | #define PWM_SIZE 0x400 |
| 33 | |
Hans de Goede | 037aca0e | 2018-04-26 14:10:23 +0200 | [diff] [blame] | 34 | #define MAX_PWMS 4 |
| 35 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 36 | struct pwm_lpss_chip { |
| 37 | struct pwm_chip chip; |
| 38 | void __iomem *regs; |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame] | 39 | const struct pwm_lpss_boardinfo *info; |
Hans de Goede | 037aca0e | 2018-04-26 14:10:23 +0200 | [diff] [blame] | 40 | u32 saved_ctrl[MAX_PWMS]; |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 41 | }; |
| 42 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 43 | /* BayTrail */ |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 44 | const struct pwm_lpss_boardinfo pwm_lpss_byt_info = { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 45 | .clk_rate = 25000000, |
| 46 | .npwm = 1, |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame] | 47 | .base_unit_bits = 16, |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 48 | }; |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 49 | EXPORT_SYMBOL_GPL(pwm_lpss_byt_info); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 50 | |
Alan Cox | 373c578 | 2014-08-19 17:18:29 +0300 | [diff] [blame] | 51 | /* Braswell */ |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 52 | const struct pwm_lpss_boardinfo pwm_lpss_bsw_info = { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 53 | .clk_rate = 19200000, |
| 54 | .npwm = 1, |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame] | 55 | .base_unit_bits = 16, |
Alan Cox | 373c578 | 2014-08-19 17:18:29 +0300 | [diff] [blame] | 56 | }; |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 57 | EXPORT_SYMBOL_GPL(pwm_lpss_bsw_info); |
Alan Cox | 373c578 | 2014-08-19 17:18:29 +0300 | [diff] [blame] | 58 | |
Mika Westerberg | 87219cb | 2015-10-20 16:53:06 +0300 | [diff] [blame] | 59 | /* Broxton */ |
| 60 | const struct pwm_lpss_boardinfo pwm_lpss_bxt_info = { |
| 61 | .clk_rate = 19200000, |
| 62 | .npwm = 4, |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame] | 63 | .base_unit_bits = 22, |
Mika Westerberg | 87219cb | 2015-10-20 16:53:06 +0300 | [diff] [blame] | 64 | }; |
| 65 | EXPORT_SYMBOL_GPL(pwm_lpss_bxt_info); |
| 66 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 67 | static inline struct pwm_lpss_chip *to_lpwm(struct pwm_chip *chip) |
| 68 | { |
| 69 | return container_of(chip, struct pwm_lpss_chip, chip); |
| 70 | } |
| 71 | |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 72 | static inline u32 pwm_lpss_read(const struct pwm_device *pwm) |
| 73 | { |
| 74 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); |
| 75 | |
| 76 | return readl(lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); |
| 77 | } |
| 78 | |
| 79 | static inline void pwm_lpss_write(const struct pwm_device *pwm, u32 value) |
| 80 | { |
| 81 | struct pwm_lpss_chip *lpwm = to_lpwm(pwm->chip); |
| 82 | |
| 83 | writel(value, lpwm->regs + pwm->hwpwm * PWM_SIZE + PWM); |
| 84 | } |
| 85 | |
Mika Westerberg | 3767067 | 2015-11-18 13:25:18 +0200 | [diff] [blame] | 86 | static void pwm_lpss_update(struct pwm_device *pwm) |
| 87 | { |
| 88 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_SW_UPDATE); |
| 89 | /* Give it some time to propagate */ |
| 90 | usleep_range(10, 50); |
| 91 | } |
| 92 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 93 | static int pwm_lpss_config(struct pwm_chip *chip, struct pwm_device *pwm, |
| 94 | int duty_ns, int period_ns) |
| 95 | { |
| 96 | struct pwm_lpss_chip *lpwm = to_lpwm(chip); |
Mika Westerberg | ab248b6 | 2016-06-10 15:43:21 +0300 | [diff] [blame] | 97 | unsigned long long on_time_div; |
Andy Shevchenko | d9cd4a7 | 2016-07-04 18:36:27 +0300 | [diff] [blame] | 98 | unsigned long c = lpwm->info->clk_rate, base_unit_range; |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame] | 99 | unsigned long long base_unit, freq = NSEC_PER_SEC; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 100 | u32 ctrl; |
| 101 | |
| 102 | do_div(freq, period_ns); |
| 103 | |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame] | 104 | /* |
| 105 | * The equation is: |
Dan O'Donovan | e5ca424 | 2016-06-01 15:31:12 +0100 | [diff] [blame] | 106 | * base_unit = round(base_unit_range * freq / c) |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame] | 107 | */ |
| 108 | base_unit_range = BIT(lpwm->info->base_unit_bits); |
Dan O'Donovan | e5ca424 | 2016-06-01 15:31:12 +0100 | [diff] [blame] | 109 | freq *= base_unit_range; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 110 | |
Dan O'Donovan | e5ca424 | 2016-06-01 15:31:12 +0100 | [diff] [blame] | 111 | base_unit = DIV_ROUND_CLOSEST_ULL(freq, c); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 112 | |
| 113 | if (duty_ns <= 0) |
| 114 | duty_ns = 1; |
Mika Westerberg | ab248b6 | 2016-06-10 15:43:21 +0300 | [diff] [blame] | 115 | on_time_div = 255ULL * duty_ns; |
| 116 | do_div(on_time_div, period_ns); |
| 117 | on_time_div = 255ULL - on_time_div; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 118 | |
Qipeng Zha | f080be2 | 2015-10-26 12:58:27 +0200 | [diff] [blame] | 119 | pm_runtime_get_sync(chip->dev); |
| 120 | |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 121 | ctrl = pwm_lpss_read(pwm); |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame] | 122 | ctrl &= ~PWM_ON_TIME_DIV_MASK; |
| 123 | ctrl &= ~((base_unit_range - 1) << PWM_BASE_UNIT_SHIFT); |
| 124 | base_unit &= (base_unit_range - 1); |
| 125 | ctrl |= (u32) base_unit << PWM_BASE_UNIT_SHIFT; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 126 | ctrl |= on_time_div; |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 127 | pwm_lpss_write(pwm, ctrl); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 128 | |
Mika Westerberg | 3767067 | 2015-11-18 13:25:18 +0200 | [diff] [blame] | 129 | /* |
| 130 | * If the PWM is already enabled we need to notify the hardware |
| 131 | * about the change by setting PWM_SW_UPDATE. |
| 132 | */ |
| 133 | if (pwm_is_enabled(pwm)) |
| 134 | pwm_lpss_update(pwm); |
| 135 | |
Qipeng Zha | f080be2 | 2015-10-26 12:58:27 +0200 | [diff] [blame] | 136 | pm_runtime_put(chip->dev); |
| 137 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 138 | return 0; |
| 139 | } |
| 140 | |
| 141 | static int pwm_lpss_enable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 142 | { |
Qipeng Zha | f080be2 | 2015-10-26 12:58:27 +0200 | [diff] [blame] | 143 | pm_runtime_get_sync(chip->dev); |
Mika Westerberg | 3767067 | 2015-11-18 13:25:18 +0200 | [diff] [blame] | 144 | |
| 145 | /* |
| 146 | * Hardware must first see PWM_SW_UPDATE before the PWM can be |
| 147 | * enabled. |
| 148 | */ |
| 149 | pwm_lpss_update(pwm); |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 150 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) | PWM_ENABLE); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 151 | return 0; |
| 152 | } |
| 153 | |
| 154 | static void pwm_lpss_disable(struct pwm_chip *chip, struct pwm_device *pwm) |
| 155 | { |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 156 | pwm_lpss_write(pwm, pwm_lpss_read(pwm) & ~PWM_ENABLE); |
Qipeng Zha | f080be2 | 2015-10-26 12:58:27 +0200 | [diff] [blame] | 157 | pm_runtime_put(chip->dev); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 158 | } |
| 159 | |
| 160 | static const struct pwm_ops pwm_lpss_ops = { |
| 161 | .config = pwm_lpss_config, |
| 162 | .enable = pwm_lpss_enable, |
| 163 | .disable = pwm_lpss_disable, |
| 164 | .owner = THIS_MODULE, |
| 165 | }; |
| 166 | |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 167 | struct pwm_lpss_chip *pwm_lpss_probe(struct device *dev, struct resource *r, |
| 168 | const struct pwm_lpss_boardinfo *info) |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 169 | { |
| 170 | struct pwm_lpss_chip *lpwm; |
Andy Shevchenko | d9cd4a7 | 2016-07-04 18:36:27 +0300 | [diff] [blame] | 171 | unsigned long c; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 172 | int ret; |
| 173 | |
Hans de Goede | 037aca0e | 2018-04-26 14:10:23 +0200 | [diff] [blame] | 174 | if (WARN_ON(info->npwm > MAX_PWMS)) |
| 175 | return ERR_PTR(-ENODEV); |
| 176 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 177 | lpwm = devm_kzalloc(dev, sizeof(*lpwm), GFP_KERNEL); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 178 | if (!lpwm) |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 179 | return ERR_PTR(-ENOMEM); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 180 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 181 | lpwm->regs = devm_ioremap_resource(dev, r); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 182 | if (IS_ERR(lpwm->regs)) |
Thierry Reding | 89c0339 | 2014-05-07 10:27:57 +0200 | [diff] [blame] | 183 | return ERR_CAST(lpwm->regs); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 184 | |
qipeng.zha | 883e4d0 | 2015-11-17 17:20:15 +0800 | [diff] [blame] | 185 | lpwm->info = info; |
Andy Shevchenko | d9cd4a7 | 2016-07-04 18:36:27 +0300 | [diff] [blame] | 186 | |
| 187 | c = lpwm->info->clk_rate; |
| 188 | if (!c) |
| 189 | return ERR_PTR(-EINVAL); |
| 190 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 191 | lpwm->chip.dev = dev; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 192 | lpwm->chip.ops = &pwm_lpss_ops; |
| 193 | lpwm->chip.base = -1; |
Mika Westerberg | 4e11f5a | 2015-10-20 16:53:05 +0300 | [diff] [blame] | 194 | lpwm->chip.npwm = info->npwm; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 195 | |
| 196 | ret = pwmchip_add(&lpwm->chip); |
| 197 | if (ret) { |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 198 | dev_err(dev, "failed to add PWM chip: %d\n", ret); |
| 199 | return ERR_PTR(ret); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 200 | } |
| 201 | |
Alan Cox | 093e00b | 2014-04-18 19:17:40 +0800 | [diff] [blame] | 202 | return lpwm; |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 203 | } |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 204 | EXPORT_SYMBOL_GPL(pwm_lpss_probe); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 205 | |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 206 | int pwm_lpss_remove(struct pwm_lpss_chip *lpwm) |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 207 | { |
Hans de Goede | 7f6e0f4 | 2018-10-12 12:12:28 +0200 | [diff] [blame] | 208 | int i; |
| 209 | |
| 210 | for (i = 0; i < lpwm->info->npwm; i++) { |
| 211 | if (pwm_is_enabled(&lpwm->chip.pwms[i])) |
| 212 | pm_runtime_put(lpwm->chip.dev); |
| 213 | } |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 214 | return pwmchip_remove(&lpwm->chip); |
| 215 | } |
Andy Shevchenko | c558e39 | 2014-08-19 19:17:35 +0300 | [diff] [blame] | 216 | EXPORT_SYMBOL_GPL(pwm_lpss_remove); |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 217 | |
Hans de Goede | 037aca0e | 2018-04-26 14:10:23 +0200 | [diff] [blame] | 218 | int pwm_lpss_suspend(struct device *dev) |
| 219 | { |
| 220 | struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev); |
| 221 | int i; |
| 222 | |
| 223 | for (i = 0; i < lpwm->info->npwm; i++) |
| 224 | lpwm->saved_ctrl[i] = readl(lpwm->regs + i * PWM_SIZE + PWM); |
| 225 | |
| 226 | return 0; |
| 227 | } |
| 228 | EXPORT_SYMBOL_GPL(pwm_lpss_suspend); |
| 229 | |
| 230 | int pwm_lpss_resume(struct device *dev) |
| 231 | { |
| 232 | struct pwm_lpss_chip *lpwm = dev_get_drvdata(dev); |
| 233 | int i; |
| 234 | |
| 235 | for (i = 0; i < lpwm->info->npwm; i++) |
| 236 | writel(lpwm->saved_ctrl[i], lpwm->regs + i * PWM_SIZE + PWM); |
| 237 | |
| 238 | return 0; |
| 239 | } |
| 240 | EXPORT_SYMBOL_GPL(pwm_lpss_resume); |
| 241 | |
Mika Westerberg | d16a5aa | 2014-03-20 22:04:23 +0800 | [diff] [blame] | 242 | MODULE_DESCRIPTION("PWM driver for Intel LPSS"); |
| 243 | MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>"); |
| 244 | MODULE_LICENSE("GPL v2"); |