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Gabor Juhosd4a67d92011-01-04 21:28:14 +01001/*
2 * Atheros AR71XX/AR724X/AR913X common routines
3 *
Gabor Juhos88896122012-03-14 10:45:22 +01004 * Copyright (C) 2010-2011 Jaiganesh Narayanan <jnarayanan@atheros.com>
Gabor Juhosd4a67d92011-01-04 21:28:14 +01005 * Copyright (C) 2011 Gabor Juhos <juhosg@openwrt.org>
6 *
Gabor Juhos88896122012-03-14 10:45:22 +01007 * Parts of this file are based on Atheros' 2.6.15/2.6.31 BSP
8 *
Gabor Juhosd4a67d92011-01-04 21:28:14 +01009 * This program is free software; you can redistribute it and/or modify it
10 * under the terms of the GNU General Public License version 2 as published
11 * by the Free Software Foundation.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/init.h>
17#include <linux/err.h>
18#include <linux/clk.h>
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020019#include <linux/clkdev.h>
Alban Bedel411520a2015-04-19 14:30:04 +020020#include <linux/clk-provider.h>
Antony Pavlov3bdf1072016-03-17 06:34:15 +030021#include <linux/of.h>
22#include <linux/of_address.h>
Antony Pavlovaf5ad0d2016-03-17 06:34:14 +030023#include <dt-bindings/clock/ath79-clk.h>
Gabor Juhosd4a67d92011-01-04 21:28:14 +010024
Gabor Juhos97541cc2012-09-08 14:02:21 +020025#include <asm/div64.h>
26
Gabor Juhosd4a67d92011-01-04 21:28:14 +010027#include <asm/mach-ath79/ath79.h>
28#include <asm/mach-ath79/ar71xx_regs.h>
29#include "common.h"
Antony Pavlov3bdf1072016-03-17 06:34:15 +030030#include "machtypes.h"
Gabor Juhosd4a67d92011-01-04 21:28:14 +010031
32#define AR71XX_BASE_FREQ 40000000
Weijie Gaoc338d592016-03-17 06:34:09 +030033#define AR724X_BASE_FREQ 40000000
Gabor Juhosd4a67d92011-01-04 21:28:14 +010034
Antony Pavlovaf5ad0d2016-03-17 06:34:14 +030035static struct clk *clks[ATH79_CLK_END];
Alban Bedel6451af02015-05-31 02:18:22 +020036static struct clk_onecell_data clk_data = {
37 .clks = clks,
38 .clk_num = ARRAY_SIZE(clks),
39};
40
41static struct clk *__init ath79_add_sys_clkdev(
42 const char *id, unsigned long rate)
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020043{
44 struct clk *clk;
45 int err;
46
Stephen Boyd9c938a02016-04-19 18:33:21 -070047 clk = clk_register_fixed_rate(NULL, id, NULL, 0, rate);
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020048 if (!clk)
49 panic("failed to allocate %s clock structure", id);
50
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020051 err = clk_register_clkdev(clk, id, NULL);
52 if (err)
53 panic("unable to register %s clock device", id);
Alban Bedel6451af02015-05-31 02:18:22 +020054
55 return clk;
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020056}
Gabor Juhosd4a67d92011-01-04 21:28:14 +010057
58static void __init ar71xx_clocks_init(void)
59{
Gabor Juhos6612a682013-08-28 10:41:46 +020060 unsigned long ref_rate;
61 unsigned long cpu_rate;
62 unsigned long ddr_rate;
63 unsigned long ahb_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010064 u32 pll;
65 u32 freq;
66 u32 div;
67
Gabor Juhos6612a682013-08-28 10:41:46 +020068 ref_rate = AR71XX_BASE_FREQ;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010069
70 pll = ath79_pll_rr(AR71XX_PLL_REG_CPU_CONFIG);
71
Alban Bedel626a0692015-04-19 14:30:02 +020072 div = ((pll >> AR71XX_PLL_FB_SHIFT) & AR71XX_PLL_FB_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +020073 freq = div * ref_rate;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010074
75 div = ((pll >> AR71XX_CPU_DIV_SHIFT) & AR71XX_CPU_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +020076 cpu_rate = freq / div;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010077
78 div = ((pll >> AR71XX_DDR_DIV_SHIFT) & AR71XX_DDR_DIV_MASK) + 1;
Gabor Juhos6612a682013-08-28 10:41:46 +020079 ddr_rate = freq / div;
Gabor Juhosd4a67d92011-01-04 21:28:14 +010080
81 div = (((pll >> AR71XX_AHB_DIV_SHIFT) & AR71XX_AHB_DIV_MASK) + 1) * 2;
Gabor Juhos6612a682013-08-28 10:41:46 +020082 ahb_rate = cpu_rate / div;
83
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020084 ath79_add_sys_clkdev("ref", ref_rate);
Antony Pavlovaf5ad0d2016-03-17 06:34:14 +030085 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
86 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
87 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhosd4a67d92011-01-04 21:28:14 +010088
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +020089 clk_add_alias("wdt", NULL, "ahb", NULL);
90 clk_add_alias("uart", NULL, "ahb", NULL);
Gabor Juhosd4a67d92011-01-04 21:28:14 +010091}
92
Antony Pavlov3bdf1072016-03-17 06:34:15 +030093static struct clk * __init ath79_reg_ffclk(const char *name,
94 const char *parent_name, unsigned int mult, unsigned int div)
95{
96 struct clk *clk;
97
98 clk = clk_register_fixed_factor(NULL, name, parent_name, 0, mult, div);
Amitoj Kaur Chawlae3b23142016-08-12 08:36:54 +053099 if (IS_ERR(clk))
Antony Pavlov3bdf1072016-03-17 06:34:15 +0300100 panic("failed to allocate %s clock structure", name);
101
102 return clk;
103}
104
105static void __init ar724x_clk_init(struct clk *ref_clk, void __iomem *pll_base)
106{
107 u32 pll;
108 u32 mult, div, ddr_div, ahb_div;
109
110 pll = __raw_readl(pll_base + AR724X_PLL_REG_CPU_CONFIG);
111
112 mult = ((pll >> AR724X_PLL_FB_SHIFT) & AR724X_PLL_FB_MASK);
113 div = ((pll >> AR724X_PLL_REF_DIV_SHIFT) & AR724X_PLL_REF_DIV_MASK) * 2;
114
115 ddr_div = ((pll >> AR724X_DDR_DIV_SHIFT) & AR724X_DDR_DIV_MASK) + 1;
116 ahb_div = (((pll >> AR724X_AHB_DIV_SHIFT) & AR724X_AHB_DIV_MASK) + 1) * 2;
117
118 clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref", mult, div);
119 clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref", mult, div * ddr_div);
120 clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref", mult, div * ahb_div);
121}
122
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100123static void __init ar724x_clocks_init(void)
124{
Antony Pavlov3bdf1072016-03-17 06:34:15 +0300125 struct clk *ref_clk;
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100126
Antony Pavlov3bdf1072016-03-17 06:34:15 +0300127 ref_clk = ath79_add_sys_clkdev("ref", AR724X_BASE_FREQ);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100128
Antony Pavlov3bdf1072016-03-17 06:34:15 +0300129 ar724x_clk_init(ref_clk, ath79_pll_base);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100130
Antony Pavlov3bdf1072016-03-17 06:34:15 +0300131 /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
132 clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
133 clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
134 clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100135
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200136 clk_add_alias("wdt", NULL, "ahb", NULL);
137 clk_add_alias("uart", NULL, "ahb", NULL);
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100138}
139
Antony Pavlov5ae5c452016-03-17 06:34:18 +0300140static void __init ar9330_clk_init(struct clk *ref_clk, void __iomem *pll_base)
141{
142 u32 clock_ctrl;
143 u32 ref_div;
144 u32 ninit_mul;
145 u32 out_div;
146
147 u32 cpu_div;
148 u32 ddr_div;
149 u32 ahb_div;
150
151 clock_ctrl = __raw_readl(pll_base + AR933X_PLL_CLOCK_CTRL_REG);
152 if (clock_ctrl & AR933X_PLL_CLOCK_CTRL_BYPASS) {
153 ref_div = 1;
154 ninit_mul = 1;
155 out_div = 1;
156
157 cpu_div = 1;
158 ddr_div = 1;
159 ahb_div = 1;
160 } else {
161 u32 cpu_config;
162 u32 t;
163
164 cpu_config = __raw_readl(pll_base + AR933X_PLL_CPU_CONFIG_REG);
165
166 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
167 AR933X_PLL_CPU_CONFIG_REFDIV_MASK;
168 ref_div = t;
169
170 ninit_mul = (cpu_config >> AR933X_PLL_CPU_CONFIG_NINT_SHIFT) &
171 AR933X_PLL_CPU_CONFIG_NINT_MASK;
172
173 t = (cpu_config >> AR933X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
174 AR933X_PLL_CPU_CONFIG_OUTDIV_MASK;
175 if (t == 0)
176 t = 1;
177
178 out_div = (1 << t);
179
180 cpu_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_CPU_DIV_SHIFT) &
181 AR933X_PLL_CLOCK_CTRL_CPU_DIV_MASK) + 1;
182
183 ddr_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_DDR_DIV_SHIFT) &
184 AR933X_PLL_CLOCK_CTRL_DDR_DIV_MASK) + 1;
185
186 ahb_div = ((clock_ctrl >> AR933X_PLL_CLOCK_CTRL_AHB_DIV_SHIFT) &
187 AR933X_PLL_CLOCK_CTRL_AHB_DIV_MASK) + 1;
188 }
189
190 clks[ATH79_CLK_CPU] = ath79_reg_ffclk("cpu", "ref",
191 ninit_mul, ref_div * out_div * cpu_div);
192 clks[ATH79_CLK_DDR] = ath79_reg_ffclk("ddr", "ref",
193 ninit_mul, ref_div * out_div * ddr_div);
194 clks[ATH79_CLK_AHB] = ath79_reg_ffclk("ahb", "ref",
195 ninit_mul, ref_div * out_div * ahb_div);
196}
197
Gabor Juhos04225e12011-06-20 21:26:04 +0200198static void __init ar933x_clocks_init(void)
199{
Antony Pavlov5ae5c452016-03-17 06:34:18 +0300200 struct clk *ref_clk;
Gabor Juhos6612a682013-08-28 10:41:46 +0200201 unsigned long ref_rate;
Gabor Juhos04225e12011-06-20 21:26:04 +0200202 u32 t;
203
204 t = ath79_reset_rr(AR933X_RESET_REG_BOOTSTRAP);
205 if (t & AR933X_BOOTSTRAP_REF_CLK_40)
Gabor Juhos6612a682013-08-28 10:41:46 +0200206 ref_rate = (40 * 1000 * 1000);
Gabor Juhos04225e12011-06-20 21:26:04 +0200207 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200208 ref_rate = (25 * 1000 * 1000);
Gabor Juhos04225e12011-06-20 21:26:04 +0200209
Antony Pavlov5ae5c452016-03-17 06:34:18 +0300210 ref_clk = ath79_add_sys_clkdev("ref", ref_rate);
Gabor Juhos04225e12011-06-20 21:26:04 +0200211
Antony Pavlov5ae5c452016-03-17 06:34:18 +0300212 ar9330_clk_init(ref_clk, ath79_pll_base);
Gabor Juhos04225e12011-06-20 21:26:04 +0200213
Antony Pavlov5ae5c452016-03-17 06:34:18 +0300214 /* just make happy plat_time_init() from arch/mips/ath79/setup.c */
215 clk_register_clkdev(clks[ATH79_CLK_CPU], "cpu", NULL);
216 clk_register_clkdev(clks[ATH79_CLK_DDR], "ddr", NULL);
217 clk_register_clkdev(clks[ATH79_CLK_AHB], "ahb", NULL);
Gabor Juhos6612a682013-08-28 10:41:46 +0200218
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200219 clk_add_alias("wdt", NULL, "ahb", NULL);
220 clk_add_alias("uart", NULL, "ref", NULL);
Gabor Juhos04225e12011-06-20 21:26:04 +0200221}
222
Gabor Juhos97541cc2012-09-08 14:02:21 +0200223static u32 __init ar934x_get_pll_freq(u32 ref, u32 ref_div, u32 nint, u32 nfrac,
224 u32 frac, u32 out_div)
225{
226 u64 t;
227 u32 ret;
228
Gabor Juhos837f0362013-08-28 10:41:43 +0200229 t = ref;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200230 t *= nint;
231 do_div(t, ref_div);
232 ret = t;
233
Gabor Juhos837f0362013-08-28 10:41:43 +0200234 t = ref;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200235 t *= nfrac;
236 do_div(t, ref_div * frac);
237 ret += t;
238
239 ret /= (1 << out_div);
240 return ret;
241}
242
Gabor Juhos88896122012-03-14 10:45:22 +0100243static void __init ar934x_clocks_init(void)
244{
Gabor Juhos6612a682013-08-28 10:41:46 +0200245 unsigned long ref_rate;
246 unsigned long cpu_rate;
247 unsigned long ddr_rate;
248 unsigned long ahb_rate;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200249 u32 pll, out_div, ref_div, nint, nfrac, frac, clk_ctrl, postdiv;
Gabor Juhos88896122012-03-14 10:45:22 +0100250 u32 cpu_pll, ddr_pll;
251 u32 bootstrap;
Gabor Juhos97541cc2012-09-08 14:02:21 +0200252 void __iomem *dpll_base;
253
254 dpll_base = ioremap(AR934X_SRIF_BASE, AR934X_SRIF_SIZE);
Gabor Juhos88896122012-03-14 10:45:22 +0100255
256 bootstrap = ath79_reset_rr(AR934X_RESET_REG_BOOTSTRAP);
Ralf Baechle70342282013-01-22 12:59:30 +0100257 if (bootstrap & AR934X_BOOTSTRAP_REF_CLK_40)
Gabor Juhos6612a682013-08-28 10:41:46 +0200258 ref_rate = 40 * 1000 * 1000;
Gabor Juhos88896122012-03-14 10:45:22 +0100259 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200260 ref_rate = 25 * 1000 * 1000;
Gabor Juhos88896122012-03-14 10:45:22 +0100261
Gabor Juhos97541cc2012-09-08 14:02:21 +0200262 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL2_REG);
263 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
264 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
265 AR934X_SRIF_DPLL2_OUTDIV_MASK;
266 pll = __raw_readl(dpll_base + AR934X_SRIF_CPU_DPLL1_REG);
267 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
268 AR934X_SRIF_DPLL1_NINT_MASK;
269 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
270 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
271 AR934X_SRIF_DPLL1_REFDIV_MASK;
272 frac = 1 << 18;
273 } else {
274 pll = ath79_pll_rr(AR934X_PLL_CPU_CONFIG_REG);
275 out_div = (pll >> AR934X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
276 AR934X_PLL_CPU_CONFIG_OUTDIV_MASK;
277 ref_div = (pll >> AR934X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
278 AR934X_PLL_CPU_CONFIG_REFDIV_MASK;
279 nint = (pll >> AR934X_PLL_CPU_CONFIG_NINT_SHIFT) &
280 AR934X_PLL_CPU_CONFIG_NINT_MASK;
281 nfrac = (pll >> AR934X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
282 AR934X_PLL_CPU_CONFIG_NFRAC_MASK;
283 frac = 1 << 6;
284 }
Gabor Juhos88896122012-03-14 10:45:22 +0100285
Gabor Juhos6612a682013-08-28 10:41:46 +0200286 cpu_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
Gabor Juhos97541cc2012-09-08 14:02:21 +0200287 nfrac, frac, out_div);
Gabor Juhos88896122012-03-14 10:45:22 +0100288
Gabor Juhos97541cc2012-09-08 14:02:21 +0200289 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL2_REG);
290 if (pll & AR934X_SRIF_DPLL2_LOCAL_PLL) {
291 out_div = (pll >> AR934X_SRIF_DPLL2_OUTDIV_SHIFT) &
292 AR934X_SRIF_DPLL2_OUTDIV_MASK;
293 pll = __raw_readl(dpll_base + AR934X_SRIF_DDR_DPLL1_REG);
294 nint = (pll >> AR934X_SRIF_DPLL1_NINT_SHIFT) &
295 AR934X_SRIF_DPLL1_NINT_MASK;
296 nfrac = pll & AR934X_SRIF_DPLL1_NFRAC_MASK;
297 ref_div = (pll >> AR934X_SRIF_DPLL1_REFDIV_SHIFT) &
298 AR934X_SRIF_DPLL1_REFDIV_MASK;
299 frac = 1 << 18;
300 } else {
301 pll = ath79_pll_rr(AR934X_PLL_DDR_CONFIG_REG);
302 out_div = (pll >> AR934X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
303 AR934X_PLL_DDR_CONFIG_OUTDIV_MASK;
304 ref_div = (pll >> AR934X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
305 AR934X_PLL_DDR_CONFIG_REFDIV_MASK;
306 nint = (pll >> AR934X_PLL_DDR_CONFIG_NINT_SHIFT) &
307 AR934X_PLL_DDR_CONFIG_NINT_MASK;
308 nfrac = (pll >> AR934X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
309 AR934X_PLL_DDR_CONFIG_NFRAC_MASK;
310 frac = 1 << 10;
311 }
Gabor Juhos88896122012-03-14 10:45:22 +0100312
Gabor Juhos6612a682013-08-28 10:41:46 +0200313 ddr_pll = ar934x_get_pll_freq(ref_rate, ref_div, nint,
Gabor Juhos97541cc2012-09-08 14:02:21 +0200314 nfrac, frac, out_div);
Gabor Juhos88896122012-03-14 10:45:22 +0100315
316 clk_ctrl = ath79_pll_rr(AR934X_PLL_CPU_DDR_CLK_CTRL_REG);
317
318 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_SHIFT) &
319 AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_POST_DIV_MASK;
320
321 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPU_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200322 cpu_rate = ref_rate;
Gabor Juhos88896122012-03-14 10:45:22 +0100323 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_CPUCLK_FROM_CPUPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200324 cpu_rate = cpu_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100325 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200326 cpu_rate = ddr_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100327
328 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_SHIFT) &
329 AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_POST_DIV_MASK;
330
331 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDR_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200332 ddr_rate = ref_rate;
Gabor Juhos88896122012-03-14 10:45:22 +0100333 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_DDRCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200334 ddr_rate = ddr_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100335 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200336 ddr_rate = cpu_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100337
338 postdiv = (clk_ctrl >> AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_SHIFT) &
339 AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_POST_DIV_MASK;
340
341 if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHB_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200342 ahb_rate = ref_rate;
Gabor Juhos88896122012-03-14 10:45:22 +0100343 else if (clk_ctrl & AR934X_PLL_CPU_DDR_CLK_CTRL_AHBCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200344 ahb_rate = ddr_pll / (postdiv + 1);
Gabor Juhos88896122012-03-14 10:45:22 +0100345 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200346 ahb_rate = cpu_pll / (postdiv + 1);
347
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200348 ath79_add_sys_clkdev("ref", ref_rate);
Antony Pavlovaf5ad0d2016-03-17 06:34:14 +0300349 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
350 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
351 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhos88896122012-03-14 10:45:22 +0100352
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200353 clk_add_alias("wdt", NULL, "ref", NULL);
354 clk_add_alias("uart", NULL, "ref", NULL);
Gabor Juhos97541cc2012-09-08 14:02:21 +0200355
356 iounmap(dpll_base);
Gabor Juhos88896122012-03-14 10:45:22 +0100357}
358
Gabor Juhos41583c02013-02-15 13:38:17 +0000359static void __init qca955x_clocks_init(void)
360{
Gabor Juhos6612a682013-08-28 10:41:46 +0200361 unsigned long ref_rate;
362 unsigned long cpu_rate;
363 unsigned long ddr_rate;
364 unsigned long ahb_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000365 u32 pll, out_div, ref_div, nint, frac, clk_ctrl, postdiv;
366 u32 cpu_pll, ddr_pll;
367 u32 bootstrap;
368
369 bootstrap = ath79_reset_rr(QCA955X_RESET_REG_BOOTSTRAP);
370 if (bootstrap & QCA955X_BOOTSTRAP_REF_CLK_40)
Gabor Juhos6612a682013-08-28 10:41:46 +0200371 ref_rate = 40 * 1000 * 1000;
Gabor Juhos41583c02013-02-15 13:38:17 +0000372 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200373 ref_rate = 25 * 1000 * 1000;
Gabor Juhos41583c02013-02-15 13:38:17 +0000374
375 pll = ath79_pll_rr(QCA955X_PLL_CPU_CONFIG_REG);
376 out_div = (pll >> QCA955X_PLL_CPU_CONFIG_OUTDIV_SHIFT) &
377 QCA955X_PLL_CPU_CONFIG_OUTDIV_MASK;
378 ref_div = (pll >> QCA955X_PLL_CPU_CONFIG_REFDIV_SHIFT) &
379 QCA955X_PLL_CPU_CONFIG_REFDIV_MASK;
380 nint = (pll >> QCA955X_PLL_CPU_CONFIG_NINT_SHIFT) &
381 QCA955X_PLL_CPU_CONFIG_NINT_MASK;
382 frac = (pll >> QCA955X_PLL_CPU_CONFIG_NFRAC_SHIFT) &
383 QCA955X_PLL_CPU_CONFIG_NFRAC_MASK;
384
Gabor Juhos6612a682013-08-28 10:41:46 +0200385 cpu_pll = nint * ref_rate / ref_div;
386 cpu_pll += frac * ref_rate / (ref_div * (1 << 6));
Gabor Juhos41583c02013-02-15 13:38:17 +0000387 cpu_pll /= (1 << out_div);
388
389 pll = ath79_pll_rr(QCA955X_PLL_DDR_CONFIG_REG);
390 out_div = (pll >> QCA955X_PLL_DDR_CONFIG_OUTDIV_SHIFT) &
391 QCA955X_PLL_DDR_CONFIG_OUTDIV_MASK;
392 ref_div = (pll >> QCA955X_PLL_DDR_CONFIG_REFDIV_SHIFT) &
393 QCA955X_PLL_DDR_CONFIG_REFDIV_MASK;
394 nint = (pll >> QCA955X_PLL_DDR_CONFIG_NINT_SHIFT) &
395 QCA955X_PLL_DDR_CONFIG_NINT_MASK;
396 frac = (pll >> QCA955X_PLL_DDR_CONFIG_NFRAC_SHIFT) &
397 QCA955X_PLL_DDR_CONFIG_NFRAC_MASK;
398
Gabor Juhos6612a682013-08-28 10:41:46 +0200399 ddr_pll = nint * ref_rate / ref_div;
400 ddr_pll += frac * ref_rate / (ref_div * (1 << 10));
Gabor Juhos41583c02013-02-15 13:38:17 +0000401 ddr_pll /= (1 << out_div);
402
403 clk_ctrl = ath79_pll_rr(QCA955X_PLL_CLK_CTRL_REG);
404
405 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_SHIFT) &
406 QCA955X_PLL_CLK_CTRL_CPU_POST_DIV_MASK;
407
408 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPU_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200409 cpu_rate = ref_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000410 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_CPUCLK_FROM_CPUPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200411 cpu_rate = ddr_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000412 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200413 cpu_rate = cpu_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000414
415 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_SHIFT) &
416 QCA955X_PLL_CLK_CTRL_DDR_POST_DIV_MASK;
417
418 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDR_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200419 ddr_rate = ref_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000420 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_DDRCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200421 ddr_rate = cpu_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000422 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200423 ddr_rate = ddr_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000424
425 postdiv = (clk_ctrl >> QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_SHIFT) &
426 QCA955X_PLL_CLK_CTRL_AHB_POST_DIV_MASK;
427
428 if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHB_PLL_BYPASS)
Gabor Juhos6612a682013-08-28 10:41:46 +0200429 ahb_rate = ref_rate;
Gabor Juhos41583c02013-02-15 13:38:17 +0000430 else if (clk_ctrl & QCA955X_PLL_CLK_CTRL_AHBCLK_FROM_DDRPLL)
Gabor Juhos6612a682013-08-28 10:41:46 +0200431 ahb_rate = ddr_pll / (postdiv + 1);
Gabor Juhos41583c02013-02-15 13:38:17 +0000432 else
Gabor Juhos6612a682013-08-28 10:41:46 +0200433 ahb_rate = cpu_pll / (postdiv + 1);
434
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200435 ath79_add_sys_clkdev("ref", ref_rate);
Antony Pavlovaf5ad0d2016-03-17 06:34:14 +0300436 clks[ATH79_CLK_CPU] = ath79_add_sys_clkdev("cpu", cpu_rate);
437 clks[ATH79_CLK_DDR] = ath79_add_sys_clkdev("ddr", ddr_rate);
438 clks[ATH79_CLK_AHB] = ath79_add_sys_clkdev("ahb", ahb_rate);
Gabor Juhos41583c02013-02-15 13:38:17 +0000439
Gabor Juhos2c4f1ac2013-08-28 10:41:47 +0200440 clk_add_alias("wdt", NULL, "ref", NULL);
441 clk_add_alias("uart", NULL, "ref", NULL);
Gabor Juhos41583c02013-02-15 13:38:17 +0000442}
443
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100444void __init ath79_clocks_init(void)
445{
446 if (soc_is_ar71xx())
447 ar71xx_clocks_init();
Alban Bedelf4c87b72016-03-17 06:34:10 +0300448 else if (soc_is_ar724x() || soc_is_ar913x())
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100449 ar724x_clocks_init();
Gabor Juhos04225e12011-06-20 21:26:04 +0200450 else if (soc_is_ar933x())
451 ar933x_clocks_init();
Gabor Juhos88896122012-03-14 10:45:22 +0100452 else if (soc_is_ar934x())
453 ar934x_clocks_init();
Gabor Juhos41583c02013-02-15 13:38:17 +0000454 else if (soc_is_qca955x())
455 qca955x_clocks_init();
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100456 else
457 BUG();
Gabor Juhosd4a67d92011-01-04 21:28:14 +0100458}
459
Gabor Juhos23107802013-08-28 10:41:44 +0200460unsigned long __init
461ath79_get_sys_clk_rate(const char *id)
462{
463 struct clk *clk;
464 unsigned long rate;
465
466 clk = clk_get(NULL, id);
467 if (IS_ERR(clk))
468 panic("unable to get %s clock, err=%d", id, (int) PTR_ERR(clk));
469
470 rate = clk_get_rate(clk);
471 clk_put(clk);
472
473 return rate;
474}
Alban Bedel6451af02015-05-31 02:18:22 +0200475
476#ifdef CONFIG_OF
477static void __init ath79_clocks_init_dt(struct device_node *np)
478{
479 of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data);
480}
481
482CLK_OF_DECLARE(ar7100, "qca,ar7100-pll", ath79_clocks_init_dt);
483CLK_OF_DECLARE(ar7240, "qca,ar7240-pll", ath79_clocks_init_dt);
Alban Bedel6451af02015-05-31 02:18:22 +0200484CLK_OF_DECLARE(ar9340, "qca,ar9340-pll", ath79_clocks_init_dt);
485CLK_OF_DECLARE(ar9550, "qca,qca9550-pll", ath79_clocks_init_dt);
Antony Pavlov3bdf1072016-03-17 06:34:15 +0300486
487static void __init ath79_clocks_init_dt_ng(struct device_node *np)
488{
489 struct clk *ref_clk;
490 void __iomem *pll_base;
491 const char *dnfn = of_node_full_name(np);
492
493 ref_clk = of_clk_get(np, 0);
494 if (IS_ERR(ref_clk)) {
495 pr_err("%s: of_clk_get failed\n", dnfn);
496 goto err;
497 }
498
499 pll_base = of_iomap(np, 0);
500 if (!pll_base) {
501 pr_err("%s: can't map pll registers\n", dnfn);
502 goto err_clk;
503 }
504
Antony Pavlov5ae5c452016-03-17 06:34:18 +0300505 if (of_device_is_compatible(np, "qca,ar9130-pll"))
506 ar724x_clk_init(ref_clk, pll_base);
507 else if (of_device_is_compatible(np, "qca,ar9330-pll"))
508 ar9330_clk_init(ref_clk, pll_base);
509 else {
510 pr_err("%s: could not find any appropriate clk_init()\n", dnfn);
511 goto err_clk;
512 }
Antony Pavlov3bdf1072016-03-17 06:34:15 +0300513
514 if (of_clk_add_provider(np, of_clk_src_onecell_get, &clk_data)) {
515 pr_err("%s: could not register clk provider\n", dnfn);
516 goto err_clk;
517 }
518
519 return;
520
521err_clk:
522 clk_put(ref_clk);
523
524err:
525 return;
526}
527CLK_OF_DECLARE(ar9130_clk, "qca,ar9130-pll", ath79_clocks_init_dt_ng);
Antony Pavlov5ae5c452016-03-17 06:34:18 +0300528CLK_OF_DECLARE(ar9330_clk, "qca,ar9330-pll", ath79_clocks_init_dt_ng);
Alban Bedel6451af02015-05-31 02:18:22 +0200529#endif