Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1 | /* |
| 2 | * Intel GTT (Graphics Translation Table) routines |
| 3 | * |
| 4 | * Caveat: This driver implements the linux agp interface, but this is far from |
| 5 | * a agp driver! GTT support ended up here for purely historical reasons: The |
| 6 | * old userspace intel graphics drivers needed an interface to map memory into |
| 7 | * the GTT. And the drm provides a default interface for graphic devices sitting |
| 8 | * on an agp port. So it made sense to fake the GTT support as an agp port to |
| 9 | * avoid having to create a new api. |
| 10 | * |
| 11 | * With gem this does not make much sense anymore, just needlessly complicates |
| 12 | * the code. But as long as the old graphics stack is still support, it's stuck |
| 13 | * here. |
| 14 | * |
| 15 | * /fairy-tale-mode off |
| 16 | */ |
| 17 | |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 18 | #include <linux/module.h> |
| 19 | #include <linux/pci.h> |
| 20 | #include <linux/init.h> |
| 21 | #include <linux/kernel.h> |
| 22 | #include <linux/pagemap.h> |
| 23 | #include <linux/agp_backend.h> |
Chris Wilson | bdb8b97 | 2010-12-22 11:37:09 +0000 | [diff] [blame] | 24 | #include <linux/delay.h> |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 25 | #include <asm/smp.h> |
| 26 | #include "agp.h" |
| 27 | #include "intel-agp.h" |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 28 | #include <drm/intel-gtt.h> |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 29 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 30 | /* |
| 31 | * If we have Intel graphics, we're not going to have anything other than |
| 32 | * an Intel IOMMU. So make the correct use of the PCI DMA API contingent |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 33 | * on the Intel IOMMU support (CONFIG_INTEL_IOMMU). |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 34 | * Only newer chipsets need to bother with this, of course. |
| 35 | */ |
Suresh Siddha | d3f1381 | 2011-08-23 17:05:25 -0700 | [diff] [blame] | 36 | #ifdef CONFIG_INTEL_IOMMU |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 37 | #define USE_PCI_DMA_API 1 |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 38 | #else |
| 39 | #define USE_PCI_DMA_API 0 |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 40 | #endif |
| 41 | |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 42 | struct intel_gtt_driver { |
| 43 | unsigned int gen : 8; |
| 44 | unsigned int is_g33 : 1; |
| 45 | unsigned int is_pineview : 1; |
| 46 | unsigned int is_ironlake : 1; |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 47 | unsigned int has_pgtbl_enable : 1; |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 48 | unsigned int dma_mask_size : 8; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 49 | /* Chipset specific GTT setup */ |
| 50 | int (*setup)(void); |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 51 | /* This should undo anything done in ->setup() save the unmapping |
| 52 | * of the mmio register file, that's done in the generic code. */ |
| 53 | void (*cleanup)(void); |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 54 | void (*write_entry)(dma_addr_t addr, unsigned int entry, unsigned int flags); |
| 55 | /* Flags is a more or less chipset specific opaque value. |
| 56 | * For chipsets that need to support old ums (non-gem) code, this |
| 57 | * needs to be identical to the various supported agp memory types! */ |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 58 | bool (*check_flags)(unsigned int flags); |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 59 | void (*chipset_flush)(void); |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 60 | }; |
| 61 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 62 | static struct _intel_private { |
Daniel Vetter | 0ade638 | 2010-08-24 22:18:41 +0200 | [diff] [blame] | 63 | struct intel_gtt base; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 64 | const struct intel_gtt_driver *driver; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 65 | struct pci_dev *pcidev; /* device one */ |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 66 | struct pci_dev *bridge_dev; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 67 | u8 __iomem *registers; |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 68 | phys_addr_t gtt_bus_addr; |
Daniel Vetter | b3eafc5 | 2010-09-23 20:04:17 +0200 | [diff] [blame] | 69 | u32 PGETBL_save; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 70 | u32 __iomem *gtt; /* I915G */ |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 71 | bool clear_fake_agp; /* on first access via agp, fill with scratch */ |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 72 | int num_dcache_entries; |
Chris Wilson | bdb8b97 | 2010-12-22 11:37:09 +0000 | [diff] [blame] | 73 | void __iomem *i9xx_flush_page; |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 74 | char *i81x_gtt_table; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 75 | struct resource ifp_resource; |
| 76 | int resource_valid; |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 77 | struct page *scratch_page; |
Ben Widawsky | 9c61a32 | 2013-01-18 12:30:32 -0800 | [diff] [blame] | 78 | phys_addr_t scratch_page_dma; |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 79 | int refcount; |
Ben Widawsky | 8d2e630 | 2013-01-18 12:30:33 -0800 | [diff] [blame] | 80 | /* Whether i915 needs to use the dmar apis or not. */ |
| 81 | unsigned int needs_dmar : 1; |
Ben Widawsky | e5c6537 | 2013-01-18 12:30:34 -0800 | [diff] [blame^] | 82 | phys_addr_t gma_bus_addr; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 83 | } intel_private; |
| 84 | |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 85 | #define INTEL_GTT_GEN intel_private.driver->gen |
| 86 | #define IS_G33 intel_private.driver->is_g33 |
| 87 | #define IS_PINEVIEW intel_private.driver->is_pineview |
| 88 | #define IS_IRONLAKE intel_private.driver->is_ironlake |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 89 | #define HAS_PGTBL_EN intel_private.driver->has_pgtbl_enable |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 90 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 91 | static int intel_gtt_map_memory(struct page **pages, |
| 92 | unsigned int num_entries, |
| 93 | struct sg_table *st) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 94 | { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 95 | struct scatterlist *sg; |
| 96 | int i; |
| 97 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 98 | DBG("try mapping %lu pages\n", (unsigned long)num_entries); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 99 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 100 | if (sg_alloc_table(st, num_entries, GFP_KERNEL)) |
Chris Wilson | 831cd44 | 2010-07-24 18:29:37 +0100 | [diff] [blame] | 101 | goto err; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 102 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 103 | for_each_sg(st->sgl, sg, num_entries, i) |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 104 | sg_set_page(sg, pages[i], PAGE_SIZE, 0); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 105 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 106 | if (!pci_map_sg(intel_private.pcidev, |
| 107 | st->sgl, st->nents, PCI_DMA_BIDIRECTIONAL)) |
Chris Wilson | 831cd44 | 2010-07-24 18:29:37 +0100 | [diff] [blame] | 108 | goto err; |
| 109 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 110 | return 0; |
Chris Wilson | 831cd44 | 2010-07-24 18:29:37 +0100 | [diff] [blame] | 111 | |
| 112 | err: |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 113 | sg_free_table(st); |
Chris Wilson | 831cd44 | 2010-07-24 18:29:37 +0100 | [diff] [blame] | 114 | return -ENOMEM; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 115 | } |
| 116 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 117 | static void intel_gtt_unmap_memory(struct scatterlist *sg_list, int num_sg) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 118 | { |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 119 | struct sg_table st; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 120 | DBG("try unmapping %lu pages\n", (unsigned long)mem->page_count); |
| 121 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 122 | pci_unmap_sg(intel_private.pcidev, sg_list, |
| 123 | num_sg, PCI_DMA_BIDIRECTIONAL); |
| 124 | |
| 125 | st.sgl = sg_list; |
| 126 | st.orig_nents = st.nents = num_sg; |
| 127 | |
| 128 | sg_free_table(&st); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 129 | } |
| 130 | |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 131 | static void intel_fake_agp_enable(struct agp_bridge_data *bridge, u32 mode) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 132 | { |
| 133 | return; |
| 134 | } |
| 135 | |
| 136 | /* Exists to support ARGB cursors */ |
| 137 | static struct page *i8xx_alloc_pages(void) |
| 138 | { |
| 139 | struct page *page; |
| 140 | |
| 141 | page = alloc_pages(GFP_KERNEL | GFP_DMA32, 2); |
| 142 | if (page == NULL) |
| 143 | return NULL; |
| 144 | |
| 145 | if (set_pages_uc(page, 4) < 0) { |
| 146 | set_pages_wb(page, 4); |
| 147 | __free_pages(page, 2); |
| 148 | return NULL; |
| 149 | } |
| 150 | get_page(page); |
| 151 | atomic_inc(&agp_bridge->current_memory_agp); |
| 152 | return page; |
| 153 | } |
| 154 | |
| 155 | static void i8xx_destroy_pages(struct page *page) |
| 156 | { |
| 157 | if (page == NULL) |
| 158 | return; |
| 159 | |
| 160 | set_pages_wb(page, 4); |
| 161 | put_page(page); |
| 162 | __free_pages(page, 2); |
| 163 | atomic_dec(&agp_bridge->current_memory_agp); |
| 164 | } |
| 165 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 166 | #define I810_GTT_ORDER 4 |
| 167 | static int i810_setup(void) |
| 168 | { |
| 169 | u32 reg_addr; |
| 170 | char *gtt_table; |
| 171 | |
| 172 | /* i81x does not preallocate the gtt. It's always 64kb in size. */ |
| 173 | gtt_table = alloc_gatt_pages(I810_GTT_ORDER); |
| 174 | if (gtt_table == NULL) |
| 175 | return -ENOMEM; |
| 176 | intel_private.i81x_gtt_table = gtt_table; |
| 177 | |
| 178 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); |
| 179 | reg_addr &= 0xfff80000; |
| 180 | |
| 181 | intel_private.registers = ioremap(reg_addr, KB(64)); |
| 182 | if (!intel_private.registers) |
| 183 | return -ENOMEM; |
| 184 | |
| 185 | writel(virt_to_phys(gtt_table) | I810_PGETBL_ENABLED, |
| 186 | intel_private.registers+I810_PGETBL_CTL); |
| 187 | |
| 188 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
| 189 | |
| 190 | if ((readl(intel_private.registers+I810_DRAM_CTL) |
| 191 | & I810_DRAM_ROW_0) == I810_DRAM_ROW_0_SDRAM) { |
| 192 | dev_info(&intel_private.pcidev->dev, |
| 193 | "detected 4MB dedicated video ram\n"); |
| 194 | intel_private.num_dcache_entries = 1024; |
| 195 | } |
| 196 | |
| 197 | return 0; |
| 198 | } |
| 199 | |
| 200 | static void i810_cleanup(void) |
| 201 | { |
| 202 | writel(0, intel_private.registers+I810_PGETBL_CTL); |
| 203 | free_gatt_pages(intel_private.i81x_gtt_table, I810_GTT_ORDER); |
| 204 | } |
| 205 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 206 | static int i810_insert_dcache_entries(struct agp_memory *mem, off_t pg_start, |
| 207 | int type) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 208 | { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 209 | int i; |
| 210 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 211 | if ((pg_start + mem->page_count) |
| 212 | > intel_private.num_dcache_entries) |
| 213 | return -EINVAL; |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 214 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 215 | if (!mem->is_flushed) |
| 216 | global_cache_flush(); |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 217 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 218 | for (i = pg_start; i < (pg_start + mem->page_count); i++) { |
| 219 | dma_addr_t addr = i << PAGE_SHIFT; |
| 220 | intel_private.driver->write_entry(addr, |
| 221 | i, type); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 222 | } |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 223 | readl(intel_private.gtt+i-1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 224 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 225 | return 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 226 | } |
| 227 | |
| 228 | /* |
| 229 | * The i810/i830 requires a physical address to program its mouse |
| 230 | * pointer into hardware. |
| 231 | * However the Xserver still writes to it through the agp aperture. |
| 232 | */ |
| 233 | static struct agp_memory *alloc_agpphysmem_i8xx(size_t pg_count, int type) |
| 234 | { |
| 235 | struct agp_memory *new; |
| 236 | struct page *page; |
| 237 | |
| 238 | switch (pg_count) { |
| 239 | case 1: page = agp_bridge->driver->agp_alloc_page(agp_bridge); |
| 240 | break; |
| 241 | case 4: |
| 242 | /* kludge to get 4 physical pages for ARGB cursor */ |
| 243 | page = i8xx_alloc_pages(); |
| 244 | break; |
| 245 | default: |
| 246 | return NULL; |
| 247 | } |
| 248 | |
| 249 | if (page == NULL) |
| 250 | return NULL; |
| 251 | |
| 252 | new = agp_create_memory(pg_count); |
| 253 | if (new == NULL) |
| 254 | return NULL; |
| 255 | |
| 256 | new->pages[0] = page; |
| 257 | if (pg_count == 4) { |
| 258 | /* kludge to get 4 physical pages for ARGB cursor */ |
| 259 | new->pages[1] = new->pages[0] + 1; |
| 260 | new->pages[2] = new->pages[1] + 1; |
| 261 | new->pages[3] = new->pages[2] + 1; |
| 262 | } |
| 263 | new->page_count = pg_count; |
| 264 | new->num_scratch_pages = pg_count; |
| 265 | new->type = AGP_PHYS_MEMORY; |
| 266 | new->physical = page_to_phys(new->pages[0]); |
| 267 | return new; |
| 268 | } |
| 269 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 270 | static void intel_i810_free_by_type(struct agp_memory *curr) |
| 271 | { |
| 272 | agp_free_key(curr->key); |
| 273 | if (curr->type == AGP_PHYS_MEMORY) { |
| 274 | if (curr->page_count == 4) |
| 275 | i8xx_destroy_pages(curr->pages[0]); |
| 276 | else { |
| 277 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
| 278 | AGP_PAGE_DESTROY_UNMAP); |
| 279 | agp_bridge->driver->agp_destroy_page(curr->pages[0], |
| 280 | AGP_PAGE_DESTROY_FREE); |
| 281 | } |
| 282 | agp_free_page_array(curr); |
| 283 | } |
| 284 | kfree(curr); |
| 285 | } |
| 286 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 287 | static int intel_gtt_setup_scratch_page(void) |
| 288 | { |
| 289 | struct page *page; |
| 290 | dma_addr_t dma_addr; |
| 291 | |
| 292 | page = alloc_page(GFP_KERNEL | GFP_DMA32 | __GFP_ZERO); |
| 293 | if (page == NULL) |
| 294 | return -ENOMEM; |
| 295 | get_page(page); |
| 296 | set_pages_uc(page, 1); |
| 297 | |
Ben Widawsky | 8d2e630 | 2013-01-18 12:30:33 -0800 | [diff] [blame] | 298 | if (intel_private.needs_dmar) { |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 299 | dma_addr = pci_map_page(intel_private.pcidev, page, 0, |
| 300 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 301 | if (pci_dma_mapping_error(intel_private.pcidev, dma_addr)) |
| 302 | return -EINVAL; |
| 303 | |
Ben Widawsky | 9c61a32 | 2013-01-18 12:30:32 -0800 | [diff] [blame] | 304 | intel_private.scratch_page_dma = dma_addr; |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 305 | } else |
Ben Widawsky | 9c61a32 | 2013-01-18 12:30:32 -0800 | [diff] [blame] | 306 | intel_private.scratch_page_dma = page_to_phys(page); |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 307 | |
| 308 | intel_private.scratch_page = page; |
| 309 | |
| 310 | return 0; |
| 311 | } |
| 312 | |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 313 | static void i810_write_entry(dma_addr_t addr, unsigned int entry, |
| 314 | unsigned int flags) |
| 315 | { |
| 316 | u32 pte_flags = I810_PTE_VALID; |
| 317 | |
| 318 | switch (flags) { |
| 319 | case AGP_DCACHE_MEMORY: |
| 320 | pte_flags |= I810_PTE_LOCAL; |
| 321 | break; |
| 322 | case AGP_USER_CACHED_MEMORY: |
| 323 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
| 324 | break; |
| 325 | } |
| 326 | |
| 327 | writel(addr | pte_flags, intel_private.gtt + entry); |
| 328 | } |
| 329 | |
Chris Wilson | 7bdc9ab | 2010-11-09 17:53:20 +0000 | [diff] [blame] | 330 | static const struct aper_size_info_fixed intel_fake_agp_sizes[] = { |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 331 | {32, 8192, 3}, |
| 332 | {64, 16384, 4}, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 333 | {128, 32768, 5}, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 334 | {256, 65536, 6}, |
| 335 | {512, 131072, 7}, |
| 336 | }; |
| 337 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 338 | static unsigned int intel_gtt_stolen_size(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 339 | { |
| 340 | u16 gmch_ctrl; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 341 | u8 rdct; |
| 342 | int local = 0; |
| 343 | static const int ddt[4] = { 0, 16, 32, 64 }; |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 344 | unsigned int stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 345 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 346 | if (INTEL_GTT_GEN == 1) |
| 347 | return 0; /* no stolen mem on i81x */ |
| 348 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 349 | pci_read_config_word(intel_private.bridge_dev, |
| 350 | I830_GMCH_CTRL, &gmch_ctrl); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 351 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 352 | if (intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82830_HB || |
| 353 | intel_private.bridge_dev->device == PCI_DEVICE_ID_INTEL_82845G_HB) { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 354 | switch (gmch_ctrl & I830_GMCH_GMS_MASK) { |
| 355 | case I830_GMCH_GMS_STOLEN_512: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 356 | stolen_size = KB(512); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 357 | break; |
| 358 | case I830_GMCH_GMS_STOLEN_1024: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 359 | stolen_size = MB(1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 360 | break; |
| 361 | case I830_GMCH_GMS_STOLEN_8192: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 362 | stolen_size = MB(8); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 363 | break; |
| 364 | case I830_GMCH_GMS_LOCAL: |
| 365 | rdct = readb(intel_private.registers+I830_RDRAM_CHANNEL_TYPE); |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 366 | stolen_size = (I830_RDRAM_ND(rdct) + 1) * |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 367 | MB(ddt[I830_RDRAM_DDT(rdct)]); |
| 368 | local = 1; |
| 369 | break; |
| 370 | default: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 371 | stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 372 | break; |
| 373 | } |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 374 | } else { |
| 375 | switch (gmch_ctrl & I855_GMCH_GMS_MASK) { |
| 376 | case I855_GMCH_GMS_STOLEN_1M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 377 | stolen_size = MB(1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 378 | break; |
| 379 | case I855_GMCH_GMS_STOLEN_4M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 380 | stolen_size = MB(4); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 381 | break; |
| 382 | case I855_GMCH_GMS_STOLEN_8M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 383 | stolen_size = MB(8); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 384 | break; |
| 385 | case I855_GMCH_GMS_STOLEN_16M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 386 | stolen_size = MB(16); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 387 | break; |
| 388 | case I855_GMCH_GMS_STOLEN_32M: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 389 | stolen_size = MB(32); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 390 | break; |
| 391 | case I915_GMCH_GMS_STOLEN_48M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 392 | stolen_size = MB(48); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 393 | break; |
| 394 | case I915_GMCH_GMS_STOLEN_64M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 395 | stolen_size = MB(64); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 396 | break; |
| 397 | case G33_GMCH_GMS_STOLEN_128M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 398 | stolen_size = MB(128); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 399 | break; |
| 400 | case G33_GMCH_GMS_STOLEN_256M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 401 | stolen_size = MB(256); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 402 | break; |
| 403 | case INTEL_GMCH_GMS_STOLEN_96M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 404 | stolen_size = MB(96); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 405 | break; |
| 406 | case INTEL_GMCH_GMS_STOLEN_160M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 407 | stolen_size = MB(160); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 408 | break; |
| 409 | case INTEL_GMCH_GMS_STOLEN_224M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 410 | stolen_size = MB(224); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 411 | break; |
| 412 | case INTEL_GMCH_GMS_STOLEN_352M: |
Daniel Vetter | 77ad498 | 2010-08-27 16:25:54 +0200 | [diff] [blame] | 413 | stolen_size = MB(352); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 414 | break; |
| 415 | default: |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 416 | stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 417 | break; |
| 418 | } |
| 419 | } |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 420 | |
Chris Wilson | 1b6064d | 2010-11-23 12:33:54 +0000 | [diff] [blame] | 421 | if (stolen_size > 0) { |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 422 | dev_info(&intel_private.bridge_dev->dev, "detected %dK %s memory\n", |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 423 | stolen_size / KB(1), local ? "local" : "stolen"); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 424 | } else { |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 425 | dev_info(&intel_private.bridge_dev->dev, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 426 | "no pre-allocated video memory detected\n"); |
Daniel Vetter | d8d9abc | 2010-08-27 16:13:52 +0200 | [diff] [blame] | 427 | stolen_size = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 428 | } |
| 429 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 430 | return stolen_size; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 431 | } |
| 432 | |
Daniel Vetter | 2017284 | 2010-09-24 18:25:59 +0200 | [diff] [blame] | 433 | static void i965_adjust_pgetbl_size(unsigned int size_flag) |
| 434 | { |
| 435 | u32 pgetbl_ctl, pgetbl_ctl2; |
| 436 | |
| 437 | /* ensure that ppgtt is disabled */ |
| 438 | pgetbl_ctl2 = readl(intel_private.registers+I965_PGETBL_CTL2); |
| 439 | pgetbl_ctl2 &= ~I810_PGETBL_ENABLED; |
| 440 | writel(pgetbl_ctl2, intel_private.registers+I965_PGETBL_CTL2); |
| 441 | |
| 442 | /* write the new ggtt size */ |
| 443 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
| 444 | pgetbl_ctl &= ~I965_PGETBL_SIZE_MASK; |
| 445 | pgetbl_ctl |= size_flag; |
| 446 | writel(pgetbl_ctl, intel_private.registers+I810_PGETBL_CTL); |
| 447 | } |
| 448 | |
| 449 | static unsigned int i965_gtt_total_entries(void) |
| 450 | { |
| 451 | int size; |
| 452 | u32 pgetbl_ctl; |
| 453 | u16 gmch_ctl; |
| 454 | |
| 455 | pci_read_config_word(intel_private.bridge_dev, |
| 456 | I830_GMCH_CTRL, &gmch_ctl); |
| 457 | |
| 458 | if (INTEL_GTT_GEN == 5) { |
| 459 | switch (gmch_ctl & G4x_GMCH_SIZE_MASK) { |
| 460 | case G4x_GMCH_SIZE_1M: |
| 461 | case G4x_GMCH_SIZE_VT_1M: |
| 462 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1MB); |
| 463 | break; |
| 464 | case G4x_GMCH_SIZE_VT_1_5M: |
| 465 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_1_5MB); |
| 466 | break; |
| 467 | case G4x_GMCH_SIZE_2M: |
| 468 | case G4x_GMCH_SIZE_VT_2M: |
| 469 | i965_adjust_pgetbl_size(I965_PGETBL_SIZE_2MB); |
| 470 | break; |
| 471 | } |
| 472 | } |
| 473 | |
| 474 | pgetbl_ctl = readl(intel_private.registers+I810_PGETBL_CTL); |
| 475 | |
| 476 | switch (pgetbl_ctl & I965_PGETBL_SIZE_MASK) { |
| 477 | case I965_PGETBL_SIZE_128KB: |
| 478 | size = KB(128); |
| 479 | break; |
| 480 | case I965_PGETBL_SIZE_256KB: |
| 481 | size = KB(256); |
| 482 | break; |
| 483 | case I965_PGETBL_SIZE_512KB: |
| 484 | size = KB(512); |
| 485 | break; |
| 486 | /* GTT pagetable sizes bigger than 512KB are not possible on G33! */ |
| 487 | case I965_PGETBL_SIZE_1MB: |
| 488 | size = KB(1024); |
| 489 | break; |
| 490 | case I965_PGETBL_SIZE_2MB: |
| 491 | size = KB(2048); |
| 492 | break; |
| 493 | case I965_PGETBL_SIZE_1_5MB: |
| 494 | size = KB(1024 + 512); |
| 495 | break; |
| 496 | default: |
| 497 | dev_info(&intel_private.pcidev->dev, |
| 498 | "unknown page table size, assuming 512KB\n"); |
| 499 | size = KB(512); |
| 500 | } |
| 501 | |
| 502 | return size/4; |
| 503 | } |
| 504 | |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 505 | static unsigned int intel_gtt_total_entries(void) |
| 506 | { |
Daniel Vetter | 2017284 | 2010-09-24 18:25:59 +0200 | [diff] [blame] | 507 | if (IS_G33 || INTEL_GTT_GEN == 4 || INTEL_GTT_GEN == 5) |
| 508 | return i965_gtt_total_entries(); |
Ben Widawsky | 009946f | 2012-11-04 09:21:29 -0800 | [diff] [blame] | 509 | else { |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 510 | /* On previous hardware, the GTT size was just what was |
| 511 | * required to map the aperture. |
| 512 | */ |
Daniel Vetter | e5e408f | 2010-08-28 11:04:32 +0200 | [diff] [blame] | 513 | return intel_private.base.gtt_mappable_entries; |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 514 | } |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 515 | } |
Daniel Vetter | fbe4078 | 2010-08-27 17:12:41 +0200 | [diff] [blame] | 516 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 517 | static unsigned int intel_gtt_mappable_entries(void) |
| 518 | { |
| 519 | unsigned int aperture_size; |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 520 | |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 521 | if (INTEL_GTT_GEN == 1) { |
| 522 | u32 smram_miscc; |
| 523 | |
| 524 | pci_read_config_dword(intel_private.bridge_dev, |
| 525 | I810_SMRAM_MISCC, &smram_miscc); |
| 526 | |
| 527 | if ((smram_miscc & I810_GFX_MEM_WIN_SIZE) |
| 528 | == I810_GFX_MEM_WIN_32M) |
| 529 | aperture_size = MB(32); |
| 530 | else |
| 531 | aperture_size = MB(64); |
| 532 | } else if (INTEL_GTT_GEN == 2) { |
Chris Wilson | b1c5b0f | 2010-09-14 19:30:13 +0100 | [diff] [blame] | 533 | u16 gmch_ctrl; |
| 534 | |
| 535 | pci_read_config_word(intel_private.bridge_dev, |
| 536 | I830_GMCH_CTRL, &gmch_ctrl); |
| 537 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 538 | if ((gmch_ctrl & I830_GMCH_MEM_MASK) == I830_GMCH_MEM_64M) |
Chris Wilson | b1c5b0f | 2010-09-14 19:30:13 +0100 | [diff] [blame] | 539 | aperture_size = MB(64); |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 540 | else |
Chris Wilson | b1c5b0f | 2010-09-14 19:30:13 +0100 | [diff] [blame] | 541 | aperture_size = MB(128); |
Daniel Vetter | 239918f | 2010-08-31 22:30:43 +0200 | [diff] [blame] | 542 | } else { |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 543 | /* 9xx supports large sizes, just look at the length */ |
| 544 | aperture_size = pci_resource_len(intel_private.pcidev, 2); |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 545 | } |
| 546 | |
| 547 | return aperture_size >> PAGE_SHIFT; |
| 548 | } |
| 549 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 550 | static void intel_gtt_teardown_scratch_page(void) |
| 551 | { |
| 552 | set_pages_wb(intel_private.scratch_page, 1); |
Ben Widawsky | 9c61a32 | 2013-01-18 12:30:32 -0800 | [diff] [blame] | 553 | pci_unmap_page(intel_private.pcidev, intel_private.scratch_page_dma, |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 554 | PAGE_SIZE, PCI_DMA_BIDIRECTIONAL); |
| 555 | put_page(intel_private.scratch_page); |
| 556 | __free_page(intel_private.scratch_page); |
| 557 | } |
| 558 | |
| 559 | static void intel_gtt_cleanup(void) |
| 560 | { |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 561 | intel_private.driver->cleanup(); |
| 562 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 563 | iounmap(intel_private.gtt); |
| 564 | iounmap(intel_private.registers); |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 565 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 566 | intel_gtt_teardown_scratch_page(); |
| 567 | } |
| 568 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 569 | static int intel_gtt_init(void) |
| 570 | { |
Daniel Vetter | 32e3cd6 | 2012-06-07 15:56:02 +0200 | [diff] [blame] | 571 | u32 gma_addr; |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 572 | u32 gtt_map_size; |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 573 | int ret; |
| 574 | |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 575 | ret = intel_private.driver->setup(); |
| 576 | if (ret != 0) |
| 577 | return ret; |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 578 | |
| 579 | intel_private.base.gtt_mappable_entries = intel_gtt_mappable_entries(); |
| 580 | intel_private.base.gtt_total_entries = intel_gtt_total_entries(); |
| 581 | |
Daniel Vetter | b3eafc5 | 2010-09-23 20:04:17 +0200 | [diff] [blame] | 582 | /* save the PGETBL reg for resume */ |
| 583 | intel_private.PGETBL_save = |
| 584 | readl(intel_private.registers+I810_PGETBL_CTL) |
| 585 | & ~I810_PGETBL_ENABLED; |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 586 | /* we only ever restore the register when enabling the PGTBL... */ |
| 587 | if (HAS_PGTBL_EN) |
| 588 | intel_private.PGETBL_save |= I810_PGETBL_ENABLED; |
Daniel Vetter | b3eafc5 | 2010-09-23 20:04:17 +0200 | [diff] [blame] | 589 | |
Daniel Vetter | 0af9e92 | 2010-09-12 14:04:03 +0200 | [diff] [blame] | 590 | dev_info(&intel_private.bridge_dev->dev, |
| 591 | "detected gtt size: %dK total, %dK mappable\n", |
| 592 | intel_private.base.gtt_total_entries * 4, |
| 593 | intel_private.base.gtt_mappable_entries * 4); |
| 594 | |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 595 | gtt_map_size = intel_private.base.gtt_total_entries * 4; |
| 596 | |
Chris Wilson | edef7e6 | 2012-09-14 11:57:47 +0100 | [diff] [blame] | 597 | intel_private.gtt = NULL; |
Daniel Vetter | 9169d3a | 2012-10-10 23:14:01 +0200 | [diff] [blame] | 598 | if (INTEL_GTT_GEN < 6 && INTEL_GTT_GEN > 2) |
Chris Wilson | edef7e6 | 2012-09-14 11:57:47 +0100 | [diff] [blame] | 599 | intel_private.gtt = ioremap_wc(intel_private.gtt_bus_addr, |
| 600 | gtt_map_size); |
| 601 | if (intel_private.gtt == NULL) |
| 602 | intel_private.gtt = ioremap(intel_private.gtt_bus_addr, |
| 603 | gtt_map_size); |
| 604 | if (intel_private.gtt == NULL) { |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 605 | intel_private.driver->cleanup(); |
Daniel Vetter | f67eab6 | 2010-08-29 17:27:36 +0200 | [diff] [blame] | 606 | iounmap(intel_private.registers); |
| 607 | return -ENOMEM; |
| 608 | } |
| 609 | |
| 610 | global_cache_flush(); /* FIXME: ? */ |
| 611 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 612 | intel_private.base.stolen_size = intel_gtt_stolen_size(); |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 613 | |
Ben Widawsky | 8d2e630 | 2013-01-18 12:30:33 -0800 | [diff] [blame] | 614 | intel_private.needs_dmar = USE_PCI_DMA_API && INTEL_GTT_GEN > 2; |
Dave Airlie | a46f310 | 2011-01-12 11:38:37 +1000 | [diff] [blame] | 615 | |
Daniel Vetter | 0e87d2b | 2010-09-07 22:11:15 +0200 | [diff] [blame] | 616 | ret = intel_gtt_setup_scratch_page(); |
| 617 | if (ret != 0) { |
| 618 | intel_gtt_cleanup(); |
| 619 | return ret; |
| 620 | } |
| 621 | |
Daniel Vetter | 32e3cd6 | 2012-06-07 15:56:02 +0200 | [diff] [blame] | 622 | if (INTEL_GTT_GEN <= 2) |
| 623 | pci_read_config_dword(intel_private.pcidev, I810_GMADDR, |
| 624 | &gma_addr); |
| 625 | else |
| 626 | pci_read_config_dword(intel_private.pcidev, I915_GMADDR, |
| 627 | &gma_addr); |
| 628 | |
Ben Widawsky | e5c6537 | 2013-01-18 12:30:34 -0800 | [diff] [blame^] | 629 | intel_private.gma_bus_addr = (gma_addr & PCI_BASE_ADDRESS_MEM_MASK); |
Daniel Vetter | 32e3cd6 | 2012-06-07 15:56:02 +0200 | [diff] [blame] | 630 | |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 631 | return 0; |
| 632 | } |
| 633 | |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 634 | static int intel_fake_agp_fetch_size(void) |
| 635 | { |
Chris Wilson | 9e76e7b | 2010-09-14 12:12:11 +0100 | [diff] [blame] | 636 | int num_sizes = ARRAY_SIZE(intel_fake_agp_sizes); |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 637 | unsigned int aper_size; |
| 638 | int i; |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 639 | |
| 640 | aper_size = (intel_private.base.gtt_mappable_entries << PAGE_SHIFT) |
| 641 | / MB(1); |
| 642 | |
| 643 | for (i = 0; i < num_sizes; i++) { |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 644 | if (aper_size == intel_fake_agp_sizes[i].size) { |
Chris Wilson | 9e76e7b | 2010-09-14 12:12:11 +0100 | [diff] [blame] | 645 | agp_bridge->current_size = |
| 646 | (void *) (intel_fake_agp_sizes + i); |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 647 | return aper_size; |
| 648 | } |
| 649 | } |
| 650 | |
| 651 | return 0; |
| 652 | } |
| 653 | |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 654 | static void i830_cleanup(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 655 | { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 656 | } |
| 657 | |
| 658 | /* The chipset_flush interface needs to get data that has already been |
| 659 | * flushed out of the CPU all the way out to main memory, because the GPU |
| 660 | * doesn't snoop those buffers. |
| 661 | * |
| 662 | * The 8xx series doesn't have the same lovely interface for flushing the |
| 663 | * chipset write buffers that the later chips do. According to the 865 |
| 664 | * specs, it's 64 octwords, or 1KB. So, to get those previous things in |
| 665 | * that buffer out, we just fill 1KB and clflush it out, on the assumption |
| 666 | * that it'll push whatever was in there out. It appears to work. |
| 667 | */ |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 668 | static void i830_chipset_flush(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 669 | { |
Chris Wilson | bdb8b97 | 2010-12-22 11:37:09 +0000 | [diff] [blame] | 670 | unsigned long timeout = jiffies + msecs_to_jiffies(1000); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 671 | |
Chris Wilson | bdb8b97 | 2010-12-22 11:37:09 +0000 | [diff] [blame] | 672 | /* Forcibly evict everything from the CPU write buffers. |
| 673 | * clflush appears to be insufficient. |
| 674 | */ |
| 675 | wbinvd_on_all_cpus(); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 676 | |
Chris Wilson | bdb8b97 | 2010-12-22 11:37:09 +0000 | [diff] [blame] | 677 | /* Now we've only seen documents for this magic bit on 855GM, |
| 678 | * we hope it exists for the other gen2 chipsets... |
| 679 | * |
| 680 | * Also works as advertised on my 845G. |
| 681 | */ |
| 682 | writel(readl(intel_private.registers+I830_HIC) | (1<<31), |
| 683 | intel_private.registers+I830_HIC); |
| 684 | |
| 685 | while (readl(intel_private.registers+I830_HIC) & (1<<31)) { |
| 686 | if (time_after(jiffies, timeout)) |
| 687 | break; |
| 688 | |
| 689 | udelay(50); |
| 690 | } |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 691 | } |
| 692 | |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 693 | static void i830_write_entry(dma_addr_t addr, unsigned int entry, |
| 694 | unsigned int flags) |
| 695 | { |
| 696 | u32 pte_flags = I810_PTE_VALID; |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 697 | |
Daniel Vetter | b47cf66 | 2010-11-04 18:41:50 +0100 | [diff] [blame] | 698 | if (flags == AGP_USER_CACHED_MEMORY) |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 699 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 700 | |
| 701 | writel(addr | pte_flags, intel_private.gtt + entry); |
| 702 | } |
| 703 | |
Daniel Vetter | 8ecd1a6 | 2012-06-07 15:56:03 +0200 | [diff] [blame] | 704 | bool intel_enable_gtt(void) |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 705 | { |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 706 | u8 __iomem *reg; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 707 | |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 708 | if (INTEL_GTT_GEN == 2) { |
| 709 | u16 gmch_ctrl; |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 710 | |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 711 | pci_read_config_word(intel_private.bridge_dev, |
| 712 | I830_GMCH_CTRL, &gmch_ctrl); |
| 713 | gmch_ctrl |= I830_GMCH_ENABLED; |
| 714 | pci_write_config_word(intel_private.bridge_dev, |
| 715 | I830_GMCH_CTRL, gmch_ctrl); |
| 716 | |
| 717 | pci_read_config_word(intel_private.bridge_dev, |
| 718 | I830_GMCH_CTRL, &gmch_ctrl); |
| 719 | if ((gmch_ctrl & I830_GMCH_ENABLED) == 0) { |
| 720 | dev_err(&intel_private.pcidev->dev, |
| 721 | "failed to enable the GTT: GMCH_CTRL=%x\n", |
| 722 | gmch_ctrl); |
| 723 | return false; |
| 724 | } |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 725 | } |
| 726 | |
Chris Wilson | c97689d | 2010-12-23 10:40:38 +0000 | [diff] [blame] | 727 | /* On the resume path we may be adjusting the PGTBL value, so |
| 728 | * be paranoid and flush all chipset write buffers... |
| 729 | */ |
| 730 | if (INTEL_GTT_GEN >= 3) |
| 731 | writel(0, intel_private.registers+GFX_FLSH_CNTL); |
| 732 | |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 733 | reg = intel_private.registers+I810_PGETBL_CTL; |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 734 | writel(intel_private.PGETBL_save, reg); |
| 735 | if (HAS_PGTBL_EN && (readl(reg) & I810_PGETBL_ENABLED) == 0) { |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 736 | dev_err(&intel_private.pcidev->dev, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 737 | "failed to enable the GTT: PGETBL=%x [expected %x]\n", |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 738 | readl(reg), intel_private.PGETBL_save); |
| 739 | return false; |
| 740 | } |
| 741 | |
Chris Wilson | c97689d | 2010-12-23 10:40:38 +0000 | [diff] [blame] | 742 | if (INTEL_GTT_GEN >= 3) |
| 743 | writel(0, intel_private.registers+GFX_FLSH_CNTL); |
| 744 | |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 745 | return true; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 746 | } |
Daniel Vetter | 8ecd1a6 | 2012-06-07 15:56:03 +0200 | [diff] [blame] | 747 | EXPORT_SYMBOL(intel_enable_gtt); |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 748 | |
| 749 | static int i830_setup(void) |
| 750 | { |
| 751 | u32 reg_addr; |
| 752 | |
| 753 | pci_read_config_dword(intel_private.pcidev, I810_MMADDR, ®_addr); |
| 754 | reg_addr &= 0xfff80000; |
| 755 | |
| 756 | intel_private.registers = ioremap(reg_addr, KB(64)); |
| 757 | if (!intel_private.registers) |
| 758 | return -ENOMEM; |
| 759 | |
| 760 | intel_private.gtt_bus_addr = reg_addr + I810_PTE_BASE; |
| 761 | |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 762 | return 0; |
| 763 | } |
| 764 | |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 765 | static int intel_fake_agp_create_gatt_table(struct agp_bridge_data *bridge) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 766 | { |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 767 | agp_bridge->gatt_table_real = NULL; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 768 | agp_bridge->gatt_table = NULL; |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 769 | agp_bridge->gatt_bus_addr = 0; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 770 | |
| 771 | return 0; |
| 772 | } |
| 773 | |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 774 | static int intel_fake_agp_free_gatt_table(struct agp_bridge_data *bridge) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 775 | { |
| 776 | return 0; |
| 777 | } |
| 778 | |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 779 | static int intel_fake_agp_configure(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 780 | { |
Chris Wilson | e380f60 | 2010-10-29 18:11:26 +0100 | [diff] [blame] | 781 | if (!intel_enable_gtt()) |
| 782 | return -EIO; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 783 | |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 784 | intel_private.clear_fake_agp = true; |
Ben Widawsky | e5c6537 | 2013-01-18 12:30:34 -0800 | [diff] [blame^] | 785 | agp_bridge->gart_bus_addr = intel_private.gma_bus_addr; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 786 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 787 | return 0; |
| 788 | } |
| 789 | |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 790 | static bool i830_check_flags(unsigned int flags) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 791 | { |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 792 | switch (flags) { |
| 793 | case 0: |
| 794 | case AGP_PHYS_MEMORY: |
| 795 | case AGP_USER_CACHED_MEMORY: |
| 796 | case AGP_USER_MEMORY: |
| 797 | return true; |
| 798 | } |
| 799 | |
| 800 | return false; |
| 801 | } |
| 802 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 803 | void intel_gtt_insert_sg_entries(struct sg_table *st, |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 804 | unsigned int pg_start, |
| 805 | unsigned int flags) |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 806 | { |
| 807 | struct scatterlist *sg; |
| 808 | unsigned int len, m; |
| 809 | int i, j; |
| 810 | |
| 811 | j = pg_start; |
| 812 | |
| 813 | /* sg may merge pages, but we have to separate |
| 814 | * per-page addr for GTT */ |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 815 | for_each_sg(st->sgl, sg, st->nents, i) { |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 816 | len = sg_dma_len(sg) >> PAGE_SHIFT; |
| 817 | for (m = 0; m < len; m++) { |
| 818 | dma_addr_t addr = sg_dma_address(sg) + (m << PAGE_SHIFT); |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 819 | intel_private.driver->write_entry(addr, j, flags); |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 820 | j++; |
| 821 | } |
| 822 | } |
| 823 | readl(intel_private.gtt+j-1); |
| 824 | } |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 825 | EXPORT_SYMBOL(intel_gtt_insert_sg_entries); |
| 826 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 827 | static void intel_gtt_insert_pages(unsigned int first_entry, |
| 828 | unsigned int num_entries, |
| 829 | struct page **pages, |
| 830 | unsigned int flags) |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 831 | { |
| 832 | int i, j; |
| 833 | |
| 834 | for (i = 0, j = first_entry; i < num_entries; i++, j++) { |
| 835 | dma_addr_t addr = page_to_phys(pages[i]); |
| 836 | intel_private.driver->write_entry(addr, |
| 837 | j, flags); |
| 838 | } |
| 839 | readl(intel_private.gtt+j-1); |
| 840 | } |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 841 | |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 842 | static int intel_fake_agp_insert_entries(struct agp_memory *mem, |
| 843 | off_t pg_start, int type) |
| 844 | { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 845 | int ret = -EINVAL; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 846 | |
Chris Wilson | bee4a18 | 2011-01-21 10:54:32 +0000 | [diff] [blame] | 847 | if (intel_private.clear_fake_agp) { |
| 848 | int start = intel_private.base.stolen_size / PAGE_SIZE; |
| 849 | int end = intel_private.base.gtt_mappable_entries; |
| 850 | intel_gtt_clear_range(start, end - start); |
| 851 | intel_private.clear_fake_agp = false; |
| 852 | } |
| 853 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 854 | if (INTEL_GTT_GEN == 1 && type == AGP_DCACHE_MEMORY) |
| 855 | return i810_insert_dcache_entries(mem, pg_start, type); |
| 856 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 857 | if (mem->page_count == 0) |
| 858 | goto out; |
| 859 | |
Chris Wilson | c64f7ba | 2010-11-23 14:24:24 +0000 | [diff] [blame] | 860 | if (pg_start + mem->page_count > intel_private.base.gtt_total_entries) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 861 | goto out_err; |
| 862 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 863 | if (type != mem->type) |
| 864 | goto out_err; |
| 865 | |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 866 | if (!intel_private.driver->check_flags(type)) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 867 | goto out_err; |
| 868 | |
| 869 | if (!mem->is_flushed) |
| 870 | global_cache_flush(); |
| 871 | |
Ben Widawsky | 8d2e630 | 2013-01-18 12:30:33 -0800 | [diff] [blame] | 872 | if (intel_private.needs_dmar) { |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 873 | struct sg_table st; |
| 874 | |
| 875 | ret = intel_gtt_map_memory(mem->pages, mem->page_count, &st); |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 876 | if (ret != 0) |
| 877 | return ret; |
| 878 | |
Chris Wilson | 9da3da6 | 2012-06-01 15:20:22 +0100 | [diff] [blame] | 879 | intel_gtt_insert_sg_entries(&st, pg_start, type); |
| 880 | mem->sg_list = st.sgl; |
| 881 | mem->num_sg = st.nents; |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 882 | } else |
| 883 | intel_gtt_insert_pages(pg_start, mem->page_count, mem->pages, |
| 884 | type); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 885 | |
| 886 | out: |
| 887 | ret = 0; |
| 888 | out_err: |
| 889 | mem->is_flushed = true; |
| 890 | return ret; |
| 891 | } |
| 892 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 893 | void intel_gtt_clear_range(unsigned int first_entry, unsigned int num_entries) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 894 | { |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 895 | unsigned int i; |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 896 | |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 897 | for (i = first_entry; i < (first_entry + num_entries); i++) { |
Ben Widawsky | 9c61a32 | 2013-01-18 12:30:32 -0800 | [diff] [blame] | 898 | intel_private.driver->write_entry(intel_private.scratch_page_dma, |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 899 | i, 0); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 900 | } |
Daniel Vetter | fdfb58a | 2010-08-29 00:15:03 +0200 | [diff] [blame] | 901 | readl(intel_private.gtt+i-1); |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 902 | } |
| 903 | EXPORT_SYMBOL(intel_gtt_clear_range); |
| 904 | |
| 905 | static int intel_fake_agp_remove_entries(struct agp_memory *mem, |
| 906 | off_t pg_start, int type) |
| 907 | { |
| 908 | if (mem->page_count == 0) |
| 909 | return 0; |
| 910 | |
Dave Airlie | d15eda5 | 2011-01-12 11:39:48 +1000 | [diff] [blame] | 911 | intel_gtt_clear_range(pg_start, mem->page_count); |
| 912 | |
Ben Widawsky | 8d2e630 | 2013-01-18 12:30:33 -0800 | [diff] [blame] | 913 | if (intel_private.needs_dmar) { |
Daniel Vetter | 4080775 | 2010-11-06 11:18:58 +0100 | [diff] [blame] | 914 | intel_gtt_unmap_memory(mem->sg_list, mem->num_sg); |
| 915 | mem->sg_list = NULL; |
| 916 | mem->num_sg = 0; |
| 917 | } |
| 918 | |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 919 | return 0; |
| 920 | } |
| 921 | |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 922 | static struct agp_memory *intel_fake_agp_alloc_by_type(size_t pg_count, |
| 923 | int type) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 924 | { |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 925 | struct agp_memory *new; |
| 926 | |
| 927 | if (type == AGP_DCACHE_MEMORY && INTEL_GTT_GEN == 1) { |
| 928 | if (pg_count != intel_private.num_dcache_entries) |
| 929 | return NULL; |
| 930 | |
| 931 | new = agp_create_memory(1); |
| 932 | if (new == NULL) |
| 933 | return NULL; |
| 934 | |
| 935 | new->type = AGP_DCACHE_MEMORY; |
| 936 | new->page_count = pg_count; |
| 937 | new->num_scratch_pages = 0; |
| 938 | agp_free_page_array(new); |
| 939 | return new; |
| 940 | } |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 941 | if (type == AGP_PHYS_MEMORY) |
| 942 | return alloc_agpphysmem_i8xx(pg_count, type); |
| 943 | /* always return NULL for other allocation types for now */ |
| 944 | return NULL; |
| 945 | } |
| 946 | |
| 947 | static int intel_alloc_chipset_flush_resource(void) |
| 948 | { |
| 949 | int ret; |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 950 | ret = pci_bus_alloc_resource(intel_private.bridge_dev->bus, &intel_private.ifp_resource, PAGE_SIZE, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 951 | PAGE_SIZE, PCIBIOS_MIN_MEM, 0, |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 952 | pcibios_align_resource, intel_private.bridge_dev); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 953 | |
| 954 | return ret; |
| 955 | } |
| 956 | |
| 957 | static void intel_i915_setup_chipset_flush(void) |
| 958 | { |
| 959 | int ret; |
| 960 | u32 temp; |
| 961 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 962 | pci_read_config_dword(intel_private.bridge_dev, I915_IFPADDR, &temp); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 963 | if (!(temp & 0x1)) { |
| 964 | intel_alloc_chipset_flush_resource(); |
| 965 | intel_private.resource_valid = 1; |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 966 | pci_write_config_dword(intel_private.bridge_dev, I915_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 967 | } else { |
| 968 | temp &= ~1; |
| 969 | |
| 970 | intel_private.resource_valid = 1; |
| 971 | intel_private.ifp_resource.start = temp; |
| 972 | intel_private.ifp_resource.end = temp + PAGE_SIZE; |
| 973 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); |
| 974 | /* some BIOSes reserve this area in a pnp some don't */ |
| 975 | if (ret) |
| 976 | intel_private.resource_valid = 0; |
| 977 | } |
| 978 | } |
| 979 | |
| 980 | static void intel_i965_g33_setup_chipset_flush(void) |
| 981 | { |
| 982 | u32 temp_hi, temp_lo; |
| 983 | int ret; |
| 984 | |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 985 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, &temp_hi); |
| 986 | pci_read_config_dword(intel_private.bridge_dev, I965_IFPADDR, &temp_lo); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 987 | |
| 988 | if (!(temp_lo & 0x1)) { |
| 989 | |
| 990 | intel_alloc_chipset_flush_resource(); |
| 991 | |
| 992 | intel_private.resource_valid = 1; |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 993 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR + 4, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 994 | upper_32_bits(intel_private.ifp_resource.start)); |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 995 | pci_write_config_dword(intel_private.bridge_dev, I965_IFPADDR, (intel_private.ifp_resource.start & 0xffffffff) | 0x1); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 996 | } else { |
| 997 | u64 l64; |
| 998 | |
| 999 | temp_lo &= ~0x1; |
| 1000 | l64 = ((u64)temp_hi << 32) | temp_lo; |
| 1001 | |
| 1002 | intel_private.resource_valid = 1; |
| 1003 | intel_private.ifp_resource.start = l64; |
| 1004 | intel_private.ifp_resource.end = l64 + PAGE_SIZE; |
| 1005 | ret = request_resource(&iomem_resource, &intel_private.ifp_resource); |
| 1006 | /* some BIOSes reserve this area in a pnp some don't */ |
| 1007 | if (ret) |
| 1008 | intel_private.resource_valid = 0; |
| 1009 | } |
| 1010 | } |
| 1011 | |
| 1012 | static void intel_i9xx_setup_flush(void) |
| 1013 | { |
| 1014 | /* return if already configured */ |
| 1015 | if (intel_private.ifp_resource.start) |
| 1016 | return; |
| 1017 | |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1018 | if (INTEL_GTT_GEN == 6) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1019 | return; |
| 1020 | |
| 1021 | /* setup a resource for this object */ |
| 1022 | intel_private.ifp_resource.name = "Intel Flush Page"; |
| 1023 | intel_private.ifp_resource.flags = IORESOURCE_MEM; |
| 1024 | |
| 1025 | /* Setup chipset flush for 915 */ |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1026 | if (IS_G33 || INTEL_GTT_GEN >= 4) { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1027 | intel_i965_g33_setup_chipset_flush(); |
| 1028 | } else { |
| 1029 | intel_i915_setup_chipset_flush(); |
| 1030 | } |
| 1031 | |
Chris Wilson | df51e7a | 2010-09-04 14:57:27 +0100 | [diff] [blame] | 1032 | if (intel_private.ifp_resource.start) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1033 | intel_private.i9xx_flush_page = ioremap_nocache(intel_private.ifp_resource.start, PAGE_SIZE); |
Chris Wilson | df51e7a | 2010-09-04 14:57:27 +0100 | [diff] [blame] | 1034 | if (!intel_private.i9xx_flush_page) |
| 1035 | dev_err(&intel_private.pcidev->dev, |
| 1036 | "can't ioremap flush page - no chipset flushing\n"); |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1037 | } |
| 1038 | |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1039 | static void i9xx_cleanup(void) |
| 1040 | { |
| 1041 | if (intel_private.i9xx_flush_page) |
| 1042 | iounmap(intel_private.i9xx_flush_page); |
| 1043 | if (intel_private.resource_valid) |
| 1044 | release_resource(&intel_private.ifp_resource); |
| 1045 | intel_private.ifp_resource.start = 0; |
| 1046 | intel_private.resource_valid = 0; |
| 1047 | } |
| 1048 | |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1049 | static void i9xx_chipset_flush(void) |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1050 | { |
| 1051 | if (intel_private.i9xx_flush_page) |
| 1052 | writel(1, intel_private.i9xx_flush_page); |
| 1053 | } |
| 1054 | |
Chris Wilson | 71f4566 | 2010-12-14 11:29:23 +0000 | [diff] [blame] | 1055 | static void i965_write_entry(dma_addr_t addr, |
| 1056 | unsigned int entry, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1057 | unsigned int flags) |
| 1058 | { |
Chris Wilson | 71f4566 | 2010-12-14 11:29:23 +0000 | [diff] [blame] | 1059 | u32 pte_flags; |
| 1060 | |
| 1061 | pte_flags = I810_PTE_VALID; |
| 1062 | if (flags == AGP_USER_CACHED_MEMORY) |
| 1063 | pte_flags |= I830_PTE_SYSTEM_CACHED; |
| 1064 | |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1065 | /* Shift high bits down */ |
| 1066 | addr |= (addr >> 28) & 0xf0; |
Chris Wilson | 71f4566 | 2010-12-14 11:29:23 +0000 | [diff] [blame] | 1067 | writel(addr | pte_flags, intel_private.gtt + entry); |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1068 | } |
| 1069 | |
Ben Widawsky | 5c04228 | 2011-10-17 15:51:55 -0700 | [diff] [blame] | 1070 | |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1071 | static int i9xx_setup(void) |
| 1072 | { |
Ben Widawsky | 009946f | 2012-11-04 09:21:29 -0800 | [diff] [blame] | 1073 | u32 reg_addr, gtt_addr; |
Jesse Barnes | 4b60d29 | 2012-03-28 13:39:33 -0700 | [diff] [blame] | 1074 | int size = KB(512); |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1075 | |
| 1076 | pci_read_config_dword(intel_private.pcidev, I915_MMADDR, ®_addr); |
| 1077 | |
| 1078 | reg_addr &= 0xfff80000; |
| 1079 | |
Jesse Barnes | 4b60d29 | 2012-03-28 13:39:33 -0700 | [diff] [blame] | 1080 | intel_private.registers = ioremap(reg_addr, size); |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1081 | if (!intel_private.registers) |
| 1082 | return -ENOMEM; |
| 1083 | |
Ben Widawsky | 009946f | 2012-11-04 09:21:29 -0800 | [diff] [blame] | 1084 | switch (INTEL_GTT_GEN) { |
| 1085 | case 3: |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1086 | pci_read_config_dword(intel_private.pcidev, |
| 1087 | I915_PTEADDR, >t_addr); |
| 1088 | intel_private.gtt_bus_addr = gtt_addr; |
Ben Widawsky | 009946f | 2012-11-04 09:21:29 -0800 | [diff] [blame] | 1089 | break; |
| 1090 | case 5: |
| 1091 | intel_private.gtt_bus_addr = reg_addr + MB(2); |
| 1092 | break; |
| 1093 | default: |
| 1094 | intel_private.gtt_bus_addr = reg_addr + KB(512); |
| 1095 | break; |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1096 | } |
| 1097 | |
| 1098 | intel_i9xx_setup_flush(); |
| 1099 | |
| 1100 | return 0; |
| 1101 | } |
| 1102 | |
Daniel Vetter | e9b1cc8 | 2010-09-12 00:29:26 +0200 | [diff] [blame] | 1103 | static const struct agp_bridge_driver intel_fake_agp_driver = { |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1104 | .owner = THIS_MODULE, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1105 | .size_type = FIXED_APER_SIZE, |
Chris Wilson | 9e76e7b | 2010-09-14 12:12:11 +0100 | [diff] [blame] | 1106 | .aperture_sizes = intel_fake_agp_sizes, |
| 1107 | .num_aperture_sizes = ARRAY_SIZE(intel_fake_agp_sizes), |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1108 | .configure = intel_fake_agp_configure, |
Daniel Vetter | 3e921f9 | 2010-08-27 15:33:26 +0200 | [diff] [blame] | 1109 | .fetch_size = intel_fake_agp_fetch_size, |
Daniel Vetter | fdfb58a | 2010-08-29 00:15:03 +0200 | [diff] [blame] | 1110 | .cleanup = intel_gtt_cleanup, |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1111 | .agp_enable = intel_fake_agp_enable, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1112 | .cache_flush = global_cache_flush, |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 1113 | .create_gatt_table = intel_fake_agp_create_gatt_table, |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1114 | .free_gatt_table = intel_fake_agp_free_gatt_table, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1115 | .insert_memory = intel_fake_agp_insert_entries, |
| 1116 | .remove_memory = intel_fake_agp_remove_entries, |
Daniel Vetter | ffdd751 | 2010-08-27 17:51:29 +0200 | [diff] [blame] | 1117 | .alloc_by_type = intel_fake_agp_alloc_by_type, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1118 | .free_by_type = intel_i810_free_by_type, |
| 1119 | .agp_alloc_page = agp_generic_alloc_page, |
| 1120 | .agp_alloc_pages = agp_generic_alloc_pages, |
| 1121 | .agp_destroy_page = agp_generic_destroy_page, |
| 1122 | .agp_destroy_pages = agp_generic_destroy_pages, |
Daniel Vetter | f51b766 | 2010-04-14 00:29:52 +0200 | [diff] [blame] | 1123 | }; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1124 | |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1125 | static const struct intel_gtt_driver i81x_gtt_driver = { |
| 1126 | .gen = 1, |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 1127 | .has_pgtbl_enable = 1, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1128 | .dma_mask_size = 32, |
Daniel Vetter | 820647b | 2010-11-05 13:30:14 +0100 | [diff] [blame] | 1129 | .setup = i810_setup, |
| 1130 | .cleanup = i810_cleanup, |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1131 | .check_flags = i830_check_flags, |
| 1132 | .write_entry = i810_write_entry, |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1133 | }; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1134 | static const struct intel_gtt_driver i8xx_gtt_driver = { |
| 1135 | .gen = 2, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 1136 | .has_pgtbl_enable = 1, |
Daniel Vetter | 7380042 | 2010-08-29 17:29:50 +0200 | [diff] [blame] | 1137 | .setup = i830_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1138 | .cleanup = i830_cleanup, |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 1139 | .write_entry = i830_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1140 | .dma_mask_size = 32, |
Daniel Vetter | 5cbecaf | 2010-09-11 21:31:04 +0200 | [diff] [blame] | 1141 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1142 | .chipset_flush = i830_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1143 | }; |
| 1144 | static const struct intel_gtt_driver i915_gtt_driver = { |
| 1145 | .gen = 3, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 1146 | .has_pgtbl_enable = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1147 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1148 | .cleanup = i9xx_cleanup, |
Daniel Vetter | 351bb27 | 2010-09-07 22:41:04 +0200 | [diff] [blame] | 1149 | /* i945 is the last gpu to need phys mem (for overlay and cursors). */ |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1150 | .write_entry = i830_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1151 | .dma_mask_size = 32, |
Daniel Vetter | fefaa70 | 2010-09-11 22:12:11 +0200 | [diff] [blame] | 1152 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1153 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1154 | }; |
| 1155 | static const struct intel_gtt_driver g33_gtt_driver = { |
| 1156 | .gen = 3, |
| 1157 | .is_g33 = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1158 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1159 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1160 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1161 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1162 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1163 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1164 | }; |
| 1165 | static const struct intel_gtt_driver pineview_gtt_driver = { |
| 1166 | .gen = 3, |
| 1167 | .is_pineview = 1, .is_g33 = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1168 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1169 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1170 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1171 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1172 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1173 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1174 | }; |
| 1175 | static const struct intel_gtt_driver i965_gtt_driver = { |
| 1176 | .gen = 4, |
Chris Wilson | 100519e | 2010-10-31 10:37:02 +0000 | [diff] [blame] | 1177 | .has_pgtbl_enable = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1178 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1179 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1180 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1181 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1182 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1183 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1184 | }; |
| 1185 | static const struct intel_gtt_driver g4x_gtt_driver = { |
| 1186 | .gen = 5, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1187 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1188 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1189 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1190 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1191 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1192 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1193 | }; |
| 1194 | static const struct intel_gtt_driver ironlake_gtt_driver = { |
| 1195 | .gen = 5, |
| 1196 | .is_ironlake = 1, |
Daniel Vetter | 2d2430c | 2010-08-29 17:35:30 +0200 | [diff] [blame] | 1197 | .setup = i9xx_setup, |
Daniel Vetter | ae83dd5 | 2010-09-12 17:11:15 +0200 | [diff] [blame] | 1198 | .cleanup = i9xx_cleanup, |
Daniel Vetter | a696359 | 2010-09-11 14:01:43 +0200 | [diff] [blame] | 1199 | .write_entry = i965_write_entry, |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1200 | .dma_mask_size = 36, |
Daniel Vetter | 450f2b3 | 2010-09-11 23:48:25 +0200 | [diff] [blame] | 1201 | .check_flags = i830_check_flags, |
Daniel Vetter | 1b263f2 | 2010-09-12 00:27:24 +0200 | [diff] [blame] | 1202 | .chipset_flush = i9xx_chipset_flush, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1203 | }; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1204 | |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1205 | /* Table to describe Intel GMCH and AGP/PCIE GART drivers. At least one of |
| 1206 | * driver and gmch_driver must be non-null, and find_gmch will determine |
| 1207 | * which one should be used if a gmch_chip_id is present. |
| 1208 | */ |
| 1209 | static const struct intel_gtt_driver_description { |
| 1210 | unsigned int gmch_chip_id; |
| 1211 | char *name; |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1212 | const struct intel_gtt_driver *gtt_driver; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1213 | } intel_gtt_chipsets[] = { |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1214 | { PCI_DEVICE_ID_INTEL_82810_IG1, "i810", |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1215 | &i81x_gtt_driver}, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1216 | { PCI_DEVICE_ID_INTEL_82810_IG3, "i810", |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1217 | &i81x_gtt_driver}, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1218 | { PCI_DEVICE_ID_INTEL_82810E_IG, "i810", |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1219 | &i81x_gtt_driver}, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1220 | { PCI_DEVICE_ID_INTEL_82815_CGC, "i815", |
Daniel Vetter | bdd3072 | 2010-09-12 12:34:44 +0200 | [diff] [blame] | 1221 | &i81x_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1222 | { PCI_DEVICE_ID_INTEL_82830_CGC, "830M", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1223 | &i8xx_gtt_driver}, |
Oswald Buddenhagen | 53371ed | 2010-06-19 23:08:37 +0200 | [diff] [blame] | 1224 | { PCI_DEVICE_ID_INTEL_82845G_IG, "845G", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1225 | &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1226 | { PCI_DEVICE_ID_INTEL_82854_IG, "854", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1227 | &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1228 | { PCI_DEVICE_ID_INTEL_82855GM_IG, "855GM", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1229 | &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1230 | { PCI_DEVICE_ID_INTEL_82865_IG, "865", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1231 | &i8xx_gtt_driver}, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1232 | { PCI_DEVICE_ID_INTEL_E7221_IG, "E7221 (i915)", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1233 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1234 | { PCI_DEVICE_ID_INTEL_82915G_IG, "915G", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1235 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1236 | { PCI_DEVICE_ID_INTEL_82915GM_IG, "915GM", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1237 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1238 | { PCI_DEVICE_ID_INTEL_82945G_IG, "945G", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1239 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1240 | { PCI_DEVICE_ID_INTEL_82945GM_IG, "945GM", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1241 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1242 | { PCI_DEVICE_ID_INTEL_82945GME_IG, "945GME", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1243 | &i915_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1244 | { PCI_DEVICE_ID_INTEL_82946GZ_IG, "946GZ", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1245 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1246 | { PCI_DEVICE_ID_INTEL_82G35_IG, "G35", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1247 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1248 | { PCI_DEVICE_ID_INTEL_82965Q_IG, "965Q", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1249 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1250 | { PCI_DEVICE_ID_INTEL_82965G_IG, "965G", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1251 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1252 | { PCI_DEVICE_ID_INTEL_82965GM_IG, "965GM", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1253 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1254 | { PCI_DEVICE_ID_INTEL_82965GME_IG, "965GME/GLE", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1255 | &i965_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1256 | { PCI_DEVICE_ID_INTEL_G33_IG, "G33", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1257 | &g33_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1258 | { PCI_DEVICE_ID_INTEL_Q35_IG, "Q35", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1259 | &g33_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1260 | { PCI_DEVICE_ID_INTEL_Q33_IG, "Q33", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1261 | &g33_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1262 | { PCI_DEVICE_ID_INTEL_PINEVIEW_M_IG, "GMA3150", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1263 | &pineview_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1264 | { PCI_DEVICE_ID_INTEL_PINEVIEW_IG, "GMA3150", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1265 | &pineview_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1266 | { PCI_DEVICE_ID_INTEL_GM45_IG, "GM45", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1267 | &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1268 | { PCI_DEVICE_ID_INTEL_EAGLELAKE_IG, "Eaglelake", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1269 | &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1270 | { PCI_DEVICE_ID_INTEL_Q45_IG, "Q45/Q43", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1271 | &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1272 | { PCI_DEVICE_ID_INTEL_G45_IG, "G45/G43", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1273 | &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1274 | { PCI_DEVICE_ID_INTEL_B43_IG, "B43", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1275 | &g4x_gtt_driver }, |
Chris Wilson | e9e5f8e | 2010-09-21 11:19:32 +0100 | [diff] [blame] | 1276 | { PCI_DEVICE_ID_INTEL_B43_1_IG, "B43", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1277 | &g4x_gtt_driver }, |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1278 | { PCI_DEVICE_ID_INTEL_G41_IG, "G41", |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1279 | &g4x_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1280 | { PCI_DEVICE_ID_INTEL_IRONLAKE_D_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1281 | "HD Graphics", &ironlake_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1282 | { PCI_DEVICE_ID_INTEL_IRONLAKE_M_IG, |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1283 | "HD Graphics", &ironlake_gtt_driver }, |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1284 | { 0, NULL, NULL } |
| 1285 | }; |
| 1286 | |
| 1287 | static int find_gmch(u16 device) |
| 1288 | { |
| 1289 | struct pci_dev *gmch_device; |
| 1290 | |
| 1291 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, device, NULL); |
| 1292 | if (gmch_device && PCI_FUNC(gmch_device->devfn) != 0) { |
| 1293 | gmch_device = pci_get_device(PCI_VENDOR_ID_INTEL, |
| 1294 | device, gmch_device); |
| 1295 | } |
| 1296 | |
| 1297 | if (!gmch_device) |
| 1298 | return 0; |
| 1299 | |
| 1300 | intel_private.pcidev = gmch_device; |
| 1301 | return 1; |
| 1302 | } |
| 1303 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1304 | int intel_gmch_probe(struct pci_dev *bridge_pdev, struct pci_dev *gpu_pdev, |
| 1305 | struct agp_bridge_data *bridge) |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1306 | { |
| 1307 | int i, mask; |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1308 | |
| 1309 | /* |
| 1310 | * Can be called from the fake agp driver but also directly from |
| 1311 | * drm/i915.ko. Hence we need to check whether everything is set up |
| 1312 | * already. |
| 1313 | */ |
| 1314 | if (intel_private.driver) { |
| 1315 | intel_private.refcount++; |
| 1316 | return 1; |
| 1317 | } |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1318 | |
| 1319 | for (i = 0; intel_gtt_chipsets[i].name != NULL; i++) { |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1320 | if (gpu_pdev) { |
| 1321 | if (gpu_pdev->device == |
| 1322 | intel_gtt_chipsets[i].gmch_chip_id) { |
| 1323 | intel_private.pcidev = pci_dev_get(gpu_pdev); |
| 1324 | intel_private.driver = |
| 1325 | intel_gtt_chipsets[i].gtt_driver; |
| 1326 | |
| 1327 | break; |
| 1328 | } |
| 1329 | } else if (find_gmch(intel_gtt_chipsets[i].gmch_chip_id)) { |
Daniel Vetter | 625dd9d | 2010-11-04 20:07:57 +0100 | [diff] [blame] | 1330 | intel_private.driver = |
Daniel Vetter | 1a997ff | 2010-09-08 21:18:53 +0200 | [diff] [blame] | 1331 | intel_gtt_chipsets[i].gtt_driver; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1332 | break; |
| 1333 | } |
| 1334 | } |
| 1335 | |
Daniel Vetter | ff26860 | 2010-11-05 15:43:35 +0100 | [diff] [blame] | 1336 | if (!intel_private.driver) |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1337 | return 0; |
| 1338 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1339 | intel_private.refcount++; |
| 1340 | |
Daniel Vetter | 7e8f630 | 2012-06-07 15:55:58 +0200 | [diff] [blame] | 1341 | if (bridge) { |
| 1342 | bridge->driver = &intel_fake_agp_driver; |
| 1343 | bridge->dev_private_data = &intel_private; |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1344 | bridge->dev = bridge_pdev; |
Daniel Vetter | 7e8f630 | 2012-06-07 15:55:58 +0200 | [diff] [blame] | 1345 | } |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1346 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1347 | intel_private.bridge_dev = pci_dev_get(bridge_pdev); |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1348 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1349 | dev_info(&bridge_pdev->dev, "Intel %s Chipset\n", intel_gtt_chipsets[i].name); |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1350 | |
Daniel Vetter | 22533b4 | 2010-09-12 16:38:55 +0200 | [diff] [blame] | 1351 | mask = intel_private.driver->dma_mask_size; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1352 | if (pci_set_dma_mask(intel_private.pcidev, DMA_BIT_MASK(mask))) |
| 1353 | dev_err(&intel_private.pcidev->dev, |
| 1354 | "set gfx device dma mask %d-bit failed!\n", mask); |
| 1355 | else |
| 1356 | pci_set_consistent_dma_mask(intel_private.pcidev, |
| 1357 | DMA_BIT_MASK(mask)); |
| 1358 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1359 | if (intel_gtt_init() != 0) { |
| 1360 | intel_gmch_remove(); |
| 1361 | |
Daniel Vetter | 3b15a9d | 2010-08-29 14:18:49 +0200 | [diff] [blame] | 1362 | return 0; |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1363 | } |
Daniel Vetter | 1784a5f | 2010-09-08 21:01:04 +0200 | [diff] [blame] | 1364 | |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1365 | return 1; |
| 1366 | } |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 1367 | EXPORT_SYMBOL(intel_gmch_probe); |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1368 | |
Ben Widawsky | e76e9ae | 2012-11-04 09:21:27 -0800 | [diff] [blame] | 1369 | struct intel_gtt *intel_gtt_get(void) |
Daniel Vetter | 1996675 | 2010-09-06 20:08:44 +0200 | [diff] [blame] | 1370 | { |
| 1371 | return &intel_private.base; |
| 1372 | } |
| 1373 | EXPORT_SYMBOL(intel_gtt_get); |
| 1374 | |
Daniel Vetter | 40ce657 | 2010-11-05 18:12:18 +0100 | [diff] [blame] | 1375 | void intel_gtt_chipset_flush(void) |
| 1376 | { |
| 1377 | if (intel_private.driver->chipset_flush) |
| 1378 | intel_private.driver->chipset_flush(); |
| 1379 | } |
| 1380 | EXPORT_SYMBOL(intel_gtt_chipset_flush); |
| 1381 | |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1382 | void intel_gmch_remove(void) |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1383 | { |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1384 | if (--intel_private.refcount) |
| 1385 | return; |
| 1386 | |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1387 | if (intel_private.pcidev) |
| 1388 | pci_dev_put(intel_private.pcidev); |
Daniel Vetter | d7cca2f | 2010-08-24 23:06:19 +0200 | [diff] [blame] | 1389 | if (intel_private.bridge_dev) |
| 1390 | pci_dev_put(intel_private.bridge_dev); |
Daniel Vetter | 14be93d | 2012-06-08 15:55:40 +0200 | [diff] [blame] | 1391 | intel_private.driver = NULL; |
Daniel Vetter | 02c026c | 2010-08-24 19:39:48 +0200 | [diff] [blame] | 1392 | } |
Daniel Vetter | e2404e7 | 2010-09-08 17:29:51 +0200 | [diff] [blame] | 1393 | EXPORT_SYMBOL(intel_gmch_remove); |
| 1394 | |
| 1395 | MODULE_AUTHOR("Dave Jones <davej@redhat.com>"); |
| 1396 | MODULE_LICENSE("GPL and additional rights"); |