Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1 | /* |
| 2 | * Driver for Microchip MRF24J40 802.15.4 Wireless-PAN Networking controller |
| 3 | * |
| 4 | * Copyright (C) 2012 Alan Ott <alan@signal11.us> |
| 5 | * Signal 11 Software |
| 6 | * |
| 7 | * This program is free software; you can redistribute it and/or modify |
| 8 | * it under the terms of the GNU General Public License as published by |
| 9 | * the Free Software Foundation; either version 2 of the License, or |
| 10 | * (at your option) any later version. |
| 11 | * |
| 12 | * This program is distributed in the hope that it will be useful, |
| 13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 15 | * GNU General Public License for more details. |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 16 | */ |
| 17 | |
| 18 | #include <linux/spi/spi.h> |
| 19 | #include <linux/interrupt.h> |
| 20 | #include <linux/module.h> |
Alexander Aring | b015679 | 2015-09-21 11:24:30 +0200 | [diff] [blame] | 21 | #include <linux/regmap.h> |
Alexander Aring | 4ca24ac | 2014-10-25 09:41:04 +0200 | [diff] [blame] | 22 | #include <linux/ieee802154.h> |
Alexander Aring | afaf7fde | 2015-09-21 11:24:42 +0200 | [diff] [blame] | 23 | #include <linux/irq.h> |
Alexander Aring | 5ad60d3 | 2014-10-25 09:41:02 +0200 | [diff] [blame] | 24 | #include <net/cfg802154.h> |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 25 | #include <net/mac802154.h> |
| 26 | |
| 27 | /* MRF24J40 Short Address Registers */ |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 28 | #define REG_RXMCR 0x00 /* Receive MAC control */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 29 | #define BIT_PROMI BIT(0) |
| 30 | #define BIT_ERRPKT BIT(1) |
| 31 | #define BIT_NOACKRSP BIT(5) |
| 32 | #define BIT_PANCOORD BIT(3) |
| 33 | |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 34 | #define REG_PANIDL 0x01 /* PAN ID (low) */ |
| 35 | #define REG_PANIDH 0x02 /* PAN ID (high) */ |
| 36 | #define REG_SADRL 0x03 /* Short address (low) */ |
| 37 | #define REG_SADRH 0x04 /* Short address (high) */ |
| 38 | #define REG_EADR0 0x05 /* Long address (low) (high is EADR7) */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 39 | #define REG_EADR1 0x06 |
| 40 | #define REG_EADR2 0x07 |
| 41 | #define REG_EADR3 0x08 |
| 42 | #define REG_EADR4 0x09 |
| 43 | #define REG_EADR5 0x0A |
| 44 | #define REG_EADR6 0x0B |
| 45 | #define REG_EADR7 0x0C |
| 46 | #define REG_RXFLUSH 0x0D |
| 47 | #define REG_ORDER 0x10 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 48 | #define REG_TXMCR 0x11 /* Transmit MAC control */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 49 | #define TXMCR_MIN_BE_SHIFT 3 |
| 50 | #define TXMCR_MIN_BE_MASK 0x18 |
| 51 | #define TXMCR_CSMA_RETRIES_SHIFT 0 |
| 52 | #define TXMCR_CSMA_RETRIES_MASK 0x07 |
| 53 | |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 54 | #define REG_ACKTMOUT 0x12 |
| 55 | #define REG_ESLOTG1 0x13 |
| 56 | #define REG_SYMTICKL 0x14 |
| 57 | #define REG_SYMTICKH 0x15 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 58 | #define REG_PACON0 0x16 /* Power Amplifier Control */ |
| 59 | #define REG_PACON1 0x17 /* Power Amplifier Control */ |
| 60 | #define REG_PACON2 0x18 /* Power Amplifier Control */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 61 | #define REG_TXBCON0 0x1A |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 62 | #define REG_TXNCON 0x1B /* Transmit Normal FIFO Control */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 63 | #define BIT_TXNTRIG BIT(0) |
| 64 | #define BIT_TXNACKREQ BIT(2) |
| 65 | |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 66 | #define REG_TXG1CON 0x1C |
| 67 | #define REG_TXG2CON 0x1D |
| 68 | #define REG_ESLOTG23 0x1E |
| 69 | #define REG_ESLOTG45 0x1F |
| 70 | #define REG_ESLOTG67 0x20 |
| 71 | #define REG_TXPEND 0x21 |
| 72 | #define REG_WAKECON 0x22 |
| 73 | #define REG_FROMOFFSET 0x23 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 74 | #define REG_TXSTAT 0x24 /* TX MAC Status Register */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 75 | #define REG_TXBCON1 0x25 |
| 76 | #define REG_GATECLK 0x26 |
| 77 | #define REG_TXTIME 0x27 |
| 78 | #define REG_HSYMTMRL 0x28 |
| 79 | #define REG_HSYMTMRH 0x29 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 80 | #define REG_SOFTRST 0x2A /* Soft Reset */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 81 | #define REG_SECCON0 0x2C |
| 82 | #define REG_SECCON1 0x2D |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 83 | #define REG_TXSTBL 0x2E /* TX Stabilization */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 84 | #define REG_RXSR 0x30 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 85 | #define REG_INTSTAT 0x31 /* Interrupt Status */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 86 | #define BIT_TXNIF BIT(0) |
| 87 | #define BIT_RXIF BIT(3) |
| 88 | |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 89 | #define REG_INTCON 0x32 /* Interrupt Control */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 90 | #define BIT_TXNIE BIT(0) |
| 91 | #define BIT_RXIE BIT(3) |
| 92 | |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 93 | #define REG_GPIO 0x33 /* GPIO */ |
| 94 | #define REG_TRISGPIO 0x34 /* GPIO direction */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 95 | #define REG_SLPACK 0x35 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 96 | #define REG_RFCTL 0x36 /* RF Control Mode Register */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 97 | #define BIT_RFRST BIT(2) |
| 98 | |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 99 | #define REG_SECCR2 0x37 |
| 100 | #define REG_BBREG0 0x38 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 101 | #define REG_BBREG1 0x39 /* Baseband Registers */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 102 | #define BIT_RXDECINV BIT(2) |
| 103 | |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 104 | #define REG_BBREG2 0x3A /* */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 105 | #define BBREG2_CCA_MODE_SHIFT 6 |
| 106 | #define BBREG2_CCA_MODE_MASK 0xc0 |
| 107 | |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 108 | #define REG_BBREG3 0x3B |
| 109 | #define REG_BBREG4 0x3C |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 110 | #define REG_BBREG6 0x3E /* */ |
| 111 | #define REG_CCAEDTH 0x3F /* Energy Detection Threshold */ |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 112 | |
| 113 | /* MRF24J40 Long Address Registers */ |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 114 | #define REG_RFCON0 0x200 /* RF Control Registers */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 115 | #define RFCON0_CH_SHIFT 4 |
| 116 | #define RFCON0_CH_MASK 0xf0 |
| 117 | #define RFOPT_RECOMMEND 3 |
| 118 | |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 119 | #define REG_RFCON1 0x201 |
| 120 | #define REG_RFCON2 0x202 |
| 121 | #define REG_RFCON3 0x203 |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 122 | |
| 123 | #define TXPWRL_MASK 0xc0 |
| 124 | #define TXPWRL_SHIFT 6 |
| 125 | #define TXPWRL_30 0x3 |
| 126 | #define TXPWRL_20 0x2 |
| 127 | #define TXPWRL_10 0x1 |
| 128 | #define TXPWRL_0 0x0 |
| 129 | |
| 130 | #define TXPWRS_MASK 0x38 |
| 131 | #define TXPWRS_SHIFT 3 |
| 132 | #define TXPWRS_6_3 0x7 |
| 133 | #define TXPWRS_4_9 0x6 |
| 134 | #define TXPWRS_3_7 0x5 |
| 135 | #define TXPWRS_2_8 0x4 |
| 136 | #define TXPWRS_1_9 0x3 |
| 137 | #define TXPWRS_1_2 0x2 |
| 138 | #define TXPWRS_0_5 0x1 |
| 139 | #define TXPWRS_0 0x0 |
| 140 | |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 141 | #define REG_RFCON5 0x205 |
| 142 | #define REG_RFCON6 0x206 |
| 143 | #define REG_RFCON7 0x207 |
| 144 | #define REG_RFCON8 0x208 |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 145 | #define REG_SLPCAL0 0x209 |
| 146 | #define REG_SLPCAL1 0x20A |
| 147 | #define REG_SLPCAL2 0x20B |
| 148 | #define REG_RFSTATE 0x20F |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 149 | #define REG_RSSI 0x210 |
| 150 | #define REG_SLPCON0 0x211 /* Sleep Clock Control Registers */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 151 | #define BIT_INTEDGE BIT(1) |
| 152 | |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 153 | #define REG_SLPCON1 0x220 |
| 154 | #define REG_WAKETIMEL 0x222 /* Wake-up Time Match Value Low */ |
| 155 | #define REG_WAKETIMEH 0x223 /* Wake-up Time Match Value High */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 156 | #define REG_REMCNTL 0x224 |
| 157 | #define REG_REMCNTH 0x225 |
| 158 | #define REG_MAINCNT0 0x226 |
| 159 | #define REG_MAINCNT1 0x227 |
| 160 | #define REG_MAINCNT2 0x228 |
| 161 | #define REG_MAINCNT3 0x229 |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 162 | #define REG_TESTMODE 0x22F /* Test mode */ |
Alexander Aring | 554b494 | 2015-09-21 11:24:29 +0200 | [diff] [blame] | 163 | #define REG_ASSOEAR0 0x230 |
| 164 | #define REG_ASSOEAR1 0x231 |
| 165 | #define REG_ASSOEAR2 0x232 |
| 166 | #define REG_ASSOEAR3 0x233 |
| 167 | #define REG_ASSOEAR4 0x234 |
| 168 | #define REG_ASSOEAR5 0x235 |
| 169 | #define REG_ASSOEAR6 0x236 |
| 170 | #define REG_ASSOEAR7 0x237 |
| 171 | #define REG_ASSOSAR0 0x238 |
| 172 | #define REG_ASSOSAR1 0x239 |
| 173 | #define REG_UNONCE0 0x240 |
| 174 | #define REG_UNONCE1 0x241 |
| 175 | #define REG_UNONCE2 0x242 |
| 176 | #define REG_UNONCE3 0x243 |
| 177 | #define REG_UNONCE4 0x244 |
| 178 | #define REG_UNONCE5 0x245 |
| 179 | #define REG_UNONCE6 0x246 |
| 180 | #define REG_UNONCE7 0x247 |
| 181 | #define REG_UNONCE8 0x248 |
| 182 | #define REG_UNONCE9 0x249 |
| 183 | #define REG_UNONCE10 0x24A |
| 184 | #define REG_UNONCE11 0x24B |
| 185 | #define REG_UNONCE12 0x24C |
Alexander Aring | c9f883f | 2015-09-21 11:24:22 +0200 | [diff] [blame] | 186 | #define REG_RX_FIFO 0x300 /* Receive FIFO */ |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 187 | |
| 188 | /* Device configuration: Only channels 11-26 on page 0 are supported. */ |
| 189 | #define MRF24J40_CHAN_MIN 11 |
| 190 | #define MRF24J40_CHAN_MAX 26 |
| 191 | #define CHANNEL_MASK (((u32)1 << (MRF24J40_CHAN_MAX + 1)) \ |
| 192 | - ((u32)1 << MRF24J40_CHAN_MIN)) |
| 193 | |
| 194 | #define TX_FIFO_SIZE 128 /* From datasheet */ |
| 195 | #define RX_FIFO_SIZE 144 /* From datasheet */ |
| 196 | #define SET_CHANNEL_DELAY_US 192 /* From datasheet */ |
| 197 | |
Simon Vincent | db9e0ee | 2014-10-06 10:39:45 +0100 | [diff] [blame] | 198 | enum mrf24j40_modules { MRF24J40, MRF24J40MA, MRF24J40MC }; |
| 199 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 200 | /* Device Private Data */ |
| 201 | struct mrf24j40 { |
| 202 | struct spi_device *spi; |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 203 | struct ieee802154_hw *hw; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 204 | |
Alexander Aring | b015679 | 2015-09-21 11:24:30 +0200 | [diff] [blame] | 205 | struct regmap *regmap_short; |
| 206 | struct regmap *regmap_long; |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 207 | |
| 208 | /* for writing txfifo */ |
| 209 | struct spi_message tx_msg; |
| 210 | u8 tx_hdr_buf[2]; |
| 211 | struct spi_transfer tx_hdr_trx; |
| 212 | u8 tx_len_buf[2]; |
| 213 | struct spi_transfer tx_len_trx; |
| 214 | struct spi_transfer tx_buf_trx; |
| 215 | struct sk_buff *tx_skb; |
| 216 | |
| 217 | /* post transmit message to send frame out */ |
| 218 | struct spi_message tx_post_msg; |
| 219 | u8 tx_post_buf[2]; |
| 220 | struct spi_transfer tx_post_trx; |
| 221 | |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 222 | /* for protect/unprotect/read length rxfifo */ |
| 223 | struct spi_message rx_msg; |
| 224 | u8 rx_buf[3]; |
| 225 | struct spi_transfer rx_trx; |
| 226 | |
| 227 | /* receive handling */ |
| 228 | struct spi_message rx_buf_msg; |
| 229 | u8 rx_addr_buf[2]; |
| 230 | struct spi_transfer rx_addr_trx; |
| 231 | u8 rx_lqi_buf[2]; |
| 232 | struct spi_transfer rx_lqi_trx; |
| 233 | u8 rx_fifo_buf[RX_FIFO_SIZE]; |
| 234 | struct spi_transfer rx_fifo_buf_trx; |
| 235 | |
Alexander Aring | 3744161 | 2015-09-21 11:24:36 +0200 | [diff] [blame] | 236 | /* isr handling for reading intstat */ |
| 237 | struct spi_message irq_msg; |
| 238 | u8 irq_buf[2]; |
| 239 | struct spi_transfer irq_trx; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 240 | }; |
| 241 | |
Alexander Aring | b015679 | 2015-09-21 11:24:30 +0200 | [diff] [blame] | 242 | /* regmap information for short address register access */ |
| 243 | #define MRF24J40_SHORT_WRITE 0x01 |
| 244 | #define MRF24J40_SHORT_READ 0x00 |
| 245 | #define MRF24J40_SHORT_NUMREGS 0x3F |
| 246 | |
| 247 | /* regmap information for long address register access */ |
| 248 | #define MRF24J40_LONG_ACCESS 0x80 |
| 249 | #define MRF24J40_LONG_NUMREGS 0x38F |
| 250 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 251 | /* Read/Write SPI Commands for Short and Long Address registers. */ |
| 252 | #define MRF24J40_READSHORT(reg) ((reg) << 1) |
| 253 | #define MRF24J40_WRITESHORT(reg) ((reg) << 1 | 1) |
| 254 | #define MRF24J40_READLONG(reg) (1 << 15 | (reg) << 5) |
| 255 | #define MRF24J40_WRITELONG(reg) (1 << 15 | (reg) << 5 | 1 << 4) |
| 256 | |
Alan Ott | cf82dab | 2013-03-18 12:06:42 +0000 | [diff] [blame] | 257 | /* The datasheet indicates the theoretical maximum for SCK to be 10MHz */ |
| 258 | #define MAX_SPI_SPEED_HZ 10000000 |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 259 | |
| 260 | #define printdev(X) (&X->spi->dev) |
| 261 | |
Alexander Aring | b015679 | 2015-09-21 11:24:30 +0200 | [diff] [blame] | 262 | static bool |
| 263 | mrf24j40_short_reg_writeable(struct device *dev, unsigned int reg) |
| 264 | { |
| 265 | switch (reg) { |
| 266 | case REG_RXMCR: |
| 267 | case REG_PANIDL: |
| 268 | case REG_PANIDH: |
| 269 | case REG_SADRL: |
| 270 | case REG_SADRH: |
| 271 | case REG_EADR0: |
| 272 | case REG_EADR1: |
| 273 | case REG_EADR2: |
| 274 | case REG_EADR3: |
| 275 | case REG_EADR4: |
| 276 | case REG_EADR5: |
| 277 | case REG_EADR6: |
| 278 | case REG_EADR7: |
| 279 | case REG_RXFLUSH: |
| 280 | case REG_ORDER: |
| 281 | case REG_TXMCR: |
| 282 | case REG_ACKTMOUT: |
| 283 | case REG_ESLOTG1: |
| 284 | case REG_SYMTICKL: |
| 285 | case REG_SYMTICKH: |
| 286 | case REG_PACON0: |
| 287 | case REG_PACON1: |
| 288 | case REG_PACON2: |
| 289 | case REG_TXBCON0: |
| 290 | case REG_TXNCON: |
| 291 | case REG_TXG1CON: |
| 292 | case REG_TXG2CON: |
| 293 | case REG_ESLOTG23: |
| 294 | case REG_ESLOTG45: |
| 295 | case REG_ESLOTG67: |
| 296 | case REG_TXPEND: |
| 297 | case REG_WAKECON: |
| 298 | case REG_FROMOFFSET: |
| 299 | case REG_TXBCON1: |
| 300 | case REG_GATECLK: |
| 301 | case REG_TXTIME: |
| 302 | case REG_HSYMTMRL: |
| 303 | case REG_HSYMTMRH: |
| 304 | case REG_SOFTRST: |
| 305 | case REG_SECCON0: |
| 306 | case REG_SECCON1: |
| 307 | case REG_TXSTBL: |
| 308 | case REG_RXSR: |
| 309 | case REG_INTCON: |
| 310 | case REG_TRISGPIO: |
| 311 | case REG_GPIO: |
| 312 | case REG_RFCTL: |
| 313 | case REG_SLPACK: |
| 314 | case REG_BBREG0: |
| 315 | case REG_BBREG1: |
| 316 | case REG_BBREG2: |
| 317 | case REG_BBREG3: |
| 318 | case REG_BBREG4: |
| 319 | case REG_BBREG6: |
| 320 | case REG_CCAEDTH: |
| 321 | return true; |
| 322 | default: |
| 323 | return false; |
| 324 | } |
| 325 | } |
| 326 | |
| 327 | static bool |
| 328 | mrf24j40_short_reg_readable(struct device *dev, unsigned int reg) |
| 329 | { |
| 330 | bool rc; |
| 331 | |
| 332 | /* all writeable are also readable */ |
| 333 | rc = mrf24j40_short_reg_writeable(dev, reg); |
| 334 | if (rc) |
| 335 | return rc; |
| 336 | |
| 337 | /* readonly regs */ |
| 338 | switch (reg) { |
| 339 | case REG_TXSTAT: |
| 340 | case REG_INTSTAT: |
| 341 | return true; |
| 342 | default: |
| 343 | return false; |
| 344 | } |
| 345 | } |
| 346 | |
| 347 | static bool |
| 348 | mrf24j40_short_reg_volatile(struct device *dev, unsigned int reg) |
| 349 | { |
| 350 | /* can be changed during runtime */ |
| 351 | switch (reg) { |
| 352 | case REG_TXSTAT: |
| 353 | case REG_INTSTAT: |
| 354 | case REG_RXFLUSH: |
| 355 | case REG_TXNCON: |
| 356 | case REG_SOFTRST: |
| 357 | case REG_RFCTL: |
| 358 | case REG_TXBCON0: |
| 359 | case REG_TXG1CON: |
| 360 | case REG_TXG2CON: |
| 361 | case REG_TXBCON1: |
| 362 | case REG_SECCON0: |
| 363 | case REG_RXSR: |
| 364 | case REG_SLPACK: |
| 365 | case REG_SECCR2: |
| 366 | case REG_BBREG6: |
| 367 | /* use them in spi_async and regmap so it's volatile */ |
| 368 | case REG_BBREG1: |
| 369 | return true; |
| 370 | default: |
| 371 | return false; |
| 372 | } |
| 373 | } |
| 374 | |
| 375 | static bool |
| 376 | mrf24j40_short_reg_precious(struct device *dev, unsigned int reg) |
| 377 | { |
| 378 | /* don't clear irq line on read */ |
| 379 | switch (reg) { |
| 380 | case REG_INTSTAT: |
| 381 | return true; |
| 382 | default: |
| 383 | return false; |
| 384 | } |
| 385 | } |
| 386 | |
| 387 | static const struct regmap_config mrf24j40_short_regmap = { |
| 388 | .name = "mrf24j40_short", |
| 389 | .reg_bits = 7, |
| 390 | .val_bits = 8, |
| 391 | .pad_bits = 1, |
| 392 | .write_flag_mask = MRF24J40_SHORT_WRITE, |
| 393 | .read_flag_mask = MRF24J40_SHORT_READ, |
| 394 | .cache_type = REGCACHE_RBTREE, |
| 395 | .max_register = MRF24J40_SHORT_NUMREGS, |
| 396 | .writeable_reg = mrf24j40_short_reg_writeable, |
| 397 | .readable_reg = mrf24j40_short_reg_readable, |
| 398 | .volatile_reg = mrf24j40_short_reg_volatile, |
| 399 | .precious_reg = mrf24j40_short_reg_precious, |
| 400 | }; |
| 401 | |
| 402 | static bool |
| 403 | mrf24j40_long_reg_writeable(struct device *dev, unsigned int reg) |
| 404 | { |
| 405 | switch (reg) { |
| 406 | case REG_RFCON0: |
| 407 | case REG_RFCON1: |
| 408 | case REG_RFCON2: |
| 409 | case REG_RFCON3: |
| 410 | case REG_RFCON5: |
| 411 | case REG_RFCON6: |
| 412 | case REG_RFCON7: |
| 413 | case REG_RFCON8: |
| 414 | case REG_SLPCAL2: |
| 415 | case REG_SLPCON0: |
| 416 | case REG_SLPCON1: |
| 417 | case REG_WAKETIMEL: |
| 418 | case REG_WAKETIMEH: |
| 419 | case REG_REMCNTL: |
| 420 | case REG_REMCNTH: |
| 421 | case REG_MAINCNT0: |
| 422 | case REG_MAINCNT1: |
| 423 | case REG_MAINCNT2: |
| 424 | case REG_MAINCNT3: |
| 425 | case REG_TESTMODE: |
| 426 | case REG_ASSOEAR0: |
| 427 | case REG_ASSOEAR1: |
| 428 | case REG_ASSOEAR2: |
| 429 | case REG_ASSOEAR3: |
| 430 | case REG_ASSOEAR4: |
| 431 | case REG_ASSOEAR5: |
| 432 | case REG_ASSOEAR6: |
| 433 | case REG_ASSOEAR7: |
| 434 | case REG_ASSOSAR0: |
| 435 | case REG_ASSOSAR1: |
| 436 | case REG_UNONCE0: |
| 437 | case REG_UNONCE1: |
| 438 | case REG_UNONCE2: |
| 439 | case REG_UNONCE3: |
| 440 | case REG_UNONCE4: |
| 441 | case REG_UNONCE5: |
| 442 | case REG_UNONCE6: |
| 443 | case REG_UNONCE7: |
| 444 | case REG_UNONCE8: |
| 445 | case REG_UNONCE9: |
| 446 | case REG_UNONCE10: |
| 447 | case REG_UNONCE11: |
| 448 | case REG_UNONCE12: |
| 449 | return true; |
| 450 | default: |
| 451 | return false; |
| 452 | } |
| 453 | } |
| 454 | |
| 455 | static bool |
| 456 | mrf24j40_long_reg_readable(struct device *dev, unsigned int reg) |
| 457 | { |
| 458 | bool rc; |
| 459 | |
| 460 | /* all writeable are also readable */ |
| 461 | rc = mrf24j40_long_reg_writeable(dev, reg); |
| 462 | if (rc) |
| 463 | return rc; |
| 464 | |
| 465 | /* readonly regs */ |
| 466 | switch (reg) { |
| 467 | case REG_SLPCAL0: |
| 468 | case REG_SLPCAL1: |
| 469 | case REG_RFSTATE: |
| 470 | case REG_RSSI: |
| 471 | return true; |
| 472 | default: |
| 473 | return false; |
| 474 | } |
| 475 | } |
| 476 | |
| 477 | static bool |
| 478 | mrf24j40_long_reg_volatile(struct device *dev, unsigned int reg) |
| 479 | { |
| 480 | /* can be changed during runtime */ |
| 481 | switch (reg) { |
| 482 | case REG_SLPCAL0: |
| 483 | case REG_SLPCAL1: |
| 484 | case REG_SLPCAL2: |
| 485 | case REG_RFSTATE: |
| 486 | case REG_RSSI: |
| 487 | case REG_MAINCNT3: |
| 488 | return true; |
| 489 | default: |
| 490 | return false; |
| 491 | } |
| 492 | } |
| 493 | |
| 494 | static const struct regmap_config mrf24j40_long_regmap = { |
| 495 | .name = "mrf24j40_long", |
| 496 | .reg_bits = 11, |
| 497 | .val_bits = 8, |
| 498 | .pad_bits = 5, |
| 499 | .write_flag_mask = MRF24J40_LONG_ACCESS, |
| 500 | .read_flag_mask = MRF24J40_LONG_ACCESS, |
| 501 | .cache_type = REGCACHE_RBTREE, |
| 502 | .max_register = MRF24J40_LONG_NUMREGS, |
| 503 | .writeable_reg = mrf24j40_long_reg_writeable, |
| 504 | .readable_reg = mrf24j40_long_reg_readable, |
| 505 | .volatile_reg = mrf24j40_long_reg_volatile, |
| 506 | }; |
| 507 | |
| 508 | static int mrf24j40_long_regmap_write(void *context, const void *data, |
| 509 | size_t count) |
| 510 | { |
| 511 | struct spi_device *spi = context; |
| 512 | u8 buf[3]; |
| 513 | |
| 514 | if (count > 3) |
| 515 | return -EINVAL; |
| 516 | |
| 517 | /* regmap supports read/write mask only in frist byte |
| 518 | * long write access need to set the 12th bit, so we |
| 519 | * make special handling for write. |
| 520 | */ |
| 521 | memcpy(buf, data, count); |
| 522 | buf[1] |= (1 << 4); |
| 523 | |
| 524 | return spi_write(spi, buf, count); |
| 525 | } |
| 526 | |
| 527 | static int |
| 528 | mrf24j40_long_regmap_read(void *context, const void *reg, size_t reg_size, |
| 529 | void *val, size_t val_size) |
| 530 | { |
| 531 | struct spi_device *spi = context; |
| 532 | |
| 533 | return spi_write_then_read(spi, reg, reg_size, val, val_size); |
| 534 | } |
| 535 | |
| 536 | static const struct regmap_bus mrf24j40_long_regmap_bus = { |
| 537 | .write = mrf24j40_long_regmap_write, |
| 538 | .read = mrf24j40_long_regmap_read, |
| 539 | .reg_format_endian_default = REGMAP_ENDIAN_BIG, |
| 540 | .val_format_endian_default = REGMAP_ENDIAN_BIG, |
| 541 | }; |
| 542 | |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 543 | static void write_tx_buf_complete(void *context) |
| 544 | { |
| 545 | struct mrf24j40 *devrec = context; |
| 546 | __le16 fc = ieee802154_get_fc_from_skb(devrec->tx_skb); |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 547 | u8 val = BIT_TXNTRIG; |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 548 | int ret; |
| 549 | |
| 550 | if (ieee802154_is_ackreq(fc)) |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 551 | val |= BIT_TXNACKREQ; |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 552 | |
| 553 | devrec->tx_post_msg.complete = NULL; |
| 554 | devrec->tx_post_buf[0] = MRF24J40_WRITESHORT(REG_TXNCON); |
| 555 | devrec->tx_post_buf[1] = val; |
| 556 | |
| 557 | ret = spi_async(devrec->spi, &devrec->tx_post_msg); |
| 558 | if (ret) |
| 559 | dev_err(printdev(devrec), "SPI write Failed for transmit buf\n"); |
| 560 | } |
| 561 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 562 | /* This function relies on an undocumented write method. Once a write command |
| 563 | and address is set, as many bytes of data as desired can be clocked into |
| 564 | the device. The datasheet only shows setting one byte at a time. */ |
| 565 | static int write_tx_buf(struct mrf24j40 *devrec, u16 reg, |
| 566 | const u8 *data, size_t length) |
| 567 | { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 568 | u16 cmd; |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 569 | int ret; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 570 | |
| 571 | /* Range check the length. 2 bytes are used for the length fields.*/ |
| 572 | if (length > TX_FIFO_SIZE-2) { |
| 573 | dev_err(printdev(devrec), "write_tx_buf() was passed too large a buffer. Performing short write.\n"); |
| 574 | length = TX_FIFO_SIZE-2; |
| 575 | } |
| 576 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 577 | cmd = MRF24J40_WRITELONG(reg); |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 578 | devrec->tx_hdr_buf[0] = cmd >> 8 & 0xff; |
| 579 | devrec->tx_hdr_buf[1] = cmd & 0xff; |
| 580 | devrec->tx_len_buf[0] = 0x0; /* Header Length. Set to 0 for now. TODO */ |
| 581 | devrec->tx_len_buf[1] = length; /* Total length */ |
| 582 | devrec->tx_buf_trx.tx_buf = data; |
| 583 | devrec->tx_buf_trx.len = length; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 584 | |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 585 | ret = spi_async(devrec->spi, &devrec->tx_msg); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 586 | if (ret) |
| 587 | dev_err(printdev(devrec), "SPI write Failed for TX buf\n"); |
| 588 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 589 | return ret; |
| 590 | } |
| 591 | |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 592 | static int mrf24j40_tx(struct ieee802154_hw *hw, struct sk_buff *skb) |
| 593 | { |
| 594 | struct mrf24j40 *devrec = hw->priv; |
| 595 | |
| 596 | dev_dbg(printdev(devrec), "tx packet of %d bytes\n", skb->len); |
| 597 | devrec->tx_skb = skb; |
| 598 | |
| 599 | return write_tx_buf(devrec, 0x000, skb->data, skb->len); |
| 600 | } |
| 601 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 602 | static int mrf24j40_ed(struct ieee802154_hw *hw, u8 *level) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 603 | { |
| 604 | /* TODO: */ |
Varka Bhadram | ca079ad | 2014-09-24 12:21:32 +0200 | [diff] [blame] | 605 | pr_warn("mrf24j40: ed not implemented\n"); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 606 | *level = 0; |
| 607 | return 0; |
| 608 | } |
| 609 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 610 | static int mrf24j40_start(struct ieee802154_hw *hw) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 611 | { |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 612 | struct mrf24j40 *devrec = hw->priv; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 613 | |
| 614 | dev_dbg(printdev(devrec), "start\n"); |
| 615 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 616 | /* Clear TXNIE and RXIE. Enable interrupts */ |
| 617 | return regmap_update_bits(devrec->regmap_short, REG_INTCON, |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 618 | BIT_TXNIE | BIT_RXIE, 0); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 619 | } |
| 620 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 621 | static void mrf24j40_stop(struct ieee802154_hw *hw) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 622 | { |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 623 | struct mrf24j40 *devrec = hw->priv; |
Varka Bhadram | 529160d | 2014-09-24 12:21:30 +0200 | [diff] [blame] | 624 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 625 | dev_dbg(printdev(devrec), "stop\n"); |
| 626 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 627 | /* Set TXNIE and RXIE. Disable Interrupts */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 628 | regmap_update_bits(devrec->regmap_short, REG_INTCON, |
| 629 | BIT_TXNIE | BIT_TXNIE, BIT_TXNIE | BIT_TXNIE); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 630 | } |
| 631 | |
Alexander Aring | e37d2ec | 2014-10-28 18:21:19 +0100 | [diff] [blame] | 632 | static int mrf24j40_set_channel(struct ieee802154_hw *hw, u8 page, u8 channel) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 633 | { |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 634 | struct mrf24j40 *devrec = hw->priv; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 635 | u8 val; |
| 636 | int ret; |
| 637 | |
| 638 | dev_dbg(printdev(devrec), "Set Channel %d\n", channel); |
| 639 | |
| 640 | WARN_ON(page != 0); |
| 641 | WARN_ON(channel < MRF24J40_CHAN_MIN); |
| 642 | WARN_ON(channel > MRF24J40_CHAN_MAX); |
| 643 | |
| 644 | /* Set Channel TODO */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 645 | val = (channel - 11) << RFCON0_CH_SHIFT | RFOPT_RECOMMEND; |
| 646 | ret = regmap_update_bits(devrec->regmap_long, REG_RFCON0, |
| 647 | RFCON0_CH_MASK, val); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 648 | if (ret) |
| 649 | return ret; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 650 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 651 | /* RF Reset */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 652 | ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, |
| 653 | BIT_RFRST); |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 654 | if (ret) |
| 655 | return ret; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 656 | |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 657 | ret = regmap_update_bits(devrec->regmap_short, REG_RFCTL, BIT_RFRST, 0); |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 658 | if (!ret) |
| 659 | udelay(SET_CHANNEL_DELAY_US); /* per datasheet */ |
| 660 | |
| 661 | return ret; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 662 | } |
| 663 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 664 | static int mrf24j40_filter(struct ieee802154_hw *hw, |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 665 | struct ieee802154_hw_addr_filt *filt, |
| 666 | unsigned long changed) |
| 667 | { |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 668 | struct mrf24j40 *devrec = hw->priv; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 669 | |
| 670 | dev_dbg(printdev(devrec), "filter\n"); |
| 671 | |
Alexander Aring | 57205c1 | 2014-10-25 05:25:09 +0200 | [diff] [blame] | 672 | if (changed & IEEE802154_AFILT_SADDR_CHANGED) { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 673 | /* Short Addr */ |
| 674 | u8 addrh, addrl; |
Varka Bhadram | 529160d | 2014-09-24 12:21:30 +0200 | [diff] [blame] | 675 | |
Phoebe Buckheister | b70ab2e | 2014-03-14 21:23:59 +0100 | [diff] [blame] | 676 | addrh = le16_to_cpu(filt->short_addr) >> 8 & 0xff; |
| 677 | addrl = le16_to_cpu(filt->short_addr) & 0xff; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 678 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 679 | regmap_write(devrec->regmap_short, REG_SADRH, addrh); |
| 680 | regmap_write(devrec->regmap_short, REG_SADRL, addrl); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 681 | dev_dbg(printdev(devrec), |
| 682 | "Set short addr to %04hx\n", filt->short_addr); |
| 683 | } |
| 684 | |
Alexander Aring | 57205c1 | 2014-10-25 05:25:09 +0200 | [diff] [blame] | 685 | if (changed & IEEE802154_AFILT_IEEEADDR_CHANGED) { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 686 | /* Device Address */ |
Phoebe Buckheister | b70ab2e | 2014-03-14 21:23:59 +0100 | [diff] [blame] | 687 | u8 i, addr[8]; |
| 688 | |
| 689 | memcpy(addr, &filt->ieee_addr, 8); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 690 | for (i = 0; i < 8; i++) |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 691 | regmap_write(devrec->regmap_short, REG_EADR0 + i, |
| 692 | addr[i]); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 693 | |
| 694 | #ifdef DEBUG |
Varka Bhadram | ca079ad | 2014-09-24 12:21:32 +0200 | [diff] [blame] | 695 | pr_debug("Set long addr to: "); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 696 | for (i = 0; i < 8; i++) |
Varka Bhadram | ca079ad | 2014-09-24 12:21:32 +0200 | [diff] [blame] | 697 | pr_debug("%02hhx ", addr[7 - i]); |
| 698 | pr_debug("\n"); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 699 | #endif |
| 700 | } |
| 701 | |
Alexander Aring | 57205c1 | 2014-10-25 05:25:09 +0200 | [diff] [blame] | 702 | if (changed & IEEE802154_AFILT_PANID_CHANGED) { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 703 | /* PAN ID */ |
| 704 | u8 panidl, panidh; |
Varka Bhadram | 529160d | 2014-09-24 12:21:30 +0200 | [diff] [blame] | 705 | |
Phoebe Buckheister | b70ab2e | 2014-03-14 21:23:59 +0100 | [diff] [blame] | 706 | panidh = le16_to_cpu(filt->pan_id) >> 8 & 0xff; |
| 707 | panidl = le16_to_cpu(filt->pan_id) & 0xff; |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 708 | regmap_write(devrec->regmap_short, REG_PANIDH, panidh); |
| 709 | regmap_write(devrec->regmap_short, REG_PANIDL, panidl); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 710 | |
| 711 | dev_dbg(printdev(devrec), "Set PANID to %04hx\n", filt->pan_id); |
| 712 | } |
| 713 | |
Alexander Aring | 57205c1 | 2014-10-25 05:25:09 +0200 | [diff] [blame] | 714 | if (changed & IEEE802154_AFILT_PANC_CHANGED) { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 715 | /* Pan Coordinator */ |
| 716 | u8 val; |
| 717 | int ret; |
| 718 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 719 | if (filt->pan_coord) |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 720 | val = BIT_PANCOORD; |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 721 | else |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 722 | val = 0; |
| 723 | ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, |
| 724 | BIT_PANCOORD, val); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 725 | if (ret) |
| 726 | return ret; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 727 | |
| 728 | /* REG_SLOTTED is maintained as default (unslotted/CSMA-CA). |
| 729 | * REG_ORDER is maintained as default (no beacon/superframe). |
| 730 | */ |
| 731 | |
| 732 | dev_dbg(printdev(devrec), "Set Pan Coord to %s\n", |
Stefan Schmidt | ce261bc | 2014-12-12 12:45:33 +0100 | [diff] [blame] | 733 | filt->pan_coord ? "on" : "off"); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 734 | } |
| 735 | |
| 736 | return 0; |
| 737 | } |
| 738 | |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 739 | static void mrf24j40_handle_rx_read_buf_unlock(struct mrf24j40 *devrec) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 740 | { |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 741 | int ret; |
| 742 | |
| 743 | /* Turn back on reception of packets off the air. */ |
| 744 | devrec->rx_msg.complete = NULL; |
| 745 | devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1); |
| 746 | devrec->rx_buf[1] = 0x00; /* CLR RXDECINV */ |
| 747 | ret = spi_async(devrec->spi, &devrec->rx_msg); |
| 748 | if (ret) |
| 749 | dev_err(printdev(devrec), "failed to unlock rx buffer\n"); |
| 750 | } |
| 751 | |
| 752 | static void mrf24j40_handle_rx_read_buf_complete(void *context) |
| 753 | { |
| 754 | struct mrf24j40 *devrec = context; |
| 755 | u8 len = devrec->rx_buf[2]; |
| 756 | u8 rx_local_buf[RX_FIFO_SIZE]; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 757 | struct sk_buff *skb; |
| 758 | |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 759 | memcpy(rx_local_buf, devrec->rx_fifo_buf, len); |
| 760 | mrf24j40_handle_rx_read_buf_unlock(devrec); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 761 | |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 762 | skb = dev_alloc_skb(IEEE802154_MTU); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 763 | if (!skb) { |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 764 | dev_err(printdev(devrec), "failed to allocate skb\n"); |
| 765 | return; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 766 | } |
| 767 | |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 768 | memcpy(skb_put(skb, len), rx_local_buf, len); |
| 769 | ieee802154_rx_irqsafe(devrec->hw, skb, 0); |
| 770 | |
| 771 | #ifdef DEBUG |
| 772 | print_hex_dump(KERN_DEBUG, "mrf24j40 rx: ", DUMP_PREFIX_OFFSET, 16, 1, |
| 773 | rx_local_buf, len, 0); |
| 774 | pr_debug("mrf24j40 rx: lqi: %02hhx rssi: %02hhx\n", |
| 775 | devrec->rx_lqi_buf[0], devrec->rx_lqi_buf[1]); |
| 776 | #endif |
| 777 | } |
| 778 | |
| 779 | static void mrf24j40_handle_rx_read_buf(void *context) |
| 780 | { |
| 781 | struct mrf24j40 *devrec = context; |
| 782 | u16 cmd; |
| 783 | int ret; |
| 784 | |
| 785 | /* if length is invalid read the full MTU */ |
| 786 | if (!ieee802154_is_valid_psdu_len(devrec->rx_buf[2])) |
| 787 | devrec->rx_buf[2] = IEEE802154_MTU; |
| 788 | |
| 789 | cmd = MRF24J40_READLONG(REG_RX_FIFO + 1); |
| 790 | devrec->rx_addr_buf[0] = cmd >> 8 & 0xff; |
| 791 | devrec->rx_addr_buf[1] = cmd & 0xff; |
| 792 | devrec->rx_fifo_buf_trx.len = devrec->rx_buf[2]; |
| 793 | ret = spi_async(devrec->spi, &devrec->rx_buf_msg); |
| 794 | if (ret) { |
| 795 | dev_err(printdev(devrec), "failed to read rx buffer\n"); |
| 796 | mrf24j40_handle_rx_read_buf_unlock(devrec); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 797 | } |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 798 | } |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 799 | |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 800 | static void mrf24j40_handle_rx_read_len(void *context) |
| 801 | { |
| 802 | struct mrf24j40 *devrec = context; |
| 803 | u16 cmd; |
| 804 | int ret; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 805 | |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 806 | /* read the length of received frame */ |
| 807 | devrec->rx_msg.complete = mrf24j40_handle_rx_read_buf; |
| 808 | devrec->rx_trx.len = 3; |
| 809 | cmd = MRF24J40_READLONG(REG_RX_FIFO); |
| 810 | devrec->rx_buf[0] = cmd >> 8 & 0xff; |
| 811 | devrec->rx_buf[1] = cmd & 0xff; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 812 | |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 813 | ret = spi_async(devrec->spi, &devrec->rx_msg); |
| 814 | if (ret) { |
| 815 | dev_err(printdev(devrec), "failed to read rx buffer length\n"); |
| 816 | mrf24j40_handle_rx_read_buf_unlock(devrec); |
| 817 | } |
| 818 | } |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 819 | |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 820 | static int mrf24j40_handle_rx(struct mrf24j40 *devrec) |
| 821 | { |
| 822 | /* Turn off reception of packets off the air. This prevents the |
| 823 | * device from overwriting the buffer while we're reading it. |
| 824 | */ |
| 825 | devrec->rx_msg.complete = mrf24j40_handle_rx_read_len; |
| 826 | devrec->rx_trx.len = 2; |
| 827 | devrec->rx_buf[0] = MRF24J40_WRITESHORT(REG_BBREG1); |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 828 | devrec->rx_buf[1] = BIT_RXDECINV; /* SET RXDECINV */ |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 829 | |
| 830 | return spi_async(devrec->spi, &devrec->rx_msg); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 831 | } |
| 832 | |
Alexander Aring | 2323cf3 | 2015-09-21 11:24:37 +0200 | [diff] [blame] | 833 | static int |
| 834 | mrf24j40_csma_params(struct ieee802154_hw *hw, u8 min_be, u8 max_be, |
| 835 | u8 retries) |
| 836 | { |
| 837 | struct mrf24j40 *devrec = hw->priv; |
| 838 | u8 val; |
| 839 | |
| 840 | /* min_be */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 841 | val = min_be << TXMCR_MIN_BE_SHIFT; |
Alexander Aring | 2323cf3 | 2015-09-21 11:24:37 +0200 | [diff] [blame] | 842 | /* csma backoffs */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 843 | val |= retries << TXMCR_CSMA_RETRIES_SHIFT; |
Alexander Aring | 2323cf3 | 2015-09-21 11:24:37 +0200 | [diff] [blame] | 844 | |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 845 | return regmap_update_bits(devrec->regmap_short, REG_TXMCR, |
| 846 | TXMCR_MIN_BE_MASK | TXMCR_CSMA_RETRIES_MASK, |
| 847 | val); |
Alexander Aring | 2323cf3 | 2015-09-21 11:24:37 +0200 | [diff] [blame] | 848 | } |
| 849 | |
Alexander Aring | f1d7812 | 2015-09-21 11:24:38 +0200 | [diff] [blame] | 850 | static int mrf24j40_set_cca_mode(struct ieee802154_hw *hw, |
| 851 | const struct wpan_phy_cca *cca) |
| 852 | { |
| 853 | struct mrf24j40 *devrec = hw->priv; |
| 854 | u8 val; |
| 855 | |
| 856 | /* mapping 802.15.4 to driver spec */ |
| 857 | switch (cca->mode) { |
| 858 | case NL802154_CCA_ENERGY: |
| 859 | val = 2; |
| 860 | break; |
| 861 | case NL802154_CCA_CARRIER: |
| 862 | val = 1; |
| 863 | break; |
| 864 | case NL802154_CCA_ENERGY_CARRIER: |
| 865 | switch (cca->opt) { |
| 866 | case NL802154_CCA_OPT_ENERGY_CARRIER_AND: |
| 867 | val = 3; |
| 868 | break; |
| 869 | default: |
| 870 | return -EINVAL; |
| 871 | } |
| 872 | break; |
| 873 | default: |
| 874 | return -EINVAL; |
| 875 | } |
| 876 | |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 877 | return regmap_update_bits(devrec->regmap_short, REG_BBREG2, |
| 878 | BBREG2_CCA_MODE_MASK, |
| 879 | val << BBREG2_CCA_MODE_SHIFT); |
Alexander Aring | f1d7812 | 2015-09-21 11:24:38 +0200 | [diff] [blame] | 880 | } |
| 881 | |
Alexander Aring | e33a0f9 | 2015-09-21 11:24:39 +0200 | [diff] [blame] | 882 | /* array for representing ed levels */ |
| 883 | static const s32 mrf24j40_ed_levels[] = { |
| 884 | -9000, -8900, -8800, -8700, -8600, -8500, -8400, -8300, -8200, -8100, |
| 885 | -8000, -7900, -7800, -7700, -7600, -7500, -7400, -7300, -7200, -7100, |
| 886 | -7000, -6900, -6800, -6700, -6600, -6500, -6400, -6300, -6200, -6100, |
| 887 | -6000, -5900, -5800, -5700, -5600, -5500, -5400, -5300, -5200, -5100, |
| 888 | -5000, -4900, -4800, -4700, -4600, -4500, -4400, -4300, -4200, -4100, |
| 889 | -4000, -3900, -3800, -3700, -3600, -3500 |
| 890 | }; |
| 891 | |
| 892 | /* map ed levels to register value */ |
| 893 | static const s32 mrf24j40_ed_levels_map[][2] = { |
| 894 | { -9000, 0 }, { -8900, 1 }, { -8800, 2 }, { -8700, 5 }, { -8600, 9 }, |
| 895 | { -8500, 13 }, { -8400, 18 }, { -8300, 23 }, { -8200, 27 }, |
| 896 | { -8100, 32 }, { -8000, 37 }, { -7900, 43 }, { -7800, 48 }, |
| 897 | { -7700, 53 }, { -7600, 58 }, { -7500, 63 }, { -7400, 68 }, |
| 898 | { -7300, 73 }, { -7200, 78 }, { -7100, 83 }, { -7000, 89 }, |
| 899 | { -6900, 95 }, { -6800, 100 }, { -6700, 107 }, { -6600, 111 }, |
| 900 | { -6500, 117 }, { -6400, 121 }, { -6300, 125 }, { -6200, 129 }, |
| 901 | { -6100, 133 }, { -6000, 138 }, { -5900, 143 }, { -5800, 148 }, |
| 902 | { -5700, 153 }, { -5600, 159 }, { -5500, 165 }, { -5400, 170 }, |
| 903 | { -5300, 176 }, { -5200, 183 }, { -5100, 188 }, { -5000, 193 }, |
| 904 | { -4900, 198 }, { -4800, 203 }, { -4700, 207 }, { -4600, 212 }, |
| 905 | { -4500, 216 }, { -4400, 221 }, { -4300, 225 }, { -4200, 228 }, |
| 906 | { -4100, 233 }, { -4000, 239 }, { -3900, 245 }, { -3800, 250 }, |
| 907 | { -3700, 253 }, { -3600, 254 }, { -3500, 255 }, |
| 908 | }; |
| 909 | |
| 910 | static int mrf24j40_set_cca_ed_level(struct ieee802154_hw *hw, s32 mbm) |
| 911 | { |
| 912 | struct mrf24j40 *devrec = hw->priv; |
| 913 | int i; |
| 914 | |
| 915 | for (i = 0; i < ARRAY_SIZE(mrf24j40_ed_levels_map); i++) { |
| 916 | if (mrf24j40_ed_levels_map[i][0] == mbm) |
| 917 | return regmap_write(devrec->regmap_short, REG_CCAEDTH, |
| 918 | mrf24j40_ed_levels_map[i][1]); |
| 919 | } |
| 920 | |
| 921 | return -EINVAL; |
| 922 | } |
| 923 | |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 924 | static const s32 mrf24j40ma_powers[] = { |
| 925 | 0, -50, -120, -190, -280, -370, -490, -630, -1000, -1050, -1120, -1190, |
| 926 | -1280, -1370, -1490, -1630, -2000, -2050, -2120, -2190, -2280, -2370, |
| 927 | -2490, -2630, -3000, -3050, -3120, -3190, -3280, -3370, -3490, -3630, |
| 928 | }; |
| 929 | |
| 930 | static int mrf24j40_set_txpower(struct ieee802154_hw *hw, s32 mbm) |
| 931 | { |
| 932 | struct mrf24j40 *devrec = hw->priv; |
| 933 | s32 small_scale; |
| 934 | u8 val; |
| 935 | |
| 936 | if (0 >= mbm && mbm > -1000) { |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 937 | val = TXPWRL_0 << TXPWRL_SHIFT; |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 938 | small_scale = mbm; |
| 939 | } else if (-1000 >= mbm && mbm > -2000) { |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 940 | val = TXPWRL_10 << TXPWRL_SHIFT; |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 941 | small_scale = mbm + 1000; |
| 942 | } else if (-2000 >= mbm && mbm > -3000) { |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 943 | val = TXPWRL_20 << TXPWRL_SHIFT; |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 944 | small_scale = mbm + 2000; |
| 945 | } else if (-3000 >= mbm && mbm > -4000) { |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 946 | val = TXPWRL_30 << TXPWRL_SHIFT; |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 947 | small_scale = mbm + 3000; |
| 948 | } else { |
| 949 | return -EINVAL; |
| 950 | } |
| 951 | |
| 952 | switch (small_scale) { |
| 953 | case 0: |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 954 | val |= (TXPWRS_0 << TXPWRS_SHIFT); |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 955 | break; |
| 956 | case -50: |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 957 | val |= (TXPWRS_0_5 << TXPWRS_SHIFT); |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 958 | break; |
| 959 | case -120: |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 960 | val |= (TXPWRS_1_2 << TXPWRS_SHIFT); |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 961 | break; |
| 962 | case -190: |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 963 | val |= (TXPWRS_1_9 << TXPWRS_SHIFT); |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 964 | break; |
| 965 | case -280: |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 966 | val |= (TXPWRS_2_8 << TXPWRS_SHIFT); |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 967 | break; |
| 968 | case -370: |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 969 | val |= (TXPWRS_3_7 << TXPWRS_SHIFT); |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 970 | break; |
| 971 | case -490: |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 972 | val |= (TXPWRS_4_9 << TXPWRS_SHIFT); |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 973 | break; |
| 974 | case -630: |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 975 | val |= (TXPWRS_6_3 << TXPWRS_SHIFT); |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 976 | break; |
| 977 | default: |
| 978 | return -EINVAL; |
| 979 | } |
| 980 | |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 981 | return regmap_update_bits(devrec->regmap_long, REG_RFCON3, |
| 982 | TXPWRL_MASK | TXPWRS_MASK, val); |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 983 | } |
| 984 | |
Alexander Aring | 8ba4041 | 2015-09-21 11:24:41 +0200 | [diff] [blame] | 985 | static int mrf24j40_set_promiscuous_mode(struct ieee802154_hw *hw, bool on) |
| 986 | { |
| 987 | struct mrf24j40 *devrec = hw->priv; |
| 988 | int ret; |
| 989 | |
| 990 | if (on) { |
| 991 | /* set PROMI, ERRPKT and NOACKRSP */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 992 | ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, |
| 993 | BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP, |
| 994 | BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP); |
Alexander Aring | 8ba4041 | 2015-09-21 11:24:41 +0200 | [diff] [blame] | 995 | } else { |
| 996 | /* clear PROMI, ERRPKT and NOACKRSP */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 997 | ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, |
| 998 | BIT_PROMI | BIT_ERRPKT | BIT_NOACKRSP, |
| 999 | 0); |
Alexander Aring | 8ba4041 | 2015-09-21 11:24:41 +0200 | [diff] [blame] | 1000 | } |
| 1001 | |
| 1002 | return ret; |
| 1003 | } |
| 1004 | |
Alexander Aring | 1630186 | 2014-10-28 18:21:18 +0100 | [diff] [blame] | 1005 | static const struct ieee802154_ops mrf24j40_ops = { |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1006 | .owner = THIS_MODULE, |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 1007 | .xmit_async = mrf24j40_tx, |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1008 | .ed = mrf24j40_ed, |
| 1009 | .start = mrf24j40_start, |
| 1010 | .stop = mrf24j40_stop, |
| 1011 | .set_channel = mrf24j40_set_channel, |
| 1012 | .set_hw_addr_filt = mrf24j40_filter, |
Alexander Aring | 2323cf3 | 2015-09-21 11:24:37 +0200 | [diff] [blame] | 1013 | .set_csma_params = mrf24j40_csma_params, |
Alexander Aring | f1d7812 | 2015-09-21 11:24:38 +0200 | [diff] [blame] | 1014 | .set_cca_mode = mrf24j40_set_cca_mode, |
Alexander Aring | e33a0f9 | 2015-09-21 11:24:39 +0200 | [diff] [blame] | 1015 | .set_cca_ed_level = mrf24j40_set_cca_ed_level, |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 1016 | .set_txpower = mrf24j40_set_txpower, |
Alexander Aring | 8ba4041 | 2015-09-21 11:24:41 +0200 | [diff] [blame] | 1017 | .set_promiscuous_mode = mrf24j40_set_promiscuous_mode, |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1018 | }; |
| 1019 | |
Alexander Aring | 3744161 | 2015-09-21 11:24:36 +0200 | [diff] [blame] | 1020 | static void mrf24j40_intstat_complete(void *context) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1021 | { |
Alexander Aring | 3744161 | 2015-09-21 11:24:36 +0200 | [diff] [blame] | 1022 | struct mrf24j40 *devrec = context; |
| 1023 | u8 intstat = devrec->irq_buf[1]; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1024 | |
Alexander Aring | 3744161 | 2015-09-21 11:24:36 +0200 | [diff] [blame] | 1025 | enable_irq(devrec->spi->irq); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1026 | |
| 1027 | /* Check for TX complete */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 1028 | if (intstat & BIT_TXNIF) |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 1029 | ieee802154_xmit_complete(devrec->hw, devrec->tx_skb, false); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1030 | |
| 1031 | /* Check for Rx */ |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 1032 | if (intstat & BIT_RXIF) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1033 | mrf24j40_handle_rx(devrec); |
Alexander Aring | 3744161 | 2015-09-21 11:24:36 +0200 | [diff] [blame] | 1034 | } |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1035 | |
Alexander Aring | 3744161 | 2015-09-21 11:24:36 +0200 | [diff] [blame] | 1036 | static irqreturn_t mrf24j40_isr(int irq, void *data) |
| 1037 | { |
| 1038 | struct mrf24j40 *devrec = data; |
| 1039 | int ret; |
| 1040 | |
| 1041 | disable_irq_nosync(irq); |
| 1042 | |
| 1043 | devrec->irq_buf[0] = MRF24J40_READSHORT(REG_INTSTAT); |
| 1044 | /* Read the interrupt status */ |
| 1045 | ret = spi_async(devrec->spi, &devrec->irq_msg); |
| 1046 | if (ret) { |
| 1047 | enable_irq(irq); |
| 1048 | return IRQ_NONE; |
| 1049 | } |
| 1050 | |
Alan Ott | 4a4e1da | 2013-10-05 23:52:23 -0400 | [diff] [blame] | 1051 | return IRQ_HANDLED; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1052 | } |
| 1053 | |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1054 | static int mrf24j40_hw_init(struct mrf24j40 *devrec) |
| 1055 | { |
Alexander Aring | afaf7fde | 2015-09-21 11:24:42 +0200 | [diff] [blame] | 1056 | u32 irq_type; |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1057 | int ret; |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1058 | |
| 1059 | /* Initialize the device. |
| 1060 | From datasheet section 3.2: Initialization. */ |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1061 | ret = regmap_write(devrec->regmap_short, REG_SOFTRST, 0x07); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1062 | if (ret) |
| 1063 | goto err_ret; |
| 1064 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1065 | ret = regmap_write(devrec->regmap_short, REG_PACON2, 0x98); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1066 | if (ret) |
| 1067 | goto err_ret; |
| 1068 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1069 | ret = regmap_write(devrec->regmap_short, REG_TXSTBL, 0x95); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1070 | if (ret) |
| 1071 | goto err_ret; |
| 1072 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1073 | ret = regmap_write(devrec->regmap_long, REG_RFCON0, 0x03); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1074 | if (ret) |
| 1075 | goto err_ret; |
| 1076 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1077 | ret = regmap_write(devrec->regmap_long, REG_RFCON1, 0x01); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1078 | if (ret) |
| 1079 | goto err_ret; |
| 1080 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1081 | ret = regmap_write(devrec->regmap_long, REG_RFCON2, 0x80); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1082 | if (ret) |
| 1083 | goto err_ret; |
| 1084 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1085 | ret = regmap_write(devrec->regmap_long, REG_RFCON6, 0x90); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1086 | if (ret) |
| 1087 | goto err_ret; |
| 1088 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1089 | ret = regmap_write(devrec->regmap_long, REG_RFCON7, 0x80); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1090 | if (ret) |
| 1091 | goto err_ret; |
| 1092 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1093 | ret = regmap_write(devrec->regmap_long, REG_RFCON8, 0x10); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1094 | if (ret) |
| 1095 | goto err_ret; |
| 1096 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1097 | ret = regmap_write(devrec->regmap_long, REG_SLPCON1, 0x21); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1098 | if (ret) |
| 1099 | goto err_ret; |
| 1100 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1101 | ret = regmap_write(devrec->regmap_short, REG_BBREG2, 0x80); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1102 | if (ret) |
| 1103 | goto err_ret; |
| 1104 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1105 | ret = regmap_write(devrec->regmap_short, REG_CCAEDTH, 0x60); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1106 | if (ret) |
| 1107 | goto err_ret; |
| 1108 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1109 | ret = regmap_write(devrec->regmap_short, REG_BBREG6, 0x40); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1110 | if (ret) |
| 1111 | goto err_ret; |
| 1112 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1113 | ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x04); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1114 | if (ret) |
| 1115 | goto err_ret; |
| 1116 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1117 | ret = regmap_write(devrec->regmap_short, REG_RFCTL, 0x0); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1118 | if (ret) |
| 1119 | goto err_ret; |
| 1120 | |
| 1121 | udelay(192); |
| 1122 | |
| 1123 | /* Set RX Mode. RXMCR<1:0>: 0x0 normal, 0x1 promisc, 0x2 error */ |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1124 | ret = regmap_update_bits(devrec->regmap_short, REG_RXMCR, 0x03, 0x00); |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1125 | if (ret) |
| 1126 | goto err_ret; |
| 1127 | |
Simon Vincent | db9e0ee | 2014-10-06 10:39:45 +0100 | [diff] [blame] | 1128 | if (spi_get_device_id(devrec->spi)->driver_data == MRF24J40MC) { |
| 1129 | /* Enable external amplifier. |
| 1130 | * From MRF24J40MC datasheet section 1.3: Operation. |
| 1131 | */ |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1132 | regmap_update_bits(devrec->regmap_long, REG_TESTMODE, 0x07, |
| 1133 | 0x07); |
Simon Vincent | db9e0ee | 2014-10-06 10:39:45 +0100 | [diff] [blame] | 1134 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1135 | /* Set GPIO3 as output. */ |
| 1136 | regmap_update_bits(devrec->regmap_short, REG_TRISGPIO, 0x08, |
| 1137 | 0x08); |
Simon Vincent | db9e0ee | 2014-10-06 10:39:45 +0100 | [diff] [blame] | 1138 | |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1139 | /* Set GPIO3 HIGH to enable U5 voltage regulator */ |
| 1140 | regmap_update_bits(devrec->regmap_short, REG_GPIO, 0x08, 0x08); |
Simon Vincent | db9e0ee | 2014-10-06 10:39:45 +0100 | [diff] [blame] | 1141 | |
| 1142 | /* Reduce TX pwr to meet FCC requirements. |
| 1143 | * From MRF24J40MC datasheet section 3.1.1 |
| 1144 | */ |
Alexander Aring | 42c7148 | 2015-09-21 11:24:31 +0200 | [diff] [blame] | 1145 | regmap_write(devrec->regmap_long, REG_RFCON3, 0x28); |
Simon Vincent | db9e0ee | 2014-10-06 10:39:45 +0100 | [diff] [blame] | 1146 | } |
| 1147 | |
Alexander Aring | afaf7fde | 2015-09-21 11:24:42 +0200 | [diff] [blame] | 1148 | irq_type = irq_get_trigger_type(devrec->spi->irq); |
| 1149 | if (irq_type == IRQ_TYPE_EDGE_RISING || |
| 1150 | irq_type == IRQ_TYPE_EDGE_FALLING) |
| 1151 | dev_warn(&devrec->spi->dev, |
| 1152 | "Using edge triggered irq's are not recommended, because it can cause races and result in a non-functional driver!\n"); |
| 1153 | switch (irq_type) { |
| 1154 | case IRQ_TYPE_EDGE_RISING: |
| 1155 | case IRQ_TYPE_LEVEL_HIGH: |
| 1156 | /* set interrupt polarity to rising */ |
| 1157 | ret = regmap_update_bits(devrec->regmap_long, REG_SLPCON0, |
Alexander Aring | 7d84054 | 2015-09-21 11:24:43 +0200 | [diff] [blame] | 1158 | BIT_INTEDGE, BIT_INTEDGE); |
Alexander Aring | afaf7fde | 2015-09-21 11:24:42 +0200 | [diff] [blame] | 1159 | if (ret) |
| 1160 | goto err_ret; |
| 1161 | break; |
| 1162 | default: |
| 1163 | /* default is falling edge */ |
| 1164 | break; |
| 1165 | } |
| 1166 | |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1167 | return 0; |
| 1168 | |
| 1169 | err_ret: |
| 1170 | return ret; |
| 1171 | } |
| 1172 | |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 1173 | static void |
| 1174 | mrf24j40_setup_tx_spi_messages(struct mrf24j40 *devrec) |
| 1175 | { |
| 1176 | spi_message_init(&devrec->tx_msg); |
| 1177 | devrec->tx_msg.context = devrec; |
| 1178 | devrec->tx_msg.complete = write_tx_buf_complete; |
| 1179 | devrec->tx_hdr_trx.len = 2; |
| 1180 | devrec->tx_hdr_trx.tx_buf = devrec->tx_hdr_buf; |
| 1181 | spi_message_add_tail(&devrec->tx_hdr_trx, &devrec->tx_msg); |
| 1182 | devrec->tx_len_trx.len = 2; |
| 1183 | devrec->tx_len_trx.tx_buf = devrec->tx_len_buf; |
| 1184 | spi_message_add_tail(&devrec->tx_len_trx, &devrec->tx_msg); |
| 1185 | spi_message_add_tail(&devrec->tx_buf_trx, &devrec->tx_msg); |
| 1186 | |
| 1187 | spi_message_init(&devrec->tx_post_msg); |
| 1188 | devrec->tx_post_msg.context = devrec; |
| 1189 | devrec->tx_post_trx.len = 2; |
| 1190 | devrec->tx_post_trx.tx_buf = devrec->tx_post_buf; |
| 1191 | spi_message_add_tail(&devrec->tx_post_trx, &devrec->tx_post_msg); |
| 1192 | } |
| 1193 | |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 1194 | static void |
| 1195 | mrf24j40_setup_rx_spi_messages(struct mrf24j40 *devrec) |
| 1196 | { |
| 1197 | spi_message_init(&devrec->rx_msg); |
| 1198 | devrec->rx_msg.context = devrec; |
| 1199 | devrec->rx_trx.len = 2; |
| 1200 | devrec->rx_trx.tx_buf = devrec->rx_buf; |
| 1201 | devrec->rx_trx.rx_buf = devrec->rx_buf; |
| 1202 | spi_message_add_tail(&devrec->rx_trx, &devrec->rx_msg); |
| 1203 | |
| 1204 | spi_message_init(&devrec->rx_buf_msg); |
| 1205 | devrec->rx_buf_msg.context = devrec; |
| 1206 | devrec->rx_buf_msg.complete = mrf24j40_handle_rx_read_buf_complete; |
| 1207 | devrec->rx_addr_trx.len = 2; |
| 1208 | devrec->rx_addr_trx.tx_buf = devrec->rx_addr_buf; |
| 1209 | spi_message_add_tail(&devrec->rx_addr_trx, &devrec->rx_buf_msg); |
| 1210 | devrec->rx_fifo_buf_trx.rx_buf = devrec->rx_fifo_buf; |
| 1211 | spi_message_add_tail(&devrec->rx_fifo_buf_trx, &devrec->rx_buf_msg); |
| 1212 | devrec->rx_lqi_trx.len = 2; |
| 1213 | devrec->rx_lqi_trx.rx_buf = devrec->rx_lqi_buf; |
| 1214 | spi_message_add_tail(&devrec->rx_lqi_trx, &devrec->rx_buf_msg); |
| 1215 | } |
| 1216 | |
Alexander Aring | 3744161 | 2015-09-21 11:24:36 +0200 | [diff] [blame] | 1217 | static void |
| 1218 | mrf24j40_setup_irq_spi_messages(struct mrf24j40 *devrec) |
| 1219 | { |
| 1220 | spi_message_init(&devrec->irq_msg); |
| 1221 | devrec->irq_msg.context = devrec; |
| 1222 | devrec->irq_msg.complete = mrf24j40_intstat_complete; |
| 1223 | devrec->irq_trx.len = 2; |
| 1224 | devrec->irq_trx.tx_buf = devrec->irq_buf; |
| 1225 | devrec->irq_trx.rx_buf = devrec->irq_buf; |
| 1226 | spi_message_add_tail(&devrec->irq_trx, &devrec->irq_msg); |
| 1227 | } |
| 1228 | |
Alexander Aring | 766928f | 2015-09-21 11:24:27 +0200 | [diff] [blame] | 1229 | static void mrf24j40_phy_setup(struct mrf24j40 *devrec) |
| 1230 | { |
Alexander Aring | d344c91 | 2015-09-21 11:24:28 +0200 | [diff] [blame] | 1231 | ieee802154_random_extended_addr(&devrec->hw->phy->perm_extended_addr); |
Alexander Aring | 766928f | 2015-09-21 11:24:27 +0200 | [diff] [blame] | 1232 | devrec->hw->phy->current_channel = 11; |
Alexander Aring | 2323cf3 | 2015-09-21 11:24:37 +0200 | [diff] [blame] | 1233 | |
| 1234 | /* mrf24j40 supports max_minbe 0 - 3 */ |
| 1235 | devrec->hw->phy->supported.max_minbe = 3; |
| 1236 | /* datasheet doesn't say anything about max_be, but we have min_be |
| 1237 | * So we assume the max_be default. |
| 1238 | */ |
| 1239 | devrec->hw->phy->supported.min_maxbe = 5; |
| 1240 | devrec->hw->phy->supported.max_maxbe = 5; |
Alexander Aring | f1d7812 | 2015-09-21 11:24:38 +0200 | [diff] [blame] | 1241 | |
Alexander Aring | eb24d06 | 2015-09-24 19:40:33 +0200 | [diff] [blame^] | 1242 | devrec->hw->phy->cca.mode = NL802154_CCA_CARRIER; |
Alexander Aring | f1d7812 | 2015-09-21 11:24:38 +0200 | [diff] [blame] | 1243 | devrec->hw->phy->supported.cca_modes = BIT(NL802154_CCA_ENERGY) | |
| 1244 | BIT(NL802154_CCA_CARRIER) | |
| 1245 | BIT(NL802154_CCA_ENERGY_CARRIER); |
| 1246 | devrec->hw->phy->supported.cca_opts = BIT(NL802154_CCA_OPT_ENERGY_CARRIER_AND); |
Alexander Aring | e33a0f9 | 2015-09-21 11:24:39 +0200 | [diff] [blame] | 1247 | |
| 1248 | devrec->hw->phy->cca_ed_level = -6900; |
| 1249 | devrec->hw->phy->supported.cca_ed_levels = mrf24j40_ed_levels; |
| 1250 | devrec->hw->phy->supported.cca_ed_levels_size = ARRAY_SIZE(mrf24j40_ed_levels); |
Alexander Aring | 00250f7 | 2015-09-21 11:24:40 +0200 | [diff] [blame] | 1251 | |
| 1252 | switch (spi_get_device_id(devrec->spi)->driver_data) { |
| 1253 | case MRF24J40: |
| 1254 | case MRF24J40MA: |
| 1255 | devrec->hw->phy->supported.tx_powers = mrf24j40ma_powers; |
| 1256 | devrec->hw->phy->supported.tx_powers_size = ARRAY_SIZE(mrf24j40ma_powers); |
| 1257 | devrec->hw->phy->flags |= WPAN_PHY_FLAG_TXPOWER; |
| 1258 | break; |
| 1259 | default: |
| 1260 | break; |
| 1261 | } |
Alexander Aring | 766928f | 2015-09-21 11:24:27 +0200 | [diff] [blame] | 1262 | } |
| 1263 | |
Bill Pemberton | bb1f460 | 2012-12-03 09:24:12 -0500 | [diff] [blame] | 1264 | static int mrf24j40_probe(struct spi_device *spi) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1265 | { |
Alexander Aring | afaf7fde | 2015-09-21 11:24:42 +0200 | [diff] [blame] | 1266 | int ret = -ENOMEM, irq_type; |
Alexander Aring | b2cfdf3 | 2015-09-21 11:24:23 +0200 | [diff] [blame] | 1267 | struct ieee802154_hw *hw; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1268 | struct mrf24j40 *devrec; |
| 1269 | |
Varka Bhadram | ca079ad | 2014-09-24 12:21:32 +0200 | [diff] [blame] | 1270 | dev_info(&spi->dev, "probe(). IRQ: %d\n", spi->irq); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1271 | |
Alexander Aring | b2cfdf3 | 2015-09-21 11:24:23 +0200 | [diff] [blame] | 1272 | /* Register with the 802154 subsystem */ |
| 1273 | |
| 1274 | hw = ieee802154_alloc_hw(sizeof(*devrec), &mrf24j40_ops); |
| 1275 | if (!hw) |
Varka Bhadram | 0aaf43f | 2014-06-11 10:04:44 +0530 | [diff] [blame] | 1276 | goto err_ret; |
Alexander Aring | b2cfdf3 | 2015-09-21 11:24:23 +0200 | [diff] [blame] | 1277 | |
| 1278 | devrec = hw->priv; |
| 1279 | devrec->spi = spi; |
| 1280 | spi_set_drvdata(spi, devrec); |
| 1281 | devrec->hw = hw; |
| 1282 | devrec->hw->parent = &spi->dev; |
| 1283 | devrec->hw->phy->supported.channels[0] = CHANNEL_MASK; |
Alexander Aring | 2323cf3 | 2015-09-21 11:24:37 +0200 | [diff] [blame] | 1284 | devrec->hw->flags = IEEE802154_HW_TX_OMIT_CKSUM | IEEE802154_HW_AFILT | |
Alexander Aring | 8ba4041 | 2015-09-21 11:24:41 +0200 | [diff] [blame] | 1285 | IEEE802154_HW_CSMA_PARAMS | |
| 1286 | IEEE802154_HW_PROMISCUOUS; |
Alexander Aring | b2cfdf3 | 2015-09-21 11:24:23 +0200 | [diff] [blame] | 1287 | |
Alexander Aring | e33a0f9 | 2015-09-21 11:24:39 +0200 | [diff] [blame] | 1288 | devrec->hw->phy->flags = WPAN_PHY_FLAG_CCA_MODE | |
| 1289 | WPAN_PHY_FLAG_CCA_ED_LEVEL; |
Alexander Aring | f1d7812 | 2015-09-21 11:24:38 +0200 | [diff] [blame] | 1290 | |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 1291 | mrf24j40_setup_tx_spi_messages(devrec); |
Alexander Aring | c91a301 | 2015-09-21 11:24:35 +0200 | [diff] [blame] | 1292 | mrf24j40_setup_rx_spi_messages(devrec); |
Alexander Aring | 3744161 | 2015-09-21 11:24:36 +0200 | [diff] [blame] | 1293 | mrf24j40_setup_irq_spi_messages(devrec); |
Alexander Aring | 6844a0e | 2015-09-21 11:24:34 +0200 | [diff] [blame] | 1294 | |
Alexander Aring | b015679 | 2015-09-21 11:24:30 +0200 | [diff] [blame] | 1295 | devrec->regmap_short = devm_regmap_init_spi(spi, |
| 1296 | &mrf24j40_short_regmap); |
| 1297 | if (IS_ERR(devrec->regmap_short)) { |
| 1298 | ret = PTR_ERR(devrec->regmap_short); |
| 1299 | dev_err(&spi->dev, "Failed to allocate short register map: %d\n", |
| 1300 | ret); |
| 1301 | goto err_register_device; |
| 1302 | } |
| 1303 | |
| 1304 | devrec->regmap_long = devm_regmap_init(&spi->dev, |
| 1305 | &mrf24j40_long_regmap_bus, |
| 1306 | spi, &mrf24j40_long_regmap); |
| 1307 | if (IS_ERR(devrec->regmap_long)) { |
| 1308 | ret = PTR_ERR(devrec->regmap_long); |
| 1309 | dev_err(&spi->dev, "Failed to allocate long register map: %d\n", |
| 1310 | ret); |
| 1311 | goto err_register_device; |
| 1312 | } |
| 1313 | |
Alexander Aring | 78aedb6 | 2015-09-21 11:24:25 +0200 | [diff] [blame] | 1314 | if (spi->max_speed_hz > MAX_SPI_SPEED_HZ) { |
| 1315 | dev_warn(&spi->dev, "spi clock above possible maximum: %d", |
| 1316 | MAX_SPI_SPEED_HZ); |
| 1317 | return -EINVAL; |
| 1318 | } |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1319 | |
Varka Bhadram | 3dac9a7 | 2014-06-16 09:12:31 +0530 | [diff] [blame] | 1320 | ret = mrf24j40_hw_init(devrec); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1321 | if (ret) |
Alexander Aring | a339e18 | 2015-09-21 11:24:24 +0200 | [diff] [blame] | 1322 | goto err_register_device; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1323 | |
Alexander Aring | 766928f | 2015-09-21 11:24:27 +0200 | [diff] [blame] | 1324 | mrf24j40_phy_setup(devrec); |
| 1325 | |
Alexander Aring | afaf7fde | 2015-09-21 11:24:42 +0200 | [diff] [blame] | 1326 | /* request IRQF_TRIGGER_LOW as fallback default */ |
| 1327 | irq_type = irq_get_trigger_type(spi->irq); |
| 1328 | if (!irq_type) |
| 1329 | irq_type = IRQF_TRIGGER_LOW; |
| 1330 | |
Alexander Aring | 3744161 | 2015-09-21 11:24:36 +0200 | [diff] [blame] | 1331 | ret = devm_request_irq(&spi->dev, spi->irq, mrf24j40_isr, |
Alexander Aring | afaf7fde | 2015-09-21 11:24:42 +0200 | [diff] [blame] | 1332 | irq_type, dev_name(&spi->dev), devrec); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1333 | if (ret) { |
| 1334 | dev_err(printdev(devrec), "Unable to get IRQ"); |
Alexander Aring | a339e18 | 2015-09-21 11:24:24 +0200 | [diff] [blame] | 1335 | goto err_register_device; |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1336 | } |
| 1337 | |
Alexander Aring | a339e18 | 2015-09-21 11:24:24 +0200 | [diff] [blame] | 1338 | dev_dbg(printdev(devrec), "registered mrf24j40\n"); |
| 1339 | ret = ieee802154_register_hw(devrec->hw); |
| 1340 | if (ret) |
| 1341 | goto err_register_device; |
| 1342 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1343 | return 0; |
| 1344 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1345 | err_register_device: |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 1346 | ieee802154_free_hw(devrec->hw); |
Varka Bhadram | 0aaf43f | 2014-06-11 10:04:44 +0530 | [diff] [blame] | 1347 | err_ret: |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1348 | return ret; |
| 1349 | } |
| 1350 | |
Bill Pemberton | bb1f460 | 2012-12-03 09:24:12 -0500 | [diff] [blame] | 1351 | static int mrf24j40_remove(struct spi_device *spi) |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1352 | { |
Jingoo Han | 4fa0a0e | 2013-04-05 20:34:18 +0000 | [diff] [blame] | 1353 | struct mrf24j40 *devrec = spi_get_drvdata(spi); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1354 | |
| 1355 | dev_dbg(printdev(devrec), "remove\n"); |
| 1356 | |
Alexander Aring | 5a50439 | 2014-10-25 17:16:34 +0200 | [diff] [blame] | 1357 | ieee802154_unregister_hw(devrec->hw); |
| 1358 | ieee802154_free_hw(devrec->hw); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1359 | /* TODO: Will ieee802154_free_device() wait until ->xmit() is |
| 1360 | * complete? */ |
| 1361 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1362 | return 0; |
| 1363 | } |
| 1364 | |
Alexander Aring | 2e6fd64 | 2015-09-21 11:24:26 +0200 | [diff] [blame] | 1365 | static const struct of_device_id mrf24j40_of_match[] = { |
| 1366 | { .compatible = "microchip,mrf24j40", .data = (void *)MRF24J40 }, |
| 1367 | { .compatible = "microchip,mrf24j40ma", .data = (void *)MRF24J40MA }, |
| 1368 | { .compatible = "microchip,mrf24j40mc", .data = (void *)MRF24J40MC }, |
| 1369 | { }, |
| 1370 | }; |
| 1371 | MODULE_DEVICE_TABLE(of, mrf24j40_of_match); |
| 1372 | |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1373 | static const struct spi_device_id mrf24j40_ids[] = { |
Simon Vincent | db9e0ee | 2014-10-06 10:39:45 +0100 | [diff] [blame] | 1374 | { "mrf24j40", MRF24J40 }, |
| 1375 | { "mrf24j40ma", MRF24J40MA }, |
| 1376 | { "mrf24j40mc", MRF24J40MC }, |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1377 | { }, |
| 1378 | }; |
| 1379 | MODULE_DEVICE_TABLE(spi, mrf24j40_ids); |
| 1380 | |
| 1381 | static struct spi_driver mrf24j40_driver = { |
| 1382 | .driver = { |
Alexander Aring | 2e6fd64 | 2015-09-21 11:24:26 +0200 | [diff] [blame] | 1383 | .of_match_table = of_match_ptr(mrf24j40_of_match), |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1384 | .name = "mrf24j40", |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1385 | .owner = THIS_MODULE, |
| 1386 | }, |
| 1387 | .id_table = mrf24j40_ids, |
| 1388 | .probe = mrf24j40_probe, |
Bill Pemberton | bb1f460 | 2012-12-03 09:24:12 -0500 | [diff] [blame] | 1389 | .remove = mrf24j40_remove, |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1390 | }; |
| 1391 | |
Wei Yongjun | 3d4a131 | 2013-04-08 20:34:44 +0000 | [diff] [blame] | 1392 | module_spi_driver(mrf24j40_driver); |
Alan Ott | 3731a33 | 2012-09-02 15:44:13 +0000 | [diff] [blame] | 1393 | |
| 1394 | MODULE_LICENSE("GPL"); |
| 1395 | MODULE_AUTHOR("Alan Ott"); |
| 1396 | MODULE_DESCRIPTION("MRF24J40 SPI 802.15.4 Controller Driver"); |