blob: 14b7d3de68832e58ee9be184e88a768d64f88f0e [file] [log] [blame]
Kalle Valo5e3dd152013-06-12 20:52:10 +03001/*
2 * Copyright (c) 2005-2011 Atheros Communications Inc.
3 * Copyright (c) 2011-2013 Qualcomm Atheros, Inc.
4 *
5 * Permission to use, copy, modify, and/or distribute this software for any
6 * purpose with or without fee is hereby granted, provided that the above
7 * copyright notice and this permission notice appear in all copies.
8 *
9 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
10 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
11 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
12 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
13 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
14 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
15 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
16 */
17
18#ifndef _CORE_H_
19#define _CORE_H_
20
21#include <linux/completion.h>
22#include <linux/if_ether.h>
23#include <linux/types.h>
24#include <linux/pci.h>
25
Michal Kazioredb82362013-07-05 16:15:14 +030026#include "htt.h"
Kalle Valo5e3dd152013-06-12 20:52:10 +030027#include "htc.h"
28#include "hw.h"
29#include "targaddrs.h"
30#include "wmi.h"
31#include "../ath.h"
32#include "../regd.h"
33
34#define MS(_v, _f) (((_v) & _f##_MASK) >> _f##_LSB)
35#define SM(_v, _f) (((_v) << _f##_LSB) & _f##_MASK)
36#define WO(_f) ((_f##_OFFSET) >> 2)
37
38#define ATH10K_SCAN_ID 0
39#define WMI_READY_TIMEOUT (5 * HZ)
40#define ATH10K_FLUSH_TIMEOUT_HZ (5*HZ)
Michal Kazior2e1dea42013-07-31 10:32:40 +020041#define ATH10K_NUM_CHANS 38
Kalle Valo5e3dd152013-06-12 20:52:10 +030042
43/* Antenna noise floor */
44#define ATH10K_DEFAULT_NOISE_FLOOR -95
45
46struct ath10k;
47
Kalle Valo5e3dd152013-06-12 20:52:10 +030048struct ath10k_skb_cb {
49 dma_addr_t paddr;
50 bool is_mapped;
51 bool is_aborted;
52
53 struct {
54 u8 vdev_id;
55 u16 msdu_id;
56 u8 tid;
57 bool is_offchan;
58 bool is_conf;
59 bool discard;
60 bool no_ack;
61 u8 refcount;
62 struct sk_buff *txfrag;
63 struct sk_buff *msdu;
64 } __packed htt;
65
66 /* 4 bytes left on 64bit arch */
67} __packed;
68
69static inline struct ath10k_skb_cb *ATH10K_SKB_CB(struct sk_buff *skb)
70{
71 BUILD_BUG_ON(sizeof(struct ath10k_skb_cb) >
72 IEEE80211_TX_INFO_DRIVER_DATA_SIZE);
73 return (struct ath10k_skb_cb *)&IEEE80211_SKB_CB(skb)->driver_data;
74}
75
76static inline int ath10k_skb_map(struct device *dev, struct sk_buff *skb)
77{
78 if (ATH10K_SKB_CB(skb)->is_mapped)
79 return -EINVAL;
80
81 ATH10K_SKB_CB(skb)->paddr = dma_map_single(dev, skb->data, skb->len,
82 DMA_TO_DEVICE);
83
84 if (unlikely(dma_mapping_error(dev, ATH10K_SKB_CB(skb)->paddr)))
85 return -EIO;
86
87 ATH10K_SKB_CB(skb)->is_mapped = true;
88 return 0;
89}
90
91static inline int ath10k_skb_unmap(struct device *dev, struct sk_buff *skb)
92{
93 if (!ATH10K_SKB_CB(skb)->is_mapped)
94 return -EINVAL;
95
96 dma_unmap_single(dev, ATH10K_SKB_CB(skb)->paddr, skb->len,
97 DMA_TO_DEVICE);
98 ATH10K_SKB_CB(skb)->is_mapped = false;
99 return 0;
100}
101
102static inline u32 host_interest_item_address(u32 item_offset)
103{
104 return QCA988X_HOST_INTEREST_ADDRESS + item_offset;
105}
106
107struct ath10k_bmi {
108 bool done_sent;
109};
110
111struct ath10k_wmi {
112 enum ath10k_htc_ep_id eid;
113 struct completion service_ready;
114 struct completion unified_ready;
115 atomic_t pending_tx_count;
116 wait_queue_head_t wq;
Michal Kaziorbe8b3942013-09-13 14:16:54 +0200117 wait_queue_head_t tx_credits_wq;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300118
119 struct sk_buff_head wmi_event_list;
120 struct work_struct wmi_event_work;
121};
122
123struct ath10k_peer_stat {
124 u8 peer_macaddr[ETH_ALEN];
125 u32 peer_rssi;
126 u32 peer_tx_rate;
127};
128
129struct ath10k_target_stats {
130 /* PDEV stats */
131 s32 ch_noise_floor;
132 u32 tx_frame_count;
133 u32 rx_frame_count;
134 u32 rx_clear_count;
135 u32 cycle_count;
136 u32 phy_err_count;
137 u32 chan_tx_power;
138
139 /* PDEV TX stats */
140 s32 comp_queued;
141 s32 comp_delivered;
142 s32 msdu_enqued;
143 s32 mpdu_enqued;
144 s32 wmm_drop;
145 s32 local_enqued;
146 s32 local_freed;
147 s32 hw_queued;
148 s32 hw_reaped;
149 s32 underrun;
150 s32 tx_abort;
151 s32 mpdus_requed;
152 u32 tx_ko;
153 u32 data_rc;
154 u32 self_triggers;
155 u32 sw_retry_failure;
156 u32 illgl_rate_phy_err;
157 u32 pdev_cont_xretry;
158 u32 pdev_tx_timeout;
159 u32 pdev_resets;
160 u32 phy_underrun;
161 u32 txop_ovf;
162
163 /* PDEV RX stats */
164 s32 mid_ppdu_route_change;
165 s32 status_rcvd;
166 s32 r0_frags;
167 s32 r1_frags;
168 s32 r2_frags;
169 s32 r3_frags;
170 s32 htt_msdus;
171 s32 htt_mpdus;
172 s32 loc_msdus;
173 s32 loc_mpdus;
174 s32 oversize_amsdu;
175 s32 phy_errs;
176 s32 phy_err_drop;
177 s32 mpdu_errs;
178
179 /* VDEV STATS */
180
181 /* PEER STATS */
182 u8 peers;
183 struct ath10k_peer_stat peer_stat[TARGET_NUM_PEERS];
184
185 /* TODO: Beacon filter stats */
186
187};
188
189#define ATH10K_MAX_NUM_PEER_IDS (1 << 11) /* htt rx_desc limit */
190
191struct ath10k_peer {
192 struct list_head list;
193 int vdev_id;
194 u8 addr[ETH_ALEN];
195 DECLARE_BITMAP(peer_ids, ATH10K_MAX_NUM_PEER_IDS);
196 struct ieee80211_key_conf *keys[WMI_MAX_KEY_INDEX + 1];
197};
198
199#define ATH10K_VDEV_SETUP_TIMEOUT_HZ (5*HZ)
200
201struct ath10k_vif {
202 u32 vdev_id;
203 enum wmi_vdev_type vdev_type;
204 enum wmi_vdev_subtype vdev_subtype;
205 u32 beacon_interval;
206 u32 dtim_period;
Michal Kaziored543882013-09-13 14:16:56 +0200207 struct sk_buff *beacon;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300208
209 struct ath10k *ar;
210 struct ieee80211_vif *vif;
211
212 struct ieee80211_key_conf *wep_keys[WMI_MAX_KEY_INDEX + 1];
213 u8 def_wep_key_index;
214
215 u16 tx_seq_no;
216
217 union {
218 struct {
219 u8 bssid[ETH_ALEN];
220 u32 uapsd;
221 } sta;
222 struct {
223 /* 127 stations; wmi limit */
224 u8 tim_bitmap[16];
225 u8 tim_len;
226 u32 ssid_len;
227 u8 ssid[IEEE80211_MAX_SSID_LEN];
228 bool hidden_ssid;
229 /* P2P_IE with NoA attribute for P2P_GO case */
230 u32 noa_len;
231 u8 *noa_data;
232 } ap;
233 struct {
234 u8 bssid[ETH_ALEN];
235 } ibss;
236 } u;
237};
238
239struct ath10k_vif_iter {
240 u32 vdev_id;
241 struct ath10k_vif *arvif;
242};
243
244struct ath10k_debug {
245 struct dentry *debugfs_phy;
246
247 struct ath10k_target_stats target_stats;
248 u32 wmi_service_bitmap[WMI_SERVICE_BM_SIZE];
249
250 struct completion event_stats_compl;
Kalle Valoa3d135e2013-09-03 11:44:10 +0300251
252 unsigned long htt_stats_mask;
253 struct delayed_work htt_stats_dwork;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300254};
255
Michal Kaziorf7843d72013-07-16 09:38:52 +0200256enum ath10k_state {
257 ATH10K_STATE_OFF = 0,
258 ATH10K_STATE_ON,
Michal Kazioraffd3212013-07-16 09:54:35 +0200259
260 /* When doing firmware recovery the device is first powered down.
261 * mac80211 is supposed to call in to start() hook later on. It is
262 * however possible that driver unloading and firmware crash overlap.
263 * mac80211 can wait on conf_mutex in stop() while the device is
264 * stopped in ath10k_core_restart() work holding conf_mutex. The state
265 * RESTARTED means that the device is up and mac80211 has started hw
266 * reconfiguration. Once mac80211 is done with the reconfiguration we
267 * set the state to STATE_ON in restart_complete(). */
268 ATH10K_STATE_RESTARTING,
269 ATH10K_STATE_RESTARTED,
270
271 /* The device has crashed while restarting hw. This state is like ON
272 * but commands are blocked in HTC and -ECOMM response is given. This
273 * prevents completion timeouts and makes the driver more responsive to
274 * userspace commands. This is also prevents recursive recovery. */
275 ATH10K_STATE_WEDGED,
Michal Kaziorf7843d72013-07-16 09:38:52 +0200276};
277
Michal Kazior0d9b0432013-08-09 10:13:33 +0200278enum ath10k_fw_features {
279 /* wmi_mgmt_rx_hdr contains extra RSSI information */
280 ATH10K_FW_FEATURE_EXT_WMI_MGMT_RX = 0,
281
282 /* keep last */
283 ATH10K_FW_FEATURE_COUNT,
284};
285
Kalle Valo5e3dd152013-06-12 20:52:10 +0300286struct ath10k {
287 struct ath_common ath_common;
288 struct ieee80211_hw *hw;
289 struct device *dev;
290 u8 mac_addr[ETH_ALEN];
291
Kalle Valoe01ae682013-09-01 11:22:14 +0300292 u32 chip_id;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300293 u32 target_version;
294 u8 fw_version_major;
295 u32 fw_version_minor;
296 u16 fw_version_release;
297 u16 fw_version_build;
298 u32 phy_capability;
299 u32 hw_min_tx_power;
300 u32 hw_max_tx_power;
301 u32 ht_cap_info;
302 u32 vht_cap_info;
Michal Kazior8865bee42013-07-24 12:36:46 +0200303 u32 num_rf_chains;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300304
Michal Kazior0d9b0432013-08-09 10:13:33 +0200305 DECLARE_BITMAP(fw_features, ATH10K_FW_FEATURE_COUNT);
306
Kalle Valo5e3dd152013-06-12 20:52:10 +0300307 struct targetdef *targetdef;
308 struct hostdef *hostdef;
309
310 bool p2p;
311
312 struct {
313 void *priv;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300314 const struct ath10k_hif_ops *ops;
315 } hif;
316
Kalle Valo5e3dd152013-06-12 20:52:10 +0300317 wait_queue_head_t event_queue;
318 bool is_target_paused;
319
320 struct ath10k_bmi bmi;
Michal Kazioredb82362013-07-05 16:15:14 +0300321 struct ath10k_wmi wmi;
Michal Kaziorcd003fa2013-07-05 16:15:13 +0300322 struct ath10k_htc htc;
Michal Kazioredb82362013-07-05 16:15:14 +0300323 struct ath10k_htt htt;
Kalle Valo5e3dd152013-06-12 20:52:10 +0300324
325 struct ath10k_hw_params {
326 u32 id;
327 const char *name;
328 u32 patch_load_addr;
329
330 struct ath10k_hw_params_fw {
331 const char *dir;
332 const char *fw;
333 const char *otp;
334 const char *board;
335 } fw;
336 } hw_params;
337
Michal Kazior29385052013-07-16 09:38:58 +0200338 const struct firmware *board_data;
339 const struct firmware *otp;
340 const struct firmware *firmware;
341
Kalle Valo5e3dd152013-06-12 20:52:10 +0300342 struct {
343 struct completion started;
344 struct completion completed;
345 struct completion on_channel;
346 struct timer_list timeout;
347 bool is_roc;
348 bool in_progress;
349 bool aborting;
350 int vdev_id;
351 int roc_freq;
352 } scan;
353
354 struct {
355 struct ieee80211_supported_band sbands[IEEE80211_NUM_BANDS];
356 } mac;
357
358 /* should never be NULL; needed for regular htt rx */
359 struct ieee80211_channel *rx_channel;
360
361 /* valid during scan; needed for mgmt rx during scan */
362 struct ieee80211_channel *scan_channel;
363
364 int free_vdev_map;
365 int monitor_vdev_id;
366 bool monitor_enabled;
367 bool monitor_present;
368 unsigned int filter_flags;
369
370 struct wmi_pdev_set_wmm_params_arg wmm_params;
371 struct completion install_key_done;
372
373 struct completion vdev_setup_done;
374
375 struct workqueue_struct *workqueue;
376
377 /* prevents concurrent FW reconfiguration */
378 struct mutex conf_mutex;
379
380 /* protects shared structure data */
381 spinlock_t data_lock;
382
383 struct list_head peers;
384 wait_queue_head_t peer_mapping_wq;
385
386 struct work_struct offchan_tx_work;
387 struct sk_buff_head offchan_tx_queue;
388 struct completion offchan_tx_completed;
389 struct sk_buff *offchan_tx_skb;
390
Michal Kaziorf7843d72013-07-16 09:38:52 +0200391 enum ath10k_state state;
392
Michal Kazioraffd3212013-07-16 09:54:35 +0200393 struct work_struct restart_work;
394
Michal Kazior2e1dea42013-07-31 10:32:40 +0200395 /* cycle count is reported twice for each visited channel during scan.
396 * access protected by data_lock */
397 u32 survey_last_rx_clear_count;
398 u32 survey_last_cycle_count;
399 struct survey_info survey[ATH10K_NUM_CHANS];
400
Kalle Valo5e3dd152013-06-12 20:52:10 +0300401#ifdef CONFIG_ATH10K_DEBUGFS
402 struct ath10k_debug debug;
403#endif
404};
405
406struct ath10k *ath10k_core_create(void *hif_priv, struct device *dev,
Kalle Valo5e3dd152013-06-12 20:52:10 +0300407 const struct ath10k_hif_ops *hif_ops);
408void ath10k_core_destroy(struct ath10k *ar);
409
Michal Kaziordd30a362013-07-16 09:38:51 +0200410int ath10k_core_start(struct ath10k *ar);
411void ath10k_core_stop(struct ath10k *ar);
Kalle Valoe01ae682013-09-01 11:22:14 +0300412int ath10k_core_register(struct ath10k *ar, u32 chip_id);
Kalle Valo5e3dd152013-06-12 20:52:10 +0300413void ath10k_core_unregister(struct ath10k *ar);
414
Kalle Valo5e3dd152013-06-12 20:52:10 +0300415#endif /* _CORE_H_ */