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gerrit-public.fairphone.software / kernel / msm-4.9 / f263839ab59a7f4beb74fc9a7ce0234b62ab2b52 / . / arch / mips / include / uapi / asm / inst.h
blob: e6e7fe372cbd65610b98aea2548de93cacd8d38d [file] [log] [blame]
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]1/*
2 * Format of an instruction in memory.
3 *
4 * This file is subject to the terms and conditions of the GNU General Public
5 * License. See the file "COPYING" in the main directory of this archive
6 * for more details.
7 *
8 * Copyright (C) 1996, 2000 by Ralf Baechle
9 * Copyright (C) 2006 by Thiemo Seufer
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]10 * Copyright (C) 2012 MIPS Technologies, Inc. All rights reserved.
Leonid Yegoshinaa1af472013-12-04 11:06:57 +0000[diff] [blame]11 * Copyright (C) 2014 Imagination Technologies Ltd.
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]12 */
13#ifndef _UAPI_ASM_INST_H
14#define _UAPI_ASM_INST_H
15
16/*
17 * Major opcodes; before MIPS IV cop1x was called cop3.
18 */
19enum major_op {
20 spec_op, bcond_op, j_op, jal_op,
21 beq_op, bne_op, blez_op, bgtz_op,
22 addi_op, addiu_op, slti_op, sltiu_op,
23 andi_op, ori_op, xori_op, lui_op,
24 cop0_op, cop1_op, cop2_op, cop1x_op,
25 beql_op, bnel_op, blezl_op, bgtzl_op,
26 daddi_op, daddiu_op, ldl_op, ldr_op,
27 spec2_op, jalx_op, mdmx_op, spec3_op,
28 lb_op, lh_op, lwl_op, lw_op,
29 lbu_op, lhu_op, lwr_op, lwu_op,
30 sb_op, sh_op, swl_op, sw_op,
31 sdl_op, sdr_op, swr_op, cache_op,
32 ll_op, lwc1_op, lwc2_op, pref_op,
33 lld_op, ldc1_op, ldc2_op, ld_op,
34 sc_op, swc1_op, swc2_op, major_3b_op,
35 scd_op, sdc1_op, sdc2_op, sd_op
36};
37
38/*
39 * func field of spec opcode.
40 */
41enum spec_op {
42 sll_op, movc_op, srl_op, sra_op,
43 sllv_op, pmon_op, srlv_op, srav_op,
44 jr_op, jalr_op, movz_op, movn_op,
45 syscall_op, break_op, spim_op, sync_op,
46 mfhi_op, mthi_op, mflo_op, mtlo_op,
47 dsllv_op, spec2_unused_op, dsrlv_op, dsrav_op,
48 mult_op, multu_op, div_op, divu_op,
49 dmult_op, dmultu_op, ddiv_op, ddivu_op,
50 add_op, addu_op, sub_op, subu_op,
51 and_op, or_op, xor_op, nor_op,
52 spec3_unused_op, spec4_unused_op, slt_op, sltu_op,
53 dadd_op, daddu_op, dsub_op, dsubu_op,
54 tge_op, tgeu_op, tlt_op, tltu_op,
55 teq_op, spec5_unused_op, tne_op, spec6_unused_op,
56 dsll_op, spec7_unused_op, dsrl_op, dsra_op,
57 dsll32_op, spec8_unused_op, dsrl32_op, dsra32_op
58};
59
60/*
61 * func field of spec2 opcode.
62 */
63enum spec2_op {
64 madd_op, maddu_op, mul_op, spec2_3_unused_op,
65 msub_op, msubu_op, /* more unused ops */
66 clz_op = 0x20, clo_op,
67 dclz_op = 0x24, dclo_op,
68 sdbpp_op = 0x3f
69};
70
71/*
72 * func field of spec3 opcode.
73 */
74enum spec3_op {
75 ext_op, dextm_op, dextu_op, dext_op,
76 ins_op, dinsm_op, dinsu_op, dins_op,
Paul Burton6f5bb422014-03-04 15:11:12 +0000[diff] [blame]77 yield_op = 0x09, lx_op = 0x0a,
78 lwle_op = 0x19, lwre_op = 0x1a,
79 cachee_op = 0x1b, sbe_op = 0x1c,
80 she_op = 0x1d, sce_op = 0x1e,
81 swe_op = 0x1f, bshfl_op = 0x20,
82 swle_op = 0x21, swre_op = 0x22,
83 prefe_op = 0x23, dbshfl_op = 0x24,
84 lbue_op = 0x28, lhue_op = 0x29,
85 lbe_op = 0x2c, lhe_op = 0x2d,
86 lle_op = 0x2e, lwe_op = 0x2f,
87 rdhwr_op = 0x3b
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]88};
89
90/*
91 * rt field of bcond opcodes.
92 */
93enum rt_op {
94 bltz_op, bgez_op, bltzl_op, bgezl_op,
95 spimi_op, unused_rt_op_0x05, unused_rt_op_0x06, unused_rt_op_0x07,
96 tgei_op, tgeiu_op, tlti_op, tltiu_op,
97 teqi_op, unused_0x0d_rt_op, tnei_op, unused_0x0f_rt_op,
98 bltzal_op, bgezal_op, bltzall_op, bgezall_op,
99 rt_op_0x14, rt_op_0x15, rt_op_0x16, rt_op_0x17,
100 rt_op_0x18, rt_op_0x19, rt_op_0x1a, rt_op_0x1b,
101 bposge32_op, rt_op_0x1d, rt_op_0x1e, rt_op_0x1f
102};
103
104/*
105 * rs field of cop opcodes.
106 */
107enum cop_op {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]108 mfc_op = 0x00, dmfc_op = 0x01,
Leonid Yegoshin1ac944002013-11-07 12:48:28 +0000[diff] [blame]109 cfc_op = 0x02, mfhc_op = 0x03,
110 mtc_op = 0x04, dmtc_op = 0x05,
111 ctc_op = 0x06, mthc_op = 0x07,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]112 bc_op = 0x08, cop_op = 0x10,
113 copm_op = 0x18
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]114};
115
116/*
117 * rt field of cop.bc_op opcodes
118 */
119enum bcop_op {
120 bcf_op, bct_op, bcfl_op, bctl_op
121};
122
123/*
124 * func field of cop0 coi opcodes.
125 */
126enum cop0_coi_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]127 tlbr_op = 0x01, tlbwi_op = 0x02,
128 tlbwr_op = 0x06, tlbp_op = 0x08,
Paul Burtonb0a3eae2013-12-24 03:44:28 +0000[diff] [blame]129 rfe_op = 0x10, eret_op = 0x18,
130 wait_op = 0x20,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]131};
132
133/*
134 * func field of cop0 com opcodes.
135 */
136enum cop0_com_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]137 tlbr1_op = 0x01, tlbw_op = 0x02,
138 tlbp1_op = 0x08, dctr_op = 0x09,
139 dctw_op = 0x0a
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]140};
141
142/*
143 * fmt field of cop1 opcodes.
144 */
145enum cop1_fmt {
146 s_fmt, d_fmt, e_fmt, q_fmt,
147 w_fmt, l_fmt
148};
149
150/*
151 * func field of cop1 instructions using d, s or w format.
152 */
153enum cop1_sdw_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]154 fadd_op = 0x00, fsub_op = 0x01,
155 fmul_op = 0x02, fdiv_op = 0x03,
156 fsqrt_op = 0x04, fabs_op = 0x05,
157 fmov_op = 0x06, fneg_op = 0x07,
158 froundl_op = 0x08, ftruncl_op = 0x09,
159 fceill_op = 0x0a, ffloorl_op = 0x0b,
160 fround_op = 0x0c, ftrunc_op = 0x0d,
161 fceil_op = 0x0e, ffloor_op = 0x0f,
162 fmovc_op = 0x11, fmovz_op = 0x12,
163 fmovn_op = 0x13, frecip_op = 0x15,
164 frsqrt_op = 0x16, fcvts_op = 0x20,
165 fcvtd_op = 0x21, fcvte_op = 0x22,
166 fcvtw_op = 0x24, fcvtl_op = 0x25,
167 fcmp_op = 0x30
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]168};
169
170/*
171 * func field of cop1x opcodes (MIPS IV).
172 */
173enum cop1x_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]174 lwxc1_op = 0x00, ldxc1_op = 0x01,
Deng-Cheng Zhu51061b82014-03-06 17:05:27 -0800[diff] [blame]175 swxc1_op = 0x08, sdxc1_op = 0x09,
176 pfetch_op = 0x0f, madd_s_op = 0x20,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]177 madd_d_op = 0x21, madd_e_op = 0x22,
178 msub_s_op = 0x28, msub_d_op = 0x29,
179 msub_e_op = 0x2a, nmadd_s_op = 0x30,
180 nmadd_d_op = 0x31, nmadd_e_op = 0x32,
181 nmsub_s_op = 0x38, nmsub_d_op = 0x39,
182 nmsub_e_op = 0x3a
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]183};
184
185/*
186 * func field for mad opcodes (MIPS IV).
187 */
188enum mad_func {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]189 madd_fp_op = 0x08, msub_fp_op = 0x0a,
190 nmadd_fp_op = 0x0c, nmsub_fp_op = 0x0e
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]191};
192
193/*
194 * func field for special3 lx opcodes (Cavium Octeon).
195 */
196enum lx_func {
197 lwx_op = 0x00,
198 lhx_op = 0x04,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]199 lbux_op = 0x06,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]200 ldx_op = 0x08,
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]201 lwux_op = 0x10,
202 lhux_op = 0x14,
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]203 lbx_op = 0x16,
204};
205
206/*
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]207 * (microMIPS) Major opcodes.
208 */
209enum mm_major_op {
210 mm_pool32a_op, mm_pool16a_op, mm_lbu16_op, mm_move16_op,
211 mm_addi32_op, mm_lbu32_op, mm_sb32_op, mm_lb32_op,
212 mm_pool32b_op, mm_pool16b_op, mm_lhu16_op, mm_andi16_op,
213 mm_addiu32_op, mm_lhu32_op, mm_sh32_op, mm_lh32_op,
214 mm_pool32i_op, mm_pool16c_op, mm_lwsp16_op, mm_pool16d_op,
215 mm_ori32_op, mm_pool32f_op, mm_reserved1_op, mm_reserved2_op,
216 mm_pool32c_op, mm_lwgp16_op, mm_lw16_op, mm_pool16e_op,
217 mm_xori32_op, mm_jals32_op, mm_addiupc_op, mm_reserved3_op,
218 mm_reserved4_op, mm_pool16f_op, mm_sb16_op, mm_beqz16_op,
219 mm_slti32_op, mm_beq32_op, mm_swc132_op, mm_lwc132_op,
220 mm_reserved5_op, mm_reserved6_op, mm_sh16_op, mm_bnez16_op,
221 mm_sltiu32_op, mm_bne32_op, mm_sdc132_op, mm_ldc132_op,
222 mm_reserved7_op, mm_reserved8_op, mm_swsp16_op, mm_b16_op,
223 mm_andi32_op, mm_j32_op, mm_sd32_op, mm_ld32_op,
224 mm_reserved11_op, mm_reserved12_op, mm_sw16_op, mm_li16_op,
225 mm_jalx32_op, mm_jal32_op, mm_sw32_op, mm_lw32_op,
226};
227
228/*
229 * (microMIPS) POOL32I minor opcodes.
230 */
231enum mm_32i_minor_op {
232 mm_bltz_op, mm_bltzal_op, mm_bgez_op, mm_bgezal_op,
233 mm_blez_op, mm_bnezc_op, mm_bgtz_op, mm_beqzc_op,
234 mm_tlti_op, mm_tgei_op, mm_tltiu_op, mm_tgeiu_op,
235 mm_tnei_op, mm_lui_op, mm_teqi_op, mm_reserved13_op,
236 mm_synci_op, mm_bltzals_op, mm_reserved14_op, mm_bgezals_op,
237 mm_bc2f_op, mm_bc2t_op, mm_reserved15_op, mm_reserved16_op,
238 mm_reserved17_op, mm_reserved18_op, mm_bposge64_op, mm_bposge32_op,
239 mm_bc1f_op, mm_bc1t_op, mm_reserved19_op, mm_reserved20_op,
240 mm_bc1any2f_op, mm_bc1any2t_op, mm_bc1any4f_op, mm_bc1any4t_op,
241};
242
243/*
244 * (microMIPS) POOL32A minor opcodes.
245 */
246enum mm_32a_minor_op {
247 mm_sll32_op = 0x000,
248 mm_ins_op = 0x00c,
249 mm_ext_op = 0x02c,
250 mm_pool32axf_op = 0x03c,
251 mm_srl32_op = 0x040,
252 mm_sra_op = 0x080,
253 mm_rotr_op = 0x0c0,
254 mm_lwxs_op = 0x118,
255 mm_addu32_op = 0x150,
256 mm_subu32_op = 0x1d0,
257 mm_and_op = 0x250,
258 mm_or32_op = 0x290,
259 mm_xor32_op = 0x310,
260};
261
262/*
263 * (microMIPS) POOL32B functions.
264 */
265enum mm_32b_func {
266 mm_lwc2_func = 0x0,
267 mm_lwp_func = 0x1,
268 mm_ldc2_func = 0x2,
269 mm_ldp_func = 0x4,
270 mm_lwm32_func = 0x5,
271 mm_cache_func = 0x6,
272 mm_ldm_func = 0x7,
273 mm_swc2_func = 0x8,
274 mm_swp_func = 0x9,
275 mm_sdc2_func = 0xa,
276 mm_sdp_func = 0xc,
277 mm_swm32_func = 0xd,
278 mm_sdm_func = 0xf,
279};
280
281/*
282 * (microMIPS) POOL32C functions.
283 */
284enum mm_32c_func {
285 mm_pref_func = 0x2,
286 mm_ll_func = 0x3,
287 mm_swr_func = 0x9,
288 mm_sc_func = 0xb,
289 mm_lwu_func = 0xe,
290};
291
292/*
293 * (microMIPS) POOL32AXF minor opcodes.
294 */
295enum mm_32axf_minor_op {
296 mm_mfc0_op = 0x003,
297 mm_mtc0_op = 0x00b,
298 mm_tlbp_op = 0x00d,
299 mm_jalr_op = 0x03c,
300 mm_tlbr_op = 0x04d,
301 mm_jalrhb_op = 0x07c,
302 mm_tlbwi_op = 0x08d,
303 mm_tlbwr_op = 0x0cd,
304 mm_jalrs_op = 0x13c,
305 mm_jalrshb_op = 0x17c,
Paul Burton7ed82ad2014-01-09 15:27:32 +0000[diff] [blame]306 mm_sync_op = 0x1ad,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]307 mm_syscall_op = 0x22d,
Paul Burtonf2638392014-01-09 15:30:37 +0000[diff] [blame^]308 mm_wait_op = 0x24d,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]309 mm_eret_op = 0x3cd,
310};
311
312/*
313 * (microMIPS) POOL32F minor opcodes.
314 */
315enum mm_32f_minor_op {
316 mm_32f_00_op = 0x00,
317 mm_32f_01_op = 0x01,
318 mm_32f_02_op = 0x02,
319 mm_32f_10_op = 0x08,
320 mm_32f_11_op = 0x09,
321 mm_32f_12_op = 0x0a,
322 mm_32f_20_op = 0x10,
323 mm_32f_30_op = 0x18,
324 mm_32f_40_op = 0x20,
325 mm_32f_41_op = 0x21,
326 mm_32f_42_op = 0x22,
327 mm_32f_50_op = 0x28,
328 mm_32f_51_op = 0x29,
329 mm_32f_52_op = 0x2a,
330 mm_32f_60_op = 0x30,
331 mm_32f_70_op = 0x38,
332 mm_32f_73_op = 0x3b,
333 mm_32f_74_op = 0x3c,
334};
335
336/*
337 * (microMIPS) POOL32F secondary minor opcodes.
338 */
339enum mm_32f_10_minor_op {
340 mm_lwxc1_op = 0x1,
341 mm_swxc1_op,
342 mm_ldxc1_op,
343 mm_sdxc1_op,
344 mm_luxc1_op,
345 mm_suxc1_op,
346};
347
348enum mm_32f_func {
349 mm_lwxc1_func = 0x048,
350 mm_swxc1_func = 0x088,
351 mm_ldxc1_func = 0x0c8,
352 mm_sdxc1_func = 0x108,
353};
354
355/*
356 * (microMIPS) POOL32F secondary minor opcodes.
357 */
358enum mm_32f_40_minor_op {
359 mm_fmovf_op,
360 mm_fmovt_op,
361};
362
363/*
364 * (microMIPS) POOL32F secondary minor opcodes.
365 */
366enum mm_32f_60_minor_op {
367 mm_fadd_op,
368 mm_fsub_op,
369 mm_fmul_op,
370 mm_fdiv_op,
371};
372
373/*
374 * (microMIPS) POOL32F secondary minor opcodes.
375 */
376enum mm_32f_70_minor_op {
377 mm_fmovn_op,
378 mm_fmovz_op,
379};
380
381/*
382 * (microMIPS) POOL32FXF secondary minor opcodes for POOL32F.
383 */
384enum mm_32f_73_minor_op {
385 mm_fmov0_op = 0x01,
386 mm_fcvtl_op = 0x04,
387 mm_movf0_op = 0x05,
388 mm_frsqrt_op = 0x08,
389 mm_ffloorl_op = 0x0c,
390 mm_fabs0_op = 0x0d,
391 mm_fcvtw_op = 0x24,
392 mm_movt0_op = 0x25,
393 mm_fsqrt_op = 0x28,
394 mm_ffloorw_op = 0x2c,
395 mm_fneg0_op = 0x2d,
396 mm_cfc1_op = 0x40,
397 mm_frecip_op = 0x48,
398 mm_fceill_op = 0x4c,
399 mm_fcvtd0_op = 0x4d,
400 mm_ctc1_op = 0x60,
401 mm_fceilw_op = 0x6c,
402 mm_fcvts0_op = 0x6d,
403 mm_mfc1_op = 0x80,
404 mm_fmov1_op = 0x81,
405 mm_movf1_op = 0x85,
406 mm_ftruncl_op = 0x8c,
407 mm_fabs1_op = 0x8d,
408 mm_mtc1_op = 0xa0,
409 mm_movt1_op = 0xa5,
410 mm_ftruncw_op = 0xac,
411 mm_fneg1_op = 0xad,
Steven J. Hill9355e592013-11-07 12:48:29 +0000[diff] [blame]412 mm_mfhc1_op = 0xc0,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]413 mm_froundl_op = 0xcc,
414 mm_fcvtd1_op = 0xcd,
Steven J. Hill9355e592013-11-07 12:48:29 +0000[diff] [blame]415 mm_mthc1_op = 0xe0,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]416 mm_froundw_op = 0xec,
417 mm_fcvts1_op = 0xed,
418};
419
420/*
421 * (microMIPS) POOL16C minor opcodes.
422 */
423enum mm_16c_minor_op {
424 mm_lwm16_op = 0x04,
425 mm_swm16_op = 0x05,
Tony Wudfb033f2013-06-20 12:32:30 +0000[diff] [blame]426 mm_jr16_op = 0x0c,
427 mm_jrc_op = 0x0d,
428 mm_jalr16_op = 0x0e,
429 mm_jalrs16_op = 0x0f,
430 mm_jraddiusp_op = 0x18,
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]431};
432
433/*
434 * (microMIPS) POOL16D minor opcodes.
435 */
436enum mm_16d_minor_op {
437 mm_addius5_func,
438 mm_addiusp_func,
439};
440
441/*
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]442 * (MIPS16e) opcodes.
443 */
444enum MIPS16e_ops {
445 MIPS16e_jal_op = 003,
446 MIPS16e_ld_op = 007,
447 MIPS16e_i8_op = 014,
448 MIPS16e_sd_op = 017,
449 MIPS16e_lb_op = 020,
450 MIPS16e_lh_op = 021,
451 MIPS16e_lwsp_op = 022,
452 MIPS16e_lw_op = 023,
453 MIPS16e_lbu_op = 024,
454 MIPS16e_lhu_op = 025,
455 MIPS16e_lwpc_op = 026,
456 MIPS16e_lwu_op = 027,
457 MIPS16e_sb_op = 030,
458 MIPS16e_sh_op = 031,
459 MIPS16e_swsp_op = 032,
460 MIPS16e_sw_op = 033,
461 MIPS16e_rr_op = 035,
462 MIPS16e_extend_op = 036,
463 MIPS16e_i64_op = 037,
464};
465
466enum MIPS16e_i64_func {
467 MIPS16e_ldsp_func,
468 MIPS16e_sdsp_func,
469 MIPS16e_sdrasp_func,
470 MIPS16e_dadjsp_func,
471 MIPS16e_ldpc_func,
472};
473
474enum MIPS16e_rr_func {
475 MIPS16e_jr_func,
476};
477
478enum MIPS6e_i8_func {
479 MIPS16e_swrasp_func = 02,
480};
481
482/*
Leonid Yegoshin102cedc2013-03-25 12:09:02 -0500[diff] [blame]483 * (microMIPS & MIPS16e) NOP instruction.
484 */
485#define MM_NOP16 0x0c00
486
487/*
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]488 * Damn ... bitfields depend from byteorder :-(
489 */
490#ifdef __MIPSEB__
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]491#define BITFIELD_FIELD(field, more) \
492 field; \
493 more
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]494
495#elif defined(__MIPSEL__)
496
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]497#define BITFIELD_FIELD(field, more) \
498 more \
499 field;
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]500
501#else /* !defined (__MIPSEB__) && !defined (__MIPSEL__) */
502#error "MIPS but neither __MIPSEL__ nor __MIPSEB__?"
503#endif
504
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]505struct j_format {
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]506 BITFIELD_FIELD(unsigned int opcode : 6, /* Jump format */
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]507 BITFIELD_FIELD(unsigned int target : 26,
508 ;))
509};
510
511struct i_format { /* signed immediate format */
512 BITFIELD_FIELD(unsigned int opcode : 6,
513 BITFIELD_FIELD(unsigned int rs : 5,
514 BITFIELD_FIELD(unsigned int rt : 5,
515 BITFIELD_FIELD(signed int simmediate : 16,
516 ;))))
517};
518
519struct u_format { /* unsigned immediate format */
520 BITFIELD_FIELD(unsigned int opcode : 6,
521 BITFIELD_FIELD(unsigned int rs : 5,
522 BITFIELD_FIELD(unsigned int rt : 5,
523 BITFIELD_FIELD(unsigned int uimmediate : 16,
524 ;))))
525};
526
527struct c_format { /* Cache (>= R6000) format */
528 BITFIELD_FIELD(unsigned int opcode : 6,
529 BITFIELD_FIELD(unsigned int rs : 5,
530 BITFIELD_FIELD(unsigned int c_op : 3,
531 BITFIELD_FIELD(unsigned int cache : 2,
532 BITFIELD_FIELD(unsigned int simmediate : 16,
533 ;)))))
534};
535
536struct r_format { /* Register format */
537 BITFIELD_FIELD(unsigned int opcode : 6,
538 BITFIELD_FIELD(unsigned int rs : 5,
539 BITFIELD_FIELD(unsigned int rt : 5,
540 BITFIELD_FIELD(unsigned int rd : 5,
541 BITFIELD_FIELD(unsigned int re : 5,
542 BITFIELD_FIELD(unsigned int func : 6,
543 ;))))))
544};
545
546struct p_format { /* Performance counter format (R10000) */
547 BITFIELD_FIELD(unsigned int opcode : 6,
548 BITFIELD_FIELD(unsigned int rs : 5,
549 BITFIELD_FIELD(unsigned int rt : 5,
550 BITFIELD_FIELD(unsigned int rd : 5,
551 BITFIELD_FIELD(unsigned int re : 5,
552 BITFIELD_FIELD(unsigned int func : 6,
553 ;))))))
554};
555
Ralf Baechle70342282013-01-22 12:59:30 +0100[diff] [blame]556struct f_format { /* FPU register format */
Ralf Baechle85dfaf02013-01-17 15:28:31 +0100[diff] [blame]557 BITFIELD_FIELD(unsigned int opcode : 6,
558 BITFIELD_FIELD(unsigned int : 1,
559 BITFIELD_FIELD(unsigned int fmt : 4,
560 BITFIELD_FIELD(unsigned int rt : 5,
561 BITFIELD_FIELD(unsigned int rd : 5,
562 BITFIELD_FIELD(unsigned int re : 5,
563 BITFIELD_FIELD(unsigned int func : 6,
564 ;)))))))
565};
566
567struct ma_format { /* FPU multiply and add format (MIPS IV) */
568 BITFIELD_FIELD(unsigned int opcode : 6,
569 BITFIELD_FIELD(unsigned int fr : 5,
570 BITFIELD_FIELD(unsigned int ft : 5,
571 BITFIELD_FIELD(unsigned int fs : 5,
572 BITFIELD_FIELD(unsigned int fd : 5,
573 BITFIELD_FIELD(unsigned int func : 4,
574 BITFIELD_FIELD(unsigned int fmt : 2,
575 ;)))))))
576};
577
578struct b_format { /* BREAK and SYSCALL */
579 BITFIELD_FIELD(unsigned int opcode : 6,
580 BITFIELD_FIELD(unsigned int code : 20,
581 BITFIELD_FIELD(unsigned int func : 6,
582 ;)))
583};
584
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]585struct ps_format { /* MIPS-3D / paired single format */
586 BITFIELD_FIELD(unsigned int opcode : 6,
587 BITFIELD_FIELD(unsigned int rs : 5,
588 BITFIELD_FIELD(unsigned int ft : 5,
589 BITFIELD_FIELD(unsigned int fs : 5,
590 BITFIELD_FIELD(unsigned int fd : 5,
591 BITFIELD_FIELD(unsigned int func : 6,
592 ;))))))
593};
594
595struct v_format { /* MDMX vector format */
596 BITFIELD_FIELD(unsigned int opcode : 6,
597 BITFIELD_FIELD(unsigned int sel : 4,
598 BITFIELD_FIELD(unsigned int fmt : 1,
599 BITFIELD_FIELD(unsigned int vt : 5,
600 BITFIELD_FIELD(unsigned int vs : 5,
601 BITFIELD_FIELD(unsigned int vd : 5,
602 BITFIELD_FIELD(unsigned int func : 6,
603 ;)))))))
604};
605
Leonid Yegoshinaa1af472013-12-04 11:06:57 +0000[diff] [blame]606struct spec3_format { /* SPEC3 */
607 BITFIELD_FIELD(unsigned int opcode:6,
608 BITFIELD_FIELD(unsigned int rs:5,
609 BITFIELD_FIELD(unsigned int rt:5,
610 BITFIELD_FIELD(signed int simmediate:9,
611 BITFIELD_FIELD(unsigned int func:7,
612 ;)))))
613};
614
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]615/*
616 * microMIPS instruction formats (32-bit length)
617 *
618 * NOTE:
619 * Parenthesis denote whether the format is a microMIPS instruction or
620 * if it is MIPS32 instruction re-encoded for use in the microMIPS ASE.
621 */
622struct fb_format { /* FPU branch format (MIPS32) */
623 BITFIELD_FIELD(unsigned int opcode : 6,
624 BITFIELD_FIELD(unsigned int bc : 5,
625 BITFIELD_FIELD(unsigned int cc : 3,
626 BITFIELD_FIELD(unsigned int flag : 2,
627 BITFIELD_FIELD(signed int simmediate : 16,
628 ;)))))
629};
630
631struct fp0_format { /* FPU multiply and add format (MIPS32) */
632 BITFIELD_FIELD(unsigned int opcode : 6,
633 BITFIELD_FIELD(unsigned int fmt : 5,
634 BITFIELD_FIELD(unsigned int ft : 5,
635 BITFIELD_FIELD(unsigned int fs : 5,
636 BITFIELD_FIELD(unsigned int fd : 5,
637 BITFIELD_FIELD(unsigned int func : 6,
638 ;))))))
639};
640
641struct mm_fp0_format { /* FPU multipy and add format (microMIPS) */
642 BITFIELD_FIELD(unsigned int opcode : 6,
643 BITFIELD_FIELD(unsigned int ft : 5,
644 BITFIELD_FIELD(unsigned int fs : 5,
645 BITFIELD_FIELD(unsigned int fd : 5,
646 BITFIELD_FIELD(unsigned int fmt : 3,
647 BITFIELD_FIELD(unsigned int op : 2,
648 BITFIELD_FIELD(unsigned int func : 6,
649 ;)))))))
650};
651
652struct fp1_format { /* FPU mfc1 and cfc1 format (MIPS32) */
653 BITFIELD_FIELD(unsigned int opcode : 6,
654 BITFIELD_FIELD(unsigned int op : 5,
655 BITFIELD_FIELD(unsigned int rt : 5,
656 BITFIELD_FIELD(unsigned int fs : 5,
657 BITFIELD_FIELD(unsigned int fd : 5,
658 BITFIELD_FIELD(unsigned int func : 6,
659 ;))))))
660};
661
662struct mm_fp1_format { /* FPU mfc1 and cfc1 format (microMIPS) */
663 BITFIELD_FIELD(unsigned int opcode : 6,
664 BITFIELD_FIELD(unsigned int rt : 5,
665 BITFIELD_FIELD(unsigned int fs : 5,
666 BITFIELD_FIELD(unsigned int fmt : 2,
667 BITFIELD_FIELD(unsigned int op : 8,
668 BITFIELD_FIELD(unsigned int func : 6,
669 ;))))))
670};
671
672struct mm_fp2_format { /* FPU movt and movf format (microMIPS) */
673 BITFIELD_FIELD(unsigned int opcode : 6,
674 BITFIELD_FIELD(unsigned int fd : 5,
675 BITFIELD_FIELD(unsigned int fs : 5,
676 BITFIELD_FIELD(unsigned int cc : 3,
677 BITFIELD_FIELD(unsigned int zero : 2,
678 BITFIELD_FIELD(unsigned int fmt : 2,
679 BITFIELD_FIELD(unsigned int op : 3,
680 BITFIELD_FIELD(unsigned int func : 6,
681 ;))))))))
682};
683
684struct mm_fp3_format { /* FPU abs and neg format (microMIPS) */
685 BITFIELD_FIELD(unsigned int opcode : 6,
686 BITFIELD_FIELD(unsigned int rt : 5,
687 BITFIELD_FIELD(unsigned int fs : 5,
688 BITFIELD_FIELD(unsigned int fmt : 3,
689 BITFIELD_FIELD(unsigned int op : 7,
690 BITFIELD_FIELD(unsigned int func : 6,
691 ;))))))
692};
693
694struct mm_fp4_format { /* FPU c.cond format (microMIPS) */
695 BITFIELD_FIELD(unsigned int opcode : 6,
696 BITFIELD_FIELD(unsigned int rt : 5,
697 BITFIELD_FIELD(unsigned int fs : 5,
698 BITFIELD_FIELD(unsigned int cc : 3,
699 BITFIELD_FIELD(unsigned int fmt : 3,
700 BITFIELD_FIELD(unsigned int cond : 4,
701 BITFIELD_FIELD(unsigned int func : 6,
702 ;)))))))
703};
704
705struct mm_fp5_format { /* FPU lwxc1 and swxc1 format (microMIPS) */
706 BITFIELD_FIELD(unsigned int opcode : 6,
707 BITFIELD_FIELD(unsigned int index : 5,
708 BITFIELD_FIELD(unsigned int base : 5,
709 BITFIELD_FIELD(unsigned int fd : 5,
710 BITFIELD_FIELD(unsigned int op : 5,
711 BITFIELD_FIELD(unsigned int func : 6,
712 ;))))))
713};
714
715struct fp6_format { /* FPU madd and msub format (MIPS IV) */
716 BITFIELD_FIELD(unsigned int opcode : 6,
717 BITFIELD_FIELD(unsigned int fr : 5,
718 BITFIELD_FIELD(unsigned int ft : 5,
719 BITFIELD_FIELD(unsigned int fs : 5,
720 BITFIELD_FIELD(unsigned int fd : 5,
721 BITFIELD_FIELD(unsigned int func : 6,
722 ;))))))
723};
724
725struct mm_fp6_format { /* FPU madd and msub format (microMIPS) */
726 BITFIELD_FIELD(unsigned int opcode : 6,
727 BITFIELD_FIELD(unsigned int ft : 5,
728 BITFIELD_FIELD(unsigned int fs : 5,
729 BITFIELD_FIELD(unsigned int fd : 5,
730 BITFIELD_FIELD(unsigned int fr : 5,
731 BITFIELD_FIELD(unsigned int func : 6,
732 ;))))))
733};
734
735struct mm_i_format { /* Immediate format (microMIPS) */
736 BITFIELD_FIELD(unsigned int opcode : 6,
737 BITFIELD_FIELD(unsigned int rt : 5,
738 BITFIELD_FIELD(unsigned int rs : 5,
739 BITFIELD_FIELD(signed int simmediate : 16,
740 ;))))
741};
742
743struct mm_m_format { /* Multi-word load/store format (microMIPS) */
744 BITFIELD_FIELD(unsigned int opcode : 6,
745 BITFIELD_FIELD(unsigned int rd : 5,
746 BITFIELD_FIELD(unsigned int base : 5,
747 BITFIELD_FIELD(unsigned int func : 4,
748 BITFIELD_FIELD(signed int simmediate : 12,
749 ;)))))
750};
751
752struct mm_x_format { /* Scaled indexed load format (microMIPS) */
753 BITFIELD_FIELD(unsigned int opcode : 6,
754 BITFIELD_FIELD(unsigned int index : 5,
755 BITFIELD_FIELD(unsigned int base : 5,
756 BITFIELD_FIELD(unsigned int rd : 5,
757 BITFIELD_FIELD(unsigned int func : 11,
758 ;)))))
759};
760
761/*
762 * microMIPS instruction formats (16-bit length)
763 */
764struct mm_b0_format { /* Unconditional branch format (microMIPS) */
765 BITFIELD_FIELD(unsigned int opcode : 6,
766 BITFIELD_FIELD(signed int simmediate : 10,
767 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
768 ;)))
769};
770
771struct mm_b1_format { /* Conditional branch format (microMIPS) */
772 BITFIELD_FIELD(unsigned int opcode : 6,
773 BITFIELD_FIELD(unsigned int rs : 3,
774 BITFIELD_FIELD(signed int simmediate : 7,
775 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
776 ;))))
777};
778
779struct mm16_m_format { /* Multi-word load/store format */
780 BITFIELD_FIELD(unsigned int opcode : 6,
781 BITFIELD_FIELD(unsigned int func : 4,
782 BITFIELD_FIELD(unsigned int rlist : 2,
783 BITFIELD_FIELD(unsigned int imm : 4,
784 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
785 ;)))))
786};
787
788struct mm16_rb_format { /* Signed immediate format */
789 BITFIELD_FIELD(unsigned int opcode : 6,
790 BITFIELD_FIELD(unsigned int rt : 3,
791 BITFIELD_FIELD(unsigned int base : 3,
792 BITFIELD_FIELD(signed int simmediate : 4,
793 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
794 ;)))))
795};
796
797struct mm16_r3_format { /* Load from global pointer format */
798 BITFIELD_FIELD(unsigned int opcode : 6,
799 BITFIELD_FIELD(unsigned int rt : 3,
800 BITFIELD_FIELD(signed int simmediate : 7,
801 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
802 ;))))
803};
804
805struct mm16_r5_format { /* Load/store from stack pointer format */
806 BITFIELD_FIELD(unsigned int opcode : 6,
807 BITFIELD_FIELD(unsigned int rt : 5,
808 BITFIELD_FIELD(signed int simmediate : 5,
809 BITFIELD_FIELD(unsigned int : 16, /* Ignored */
810 ;))))
811};
812
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]813/*
814 * MIPS16e instruction formats (16-bit length)
815 */
816struct m16e_rr {
817 BITFIELD_FIELD(unsigned int opcode : 5,
818 BITFIELD_FIELD(unsigned int rx : 3,
819 BITFIELD_FIELD(unsigned int nd : 1,
820 BITFIELD_FIELD(unsigned int l : 1,
821 BITFIELD_FIELD(unsigned int ra : 1,
822 BITFIELD_FIELD(unsigned int func : 5,
823 ;))))))
824};
825
826struct m16e_jal {
827 BITFIELD_FIELD(unsigned int opcode : 5,
828 BITFIELD_FIELD(unsigned int x : 1,
829 BITFIELD_FIELD(unsigned int imm20_16 : 5,
830 BITFIELD_FIELD(signed int imm25_21 : 5,
831 ;))))
832};
833
834struct m16e_i64 {
835 BITFIELD_FIELD(unsigned int opcode : 5,
836 BITFIELD_FIELD(unsigned int func : 3,
837 BITFIELD_FIELD(unsigned int imm : 8,
838 ;)))
839};
840
841struct m16e_ri64 {
842 BITFIELD_FIELD(unsigned int opcode : 5,
843 BITFIELD_FIELD(unsigned int func : 3,
844 BITFIELD_FIELD(unsigned int ry : 3,
845 BITFIELD_FIELD(unsigned int imm : 5,
846 ;))))
847};
848
849struct m16e_ri {
850 BITFIELD_FIELD(unsigned int opcode : 5,
851 BITFIELD_FIELD(unsigned int rx : 3,
852 BITFIELD_FIELD(unsigned int imm : 8,
853 ;)))
854};
855
856struct m16e_rri {
857 BITFIELD_FIELD(unsigned int opcode : 5,
858 BITFIELD_FIELD(unsigned int rx : 3,
859 BITFIELD_FIELD(unsigned int ry : 3,
860 BITFIELD_FIELD(unsigned int imm : 5,
861 ;))))
862};
863
864struct m16e_i8 {
865 BITFIELD_FIELD(unsigned int opcode : 5,
866 BITFIELD_FIELD(unsigned int func : 3,
867 BITFIELD_FIELD(unsigned int imm : 8,
868 ;)))
869};
870
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]871union mips_instruction {
872 unsigned int word;
873 unsigned short halfword[2];
874 unsigned char byte[4];
875 struct j_format j_format;
876 struct i_format i_format;
877 struct u_format u_format;
878 struct c_format c_format;
879 struct r_format r_format;
880 struct p_format p_format;
881 struct f_format f_format;
882 struct ma_format ma_format;
883 struct b_format b_format;
Ralf Baechle8fba1e52013-01-17 16:29:27 +0100[diff] [blame]884 struct ps_format ps_format;
885 struct v_format v_format;
Leonid Yegoshinaa1af472013-12-04 11:06:57 +0000[diff] [blame]886 struct spec3_format spec3_format;
Steven J. Hill2aa9fd02013-02-05 16:52:00 -0600[diff] [blame]887 struct fb_format fb_format;
888 struct fp0_format fp0_format;
889 struct mm_fp0_format mm_fp0_format;
890 struct fp1_format fp1_format;
891 struct mm_fp1_format mm_fp1_format;
892 struct mm_fp2_format mm_fp2_format;
893 struct mm_fp3_format mm_fp3_format;
894 struct mm_fp4_format mm_fp4_format;
895 struct mm_fp5_format mm_fp5_format;
896 struct fp6_format fp6_format;
897 struct mm_fp6_format mm_fp6_format;
898 struct mm_i_format mm_i_format;
899 struct mm_m_format mm_m_format;
900 struct mm_x_format mm_x_format;
901 struct mm_b0_format mm_b0_format;
902 struct mm_b1_format mm_b1_format;
903 struct mm16_m_format mm16_m_format ;
904 struct mm16_rb_format mm16_rb_format;
905 struct mm16_r3_format mm16_r3_format;
906 struct mm16_r5_format mm16_r5_format;
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]907};
908
Steven J. Hillcd574702013-03-25 13:44:04 -0500[diff] [blame]909union mips16e_instruction {
910 unsigned int full : 16;
911 struct m16e_rr rr;
912 struct m16e_jal jal;
913 struct m16e_i64 i64;
914 struct m16e_ri64 ri64;
915 struct m16e_ri ri;
916 struct m16e_rri rri;
917 struct m16e_i8 i8;
918};
919
Ralf Baechle90e8cac2013-01-17 15:11:16 +0100[diff] [blame]920#endif /* _UAPI_ASM_INST_H */