Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright © 2008 Intel Corporation |
| 3 | * |
| 4 | * Permission is hereby granted, free of charge, to any person obtaining a |
| 5 | * copy of this software and associated documentation files (the "Software"), |
| 6 | * to deal in the Software without restriction, including without limitation |
| 7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, |
| 8 | * and/or sell copies of the Software, and to permit persons to whom the |
| 9 | * Software is furnished to do so, subject to the following conditions: |
| 10 | * |
| 11 | * The above copyright notice and this permission notice (including the next |
| 12 | * paragraph) shall be included in all copies or substantial portions of the |
| 13 | * Software. |
| 14 | * |
| 15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR |
| 16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, |
| 17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL |
| 18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER |
| 19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING |
| 20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS |
| 21 | * IN THE SOFTWARE. |
| 22 | * |
| 23 | * Authors: |
| 24 | * Eric Anholt <eric@anholt.net> |
| 25 | * |
| 26 | */ |
| 27 | |
| 28 | #include "drmP.h" |
| 29 | #include "drm.h" |
| 30 | #include "i915_drm.h" |
| 31 | #include "i915_drv.h" |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 32 | #include "i915_trace.h" |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 33 | #include "intel_drv.h" |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 34 | #include <linux/swap.h> |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 35 | #include <linux/pci.h> |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 36 | |
Eric Anholt | 28dfe52 | 2008-11-13 15:00:55 -0800 | [diff] [blame] | 37 | #define I915_GEM_GPU_DOMAINS (~(I915_GEM_DOMAIN_CPU | I915_GEM_DOMAIN_GTT)) |
| 38 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 39 | static void i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj); |
| 40 | static void i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj); |
| 41 | static void i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 42 | static int i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, |
| 43 | int write); |
| 44 | static int i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 45 | uint64_t offset, |
| 46 | uint64_t size); |
| 47 | static void i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 48 | static int i915_gem_object_wait_rendering(struct drm_gem_object *obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 49 | static int i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, |
| 50 | unsigned alignment); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 51 | static void i915_gem_clear_fence_reg(struct drm_gem_object *obj); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 52 | static int i915_gem_evict_something(struct drm_device *dev, int min_size); |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 53 | static int i915_gem_evict_from_inactive_list(struct drm_device *dev); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 54 | static int i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 55 | struct drm_i915_gem_pwrite *args, |
| 56 | struct drm_file *file_priv); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 57 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 58 | static LIST_HEAD(shrink_list); |
| 59 | static DEFINE_SPINLOCK(shrink_list_lock); |
| 60 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 61 | int i915_gem_do_init(struct drm_device *dev, unsigned long start, |
| 62 | unsigned long end) |
| 63 | { |
| 64 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 65 | |
| 66 | if (start >= end || |
| 67 | (start & (PAGE_SIZE - 1)) != 0 || |
| 68 | (end & (PAGE_SIZE - 1)) != 0) { |
| 69 | return -EINVAL; |
| 70 | } |
| 71 | |
| 72 | drm_mm_init(&dev_priv->mm.gtt_space, start, |
| 73 | end - start); |
| 74 | |
| 75 | dev->gtt_total = (uint32_t) (end - start); |
| 76 | |
| 77 | return 0; |
| 78 | } |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 79 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 80 | int |
| 81 | i915_gem_init_ioctl(struct drm_device *dev, void *data, |
| 82 | struct drm_file *file_priv) |
| 83 | { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 84 | struct drm_i915_gem_init *args = data; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 85 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 86 | |
| 87 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 88 | ret = i915_gem_do_init(dev, args->gtt_start, args->gtt_end); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 89 | mutex_unlock(&dev->struct_mutex); |
| 90 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 91 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 92 | } |
| 93 | |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 94 | int |
| 95 | i915_gem_get_aperture_ioctl(struct drm_device *dev, void *data, |
| 96 | struct drm_file *file_priv) |
| 97 | { |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 98 | struct drm_i915_gem_get_aperture *args = data; |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 99 | |
| 100 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 101 | return -ENODEV; |
| 102 | |
| 103 | args->aper_size = dev->gtt_total; |
Keith Packard | 2678d9d | 2008-11-20 22:54:54 -0800 | [diff] [blame] | 104 | args->aper_available_size = (args->aper_size - |
| 105 | atomic_read(&dev->pin_memory)); |
Eric Anholt | 5a125c3 | 2008-10-22 21:40:13 -0700 | [diff] [blame] | 106 | |
| 107 | return 0; |
| 108 | } |
| 109 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 110 | |
| 111 | /** |
| 112 | * Creates a new mm object and returns a handle to it. |
| 113 | */ |
| 114 | int |
| 115 | i915_gem_create_ioctl(struct drm_device *dev, void *data, |
| 116 | struct drm_file *file_priv) |
| 117 | { |
| 118 | struct drm_i915_gem_create *args = data; |
| 119 | struct drm_gem_object *obj; |
Pekka Paalanen | a1a2d1d | 2009-08-23 12:40:55 +0300 | [diff] [blame] | 120 | int ret; |
| 121 | u32 handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 122 | |
| 123 | args->size = roundup(args->size, PAGE_SIZE); |
| 124 | |
| 125 | /* Allocate the new object */ |
| 126 | obj = drm_gem_object_alloc(dev, args->size); |
| 127 | if (obj == NULL) |
| 128 | return -ENOMEM; |
| 129 | |
| 130 | ret = drm_gem_handle_create(file_priv, obj, &handle); |
| 131 | mutex_lock(&dev->struct_mutex); |
| 132 | drm_gem_object_handle_unreference(obj); |
| 133 | mutex_unlock(&dev->struct_mutex); |
| 134 | |
| 135 | if (ret) |
| 136 | return ret; |
| 137 | |
| 138 | args->handle = handle; |
| 139 | |
| 140 | return 0; |
| 141 | } |
| 142 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 143 | static inline int |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 144 | fast_shmem_read(struct page **pages, |
| 145 | loff_t page_base, int page_offset, |
| 146 | char __user *data, |
| 147 | int length) |
| 148 | { |
| 149 | char __iomem *vaddr; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 150 | int unwritten; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 151 | |
| 152 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 153 | if (vaddr == NULL) |
| 154 | return -ENOMEM; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 155 | unwritten = __copy_to_user_inatomic(data, vaddr + page_offset, length); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 156 | kunmap_atomic(vaddr, KM_USER0); |
| 157 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 158 | if (unwritten) |
| 159 | return -EFAULT; |
| 160 | |
| 161 | return 0; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 162 | } |
| 163 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 164 | static int i915_gem_object_needs_bit17_swizzle(struct drm_gem_object *obj) |
| 165 | { |
| 166 | drm_i915_private_t *dev_priv = obj->dev->dev_private; |
| 167 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 168 | |
| 169 | return dev_priv->mm.bit_6_swizzle_x == I915_BIT_6_SWIZZLE_9_10_17 && |
| 170 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 171 | } |
| 172 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 173 | static inline int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 174 | slow_shmem_copy(struct page *dst_page, |
| 175 | int dst_offset, |
| 176 | struct page *src_page, |
| 177 | int src_offset, |
| 178 | int length) |
| 179 | { |
| 180 | char *dst_vaddr, *src_vaddr; |
| 181 | |
| 182 | dst_vaddr = kmap_atomic(dst_page, KM_USER0); |
| 183 | if (dst_vaddr == NULL) |
| 184 | return -ENOMEM; |
| 185 | |
| 186 | src_vaddr = kmap_atomic(src_page, KM_USER1); |
| 187 | if (src_vaddr == NULL) { |
| 188 | kunmap_atomic(dst_vaddr, KM_USER0); |
| 189 | return -ENOMEM; |
| 190 | } |
| 191 | |
| 192 | memcpy(dst_vaddr + dst_offset, src_vaddr + src_offset, length); |
| 193 | |
| 194 | kunmap_atomic(src_vaddr, KM_USER1); |
| 195 | kunmap_atomic(dst_vaddr, KM_USER0); |
| 196 | |
| 197 | return 0; |
| 198 | } |
| 199 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 200 | static inline int |
| 201 | slow_shmem_bit17_copy(struct page *gpu_page, |
| 202 | int gpu_offset, |
| 203 | struct page *cpu_page, |
| 204 | int cpu_offset, |
| 205 | int length, |
| 206 | int is_read) |
| 207 | { |
| 208 | char *gpu_vaddr, *cpu_vaddr; |
| 209 | |
| 210 | /* Use the unswizzled path if this page isn't affected. */ |
| 211 | if ((page_to_phys(gpu_page) & (1 << 17)) == 0) { |
| 212 | if (is_read) |
| 213 | return slow_shmem_copy(cpu_page, cpu_offset, |
| 214 | gpu_page, gpu_offset, length); |
| 215 | else |
| 216 | return slow_shmem_copy(gpu_page, gpu_offset, |
| 217 | cpu_page, cpu_offset, length); |
| 218 | } |
| 219 | |
| 220 | gpu_vaddr = kmap_atomic(gpu_page, KM_USER0); |
| 221 | if (gpu_vaddr == NULL) |
| 222 | return -ENOMEM; |
| 223 | |
| 224 | cpu_vaddr = kmap_atomic(cpu_page, KM_USER1); |
| 225 | if (cpu_vaddr == NULL) { |
| 226 | kunmap_atomic(gpu_vaddr, KM_USER0); |
| 227 | return -ENOMEM; |
| 228 | } |
| 229 | |
| 230 | /* Copy the data, XORing A6 with A17 (1). The user already knows he's |
| 231 | * XORing with the other bits (A9 for Y, A9 and A10 for X) |
| 232 | */ |
| 233 | while (length > 0) { |
| 234 | int cacheline_end = ALIGN(gpu_offset + 1, 64); |
| 235 | int this_length = min(cacheline_end - gpu_offset, length); |
| 236 | int swizzled_gpu_offset = gpu_offset ^ 64; |
| 237 | |
| 238 | if (is_read) { |
| 239 | memcpy(cpu_vaddr + cpu_offset, |
| 240 | gpu_vaddr + swizzled_gpu_offset, |
| 241 | this_length); |
| 242 | } else { |
| 243 | memcpy(gpu_vaddr + swizzled_gpu_offset, |
| 244 | cpu_vaddr + cpu_offset, |
| 245 | this_length); |
| 246 | } |
| 247 | cpu_offset += this_length; |
| 248 | gpu_offset += this_length; |
| 249 | length -= this_length; |
| 250 | } |
| 251 | |
| 252 | kunmap_atomic(cpu_vaddr, KM_USER1); |
| 253 | kunmap_atomic(gpu_vaddr, KM_USER0); |
| 254 | |
| 255 | return 0; |
| 256 | } |
| 257 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 258 | /** |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 259 | * This is the fast shmem pread path, which attempts to copy_from_user directly |
| 260 | * from the backing pages of the object to the user's address space. On a |
| 261 | * fault, it fails so we can fall back to i915_gem_shmem_pwrite_slow(). |
| 262 | */ |
| 263 | static int |
| 264 | i915_gem_shmem_pread_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 265 | struct drm_i915_gem_pread *args, |
| 266 | struct drm_file *file_priv) |
| 267 | { |
| 268 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 269 | ssize_t remain; |
| 270 | loff_t offset, page_base; |
| 271 | char __user *user_data; |
| 272 | int page_offset, page_length; |
| 273 | int ret; |
| 274 | |
| 275 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 276 | remain = args->size; |
| 277 | |
| 278 | mutex_lock(&dev->struct_mutex); |
| 279 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 280 | ret = i915_gem_object_get_pages(obj, 0); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 281 | if (ret != 0) |
| 282 | goto fail_unlock; |
| 283 | |
| 284 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 285 | args->size); |
| 286 | if (ret != 0) |
| 287 | goto fail_put_pages; |
| 288 | |
| 289 | obj_priv = obj->driver_private; |
| 290 | offset = args->offset; |
| 291 | |
| 292 | while (remain > 0) { |
| 293 | /* Operation in this page |
| 294 | * |
| 295 | * page_base = page offset within aperture |
| 296 | * page_offset = offset within page |
| 297 | * page_length = bytes to copy for this page |
| 298 | */ |
| 299 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 300 | page_offset = offset & (PAGE_SIZE-1); |
| 301 | page_length = remain; |
| 302 | if ((page_offset + remain) > PAGE_SIZE) |
| 303 | page_length = PAGE_SIZE - page_offset; |
| 304 | |
| 305 | ret = fast_shmem_read(obj_priv->pages, |
| 306 | page_base, page_offset, |
| 307 | user_data, page_length); |
| 308 | if (ret) |
| 309 | goto fail_put_pages; |
| 310 | |
| 311 | remain -= page_length; |
| 312 | user_data += page_length; |
| 313 | offset += page_length; |
| 314 | } |
| 315 | |
| 316 | fail_put_pages: |
| 317 | i915_gem_object_put_pages(obj); |
| 318 | fail_unlock: |
| 319 | mutex_unlock(&dev->struct_mutex); |
| 320 | |
| 321 | return ret; |
| 322 | } |
| 323 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 324 | static int |
| 325 | i915_gem_object_get_pages_or_evict(struct drm_gem_object *obj) |
| 326 | { |
| 327 | int ret; |
| 328 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 329 | ret = i915_gem_object_get_pages(obj, __GFP_NORETRY | __GFP_NOWARN); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 330 | |
| 331 | /* If we've insufficient memory to map in the pages, attempt |
| 332 | * to make some space by throwing out some old buffers. |
| 333 | */ |
| 334 | if (ret == -ENOMEM) { |
| 335 | struct drm_device *dev = obj->dev; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 336 | |
| 337 | ret = i915_gem_evict_something(dev, obj->size); |
| 338 | if (ret) |
| 339 | return ret; |
| 340 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 341 | ret = i915_gem_object_get_pages(obj, 0); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 342 | } |
| 343 | |
| 344 | return ret; |
| 345 | } |
| 346 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 347 | /** |
| 348 | * This is the fallback shmem pread path, which allocates temporary storage |
| 349 | * in kernel space to copy_to_user into outside of the struct_mutex, so we |
| 350 | * can copy out of the object's backing pages while holding the struct mutex |
| 351 | * and not take page faults. |
| 352 | */ |
| 353 | static int |
| 354 | i915_gem_shmem_pread_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 355 | struct drm_i915_gem_pread *args, |
| 356 | struct drm_file *file_priv) |
| 357 | { |
| 358 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 359 | struct mm_struct *mm = current->mm; |
| 360 | struct page **user_pages; |
| 361 | ssize_t remain; |
| 362 | loff_t offset, pinned_pages, i; |
| 363 | loff_t first_data_page, last_data_page, num_pages; |
| 364 | int shmem_page_index, shmem_page_offset; |
| 365 | int data_page_index, data_page_offset; |
| 366 | int page_length; |
| 367 | int ret; |
| 368 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 369 | int do_bit17_swizzling; |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 370 | |
| 371 | remain = args->size; |
| 372 | |
| 373 | /* Pin the user pages containing the data. We can't fault while |
| 374 | * holding the struct mutex, yet we want to hold it while |
| 375 | * dereferencing the user data. |
| 376 | */ |
| 377 | first_data_page = data_ptr / PAGE_SIZE; |
| 378 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 379 | num_pages = last_data_page - first_data_page + 1; |
| 380 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 381 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 382 | if (user_pages == NULL) |
| 383 | return -ENOMEM; |
| 384 | |
| 385 | down_read(&mm->mmap_sem); |
| 386 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
Eric Anholt | e5e9ecd | 2009-04-07 16:01:22 -0700 | [diff] [blame] | 387 | num_pages, 1, 0, user_pages, NULL); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 388 | up_read(&mm->mmap_sem); |
| 389 | if (pinned_pages < num_pages) { |
| 390 | ret = -EFAULT; |
| 391 | goto fail_put_user_pages; |
| 392 | } |
| 393 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 394 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 395 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 396 | mutex_lock(&dev->struct_mutex); |
| 397 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 398 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 399 | if (ret) |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 400 | goto fail_unlock; |
| 401 | |
| 402 | ret = i915_gem_object_set_cpu_read_domain_range(obj, args->offset, |
| 403 | args->size); |
| 404 | if (ret != 0) |
| 405 | goto fail_put_pages; |
| 406 | |
| 407 | obj_priv = obj->driver_private; |
| 408 | offset = args->offset; |
| 409 | |
| 410 | while (remain > 0) { |
| 411 | /* Operation in this page |
| 412 | * |
| 413 | * shmem_page_index = page number within shmem file |
| 414 | * shmem_page_offset = offset within page in shmem file |
| 415 | * data_page_index = page number in get_user_pages return |
| 416 | * data_page_offset = offset with data_page_index page. |
| 417 | * page_length = bytes to copy for this page |
| 418 | */ |
| 419 | shmem_page_index = offset / PAGE_SIZE; |
| 420 | shmem_page_offset = offset & ~PAGE_MASK; |
| 421 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 422 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 423 | |
| 424 | page_length = remain; |
| 425 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 426 | page_length = PAGE_SIZE - shmem_page_offset; |
| 427 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 428 | page_length = PAGE_SIZE - data_page_offset; |
| 429 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 430 | if (do_bit17_swizzling) { |
| 431 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
| 432 | shmem_page_offset, |
| 433 | user_pages[data_page_index], |
| 434 | data_page_offset, |
| 435 | page_length, |
| 436 | 1); |
| 437 | } else { |
| 438 | ret = slow_shmem_copy(user_pages[data_page_index], |
| 439 | data_page_offset, |
| 440 | obj_priv->pages[shmem_page_index], |
| 441 | shmem_page_offset, |
| 442 | page_length); |
| 443 | } |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 444 | if (ret) |
| 445 | goto fail_put_pages; |
| 446 | |
| 447 | remain -= page_length; |
| 448 | data_ptr += page_length; |
| 449 | offset += page_length; |
| 450 | } |
| 451 | |
| 452 | fail_put_pages: |
| 453 | i915_gem_object_put_pages(obj); |
| 454 | fail_unlock: |
| 455 | mutex_unlock(&dev->struct_mutex); |
| 456 | fail_put_user_pages: |
| 457 | for (i = 0; i < pinned_pages; i++) { |
| 458 | SetPageDirty(user_pages[i]); |
| 459 | page_cache_release(user_pages[i]); |
| 460 | } |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 461 | drm_free_large(user_pages); |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 462 | |
| 463 | return ret; |
| 464 | } |
| 465 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 466 | /** |
| 467 | * Reads data from the object referenced by handle. |
| 468 | * |
| 469 | * On error, the contents of *data are undefined. |
| 470 | */ |
| 471 | int |
| 472 | i915_gem_pread_ioctl(struct drm_device *dev, void *data, |
| 473 | struct drm_file *file_priv) |
| 474 | { |
| 475 | struct drm_i915_gem_pread *args = data; |
| 476 | struct drm_gem_object *obj; |
| 477 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 478 | int ret; |
| 479 | |
| 480 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 481 | if (obj == NULL) |
| 482 | return -EBADF; |
| 483 | obj_priv = obj->driver_private; |
| 484 | |
| 485 | /* Bounds check source. |
| 486 | * |
| 487 | * XXX: This could use review for overflow issues... |
| 488 | */ |
| 489 | if (args->offset > obj->size || args->size > obj->size || |
| 490 | args->offset + args->size > obj->size) { |
| 491 | drm_gem_object_unreference(obj); |
| 492 | return -EINVAL; |
| 493 | } |
| 494 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 495 | if (i915_gem_object_needs_bit17_swizzle(obj)) { |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 496 | ret = i915_gem_shmem_pread_slow(dev, obj, args, file_priv); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 497 | } else { |
| 498 | ret = i915_gem_shmem_pread_fast(dev, obj, args, file_priv); |
| 499 | if (ret != 0) |
| 500 | ret = i915_gem_shmem_pread_slow(dev, obj, args, |
| 501 | file_priv); |
| 502 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 503 | |
| 504 | drm_gem_object_unreference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 505 | |
Eric Anholt | eb01459 | 2009-03-10 11:44:52 -0700 | [diff] [blame] | 506 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 507 | } |
| 508 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 509 | /* This is the fast write path which cannot handle |
| 510 | * page faults in the source data |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 511 | */ |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 512 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 513 | static inline int |
| 514 | fast_user_write(struct io_mapping *mapping, |
| 515 | loff_t page_base, int page_offset, |
| 516 | char __user *user_data, |
| 517 | int length) |
| 518 | { |
| 519 | char *vaddr_atomic; |
| 520 | unsigned long unwritten; |
| 521 | |
| 522 | vaddr_atomic = io_mapping_map_atomic_wc(mapping, page_base); |
| 523 | unwritten = __copy_from_user_inatomic_nocache(vaddr_atomic + page_offset, |
| 524 | user_data, length); |
| 525 | io_mapping_unmap_atomic(vaddr_atomic); |
| 526 | if (unwritten) |
| 527 | return -EFAULT; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 528 | return 0; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 529 | } |
| 530 | |
| 531 | /* Here's the write path which can sleep for |
| 532 | * page faults |
| 533 | */ |
| 534 | |
| 535 | static inline int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 536 | slow_kernel_write(struct io_mapping *mapping, |
| 537 | loff_t gtt_base, int gtt_offset, |
| 538 | struct page *user_page, int user_offset, |
| 539 | int length) |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 540 | { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 541 | char *src_vaddr, *dst_vaddr; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 542 | unsigned long unwritten; |
| 543 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 544 | dst_vaddr = io_mapping_map_atomic_wc(mapping, gtt_base); |
| 545 | src_vaddr = kmap_atomic(user_page, KM_USER1); |
| 546 | unwritten = __copy_from_user_inatomic_nocache(dst_vaddr + gtt_offset, |
| 547 | src_vaddr + user_offset, |
| 548 | length); |
| 549 | kunmap_atomic(src_vaddr, KM_USER1); |
| 550 | io_mapping_unmap_atomic(dst_vaddr); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 551 | if (unwritten) |
| 552 | return -EFAULT; |
| 553 | return 0; |
Linus Torvalds | 9b7530cc | 2008-10-20 14:16:43 -0700 | [diff] [blame] | 554 | } |
| 555 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 556 | static inline int |
| 557 | fast_shmem_write(struct page **pages, |
| 558 | loff_t page_base, int page_offset, |
| 559 | char __user *data, |
| 560 | int length) |
| 561 | { |
| 562 | char __iomem *vaddr; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 563 | unsigned long unwritten; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 564 | |
| 565 | vaddr = kmap_atomic(pages[page_base >> PAGE_SHIFT], KM_USER0); |
| 566 | if (vaddr == NULL) |
| 567 | return -ENOMEM; |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 568 | unwritten = __copy_from_user_inatomic(vaddr + page_offset, data, length); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 569 | kunmap_atomic(vaddr, KM_USER0); |
| 570 | |
Dave Airlie | d008877 | 2009-03-28 20:29:48 -0400 | [diff] [blame] | 571 | if (unwritten) |
| 572 | return -EFAULT; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 573 | return 0; |
| 574 | } |
| 575 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 576 | /** |
| 577 | * This is the fast pwrite path, where we copy the data directly from the |
| 578 | * user into the GTT, uncached. |
| 579 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 580 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 581 | i915_gem_gtt_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 582 | struct drm_i915_gem_pwrite *args, |
| 583 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 584 | { |
| 585 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 586 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 587 | ssize_t remain; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 588 | loff_t offset, page_base; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 589 | char __user *user_data; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 590 | int page_offset, page_length; |
| 591 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 592 | |
| 593 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 594 | remain = args->size; |
| 595 | if (!access_ok(VERIFY_READ, user_data, remain)) |
| 596 | return -EFAULT; |
| 597 | |
| 598 | |
| 599 | mutex_lock(&dev->struct_mutex); |
| 600 | ret = i915_gem_object_pin(obj, 0); |
| 601 | if (ret) { |
| 602 | mutex_unlock(&dev->struct_mutex); |
| 603 | return ret; |
| 604 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 605 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 606 | if (ret) |
| 607 | goto fail; |
| 608 | |
| 609 | obj_priv = obj->driver_private; |
| 610 | offset = obj_priv->gtt_offset + args->offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 611 | |
| 612 | while (remain > 0) { |
| 613 | /* Operation in this page |
| 614 | * |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 615 | * page_base = page offset within aperture |
| 616 | * page_offset = offset within page |
| 617 | * page_length = bytes to copy for this page |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 618 | */ |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 619 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 620 | page_offset = offset & (PAGE_SIZE-1); |
| 621 | page_length = remain; |
| 622 | if ((page_offset + remain) > PAGE_SIZE) |
| 623 | page_length = PAGE_SIZE - page_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 624 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 625 | ret = fast_user_write (dev_priv->mm.gtt_mapping, page_base, |
| 626 | page_offset, user_data, page_length); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 627 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 628 | /* If we get a fault while copying data, then (presumably) our |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 629 | * source page isn't available. Return the error and we'll |
| 630 | * retry in the slow path. |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 631 | */ |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 632 | if (ret) |
| 633 | goto fail; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 634 | |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 635 | remain -= page_length; |
| 636 | user_data += page_length; |
| 637 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 638 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 639 | |
| 640 | fail: |
| 641 | i915_gem_object_unpin(obj); |
| 642 | mutex_unlock(&dev->struct_mutex); |
| 643 | |
| 644 | return ret; |
| 645 | } |
| 646 | |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 647 | /** |
| 648 | * This is the fallback GTT pwrite path, which uses get_user_pages to pin |
| 649 | * the memory and maps it using kmap_atomic for copying. |
| 650 | * |
| 651 | * This code resulted in x11perf -rgb10text consuming about 10% more CPU |
| 652 | * than using i915_gem_gtt_pwrite_fast on a G45 (32-bit). |
| 653 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 654 | static int |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 655 | i915_gem_gtt_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 656 | struct drm_i915_gem_pwrite *args, |
| 657 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 658 | { |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 659 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 660 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 661 | ssize_t remain; |
| 662 | loff_t gtt_page_base, offset; |
| 663 | loff_t first_data_page, last_data_page, num_pages; |
| 664 | loff_t pinned_pages, i; |
| 665 | struct page **user_pages; |
| 666 | struct mm_struct *mm = current->mm; |
| 667 | int gtt_page_offset, data_page_offset, data_page_index, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 668 | int ret; |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 669 | uint64_t data_ptr = args->data_ptr; |
| 670 | |
| 671 | remain = args->size; |
| 672 | |
| 673 | /* Pin the user pages containing the data. We can't fault while |
| 674 | * holding the struct mutex, and all of the pwrite implementations |
| 675 | * want to hold it while dereferencing the user data. |
| 676 | */ |
| 677 | first_data_page = data_ptr / PAGE_SIZE; |
| 678 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 679 | num_pages = last_data_page - first_data_page + 1; |
| 680 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 681 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 682 | if (user_pages == NULL) |
| 683 | return -ENOMEM; |
| 684 | |
| 685 | down_read(&mm->mmap_sem); |
| 686 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 687 | num_pages, 0, 0, user_pages, NULL); |
| 688 | up_read(&mm->mmap_sem); |
| 689 | if (pinned_pages < num_pages) { |
| 690 | ret = -EFAULT; |
| 691 | goto out_unpin_pages; |
| 692 | } |
| 693 | |
| 694 | mutex_lock(&dev->struct_mutex); |
| 695 | ret = i915_gem_object_pin(obj, 0); |
| 696 | if (ret) |
| 697 | goto out_unlock; |
| 698 | |
| 699 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 700 | if (ret) |
| 701 | goto out_unpin_object; |
| 702 | |
| 703 | obj_priv = obj->driver_private; |
| 704 | offset = obj_priv->gtt_offset + args->offset; |
| 705 | |
| 706 | while (remain > 0) { |
| 707 | /* Operation in this page |
| 708 | * |
| 709 | * gtt_page_base = page offset within aperture |
| 710 | * gtt_page_offset = offset within page in aperture |
| 711 | * data_page_index = page number in get_user_pages return |
| 712 | * data_page_offset = offset with data_page_index page. |
| 713 | * page_length = bytes to copy for this page |
| 714 | */ |
| 715 | gtt_page_base = offset & PAGE_MASK; |
| 716 | gtt_page_offset = offset & ~PAGE_MASK; |
| 717 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 718 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 719 | |
| 720 | page_length = remain; |
| 721 | if ((gtt_page_offset + page_length) > PAGE_SIZE) |
| 722 | page_length = PAGE_SIZE - gtt_page_offset; |
| 723 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 724 | page_length = PAGE_SIZE - data_page_offset; |
| 725 | |
| 726 | ret = slow_kernel_write(dev_priv->mm.gtt_mapping, |
| 727 | gtt_page_base, gtt_page_offset, |
| 728 | user_pages[data_page_index], |
| 729 | data_page_offset, |
| 730 | page_length); |
| 731 | |
| 732 | /* If we get a fault while copying data, then (presumably) our |
| 733 | * source page isn't available. Return the error and we'll |
| 734 | * retry in the slow path. |
| 735 | */ |
| 736 | if (ret) |
| 737 | goto out_unpin_object; |
| 738 | |
| 739 | remain -= page_length; |
| 740 | offset += page_length; |
| 741 | data_ptr += page_length; |
| 742 | } |
| 743 | |
| 744 | out_unpin_object: |
| 745 | i915_gem_object_unpin(obj); |
| 746 | out_unlock: |
| 747 | mutex_unlock(&dev->struct_mutex); |
| 748 | out_unpin_pages: |
| 749 | for (i = 0; i < pinned_pages; i++) |
| 750 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 751 | drm_free_large(user_pages); |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 752 | |
| 753 | return ret; |
| 754 | } |
| 755 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 756 | /** |
| 757 | * This is the fast shmem pwrite path, which attempts to directly |
| 758 | * copy_from_user into the kmapped pages backing the object. |
| 759 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 760 | static int |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 761 | i915_gem_shmem_pwrite_fast(struct drm_device *dev, struct drm_gem_object *obj, |
| 762 | struct drm_i915_gem_pwrite *args, |
| 763 | struct drm_file *file_priv) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 764 | { |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 765 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 766 | ssize_t remain; |
| 767 | loff_t offset, page_base; |
| 768 | char __user *user_data; |
| 769 | int page_offset, page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 770 | int ret; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 771 | |
| 772 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 773 | remain = args->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 774 | |
| 775 | mutex_lock(&dev->struct_mutex); |
| 776 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 777 | ret = i915_gem_object_get_pages(obj, 0); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 778 | if (ret != 0) |
| 779 | goto fail_unlock; |
| 780 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 781 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 782 | if (ret != 0) |
| 783 | goto fail_put_pages; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 784 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 785 | obj_priv = obj->driver_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 786 | offset = args->offset; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 787 | obj_priv->dirty = 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 788 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 789 | while (remain > 0) { |
| 790 | /* Operation in this page |
| 791 | * |
| 792 | * page_base = page offset within aperture |
| 793 | * page_offset = offset within page |
| 794 | * page_length = bytes to copy for this page |
| 795 | */ |
| 796 | page_base = (offset & ~(PAGE_SIZE-1)); |
| 797 | page_offset = offset & (PAGE_SIZE-1); |
| 798 | page_length = remain; |
| 799 | if ((page_offset + remain) > PAGE_SIZE) |
| 800 | page_length = PAGE_SIZE - page_offset; |
| 801 | |
| 802 | ret = fast_shmem_write(obj_priv->pages, |
| 803 | page_base, page_offset, |
| 804 | user_data, page_length); |
| 805 | if (ret) |
| 806 | goto fail_put_pages; |
| 807 | |
| 808 | remain -= page_length; |
| 809 | user_data += page_length; |
| 810 | offset += page_length; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 811 | } |
| 812 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 813 | fail_put_pages: |
| 814 | i915_gem_object_put_pages(obj); |
| 815 | fail_unlock: |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 816 | mutex_unlock(&dev->struct_mutex); |
| 817 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 818 | return ret; |
| 819 | } |
| 820 | |
| 821 | /** |
| 822 | * This is the fallback shmem pwrite path, which uses get_user_pages to pin |
| 823 | * the memory and maps it using kmap_atomic for copying. |
| 824 | * |
| 825 | * This avoids taking mmap_sem for faulting on the user's address while the |
| 826 | * struct_mutex is held. |
| 827 | */ |
| 828 | static int |
| 829 | i915_gem_shmem_pwrite_slow(struct drm_device *dev, struct drm_gem_object *obj, |
| 830 | struct drm_i915_gem_pwrite *args, |
| 831 | struct drm_file *file_priv) |
| 832 | { |
| 833 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 834 | struct mm_struct *mm = current->mm; |
| 835 | struct page **user_pages; |
| 836 | ssize_t remain; |
| 837 | loff_t offset, pinned_pages, i; |
| 838 | loff_t first_data_page, last_data_page, num_pages; |
| 839 | int shmem_page_index, shmem_page_offset; |
| 840 | int data_page_index, data_page_offset; |
| 841 | int page_length; |
| 842 | int ret; |
| 843 | uint64_t data_ptr = args->data_ptr; |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 844 | int do_bit17_swizzling; |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 845 | |
| 846 | remain = args->size; |
| 847 | |
| 848 | /* Pin the user pages containing the data. We can't fault while |
| 849 | * holding the struct mutex, and all of the pwrite implementations |
| 850 | * want to hold it while dereferencing the user data. |
| 851 | */ |
| 852 | first_data_page = data_ptr / PAGE_SIZE; |
| 853 | last_data_page = (data_ptr + args->size - 1) / PAGE_SIZE; |
| 854 | num_pages = last_data_page - first_data_page + 1; |
| 855 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 856 | user_pages = drm_calloc_large(num_pages, sizeof(struct page *)); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 857 | if (user_pages == NULL) |
| 858 | return -ENOMEM; |
| 859 | |
| 860 | down_read(&mm->mmap_sem); |
| 861 | pinned_pages = get_user_pages(current, mm, (uintptr_t)args->data_ptr, |
| 862 | num_pages, 0, 0, user_pages, NULL); |
| 863 | up_read(&mm->mmap_sem); |
| 864 | if (pinned_pages < num_pages) { |
| 865 | ret = -EFAULT; |
| 866 | goto fail_put_user_pages; |
| 867 | } |
| 868 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 869 | do_bit17_swizzling = i915_gem_object_needs_bit17_swizzle(obj); |
| 870 | |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 871 | mutex_lock(&dev->struct_mutex); |
| 872 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 873 | ret = i915_gem_object_get_pages_or_evict(obj); |
| 874 | if (ret) |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 875 | goto fail_unlock; |
| 876 | |
| 877 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
| 878 | if (ret != 0) |
| 879 | goto fail_put_pages; |
| 880 | |
| 881 | obj_priv = obj->driver_private; |
| 882 | offset = args->offset; |
| 883 | obj_priv->dirty = 1; |
| 884 | |
| 885 | while (remain > 0) { |
| 886 | /* Operation in this page |
| 887 | * |
| 888 | * shmem_page_index = page number within shmem file |
| 889 | * shmem_page_offset = offset within page in shmem file |
| 890 | * data_page_index = page number in get_user_pages return |
| 891 | * data_page_offset = offset with data_page_index page. |
| 892 | * page_length = bytes to copy for this page |
| 893 | */ |
| 894 | shmem_page_index = offset / PAGE_SIZE; |
| 895 | shmem_page_offset = offset & ~PAGE_MASK; |
| 896 | data_page_index = data_ptr / PAGE_SIZE - first_data_page; |
| 897 | data_page_offset = data_ptr & ~PAGE_MASK; |
| 898 | |
| 899 | page_length = remain; |
| 900 | if ((shmem_page_offset + page_length) > PAGE_SIZE) |
| 901 | page_length = PAGE_SIZE - shmem_page_offset; |
| 902 | if ((data_page_offset + page_length) > PAGE_SIZE) |
| 903 | page_length = PAGE_SIZE - data_page_offset; |
| 904 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 905 | if (do_bit17_swizzling) { |
| 906 | ret = slow_shmem_bit17_copy(obj_priv->pages[shmem_page_index], |
| 907 | shmem_page_offset, |
| 908 | user_pages[data_page_index], |
| 909 | data_page_offset, |
| 910 | page_length, |
| 911 | 0); |
| 912 | } else { |
| 913 | ret = slow_shmem_copy(obj_priv->pages[shmem_page_index], |
| 914 | shmem_page_offset, |
| 915 | user_pages[data_page_index], |
| 916 | data_page_offset, |
| 917 | page_length); |
| 918 | } |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 919 | if (ret) |
| 920 | goto fail_put_pages; |
| 921 | |
| 922 | remain -= page_length; |
| 923 | data_ptr += page_length; |
| 924 | offset += page_length; |
| 925 | } |
| 926 | |
| 927 | fail_put_pages: |
| 928 | i915_gem_object_put_pages(obj); |
| 929 | fail_unlock: |
| 930 | mutex_unlock(&dev->struct_mutex); |
| 931 | fail_put_user_pages: |
| 932 | for (i = 0; i < pinned_pages; i++) |
| 933 | page_cache_release(user_pages[i]); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 934 | drm_free_large(user_pages); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 935 | |
| 936 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 937 | } |
| 938 | |
| 939 | /** |
| 940 | * Writes data to the object referenced by handle. |
| 941 | * |
| 942 | * On error, the contents of the buffer that were to be modified are undefined. |
| 943 | */ |
| 944 | int |
| 945 | i915_gem_pwrite_ioctl(struct drm_device *dev, void *data, |
| 946 | struct drm_file *file_priv) |
| 947 | { |
| 948 | struct drm_i915_gem_pwrite *args = data; |
| 949 | struct drm_gem_object *obj; |
| 950 | struct drm_i915_gem_object *obj_priv; |
| 951 | int ret = 0; |
| 952 | |
| 953 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 954 | if (obj == NULL) |
| 955 | return -EBADF; |
| 956 | obj_priv = obj->driver_private; |
| 957 | |
| 958 | /* Bounds check destination. |
| 959 | * |
| 960 | * XXX: This could use review for overflow issues... |
| 961 | */ |
| 962 | if (args->offset > obj->size || args->size > obj->size || |
| 963 | args->offset + args->size > obj->size) { |
| 964 | drm_gem_object_unreference(obj); |
| 965 | return -EINVAL; |
| 966 | } |
| 967 | |
| 968 | /* We can only do the GTT pwrite on untiled buffers, as otherwise |
| 969 | * it would end up going through the fenced access, and we'll get |
| 970 | * different detiling behavior between reading and writing. |
| 971 | * pread/pwrite currently are reading and writing from the CPU |
| 972 | * perspective, requiring manual detiling by the client. |
| 973 | */ |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 974 | if (obj_priv->phys_obj) |
| 975 | ret = i915_gem_phys_pwrite(dev, obj, args, file_priv); |
| 976 | else if (obj_priv->tiling_mode == I915_TILING_NONE && |
Eric Anholt | 3de09aa | 2009-03-09 09:42:23 -0700 | [diff] [blame] | 977 | dev->gtt_total != 0) { |
| 978 | ret = i915_gem_gtt_pwrite_fast(dev, obj, args, file_priv); |
| 979 | if (ret == -EFAULT) { |
| 980 | ret = i915_gem_gtt_pwrite_slow(dev, obj, args, |
| 981 | file_priv); |
| 982 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 983 | } else if (i915_gem_object_needs_bit17_swizzle(obj)) { |
| 984 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, file_priv); |
Eric Anholt | 40123c1 | 2009-03-09 13:42:30 -0700 | [diff] [blame] | 985 | } else { |
| 986 | ret = i915_gem_shmem_pwrite_fast(dev, obj, args, file_priv); |
| 987 | if (ret == -EFAULT) { |
| 988 | ret = i915_gem_shmem_pwrite_slow(dev, obj, args, |
| 989 | file_priv); |
| 990 | } |
| 991 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 992 | |
| 993 | #if WATCH_PWRITE |
| 994 | if (ret) |
| 995 | DRM_INFO("pwrite failed %d\n", ret); |
| 996 | #endif |
| 997 | |
| 998 | drm_gem_object_unreference(obj); |
| 999 | |
| 1000 | return ret; |
| 1001 | } |
| 1002 | |
| 1003 | /** |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1004 | * Called when user space prepares to use an object with the CPU, either |
| 1005 | * through the mmap ioctl's mapping or a GTT mapping. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1006 | */ |
| 1007 | int |
| 1008 | i915_gem_set_domain_ioctl(struct drm_device *dev, void *data, |
| 1009 | struct drm_file *file_priv) |
| 1010 | { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1011 | struct drm_i915_private *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1012 | struct drm_i915_gem_set_domain *args = data; |
| 1013 | struct drm_gem_object *obj; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1014 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1015 | uint32_t read_domains = args->read_domains; |
| 1016 | uint32_t write_domain = args->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1017 | int ret; |
| 1018 | |
| 1019 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1020 | return -ENODEV; |
| 1021 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1022 | /* Only handle setting domains to types used by the CPU. */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1023 | if (write_domain & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1024 | return -EINVAL; |
| 1025 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1026 | if (read_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1027 | return -EINVAL; |
| 1028 | |
| 1029 | /* Having something in the write domain implies it's in the read |
| 1030 | * domain, and only that read domain. Enforce that in the request. |
| 1031 | */ |
| 1032 | if (write_domain != 0 && read_domains != write_domain) |
| 1033 | return -EINVAL; |
| 1034 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1035 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1036 | if (obj == NULL) |
| 1037 | return -EBADF; |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1038 | obj_priv = obj->driver_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1039 | |
| 1040 | mutex_lock(&dev->struct_mutex); |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 1041 | |
| 1042 | intel_mark_busy(dev, obj); |
| 1043 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1044 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 1045 | DRM_INFO("set_domain_ioctl %p(%zd), %08x %08x\n", |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1046 | obj, obj->size, read_domains, write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1047 | #endif |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1048 | if (read_domains & I915_GEM_DOMAIN_GTT) { |
| 1049 | ret = i915_gem_object_set_to_gtt_domain(obj, write_domain != 0); |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1050 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1051 | /* Update the LRU on the fence for the CPU access that's |
| 1052 | * about to occur. |
| 1053 | */ |
| 1054 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 1055 | list_move_tail(&obj_priv->fence_list, |
| 1056 | &dev_priv->mm.fence_list); |
| 1057 | } |
| 1058 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 1059 | /* Silently promote "you're not bound, there was nothing to do" |
| 1060 | * to success, since the client was just asking us to |
| 1061 | * make sure everything was done. |
| 1062 | */ |
| 1063 | if (ret == -EINVAL) |
| 1064 | ret = 0; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1065 | } else { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1066 | ret = i915_gem_object_set_to_cpu_domain(obj, write_domain != 0); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 1067 | } |
| 1068 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1069 | drm_gem_object_unreference(obj); |
| 1070 | mutex_unlock(&dev->struct_mutex); |
| 1071 | return ret; |
| 1072 | } |
| 1073 | |
| 1074 | /** |
| 1075 | * Called when user space has done writes to this buffer |
| 1076 | */ |
| 1077 | int |
| 1078 | i915_gem_sw_finish_ioctl(struct drm_device *dev, void *data, |
| 1079 | struct drm_file *file_priv) |
| 1080 | { |
| 1081 | struct drm_i915_gem_sw_finish *args = data; |
| 1082 | struct drm_gem_object *obj; |
| 1083 | struct drm_i915_gem_object *obj_priv; |
| 1084 | int ret = 0; |
| 1085 | |
| 1086 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1087 | return -ENODEV; |
| 1088 | |
| 1089 | mutex_lock(&dev->struct_mutex); |
| 1090 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1091 | if (obj == NULL) { |
| 1092 | mutex_unlock(&dev->struct_mutex); |
| 1093 | return -EBADF; |
| 1094 | } |
| 1095 | |
| 1096 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 1097 | DRM_INFO("%s: sw_finish %d (%p %zd)\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1098 | __func__, args->handle, obj, obj->size); |
| 1099 | #endif |
| 1100 | obj_priv = obj->driver_private; |
| 1101 | |
| 1102 | /* Pinned buffers may be scanout, so flush the cache */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1103 | if (obj_priv->pin_count) |
| 1104 | i915_gem_object_flush_cpu_write_domain(obj); |
| 1105 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1106 | drm_gem_object_unreference(obj); |
| 1107 | mutex_unlock(&dev->struct_mutex); |
| 1108 | return ret; |
| 1109 | } |
| 1110 | |
| 1111 | /** |
| 1112 | * Maps the contents of an object, returning the address it is mapped |
| 1113 | * into. |
| 1114 | * |
| 1115 | * While the mapping holds a reference on the contents of the object, it doesn't |
| 1116 | * imply a ref on the object itself. |
| 1117 | */ |
| 1118 | int |
| 1119 | i915_gem_mmap_ioctl(struct drm_device *dev, void *data, |
| 1120 | struct drm_file *file_priv) |
| 1121 | { |
| 1122 | struct drm_i915_gem_mmap *args = data; |
| 1123 | struct drm_gem_object *obj; |
| 1124 | loff_t offset; |
| 1125 | unsigned long addr; |
| 1126 | |
| 1127 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1128 | return -ENODEV; |
| 1129 | |
| 1130 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1131 | if (obj == NULL) |
| 1132 | return -EBADF; |
| 1133 | |
| 1134 | offset = args->offset; |
| 1135 | |
| 1136 | down_write(¤t->mm->mmap_sem); |
| 1137 | addr = do_mmap(obj->filp, 0, args->size, |
| 1138 | PROT_READ | PROT_WRITE, MAP_SHARED, |
| 1139 | args->offset); |
| 1140 | up_write(¤t->mm->mmap_sem); |
| 1141 | mutex_lock(&dev->struct_mutex); |
| 1142 | drm_gem_object_unreference(obj); |
| 1143 | mutex_unlock(&dev->struct_mutex); |
| 1144 | if (IS_ERR((void *)addr)) |
| 1145 | return addr; |
| 1146 | |
| 1147 | args->addr_ptr = (uint64_t) addr; |
| 1148 | |
| 1149 | return 0; |
| 1150 | } |
| 1151 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1152 | /** |
| 1153 | * i915_gem_fault - fault a page into the GTT |
| 1154 | * vma: VMA in question |
| 1155 | * vmf: fault info |
| 1156 | * |
| 1157 | * The fault handler is set up by drm_gem_mmap() when a object is GTT mapped |
| 1158 | * from userspace. The fault handler takes care of binding the object to |
| 1159 | * the GTT (if needed), allocating and programming a fence register (again, |
| 1160 | * only if needed based on whether the old reg is still valid or the object |
| 1161 | * is tiled) and inserting a new PTE into the faulting process. |
| 1162 | * |
| 1163 | * Note that the faulting process may involve evicting existing objects |
| 1164 | * from the GTT and/or fence registers to make room. So performance may |
| 1165 | * suffer if the GTT working set is large or there are few fence registers |
| 1166 | * left. |
| 1167 | */ |
| 1168 | int i915_gem_fault(struct vm_area_struct *vma, struct vm_fault *vmf) |
| 1169 | { |
| 1170 | struct drm_gem_object *obj = vma->vm_private_data; |
| 1171 | struct drm_device *dev = obj->dev; |
| 1172 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1173 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1174 | pgoff_t page_offset; |
| 1175 | unsigned long pfn; |
| 1176 | int ret = 0; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1177 | bool write = !!(vmf->flags & FAULT_FLAG_WRITE); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1178 | |
| 1179 | /* We don't use vmf->pgoff since that has the fake offset */ |
| 1180 | page_offset = ((unsigned long)vmf->virtual_address - vma->vm_start) >> |
| 1181 | PAGE_SHIFT; |
| 1182 | |
| 1183 | /* Now bind it into the GTT if needed */ |
| 1184 | mutex_lock(&dev->struct_mutex); |
| 1185 | if (!obj_priv->gtt_space) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1186 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1187 | if (ret) |
| 1188 | goto unlock; |
Kristian Høgsberg | 07f4f3e | 2009-05-27 14:37:28 -0400 | [diff] [blame] | 1189 | |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 1190 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1191 | |
| 1192 | ret = i915_gem_object_set_to_gtt_domain(obj, write); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1193 | if (ret) |
| 1194 | goto unlock; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1195 | } |
| 1196 | |
| 1197 | /* Need a new fence register? */ |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 1198 | if (obj_priv->tiling_mode != I915_TILING_NONE) { |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 1199 | ret = i915_gem_object_get_fence_reg(obj); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1200 | if (ret) |
| 1201 | goto unlock; |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 1202 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1203 | |
| 1204 | pfn = ((dev->agp->base + obj_priv->gtt_offset) >> PAGE_SHIFT) + |
| 1205 | page_offset; |
| 1206 | |
| 1207 | /* Finally, remap it using the new GTT offset */ |
| 1208 | ret = vm_insert_pfn(vma, (unsigned long)vmf->virtual_address, pfn); |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1209 | unlock: |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1210 | mutex_unlock(&dev->struct_mutex); |
| 1211 | |
| 1212 | switch (ret) { |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1213 | case 0: |
| 1214 | case -ERESTARTSYS: |
| 1215 | return VM_FAULT_NOPAGE; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1216 | case -ENOMEM: |
| 1217 | case -EAGAIN: |
| 1218 | return VM_FAULT_OOM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1219 | default: |
Chris Wilson | c715089 | 2009-09-23 00:43:56 +0100 | [diff] [blame] | 1220 | return VM_FAULT_SIGBUS; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1221 | } |
| 1222 | } |
| 1223 | |
| 1224 | /** |
| 1225 | * i915_gem_create_mmap_offset - create a fake mmap offset for an object |
| 1226 | * @obj: obj in question |
| 1227 | * |
| 1228 | * GEM memory mapping works by handing back to userspace a fake mmap offset |
| 1229 | * it can use in a subsequent mmap(2) call. The DRM core code then looks |
| 1230 | * up the object based on the offset and sets up the various memory mapping |
| 1231 | * structures. |
| 1232 | * |
| 1233 | * This routine allocates and attaches a fake offset for @obj. |
| 1234 | */ |
| 1235 | static int |
| 1236 | i915_gem_create_mmap_offset(struct drm_gem_object *obj) |
| 1237 | { |
| 1238 | struct drm_device *dev = obj->dev; |
| 1239 | struct drm_gem_mm *mm = dev->mm_private; |
| 1240 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1241 | struct drm_map_list *list; |
Benjamin Herrenschmidt | f77d390 | 2009-02-02 16:55:46 +1100 | [diff] [blame] | 1242 | struct drm_local_map *map; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1243 | int ret = 0; |
| 1244 | |
| 1245 | /* Set the object up for mmap'ing */ |
| 1246 | list = &obj->map_list; |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1247 | list->map = kzalloc(sizeof(struct drm_map_list), GFP_KERNEL); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1248 | if (!list->map) |
| 1249 | return -ENOMEM; |
| 1250 | |
| 1251 | map = list->map; |
| 1252 | map->type = _DRM_GEM; |
| 1253 | map->size = obj->size; |
| 1254 | map->handle = obj; |
| 1255 | |
| 1256 | /* Get a DRM GEM mmap offset allocated... */ |
| 1257 | list->file_offset_node = drm_mm_search_free(&mm->offset_manager, |
| 1258 | obj->size / PAGE_SIZE, 0, 0); |
| 1259 | if (!list->file_offset_node) { |
| 1260 | DRM_ERROR("failed to allocate offset for bo %d\n", obj->name); |
| 1261 | ret = -ENOMEM; |
| 1262 | goto out_free_list; |
| 1263 | } |
| 1264 | |
| 1265 | list->file_offset_node = drm_mm_get_block(list->file_offset_node, |
| 1266 | obj->size / PAGE_SIZE, 0); |
| 1267 | if (!list->file_offset_node) { |
| 1268 | ret = -ENOMEM; |
| 1269 | goto out_free_list; |
| 1270 | } |
| 1271 | |
| 1272 | list->hash.key = list->file_offset_node->start; |
| 1273 | if (drm_ht_insert_item(&mm->offset_hash, &list->hash)) { |
| 1274 | DRM_ERROR("failed to add to map hash\n"); |
Chris Wilson | 5618ca6 | 2009-12-02 15:15:30 +0000 | [diff] [blame] | 1275 | ret = -ENOMEM; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1276 | goto out_free_mm; |
| 1277 | } |
| 1278 | |
| 1279 | /* By now we should be all set, any drm_mmap request on the offset |
| 1280 | * below will get to our mmap & fault handler */ |
| 1281 | obj_priv->mmap_offset = ((uint64_t) list->hash.key) << PAGE_SHIFT; |
| 1282 | |
| 1283 | return 0; |
| 1284 | |
| 1285 | out_free_mm: |
| 1286 | drm_mm_put_block(list->file_offset_node); |
| 1287 | out_free_list: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1288 | kfree(list->map); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1289 | |
| 1290 | return ret; |
| 1291 | } |
| 1292 | |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1293 | /** |
| 1294 | * i915_gem_release_mmap - remove physical page mappings |
| 1295 | * @obj: obj in question |
| 1296 | * |
André Goddard Rosa | af901ca | 2009-11-14 13:09:05 -0200 | [diff] [blame] | 1297 | * Preserve the reservation of the mmapping with the DRM core code, but |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1298 | * relinquish ownership of the pages back to the system. |
| 1299 | * |
| 1300 | * It is vital that we remove the page mapping if we have mapped a tiled |
| 1301 | * object through the GTT and then lose the fence register due to |
| 1302 | * resource pressure. Similarly if the object has been moved out of the |
| 1303 | * aperture, than pages mapped into userspace must be revoked. Removing the |
| 1304 | * mapping will then trigger a page fault on the next user access, allowing |
| 1305 | * fixup by i915_gem_fault(). |
| 1306 | */ |
Eric Anholt | d05ca30 | 2009-07-10 13:02:26 -0700 | [diff] [blame] | 1307 | void |
Chris Wilson | 901782b | 2009-07-10 08:18:50 +0100 | [diff] [blame] | 1308 | i915_gem_release_mmap(struct drm_gem_object *obj) |
| 1309 | { |
| 1310 | struct drm_device *dev = obj->dev; |
| 1311 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1312 | |
| 1313 | if (dev->dev_mapping) |
| 1314 | unmap_mapping_range(dev->dev_mapping, |
| 1315 | obj_priv->mmap_offset, obj->size, 1); |
| 1316 | } |
| 1317 | |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1318 | static void |
| 1319 | i915_gem_free_mmap_offset(struct drm_gem_object *obj) |
| 1320 | { |
| 1321 | struct drm_device *dev = obj->dev; |
| 1322 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1323 | struct drm_gem_mm *mm = dev->mm_private; |
| 1324 | struct drm_map_list *list; |
| 1325 | |
| 1326 | list = &obj->map_list; |
| 1327 | drm_ht_remove_item(&mm->offset_hash, &list->hash); |
| 1328 | |
| 1329 | if (list->file_offset_node) { |
| 1330 | drm_mm_put_block(list->file_offset_node); |
| 1331 | list->file_offset_node = NULL; |
| 1332 | } |
| 1333 | |
| 1334 | if (list->map) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1335 | kfree(list->map); |
Jesse Barnes | ab00b3e | 2009-02-11 14:01:46 -0800 | [diff] [blame] | 1336 | list->map = NULL; |
| 1337 | } |
| 1338 | |
| 1339 | obj_priv->mmap_offset = 0; |
| 1340 | } |
| 1341 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1342 | /** |
| 1343 | * i915_gem_get_gtt_alignment - return required GTT alignment for an object |
| 1344 | * @obj: object to check |
| 1345 | * |
| 1346 | * Return the required GTT alignment for an object, taking into account |
| 1347 | * potential fence register mapping if needed. |
| 1348 | */ |
| 1349 | static uint32_t |
| 1350 | i915_gem_get_gtt_alignment(struct drm_gem_object *obj) |
| 1351 | { |
| 1352 | struct drm_device *dev = obj->dev; |
| 1353 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1354 | int start, i; |
| 1355 | |
| 1356 | /* |
| 1357 | * Minimum alignment is 4k (GTT page size), but might be greater |
| 1358 | * if a fence register is needed for the object. |
| 1359 | */ |
| 1360 | if (IS_I965G(dev) || obj_priv->tiling_mode == I915_TILING_NONE) |
| 1361 | return 4096; |
| 1362 | |
| 1363 | /* |
| 1364 | * Previous chips need to be aligned to the size of the smallest |
| 1365 | * fence register that can contain the object. |
| 1366 | */ |
| 1367 | if (IS_I9XX(dev)) |
| 1368 | start = 1024*1024; |
| 1369 | else |
| 1370 | start = 512*1024; |
| 1371 | |
| 1372 | for (i = start; i < obj->size; i <<= 1) |
| 1373 | ; |
| 1374 | |
| 1375 | return i; |
| 1376 | } |
| 1377 | |
| 1378 | /** |
| 1379 | * i915_gem_mmap_gtt_ioctl - prepare an object for GTT mmap'ing |
| 1380 | * @dev: DRM device |
| 1381 | * @data: GTT mapping ioctl data |
| 1382 | * @file_priv: GEM object info |
| 1383 | * |
| 1384 | * Simply returns the fake offset to userspace so it can mmap it. |
| 1385 | * The mmap call will end up in drm_gem_mmap(), which will set things |
| 1386 | * up so we can get faults in the handler above. |
| 1387 | * |
| 1388 | * The fault handler will take care of binding the object into the GTT |
| 1389 | * (since it may have been evicted to make room for something), allocating |
| 1390 | * a fence register, and mapping the appropriate aperture address into |
| 1391 | * userspace. |
| 1392 | */ |
| 1393 | int |
| 1394 | i915_gem_mmap_gtt_ioctl(struct drm_device *dev, void *data, |
| 1395 | struct drm_file *file_priv) |
| 1396 | { |
| 1397 | struct drm_i915_gem_mmap_gtt *args = data; |
| 1398 | struct drm_i915_private *dev_priv = dev->dev_private; |
| 1399 | struct drm_gem_object *obj; |
| 1400 | struct drm_i915_gem_object *obj_priv; |
| 1401 | int ret; |
| 1402 | |
| 1403 | if (!(dev->driver->driver_features & DRIVER_GEM)) |
| 1404 | return -ENODEV; |
| 1405 | |
| 1406 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 1407 | if (obj == NULL) |
| 1408 | return -EBADF; |
| 1409 | |
| 1410 | mutex_lock(&dev->struct_mutex); |
| 1411 | |
| 1412 | obj_priv = obj->driver_private; |
| 1413 | |
Chris Wilson | ab18282 | 2009-09-22 18:46:17 +0100 | [diff] [blame] | 1414 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 1415 | DRM_ERROR("Attempting to mmap a purgeable buffer\n"); |
| 1416 | drm_gem_object_unreference(obj); |
| 1417 | mutex_unlock(&dev->struct_mutex); |
| 1418 | return -EINVAL; |
| 1419 | } |
| 1420 | |
| 1421 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1422 | if (!obj_priv->mmap_offset) { |
| 1423 | ret = i915_gem_create_mmap_offset(obj); |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1424 | if (ret) { |
| 1425 | drm_gem_object_unreference(obj); |
| 1426 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1427 | return ret; |
Chris Wilson | 13af106 | 2009-02-11 14:26:31 +0000 | [diff] [blame] | 1428 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1429 | } |
| 1430 | |
| 1431 | args->offset = obj_priv->mmap_offset; |
| 1432 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1433 | /* |
| 1434 | * Pull it into the GTT so that we have a page list (makes the |
| 1435 | * initial fault faster and any subsequent flushing possible). |
| 1436 | */ |
| 1437 | if (!obj_priv->agp_mem) { |
Chris Wilson | e67b8ce | 2009-09-14 16:50:26 +0100 | [diff] [blame] | 1438 | ret = i915_gem_object_bind_to_gtt(obj, 0); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1439 | if (ret) { |
| 1440 | drm_gem_object_unreference(obj); |
| 1441 | mutex_unlock(&dev->struct_mutex); |
| 1442 | return ret; |
| 1443 | } |
Jesse Barnes | 14b6039 | 2009-05-20 16:47:08 -0400 | [diff] [blame] | 1444 | list_add_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1445 | } |
| 1446 | |
| 1447 | drm_gem_object_unreference(obj); |
| 1448 | mutex_unlock(&dev->struct_mutex); |
| 1449 | |
| 1450 | return 0; |
| 1451 | } |
| 1452 | |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 1453 | void |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1454 | i915_gem_object_put_pages(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1455 | { |
| 1456 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1457 | int page_count = obj->size / PAGE_SIZE; |
| 1458 | int i; |
| 1459 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1460 | BUG_ON(obj_priv->pages_refcount == 0); |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1461 | BUG_ON(obj_priv->madv == __I915_MADV_PURGED); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1462 | |
| 1463 | if (--obj_priv->pages_refcount != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1464 | return; |
| 1465 | |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 1466 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 1467 | i915_gem_object_save_bit_17_swizzle(obj); |
| 1468 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1469 | if (obj_priv->madv == I915_MADV_DONTNEED) |
Chris Wilson | 13a05fd | 2009-09-20 23:03:19 +0100 | [diff] [blame] | 1470 | obj_priv->dirty = 0; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1471 | |
| 1472 | for (i = 0; i < page_count; i++) { |
| 1473 | if (obj_priv->pages[i] == NULL) |
| 1474 | break; |
| 1475 | |
| 1476 | if (obj_priv->dirty) |
| 1477 | set_page_dirty(obj_priv->pages[i]); |
| 1478 | |
| 1479 | if (obj_priv->madv == I915_MADV_WILLNEED) |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1480 | mark_page_accessed(obj_priv->pages[i]); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 1481 | |
| 1482 | page_cache_release(obj_priv->pages[i]); |
| 1483 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1484 | obj_priv->dirty = 0; |
| 1485 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 1486 | drm_free_large(obj_priv->pages); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 1487 | obj_priv->pages = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1488 | } |
| 1489 | |
| 1490 | static void |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1491 | i915_gem_object_move_to_active(struct drm_gem_object *obj, uint32_t seqno) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1492 | { |
| 1493 | struct drm_device *dev = obj->dev; |
| 1494 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1495 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1496 | |
| 1497 | /* Add a reference if we're newly entering the active list. */ |
| 1498 | if (!obj_priv->active) { |
| 1499 | drm_gem_object_reference(obj); |
| 1500 | obj_priv->active = 1; |
| 1501 | } |
| 1502 | /* Move from whatever list we were on to the tail of execution. */ |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1503 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1504 | list_move_tail(&obj_priv->list, |
| 1505 | &dev_priv->mm.active_list); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1506 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1507 | obj_priv->last_rendering_seqno = seqno; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1508 | } |
| 1509 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1510 | static void |
| 1511 | i915_gem_object_move_to_flushing(struct drm_gem_object *obj) |
| 1512 | { |
| 1513 | struct drm_device *dev = obj->dev; |
| 1514 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1515 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1516 | |
| 1517 | BUG_ON(!obj_priv->active); |
| 1518 | list_move_tail(&obj_priv->list, &dev_priv->mm.flushing_list); |
| 1519 | obj_priv->last_rendering_seqno = 0; |
| 1520 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1521 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1522 | /* Immediately discard the backing storage */ |
| 1523 | static void |
| 1524 | i915_gem_object_truncate(struct drm_gem_object *obj) |
| 1525 | { |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1526 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1527 | struct inode *inode; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1528 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 1529 | inode = obj->filp->f_path.dentry->d_inode; |
| 1530 | if (inode->i_op->truncate) |
| 1531 | inode->i_op->truncate (inode); |
| 1532 | |
| 1533 | obj_priv->madv = __I915_MADV_PURGED; |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 1534 | } |
| 1535 | |
| 1536 | static inline int |
| 1537 | i915_gem_object_is_purgeable(struct drm_i915_gem_object *obj_priv) |
| 1538 | { |
| 1539 | return obj_priv->madv == I915_MADV_DONTNEED; |
| 1540 | } |
| 1541 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1542 | static void |
| 1543 | i915_gem_object_move_to_inactive(struct drm_gem_object *obj) |
| 1544 | { |
| 1545 | struct drm_device *dev = obj->dev; |
| 1546 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1547 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1548 | |
| 1549 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 1550 | if (obj_priv->pin_count != 0) |
| 1551 | list_del_init(&obj_priv->list); |
| 1552 | else |
| 1553 | list_move_tail(&obj_priv->list, &dev_priv->mm.inactive_list); |
| 1554 | |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 1555 | BUG_ON(!list_empty(&obj_priv->gpu_write_list)); |
| 1556 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1557 | obj_priv->last_rendering_seqno = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1558 | if (obj_priv->active) { |
| 1559 | obj_priv->active = 0; |
| 1560 | drm_gem_object_unreference(obj); |
| 1561 | } |
| 1562 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 1563 | } |
| 1564 | |
| 1565 | /** |
| 1566 | * Creates a new sequence number, emitting a write of it to the status page |
| 1567 | * plus an interrupt, which will trigger i915_user_interrupt_handler. |
| 1568 | * |
| 1569 | * Must be called with struct_lock held. |
| 1570 | * |
| 1571 | * Returned sequence numbers are nonzero on success. |
| 1572 | */ |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1573 | uint32_t |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1574 | i915_add_request(struct drm_device *dev, struct drm_file *file_priv, |
| 1575 | uint32_t flush_domains) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1576 | { |
| 1577 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1578 | struct drm_i915_file_private *i915_file_priv = NULL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1579 | struct drm_i915_gem_request *request; |
| 1580 | uint32_t seqno; |
| 1581 | int was_empty; |
| 1582 | RING_LOCALS; |
| 1583 | |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1584 | if (file_priv != NULL) |
| 1585 | i915_file_priv = file_priv->driver_priv; |
| 1586 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1587 | request = kzalloc(sizeof(*request), GFP_KERNEL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1588 | if (request == NULL) |
| 1589 | return 0; |
| 1590 | |
| 1591 | /* Grab the seqno we're going to make this request be, and bump the |
| 1592 | * next (skipping 0 so it can be the reserved no-seqno value). |
| 1593 | */ |
| 1594 | seqno = dev_priv->mm.next_gem_seqno; |
| 1595 | dev_priv->mm.next_gem_seqno++; |
| 1596 | if (dev_priv->mm.next_gem_seqno == 0) |
| 1597 | dev_priv->mm.next_gem_seqno++; |
| 1598 | |
| 1599 | BEGIN_LP_RING(4); |
| 1600 | OUT_RING(MI_STORE_DWORD_INDEX); |
| 1601 | OUT_RING(I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT); |
| 1602 | OUT_RING(seqno); |
| 1603 | |
| 1604 | OUT_RING(MI_USER_INTERRUPT); |
| 1605 | ADVANCE_LP_RING(); |
| 1606 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 1607 | DRM_DEBUG_DRIVER("%d\n", seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1608 | |
| 1609 | request->seqno = seqno; |
| 1610 | request->emitted_jiffies = jiffies; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1611 | was_empty = list_empty(&dev_priv->mm.request_list); |
| 1612 | list_add_tail(&request->list, &dev_priv->mm.request_list); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1613 | if (i915_file_priv) { |
| 1614 | list_add_tail(&request->client_list, |
| 1615 | &i915_file_priv->mm.request_list); |
| 1616 | } else { |
| 1617 | INIT_LIST_HEAD(&request->client_list); |
| 1618 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1619 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1620 | /* Associate any objects on the flushing list matching the write |
| 1621 | * domain we're flushing with our flush. |
| 1622 | */ |
| 1623 | if (flush_domains != 0) { |
| 1624 | struct drm_i915_gem_object *obj_priv, *next; |
| 1625 | |
| 1626 | list_for_each_entry_safe(obj_priv, next, |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 1627 | &dev_priv->mm.gpu_write_list, |
| 1628 | gpu_write_list) { |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1629 | struct drm_gem_object *obj = obj_priv->obj; |
| 1630 | |
| 1631 | if ((obj->write_domain & flush_domains) == |
| 1632 | obj->write_domain) { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1633 | uint32_t old_write_domain = obj->write_domain; |
| 1634 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1635 | obj->write_domain = 0; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 1636 | list_del_init(&obj_priv->gpu_write_list); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1637 | i915_gem_object_move_to_active(obj, seqno); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1638 | |
| 1639 | trace_i915_gem_object_change_domain(obj, |
| 1640 | obj->read_domains, |
| 1641 | old_write_domain); |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1642 | } |
| 1643 | } |
| 1644 | |
| 1645 | } |
| 1646 | |
Ben Gamari | f65d942 | 2009-09-14 17:48:44 -0400 | [diff] [blame] | 1647 | if (!dev_priv->mm.suspended) { |
| 1648 | mod_timer(&dev_priv->hangcheck_timer, jiffies + DRM_I915_HANGCHECK_PERIOD); |
| 1649 | if (was_empty) |
| 1650 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
| 1651 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1652 | return seqno; |
| 1653 | } |
| 1654 | |
| 1655 | /** |
| 1656 | * Command execution barrier |
| 1657 | * |
| 1658 | * Ensures that all commands in the ring are finished |
| 1659 | * before signalling the CPU |
| 1660 | */ |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 1661 | static uint32_t |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1662 | i915_retire_commands(struct drm_device *dev) |
| 1663 | { |
| 1664 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1665 | uint32_t cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 1666 | uint32_t flush_domains = 0; |
| 1667 | RING_LOCALS; |
| 1668 | |
| 1669 | /* The sampler always gets flushed on i965 (sigh) */ |
| 1670 | if (IS_I965G(dev)) |
| 1671 | flush_domains |= I915_GEM_DOMAIN_SAMPLER; |
| 1672 | BEGIN_LP_RING(2); |
| 1673 | OUT_RING(cmd); |
| 1674 | OUT_RING(0); /* noop */ |
| 1675 | ADVANCE_LP_RING(); |
| 1676 | return flush_domains; |
| 1677 | } |
| 1678 | |
| 1679 | /** |
| 1680 | * Moves buffers associated only with the given active seqno from the active |
| 1681 | * to inactive list, potentially freeing them. |
| 1682 | */ |
| 1683 | static void |
| 1684 | i915_gem_retire_request(struct drm_device *dev, |
| 1685 | struct drm_i915_gem_request *request) |
| 1686 | { |
| 1687 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1688 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1689 | trace_i915_gem_request_retire(dev, request->seqno); |
| 1690 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1691 | /* Move any buffers on the active list that are no longer referenced |
| 1692 | * by the ringbuffer to the flushing/inactive lists as appropriate. |
| 1693 | */ |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1694 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1695 | while (!list_empty(&dev_priv->mm.active_list)) { |
| 1696 | struct drm_gem_object *obj; |
| 1697 | struct drm_i915_gem_object *obj_priv; |
| 1698 | |
| 1699 | obj_priv = list_first_entry(&dev_priv->mm.active_list, |
| 1700 | struct drm_i915_gem_object, |
| 1701 | list); |
| 1702 | obj = obj_priv->obj; |
| 1703 | |
| 1704 | /* If the seqno being retired doesn't match the oldest in the |
| 1705 | * list, then the oldest in the list must still be newer than |
| 1706 | * this seqno. |
| 1707 | */ |
| 1708 | if (obj_priv->last_rendering_seqno != request->seqno) |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1709 | goto out; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 1710 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1711 | #if WATCH_LRU |
| 1712 | DRM_INFO("%s: retire %d moves to inactive list %p\n", |
| 1713 | __func__, request->seqno, obj); |
| 1714 | #endif |
| 1715 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 1716 | if (obj->write_domain != 0) |
| 1717 | i915_gem_object_move_to_flushing(obj); |
Shaohua Li | 68c8434 | 2009-04-08 10:58:23 +0800 | [diff] [blame] | 1718 | else { |
| 1719 | /* Take a reference on the object so it won't be |
| 1720 | * freed while the spinlock is held. The list |
| 1721 | * protection for this spinlock is safe when breaking |
| 1722 | * the lock like this since the next thing we do |
| 1723 | * is just get the head of the list again. |
| 1724 | */ |
| 1725 | drm_gem_object_reference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1726 | i915_gem_object_move_to_inactive(obj); |
Shaohua Li | 68c8434 | 2009-04-08 10:58:23 +0800 | [diff] [blame] | 1727 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 1728 | drm_gem_object_unreference(obj); |
| 1729 | spin_lock(&dev_priv->mm.active_list_lock); |
| 1730 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1731 | } |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 1732 | out: |
| 1733 | spin_unlock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1734 | } |
| 1735 | |
| 1736 | /** |
| 1737 | * Returns true if seq1 is later than seq2. |
| 1738 | */ |
Ben Gamari | 22be172 | 2009-09-14 17:48:43 -0400 | [diff] [blame] | 1739 | bool |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1740 | i915_seqno_passed(uint32_t seq1, uint32_t seq2) |
| 1741 | { |
| 1742 | return (int32_t)(seq1 - seq2) >= 0; |
| 1743 | } |
| 1744 | |
| 1745 | uint32_t |
| 1746 | i915_get_gem_seqno(struct drm_device *dev) |
| 1747 | { |
| 1748 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1749 | |
| 1750 | return READ_HWSP(dev_priv, I915_GEM_HWS_INDEX); |
| 1751 | } |
| 1752 | |
| 1753 | /** |
| 1754 | * This function clears the request list as sequence numbers are passed. |
| 1755 | */ |
| 1756 | void |
| 1757 | i915_gem_retire_requests(struct drm_device *dev) |
| 1758 | { |
| 1759 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1760 | uint32_t seqno; |
| 1761 | |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1762 | if (!dev_priv->hw_status_page || list_empty(&dev_priv->mm.request_list)) |
Karsten Wiese | 6c0594a | 2009-02-23 15:07:57 +0100 | [diff] [blame] | 1763 | return; |
| 1764 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1765 | seqno = i915_get_gem_seqno(dev); |
| 1766 | |
| 1767 | while (!list_empty(&dev_priv->mm.request_list)) { |
| 1768 | struct drm_i915_gem_request *request; |
| 1769 | uint32_t retiring_seqno; |
| 1770 | |
| 1771 | request = list_first_entry(&dev_priv->mm.request_list, |
| 1772 | struct drm_i915_gem_request, |
| 1773 | list); |
| 1774 | retiring_seqno = request->seqno; |
| 1775 | |
| 1776 | if (i915_seqno_passed(seqno, retiring_seqno) || |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1777 | atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1778 | i915_gem_retire_request(dev, request); |
| 1779 | |
| 1780 | list_del(&request->list); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 1781 | list_del(&request->client_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 1782 | kfree(request); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1783 | } else |
| 1784 | break; |
| 1785 | } |
Chris Wilson | 9d34e5d | 2009-09-24 05:26:06 +0100 | [diff] [blame] | 1786 | |
| 1787 | if (unlikely (dev_priv->trace_irq_seqno && |
| 1788 | i915_seqno_passed(dev_priv->trace_irq_seqno, seqno))) { |
| 1789 | i915_user_irq_put(dev); |
| 1790 | dev_priv->trace_irq_seqno = 0; |
| 1791 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1792 | } |
| 1793 | |
| 1794 | void |
| 1795 | i915_gem_retire_work_handler(struct work_struct *work) |
| 1796 | { |
| 1797 | drm_i915_private_t *dev_priv; |
| 1798 | struct drm_device *dev; |
| 1799 | |
| 1800 | dev_priv = container_of(work, drm_i915_private_t, |
| 1801 | mm.retire_work.work); |
| 1802 | dev = dev_priv->dev; |
| 1803 | |
| 1804 | mutex_lock(&dev->struct_mutex); |
| 1805 | i915_gem_retire_requests(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 1806 | if (!dev_priv->mm.suspended && |
| 1807 | !list_empty(&dev_priv->mm.request_list)) |
Eric Anholt | 9c9fe1f | 2009-08-03 16:09:16 -0700 | [diff] [blame] | 1808 | queue_delayed_work(dev_priv->wq, &dev_priv->mm.retire_work, HZ); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1809 | mutex_unlock(&dev->struct_mutex); |
| 1810 | } |
| 1811 | |
Daniel Vetter | 5a5a0c6 | 2009-09-15 22:57:36 +0200 | [diff] [blame] | 1812 | int |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1813 | i915_do_wait_request(struct drm_device *dev, uint32_t seqno, int interruptible) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1814 | { |
| 1815 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1816 | u32 ier; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1817 | int ret = 0; |
| 1818 | |
| 1819 | BUG_ON(seqno == 0); |
| 1820 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1821 | if (atomic_read(&dev_priv->mm.wedged)) |
Ben Gamari | ffed1d0 | 2009-09-14 17:48:41 -0400 | [diff] [blame] | 1822 | return -EIO; |
| 1823 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1824 | if (!i915_seqno_passed(i915_get_gem_seqno(dev), seqno)) { |
Adam Jackson | f2b115e | 2009-12-03 17:14:42 -0500 | [diff] [blame] | 1825 | if (IS_IRONLAKE(dev)) |
Zhenyu Wang | 036a4a7 | 2009-06-08 14:40:19 +0800 | [diff] [blame] | 1826 | ier = I915_READ(DEIER) | I915_READ(GTIER); |
| 1827 | else |
| 1828 | ier = I915_READ(IER); |
Jesse Barnes | 802c7eb | 2009-05-05 16:03:48 -0700 | [diff] [blame] | 1829 | if (!ier) { |
| 1830 | DRM_ERROR("something (likely vbetool) disabled " |
| 1831 | "interrupts, re-enabling\n"); |
| 1832 | i915_driver_irq_preinstall(dev); |
| 1833 | i915_driver_irq_postinstall(dev); |
| 1834 | } |
| 1835 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1836 | trace_i915_gem_request_wait_begin(dev, seqno); |
| 1837 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1838 | dev_priv->mm.waiting_gem_seqno = seqno; |
| 1839 | i915_user_irq_get(dev); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1840 | if (interruptible) |
| 1841 | ret = wait_event_interruptible(dev_priv->irq_queue, |
| 1842 | i915_seqno_passed(i915_get_gem_seqno(dev), seqno) || |
| 1843 | atomic_read(&dev_priv->mm.wedged)); |
| 1844 | else |
| 1845 | wait_event(dev_priv->irq_queue, |
| 1846 | i915_seqno_passed(i915_get_gem_seqno(dev), seqno) || |
| 1847 | atomic_read(&dev_priv->mm.wedged)); |
| 1848 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1849 | i915_user_irq_put(dev); |
| 1850 | dev_priv->mm.waiting_gem_seqno = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1851 | |
| 1852 | trace_i915_gem_request_wait_end(dev, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1853 | } |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 1854 | if (atomic_read(&dev_priv->mm.wedged)) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1855 | ret = -EIO; |
| 1856 | |
| 1857 | if (ret && ret != -ERESTARTSYS) |
| 1858 | DRM_ERROR("%s returns %d (awaiting %d at %d)\n", |
| 1859 | __func__, ret, seqno, i915_get_gem_seqno(dev)); |
| 1860 | |
| 1861 | /* Directly dispatch request retiring. While we have the work queue |
| 1862 | * to handle this, the waiter on a request often wants an associated |
| 1863 | * buffer to have made it to the inactive list, and we would need |
| 1864 | * a separate wait queue to handle that. |
| 1865 | */ |
| 1866 | if (ret == 0) |
| 1867 | i915_gem_retire_requests(dev); |
| 1868 | |
| 1869 | return ret; |
| 1870 | } |
| 1871 | |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1872 | /** |
| 1873 | * Waits for a sequence number to be signaled, and cleans up the |
| 1874 | * request and object lists appropriately for that event. |
| 1875 | */ |
| 1876 | static int |
| 1877 | i915_wait_request(struct drm_device *dev, uint32_t seqno) |
| 1878 | { |
| 1879 | return i915_do_wait_request(dev, seqno, 1); |
| 1880 | } |
| 1881 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1882 | static void |
| 1883 | i915_gem_flush(struct drm_device *dev, |
| 1884 | uint32_t invalidate_domains, |
| 1885 | uint32_t flush_domains) |
| 1886 | { |
| 1887 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 1888 | uint32_t cmd; |
| 1889 | RING_LOCALS; |
| 1890 | |
| 1891 | #if WATCH_EXEC |
| 1892 | DRM_INFO("%s: invalidate %08x flush %08x\n", __func__, |
| 1893 | invalidate_domains, flush_domains); |
| 1894 | #endif |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 1895 | trace_i915_gem_request_flush(dev, dev_priv->mm.next_gem_seqno, |
| 1896 | invalidate_domains, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1897 | |
| 1898 | if (flush_domains & I915_GEM_DOMAIN_CPU) |
| 1899 | drm_agp_chipset_flush(dev); |
| 1900 | |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 1901 | if ((invalidate_domains | flush_domains) & I915_GEM_GPU_DOMAINS) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1902 | /* |
| 1903 | * read/write caches: |
| 1904 | * |
| 1905 | * I915_GEM_DOMAIN_RENDER is always invalidated, but is |
| 1906 | * only flushed if MI_NO_WRITE_FLUSH is unset. On 965, it is |
| 1907 | * also flushed at 2d versus 3d pipeline switches. |
| 1908 | * |
| 1909 | * read-only caches: |
| 1910 | * |
| 1911 | * I915_GEM_DOMAIN_SAMPLER is flushed on pre-965 if |
| 1912 | * MI_READ_FLUSH is set, and is always flushed on 965. |
| 1913 | * |
| 1914 | * I915_GEM_DOMAIN_COMMAND may not exist? |
| 1915 | * |
| 1916 | * I915_GEM_DOMAIN_INSTRUCTION, which exists on 965, is |
| 1917 | * invalidated when MI_EXE_FLUSH is set. |
| 1918 | * |
| 1919 | * I915_GEM_DOMAIN_VERTEX, which exists on 965, is |
| 1920 | * invalidated with every MI_FLUSH. |
| 1921 | * |
| 1922 | * TLBs: |
| 1923 | * |
| 1924 | * On 965, TLBs associated with I915_GEM_DOMAIN_COMMAND |
| 1925 | * and I915_GEM_DOMAIN_CPU in are invalidated at PTE write and |
| 1926 | * I915_GEM_DOMAIN_RENDER and I915_GEM_DOMAIN_SAMPLER |
| 1927 | * are flushed at any MI_FLUSH. |
| 1928 | */ |
| 1929 | |
| 1930 | cmd = MI_FLUSH | MI_NO_WRITE_FLUSH; |
| 1931 | if ((invalidate_domains|flush_domains) & |
| 1932 | I915_GEM_DOMAIN_RENDER) |
| 1933 | cmd &= ~MI_NO_WRITE_FLUSH; |
| 1934 | if (!IS_I965G(dev)) { |
| 1935 | /* |
| 1936 | * On the 965, the sampler cache always gets flushed |
| 1937 | * and this bit is reserved. |
| 1938 | */ |
| 1939 | if (invalidate_domains & I915_GEM_DOMAIN_SAMPLER) |
| 1940 | cmd |= MI_READ_FLUSH; |
| 1941 | } |
| 1942 | if (invalidate_domains & I915_GEM_DOMAIN_INSTRUCTION) |
| 1943 | cmd |= MI_EXE_FLUSH; |
| 1944 | |
| 1945 | #if WATCH_EXEC |
| 1946 | DRM_INFO("%s: queue flush %08x to ring\n", __func__, cmd); |
| 1947 | #endif |
| 1948 | BEGIN_LP_RING(2); |
| 1949 | OUT_RING(cmd); |
Daniel Vetter | 48764bf | 2009-09-15 22:57:32 +0200 | [diff] [blame] | 1950 | OUT_RING(MI_NOOP); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1951 | ADVANCE_LP_RING(); |
| 1952 | } |
| 1953 | } |
| 1954 | |
| 1955 | /** |
| 1956 | * Ensures that all rendering to the object has completed and the object is |
| 1957 | * safe to unbind from the GTT or access from the CPU. |
| 1958 | */ |
| 1959 | static int |
| 1960 | i915_gem_object_wait_rendering(struct drm_gem_object *obj) |
| 1961 | { |
| 1962 | struct drm_device *dev = obj->dev; |
| 1963 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1964 | int ret; |
| 1965 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1966 | /* This function only exists to support waiting for existing rendering, |
| 1967 | * not for emitting required flushes. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1968 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 1969 | BUG_ON((obj->write_domain & I915_GEM_GPU_DOMAINS) != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1970 | |
| 1971 | /* If there is rendering queued on the buffer being evicted, wait for |
| 1972 | * it. |
| 1973 | */ |
| 1974 | if (obj_priv->active) { |
| 1975 | #if WATCH_BUF |
| 1976 | DRM_INFO("%s: object %p wait for seqno %08x\n", |
| 1977 | __func__, obj, obj_priv->last_rendering_seqno); |
| 1978 | #endif |
| 1979 | ret = i915_wait_request(dev, obj_priv->last_rendering_seqno); |
| 1980 | if (ret != 0) |
| 1981 | return ret; |
| 1982 | } |
| 1983 | |
| 1984 | return 0; |
| 1985 | } |
| 1986 | |
| 1987 | /** |
| 1988 | * Unbinds an object from the GTT aperture. |
| 1989 | */ |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 1990 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 1991 | i915_gem_object_unbind(struct drm_gem_object *obj) |
| 1992 | { |
| 1993 | struct drm_device *dev = obj->dev; |
| 1994 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 1995 | int ret = 0; |
| 1996 | |
| 1997 | #if WATCH_BUF |
| 1998 | DRM_INFO("%s:%d %p\n", __func__, __LINE__, obj); |
| 1999 | DRM_INFO("gtt_space %p\n", obj_priv->gtt_space); |
| 2000 | #endif |
| 2001 | if (obj_priv->gtt_space == NULL) |
| 2002 | return 0; |
| 2003 | |
| 2004 | if (obj_priv->pin_count != 0) { |
| 2005 | DRM_ERROR("Attempting to unbind pinned buffer\n"); |
| 2006 | return -EINVAL; |
| 2007 | } |
| 2008 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2009 | /* blow away mappings if mapped through GTT */ |
| 2010 | i915_gem_release_mmap(obj); |
| 2011 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2012 | /* Move the object to the CPU domain to ensure that |
| 2013 | * any possible CPU writes while it's not in the GTT |
| 2014 | * are flushed when we go to remap it. This will |
| 2015 | * also ensure that all pending GPU writes are finished |
| 2016 | * before we unbind. |
| 2017 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2018 | ret = i915_gem_object_set_to_cpu_domain(obj, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2019 | if (ret) { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2020 | if (ret != -ERESTARTSYS) |
| 2021 | DRM_ERROR("set_domain failed: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2022 | return ret; |
| 2023 | } |
| 2024 | |
Eric Anholt | 5323fd0 | 2009-09-09 11:50:45 -0700 | [diff] [blame] | 2025 | BUG_ON(obj_priv->active); |
| 2026 | |
Daniel Vetter | 96b47b6 | 2009-12-15 17:50:00 +0100 | [diff] [blame] | 2027 | /* release the fence reg _after_ flushing */ |
| 2028 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) |
| 2029 | i915_gem_clear_fence_reg(obj); |
| 2030 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2031 | if (obj_priv->agp_mem != NULL) { |
| 2032 | drm_unbind_agp(obj_priv->agp_mem); |
| 2033 | drm_free_agp(obj_priv->agp_mem, obj->size / PAGE_SIZE); |
| 2034 | obj_priv->agp_mem = NULL; |
| 2035 | } |
| 2036 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2037 | i915_gem_object_put_pages(obj); |
Chris Wilson | a32808c | 2009-09-20 21:29:47 +0100 | [diff] [blame] | 2038 | BUG_ON(obj_priv->pages_refcount); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2039 | |
| 2040 | if (obj_priv->gtt_space) { |
| 2041 | atomic_dec(&dev->gtt_count); |
| 2042 | atomic_sub(obj->size, &dev->gtt_memory); |
| 2043 | |
| 2044 | drm_mm_put_block(obj_priv->gtt_space); |
| 2045 | obj_priv->gtt_space = NULL; |
| 2046 | } |
| 2047 | |
| 2048 | /* Remove ourselves from the LRU list if present. */ |
| 2049 | if (!list_empty(&obj_priv->list)) |
| 2050 | list_del_init(&obj_priv->list); |
| 2051 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2052 | if (i915_gem_object_is_purgeable(obj_priv)) |
| 2053 | i915_gem_object_truncate(obj); |
| 2054 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2055 | trace_i915_gem_object_unbind(obj); |
| 2056 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2057 | return 0; |
| 2058 | } |
| 2059 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2060 | static struct drm_gem_object * |
| 2061 | i915_gem_find_inactive_object(struct drm_device *dev, int min_size) |
| 2062 | { |
| 2063 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2064 | struct drm_i915_gem_object *obj_priv; |
| 2065 | struct drm_gem_object *best = NULL; |
| 2066 | struct drm_gem_object *first = NULL; |
| 2067 | |
| 2068 | /* Try to find the smallest clean object */ |
| 2069 | list_for_each_entry(obj_priv, &dev_priv->mm.inactive_list, list) { |
| 2070 | struct drm_gem_object *obj = obj_priv->obj; |
| 2071 | if (obj->size >= min_size) { |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 2072 | if ((!obj_priv->dirty || |
| 2073 | i915_gem_object_is_purgeable(obj_priv)) && |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2074 | (!best || obj->size < best->size)) { |
| 2075 | best = obj; |
| 2076 | if (best->size == min_size) |
| 2077 | return best; |
| 2078 | } |
| 2079 | if (!first) |
| 2080 | first = obj; |
| 2081 | } |
| 2082 | } |
| 2083 | |
| 2084 | return best ? best : first; |
| 2085 | } |
| 2086 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2087 | static int |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2088 | i915_gem_evict_everything(struct drm_device *dev) |
| 2089 | { |
| 2090 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2091 | int ret; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 2092 | uint32_t seqno; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2093 | bool lists_empty; |
| 2094 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2095 | spin_lock(&dev_priv->mm.active_list_lock); |
| 2096 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && |
| 2097 | list_empty(&dev_priv->mm.flushing_list) && |
| 2098 | list_empty(&dev_priv->mm.active_list)); |
| 2099 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 2100 | |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2101 | if (lists_empty) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2102 | return -ENOSPC; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2103 | |
| 2104 | /* Flush everything (on to the inactive lists) and evict */ |
| 2105 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 2106 | seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); |
| 2107 | if (seqno == 0) |
| 2108 | return -ENOMEM; |
| 2109 | |
| 2110 | ret = i915_wait_request(dev, seqno); |
| 2111 | if (ret) |
| 2112 | return ret; |
| 2113 | |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 2114 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 2115 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 2116 | ret = i915_gem_evict_from_inactive_list(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2117 | if (ret) |
| 2118 | return ret; |
| 2119 | |
| 2120 | spin_lock(&dev_priv->mm.active_list_lock); |
| 2121 | lists_empty = (list_empty(&dev_priv->mm.inactive_list) && |
| 2122 | list_empty(&dev_priv->mm.flushing_list) && |
| 2123 | list_empty(&dev_priv->mm.active_list)); |
| 2124 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 2125 | BUG_ON(!lists_empty); |
| 2126 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2127 | return 0; |
| 2128 | } |
| 2129 | |
| 2130 | static int |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2131 | i915_gem_evict_something(struct drm_device *dev, int min_size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2132 | { |
| 2133 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2134 | struct drm_gem_object *obj; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2135 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2136 | |
| 2137 | for (;;) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2138 | i915_gem_retire_requests(dev); |
| 2139 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2140 | /* If there's an inactive buffer available now, grab it |
| 2141 | * and be done. |
| 2142 | */ |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2143 | obj = i915_gem_find_inactive_object(dev, min_size); |
| 2144 | if (obj) { |
| 2145 | struct drm_i915_gem_object *obj_priv; |
| 2146 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2147 | #if WATCH_LRU |
| 2148 | DRM_INFO("%s: evicting %p\n", __func__, obj); |
| 2149 | #endif |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2150 | obj_priv = obj->driver_private; |
| 2151 | BUG_ON(obj_priv->pin_count != 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2152 | BUG_ON(obj_priv->active); |
| 2153 | |
| 2154 | /* Wait on the rendering and unbind the buffer. */ |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2155 | return i915_gem_object_unbind(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2156 | } |
| 2157 | |
| 2158 | /* If we didn't get anything, but the ring is still processing |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2159 | * things, wait for the next to finish and hopefully leave us |
| 2160 | * a buffer to evict. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2161 | */ |
| 2162 | if (!list_empty(&dev_priv->mm.request_list)) { |
| 2163 | struct drm_i915_gem_request *request; |
| 2164 | |
| 2165 | request = list_first_entry(&dev_priv->mm.request_list, |
| 2166 | struct drm_i915_gem_request, |
| 2167 | list); |
| 2168 | |
| 2169 | ret = i915_wait_request(dev, request->seqno); |
| 2170 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2171 | return ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2172 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2173 | continue; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2174 | } |
| 2175 | |
| 2176 | /* If we didn't have anything on the request list but there |
| 2177 | * are buffers awaiting a flush, emit one and try again. |
| 2178 | * When we wait on it, those buffers waiting for that flush |
| 2179 | * will get moved to inactive. |
| 2180 | */ |
| 2181 | if (!list_empty(&dev_priv->mm.flushing_list)) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2182 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2183 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2184 | /* Find an object that we can immediately reuse */ |
| 2185 | list_for_each_entry(obj_priv, &dev_priv->mm.flushing_list, list) { |
| 2186 | obj = obj_priv->obj; |
| 2187 | if (obj->size >= min_size) |
| 2188 | break; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2189 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2190 | obj = NULL; |
| 2191 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2192 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2193 | if (obj != NULL) { |
| 2194 | uint32_t seqno; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2195 | |
Chris Wilson | 9a1e258 | 2009-09-20 20:16:50 +0100 | [diff] [blame] | 2196 | i915_gem_flush(dev, |
| 2197 | obj->write_domain, |
| 2198 | obj->write_domain); |
| 2199 | seqno = i915_add_request(dev, NULL, obj->write_domain); |
| 2200 | if (seqno == 0) |
| 2201 | return -ENOMEM; |
| 2202 | |
| 2203 | ret = i915_wait_request(dev, seqno); |
| 2204 | if (ret) |
| 2205 | return ret; |
| 2206 | |
| 2207 | continue; |
| 2208 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2209 | } |
| 2210 | |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2211 | /* If we didn't do any of the above, there's no single buffer |
| 2212 | * large enough to swap out for the new one, so just evict |
| 2213 | * everything and start again. (This should be rare.) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2214 | */ |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2215 | if (!list_empty (&dev_priv->mm.inactive_list)) |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 2216 | return i915_gem_evict_from_inactive_list(dev); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2217 | else |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2218 | return i915_gem_evict_everything(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2219 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 2220 | } |
| 2221 | |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 2222 | int |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2223 | i915_gem_object_get_pages(struct drm_gem_object *obj, |
| 2224 | gfp_t gfpmask) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2225 | { |
| 2226 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2227 | int page_count, i; |
| 2228 | struct address_space *mapping; |
| 2229 | struct inode *inode; |
| 2230 | struct page *page; |
| 2231 | int ret; |
| 2232 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2233 | if (obj_priv->pages_refcount++ != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2234 | return 0; |
| 2235 | |
| 2236 | /* Get the list of pages out of our struct file. They'll be pinned |
| 2237 | * at this point until we release them. |
| 2238 | */ |
| 2239 | page_count = obj->size / PAGE_SIZE; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2240 | BUG_ON(obj_priv->pages != NULL); |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 2241 | obj_priv->pages = drm_calloc_large(page_count, sizeof(struct page *)); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2242 | if (obj_priv->pages == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2243 | obj_priv->pages_refcount--; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2244 | return -ENOMEM; |
| 2245 | } |
| 2246 | |
| 2247 | inode = obj->filp->f_path.dentry->d_inode; |
| 2248 | mapping = inode->i_mapping; |
| 2249 | for (i = 0; i < page_count; i++) { |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2250 | page = read_cache_page_gfp(mapping, i, |
| 2251 | mapping_gfp_mask (mapping) | |
| 2252 | __GFP_COLD | |
| 2253 | gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2254 | if (IS_ERR(page)) { |
| 2255 | ret = PTR_ERR(page); |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2256 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2257 | return ret; |
| 2258 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2259 | obj_priv->pages[i] = page; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2260 | } |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 2261 | |
| 2262 | if (obj_priv->tiling_mode != I915_TILING_NONE) |
| 2263 | i915_gem_object_do_bit_17_swizzle(obj); |
| 2264 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2265 | return 0; |
| 2266 | } |
| 2267 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2268 | static void i965_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2269 | { |
| 2270 | struct drm_gem_object *obj = reg->obj; |
| 2271 | struct drm_device *dev = obj->dev; |
| 2272 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2273 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2274 | int regnum = obj_priv->fence_reg; |
| 2275 | uint64_t val; |
| 2276 | |
| 2277 | val = (uint64_t)((obj_priv->gtt_offset + obj->size - 4096) & |
| 2278 | 0xfffff000) << 32; |
| 2279 | val |= obj_priv->gtt_offset & 0xfffff000; |
| 2280 | val |= ((obj_priv->stride / 128) - 1) << I965_FENCE_PITCH_SHIFT; |
| 2281 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2282 | val |= 1 << I965_FENCE_TILING_Y_SHIFT; |
| 2283 | val |= I965_FENCE_REG_VALID; |
| 2284 | |
| 2285 | I915_WRITE64(FENCE_REG_965_0 + (regnum * 8), val); |
| 2286 | } |
| 2287 | |
| 2288 | static void i915_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2289 | { |
| 2290 | struct drm_gem_object *obj = reg->obj; |
| 2291 | struct drm_device *dev = obj->dev; |
| 2292 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2293 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2294 | int regnum = obj_priv->fence_reg; |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2295 | int tile_width; |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2296 | uint32_t fence_reg, val; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2297 | uint32_t pitch_val; |
| 2298 | |
| 2299 | if ((obj_priv->gtt_offset & ~I915_FENCE_START_MASK) || |
| 2300 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Linus Torvalds | f06da26 | 2009-02-09 08:57:29 -0800 | [diff] [blame] | 2301 | WARN(1, "%s: object 0x%08x not 1M or size (0x%zx) aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2302 | __func__, obj_priv->gtt_offset, obj->size); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2303 | return; |
| 2304 | } |
| 2305 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2306 | if (obj_priv->tiling_mode == I915_TILING_Y && |
| 2307 | HAS_128_BYTE_Y_TILING(dev)) |
| 2308 | tile_width = 128; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2309 | else |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2310 | tile_width = 512; |
| 2311 | |
| 2312 | /* Note: pitch better be a power of two tile widths */ |
| 2313 | pitch_val = obj_priv->stride / tile_width; |
| 2314 | pitch_val = ffs(pitch_val) - 1; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2315 | |
| 2316 | val = obj_priv->gtt_offset; |
| 2317 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2318 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
| 2319 | val |= I915_FENCE_SIZE_BITS(obj->size); |
| 2320 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2321 | val |= I830_FENCE_REG_VALID; |
| 2322 | |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2323 | if (regnum < 8) |
| 2324 | fence_reg = FENCE_REG_830_0 + (regnum * 4); |
| 2325 | else |
| 2326 | fence_reg = FENCE_REG_945_8 + ((regnum - 8) * 4); |
| 2327 | I915_WRITE(fence_reg, val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2328 | } |
| 2329 | |
| 2330 | static void i830_write_fence_reg(struct drm_i915_fence_reg *reg) |
| 2331 | { |
| 2332 | struct drm_gem_object *obj = reg->obj; |
| 2333 | struct drm_device *dev = obj->dev; |
| 2334 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2335 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2336 | int regnum = obj_priv->fence_reg; |
| 2337 | uint32_t val; |
| 2338 | uint32_t pitch_val; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2339 | uint32_t fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2340 | |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2341 | if ((obj_priv->gtt_offset & ~I830_FENCE_START_MASK) || |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2342 | (obj_priv->gtt_offset & (obj->size - 1))) { |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2343 | WARN(1, "%s: object 0x%08x not 512K or size aligned\n", |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2344 | __func__, obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2345 | return; |
| 2346 | } |
| 2347 | |
Eric Anholt | e76a16d | 2009-05-26 17:44:56 -0700 | [diff] [blame] | 2348 | pitch_val = obj_priv->stride / 128; |
| 2349 | pitch_val = ffs(pitch_val) - 1; |
| 2350 | WARN_ON(pitch_val > I830_FENCE_MAX_PITCH_VAL); |
| 2351 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2352 | val = obj_priv->gtt_offset; |
| 2353 | if (obj_priv->tiling_mode == I915_TILING_Y) |
| 2354 | val |= 1 << I830_FENCE_TILING_Y_SHIFT; |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2355 | fence_size_bits = I830_FENCE_SIZE_BITS(obj->size); |
| 2356 | WARN_ON(fence_size_bits & ~0x00000f00); |
| 2357 | val |= fence_size_bits; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2358 | val |= pitch_val << I830_FENCE_PITCH_SHIFT; |
| 2359 | val |= I830_FENCE_REG_VALID; |
| 2360 | |
| 2361 | I915_WRITE(FENCE_REG_830_0 + (regnum * 4), val); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2362 | } |
| 2363 | |
| 2364 | /** |
| 2365 | * i915_gem_object_get_fence_reg - set up a fence reg for an object |
| 2366 | * @obj: object to map through a fence reg |
| 2367 | * |
| 2368 | * When mapping objects through the GTT, userspace wants to be able to write |
| 2369 | * to them without having to worry about swizzling if the object is tiled. |
| 2370 | * |
| 2371 | * This function walks the fence regs looking for a free one for @obj, |
| 2372 | * stealing one if it can't find any. |
| 2373 | * |
| 2374 | * It then sets up the reg based on the object's properties: address, pitch |
| 2375 | * and tiling format. |
| 2376 | */ |
Chris Wilson | 8c4b8c3 | 2009-06-17 22:08:52 +0100 | [diff] [blame] | 2377 | int |
| 2378 | i915_gem_object_get_fence_reg(struct drm_gem_object *obj) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2379 | { |
| 2380 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2381 | struct drm_i915_private *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2382 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2383 | struct drm_i915_fence_reg *reg = NULL; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2384 | struct drm_i915_gem_object *old_obj_priv = NULL; |
| 2385 | int i, ret, avail; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2386 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2387 | /* Just update our place in the LRU if our fence is getting used. */ |
| 2388 | if (obj_priv->fence_reg != I915_FENCE_REG_NONE) { |
| 2389 | list_move_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); |
| 2390 | return 0; |
| 2391 | } |
| 2392 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2393 | switch (obj_priv->tiling_mode) { |
| 2394 | case I915_TILING_NONE: |
| 2395 | WARN(1, "allocating a fence for non-tiled object?\n"); |
| 2396 | break; |
| 2397 | case I915_TILING_X: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2398 | if (!obj_priv->stride) |
| 2399 | return -EINVAL; |
| 2400 | WARN((obj_priv->stride & (512 - 1)), |
| 2401 | "object 0x%08x is X tiled but has non-512B pitch\n", |
| 2402 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2403 | break; |
| 2404 | case I915_TILING_Y: |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2405 | if (!obj_priv->stride) |
| 2406 | return -EINVAL; |
| 2407 | WARN((obj_priv->stride & (128 - 1)), |
| 2408 | "object 0x%08x is Y tiled but has non-128B pitch\n", |
| 2409 | obj_priv->gtt_offset); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2410 | break; |
| 2411 | } |
| 2412 | |
| 2413 | /* First try to find a free reg */ |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2414 | avail = 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2415 | for (i = dev_priv->fence_reg_start; i < dev_priv->num_fence_regs; i++) { |
| 2416 | reg = &dev_priv->fence_regs[i]; |
| 2417 | if (!reg->obj) |
| 2418 | break; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2419 | |
| 2420 | old_obj_priv = reg->obj->driver_private; |
| 2421 | if (!old_obj_priv->pin_count) |
| 2422 | avail++; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2423 | } |
| 2424 | |
| 2425 | /* None available, try to steal one or wait for a user to finish */ |
| 2426 | if (i == dev_priv->num_fence_regs) { |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2427 | struct drm_gem_object *old_obj = NULL; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2428 | |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2429 | if (avail == 0) |
Chris Wilson | 2939e1f | 2009-06-06 09:46:03 +0100 | [diff] [blame] | 2430 | return -ENOSPC; |
Chris Wilson | fc7170b | 2009-02-11 14:26:46 +0000 | [diff] [blame] | 2431 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2432 | list_for_each_entry(old_obj_priv, &dev_priv->mm.fence_list, |
| 2433 | fence_list) { |
| 2434 | old_obj = old_obj_priv->obj; |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2435 | |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2436 | if (old_obj_priv->pin_count) |
| 2437 | continue; |
| 2438 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2439 | /* Take a reference, as otherwise the wait_rendering |
| 2440 | * below may cause the object to get freed out from |
| 2441 | * under us. |
| 2442 | */ |
| 2443 | drm_gem_object_reference(old_obj); |
| 2444 | |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2445 | /* i915 uses fences for GPU access to tiled buffers */ |
| 2446 | if (IS_I965G(dev) || !old_obj_priv->active) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2447 | break; |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2448 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2449 | /* This brings the object to the head of the LRU if it |
| 2450 | * had been written to. The only way this should |
| 2451 | * result in us waiting longer than the expected |
| 2452 | * optimal amount of time is if there was a |
| 2453 | * fence-using buffer later that was read-only. |
| 2454 | */ |
| 2455 | i915_gem_object_flush_gpu_write_domain(old_obj); |
| 2456 | ret = i915_gem_object_wait_rendering(old_obj); |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2457 | if (ret != 0) { |
| 2458 | drm_gem_object_unreference(old_obj); |
Chris Wilson | d7619c4 | 2009-02-11 14:26:47 +0000 | [diff] [blame] | 2459 | return ret; |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2460 | } |
| 2461 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2462 | break; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2463 | } |
| 2464 | |
| 2465 | /* |
| 2466 | * Zap this virtual mapping so we can set up a fence again |
| 2467 | * for this object next time we need it. |
| 2468 | */ |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2469 | i915_gem_release_mmap(old_obj); |
| 2470 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2471 | i = old_obj_priv->fence_reg; |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2472 | reg = &dev_priv->fence_regs[i]; |
| 2473 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2474 | old_obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2475 | list_del_init(&old_obj_priv->fence_list); |
Chris Wilson | 58c2fb6 | 2009-09-01 12:02:39 +0100 | [diff] [blame] | 2476 | |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2477 | drm_gem_object_unreference(old_obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2478 | } |
| 2479 | |
| 2480 | obj_priv->fence_reg = i; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2481 | list_add_tail(&obj_priv->fence_list, &dev_priv->mm.fence_list); |
| 2482 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2483 | reg->obj = obj; |
| 2484 | |
| 2485 | if (IS_I965G(dev)) |
| 2486 | i965_write_fence_reg(reg); |
| 2487 | else if (IS_I9XX(dev)) |
| 2488 | i915_write_fence_reg(reg); |
| 2489 | else |
| 2490 | i830_write_fence_reg(reg); |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2491 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2492 | trace_i915_gem_object_get_fence(obj, i, obj_priv->tiling_mode); |
| 2493 | |
Eric Anholt | d9ddcb9 | 2009-01-27 10:33:49 -0800 | [diff] [blame] | 2494 | return 0; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2495 | } |
| 2496 | |
| 2497 | /** |
| 2498 | * i915_gem_clear_fence_reg - clear out fence register info |
| 2499 | * @obj: object to clear |
| 2500 | * |
| 2501 | * Zeroes out the fence register itself and clears out the associated |
| 2502 | * data structures in dev_priv and obj_priv. |
| 2503 | */ |
| 2504 | static void |
| 2505 | i915_gem_clear_fence_reg(struct drm_gem_object *obj) |
| 2506 | { |
| 2507 | struct drm_device *dev = obj->dev; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2508 | drm_i915_private_t *dev_priv = dev->dev_private; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2509 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2510 | |
| 2511 | if (IS_I965G(dev)) |
| 2512 | I915_WRITE64(FENCE_REG_965_0 + (obj_priv->fence_reg * 8), 0); |
Eric Anholt | dc529a4 | 2009-03-10 22:34:49 -0700 | [diff] [blame] | 2513 | else { |
| 2514 | uint32_t fence_reg; |
| 2515 | |
| 2516 | if (obj_priv->fence_reg < 8) |
| 2517 | fence_reg = FENCE_REG_830_0 + obj_priv->fence_reg * 4; |
| 2518 | else |
| 2519 | fence_reg = FENCE_REG_945_8 + (obj_priv->fence_reg - |
| 2520 | 8) * 4; |
| 2521 | |
| 2522 | I915_WRITE(fence_reg, 0); |
| 2523 | } |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2524 | |
| 2525 | dev_priv->fence_regs[obj_priv->fence_reg].obj = NULL; |
| 2526 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 2527 | list_del_init(&obj_priv->fence_list); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 2528 | } |
| 2529 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2530 | /** |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2531 | * i915_gem_object_put_fence_reg - waits on outstanding fenced access |
| 2532 | * to the buffer to finish, and then resets the fence register. |
| 2533 | * @obj: tiled object holding a fence register. |
| 2534 | * |
| 2535 | * Zeroes out the fence register itself and clears out the associated |
| 2536 | * data structures in dev_priv and obj_priv. |
| 2537 | */ |
| 2538 | int |
| 2539 | i915_gem_object_put_fence_reg(struct drm_gem_object *obj) |
| 2540 | { |
| 2541 | struct drm_device *dev = obj->dev; |
| 2542 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2543 | |
| 2544 | if (obj_priv->fence_reg == I915_FENCE_REG_NONE) |
| 2545 | return 0; |
| 2546 | |
Daniel Vetter | 10ae9bd | 2010-02-01 13:59:17 +0100 | [diff] [blame] | 2547 | /* If we've changed tiling, GTT-mappings of the object |
| 2548 | * need to re-fault to ensure that the correct fence register |
| 2549 | * setup is in place. |
| 2550 | */ |
| 2551 | i915_gem_release_mmap(obj); |
| 2552 | |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2553 | /* On the i915, GPU access to tiled buffers is via a fence, |
| 2554 | * therefore we must wait for any outstanding access to complete |
| 2555 | * before clearing the fence. |
| 2556 | */ |
| 2557 | if (!IS_I965G(dev)) { |
| 2558 | int ret; |
| 2559 | |
| 2560 | i915_gem_object_flush_gpu_write_domain(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2561 | ret = i915_gem_object_wait_rendering(obj); |
| 2562 | if (ret != 0) |
| 2563 | return ret; |
| 2564 | } |
| 2565 | |
Daniel Vetter | 4a72661 | 2010-02-01 13:59:16 +0100 | [diff] [blame] | 2566 | i915_gem_object_flush_gtt_write_domain(obj); |
Chris Wilson | 52dc7d3 | 2009-06-06 09:46:01 +0100 | [diff] [blame] | 2567 | i915_gem_clear_fence_reg (obj); |
| 2568 | |
| 2569 | return 0; |
| 2570 | } |
| 2571 | |
| 2572 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2573 | * Finds free space in the GTT aperture and binds the object there. |
| 2574 | */ |
| 2575 | static int |
| 2576 | i915_gem_object_bind_to_gtt(struct drm_gem_object *obj, unsigned alignment) |
| 2577 | { |
| 2578 | struct drm_device *dev = obj->dev; |
| 2579 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 2580 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2581 | struct drm_mm_node *free_space; |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2582 | gfp_t gfpmask = __GFP_NORETRY | __GFP_NOWARN; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2583 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2584 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 2585 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 2586 | DRM_ERROR("Attempting to bind a purgeable object\n"); |
| 2587 | return -EINVAL; |
| 2588 | } |
| 2589 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2590 | if (alignment == 0) |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 2591 | alignment = i915_gem_get_gtt_alignment(obj); |
Daniel Vetter | 8d7773a | 2009-03-29 14:09:41 +0200 | [diff] [blame] | 2592 | if (alignment & (i915_gem_get_gtt_alignment(obj) - 1)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2593 | DRM_ERROR("Invalid object alignment requested %u\n", alignment); |
| 2594 | return -EINVAL; |
| 2595 | } |
| 2596 | |
| 2597 | search_free: |
| 2598 | free_space = drm_mm_search_free(&dev_priv->mm.gtt_space, |
| 2599 | obj->size, alignment, 0); |
| 2600 | if (free_space != NULL) { |
| 2601 | obj_priv->gtt_space = drm_mm_get_block(free_space, obj->size, |
| 2602 | alignment); |
| 2603 | if (obj_priv->gtt_space != NULL) { |
| 2604 | obj_priv->gtt_space->private = obj; |
| 2605 | obj_priv->gtt_offset = obj_priv->gtt_space->start; |
| 2606 | } |
| 2607 | } |
| 2608 | if (obj_priv->gtt_space == NULL) { |
| 2609 | /* If the gtt is empty and we're still having trouble |
| 2610 | * fitting our object in, we're out of memory. |
| 2611 | */ |
| 2612 | #if WATCH_LRU |
| 2613 | DRM_INFO("%s: GTT full, evicting something\n", __func__); |
| 2614 | #endif |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2615 | ret = i915_gem_evict_something(dev, obj->size); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2616 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2617 | return ret; |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2618 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2619 | goto search_free; |
| 2620 | } |
| 2621 | |
| 2622 | #if WATCH_BUF |
Krzysztof Halasa | cfd43c0 | 2009-06-20 00:31:28 +0200 | [diff] [blame] | 2623 | DRM_INFO("Binding object of size %zd at 0x%08x\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2624 | obj->size, obj_priv->gtt_offset); |
| 2625 | #endif |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2626 | ret = i915_gem_object_get_pages(obj, gfpmask); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2627 | if (ret) { |
| 2628 | drm_mm_put_block(obj_priv->gtt_space); |
| 2629 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2630 | |
| 2631 | if (ret == -ENOMEM) { |
| 2632 | /* first try to clear up some space from the GTT */ |
| 2633 | ret = i915_gem_evict_something(dev, obj->size); |
| 2634 | if (ret) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2635 | /* now try to shrink everyone else */ |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 2636 | if (gfpmask) { |
| 2637 | gfpmask = 0; |
| 2638 | goto search_free; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2639 | } |
| 2640 | |
| 2641 | return ret; |
| 2642 | } |
| 2643 | |
| 2644 | goto search_free; |
| 2645 | } |
| 2646 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2647 | return ret; |
| 2648 | } |
| 2649 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2650 | /* Create an AGP memory structure pointing at our pages, and bind it |
| 2651 | * into the GTT. |
| 2652 | */ |
| 2653 | obj_priv->agp_mem = drm_agp_bind_pages(dev, |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2654 | obj_priv->pages, |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2655 | obj->size >> PAGE_SHIFT, |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 2656 | obj_priv->gtt_offset, |
| 2657 | obj_priv->agp_type); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2658 | if (obj_priv->agp_mem == NULL) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2659 | i915_gem_object_put_pages(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2660 | drm_mm_put_block(obj_priv->gtt_space); |
| 2661 | obj_priv->gtt_space = NULL; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2662 | |
| 2663 | ret = i915_gem_evict_something(dev, obj->size); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 2664 | if (ret) |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2665 | return ret; |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 2666 | |
| 2667 | goto search_free; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2668 | } |
| 2669 | atomic_inc(&dev->gtt_count); |
| 2670 | atomic_add(obj->size, &dev->gtt_memory); |
| 2671 | |
| 2672 | /* Assert that the object is not currently in any GPU domain. As it |
| 2673 | * wasn't in the GTT, there shouldn't be any way it could have been in |
| 2674 | * a GPU cache |
| 2675 | */ |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 2676 | BUG_ON(obj->read_domains & I915_GEM_GPU_DOMAINS); |
| 2677 | BUG_ON(obj->write_domain & I915_GEM_GPU_DOMAINS); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2678 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2679 | trace_i915_gem_object_bind(obj, obj_priv->gtt_offset); |
| 2680 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2681 | return 0; |
| 2682 | } |
| 2683 | |
| 2684 | void |
| 2685 | i915_gem_clflush_object(struct drm_gem_object *obj) |
| 2686 | { |
| 2687 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2688 | |
| 2689 | /* If we don't have a page list set up, then we're not pinned |
| 2690 | * to GPU, and we can ignore the cache flush because it'll happen |
| 2691 | * again at bind time. |
| 2692 | */ |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2693 | if (obj_priv->pages == NULL) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2694 | return; |
| 2695 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2696 | trace_i915_gem_object_clflush(obj); |
Eric Anholt | cfa16a0 | 2009-05-26 18:46:16 -0700 | [diff] [blame] | 2697 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 2698 | drm_clflush_pages(obj_priv->pages, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2699 | } |
| 2700 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2701 | /** Flushes any GPU write domain for the object if it's dirty. */ |
| 2702 | static void |
| 2703 | i915_gem_object_flush_gpu_write_domain(struct drm_gem_object *obj) |
| 2704 | { |
| 2705 | struct drm_device *dev = obj->dev; |
| 2706 | uint32_t seqno; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2707 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2708 | |
| 2709 | if ((obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
| 2710 | return; |
| 2711 | |
| 2712 | /* Queue the GPU write cache flushing we need. */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2713 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2714 | i915_gem_flush(dev, 0, obj->write_domain); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 2715 | seqno = i915_add_request(dev, NULL, obj->write_domain); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 2716 | BUG_ON(obj->write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2717 | i915_gem_object_move_to_active(obj, seqno); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2718 | |
| 2719 | trace_i915_gem_object_change_domain(obj, |
| 2720 | obj->read_domains, |
| 2721 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2722 | } |
| 2723 | |
| 2724 | /** Flushes the GTT write domain for the object if it's dirty. */ |
| 2725 | static void |
| 2726 | i915_gem_object_flush_gtt_write_domain(struct drm_gem_object *obj) |
| 2727 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2728 | uint32_t old_write_domain; |
| 2729 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2730 | if (obj->write_domain != I915_GEM_DOMAIN_GTT) |
| 2731 | return; |
| 2732 | |
| 2733 | /* No actual flushing is required for the GTT write domain. Writes |
| 2734 | * to it immediately go to main memory as far as we know, so there's |
| 2735 | * no chipset flush. It also doesn't land in render cache. |
| 2736 | */ |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2737 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2738 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2739 | |
| 2740 | trace_i915_gem_object_change_domain(obj, |
| 2741 | obj->read_domains, |
| 2742 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2743 | } |
| 2744 | |
| 2745 | /** Flushes the CPU write domain for the object if it's dirty. */ |
| 2746 | static void |
| 2747 | i915_gem_object_flush_cpu_write_domain(struct drm_gem_object *obj) |
| 2748 | { |
| 2749 | struct drm_device *dev = obj->dev; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2750 | uint32_t old_write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2751 | |
| 2752 | if (obj->write_domain != I915_GEM_DOMAIN_CPU) |
| 2753 | return; |
| 2754 | |
| 2755 | i915_gem_clflush_object(obj); |
| 2756 | drm_agp_chipset_flush(dev); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2757 | old_write_domain = obj->write_domain; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2758 | obj->write_domain = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2759 | |
| 2760 | trace_i915_gem_object_change_domain(obj, |
| 2761 | obj->read_domains, |
| 2762 | old_write_domain); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2763 | } |
| 2764 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 2765 | void |
| 2766 | i915_gem_object_flush_write_domain(struct drm_gem_object *obj) |
| 2767 | { |
| 2768 | switch (obj->write_domain) { |
| 2769 | case I915_GEM_DOMAIN_GTT: |
| 2770 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2771 | break; |
| 2772 | case I915_GEM_DOMAIN_CPU: |
| 2773 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2774 | break; |
| 2775 | default: |
| 2776 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2777 | break; |
| 2778 | } |
| 2779 | } |
| 2780 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2781 | /** |
| 2782 | * Moves a single object to the GTT read, and possibly write domain. |
| 2783 | * |
| 2784 | * This function returns when the move is complete, including waiting on |
| 2785 | * flushes to occur. |
| 2786 | */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 2787 | int |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2788 | i915_gem_object_set_to_gtt_domain(struct drm_gem_object *obj, int write) |
| 2789 | { |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2790 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2791 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2792 | int ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2793 | |
Eric Anholt | 0235439 | 2008-11-26 13:58:13 -0800 | [diff] [blame] | 2794 | /* Not valid to be called on unbound objects. */ |
| 2795 | if (obj_priv->gtt_space == NULL) |
| 2796 | return -EINVAL; |
| 2797 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2798 | i915_gem_object_flush_gpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2799 | /* Wait on any GPU rendering and flushing to occur. */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2800 | ret = i915_gem_object_wait_rendering(obj); |
| 2801 | if (ret != 0) |
| 2802 | return ret; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2803 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2804 | old_write_domain = obj->write_domain; |
| 2805 | old_read_domains = obj->read_domains; |
| 2806 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2807 | /* If we're writing through the GTT domain, then CPU and GPU caches |
| 2808 | * will need to be invalidated at next use. |
| 2809 | */ |
| 2810 | if (write) |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2811 | obj->read_domains &= I915_GEM_DOMAIN_GTT; |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2812 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2813 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2814 | |
| 2815 | /* It should now be out of any other write domains, and we can update |
| 2816 | * the domain values for our changes. |
| 2817 | */ |
| 2818 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2819 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2820 | if (write) { |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2821 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2822 | obj_priv->dirty = 1; |
| 2823 | } |
| 2824 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2825 | trace_i915_gem_object_change_domain(obj, |
| 2826 | old_read_domains, |
| 2827 | old_write_domain); |
| 2828 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2829 | return 0; |
| 2830 | } |
| 2831 | |
Zhenyu Wang | b9241ea | 2009-11-25 13:09:39 +0800 | [diff] [blame] | 2832 | /* |
| 2833 | * Prepare buffer for display plane. Use uninterruptible for possible flush |
| 2834 | * wait, as in modesetting process we're not supposed to be interrupted. |
| 2835 | */ |
| 2836 | int |
| 2837 | i915_gem_object_set_to_display_plane(struct drm_gem_object *obj) |
| 2838 | { |
| 2839 | struct drm_device *dev = obj->dev; |
| 2840 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 2841 | uint32_t old_write_domain, old_read_domains; |
| 2842 | int ret; |
| 2843 | |
| 2844 | /* Not valid to be called on unbound objects. */ |
| 2845 | if (obj_priv->gtt_space == NULL) |
| 2846 | return -EINVAL; |
| 2847 | |
| 2848 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2849 | |
| 2850 | /* Wait on any GPU rendering and flushing to occur. */ |
| 2851 | if (obj_priv->active) { |
| 2852 | #if WATCH_BUF |
| 2853 | DRM_INFO("%s: object %p wait for seqno %08x\n", |
| 2854 | __func__, obj, obj_priv->last_rendering_seqno); |
| 2855 | #endif |
| 2856 | ret = i915_do_wait_request(dev, obj_priv->last_rendering_seqno, 0); |
| 2857 | if (ret != 0) |
| 2858 | return ret; |
| 2859 | } |
| 2860 | |
| 2861 | old_write_domain = obj->write_domain; |
| 2862 | old_read_domains = obj->read_domains; |
| 2863 | |
| 2864 | obj->read_domains &= I915_GEM_DOMAIN_GTT; |
| 2865 | |
| 2866 | i915_gem_object_flush_cpu_write_domain(obj); |
| 2867 | |
| 2868 | /* It should now be out of any other write domains, and we can update |
| 2869 | * the domain values for our changes. |
| 2870 | */ |
| 2871 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_GTT) != 0); |
| 2872 | obj->read_domains |= I915_GEM_DOMAIN_GTT; |
| 2873 | obj->write_domain = I915_GEM_DOMAIN_GTT; |
| 2874 | obj_priv->dirty = 1; |
| 2875 | |
| 2876 | trace_i915_gem_object_change_domain(obj, |
| 2877 | old_read_domains, |
| 2878 | old_write_domain); |
| 2879 | |
| 2880 | return 0; |
| 2881 | } |
| 2882 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2883 | /** |
| 2884 | * Moves a single object to the CPU read, and possibly write domain. |
| 2885 | * |
| 2886 | * This function returns when the move is complete, including waiting on |
| 2887 | * flushes to occur. |
| 2888 | */ |
| 2889 | static int |
| 2890 | i915_gem_object_set_to_cpu_domain(struct drm_gem_object *obj, int write) |
| 2891 | { |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2892 | uint32_t old_write_domain, old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2893 | int ret; |
| 2894 | |
| 2895 | i915_gem_object_flush_gpu_write_domain(obj); |
| 2896 | /* Wait on any GPU rendering and flushing to occur. */ |
| 2897 | ret = i915_gem_object_wait_rendering(obj); |
| 2898 | if (ret != 0) |
| 2899 | return ret; |
| 2900 | |
| 2901 | i915_gem_object_flush_gtt_write_domain(obj); |
| 2902 | |
| 2903 | /* If we have a partially-valid cache of the object in the CPU, |
| 2904 | * finish invalidating it and free the per-page flags. |
| 2905 | */ |
| 2906 | i915_gem_object_set_to_full_cpu_read_domain(obj); |
| 2907 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2908 | old_write_domain = obj->write_domain; |
| 2909 | old_read_domains = obj->read_domains; |
| 2910 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2911 | /* Flush the CPU cache if it's still invalid. */ |
| 2912 | if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) { |
| 2913 | i915_gem_clflush_object(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 2914 | |
| 2915 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 2916 | } |
| 2917 | |
| 2918 | /* It should now be out of any other write domains, and we can update |
| 2919 | * the domain values for our changes. |
| 2920 | */ |
| 2921 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 2922 | |
| 2923 | /* If we're writing through the CPU, then the GPU read domains will |
| 2924 | * need to be invalidated at next use. |
| 2925 | */ |
| 2926 | if (write) { |
| 2927 | obj->read_domains &= I915_GEM_DOMAIN_CPU; |
| 2928 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 2929 | } |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2930 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 2931 | trace_i915_gem_object_change_domain(obj, |
| 2932 | old_read_domains, |
| 2933 | old_write_domain); |
| 2934 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 2935 | return 0; |
| 2936 | } |
| 2937 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 2938 | /* |
| 2939 | * Set the next domain for the specified object. This |
| 2940 | * may not actually perform the necessary flushing/invaliding though, |
| 2941 | * as that may want to be batched with other set_domain operations |
| 2942 | * |
| 2943 | * This is (we hope) the only really tricky part of gem. The goal |
| 2944 | * is fairly simple -- track which caches hold bits of the object |
| 2945 | * and make sure they remain coherent. A few concrete examples may |
| 2946 | * help to explain how it works. For shorthand, we use the notation |
| 2947 | * (read_domains, write_domain), e.g. (CPU, CPU) to indicate the |
| 2948 | * a pair of read and write domain masks. |
| 2949 | * |
| 2950 | * Case 1: the batch buffer |
| 2951 | * |
| 2952 | * 1. Allocated |
| 2953 | * 2. Written by CPU |
| 2954 | * 3. Mapped to GTT |
| 2955 | * 4. Read by GPU |
| 2956 | * 5. Unmapped from GTT |
| 2957 | * 6. Freed |
| 2958 | * |
| 2959 | * Let's take these a step at a time |
| 2960 | * |
| 2961 | * 1. Allocated |
| 2962 | * Pages allocated from the kernel may still have |
| 2963 | * cache contents, so we set them to (CPU, CPU) always. |
| 2964 | * 2. Written by CPU (using pwrite) |
| 2965 | * The pwrite function calls set_domain (CPU, CPU) and |
| 2966 | * this function does nothing (as nothing changes) |
| 2967 | * 3. Mapped by GTT |
| 2968 | * This function asserts that the object is not |
| 2969 | * currently in any GPU-based read or write domains |
| 2970 | * 4. Read by GPU |
| 2971 | * i915_gem_execbuffer calls set_domain (COMMAND, 0). |
| 2972 | * As write_domain is zero, this function adds in the |
| 2973 | * current read domains (CPU+COMMAND, 0). |
| 2974 | * flush_domains is set to CPU. |
| 2975 | * invalidate_domains is set to COMMAND |
| 2976 | * clflush is run to get data out of the CPU caches |
| 2977 | * then i915_dev_set_domain calls i915_gem_flush to |
| 2978 | * emit an MI_FLUSH and drm_agp_chipset_flush |
| 2979 | * 5. Unmapped from GTT |
| 2980 | * i915_gem_object_unbind calls set_domain (CPU, CPU) |
| 2981 | * flush_domains and invalidate_domains end up both zero |
| 2982 | * so no flushing/invalidating happens |
| 2983 | * 6. Freed |
| 2984 | * yay, done |
| 2985 | * |
| 2986 | * Case 2: The shared render buffer |
| 2987 | * |
| 2988 | * 1. Allocated |
| 2989 | * 2. Mapped to GTT |
| 2990 | * 3. Read/written by GPU |
| 2991 | * 4. set_domain to (CPU,CPU) |
| 2992 | * 5. Read/written by CPU |
| 2993 | * 6. Read/written by GPU |
| 2994 | * |
| 2995 | * 1. Allocated |
| 2996 | * Same as last example, (CPU, CPU) |
| 2997 | * 2. Mapped to GTT |
| 2998 | * Nothing changes (assertions find that it is not in the GPU) |
| 2999 | * 3. Read/written by GPU |
| 3000 | * execbuffer calls set_domain (RENDER, RENDER) |
| 3001 | * flush_domains gets CPU |
| 3002 | * invalidate_domains gets GPU |
| 3003 | * clflush (obj) |
| 3004 | * MI_FLUSH and drm_agp_chipset_flush |
| 3005 | * 4. set_domain (CPU, CPU) |
| 3006 | * flush_domains gets GPU |
| 3007 | * invalidate_domains gets CPU |
| 3008 | * wait_rendering (obj) to make sure all drawing is complete. |
| 3009 | * This will include an MI_FLUSH to get the data from GPU |
| 3010 | * to memory |
| 3011 | * clflush (obj) to invalidate the CPU cache |
| 3012 | * Another MI_FLUSH in i915_gem_flush (eliminate this somehow?) |
| 3013 | * 5. Read/written by CPU |
| 3014 | * cache lines are loaded and dirtied |
| 3015 | * 6. Read written by GPU |
| 3016 | * Same as last GPU access |
| 3017 | * |
| 3018 | * Case 3: The constant buffer |
| 3019 | * |
| 3020 | * 1. Allocated |
| 3021 | * 2. Written by CPU |
| 3022 | * 3. Read by GPU |
| 3023 | * 4. Updated (written) by CPU again |
| 3024 | * 5. Read by GPU |
| 3025 | * |
| 3026 | * 1. Allocated |
| 3027 | * (CPU, CPU) |
| 3028 | * 2. Written by CPU |
| 3029 | * (CPU, CPU) |
| 3030 | * 3. Read by GPU |
| 3031 | * (CPU+RENDER, 0) |
| 3032 | * flush_domains = CPU |
| 3033 | * invalidate_domains = RENDER |
| 3034 | * clflush (obj) |
| 3035 | * MI_FLUSH |
| 3036 | * drm_agp_chipset_flush |
| 3037 | * 4. Updated (written) by CPU again |
| 3038 | * (CPU, CPU) |
| 3039 | * flush_domains = 0 (no previous write domain) |
| 3040 | * invalidate_domains = 0 (no new read domains) |
| 3041 | * 5. Read by GPU |
| 3042 | * (CPU+RENDER, 0) |
| 3043 | * flush_domains = CPU |
| 3044 | * invalidate_domains = RENDER |
| 3045 | * clflush (obj) |
| 3046 | * MI_FLUSH |
| 3047 | * drm_agp_chipset_flush |
| 3048 | */ |
Keith Packard | c0d9082 | 2008-11-20 23:11:08 -0800 | [diff] [blame] | 3049 | static void |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3050 | i915_gem_object_set_to_gpu_domain(struct drm_gem_object *obj) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3051 | { |
| 3052 | struct drm_device *dev = obj->dev; |
| 3053 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3054 | uint32_t invalidate_domains = 0; |
| 3055 | uint32_t flush_domains = 0; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3056 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3057 | |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3058 | BUG_ON(obj->pending_read_domains & I915_GEM_DOMAIN_CPU); |
| 3059 | BUG_ON(obj->pending_write_domain == I915_GEM_DOMAIN_CPU); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3060 | |
Jesse Barnes | 652c393 | 2009-08-17 13:31:43 -0700 | [diff] [blame] | 3061 | intel_mark_busy(dev, obj); |
| 3062 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3063 | #if WATCH_BUF |
| 3064 | DRM_INFO("%s: object %p read %08x -> %08x write %08x -> %08x\n", |
| 3065 | __func__, obj, |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3066 | obj->read_domains, obj->pending_read_domains, |
| 3067 | obj->write_domain, obj->pending_write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3068 | #endif |
| 3069 | /* |
| 3070 | * If the object isn't moving to a new write domain, |
| 3071 | * let the object stay in multiple read domains |
| 3072 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3073 | if (obj->pending_write_domain == 0) |
| 3074 | obj->pending_read_domains |= obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3075 | else |
| 3076 | obj_priv->dirty = 1; |
| 3077 | |
| 3078 | /* |
| 3079 | * Flush the current write domain if |
| 3080 | * the new read domains don't match. Invalidate |
| 3081 | * any read domains which differ from the old |
| 3082 | * write domain |
| 3083 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3084 | if (obj->write_domain && |
| 3085 | obj->write_domain != obj->pending_read_domains) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3086 | flush_domains |= obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3087 | invalidate_domains |= |
| 3088 | obj->pending_read_domains & ~obj->write_domain; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3089 | } |
| 3090 | /* |
| 3091 | * Invalidate any read caches which may have |
| 3092 | * stale data. That is, any new read domains. |
| 3093 | */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3094 | invalidate_domains |= obj->pending_read_domains & ~obj->read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3095 | if ((flush_domains | invalidate_domains) & I915_GEM_DOMAIN_CPU) { |
| 3096 | #if WATCH_BUF |
| 3097 | DRM_INFO("%s: CPU domain flush %08x invalidate %08x\n", |
| 3098 | __func__, flush_domains, invalidate_domains); |
| 3099 | #endif |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3100 | i915_gem_clflush_object(obj); |
| 3101 | } |
| 3102 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3103 | old_read_domains = obj->read_domains; |
| 3104 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3105 | /* The actual obj->write_domain will be updated with |
| 3106 | * pending_write_domain after we emit the accumulated flush for all |
| 3107 | * of our domain changes in execbuffers (which clears objects' |
| 3108 | * write_domains). So if we have a current write domain that we |
| 3109 | * aren't changing, set pending_write_domain to that. |
| 3110 | */ |
| 3111 | if (flush_domains == 0 && obj->pending_write_domain == 0) |
| 3112 | obj->pending_write_domain = obj->write_domain; |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3113 | obj->read_domains = obj->pending_read_domains; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3114 | |
| 3115 | dev->invalidate_domains |= invalidate_domains; |
| 3116 | dev->flush_domains |= flush_domains; |
| 3117 | #if WATCH_BUF |
| 3118 | DRM_INFO("%s: read %08x write %08x invalidate %08x flush %08x\n", |
| 3119 | __func__, |
| 3120 | obj->read_domains, obj->write_domain, |
| 3121 | dev->invalidate_domains, dev->flush_domains); |
| 3122 | #endif |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3123 | |
| 3124 | trace_i915_gem_object_change_domain(obj, |
| 3125 | old_read_domains, |
| 3126 | obj->write_domain); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3127 | } |
| 3128 | |
| 3129 | /** |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3130 | * Moves the object from a partially CPU read to a full one. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3131 | * |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3132 | * Note that this only resolves i915_gem_object_set_cpu_read_domain_range(), |
| 3133 | * and doesn't handle transitioning from !(read_domains & I915_GEM_DOMAIN_CPU). |
| 3134 | */ |
| 3135 | static void |
| 3136 | i915_gem_object_set_to_full_cpu_read_domain(struct drm_gem_object *obj) |
| 3137 | { |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3138 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3139 | |
| 3140 | if (!obj_priv->page_cpu_valid) |
| 3141 | return; |
| 3142 | |
| 3143 | /* If we're partially in the CPU read domain, finish moving it in. |
| 3144 | */ |
| 3145 | if (obj->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3146 | int i; |
| 3147 | |
| 3148 | for (i = 0; i <= (obj->size - 1) / PAGE_SIZE; i++) { |
| 3149 | if (obj_priv->page_cpu_valid[i]) |
| 3150 | continue; |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3151 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3152 | } |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3153 | } |
| 3154 | |
| 3155 | /* Free the page_cpu_valid mappings which are now stale, whether |
| 3156 | * or not we've got I915_GEM_DOMAIN_CPU. |
| 3157 | */ |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3158 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3159 | obj_priv->page_cpu_valid = NULL; |
| 3160 | } |
| 3161 | |
| 3162 | /** |
| 3163 | * Set the CPU read domain on a range of the object. |
| 3164 | * |
| 3165 | * The object ends up with I915_GEM_DOMAIN_CPU in its read flags although it's |
| 3166 | * not entirely valid. The page_cpu_valid member of the object flags which |
| 3167 | * pages have been flushed, and will be respected by |
| 3168 | * i915_gem_object_set_to_cpu_domain() if it's called on to get a valid mapping |
| 3169 | * of the whole object. |
| 3170 | * |
| 3171 | * This function returns when the move is complete, including waiting on |
| 3172 | * flushes to occur. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3173 | */ |
| 3174 | static int |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3175 | i915_gem_object_set_cpu_read_domain_range(struct drm_gem_object *obj, |
| 3176 | uint64_t offset, uint64_t size) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3177 | { |
| 3178 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3179 | uint32_t old_read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3180 | int i, ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3181 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3182 | if (offset == 0 && size == obj->size) |
| 3183 | return i915_gem_object_set_to_cpu_domain(obj, 0); |
| 3184 | |
| 3185 | i915_gem_object_flush_gpu_write_domain(obj); |
| 3186 | /* Wait on any GPU rendering and flushing to occur. */ |
| 3187 | ret = i915_gem_object_wait_rendering(obj); |
| 3188 | if (ret != 0) |
| 3189 | return ret; |
| 3190 | i915_gem_object_flush_gtt_write_domain(obj); |
| 3191 | |
| 3192 | /* If we're already fully in the CPU read domain, we're done. */ |
| 3193 | if (obj_priv->page_cpu_valid == NULL && |
| 3194 | (obj->read_domains & I915_GEM_DOMAIN_CPU) != 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3195 | return 0; |
| 3196 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3197 | /* Otherwise, create/clear the per-page CPU read domain flag if we're |
| 3198 | * newly adding I915_GEM_DOMAIN_CPU |
| 3199 | */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3200 | if (obj_priv->page_cpu_valid == NULL) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3201 | obj_priv->page_cpu_valid = kzalloc(obj->size / PAGE_SIZE, |
| 3202 | GFP_KERNEL); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3203 | if (obj_priv->page_cpu_valid == NULL) |
| 3204 | return -ENOMEM; |
| 3205 | } else if ((obj->read_domains & I915_GEM_DOMAIN_CPU) == 0) |
| 3206 | memset(obj_priv->page_cpu_valid, 0, obj->size / PAGE_SIZE); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3207 | |
| 3208 | /* Flush the cache on any pages that are still invalid from the CPU's |
| 3209 | * perspective. |
| 3210 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3211 | for (i = offset / PAGE_SIZE; i <= (offset + size - 1) / PAGE_SIZE; |
| 3212 | i++) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3213 | if (obj_priv->page_cpu_valid[i]) |
| 3214 | continue; |
| 3215 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 3216 | drm_clflush_pages(obj_priv->pages + i, 1); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3217 | |
| 3218 | obj_priv->page_cpu_valid[i] = 1; |
| 3219 | } |
| 3220 | |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3221 | /* It should now be out of any other write domains, and we can update |
| 3222 | * the domain values for our changes. |
| 3223 | */ |
| 3224 | BUG_ON((obj->write_domain & ~I915_GEM_DOMAIN_CPU) != 0); |
| 3225 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3226 | old_read_domains = obj->read_domains; |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3227 | obj->read_domains |= I915_GEM_DOMAIN_CPU; |
| 3228 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3229 | trace_i915_gem_object_change_domain(obj, |
| 3230 | old_read_domains, |
| 3231 | obj->write_domain); |
| 3232 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3233 | return 0; |
| 3234 | } |
| 3235 | |
| 3236 | /** |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3237 | * Pin an object to the GTT and evaluate the relocations landing in it. |
| 3238 | */ |
| 3239 | static int |
| 3240 | i915_gem_object_pin_and_relocate(struct drm_gem_object *obj, |
| 3241 | struct drm_file *file_priv, |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3242 | struct drm_i915_gem_exec_object2 *entry, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3243 | struct drm_i915_gem_relocation_entry *relocs) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3244 | { |
| 3245 | struct drm_device *dev = obj->dev; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3246 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3247 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 3248 | int i, ret; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3249 | void __iomem *reloc_page; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3250 | bool need_fence; |
| 3251 | |
| 3252 | need_fence = entry->flags & EXEC_OBJECT_NEEDS_FENCE && |
| 3253 | obj_priv->tiling_mode != I915_TILING_NONE; |
| 3254 | |
| 3255 | /* Check fence reg constraints and rebind if necessary */ |
Owain Ainsworth | f590d27 | 2010-02-18 15:33:00 +0000 | [diff] [blame^] | 3256 | if (need_fence && !i915_gem_object_fence_offset_ok(obj, |
| 3257 | obj_priv->tiling_mode)) |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3258 | i915_gem_object_unbind(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3259 | |
| 3260 | /* Choose the GTT offset for our buffer and put it there. */ |
| 3261 | ret = i915_gem_object_pin(obj, (uint32_t) entry->alignment); |
| 3262 | if (ret) |
| 3263 | return ret; |
| 3264 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3265 | /* |
| 3266 | * Pre-965 chips need a fence register set up in order to |
| 3267 | * properly handle blits to/from tiled surfaces. |
| 3268 | */ |
| 3269 | if (need_fence) { |
| 3270 | ret = i915_gem_object_get_fence_reg(obj); |
| 3271 | if (ret != 0) { |
| 3272 | if (ret != -EBUSY && ret != -ERESTARTSYS) |
| 3273 | DRM_ERROR("Failure to install fence: %d\n", |
| 3274 | ret); |
| 3275 | i915_gem_object_unpin(obj); |
| 3276 | return ret; |
| 3277 | } |
| 3278 | } |
| 3279 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3280 | entry->offset = obj_priv->gtt_offset; |
| 3281 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3282 | /* Apply the relocations, using the GTT aperture to avoid cache |
| 3283 | * flushing requirements. |
| 3284 | */ |
| 3285 | for (i = 0; i < entry->relocation_count; i++) { |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3286 | struct drm_i915_gem_relocation_entry *reloc= &relocs[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3287 | struct drm_gem_object *target_obj; |
| 3288 | struct drm_i915_gem_object *target_obj_priv; |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3289 | uint32_t reloc_val, reloc_offset; |
| 3290 | uint32_t __iomem *reloc_entry; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3291 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3292 | target_obj = drm_gem_object_lookup(obj->dev, file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3293 | reloc->target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3294 | if (target_obj == NULL) { |
| 3295 | i915_gem_object_unpin(obj); |
| 3296 | return -EBADF; |
| 3297 | } |
| 3298 | target_obj_priv = target_obj->driver_private; |
| 3299 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3300 | #if WATCH_RELOC |
| 3301 | DRM_INFO("%s: obj %p offset %08x target %d " |
| 3302 | "read %08x write %08x gtt %08x " |
| 3303 | "presumed %08x delta %08x\n", |
| 3304 | __func__, |
| 3305 | obj, |
| 3306 | (int) reloc->offset, |
| 3307 | (int) reloc->target_handle, |
| 3308 | (int) reloc->read_domains, |
| 3309 | (int) reloc->write_domain, |
| 3310 | (int) target_obj_priv->gtt_offset, |
| 3311 | (int) reloc->presumed_offset, |
| 3312 | reloc->delta); |
| 3313 | #endif |
| 3314 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3315 | /* The target buffer should have appeared before us in the |
| 3316 | * exec_object list, so it should have a GTT space bound by now. |
| 3317 | */ |
| 3318 | if (target_obj_priv->gtt_space == NULL) { |
| 3319 | DRM_ERROR("No GTT space found for object %d\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3320 | reloc->target_handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3321 | drm_gem_object_unreference(target_obj); |
| 3322 | i915_gem_object_unpin(obj); |
| 3323 | return -EINVAL; |
| 3324 | } |
| 3325 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3326 | /* Validate that the target is in a valid r/w GPU domain */ |
| 3327 | if (reloc->write_domain & I915_GEM_DOMAIN_CPU || |
| 3328 | reloc->read_domains & I915_GEM_DOMAIN_CPU) { |
| 3329 | DRM_ERROR("reloc with read/write CPU domains: " |
| 3330 | "obj %p target %d offset %d " |
| 3331 | "read %08x write %08x", |
| 3332 | obj, reloc->target_handle, |
| 3333 | (int) reloc->offset, |
| 3334 | reloc->read_domains, |
| 3335 | reloc->write_domain); |
| 3336 | drm_gem_object_unreference(target_obj); |
| 3337 | i915_gem_object_unpin(obj); |
| 3338 | return -EINVAL; |
| 3339 | } |
| 3340 | if (reloc->write_domain && target_obj->pending_write_domain && |
| 3341 | reloc->write_domain != target_obj->pending_write_domain) { |
| 3342 | DRM_ERROR("Write domain conflict: " |
| 3343 | "obj %p target %d offset %d " |
| 3344 | "new %08x old %08x\n", |
| 3345 | obj, reloc->target_handle, |
| 3346 | (int) reloc->offset, |
| 3347 | reloc->write_domain, |
| 3348 | target_obj->pending_write_domain); |
| 3349 | drm_gem_object_unreference(target_obj); |
| 3350 | i915_gem_object_unpin(obj); |
| 3351 | return -EINVAL; |
| 3352 | } |
| 3353 | |
| 3354 | target_obj->pending_read_domains |= reloc->read_domains; |
| 3355 | target_obj->pending_write_domain |= reloc->write_domain; |
| 3356 | |
| 3357 | /* If the relocation already has the right value in it, no |
| 3358 | * more work needs to be done. |
| 3359 | */ |
| 3360 | if (target_obj_priv->gtt_offset == reloc->presumed_offset) { |
| 3361 | drm_gem_object_unreference(target_obj); |
| 3362 | continue; |
| 3363 | } |
| 3364 | |
| 3365 | /* Check that the relocation address is valid... */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3366 | if (reloc->offset > obj->size - 4) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3367 | DRM_ERROR("Relocation beyond object bounds: " |
| 3368 | "obj %p target %d offset %d size %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3369 | obj, reloc->target_handle, |
| 3370 | (int) reloc->offset, (int) obj->size); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3371 | drm_gem_object_unreference(target_obj); |
| 3372 | i915_gem_object_unpin(obj); |
| 3373 | return -EINVAL; |
| 3374 | } |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3375 | if (reloc->offset & 3) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3376 | DRM_ERROR("Relocation not 4-byte aligned: " |
| 3377 | "obj %p target %d offset %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3378 | obj, reloc->target_handle, |
| 3379 | (int) reloc->offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3380 | drm_gem_object_unreference(target_obj); |
| 3381 | i915_gem_object_unpin(obj); |
| 3382 | return -EINVAL; |
| 3383 | } |
| 3384 | |
Chris Wilson | 8542a0b | 2009-09-09 21:15:15 +0100 | [diff] [blame] | 3385 | /* and points to somewhere within the target object. */ |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3386 | if (reloc->delta >= target_obj->size) { |
| 3387 | DRM_ERROR("Relocation beyond target object bounds: " |
| 3388 | "obj %p target %d delta %d size %d.\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3389 | obj, reloc->target_handle, |
Chris Wilson | cd0b9fb | 2009-09-15 23:23:18 +0100 | [diff] [blame] | 3390 | (int) reloc->delta, (int) target_obj->size); |
Chris Wilson | 491152b | 2009-02-11 14:26:32 +0000 | [diff] [blame] | 3391 | drm_gem_object_unreference(target_obj); |
| 3392 | i915_gem_object_unpin(obj); |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 3393 | return -EINVAL; |
| 3394 | } |
| 3395 | |
Eric Anholt | 2ef7eea | 2008-11-10 10:53:25 -0800 | [diff] [blame] | 3396 | ret = i915_gem_object_set_to_gtt_domain(obj, 1); |
| 3397 | if (ret != 0) { |
| 3398 | drm_gem_object_unreference(target_obj); |
| 3399 | i915_gem_object_unpin(obj); |
| 3400 | return -EINVAL; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3401 | } |
| 3402 | |
| 3403 | /* Map the page containing the relocation we're going to |
| 3404 | * perform. |
| 3405 | */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3406 | reloc_offset = obj_priv->gtt_offset + reloc->offset; |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3407 | reloc_page = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping, |
| 3408 | (reloc_offset & |
| 3409 | ~(PAGE_SIZE - 1))); |
Eric Anholt | 3043c60 | 2008-10-02 12:24:47 -0700 | [diff] [blame] | 3410 | reloc_entry = (uint32_t __iomem *)(reloc_page + |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3411 | (reloc_offset & (PAGE_SIZE - 1))); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3412 | reloc_val = target_obj_priv->gtt_offset + reloc->delta; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3413 | |
| 3414 | #if WATCH_BUF |
| 3415 | DRM_INFO("Applied relocation: %p@0x%08x %08x -> %08x\n", |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3416 | obj, (unsigned int) reloc->offset, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3417 | readl(reloc_entry), reloc_val); |
| 3418 | #endif |
| 3419 | writel(reloc_val, reloc_entry); |
Keith Packard | 0839ccb | 2008-10-30 19:38:48 -0700 | [diff] [blame] | 3420 | io_mapping_unmap_atomic(reloc_page); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3421 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3422 | /* The updated presumed offset for this entry will be |
| 3423 | * copied back out to the user. |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3424 | */ |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3425 | reloc->presumed_offset = target_obj_priv->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3426 | |
| 3427 | drm_gem_object_unreference(target_obj); |
| 3428 | } |
| 3429 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3430 | #if WATCH_BUF |
| 3431 | if (0) |
| 3432 | i915_gem_dump_object(obj, 128, __func__, ~0); |
| 3433 | #endif |
| 3434 | return 0; |
| 3435 | } |
| 3436 | |
| 3437 | /** Dispatch a batchbuffer to the ring |
| 3438 | */ |
| 3439 | static int |
| 3440 | i915_dispatch_gem_execbuffer(struct drm_device *dev, |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3441 | struct drm_i915_gem_execbuffer2 *exec, |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3442 | struct drm_clip_rect *cliprects, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3443 | uint64_t exec_offset) |
| 3444 | { |
| 3445 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3446 | int nbox = exec->num_cliprects; |
| 3447 | int i = 0, count; |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3448 | uint32_t exec_start, exec_len; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3449 | RING_LOCALS; |
| 3450 | |
| 3451 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3452 | exec_len = (uint32_t) exec->batch_len; |
| 3453 | |
Chris Wilson | 8f0dc5b | 2009-09-24 00:43:17 +0100 | [diff] [blame] | 3454 | trace_i915_gem_request_submit(dev, dev_priv->mm.next_gem_seqno + 1); |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3455 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3456 | count = nbox ? nbox : 1; |
| 3457 | |
| 3458 | for (i = 0; i < count; i++) { |
| 3459 | if (i < nbox) { |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3460 | int ret = i915_emit_box(dev, cliprects, i, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3461 | exec->DR1, exec->DR4); |
| 3462 | if (ret) |
| 3463 | return ret; |
| 3464 | } |
| 3465 | |
| 3466 | if (IS_I830(dev) || IS_845G(dev)) { |
| 3467 | BEGIN_LP_RING(4); |
| 3468 | OUT_RING(MI_BATCH_BUFFER); |
| 3469 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); |
| 3470 | OUT_RING(exec_start + exec_len - 4); |
| 3471 | OUT_RING(0); |
| 3472 | ADVANCE_LP_RING(); |
| 3473 | } else { |
| 3474 | BEGIN_LP_RING(2); |
| 3475 | if (IS_I965G(dev)) { |
| 3476 | OUT_RING(MI_BATCH_BUFFER_START | |
| 3477 | (2 << 6) | |
| 3478 | MI_BATCH_NON_SECURE_I965); |
| 3479 | OUT_RING(exec_start); |
| 3480 | } else { |
| 3481 | OUT_RING(MI_BATCH_BUFFER_START | |
| 3482 | (2 << 6)); |
| 3483 | OUT_RING(exec_start | MI_BATCH_NON_SECURE); |
| 3484 | } |
| 3485 | ADVANCE_LP_RING(); |
| 3486 | } |
| 3487 | } |
| 3488 | |
| 3489 | /* XXX breadcrumb */ |
| 3490 | return 0; |
| 3491 | } |
| 3492 | |
| 3493 | /* Throttle our rendering by waiting until the ring has completed our requests |
| 3494 | * emitted over 20 msec ago. |
| 3495 | * |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3496 | * Note that if we were to use the current jiffies each time around the loop, |
| 3497 | * we wouldn't escape the function with any frames outstanding if the time to |
| 3498 | * render a frame was over 20ms. |
| 3499 | * |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3500 | * This should get us reasonable parallelism between CPU and GPU but also |
| 3501 | * relatively low latency when blocking on a particular request to finish. |
| 3502 | */ |
| 3503 | static int |
| 3504 | i915_gem_ring_throttle(struct drm_device *dev, struct drm_file *file_priv) |
| 3505 | { |
| 3506 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 3507 | int ret = 0; |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3508 | unsigned long recent_enough = jiffies - msecs_to_jiffies(20); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3509 | |
| 3510 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3511 | while (!list_empty(&i915_file_priv->mm.request_list)) { |
| 3512 | struct drm_i915_gem_request *request; |
| 3513 | |
| 3514 | request = list_first_entry(&i915_file_priv->mm.request_list, |
| 3515 | struct drm_i915_gem_request, |
| 3516 | client_list); |
| 3517 | |
| 3518 | if (time_after_eq(request->emitted_jiffies, recent_enough)) |
| 3519 | break; |
| 3520 | |
| 3521 | ret = i915_wait_request(dev, request->seqno); |
| 3522 | if (ret != 0) |
| 3523 | break; |
| 3524 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3525 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3526 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3527 | return ret; |
| 3528 | } |
| 3529 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3530 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3531 | i915_gem_get_relocs_from_user(struct drm_i915_gem_exec_object2 *exec_list, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3532 | uint32_t buffer_count, |
| 3533 | struct drm_i915_gem_relocation_entry **relocs) |
| 3534 | { |
| 3535 | uint32_t reloc_count = 0, reloc_index = 0, i; |
| 3536 | int ret; |
| 3537 | |
| 3538 | *relocs = NULL; |
| 3539 | for (i = 0; i < buffer_count; i++) { |
| 3540 | if (reloc_count + exec_list[i].relocation_count < reloc_count) |
| 3541 | return -EINVAL; |
| 3542 | reloc_count += exec_list[i].relocation_count; |
| 3543 | } |
| 3544 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3545 | *relocs = drm_calloc_large(reloc_count, sizeof(**relocs)); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3546 | if (*relocs == NULL) { |
| 3547 | DRM_ERROR("failed to alloc relocs, count %d\n", reloc_count); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3548 | return -ENOMEM; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3549 | } |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3550 | |
| 3551 | for (i = 0; i < buffer_count; i++) { |
| 3552 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
| 3553 | |
| 3554 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3555 | |
| 3556 | ret = copy_from_user(&(*relocs)[reloc_index], |
| 3557 | user_relocs, |
| 3558 | exec_list[i].relocation_count * |
| 3559 | sizeof(**relocs)); |
| 3560 | if (ret != 0) { |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3561 | drm_free_large(*relocs); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3562 | *relocs = NULL; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3563 | return -EFAULT; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3564 | } |
| 3565 | |
| 3566 | reloc_index += exec_list[i].relocation_count; |
| 3567 | } |
| 3568 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3569 | return 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3570 | } |
| 3571 | |
| 3572 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3573 | i915_gem_put_relocs_to_user(struct drm_i915_gem_exec_object2 *exec_list, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3574 | uint32_t buffer_count, |
| 3575 | struct drm_i915_gem_relocation_entry *relocs) |
| 3576 | { |
| 3577 | uint32_t reloc_count = 0, i; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3578 | int ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3579 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3580 | if (relocs == NULL) |
| 3581 | return 0; |
| 3582 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3583 | for (i = 0; i < buffer_count; i++) { |
| 3584 | struct drm_i915_gem_relocation_entry __user *user_relocs; |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3585 | int unwritten; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3586 | |
| 3587 | user_relocs = (void __user *)(uintptr_t)exec_list[i].relocs_ptr; |
| 3588 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3589 | unwritten = copy_to_user(user_relocs, |
| 3590 | &relocs[reloc_count], |
| 3591 | exec_list[i].relocation_count * |
| 3592 | sizeof(*relocs)); |
| 3593 | |
| 3594 | if (unwritten) { |
| 3595 | ret = -EFAULT; |
| 3596 | goto err; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3597 | } |
| 3598 | |
| 3599 | reloc_count += exec_list[i].relocation_count; |
| 3600 | } |
| 3601 | |
Florian Mickler | 2bc43b5 | 2009-04-06 22:55:41 +0200 | [diff] [blame] | 3602 | err: |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3603 | drm_free_large(relocs); |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3604 | |
| 3605 | return ret; |
| 3606 | } |
| 3607 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3608 | static int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3609 | i915_gem_check_execbuffer (struct drm_i915_gem_execbuffer2 *exec, |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3610 | uint64_t exec_offset) |
| 3611 | { |
| 3612 | uint32_t exec_start, exec_len; |
| 3613 | |
| 3614 | exec_start = (uint32_t) exec_offset + exec->batch_start_offset; |
| 3615 | exec_len = (uint32_t) exec->batch_len; |
| 3616 | |
| 3617 | if ((exec_start | exec_len) & 0x7) |
| 3618 | return -EINVAL; |
| 3619 | |
| 3620 | if (!exec_start) |
| 3621 | return -EINVAL; |
| 3622 | |
| 3623 | return 0; |
| 3624 | } |
| 3625 | |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3626 | static int |
| 3627 | i915_gem_wait_for_pending_flip(struct drm_device *dev, |
| 3628 | struct drm_gem_object **object_list, |
| 3629 | int count) |
| 3630 | { |
| 3631 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 3632 | struct drm_i915_gem_object *obj_priv; |
| 3633 | DEFINE_WAIT(wait); |
| 3634 | int i, ret = 0; |
| 3635 | |
| 3636 | for (;;) { |
| 3637 | prepare_to_wait(&dev_priv->pending_flip_queue, |
| 3638 | &wait, TASK_INTERRUPTIBLE); |
| 3639 | for (i = 0; i < count; i++) { |
| 3640 | obj_priv = object_list[i]->driver_private; |
| 3641 | if (atomic_read(&obj_priv->pending_flip) > 0) |
| 3642 | break; |
| 3643 | } |
| 3644 | if (i == count) |
| 3645 | break; |
| 3646 | |
| 3647 | if (!signal_pending(current)) { |
| 3648 | mutex_unlock(&dev->struct_mutex); |
| 3649 | schedule(); |
| 3650 | mutex_lock(&dev->struct_mutex); |
| 3651 | continue; |
| 3652 | } |
| 3653 | ret = -ERESTARTSYS; |
| 3654 | break; |
| 3655 | } |
| 3656 | finish_wait(&dev_priv->pending_flip_queue, &wait); |
| 3657 | |
| 3658 | return ret; |
| 3659 | } |
| 3660 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3661 | int |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3662 | i915_gem_do_execbuffer(struct drm_device *dev, void *data, |
| 3663 | struct drm_file *file_priv, |
| 3664 | struct drm_i915_gem_execbuffer2 *args, |
| 3665 | struct drm_i915_gem_exec_object2 *exec_list) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3666 | { |
| 3667 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3668 | struct drm_gem_object **object_list = NULL; |
| 3669 | struct drm_gem_object *batch_obj; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3670 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3671 | struct drm_clip_rect *cliprects = NULL; |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3672 | struct drm_i915_gem_relocation_entry *relocs = NULL; |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3673 | int ret = 0, ret2, i, pinned = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3674 | uint64_t exec_offset; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3675 | uint32_t seqno, flush_domains, reloc_index; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3676 | int pin_tries, flips; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3677 | |
| 3678 | #if WATCH_EXEC |
| 3679 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3680 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3681 | #endif |
| 3682 | |
Eric Anholt | 4f481ed | 2008-09-10 14:22:49 -0700 | [diff] [blame] | 3683 | if (args->buffer_count < 1) { |
| 3684 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 3685 | return -EINVAL; |
| 3686 | } |
Eric Anholt | c8e0f93 | 2009-11-22 03:49:37 +0100 | [diff] [blame] | 3687 | object_list = drm_malloc_ab(sizeof(*object_list), args->buffer_count); |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3688 | if (object_list == NULL) { |
| 3689 | DRM_ERROR("Failed to allocate object list for %d buffers\n", |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3690 | args->buffer_count); |
| 3691 | ret = -ENOMEM; |
| 3692 | goto pre_mutex_err; |
| 3693 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3694 | |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3695 | if (args->num_cliprects != 0) { |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3696 | cliprects = kcalloc(args->num_cliprects, sizeof(*cliprects), |
| 3697 | GFP_KERNEL); |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3698 | if (cliprects == NULL) { |
| 3699 | ret = -ENOMEM; |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3700 | goto pre_mutex_err; |
Owain Ainsworth | a40e8d3 | 2010-02-09 14:25:55 +0000 | [diff] [blame] | 3701 | } |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3702 | |
| 3703 | ret = copy_from_user(cliprects, |
| 3704 | (struct drm_clip_rect __user *) |
| 3705 | (uintptr_t) args->cliprects_ptr, |
| 3706 | sizeof(*cliprects) * args->num_cliprects); |
| 3707 | if (ret != 0) { |
| 3708 | DRM_ERROR("copy %d cliprects failed: %d\n", |
| 3709 | args->num_cliprects, ret); |
| 3710 | goto pre_mutex_err; |
| 3711 | } |
| 3712 | } |
| 3713 | |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3714 | ret = i915_gem_get_relocs_from_user(exec_list, args->buffer_count, |
| 3715 | &relocs); |
| 3716 | if (ret != 0) |
| 3717 | goto pre_mutex_err; |
| 3718 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3719 | mutex_lock(&dev->struct_mutex); |
| 3720 | |
| 3721 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3722 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 3723 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3724 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3725 | ret = -EIO; |
| 3726 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3727 | } |
| 3728 | |
| 3729 | if (dev_priv->mm.suspended) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3730 | mutex_unlock(&dev->struct_mutex); |
Chris Wilson | a198bc8 | 2009-02-06 16:55:20 +0000 | [diff] [blame] | 3731 | ret = -EBUSY; |
| 3732 | goto pre_mutex_err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3733 | } |
| 3734 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3735 | /* Look up object handles */ |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3736 | flips = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3737 | for (i = 0; i < args->buffer_count; i++) { |
| 3738 | object_list[i] = drm_gem_object_lookup(dev, file_priv, |
| 3739 | exec_list[i].handle); |
| 3740 | if (object_list[i] == NULL) { |
| 3741 | DRM_ERROR("Invalid object handle %d at index %d\n", |
| 3742 | exec_list[i].handle, i); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3743 | /* prevent error path from reading uninitialized data */ |
| 3744 | args->buffer_count = i + 1; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3745 | ret = -EBADF; |
| 3746 | goto err; |
| 3747 | } |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3748 | |
| 3749 | obj_priv = object_list[i]->driver_private; |
| 3750 | if (obj_priv->in_execbuffer) { |
| 3751 | DRM_ERROR("Object %p appears more than once in object list\n", |
| 3752 | object_list[i]); |
Chris Wilson | 0ce907f | 2010-01-23 20:26:35 +0000 | [diff] [blame] | 3753 | /* prevent error path from reading uninitialized data */ |
| 3754 | args->buffer_count = i + 1; |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3755 | ret = -EBADF; |
| 3756 | goto err; |
| 3757 | } |
| 3758 | obj_priv->in_execbuffer = true; |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 3759 | flips += atomic_read(&obj_priv->pending_flip); |
| 3760 | } |
| 3761 | |
| 3762 | if (flips > 0) { |
| 3763 | ret = i915_gem_wait_for_pending_flip(dev, object_list, |
| 3764 | args->buffer_count); |
| 3765 | if (ret) |
| 3766 | goto err; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3767 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3768 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3769 | /* Pin and relocate */ |
| 3770 | for (pin_tries = 0; ; pin_tries++) { |
| 3771 | ret = 0; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3772 | reloc_index = 0; |
| 3773 | |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3774 | for (i = 0; i < args->buffer_count; i++) { |
| 3775 | object_list[i]->pending_read_domains = 0; |
| 3776 | object_list[i]->pending_write_domain = 0; |
| 3777 | ret = i915_gem_object_pin_and_relocate(object_list[i], |
| 3778 | file_priv, |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3779 | &exec_list[i], |
| 3780 | &relocs[reloc_index]); |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3781 | if (ret) |
| 3782 | break; |
| 3783 | pinned = i + 1; |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3784 | reloc_index += exec_list[i].relocation_count; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3785 | } |
| 3786 | /* success */ |
| 3787 | if (ret == 0) |
| 3788 | break; |
| 3789 | |
| 3790 | /* error other than GTT full, or we've already tried again */ |
Chris Wilson | 2939e1f | 2009-06-06 09:46:03 +0100 | [diff] [blame] | 3791 | if (ret != -ENOSPC || pin_tries >= 1) { |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3792 | if (ret != -ERESTARTSYS) { |
| 3793 | unsigned long long total_size = 0; |
| 3794 | for (i = 0; i < args->buffer_count; i++) |
| 3795 | total_size += object_list[i]->size; |
| 3796 | DRM_ERROR("Failed to pin buffer %d of %d, total %llu bytes: %d\n", |
| 3797 | pinned+1, args->buffer_count, |
| 3798 | total_size, ret); |
| 3799 | DRM_ERROR("%d objects [%d pinned], " |
| 3800 | "%d object bytes [%d pinned], " |
| 3801 | "%d/%d gtt bytes\n", |
| 3802 | atomic_read(&dev->object_count), |
| 3803 | atomic_read(&dev->pin_count), |
| 3804 | atomic_read(&dev->object_memory), |
| 3805 | atomic_read(&dev->pin_memory), |
| 3806 | atomic_read(&dev->gtt_memory), |
| 3807 | dev->gtt_total); |
| 3808 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3809 | goto err; |
| 3810 | } |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3811 | |
| 3812 | /* unpin all of our buffers */ |
| 3813 | for (i = 0; i < pinned; i++) |
| 3814 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | b117763 | 2008-12-10 10:09:41 -0800 | [diff] [blame] | 3815 | pinned = 0; |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3816 | |
| 3817 | /* evict everyone we can from the aperture */ |
| 3818 | ret = i915_gem_evict_everything(dev); |
Chris Wilson | 07f73f6 | 2009-09-14 16:50:30 +0100 | [diff] [blame] | 3819 | if (ret && ret != -ENOSPC) |
Keith Packard | ac94a96 | 2008-11-20 23:30:27 -0800 | [diff] [blame] | 3820 | goto err; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3821 | } |
| 3822 | |
| 3823 | /* Set the pending read domains for the batch buffer to COMMAND */ |
| 3824 | batch_obj = object_list[args->buffer_count-1]; |
Chris Wilson | 5f26a2c | 2009-06-06 09:45:58 +0100 | [diff] [blame] | 3825 | if (batch_obj->pending_write_domain) { |
| 3826 | DRM_ERROR("Attempting to use self-modifying batch buffer\n"); |
| 3827 | ret = -EINVAL; |
| 3828 | goto err; |
| 3829 | } |
| 3830 | batch_obj->pending_read_domains |= I915_GEM_DOMAIN_COMMAND; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3831 | |
Chris Wilson | 83d6079 | 2009-06-06 09:45:57 +0100 | [diff] [blame] | 3832 | /* Sanity check the batch buffer, prior to moving objects */ |
| 3833 | exec_offset = exec_list[args->buffer_count - 1].offset; |
| 3834 | ret = i915_gem_check_execbuffer (args, exec_offset); |
| 3835 | if (ret != 0) { |
| 3836 | DRM_ERROR("execbuf with invalid offset/length\n"); |
| 3837 | goto err; |
| 3838 | } |
| 3839 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3840 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3841 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3842 | /* Zero the global flush/invalidate flags. These |
| 3843 | * will be modified as new domains are computed |
| 3844 | * for each object |
| 3845 | */ |
| 3846 | dev->invalidate_domains = 0; |
| 3847 | dev->flush_domains = 0; |
| 3848 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3849 | for (i = 0; i < args->buffer_count; i++) { |
| 3850 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3851 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3852 | /* Compute new gpu domains and update invalidate/flush */ |
Eric Anholt | 8b0e378 | 2009-02-19 14:40:50 -0800 | [diff] [blame] | 3853 | i915_gem_object_set_to_gpu_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3854 | } |
| 3855 | |
| 3856 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3857 | |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3858 | if (dev->invalidate_domains | dev->flush_domains) { |
| 3859 | #if WATCH_EXEC |
| 3860 | DRM_INFO("%s: invalidate_domains %08x flush_domains %08x\n", |
| 3861 | __func__, |
| 3862 | dev->invalidate_domains, |
| 3863 | dev->flush_domains); |
| 3864 | #endif |
| 3865 | i915_gem_flush(dev, |
| 3866 | dev->invalidate_domains, |
| 3867 | dev->flush_domains); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 3868 | if (dev->flush_domains & I915_GEM_GPU_DOMAINS) |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3869 | (void)i915_add_request(dev, file_priv, |
| 3870 | dev->flush_domains); |
Keith Packard | 646f0f6 | 2008-11-20 23:23:03 -0800 | [diff] [blame] | 3871 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3872 | |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3873 | for (i = 0; i < args->buffer_count; i++) { |
| 3874 | struct drm_gem_object *obj = object_list[i]; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 3875 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3876 | uint32_t old_write_domain = obj->write_domain; |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3877 | |
| 3878 | obj->write_domain = obj->pending_write_domain; |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 3879 | if (obj->write_domain) |
| 3880 | list_move_tail(&obj_priv->gpu_write_list, |
| 3881 | &dev_priv->mm.gpu_write_list); |
| 3882 | else |
| 3883 | list_del_init(&obj_priv->gpu_write_list); |
| 3884 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 3885 | trace_i915_gem_object_change_domain(obj, |
| 3886 | obj->read_domains, |
| 3887 | old_write_domain); |
Eric Anholt | efbeed9 | 2009-02-19 14:54:51 -0800 | [diff] [blame] | 3888 | } |
| 3889 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3890 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3891 | |
| 3892 | #if WATCH_COHERENCY |
| 3893 | for (i = 0; i < args->buffer_count; i++) { |
| 3894 | i915_gem_object_check_coherency(object_list[i], |
| 3895 | exec_list[i].handle); |
| 3896 | } |
| 3897 | #endif |
| 3898 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3899 | #if WATCH_EXEC |
Ben Gamari | 6911a9b | 2009-04-02 11:24:54 -0700 | [diff] [blame] | 3900 | i915_gem_dump_object(batch_obj, |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3901 | args->batch_len, |
| 3902 | __func__, |
| 3903 | ~0); |
| 3904 | #endif |
| 3905 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3906 | /* Exec the batchbuffer */ |
Eric Anholt | 201361a | 2009-03-11 12:30:04 -0700 | [diff] [blame] | 3907 | ret = i915_dispatch_gem_execbuffer(dev, args, cliprects, exec_offset); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3908 | if (ret) { |
| 3909 | DRM_ERROR("dispatch failed %d\n", ret); |
| 3910 | goto err; |
| 3911 | } |
| 3912 | |
| 3913 | /* |
| 3914 | * Ensure that the commands in the batch buffer are |
| 3915 | * finished before the interrupt fires |
| 3916 | */ |
| 3917 | flush_domains = i915_retire_commands(dev); |
| 3918 | |
| 3919 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3920 | |
| 3921 | /* |
| 3922 | * Get a seqno representing the execution of the current buffer, |
| 3923 | * which we can wait on. We would like to mitigate these interrupts, |
| 3924 | * likely by only creating seqnos occasionally (so that we have |
| 3925 | * *some* interrupts representing completion of buffers that we can |
| 3926 | * wait on when trying to clear up gtt space). |
| 3927 | */ |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 3928 | seqno = i915_add_request(dev, file_priv, flush_domains); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3929 | BUG_ON(seqno == 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3930 | for (i = 0; i < args->buffer_count; i++) { |
| 3931 | struct drm_gem_object *obj = object_list[i]; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3932 | |
Eric Anholt | ce44b0e | 2008-11-06 16:00:31 -0800 | [diff] [blame] | 3933 | i915_gem_object_move_to_active(obj, seqno); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3934 | #if WATCH_LRU |
| 3935 | DRM_INFO("%s: move to exec list %p\n", __func__, obj); |
| 3936 | #endif |
| 3937 | } |
| 3938 | #if WATCH_LRU |
| 3939 | i915_dump_lru(dev, __func__); |
| 3940 | #endif |
| 3941 | |
| 3942 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 3943 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3944 | err: |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3945 | for (i = 0; i < pinned; i++) |
| 3946 | i915_gem_object_unpin(object_list[i]); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3947 | |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3948 | for (i = 0; i < args->buffer_count; i++) { |
| 3949 | if (object_list[i]) { |
| 3950 | obj_priv = object_list[i]->driver_private; |
| 3951 | obj_priv->in_execbuffer = false; |
| 3952 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3953 | drm_gem_object_unreference(object_list[i]); |
Kristian Høgsberg | b70d11d | 2009-03-03 14:45:57 -0500 | [diff] [blame] | 3954 | } |
Julia Lawall | aad87df | 2008-12-21 16:28:47 +0100 | [diff] [blame] | 3955 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3956 | mutex_unlock(&dev->struct_mutex); |
| 3957 | |
Chris Wilson | 93533c2 | 2010-01-31 10:40:48 +0000 | [diff] [blame] | 3958 | pre_mutex_err: |
Eric Anholt | 40a5f0d | 2009-03-12 11:23:52 -0700 | [diff] [blame] | 3959 | /* Copy the updated relocations out regardless of current error |
| 3960 | * state. Failure to update the relocs would mean that the next |
| 3961 | * time userland calls execbuf, it would do so with presumed offset |
| 3962 | * state that didn't match the actual object state. |
| 3963 | */ |
| 3964 | ret2 = i915_gem_put_relocs_to_user(exec_list, args->buffer_count, |
| 3965 | relocs); |
| 3966 | if (ret2 != 0) { |
| 3967 | DRM_ERROR("Failed to copy relocations back out: %d\n", ret2); |
| 3968 | |
| 3969 | if (ret == 0) |
| 3970 | ret = ret2; |
| 3971 | } |
| 3972 | |
Jesse Barnes | 8e7d2b2 | 2009-05-08 16:13:25 -0700 | [diff] [blame] | 3973 | drm_free_large(object_list); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 3974 | kfree(cliprects); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 3975 | |
| 3976 | return ret; |
| 3977 | } |
| 3978 | |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 3979 | /* |
| 3980 | * Legacy execbuffer just creates an exec2 list from the original exec object |
| 3981 | * list array and passes it to the real function. |
| 3982 | */ |
| 3983 | int |
| 3984 | i915_gem_execbuffer(struct drm_device *dev, void *data, |
| 3985 | struct drm_file *file_priv) |
| 3986 | { |
| 3987 | struct drm_i915_gem_execbuffer *args = data; |
| 3988 | struct drm_i915_gem_execbuffer2 exec2; |
| 3989 | struct drm_i915_gem_exec_object *exec_list = NULL; |
| 3990 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 3991 | int ret, i; |
| 3992 | |
| 3993 | #if WATCH_EXEC |
| 3994 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 3995 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 3996 | #endif |
| 3997 | |
| 3998 | if (args->buffer_count < 1) { |
| 3999 | DRM_ERROR("execbuf with %d buffers\n", args->buffer_count); |
| 4000 | return -EINVAL; |
| 4001 | } |
| 4002 | |
| 4003 | /* Copy in the exec list from userland */ |
| 4004 | exec_list = drm_malloc_ab(sizeof(*exec_list), args->buffer_count); |
| 4005 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4006 | if (exec_list == NULL || exec2_list == NULL) { |
| 4007 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4008 | args->buffer_count); |
| 4009 | drm_free_large(exec_list); |
| 4010 | drm_free_large(exec2_list); |
| 4011 | return -ENOMEM; |
| 4012 | } |
| 4013 | ret = copy_from_user(exec_list, |
| 4014 | (struct drm_i915_relocation_entry __user *) |
| 4015 | (uintptr_t) args->buffers_ptr, |
| 4016 | sizeof(*exec_list) * args->buffer_count); |
| 4017 | if (ret != 0) { |
| 4018 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4019 | args->buffer_count, ret); |
| 4020 | drm_free_large(exec_list); |
| 4021 | drm_free_large(exec2_list); |
| 4022 | return -EFAULT; |
| 4023 | } |
| 4024 | |
| 4025 | for (i = 0; i < args->buffer_count; i++) { |
| 4026 | exec2_list[i].handle = exec_list[i].handle; |
| 4027 | exec2_list[i].relocation_count = exec_list[i].relocation_count; |
| 4028 | exec2_list[i].relocs_ptr = exec_list[i].relocs_ptr; |
| 4029 | exec2_list[i].alignment = exec_list[i].alignment; |
| 4030 | exec2_list[i].offset = exec_list[i].offset; |
| 4031 | if (!IS_I965G(dev)) |
| 4032 | exec2_list[i].flags = EXEC_OBJECT_NEEDS_FENCE; |
| 4033 | else |
| 4034 | exec2_list[i].flags = 0; |
| 4035 | } |
| 4036 | |
| 4037 | exec2.buffers_ptr = args->buffers_ptr; |
| 4038 | exec2.buffer_count = args->buffer_count; |
| 4039 | exec2.batch_start_offset = args->batch_start_offset; |
| 4040 | exec2.batch_len = args->batch_len; |
| 4041 | exec2.DR1 = args->DR1; |
| 4042 | exec2.DR4 = args->DR4; |
| 4043 | exec2.num_cliprects = args->num_cliprects; |
| 4044 | exec2.cliprects_ptr = args->cliprects_ptr; |
| 4045 | exec2.flags = 0; |
| 4046 | |
| 4047 | ret = i915_gem_do_execbuffer(dev, data, file_priv, &exec2, exec2_list); |
| 4048 | if (!ret) { |
| 4049 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4050 | for (i = 0; i < args->buffer_count; i++) |
| 4051 | exec_list[i].offset = exec2_list[i].offset; |
| 4052 | /* ... and back out to userspace */ |
| 4053 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4054 | (uintptr_t) args->buffers_ptr, |
| 4055 | exec_list, |
| 4056 | sizeof(*exec_list) * args->buffer_count); |
| 4057 | if (ret) { |
| 4058 | ret = -EFAULT; |
| 4059 | DRM_ERROR("failed to copy %d exec entries " |
| 4060 | "back to user (%d)\n", |
| 4061 | args->buffer_count, ret); |
| 4062 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4063 | } |
| 4064 | |
| 4065 | drm_free_large(exec_list); |
| 4066 | drm_free_large(exec2_list); |
| 4067 | return ret; |
| 4068 | } |
| 4069 | |
| 4070 | int |
| 4071 | i915_gem_execbuffer2(struct drm_device *dev, void *data, |
| 4072 | struct drm_file *file_priv) |
| 4073 | { |
| 4074 | struct drm_i915_gem_execbuffer2 *args = data; |
| 4075 | struct drm_i915_gem_exec_object2 *exec2_list = NULL; |
| 4076 | int ret; |
| 4077 | |
| 4078 | #if WATCH_EXEC |
| 4079 | DRM_INFO("buffers_ptr %d buffer_count %d len %08x\n", |
| 4080 | (int) args->buffers_ptr, args->buffer_count, args->batch_len); |
| 4081 | #endif |
| 4082 | |
| 4083 | if (args->buffer_count < 1) { |
| 4084 | DRM_ERROR("execbuf2 with %d buffers\n", args->buffer_count); |
| 4085 | return -EINVAL; |
| 4086 | } |
| 4087 | |
| 4088 | exec2_list = drm_malloc_ab(sizeof(*exec2_list), args->buffer_count); |
| 4089 | if (exec2_list == NULL) { |
| 4090 | DRM_ERROR("Failed to allocate exec list for %d buffers\n", |
| 4091 | args->buffer_count); |
| 4092 | return -ENOMEM; |
| 4093 | } |
| 4094 | ret = copy_from_user(exec2_list, |
| 4095 | (struct drm_i915_relocation_entry __user *) |
| 4096 | (uintptr_t) args->buffers_ptr, |
| 4097 | sizeof(*exec2_list) * args->buffer_count); |
| 4098 | if (ret != 0) { |
| 4099 | DRM_ERROR("copy %d exec entries failed %d\n", |
| 4100 | args->buffer_count, ret); |
| 4101 | drm_free_large(exec2_list); |
| 4102 | return -EFAULT; |
| 4103 | } |
| 4104 | |
| 4105 | ret = i915_gem_do_execbuffer(dev, data, file_priv, args, exec2_list); |
| 4106 | if (!ret) { |
| 4107 | /* Copy the new buffer offsets back to the user's exec list. */ |
| 4108 | ret = copy_to_user((struct drm_i915_relocation_entry __user *) |
| 4109 | (uintptr_t) args->buffers_ptr, |
| 4110 | exec2_list, |
| 4111 | sizeof(*exec2_list) * args->buffer_count); |
| 4112 | if (ret) { |
| 4113 | ret = -EFAULT; |
| 4114 | DRM_ERROR("failed to copy %d exec entries " |
| 4115 | "back to user (%d)\n", |
| 4116 | args->buffer_count, ret); |
| 4117 | } |
| 4118 | } |
| 4119 | |
| 4120 | drm_free_large(exec2_list); |
| 4121 | return ret; |
| 4122 | } |
| 4123 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4124 | int |
| 4125 | i915_gem_object_pin(struct drm_gem_object *obj, uint32_t alignment) |
| 4126 | { |
| 4127 | struct drm_device *dev = obj->dev; |
| 4128 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 4129 | int ret; |
| 4130 | |
| 4131 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 4132 | if (obj_priv->gtt_space == NULL) { |
| 4133 | ret = i915_gem_object_bind_to_gtt(obj, alignment); |
Chris Wilson | 9731129 | 2009-09-21 00:22:34 +0100 | [diff] [blame] | 4134 | if (ret) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4135 | return ret; |
Chris Wilson | 22c344e | 2009-02-11 14:26:45 +0000 | [diff] [blame] | 4136 | } |
Jesse Barnes | 76446ca | 2009-12-17 22:05:42 -0500 | [diff] [blame] | 4137 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4138 | obj_priv->pin_count++; |
| 4139 | |
| 4140 | /* If the object is not active and not pending a flush, |
| 4141 | * remove it from the inactive list |
| 4142 | */ |
| 4143 | if (obj_priv->pin_count == 1) { |
| 4144 | atomic_inc(&dev->pin_count); |
| 4145 | atomic_add(obj->size, &dev->pin_memory); |
| 4146 | if (!obj_priv->active && |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 4147 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0 && |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4148 | !list_empty(&obj_priv->list)) |
| 4149 | list_del_init(&obj_priv->list); |
| 4150 | } |
| 4151 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 4152 | |
| 4153 | return 0; |
| 4154 | } |
| 4155 | |
| 4156 | void |
| 4157 | i915_gem_object_unpin(struct drm_gem_object *obj) |
| 4158 | { |
| 4159 | struct drm_device *dev = obj->dev; |
| 4160 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4161 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 4162 | |
| 4163 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 4164 | obj_priv->pin_count--; |
| 4165 | BUG_ON(obj_priv->pin_count < 0); |
| 4166 | BUG_ON(obj_priv->gtt_space == NULL); |
| 4167 | |
| 4168 | /* If the object is no longer pinned, and is |
| 4169 | * neither active nor being flushed, then stick it on |
| 4170 | * the inactive list |
| 4171 | */ |
| 4172 | if (obj_priv->pin_count == 0) { |
| 4173 | if (!obj_priv->active && |
Chris Wilson | 21d509e | 2009-06-06 09:46:02 +0100 | [diff] [blame] | 4174 | (obj->write_domain & I915_GEM_GPU_DOMAINS) == 0) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4175 | list_move_tail(&obj_priv->list, |
| 4176 | &dev_priv->mm.inactive_list); |
| 4177 | atomic_dec(&dev->pin_count); |
| 4178 | atomic_sub(obj->size, &dev->pin_memory); |
| 4179 | } |
| 4180 | i915_verify_inactive(dev, __FILE__, __LINE__); |
| 4181 | } |
| 4182 | |
| 4183 | int |
| 4184 | i915_gem_pin_ioctl(struct drm_device *dev, void *data, |
| 4185 | struct drm_file *file_priv) |
| 4186 | { |
| 4187 | struct drm_i915_gem_pin *args = data; |
| 4188 | struct drm_gem_object *obj; |
| 4189 | struct drm_i915_gem_object *obj_priv; |
| 4190 | int ret; |
| 4191 | |
| 4192 | mutex_lock(&dev->struct_mutex); |
| 4193 | |
| 4194 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4195 | if (obj == NULL) { |
| 4196 | DRM_ERROR("Bad handle in i915_gem_pin_ioctl(): %d\n", |
| 4197 | args->handle); |
| 4198 | mutex_unlock(&dev->struct_mutex); |
| 4199 | return -EBADF; |
| 4200 | } |
| 4201 | obj_priv = obj->driver_private; |
| 4202 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4203 | if (obj_priv->madv != I915_MADV_WILLNEED) { |
| 4204 | DRM_ERROR("Attempting to pin a purgeable buffer\n"); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4205 | drm_gem_object_unreference(obj); |
| 4206 | mutex_unlock(&dev->struct_mutex); |
| 4207 | return -EINVAL; |
| 4208 | } |
| 4209 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4210 | if (obj_priv->pin_filp != NULL && obj_priv->pin_filp != file_priv) { |
| 4211 | DRM_ERROR("Already pinned in i915_gem_pin_ioctl(): %d\n", |
| 4212 | args->handle); |
Chris Wilson | 96dec61 | 2009-02-08 19:08:04 +0000 | [diff] [blame] | 4213 | drm_gem_object_unreference(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4214 | mutex_unlock(&dev->struct_mutex); |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4215 | return -EINVAL; |
| 4216 | } |
| 4217 | |
| 4218 | obj_priv->user_pin_count++; |
| 4219 | obj_priv->pin_filp = file_priv; |
| 4220 | if (obj_priv->user_pin_count == 1) { |
| 4221 | ret = i915_gem_object_pin(obj, args->alignment); |
| 4222 | if (ret != 0) { |
| 4223 | drm_gem_object_unreference(obj); |
| 4224 | mutex_unlock(&dev->struct_mutex); |
| 4225 | return ret; |
| 4226 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4227 | } |
| 4228 | |
| 4229 | /* XXX - flush the CPU caches for pinned objects |
| 4230 | * as the X server doesn't manage domains yet |
| 4231 | */ |
Eric Anholt | e47c68e | 2008-11-14 13:35:19 -0800 | [diff] [blame] | 4232 | i915_gem_object_flush_cpu_write_domain(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4233 | args->offset = obj_priv->gtt_offset; |
| 4234 | drm_gem_object_unreference(obj); |
| 4235 | mutex_unlock(&dev->struct_mutex); |
| 4236 | |
| 4237 | return 0; |
| 4238 | } |
| 4239 | |
| 4240 | int |
| 4241 | i915_gem_unpin_ioctl(struct drm_device *dev, void *data, |
| 4242 | struct drm_file *file_priv) |
| 4243 | { |
| 4244 | struct drm_i915_gem_pin *args = data; |
| 4245 | struct drm_gem_object *obj; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4246 | struct drm_i915_gem_object *obj_priv; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4247 | |
| 4248 | mutex_lock(&dev->struct_mutex); |
| 4249 | |
| 4250 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4251 | if (obj == NULL) { |
| 4252 | DRM_ERROR("Bad handle in i915_gem_unpin_ioctl(): %d\n", |
| 4253 | args->handle); |
| 4254 | mutex_unlock(&dev->struct_mutex); |
| 4255 | return -EBADF; |
| 4256 | } |
| 4257 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4258 | obj_priv = obj->driver_private; |
| 4259 | if (obj_priv->pin_filp != file_priv) { |
| 4260 | DRM_ERROR("Not pinned by caller in i915_gem_pin_ioctl(): %d\n", |
| 4261 | args->handle); |
| 4262 | drm_gem_object_unreference(obj); |
| 4263 | mutex_unlock(&dev->struct_mutex); |
| 4264 | return -EINVAL; |
| 4265 | } |
| 4266 | obj_priv->user_pin_count--; |
| 4267 | if (obj_priv->user_pin_count == 0) { |
| 4268 | obj_priv->pin_filp = NULL; |
| 4269 | i915_gem_object_unpin(obj); |
| 4270 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4271 | |
| 4272 | drm_gem_object_unreference(obj); |
| 4273 | mutex_unlock(&dev->struct_mutex); |
| 4274 | return 0; |
| 4275 | } |
| 4276 | |
| 4277 | int |
| 4278 | i915_gem_busy_ioctl(struct drm_device *dev, void *data, |
| 4279 | struct drm_file *file_priv) |
| 4280 | { |
| 4281 | struct drm_i915_gem_busy *args = data; |
| 4282 | struct drm_gem_object *obj; |
| 4283 | struct drm_i915_gem_object *obj_priv; |
| 4284 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4285 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4286 | if (obj == NULL) { |
| 4287 | DRM_ERROR("Bad handle in i915_gem_busy_ioctl(): %d\n", |
| 4288 | args->handle); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4289 | return -EBADF; |
| 4290 | } |
| 4291 | |
Chris Wilson | b1ce786 | 2009-06-06 09:46:00 +0100 | [diff] [blame] | 4292 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | f21289b | 2009-02-18 09:44:56 -0800 | [diff] [blame] | 4293 | /* Update the active list for the hardware's current position. |
| 4294 | * Otherwise this only updates on a delayed timer or when irqs are |
| 4295 | * actually unmasked, and our working set ends up being larger than |
| 4296 | * required. |
| 4297 | */ |
| 4298 | i915_gem_retire_requests(dev); |
| 4299 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4300 | obj_priv = obj->driver_private; |
Eric Anholt | c4de0a5 | 2008-12-14 19:05:04 -0800 | [diff] [blame] | 4301 | /* Don't count being on the flushing list against the object being |
| 4302 | * done. Otherwise, a buffer left on the flushing list but not getting |
| 4303 | * flushed (because nobody's flushing that domain) won't ever return |
| 4304 | * unbusy and get reused by libdrm's bo cache. The other expected |
| 4305 | * consumer of this interface, OpenGL's occlusion queries, also specs |
| 4306 | * that the objects get unbusy "eventually" without any interference. |
| 4307 | */ |
| 4308 | args->busy = obj_priv->active && obj_priv->last_rendering_seqno != 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4309 | |
| 4310 | drm_gem_object_unreference(obj); |
| 4311 | mutex_unlock(&dev->struct_mutex); |
| 4312 | return 0; |
| 4313 | } |
| 4314 | |
| 4315 | int |
| 4316 | i915_gem_throttle_ioctl(struct drm_device *dev, void *data, |
| 4317 | struct drm_file *file_priv) |
| 4318 | { |
| 4319 | return i915_gem_ring_throttle(dev, file_priv); |
| 4320 | } |
| 4321 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4322 | int |
| 4323 | i915_gem_madvise_ioctl(struct drm_device *dev, void *data, |
| 4324 | struct drm_file *file_priv) |
| 4325 | { |
| 4326 | struct drm_i915_gem_madvise *args = data; |
| 4327 | struct drm_gem_object *obj; |
| 4328 | struct drm_i915_gem_object *obj_priv; |
| 4329 | |
| 4330 | switch (args->madv) { |
| 4331 | case I915_MADV_DONTNEED: |
| 4332 | case I915_MADV_WILLNEED: |
| 4333 | break; |
| 4334 | default: |
| 4335 | return -EINVAL; |
| 4336 | } |
| 4337 | |
| 4338 | obj = drm_gem_object_lookup(dev, file_priv, args->handle); |
| 4339 | if (obj == NULL) { |
| 4340 | DRM_ERROR("Bad handle in i915_gem_madvise_ioctl(): %d\n", |
| 4341 | args->handle); |
| 4342 | return -EBADF; |
| 4343 | } |
| 4344 | |
| 4345 | mutex_lock(&dev->struct_mutex); |
| 4346 | obj_priv = obj->driver_private; |
| 4347 | |
| 4348 | if (obj_priv->pin_count) { |
| 4349 | drm_gem_object_unreference(obj); |
| 4350 | mutex_unlock(&dev->struct_mutex); |
| 4351 | |
| 4352 | DRM_ERROR("Attempted i915_gem_madvise_ioctl() on a pinned object\n"); |
| 4353 | return -EINVAL; |
| 4354 | } |
| 4355 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4356 | if (obj_priv->madv != __I915_MADV_PURGED) |
| 4357 | obj_priv->madv = args->madv; |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4358 | |
Chris Wilson | 2d7ef39 | 2009-09-20 23:13:10 +0100 | [diff] [blame] | 4359 | /* if the object is no longer bound, discard its backing storage */ |
| 4360 | if (i915_gem_object_is_purgeable(obj_priv) && |
| 4361 | obj_priv->gtt_space == NULL) |
| 4362 | i915_gem_object_truncate(obj); |
| 4363 | |
Chris Wilson | bb6baf7 | 2009-09-22 14:24:13 +0100 | [diff] [blame] | 4364 | args->retained = obj_priv->madv != __I915_MADV_PURGED; |
| 4365 | |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4366 | drm_gem_object_unreference(obj); |
| 4367 | mutex_unlock(&dev->struct_mutex); |
| 4368 | |
| 4369 | return 0; |
| 4370 | } |
| 4371 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4372 | int i915_gem_init_object(struct drm_gem_object *obj) |
| 4373 | { |
| 4374 | struct drm_i915_gem_object *obj_priv; |
| 4375 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4376 | obj_priv = kzalloc(sizeof(*obj_priv), GFP_KERNEL); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4377 | if (obj_priv == NULL) |
| 4378 | return -ENOMEM; |
| 4379 | |
| 4380 | /* |
| 4381 | * We've just allocated pages from the kernel, |
| 4382 | * so they've just been written by the CPU with |
| 4383 | * zeros. They'll need to be clflushed before we |
| 4384 | * use them with the GPU. |
| 4385 | */ |
| 4386 | obj->write_domain = I915_GEM_DOMAIN_CPU; |
| 4387 | obj->read_domains = I915_GEM_DOMAIN_CPU; |
| 4388 | |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4389 | obj_priv->agp_type = AGP_USER_MEMORY; |
| 4390 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4391 | obj->driver_private = obj_priv; |
| 4392 | obj_priv->obj = obj; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4393 | obj_priv->fence_reg = I915_FENCE_REG_NONE; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4394 | INIT_LIST_HEAD(&obj_priv->list); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 4395 | INIT_LIST_HEAD(&obj_priv->gpu_write_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4396 | INIT_LIST_HEAD(&obj_priv->fence_list); |
Chris Wilson | 3ef94da | 2009-09-14 16:50:29 +0100 | [diff] [blame] | 4397 | obj_priv->madv = I915_MADV_WILLNEED; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4398 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4399 | trace_i915_gem_object_create(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4400 | |
| 4401 | return 0; |
| 4402 | } |
| 4403 | |
| 4404 | void i915_gem_free_object(struct drm_gem_object *obj) |
| 4405 | { |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4406 | struct drm_device *dev = obj->dev; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4407 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 4408 | |
Chris Wilson | 1c5d22f | 2009-08-25 11:15:50 +0100 | [diff] [blame] | 4409 | trace_i915_gem_object_destroy(obj); |
| 4410 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4411 | while (obj_priv->pin_count > 0) |
| 4412 | i915_gem_object_unpin(obj); |
| 4413 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4414 | if (obj_priv->phys_obj) |
| 4415 | i915_gem_detach_phys_object(dev, obj); |
| 4416 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4417 | i915_gem_object_unbind(obj); |
| 4418 | |
Chris Wilson | 7e61615 | 2009-09-10 08:53:04 +0100 | [diff] [blame] | 4419 | if (obj_priv->mmap_offset) |
| 4420 | i915_gem_free_mmap_offset(obj); |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4421 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4422 | kfree(obj_priv->page_cpu_valid); |
Eric Anholt | 280b713 | 2009-03-12 16:56:27 -0700 | [diff] [blame] | 4423 | kfree(obj_priv->bit_17); |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4424 | kfree(obj->driver_private); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4425 | } |
| 4426 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4427 | /** Unbinds all inactive objects. */ |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4428 | static int |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4429 | i915_gem_evict_from_inactive_list(struct drm_device *dev) |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4430 | { |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4431 | drm_i915_private_t *dev_priv = dev->dev_private; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4432 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4433 | while (!list_empty(&dev_priv->mm.inactive_list)) { |
| 4434 | struct drm_gem_object *obj; |
| 4435 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4436 | |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4437 | obj = list_first_entry(&dev_priv->mm.inactive_list, |
| 4438 | struct drm_i915_gem_object, |
| 4439 | list)->obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4440 | |
| 4441 | ret = i915_gem_object_unbind(obj); |
| 4442 | if (ret != 0) { |
Chris Wilson | ab5ee57 | 2009-09-20 19:25:47 +0100 | [diff] [blame] | 4443 | DRM_ERROR("Error unbinding object: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4444 | return ret; |
| 4445 | } |
| 4446 | } |
| 4447 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4448 | return 0; |
| 4449 | } |
| 4450 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4451 | static int |
| 4452 | i915_gpu_idle(struct drm_device *dev) |
| 4453 | { |
| 4454 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4455 | bool lists_empty; |
| 4456 | uint32_t seqno; |
| 4457 | |
| 4458 | spin_lock(&dev_priv->mm.active_list_lock); |
| 4459 | lists_empty = list_empty(&dev_priv->mm.flushing_list) && |
| 4460 | list_empty(&dev_priv->mm.active_list); |
| 4461 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 4462 | |
| 4463 | if (lists_empty) |
| 4464 | return 0; |
| 4465 | |
| 4466 | /* Flush everything onto the inactive list. */ |
| 4467 | i915_gem_flush(dev, I915_GEM_GPU_DOMAINS, I915_GEM_GPU_DOMAINS); |
| 4468 | seqno = i915_add_request(dev, NULL, I915_GEM_GPU_DOMAINS); |
| 4469 | if (seqno == 0) |
| 4470 | return -ENOMEM; |
| 4471 | |
| 4472 | return i915_wait_request(dev, seqno); |
| 4473 | } |
| 4474 | |
Jesse Barnes | 5669fca | 2009-02-17 15:13:31 -0800 | [diff] [blame] | 4475 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4476 | i915_gem_idle(struct drm_device *dev) |
| 4477 | { |
| 4478 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4479 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4480 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4481 | mutex_lock(&dev->struct_mutex); |
| 4482 | |
| 4483 | if (dev_priv->mm.suspended || dev_priv->ring.ring_obj == NULL) { |
| 4484 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4485 | return 0; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4486 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4487 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4488 | ret = i915_gpu_idle(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4489 | if (ret) { |
| 4490 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4491 | return ret; |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4492 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4493 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4494 | /* Under UMS, be paranoid and evict. */ |
| 4495 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) { |
| 4496 | ret = i915_gem_evict_from_inactive_list(dev); |
| 4497 | if (ret) { |
| 4498 | mutex_unlock(&dev->struct_mutex); |
| 4499 | return ret; |
| 4500 | } |
| 4501 | } |
| 4502 | |
| 4503 | /* Hack! Don't let anybody do execbuf while we don't control the chip. |
| 4504 | * We need to replace this with a semaphore, or something. |
| 4505 | * And not confound mm.suspended! |
| 4506 | */ |
| 4507 | dev_priv->mm.suspended = 1; |
| 4508 | del_timer(&dev_priv->hangcheck_timer); |
| 4509 | |
| 4510 | i915_kernel_lost_context(dev); |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4511 | i915_gem_cleanup_ringbuffer(dev); |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4512 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4513 | mutex_unlock(&dev->struct_mutex); |
| 4514 | |
Chris Wilson | 29105cc | 2010-01-07 10:39:13 +0000 | [diff] [blame] | 4515 | /* Cancel the retire work handler, which should be idle now. */ |
| 4516 | cancel_delayed_work_sync(&dev_priv->mm.retire_work); |
| 4517 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4518 | return 0; |
| 4519 | } |
| 4520 | |
| 4521 | static int |
| 4522 | i915_gem_init_hws(struct drm_device *dev) |
| 4523 | { |
| 4524 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4525 | struct drm_gem_object *obj; |
| 4526 | struct drm_i915_gem_object *obj_priv; |
| 4527 | int ret; |
| 4528 | |
| 4529 | /* If we need a physical address for the status page, it's already |
| 4530 | * initialized at driver load time. |
| 4531 | */ |
| 4532 | if (!I915_NEED_GFX_HWS(dev)) |
| 4533 | return 0; |
| 4534 | |
| 4535 | obj = drm_gem_object_alloc(dev, 4096); |
| 4536 | if (obj == NULL) { |
| 4537 | DRM_ERROR("Failed to allocate status page\n"); |
| 4538 | return -ENOMEM; |
| 4539 | } |
| 4540 | obj_priv = obj->driver_private; |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4541 | obj_priv->agp_type = AGP_USER_CACHED_MEMORY; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4542 | |
| 4543 | ret = i915_gem_object_pin(obj, 4096); |
| 4544 | if (ret != 0) { |
| 4545 | drm_gem_object_unreference(obj); |
| 4546 | return ret; |
| 4547 | } |
| 4548 | |
| 4549 | dev_priv->status_gfx_addr = obj_priv->gtt_offset; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4550 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4551 | dev_priv->hw_status_page = kmap(obj_priv->pages[0]); |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4552 | if (dev_priv->hw_status_page == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4553 | DRM_ERROR("Failed to map status page.\n"); |
| 4554 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
Chris Wilson | 3eb2ee7 | 2009-02-11 14:26:34 +0000 | [diff] [blame] | 4555 | i915_gem_object_unpin(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4556 | drm_gem_object_unreference(obj); |
| 4557 | return -EINVAL; |
| 4558 | } |
| 4559 | dev_priv->hws_obj = obj; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4560 | memset(dev_priv->hw_status_page, 0, PAGE_SIZE); |
| 4561 | I915_WRITE(HWS_PGA, dev_priv->status_gfx_addr); |
Keith Packard | ba1eb1d | 2008-10-14 19:55:10 -0700 | [diff] [blame] | 4562 | I915_READ(HWS_PGA); /* posting read */ |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4563 | DRM_DEBUG_DRIVER("hws offset: 0x%08x\n", dev_priv->status_gfx_addr); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4564 | |
| 4565 | return 0; |
| 4566 | } |
| 4567 | |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4568 | static void |
| 4569 | i915_gem_cleanup_hws(struct drm_device *dev) |
| 4570 | { |
| 4571 | drm_i915_private_t *dev_priv = dev->dev_private; |
Chris Wilson | bab2d1f | 2009-02-20 17:52:20 +0000 | [diff] [blame] | 4572 | struct drm_gem_object *obj; |
| 4573 | struct drm_i915_gem_object *obj_priv; |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4574 | |
| 4575 | if (dev_priv->hws_obj == NULL) |
| 4576 | return; |
| 4577 | |
Chris Wilson | bab2d1f | 2009-02-20 17:52:20 +0000 | [diff] [blame] | 4578 | obj = dev_priv->hws_obj; |
| 4579 | obj_priv = obj->driver_private; |
| 4580 | |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4581 | kunmap(obj_priv->pages[0]); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4582 | i915_gem_object_unpin(obj); |
| 4583 | drm_gem_object_unreference(obj); |
| 4584 | dev_priv->hws_obj = NULL; |
Chris Wilson | bab2d1f | 2009-02-20 17:52:20 +0000 | [diff] [blame] | 4585 | |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4586 | memset(&dev_priv->hws_map, 0, sizeof(dev_priv->hws_map)); |
| 4587 | dev_priv->hw_status_page = NULL; |
| 4588 | |
| 4589 | /* Write high address into HWS_PGA when disabling. */ |
| 4590 | I915_WRITE(HWS_PGA, 0x1ffff000); |
| 4591 | } |
| 4592 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4593 | int |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4594 | i915_gem_init_ringbuffer(struct drm_device *dev) |
| 4595 | { |
| 4596 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4597 | struct drm_gem_object *obj; |
| 4598 | struct drm_i915_gem_object *obj_priv; |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4599 | drm_i915_ring_buffer_t *ring = &dev_priv->ring; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4600 | int ret; |
Keith Packard | 50aa253d | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4601 | u32 head; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4602 | |
| 4603 | ret = i915_gem_init_hws(dev); |
| 4604 | if (ret != 0) |
| 4605 | return ret; |
| 4606 | |
| 4607 | obj = drm_gem_object_alloc(dev, 128 * 1024); |
| 4608 | if (obj == NULL) { |
| 4609 | DRM_ERROR("Failed to allocate ringbuffer\n"); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4610 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4611 | return -ENOMEM; |
| 4612 | } |
| 4613 | obj_priv = obj->driver_private; |
| 4614 | |
| 4615 | ret = i915_gem_object_pin(obj, 4096); |
| 4616 | if (ret != 0) { |
| 4617 | drm_gem_object_unreference(obj); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4618 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4619 | return ret; |
| 4620 | } |
| 4621 | |
| 4622 | /* Set up the kernel mapping for the ring. */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4623 | ring->Size = obj->size; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4624 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4625 | ring->map.offset = dev->agp->base + obj_priv->gtt_offset; |
| 4626 | ring->map.size = obj->size; |
| 4627 | ring->map.type = 0; |
| 4628 | ring->map.flags = 0; |
| 4629 | ring->map.mtrr = 0; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4630 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4631 | drm_core_ioremap_wc(&ring->map, dev); |
| 4632 | if (ring->map.handle == NULL) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4633 | DRM_ERROR("Failed to map ringbuffer.\n"); |
| 4634 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); |
Chris Wilson | 47ed185 | 2009-02-11 14:26:33 +0000 | [diff] [blame] | 4635 | i915_gem_object_unpin(obj); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4636 | drm_gem_object_unreference(obj); |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4637 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4638 | return -EINVAL; |
| 4639 | } |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4640 | ring->ring_obj = obj; |
| 4641 | ring->virtual_start = ring->map.handle; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4642 | |
| 4643 | /* Stop the ring if it's running. */ |
| 4644 | I915_WRITE(PRB0_CTL, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4645 | I915_WRITE(PRB0_TAIL, 0); |
Keith Packard | 50aa253d | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4646 | I915_WRITE(PRB0_HEAD, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4647 | |
| 4648 | /* Initialize the ring. */ |
| 4649 | I915_WRITE(PRB0_START, obj_priv->gtt_offset); |
Keith Packard | 50aa253d | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4650 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 4651 | |
| 4652 | /* G45 ring initialization fails to reset head to zero */ |
| 4653 | if (head != 0) { |
| 4654 | DRM_ERROR("Ring head not reset to zero " |
| 4655 | "ctl %08x head %08x tail %08x start %08x\n", |
| 4656 | I915_READ(PRB0_CTL), |
| 4657 | I915_READ(PRB0_HEAD), |
| 4658 | I915_READ(PRB0_TAIL), |
| 4659 | I915_READ(PRB0_START)); |
| 4660 | I915_WRITE(PRB0_HEAD, 0); |
| 4661 | |
| 4662 | DRM_ERROR("Ring head forced to zero " |
| 4663 | "ctl %08x head %08x tail %08x start %08x\n", |
| 4664 | I915_READ(PRB0_CTL), |
| 4665 | I915_READ(PRB0_HEAD), |
| 4666 | I915_READ(PRB0_TAIL), |
| 4667 | I915_READ(PRB0_START)); |
| 4668 | } |
| 4669 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4670 | I915_WRITE(PRB0_CTL, |
| 4671 | ((obj->size - 4096) & RING_NR_PAGES) | |
| 4672 | RING_NO_REPORT | |
| 4673 | RING_VALID); |
| 4674 | |
Keith Packard | 50aa253d | 2008-10-14 17:20:35 -0700 | [diff] [blame] | 4675 | head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 4676 | |
| 4677 | /* If the head is still not zero, the ring is dead */ |
| 4678 | if (head != 0) { |
| 4679 | DRM_ERROR("Ring initialization failed " |
| 4680 | "ctl %08x head %08x tail %08x start %08x\n", |
| 4681 | I915_READ(PRB0_CTL), |
| 4682 | I915_READ(PRB0_HEAD), |
| 4683 | I915_READ(PRB0_TAIL), |
| 4684 | I915_READ(PRB0_START)); |
| 4685 | return -EIO; |
| 4686 | } |
| 4687 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4688 | /* Update our cache of the ring state */ |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4689 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4690 | i915_kernel_lost_context(dev); |
| 4691 | else { |
| 4692 | ring->head = I915_READ(PRB0_HEAD) & HEAD_ADDR; |
| 4693 | ring->tail = I915_READ(PRB0_TAIL) & TAIL_ADDR; |
| 4694 | ring->space = ring->head - (ring->tail + 8); |
| 4695 | if (ring->space < 0) |
| 4696 | ring->space += ring->Size; |
| 4697 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4698 | |
| 4699 | return 0; |
| 4700 | } |
| 4701 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4702 | void |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4703 | i915_gem_cleanup_ringbuffer(struct drm_device *dev) |
| 4704 | { |
| 4705 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4706 | |
| 4707 | if (dev_priv->ring.ring_obj == NULL) |
| 4708 | return; |
| 4709 | |
| 4710 | drm_core_ioremapfree(&dev_priv->ring.map, dev); |
| 4711 | |
| 4712 | i915_gem_object_unpin(dev_priv->ring.ring_obj); |
| 4713 | drm_gem_object_unreference(dev_priv->ring.ring_obj); |
| 4714 | dev_priv->ring.ring_obj = NULL; |
| 4715 | memset(&dev_priv->ring, 0, sizeof(dev_priv->ring)); |
| 4716 | |
Chris Wilson | 85a7bb9 | 2009-02-11 14:52:44 +0000 | [diff] [blame] | 4717 | i915_gem_cleanup_hws(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4718 | } |
| 4719 | |
| 4720 | int |
| 4721 | i915_gem_entervt_ioctl(struct drm_device *dev, void *data, |
| 4722 | struct drm_file *file_priv) |
| 4723 | { |
| 4724 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4725 | int ret; |
| 4726 | |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4727 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4728 | return 0; |
| 4729 | |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4730 | if (atomic_read(&dev_priv->mm.wedged)) { |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4731 | DRM_ERROR("Reenabling wedged hardware, good luck\n"); |
Ben Gamari | ba1234d | 2009-09-14 17:48:47 -0400 | [diff] [blame] | 4732 | atomic_set(&dev_priv->mm.wedged, 0); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4733 | } |
| 4734 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4735 | mutex_lock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4736 | dev_priv->mm.suspended = 0; |
| 4737 | |
| 4738 | ret = i915_gem_init_ringbuffer(dev); |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4739 | if (ret != 0) { |
| 4740 | mutex_unlock(&dev->struct_mutex); |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4741 | return ret; |
Wu Fengguang | d816f6a | 2009-04-18 10:43:32 +0800 | [diff] [blame] | 4742 | } |
Eric Anholt | 9bb2d6f | 2008-12-23 18:42:32 -0800 | [diff] [blame] | 4743 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4744 | spin_lock(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4745 | BUG_ON(!list_empty(&dev_priv->mm.active_list)); |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4746 | spin_unlock(&dev_priv->mm.active_list_lock); |
| 4747 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4748 | BUG_ON(!list_empty(&dev_priv->mm.flushing_list)); |
| 4749 | BUG_ON(!list_empty(&dev_priv->mm.inactive_list)); |
| 4750 | BUG_ON(!list_empty(&dev_priv->mm.request_list)); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4751 | mutex_unlock(&dev->struct_mutex); |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4752 | |
| 4753 | drm_irq_install(dev); |
| 4754 | |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4755 | return 0; |
| 4756 | } |
| 4757 | |
| 4758 | int |
| 4759 | i915_gem_leavevt_ioctl(struct drm_device *dev, void *data, |
| 4760 | struct drm_file *file_priv) |
| 4761 | { |
Jesse Barnes | 79e5394 | 2008-11-07 14:24:08 -0800 | [diff] [blame] | 4762 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4763 | return 0; |
| 4764 | |
Kristian Høgsberg | dbb19d3 | 2008-08-20 11:04:27 -0400 | [diff] [blame] | 4765 | drm_irq_uninstall(dev); |
Linus Torvalds | e6890f6 | 2009-09-08 17:09:24 -0700 | [diff] [blame] | 4766 | return i915_gem_idle(dev); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4767 | } |
| 4768 | |
| 4769 | void |
| 4770 | i915_gem_lastclose(struct drm_device *dev) |
| 4771 | { |
| 4772 | int ret; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4773 | |
Eric Anholt | e806b49 | 2009-01-22 09:56:58 -0800 | [diff] [blame] | 4774 | if (drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4775 | return; |
| 4776 | |
Keith Packard | 6dbe277 | 2008-10-14 21:41:13 -0700 | [diff] [blame] | 4777 | ret = i915_gem_idle(dev); |
| 4778 | if (ret) |
| 4779 | DRM_ERROR("failed to idle hardware: %d\n", ret); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4780 | } |
| 4781 | |
| 4782 | void |
| 4783 | i915_gem_load(struct drm_device *dev) |
| 4784 | { |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4785 | int i; |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4786 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4787 | |
Carl Worth | 5e118f4 | 2009-03-20 11:54:25 -0700 | [diff] [blame] | 4788 | spin_lock_init(&dev_priv->mm.active_list_lock); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4789 | INIT_LIST_HEAD(&dev_priv->mm.active_list); |
| 4790 | INIT_LIST_HEAD(&dev_priv->mm.flushing_list); |
Daniel Vetter | 99fcb76 | 2010-02-07 16:20:18 +0100 | [diff] [blame] | 4791 | INIT_LIST_HEAD(&dev_priv->mm.gpu_write_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4792 | INIT_LIST_HEAD(&dev_priv->mm.inactive_list); |
| 4793 | INIT_LIST_HEAD(&dev_priv->mm.request_list); |
Eric Anholt | a09ba7f | 2009-08-29 12:49:51 -0700 | [diff] [blame] | 4794 | INIT_LIST_HEAD(&dev_priv->mm.fence_list); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4795 | INIT_DELAYED_WORK(&dev_priv->mm.retire_work, |
| 4796 | i915_gem_retire_work_handler); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4797 | dev_priv->mm.next_gem_seqno = 1; |
| 4798 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 4799 | spin_lock(&shrink_list_lock); |
| 4800 | list_add(&dev_priv->mm.shrink_list, &shrink_list); |
| 4801 | spin_unlock(&shrink_list_lock); |
| 4802 | |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4803 | /* Old X drivers will take 0-2 for front, back, depth buffers */ |
Eric Anholt | b397c83 | 2010-01-26 09:43:10 -0800 | [diff] [blame] | 4804 | if (!drm_core_check_feature(dev, DRIVER_MODESET)) |
| 4805 | dev_priv->fence_reg_start = 3; |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4806 | |
Jesse Barnes | 0f973f2 | 2009-01-26 17:10:45 -0800 | [diff] [blame] | 4807 | if (IS_I965G(dev) || IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
Jesse Barnes | de151cf | 2008-11-12 10:03:55 -0800 | [diff] [blame] | 4808 | dev_priv->num_fence_regs = 16; |
| 4809 | else |
| 4810 | dev_priv->num_fence_regs = 8; |
| 4811 | |
Grégoire Henry | b5aa8a0 | 2009-06-23 15:41:02 +0200 | [diff] [blame] | 4812 | /* Initialize fence registers to zero */ |
| 4813 | if (IS_I965G(dev)) { |
| 4814 | for (i = 0; i < 16; i++) |
| 4815 | I915_WRITE64(FENCE_REG_965_0 + (i * 8), 0); |
| 4816 | } else { |
| 4817 | for (i = 0; i < 8; i++) |
| 4818 | I915_WRITE(FENCE_REG_830_0 + (i * 4), 0); |
| 4819 | if (IS_I945G(dev) || IS_I945GM(dev) || IS_G33(dev)) |
| 4820 | for (i = 0; i < 8; i++) |
| 4821 | I915_WRITE(FENCE_REG_945_8 + (i * 4), 0); |
| 4822 | } |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4823 | i915_gem_detect_bit_6_swizzle(dev); |
Kristian Høgsberg | 6b95a20 | 2009-11-18 11:25:18 -0500 | [diff] [blame] | 4824 | init_waitqueue_head(&dev_priv->pending_flip_queue); |
Eric Anholt | 673a394 | 2008-07-30 12:06:12 -0700 | [diff] [blame] | 4825 | } |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4826 | |
| 4827 | /* |
| 4828 | * Create a physically contiguous memory object for this object |
| 4829 | * e.g. for cursor + overlay regs |
| 4830 | */ |
| 4831 | int i915_gem_init_phys_object(struct drm_device *dev, |
| 4832 | int id, int size) |
| 4833 | { |
| 4834 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4835 | struct drm_i915_gem_phys_object *phys_obj; |
| 4836 | int ret; |
| 4837 | |
| 4838 | if (dev_priv->mm.phys_objs[id - 1] || !size) |
| 4839 | return 0; |
| 4840 | |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4841 | phys_obj = kzalloc(sizeof(struct drm_i915_gem_phys_object), GFP_KERNEL); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4842 | if (!phys_obj) |
| 4843 | return -ENOMEM; |
| 4844 | |
| 4845 | phys_obj->id = id; |
| 4846 | |
Zhenyu Wang | e6be8d9 | 2010-01-05 11:25:05 +0800 | [diff] [blame] | 4847 | phys_obj->handle = drm_pci_alloc(dev, size, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4848 | if (!phys_obj->handle) { |
| 4849 | ret = -ENOMEM; |
| 4850 | goto kfree_obj; |
| 4851 | } |
| 4852 | #ifdef CONFIG_X86 |
| 4853 | set_memory_wc((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4854 | #endif |
| 4855 | |
| 4856 | dev_priv->mm.phys_objs[id - 1] = phys_obj; |
| 4857 | |
| 4858 | return 0; |
| 4859 | kfree_obj: |
Eric Anholt | 9a298b2 | 2009-03-24 12:23:04 -0700 | [diff] [blame] | 4860 | kfree(phys_obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4861 | return ret; |
| 4862 | } |
| 4863 | |
| 4864 | void i915_gem_free_phys_object(struct drm_device *dev, int id) |
| 4865 | { |
| 4866 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4867 | struct drm_i915_gem_phys_object *phys_obj; |
| 4868 | |
| 4869 | if (!dev_priv->mm.phys_objs[id - 1]) |
| 4870 | return; |
| 4871 | |
| 4872 | phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4873 | if (phys_obj->cur_obj) { |
| 4874 | i915_gem_detach_phys_object(dev, phys_obj->cur_obj); |
| 4875 | } |
| 4876 | |
| 4877 | #ifdef CONFIG_X86 |
| 4878 | set_memory_wb((unsigned long)phys_obj->handle->vaddr, phys_obj->handle->size / PAGE_SIZE); |
| 4879 | #endif |
| 4880 | drm_pci_free(dev, phys_obj->handle); |
| 4881 | kfree(phys_obj); |
| 4882 | dev_priv->mm.phys_objs[id - 1] = NULL; |
| 4883 | } |
| 4884 | |
| 4885 | void i915_gem_free_all_phys_object(struct drm_device *dev) |
| 4886 | { |
| 4887 | int i; |
| 4888 | |
Dave Airlie | 260883c | 2009-01-22 17:58:49 +1000 | [diff] [blame] | 4889 | for (i = I915_GEM_PHYS_CURSOR_0; i <= I915_MAX_PHYS_OBJECT; i++) |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4890 | i915_gem_free_phys_object(dev, i); |
| 4891 | } |
| 4892 | |
| 4893 | void i915_gem_detach_phys_object(struct drm_device *dev, |
| 4894 | struct drm_gem_object *obj) |
| 4895 | { |
| 4896 | struct drm_i915_gem_object *obj_priv; |
| 4897 | int i; |
| 4898 | int ret; |
| 4899 | int page_count; |
| 4900 | |
| 4901 | obj_priv = obj->driver_private; |
| 4902 | if (!obj_priv->phys_obj) |
| 4903 | return; |
| 4904 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4905 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4906 | if (ret) |
| 4907 | goto out; |
| 4908 | |
| 4909 | page_count = obj->size / PAGE_SIZE; |
| 4910 | |
| 4911 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4912 | char *dst = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4913 | char *src = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4914 | |
| 4915 | memcpy(dst, src, PAGE_SIZE); |
| 4916 | kunmap_atomic(dst, KM_USER0); |
| 4917 | } |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4918 | drm_clflush_pages(obj_priv->pages, page_count); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4919 | drm_agp_chipset_flush(dev); |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4920 | |
| 4921 | i915_gem_object_put_pages(obj); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4922 | out: |
| 4923 | obj_priv->phys_obj->cur_obj = NULL; |
| 4924 | obj_priv->phys_obj = NULL; |
| 4925 | } |
| 4926 | |
| 4927 | int |
| 4928 | i915_gem_attach_phys_object(struct drm_device *dev, |
| 4929 | struct drm_gem_object *obj, int id) |
| 4930 | { |
| 4931 | drm_i915_private_t *dev_priv = dev->dev_private; |
| 4932 | struct drm_i915_gem_object *obj_priv; |
| 4933 | int ret = 0; |
| 4934 | int page_count; |
| 4935 | int i; |
| 4936 | |
| 4937 | if (id > I915_MAX_PHYS_OBJECT) |
| 4938 | return -EINVAL; |
| 4939 | |
| 4940 | obj_priv = obj->driver_private; |
| 4941 | |
| 4942 | if (obj_priv->phys_obj) { |
| 4943 | if (obj_priv->phys_obj->id == id) |
| 4944 | return 0; |
| 4945 | i915_gem_detach_phys_object(dev, obj); |
| 4946 | } |
| 4947 | |
| 4948 | |
| 4949 | /* create a new object */ |
| 4950 | if (!dev_priv->mm.phys_objs[id - 1]) { |
| 4951 | ret = i915_gem_init_phys_object(dev, id, |
| 4952 | obj->size); |
| 4953 | if (ret) { |
Linus Torvalds | aeb565d | 2009-01-26 10:01:53 -0800 | [diff] [blame] | 4954 | DRM_ERROR("failed to init phys object %d size: %zu\n", id, obj->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4955 | goto out; |
| 4956 | } |
| 4957 | } |
| 4958 | |
| 4959 | /* bind to the object */ |
| 4960 | obj_priv->phys_obj = dev_priv->mm.phys_objs[id - 1]; |
| 4961 | obj_priv->phys_obj->cur_obj = obj; |
| 4962 | |
Chris Wilson | 4bdadb9 | 2010-01-27 13:36:32 +0000 | [diff] [blame] | 4963 | ret = i915_gem_object_get_pages(obj, 0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4964 | if (ret) { |
| 4965 | DRM_ERROR("failed to get page list\n"); |
| 4966 | goto out; |
| 4967 | } |
| 4968 | |
| 4969 | page_count = obj->size / PAGE_SIZE; |
| 4970 | |
| 4971 | for (i = 0; i < page_count; i++) { |
Eric Anholt | 856fa19 | 2009-03-19 14:10:50 -0700 | [diff] [blame] | 4972 | char *src = kmap_atomic(obj_priv->pages[i], KM_USER0); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4973 | char *dst = obj_priv->phys_obj->handle->vaddr + (i * PAGE_SIZE); |
| 4974 | |
| 4975 | memcpy(dst, src, PAGE_SIZE); |
| 4976 | kunmap_atomic(src, KM_USER0); |
| 4977 | } |
| 4978 | |
Chris Wilson | d78b47b | 2009-06-17 21:52:49 +0100 | [diff] [blame] | 4979 | i915_gem_object_put_pages(obj); |
| 4980 | |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 4981 | return 0; |
| 4982 | out: |
| 4983 | return ret; |
| 4984 | } |
| 4985 | |
| 4986 | static int |
| 4987 | i915_gem_phys_pwrite(struct drm_device *dev, struct drm_gem_object *obj, |
| 4988 | struct drm_i915_gem_pwrite *args, |
| 4989 | struct drm_file *file_priv) |
| 4990 | { |
| 4991 | struct drm_i915_gem_object *obj_priv = obj->driver_private; |
| 4992 | void *obj_addr; |
| 4993 | int ret; |
| 4994 | char __user *user_data; |
| 4995 | |
| 4996 | user_data = (char __user *) (uintptr_t) args->data_ptr; |
| 4997 | obj_addr = obj_priv->phys_obj->handle->vaddr + args->offset; |
| 4998 | |
Zhao Yakui | 44d98a6 | 2009-10-09 11:39:40 +0800 | [diff] [blame] | 4999 | DRM_DEBUG_DRIVER("obj_addr %p, %lld\n", obj_addr, args->size); |
Dave Airlie | 71acb5e | 2008-12-30 20:31:46 +1000 | [diff] [blame] | 5000 | ret = copy_from_user(obj_addr, user_data, args->size); |
| 5001 | if (ret) |
| 5002 | return -EFAULT; |
| 5003 | |
| 5004 | drm_agp_chipset_flush(dev); |
| 5005 | return 0; |
| 5006 | } |
Eric Anholt | b962442 | 2009-06-03 07:27:35 +0000 | [diff] [blame] | 5007 | |
| 5008 | void i915_gem_release(struct drm_device * dev, struct drm_file *file_priv) |
| 5009 | { |
| 5010 | struct drm_i915_file_private *i915_file_priv = file_priv->driver_priv; |
| 5011 | |
| 5012 | /* Clean up our request list when the client is going away, so that |
| 5013 | * later retire_requests won't dereference our soon-to-be-gone |
| 5014 | * file_priv. |
| 5015 | */ |
| 5016 | mutex_lock(&dev->struct_mutex); |
| 5017 | while (!list_empty(&i915_file_priv->mm.request_list)) |
| 5018 | list_del_init(i915_file_priv->mm.request_list.next); |
| 5019 | mutex_unlock(&dev->struct_mutex); |
| 5020 | } |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5021 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5022 | static int |
| 5023 | i915_gem_shrink(int nr_to_scan, gfp_t gfp_mask) |
| 5024 | { |
| 5025 | drm_i915_private_t *dev_priv, *next_dev; |
| 5026 | struct drm_i915_gem_object *obj_priv, *next_obj; |
| 5027 | int cnt = 0; |
| 5028 | int would_deadlock = 1; |
| 5029 | |
| 5030 | /* "fast-path" to count number of available objects */ |
| 5031 | if (nr_to_scan == 0) { |
| 5032 | spin_lock(&shrink_list_lock); |
| 5033 | list_for_each_entry(dev_priv, &shrink_list, mm.shrink_list) { |
| 5034 | struct drm_device *dev = dev_priv->dev; |
| 5035 | |
| 5036 | if (mutex_trylock(&dev->struct_mutex)) { |
| 5037 | list_for_each_entry(obj_priv, |
| 5038 | &dev_priv->mm.inactive_list, |
| 5039 | list) |
| 5040 | cnt++; |
| 5041 | mutex_unlock(&dev->struct_mutex); |
| 5042 | } |
| 5043 | } |
| 5044 | spin_unlock(&shrink_list_lock); |
| 5045 | |
| 5046 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 5047 | } |
| 5048 | |
| 5049 | spin_lock(&shrink_list_lock); |
| 5050 | |
| 5051 | /* first scan for clean buffers */ |
| 5052 | list_for_each_entry_safe(dev_priv, next_dev, |
| 5053 | &shrink_list, mm.shrink_list) { |
| 5054 | struct drm_device *dev = dev_priv->dev; |
| 5055 | |
| 5056 | if (! mutex_trylock(&dev->struct_mutex)) |
| 5057 | continue; |
| 5058 | |
| 5059 | spin_unlock(&shrink_list_lock); |
| 5060 | |
| 5061 | i915_gem_retire_requests(dev); |
| 5062 | |
| 5063 | list_for_each_entry_safe(obj_priv, next_obj, |
| 5064 | &dev_priv->mm.inactive_list, |
| 5065 | list) { |
| 5066 | if (i915_gem_object_is_purgeable(obj_priv)) { |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 5067 | i915_gem_object_unbind(obj_priv->obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5068 | if (--nr_to_scan <= 0) |
| 5069 | break; |
| 5070 | } |
| 5071 | } |
| 5072 | |
| 5073 | spin_lock(&shrink_list_lock); |
| 5074 | mutex_unlock(&dev->struct_mutex); |
| 5075 | |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 5076 | would_deadlock = 0; |
| 5077 | |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5078 | if (nr_to_scan <= 0) |
| 5079 | break; |
| 5080 | } |
| 5081 | |
| 5082 | /* second pass, evict/count anything still on the inactive list */ |
| 5083 | list_for_each_entry_safe(dev_priv, next_dev, |
| 5084 | &shrink_list, mm.shrink_list) { |
| 5085 | struct drm_device *dev = dev_priv->dev; |
| 5086 | |
| 5087 | if (! mutex_trylock(&dev->struct_mutex)) |
| 5088 | continue; |
| 5089 | |
| 5090 | spin_unlock(&shrink_list_lock); |
| 5091 | |
| 5092 | list_for_each_entry_safe(obj_priv, next_obj, |
| 5093 | &dev_priv->mm.inactive_list, |
| 5094 | list) { |
| 5095 | if (nr_to_scan > 0) { |
Chris Wilson | 963b483 | 2009-09-20 23:03:54 +0100 | [diff] [blame] | 5096 | i915_gem_object_unbind(obj_priv->obj); |
Chris Wilson | 3116971 | 2009-09-14 16:50:28 +0100 | [diff] [blame] | 5097 | nr_to_scan--; |
| 5098 | } else |
| 5099 | cnt++; |
| 5100 | } |
| 5101 | |
| 5102 | spin_lock(&shrink_list_lock); |
| 5103 | mutex_unlock(&dev->struct_mutex); |
| 5104 | |
| 5105 | would_deadlock = 0; |
| 5106 | } |
| 5107 | |
| 5108 | spin_unlock(&shrink_list_lock); |
| 5109 | |
| 5110 | if (would_deadlock) |
| 5111 | return -1; |
| 5112 | else if (cnt > 0) |
| 5113 | return (cnt / 100) * sysctl_vfs_cache_pressure; |
| 5114 | else |
| 5115 | return 0; |
| 5116 | } |
| 5117 | |
| 5118 | static struct shrinker shrinker = { |
| 5119 | .shrink = i915_gem_shrink, |
| 5120 | .seeks = DEFAULT_SEEKS, |
| 5121 | }; |
| 5122 | |
| 5123 | __init void |
| 5124 | i915_gem_shrinker_init(void) |
| 5125 | { |
| 5126 | register_shrinker(&shrinker); |
| 5127 | } |
| 5128 | |
| 5129 | __exit void |
| 5130 | i915_gem_shrinker_exit(void) |
| 5131 | { |
| 5132 | unregister_shrinker(&shrinker); |
| 5133 | } |