Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (c) 2004, 2005 Topspin Communications. All rights reserved. |
Jack Morgenstein | 51a379d | 2008-07-25 10:32:52 -0700 | [diff] [blame] | 3 | * Copyright (c) 2005, 2006, 2007, 2008 Mellanox Technologies. All rights reserved. |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 4 | * Copyright (c) 2005, 2006, 2007 Cisco Systems, Inc. All rights reserved. |
| 5 | * |
| 6 | * This software is available to you under a choice of one of two |
| 7 | * licenses. You may choose to be licensed under the terms of the GNU |
| 8 | * General Public License (GPL) Version 2, available from the file |
| 9 | * COPYING in the main directory of this source tree, or the |
| 10 | * OpenIB.org BSD license below: |
| 11 | * |
| 12 | * Redistribution and use in source and binary forms, with or |
| 13 | * without modification, are permitted provided that the following |
| 14 | * conditions are met: |
| 15 | * |
| 16 | * - Redistributions of source code must retain the above |
| 17 | * copyright notice, this list of conditions and the following |
| 18 | * disclaimer. |
| 19 | * |
| 20 | * - Redistributions in binary form must reproduce the above |
| 21 | * copyright notice, this list of conditions and the following |
| 22 | * disclaimer in the documentation and/or other materials |
| 23 | * provided with the distribution. |
| 24 | * |
| 25 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, |
| 26 | * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF |
| 27 | * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND |
| 28 | * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS |
| 29 | * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN |
| 30 | * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN |
| 31 | * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE |
| 32 | * SOFTWARE. |
| 33 | */ |
| 34 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 35 | #include <linux/etherdevice.h> |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 36 | #include <linux/mlx4/cmd.h> |
Paul Gortmaker | 9d9779e | 2011-07-03 15:21:01 -0400 | [diff] [blame] | 37 | #include <linux/module.h> |
Eli Cohen | c57e20dcf | 2009-09-24 11:03:03 -0700 | [diff] [blame] | 38 | #include <linux/cache.h> |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 39 | |
| 40 | #include "fw.h" |
| 41 | #include "icm.h" |
| 42 | |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 43 | enum { |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 44 | MLX4_COMMAND_INTERFACE_MIN_REV = 2, |
| 45 | MLX4_COMMAND_INTERFACE_MAX_REV = 3, |
| 46 | MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS = 3, |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 47 | }; |
| 48 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 49 | extern void __buggy_use_of_MLX4_GET(void); |
| 50 | extern void __buggy_use_of_MLX4_PUT(void); |
| 51 | |
Ido Shamay | 38438f7 | 2015-04-02 16:31:18 +0300 | [diff] [blame] | 52 | static bool enable_qos = true; |
Jack Morgenstein | 51f5f0e | 2008-07-22 14:19:37 -0700 | [diff] [blame] | 53 | module_param(enable_qos, bool, 0444); |
Ido Shamay | 38438f7 | 2015-04-02 16:31:18 +0300 | [diff] [blame] | 54 | MODULE_PARM_DESC(enable_qos, "Enable Enhanced QoS support (default: on)"); |
Jack Morgenstein | 51f5f0e | 2008-07-22 14:19:37 -0700 | [diff] [blame] | 55 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 56 | #define MLX4_GET(dest, source, offset) \ |
| 57 | do { \ |
| 58 | void *__p = (char *) (source) + (offset); \ |
David Ahern | 17d5ceb | 2015-04-29 16:52:51 -0400 | [diff] [blame] | 59 | u64 val; \ |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 60 | switch (sizeof (dest)) { \ |
| 61 | case 1: (dest) = *(u8 *) __p; break; \ |
| 62 | case 2: (dest) = be16_to_cpup(__p); break; \ |
| 63 | case 4: (dest) = be32_to_cpup(__p); break; \ |
David Ahern | 17d5ceb | 2015-04-29 16:52:51 -0400 | [diff] [blame] | 64 | case 8: val = get_unaligned((u64 *)__p); \ |
| 65 | (dest) = be64_to_cpu(val); break; \ |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 66 | default: __buggy_use_of_MLX4_GET(); \ |
| 67 | } \ |
| 68 | } while (0) |
| 69 | |
| 70 | #define MLX4_PUT(dest, source, offset) \ |
| 71 | do { \ |
| 72 | void *__d = ((char *) (dest) + (offset)); \ |
| 73 | switch (sizeof(source)) { \ |
| 74 | case 1: *(u8 *) __d = (source); break; \ |
| 75 | case 2: *(__be16 *) __d = cpu_to_be16(source); break; \ |
| 76 | case 4: *(__be32 *) __d = cpu_to_be32(source); break; \ |
| 77 | case 8: *(__be64 *) __d = cpu_to_be64(source); break; \ |
| 78 | default: __buggy_use_of_MLX4_PUT(); \ |
| 79 | } \ |
| 80 | } while (0) |
| 81 | |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 82 | static void dump_dev_cap_flags(struct mlx4_dev *dev, u64 flags) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 83 | { |
| 84 | static const char *fname[] = { |
| 85 | [ 0] = "RC transport", |
| 86 | [ 1] = "UC transport", |
| 87 | [ 2] = "UD transport", |
Roland Dreier | ea98054 | 2007-10-09 19:59:13 -0700 | [diff] [blame] | 88 | [ 3] = "XRC transport", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 89 | [ 6] = "SRQ support", |
| 90 | [ 7] = "IPoIB checksum offload", |
| 91 | [ 8] = "P_Key violation counter", |
| 92 | [ 9] = "Q_Key violation counter", |
Or Gerlitz | 4d531aa | 2013-04-07 03:44:06 +0000 | [diff] [blame] | 93 | [12] = "Dual Port Different Protocol (DPDP) support", |
Eli Cohen | 417608c | 2009-11-12 11:19:44 -0800 | [diff] [blame] | 94 | [15] = "Big LSO headers", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 95 | [16] = "MW support", |
| 96 | [17] = "APM support", |
| 97 | [18] = "Atomic ops support", |
| 98 | [19] = "Raw multicast support", |
| 99 | [20] = "Address vector port checking support", |
| 100 | [21] = "UD multicast support", |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 101 | [30] = "IBoE support", |
| 102 | [32] = "Unicast loopback support", |
Yevgeny Petrilin | f3a9d1f | 2011-10-18 01:50:42 +0000 | [diff] [blame] | 103 | [34] = "FCS header control", |
Or Gerlitz | cb2147a | 2015-01-27 15:58:08 +0200 | [diff] [blame] | 104 | [37] = "Wake On LAN (port1) support", |
| 105 | [38] = "Wake On LAN (port2) support", |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 106 | [40] = "UDP RSS support", |
| 107 | [41] = "Unicast VEP steering support", |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 108 | [42] = "Multicast VEP steering support", |
| 109 | [48] = "Counters support", |
Ido Shamay | 802f42a | 2015-04-02 16:31:06 +0300 | [diff] [blame] | 110 | [52] = "RSS IP fragments support", |
Or Gerlitz | 540b3a3 | 2013-04-07 03:44:07 +0000 | [diff] [blame] | 111 | [53] = "Port ETS Scheduler support", |
Or Gerlitz | 4d531aa | 2013-04-07 03:44:06 +0000 | [diff] [blame] | 112 | [55] = "Port link type sensing support", |
Jack Morgenstein | 00f5ce9 | 2012-06-19 11:21:40 +0300 | [diff] [blame] | 113 | [59] = "Port management change event support", |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 114 | [61] = "64 byte EQE support", |
| 115 | [62] = "64 byte CQE support", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 116 | }; |
| 117 | int i; |
| 118 | |
| 119 | mlx4_dbg(dev, "DEV_CAP flags:\n"); |
Roland Dreier | 23c15c2 | 2007-05-19 08:51:57 -0700 | [diff] [blame] | 120 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 121 | if (fname[i] && (flags & (1LL << i))) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 122 | mlx4_dbg(dev, " %s\n", fname[i]); |
| 123 | } |
| 124 | |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 125 | static void dump_dev_cap_flags2(struct mlx4_dev *dev, u64 flags) |
| 126 | { |
| 127 | static const char * const fname[] = { |
| 128 | [0] = "RSS support", |
| 129 | [1] = "RSS Toeplitz Hash Function support", |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 130 | [2] = "RSS XOR Hash Function support", |
Or Gerlitz | 56cb456 | 2014-03-12 17:16:30 +0200 | [diff] [blame] | 131 | [3] = "Device managed flow steering support", |
Eugenia Emantayev | d998735 | 2013-04-23 06:06:47 +0000 | [diff] [blame] | 132 | [4] = "Automatic MAC reassignment support", |
Or Gerlitz | 4e8cf5b | 2013-05-08 22:22:34 +0000 | [diff] [blame] | 133 | [5] = "Time stamping support", |
| 134 | [6] = "VST (control vlan insertion/stripping) support", |
Jack Morgenstein | b01978c | 2013-06-27 19:05:21 +0300 | [diff] [blame] | 135 | [7] = "FSM (MAC anti-spoofing) support", |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 136 | [8] = "Dynamic QP updates support", |
Or Gerlitz | 56cb456 | 2014-03-12 17:16:30 +0200 | [diff] [blame] | 137 | [9] = "Device managed flow steering IPoIB support", |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 138 | [10] = "TCP/IP offloads/flow-steering for VXLAN support", |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 139 | [11] = "MAD DEMUX (Secure-Host) support", |
| 140 | [12] = "Large cache line (>64B) CQE stride support", |
Saeed Mahameed | adbc7ac | 2014-10-27 11:37:37 +0200 | [diff] [blame] | 141 | [13] = "Large cache line (>64B) EQE stride support", |
Saeed Mahameed | a53e3e8 | 2014-10-27 11:37:38 +0200 | [diff] [blame] | 142 | [14] = "Ethernet protocol control support", |
Matan Barak | d475c95 | 2014-11-02 16:26:17 +0200 | [diff] [blame] | 143 | [15] = "Ethernet Backplane autoneg support", |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 144 | [16] = "CONFIG DEV support", |
Matan Barak | de966c5 | 2014-11-13 14:45:33 +0200 | [diff] [blame] | 145 | [17] = "Asymmetric EQs support", |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 146 | [18] = "More than 80 VFs support", |
Jack Morgenstein | be6a6b4 | 2015-01-27 15:57:59 +0200 | [diff] [blame] | 147 | [19] = "Performance optimized for limited rule configuration flow steering support", |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 148 | [20] = "Recoverable error events support", |
Shani Michaeli | d237baa | 2015-03-05 20:16:12 +0200 | [diff] [blame] | 149 | [21] = "Port Remap support", |
Or Gerlitz | fc31e25 | 2015-03-18 14:57:34 +0200 | [diff] [blame] | 150 | [22] = "QCN support", |
Matan Barak | 0b13156 | 2015-03-30 17:45:25 +0300 | [diff] [blame] | 151 | [23] = "QP rate limiting support", |
Ido Shamay | d019fcb | 2015-04-02 16:31:13 +0300 | [diff] [blame] | 152 | [24] = "Ethernet Flow control statistics support", |
| 153 | [25] = "Granular QoS per VF support", |
Ido Shamay | 3742cc6 | 2015-04-02 16:31:17 +0300 | [diff] [blame] | 154 | [26] = "Port ETS Scheduler support", |
Ido Shamay | 51af33c | 2015-04-02 16:31:20 +0300 | [diff] [blame] | 155 | [27] = "Port beacon support", |
Muhammad Mahajna | 78500b8 | 2015-04-02 16:31:22 +0300 | [diff] [blame] | 156 | [28] = "RX-ALL support", |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 157 | [29] = "802.1ad offload support", |
Maor Gottlieb | 9a89283 | 2015-10-15 14:44:38 +0300 | [diff] [blame] | 158 | [31] = "Modifying loopback source checks using UPDATE_QP support", |
| 159 | [32] = "Loopback source checks support", |
Marina Varshaver | 0e451e8 | 2016-02-18 18:31:06 +0200 | [diff] [blame] | 160 | [33] = "RoCEv2 support", |
| 161 | [34] = "DMFS Sniffer support (UC & MC)" |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 162 | }; |
| 163 | int i; |
| 164 | |
| 165 | for (i = 0; i < ARRAY_SIZE(fname); ++i) |
| 166 | if (fname[i] && (flags & (1LL << i))) |
| 167 | mlx4_dbg(dev, " %s\n", fname[i]); |
| 168 | } |
| 169 | |
Vladimir Sokolovsky | 2d92865 | 2008-07-14 23:48:53 -0700 | [diff] [blame] | 170 | int mlx4_MOD_STAT_CFG(struct mlx4_dev *dev, struct mlx4_mod_stat_cfg *cfg) |
| 171 | { |
| 172 | struct mlx4_cmd_mailbox *mailbox; |
| 173 | u32 *inbox; |
| 174 | int err = 0; |
| 175 | |
| 176 | #define MOD_STAT_CFG_IN_SIZE 0x100 |
| 177 | |
| 178 | #define MOD_STAT_CFG_PG_SZ_M_OFFSET 0x002 |
| 179 | #define MOD_STAT_CFG_PG_SZ_OFFSET 0x003 |
| 180 | |
| 181 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 182 | if (IS_ERR(mailbox)) |
| 183 | return PTR_ERR(mailbox); |
| 184 | inbox = mailbox->buf; |
| 185 | |
Vladimir Sokolovsky | 2d92865 | 2008-07-14 23:48:53 -0700 | [diff] [blame] | 186 | MLX4_PUT(inbox, cfg->log_pg_sz, MOD_STAT_CFG_PG_SZ_OFFSET); |
| 187 | MLX4_PUT(inbox, cfg->log_pg_sz_m, MOD_STAT_CFG_PG_SZ_M_OFFSET); |
| 188 | |
| 189 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_MOD_STAT_CFG, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 190 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Vladimir Sokolovsky | 2d92865 | 2008-07-14 23:48:53 -0700 | [diff] [blame] | 191 | |
| 192 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 193 | return err; |
| 194 | } |
| 195 | |
Matan Barak | e8c4265 | 2014-11-13 14:45:31 +0200 | [diff] [blame] | 196 | int mlx4_QUERY_FUNC(struct mlx4_dev *dev, struct mlx4_func *func, int slave) |
| 197 | { |
| 198 | struct mlx4_cmd_mailbox *mailbox; |
| 199 | u32 *outbox; |
| 200 | u8 in_modifier; |
| 201 | u8 field; |
| 202 | u16 field16; |
| 203 | int err; |
| 204 | |
| 205 | #define QUERY_FUNC_BUS_OFFSET 0x00 |
| 206 | #define QUERY_FUNC_DEVICE_OFFSET 0x01 |
| 207 | #define QUERY_FUNC_FUNCTION_OFFSET 0x01 |
| 208 | #define QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET 0x03 |
| 209 | #define QUERY_FUNC_RSVD_EQS_OFFSET 0x04 |
| 210 | #define QUERY_FUNC_MAX_EQ_OFFSET 0x06 |
| 211 | #define QUERY_FUNC_RSVD_UARS_OFFSET 0x0b |
| 212 | |
| 213 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 214 | if (IS_ERR(mailbox)) |
| 215 | return PTR_ERR(mailbox); |
| 216 | outbox = mailbox->buf; |
| 217 | |
| 218 | in_modifier = slave; |
Matan Barak | e8c4265 | 2014-11-13 14:45:31 +0200 | [diff] [blame] | 219 | |
| 220 | err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, 0, |
| 221 | MLX4_CMD_QUERY_FUNC, |
| 222 | MLX4_CMD_TIME_CLASS_A, |
| 223 | MLX4_CMD_NATIVE); |
| 224 | if (err) |
| 225 | goto out; |
| 226 | |
| 227 | MLX4_GET(field, outbox, QUERY_FUNC_BUS_OFFSET); |
| 228 | func->bus = field & 0xf; |
| 229 | MLX4_GET(field, outbox, QUERY_FUNC_DEVICE_OFFSET); |
| 230 | func->device = field & 0xf1; |
| 231 | MLX4_GET(field, outbox, QUERY_FUNC_FUNCTION_OFFSET); |
| 232 | func->function = field & 0x7; |
| 233 | MLX4_GET(field, outbox, QUERY_FUNC_PHYSICAL_FUNCTION_OFFSET); |
| 234 | func->physical_function = field & 0xf; |
| 235 | MLX4_GET(field16, outbox, QUERY_FUNC_RSVD_EQS_OFFSET); |
| 236 | func->rsvd_eqs = field16 & 0xffff; |
| 237 | MLX4_GET(field16, outbox, QUERY_FUNC_MAX_EQ_OFFSET); |
| 238 | func->max_eq = field16 & 0xffff; |
| 239 | MLX4_GET(field, outbox, QUERY_FUNC_RSVD_UARS_OFFSET); |
| 240 | func->rsvd_uars = field & 0x0f; |
| 241 | |
| 242 | mlx4_dbg(dev, "Bus: %d, Device: %d, Function: %d, Physical function: %d, Max EQs: %d, Reserved EQs: %d, Reserved UARs: %d\n", |
| 243 | func->bus, func->device, func->function, func->physical_function, |
| 244 | func->max_eq, func->rsvd_eqs, func->rsvd_uars); |
| 245 | |
| 246 | out: |
| 247 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 248 | return err; |
| 249 | } |
| 250 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 251 | int mlx4_QUERY_FUNC_CAP_wrapper(struct mlx4_dev *dev, int slave, |
| 252 | struct mlx4_vhcr *vhcr, |
| 253 | struct mlx4_cmd_mailbox *inbox, |
| 254 | struct mlx4_cmd_mailbox *outbox, |
| 255 | struct mlx4_cmd_info *cmd) |
| 256 | { |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 257 | struct mlx4_priv *priv = mlx4_priv(dev); |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 258 | u8 field, port; |
| 259 | u32 size, proxy_qp, qkey; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 260 | int err = 0; |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 261 | struct mlx4_func func; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 262 | |
| 263 | #define QUERY_FUNC_CAP_FLAGS_OFFSET 0x0 |
| 264 | #define QUERY_FUNC_CAP_NUM_PORTS_OFFSET 0x1 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 265 | #define QUERY_FUNC_CAP_PF_BHVR_OFFSET 0x4 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 266 | #define QUERY_FUNC_CAP_FMR_OFFSET 0x8 |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 267 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP 0x10 |
| 268 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP 0x14 |
| 269 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP 0x18 |
| 270 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP 0x20 |
| 271 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP 0x24 |
| 272 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP 0x28 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 273 | #define QUERY_FUNC_CAP_MAX_EQ_OFFSET 0x2c |
Roland Dreier | 69612b9 | 2012-09-23 09:18:24 -0700 | [diff] [blame] | 274 | #define QUERY_FUNC_CAP_RESERVED_EQ_OFFSET 0x30 |
Jack Morgenstein | f0ce061 | 2015-01-27 15:58:00 +0200 | [diff] [blame] | 275 | #define QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET 0x48 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 276 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 277 | #define QUERY_FUNC_CAP_QP_QUOTA_OFFSET 0x50 |
| 278 | #define QUERY_FUNC_CAP_CQ_QUOTA_OFFSET 0x54 |
| 279 | #define QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET 0x58 |
| 280 | #define QUERY_FUNC_CAP_MPT_QUOTA_OFFSET 0x60 |
| 281 | #define QUERY_FUNC_CAP_MTT_QUOTA_OFFSET 0x64 |
| 282 | #define QUERY_FUNC_CAP_MCG_QUOTA_OFFSET 0x68 |
| 283 | |
Eugenia Emantayev | ddae034 | 2014-12-11 10:57:54 +0200 | [diff] [blame] | 284 | #define QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET 0x6c |
| 285 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 286 | #define QUERY_FUNC_CAP_FMR_FLAG 0x80 |
| 287 | #define QUERY_FUNC_CAP_FLAG_RDMA 0x40 |
| 288 | #define QUERY_FUNC_CAP_FLAG_ETH 0x80 |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 289 | #define QUERY_FUNC_CAP_FLAG_QUOTAS 0x10 |
Jack Morgenstein | f0ce061 | 2015-01-27 15:58:00 +0200 | [diff] [blame] | 290 | #define QUERY_FUNC_CAP_FLAG_RESD_LKEY 0x08 |
Eugenia Emantayev | ddae034 | 2014-12-11 10:57:54 +0200 | [diff] [blame] | 291 | #define QUERY_FUNC_CAP_FLAG_VALID_MAILBOX 0x04 |
| 292 | |
| 293 | #define QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG (1UL << 31) |
Matan Barak | d57febe | 2014-12-11 10:57:57 +0200 | [diff] [blame] | 294 | #define QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG (1UL << 30) |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 295 | |
| 296 | /* when opcode modifier = 1 */ |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 297 | #define QUERY_FUNC_CAP_PHYS_PORT_OFFSET 0x3 |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 298 | #define QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET 0x4 |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 299 | #define QUERY_FUNC_CAP_FLAGS0_OFFSET 0x8 |
| 300 | #define QUERY_FUNC_CAP_FLAGS1_OFFSET 0xc |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 301 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 302 | #define QUERY_FUNC_CAP_QP0_TUNNEL 0x10 |
| 303 | #define QUERY_FUNC_CAP_QP0_PROXY 0x14 |
| 304 | #define QUERY_FUNC_CAP_QP1_TUNNEL 0x18 |
| 305 | #define QUERY_FUNC_CAP_QP1_PROXY 0x1c |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 306 | #define QUERY_FUNC_CAP_PHYS_PORT_ID 0x28 |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 307 | |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 308 | #define QUERY_FUNC_CAP_FLAGS1_FORCE_MAC 0x40 |
| 309 | #define QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN 0x80 |
Hadar Hen Zion | eb17711 | 2013-12-19 21:20:11 +0200 | [diff] [blame] | 310 | #define QUERY_FUNC_CAP_FLAGS1_NIC_INFO 0x10 |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 311 | #define QUERY_FUNC_CAP_VF_ENABLE_QP0 0x08 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 312 | |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 313 | #define QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID 0x80 |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 314 | #define QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS (1 << 31) |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 315 | #define QUERY_FUNC_CAP_PHV_BIT 0x40 |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 316 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 317 | if (vhcr->op_modifier == 1) { |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 318 | struct mlx4_active_ports actv_ports = |
| 319 | mlx4_get_active_ports(dev, slave); |
| 320 | int converted_port = mlx4_slave_convert_port( |
| 321 | dev, slave, vhcr->in_modifier); |
| 322 | |
| 323 | if (converted_port < 0) |
| 324 | return -EINVAL; |
| 325 | |
| 326 | vhcr->in_modifier = converted_port; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 327 | /* phys-port = logical-port */ |
| 328 | field = vhcr->in_modifier - |
| 329 | find_first_bit(actv_ports.ports, dev->caps.num_ports); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 330 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
| 331 | |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 332 | port = vhcr->in_modifier; |
| 333 | proxy_qp = dev->phys_caps.base_proxy_sqpn + 8 * slave + port - 1; |
| 334 | |
| 335 | /* Set nic_info bit to mark new fields support */ |
| 336 | field = QUERY_FUNC_CAP_FLAGS1_NIC_INFO; |
| 337 | |
| 338 | if (mlx4_vf_smi_enabled(dev, slave, port) && |
| 339 | !mlx4_get_parav_qkey(dev, proxy_qp, &qkey)) { |
| 340 | field |= QUERY_FUNC_CAP_VF_ENABLE_QP0; |
| 341 | MLX4_PUT(outbox->buf, qkey, |
| 342 | QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); |
| 343 | } |
| 344 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS1_OFFSET); |
| 345 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 346 | /* size is now the QP number */ |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 347 | size = dev->phys_caps.base_tunnel_sqpn + 8 * slave + port - 1; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 348 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP0_TUNNEL); |
| 349 | |
| 350 | size += 2; |
| 351 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP1_TUNNEL); |
| 352 | |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 353 | MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP0_PROXY); |
| 354 | proxy_qp += 2; |
| 355 | MLX4_PUT(outbox->buf, proxy_qp, QUERY_FUNC_CAP_QP1_PROXY); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 356 | |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 357 | MLX4_PUT(outbox->buf, dev->caps.phys_port_id[vhcr->in_modifier], |
| 358 | QUERY_FUNC_CAP_PHYS_PORT_ID); |
| 359 | |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 360 | if (dev->caps.phv_bit[port]) { |
| 361 | field = QUERY_FUNC_CAP_PHV_BIT; |
| 362 | MLX4_PUT(outbox->buf, field, |
| 363 | QUERY_FUNC_CAP_FLAGS0_OFFSET); |
| 364 | } |
| 365 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 366 | } else if (vhcr->op_modifier == 0) { |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 367 | struct mlx4_active_ports actv_ports = |
| 368 | mlx4_get_active_ports(dev, slave); |
Jack Morgenstein | f0ce061 | 2015-01-27 15:58:00 +0200 | [diff] [blame] | 369 | /* enable rdma and ethernet interfaces, new quota locations, |
| 370 | * and reserved lkey |
| 371 | */ |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 372 | field = (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA | |
Jack Morgenstein | f0ce061 | 2015-01-27 15:58:00 +0200 | [diff] [blame] | 373 | QUERY_FUNC_CAP_FLAG_QUOTAS | QUERY_FUNC_CAP_FLAG_VALID_MAILBOX | |
| 374 | QUERY_FUNC_CAP_FLAG_RESD_LKEY); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 375 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FLAGS_OFFSET); |
| 376 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 377 | field = min( |
| 378 | bitmap_weight(actv_ports.ports, dev->caps.num_ports), |
| 379 | dev->caps.num_ports); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 380 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
| 381 | |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 382 | size = dev->caps.function_caps; /* set PF behaviours */ |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 383 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
| 384 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 385 | field = 0; /* protected FMR support not available as yet */ |
| 386 | MLX4_PUT(outbox->buf, field, QUERY_FUNC_CAP_FMR_OFFSET); |
| 387 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 388 | size = priv->mfunc.master.res_tracker.res_alloc[RES_QP].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 389 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 390 | size = dev->caps.num_qps; |
| 391 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 392 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 393 | size = priv->mfunc.master.res_tracker.res_alloc[RES_SRQ].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 394 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 395 | size = dev->caps.num_srqs; |
| 396 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 397 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 398 | size = priv->mfunc.master.res_tracker.res_alloc[RES_CQ].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 399 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 400 | size = dev->caps.num_cqs; |
| 401 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 402 | |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 403 | if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SYS_EQS) || |
| 404 | mlx4_QUERY_FUNC(dev, &func, slave)) { |
| 405 | size = vhcr->in_modifier & |
| 406 | QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? |
| 407 | dev->caps.num_eqs : |
| 408 | rounddown_pow_of_two(dev->caps.num_eqs); |
| 409 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 410 | size = dev->caps.reserved_eqs; |
| 411 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 412 | } else { |
| 413 | size = vhcr->in_modifier & |
| 414 | QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS ? |
| 415 | func.max_eq : |
| 416 | rounddown_pow_of_two(func.max_eq); |
| 417 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 418 | size = func.rsvd_eqs; |
| 419 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 420 | } |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 421 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 422 | size = priv->mfunc.master.res_tracker.res_alloc[RES_MPT].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 423 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 424 | size = dev->caps.num_mpts; |
| 425 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 426 | |
Jack Morgenstein | 5a0d0a6 | 2013-11-03 10:03:23 +0200 | [diff] [blame] | 427 | size = priv->mfunc.master.res_tracker.res_alloc[RES_MTT].quota[slave]; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 428 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 429 | size = dev->caps.num_mtts; |
| 430 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 431 | |
| 432 | size = dev->caps.num_mgms + dev->caps.num_amgms; |
| 433 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 434 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 435 | |
Matan Barak | d57febe | 2014-12-11 10:57:57 +0200 | [diff] [blame] | 436 | size = QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG | |
| 437 | QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG; |
Eugenia Emantayev | ddae034 | 2014-12-11 10:57:54 +0200 | [diff] [blame] | 438 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); |
Jack Morgenstein | f0ce061 | 2015-01-27 15:58:00 +0200 | [diff] [blame] | 439 | |
| 440 | size = dev->caps.reserved_lkey + ((slave << 8) & 0xFF00); |
| 441 | MLX4_PUT(outbox->buf, size, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 442 | } else |
| 443 | err = -EINVAL; |
| 444 | |
| 445 | return err; |
| 446 | } |
| 447 | |
Matan Barak | 225c6c8 | 2014-11-13 14:45:28 +0200 | [diff] [blame] | 448 | int mlx4_QUERY_FUNC_CAP(struct mlx4_dev *dev, u8 gen_or_port, |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 449 | struct mlx4_func_cap *func_cap) |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 450 | { |
| 451 | struct mlx4_cmd_mailbox *mailbox; |
| 452 | u32 *outbox; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 453 | u8 field, op_modifier; |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 454 | u32 size, qkey; |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 455 | int err = 0, quotas = 0; |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 456 | u32 in_modifier; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 457 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 458 | op_modifier = !!gen_or_port; /* 0 = general, 1 = logical port */ |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 459 | in_modifier = op_modifier ? gen_or_port : |
| 460 | QUERY_FUNC_CAP_SUPPORTS_NON_POWER_OF_2_NUM_EQS; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 461 | |
| 462 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 463 | if (IS_ERR(mailbox)) |
| 464 | return PTR_ERR(mailbox); |
| 465 | |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 466 | err = mlx4_cmd_box(dev, 0, mailbox->dma, in_modifier, op_modifier, |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 467 | MLX4_CMD_QUERY_FUNC_CAP, |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 468 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
| 469 | if (err) |
| 470 | goto out; |
| 471 | |
| 472 | outbox = mailbox->buf; |
| 473 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 474 | if (!op_modifier) { |
| 475 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS_OFFSET); |
| 476 | if (!(field & (QUERY_FUNC_CAP_FLAG_ETH | QUERY_FUNC_CAP_FLAG_RDMA))) { |
| 477 | mlx4_err(dev, "The host supports neither eth nor rdma interfaces\n"); |
| 478 | err = -EPROTONOSUPPORT; |
| 479 | goto out; |
| 480 | } |
| 481 | func_cap->flags = field; |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 482 | quotas = !!(func_cap->flags & QUERY_FUNC_CAP_FLAG_QUOTAS); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 483 | |
| 484 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_NUM_PORTS_OFFSET); |
| 485 | func_cap->num_ports = field; |
| 486 | |
| 487 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_PF_BHVR_OFFSET); |
| 488 | func_cap->pf_context_behaviour = size; |
| 489 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 490 | if (quotas) { |
| 491 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET); |
| 492 | func_cap->qp_quota = size & 0xFFFFFF; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 493 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 494 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET); |
| 495 | func_cap->srq_quota = size & 0xFFFFFF; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 496 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 497 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET); |
| 498 | func_cap->cq_quota = size & 0xFFFFFF; |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 499 | |
Jack Morgenstein | eb456a6 | 2013-11-03 10:03:24 +0200 | [diff] [blame] | 500 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET); |
| 501 | func_cap->mpt_quota = size & 0xFFFFFF; |
| 502 | |
| 503 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET); |
| 504 | func_cap->mtt_quota = size & 0xFFFFFF; |
| 505 | |
| 506 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET); |
| 507 | func_cap->mcg_quota = size & 0xFFFFFF; |
| 508 | |
| 509 | } else { |
| 510 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_QUOTA_OFFSET_DEP); |
| 511 | func_cap->qp_quota = size & 0xFFFFFF; |
| 512 | |
| 513 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_SRQ_QUOTA_OFFSET_DEP); |
| 514 | func_cap->srq_quota = size & 0xFFFFFF; |
| 515 | |
| 516 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_CQ_QUOTA_OFFSET_DEP); |
| 517 | func_cap->cq_quota = size & 0xFFFFFF; |
| 518 | |
| 519 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MPT_QUOTA_OFFSET_DEP); |
| 520 | func_cap->mpt_quota = size & 0xFFFFFF; |
| 521 | |
| 522 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MTT_QUOTA_OFFSET_DEP); |
| 523 | func_cap->mtt_quota = size & 0xFFFFFF; |
| 524 | |
| 525 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MCG_QUOTA_OFFSET_DEP); |
| 526 | func_cap->mcg_quota = size & 0xFFFFFF; |
| 527 | } |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 528 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_MAX_EQ_OFFSET); |
| 529 | func_cap->max_eq = size & 0xFFFFFF; |
| 530 | |
| 531 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_RESERVED_EQ_OFFSET); |
| 532 | func_cap->reserved_eq = size & 0xFFFFFF; |
| 533 | |
Jack Morgenstein | f0ce061 | 2015-01-27 15:58:00 +0200 | [diff] [blame] | 534 | if (func_cap->flags & QUERY_FUNC_CAP_FLAG_RESD_LKEY) { |
| 535 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP_RESD_LKEY_OFFSET); |
| 536 | func_cap->reserved_lkey = size; |
| 537 | } else { |
| 538 | func_cap->reserved_lkey = 0; |
| 539 | } |
| 540 | |
Eugenia Emantayev | ddae034 | 2014-12-11 10:57:54 +0200 | [diff] [blame] | 541 | func_cap->extra_flags = 0; |
| 542 | |
| 543 | /* Mailbox data from 0x6c and onward should only be treated if |
| 544 | * QUERY_FUNC_CAP_FLAG_VALID_MAILBOX is set in func_cap->flags |
| 545 | */ |
| 546 | if (func_cap->flags & QUERY_FUNC_CAP_FLAG_VALID_MAILBOX) { |
| 547 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_EXTRA_FLAGS_OFFSET); |
| 548 | if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_BF_QP_ALLOC_FLAG) |
| 549 | func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_BF_RES_QP; |
Matan Barak | d57febe | 2014-12-11 10:57:57 +0200 | [diff] [blame] | 550 | if (size & QUERY_FUNC_CAP_EXTRA_FLAGS_A0_QP_ALLOC_FLAG) |
| 551 | func_cap->extra_flags |= MLX4_QUERY_FUNC_FLAGS_A0_RES_QP; |
Eugenia Emantayev | ddae034 | 2014-12-11 10:57:54 +0200 | [diff] [blame] | 552 | } |
| 553 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 554 | goto out; |
| 555 | } |
| 556 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 557 | /* logical port query */ |
| 558 | if (gen_or_port > dev->caps.num_ports) { |
| 559 | err = -EINVAL; |
| 560 | goto out; |
| 561 | } |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 562 | |
Hadar Hen Zion | eb17711 | 2013-12-19 21:20:11 +0200 | [diff] [blame] | 563 | MLX4_GET(func_cap->flags1, outbox, QUERY_FUNC_CAP_FLAGS1_OFFSET); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 564 | if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_ETH) { |
Jack Morgenstein | bc82878 | 2014-05-29 16:31:00 +0300 | [diff] [blame] | 565 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_VLAN) { |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 566 | mlx4_err(dev, "VLAN is enforced on this port\n"); |
| 567 | err = -EPROTONOSUPPORT; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 568 | goto out; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 569 | } |
| 570 | |
Hadar Hen Zion | eb17711 | 2013-12-19 21:20:11 +0200 | [diff] [blame] | 571 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_FORCE_MAC) { |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 572 | mlx4_err(dev, "Force mac is enabled on this port\n"); |
| 573 | err = -EPROTONOSUPPORT; |
| 574 | goto out; |
| 575 | } |
| 576 | } else if (dev->caps.port_type[gen_or_port] == MLX4_PORT_TYPE_IB) { |
Hadar Hen Zion | 73e74ab | 2013-12-19 21:20:10 +0200 | [diff] [blame] | 577 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); |
| 578 | if (field & QUERY_FUNC_CAP_FLAGS0_FORCE_PHY_WQE_GID) { |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 579 | mlx4_err(dev, "phy_wqe_gid is enforced on this ib port\n"); |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 580 | err = -EPROTONOSUPPORT; |
| 581 | goto out; |
| 582 | } |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 583 | } |
| 584 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 585 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_PHYS_PORT_OFFSET); |
| 586 | func_cap->physical_port = field; |
| 587 | if (func_cap->physical_port != gen_or_port) { |
| 588 | err = -ENOSYS; |
| 589 | goto out; |
| 590 | } |
| 591 | |
Jack Morgenstein | 99ec41d | 2014-05-29 16:31:03 +0300 | [diff] [blame] | 592 | if (func_cap->flags1 & QUERY_FUNC_CAP_VF_ENABLE_QP0) { |
| 593 | MLX4_GET(qkey, outbox, QUERY_FUNC_CAP_PRIV_VF_QKEY_OFFSET); |
| 594 | func_cap->qp0_qkey = qkey; |
| 595 | } else { |
| 596 | func_cap->qp0_qkey = 0; |
| 597 | } |
| 598 | |
Jack Morgenstein | 47605df | 2012-08-03 08:40:57 +0000 | [diff] [blame] | 599 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_TUNNEL); |
| 600 | func_cap->qp0_tunnel_qpn = size & 0xFFFFFF; |
| 601 | |
| 602 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP0_PROXY); |
| 603 | func_cap->qp0_proxy_qpn = size & 0xFFFFFF; |
| 604 | |
| 605 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_TUNNEL); |
| 606 | func_cap->qp1_tunnel_qpn = size & 0xFFFFFF; |
| 607 | |
| 608 | MLX4_GET(size, outbox, QUERY_FUNC_CAP_QP1_PROXY); |
| 609 | func_cap->qp1_proxy_qpn = size & 0xFFFFFF; |
| 610 | |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 611 | if (func_cap->flags1 & QUERY_FUNC_CAP_FLAGS1_NIC_INFO) |
| 612 | MLX4_GET(func_cap->phys_port_id, outbox, |
| 613 | QUERY_FUNC_CAP_PHYS_PORT_ID); |
| 614 | |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 615 | MLX4_GET(field, outbox, QUERY_FUNC_CAP_FLAGS0_OFFSET); |
| 616 | func_cap->flags |= (field & QUERY_FUNC_CAP_PHV_BIT); |
| 617 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 618 | /* All other resources are allocated by the master, but we still report |
| 619 | * 'num' and 'reserved' capabilities as follows: |
| 620 | * - num remains the maximum resource index |
| 621 | * - 'num - reserved' is the total available objects of a resource, but |
| 622 | * resource indices may be less than 'reserved' |
| 623 | * TODO: set per-resource quotas */ |
| 624 | |
| 625 | out: |
| 626 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 627 | |
| 628 | return err; |
| 629 | } |
| 630 | |
Moni Shoua | d8ae914 | 2016-01-14 17:50:32 +0200 | [diff] [blame] | 631 | static void disable_unsupported_roce_caps(void *buf); |
| 632 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 633 | int mlx4_QUERY_DEV_CAP(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
| 634 | { |
| 635 | struct mlx4_cmd_mailbox *mailbox; |
| 636 | u32 *outbox; |
| 637 | u8 field; |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 638 | u32 field32, flags, ext_flags; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 639 | u16 size; |
| 640 | u16 stat_rate; |
| 641 | int err; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 642 | int i; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 643 | |
| 644 | #define QUERY_DEV_CAP_OUT_SIZE 0x100 |
| 645 | #define QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET 0x10 |
| 646 | #define QUERY_DEV_CAP_MAX_QP_SZ_OFFSET 0x11 |
| 647 | #define QUERY_DEV_CAP_RSVD_QP_OFFSET 0x12 |
| 648 | #define QUERY_DEV_CAP_MAX_QP_OFFSET 0x13 |
| 649 | #define QUERY_DEV_CAP_RSVD_SRQ_OFFSET 0x14 |
| 650 | #define QUERY_DEV_CAP_MAX_SRQ_OFFSET 0x15 |
| 651 | #define QUERY_DEV_CAP_RSVD_EEC_OFFSET 0x16 |
| 652 | #define QUERY_DEV_CAP_MAX_EEC_OFFSET 0x17 |
| 653 | #define QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET 0x19 |
| 654 | #define QUERY_DEV_CAP_RSVD_CQ_OFFSET 0x1a |
| 655 | #define QUERY_DEV_CAP_MAX_CQ_OFFSET 0x1b |
| 656 | #define QUERY_DEV_CAP_MAX_MPT_OFFSET 0x1d |
| 657 | #define QUERY_DEV_CAP_RSVD_EQ_OFFSET 0x1e |
| 658 | #define QUERY_DEV_CAP_MAX_EQ_OFFSET 0x1f |
| 659 | #define QUERY_DEV_CAP_RSVD_MTT_OFFSET 0x20 |
| 660 | #define QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET 0x21 |
| 661 | #define QUERY_DEV_CAP_RSVD_MRW_OFFSET 0x22 |
| 662 | #define QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET 0x23 |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 663 | #define QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET 0x26 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 664 | #define QUERY_DEV_CAP_MAX_AV_OFFSET 0x27 |
| 665 | #define QUERY_DEV_CAP_MAX_REQ_QP_OFFSET 0x29 |
| 666 | #define QUERY_DEV_CAP_MAX_RES_QP_OFFSET 0x2b |
Eli Cohen | b832be1 | 2008-04-16 21:09:27 -0700 | [diff] [blame] | 667 | #define QUERY_DEV_CAP_MAX_GSO_OFFSET 0x2d |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 668 | #define QUERY_DEV_CAP_RSS_OFFSET 0x2e |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 669 | #define QUERY_DEV_CAP_MAX_RDMA_OFFSET 0x2f |
| 670 | #define QUERY_DEV_CAP_RSZ_SRQ_OFFSET 0x33 |
Ido Shamay | 51af33c | 2015-04-02 16:31:20 +0300 | [diff] [blame] | 671 | #define QUERY_DEV_CAP_PORT_BEACON_OFFSET 0x34 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 672 | #define QUERY_DEV_CAP_ACK_DELAY_OFFSET 0x35 |
| 673 | #define QUERY_DEV_CAP_MTU_WIDTH_OFFSET 0x36 |
| 674 | #define QUERY_DEV_CAP_VL_PORT_OFFSET 0x37 |
Dotan Barak | 149983af | 2007-06-26 15:55:28 +0300 | [diff] [blame] | 675 | #define QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET 0x38 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 676 | #define QUERY_DEV_CAP_MAX_GID_OFFSET 0x3b |
| 677 | #define QUERY_DEV_CAP_RATE_SUPPORT_OFFSET 0x3c |
Eugenia Emantayev | d998735 | 2013-04-23 06:06:47 +0000 | [diff] [blame] | 678 | #define QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET 0x3e |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 679 | #define QUERY_DEV_CAP_MAX_PKEY_OFFSET 0x3f |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 680 | #define QUERY_DEV_CAP_EXT_FLAGS_OFFSET 0x40 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 681 | #define QUERY_DEV_CAP_FLAGS_OFFSET 0x44 |
| 682 | #define QUERY_DEV_CAP_RSVD_UAR_OFFSET 0x48 |
| 683 | #define QUERY_DEV_CAP_UAR_SZ_OFFSET 0x49 |
| 684 | #define QUERY_DEV_CAP_PAGE_SZ_OFFSET 0x4b |
| 685 | #define QUERY_DEV_CAP_BF_OFFSET 0x4c |
| 686 | #define QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET 0x4d |
| 687 | #define QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET 0x4e |
| 688 | #define QUERY_DEV_CAP_LOG_MAX_BF_PAGES_OFFSET 0x4f |
| 689 | #define QUERY_DEV_CAP_MAX_SG_SQ_OFFSET 0x51 |
| 690 | #define QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET 0x52 |
| 691 | #define QUERY_DEV_CAP_MAX_SG_RQ_OFFSET 0x55 |
| 692 | #define QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET 0x56 |
| 693 | #define QUERY_DEV_CAP_MAX_QP_MCG_OFFSET 0x61 |
| 694 | #define QUERY_DEV_CAP_RSVD_MCG_OFFSET 0x62 |
| 695 | #define QUERY_DEV_CAP_MAX_MCG_OFFSET 0x63 |
| 696 | #define QUERY_DEV_CAP_RSVD_PD_OFFSET 0x64 |
| 697 | #define QUERY_DEV_CAP_MAX_PD_OFFSET 0x65 |
Linus Torvalds | f470f8d | 2011-11-01 10:51:38 -0700 | [diff] [blame] | 698 | #define QUERY_DEV_CAP_RSVD_XRC_OFFSET 0x66 |
| 699 | #define QUERY_DEV_CAP_MAX_XRC_OFFSET 0x67 |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 700 | #define QUERY_DEV_CAP_MAX_COUNTERS_OFFSET 0x68 |
Matan Barak | 0b13156 | 2015-03-30 17:45:25 +0300 | [diff] [blame] | 701 | #define QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET 0x70 |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 702 | #define QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET 0x70 |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 703 | #define QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET 0x74 |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 704 | #define QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET 0x76 |
| 705 | #define QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET 0x77 |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 706 | #define QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE 0x7a |
Shani Michaeli | d237baa | 2015-03-05 20:16:12 +0200 | [diff] [blame] | 707 | #define QUERY_DEV_CAP_ECN_QCN_VER_OFFSET 0x7b |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 708 | #define QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET 0x80 |
| 709 | #define QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET 0x82 |
| 710 | #define QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET 0x84 |
| 711 | #define QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET 0x86 |
| 712 | #define QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET 0x88 |
| 713 | #define QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET 0x8a |
| 714 | #define QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET 0x8c |
| 715 | #define QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET 0x8e |
| 716 | #define QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET 0x90 |
| 717 | #define QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET 0x92 |
Roland Dreier | 95d04f0 | 2008-07-23 08:12:26 -0700 | [diff] [blame] | 718 | #define QUERY_DEV_CAP_BMME_FLAGS_OFFSET 0x94 |
Matan Barak | d475c95 | 2014-11-02 16:26:17 +0200 | [diff] [blame] | 719 | #define QUERY_DEV_CAP_CONFIG_DEV_OFFSET 0x94 |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 720 | #define QUERY_DEV_CAP_PHV_EN_OFFSET 0x96 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 721 | #define QUERY_DEV_CAP_RSVD_LKEY_OFFSET 0x98 |
| 722 | #define QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET 0xa0 |
Saeed Mahameed | a53e3e8 | 2014-10-27 11:37:38 +0200 | [diff] [blame] | 723 | #define QUERY_DEV_CAP_ETH_BACKPL_OFFSET 0x9c |
Mark Bloch | c7c122e | 2016-07-19 20:54:56 +0300 | [diff] [blame] | 724 | #define QUERY_DEV_CAP_DIAG_RPRT_PER_PORT 0x9c |
Matan Barak | 955154f | 2013-01-30 23:07:10 +0000 | [diff] [blame] | 725 | #define QUERY_DEV_CAP_FW_REASSIGN_MAC 0x9d |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 726 | #define QUERY_DEV_CAP_VXLAN 0x9e |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 727 | #define QUERY_DEV_CAP_MAD_DEMUX_OFFSET 0xb0 |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 728 | #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET 0xa8 |
| 729 | #define QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET 0xac |
Or Gerlitz | fc31e25 | 2015-03-18 14:57:34 +0200 | [diff] [blame] | 730 | #define QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET 0xcc |
| 731 | #define QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET 0xd0 |
| 732 | #define QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET 0xd2 |
| 733 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 734 | |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 735 | dev_cap->flags2 = 0; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 736 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 737 | if (IS_ERR(mailbox)) |
| 738 | return PTR_ERR(mailbox); |
| 739 | outbox = mailbox->buf; |
| 740 | |
| 741 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
Jack Morgenstein | 401453a | 2012-05-30 09:14:55 +0000 | [diff] [blame] | 742 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 743 | if (err) |
| 744 | goto out; |
| 745 | |
Moni Shoua | d8ae914 | 2016-01-14 17:50:32 +0200 | [diff] [blame] | 746 | if (mlx4_is_mfunc(dev)) |
| 747 | disable_unsupported_roce_caps(outbox); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 748 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_QP_OFFSET); |
| 749 | dev_cap->reserved_qps = 1 << (field & 0xf); |
| 750 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_OFFSET); |
| 751 | dev_cap->max_qps = 1 << (field & 0x1f); |
| 752 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_SRQ_OFFSET); |
| 753 | dev_cap->reserved_srqs = 1 << (field >> 4); |
| 754 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_OFFSET); |
| 755 | dev_cap->max_srqs = 1 << (field & 0x1f); |
| 756 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_SZ_OFFSET); |
| 757 | dev_cap->max_cq_sz = 1 << field; |
| 758 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_CQ_OFFSET); |
| 759 | dev_cap->reserved_cqs = 1 << (field & 0xf); |
| 760 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_CQ_OFFSET); |
| 761 | dev_cap->max_cqs = 1 << (field & 0x1f); |
| 762 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MPT_OFFSET); |
| 763 | dev_cap->max_mpts = 1 << (field & 0x3f); |
| 764 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_EQ_OFFSET); |
Matan Barak | 7c68dd4 | 2014-11-13 14:45:27 +0200 | [diff] [blame] | 765 | dev_cap->reserved_eqs = 1 << (field & 0xf); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 766 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_EQ_OFFSET); |
Jack Morgenstein | 5920869 | 2007-12-10 05:25:23 +0200 | [diff] [blame] | 767 | dev_cap->max_eqs = 1 << (field & 0xf); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 768 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MTT_OFFSET); |
| 769 | dev_cap->reserved_mtts = 1 << (field >> 4); |
| 770 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MRW_SZ_OFFSET); |
| 771 | dev_cap->max_mrw_sz = 1 << field; |
| 772 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MRW_OFFSET); |
| 773 | dev_cap->reserved_mrws = 1 << (field & 0xf); |
| 774 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MTT_SEG_OFFSET); |
| 775 | dev_cap->max_mtt_seg = 1 << (field & 0x3f); |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 776 | MLX4_GET(size, outbox, QUERY_DEV_CAP_NUM_SYS_EQ_OFFSET); |
| 777 | dev_cap->num_sys_eqs = size & 0xfff; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 778 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_REQ_QP_OFFSET); |
| 779 | dev_cap->max_requester_per_qp = 1 << (field & 0x3f); |
| 780 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RES_QP_OFFSET); |
| 781 | dev_cap->max_responder_per_qp = 1 << (field & 0x3f); |
Eli Cohen | b832be1 | 2008-04-16 21:09:27 -0700 | [diff] [blame] | 782 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GSO_OFFSET); |
| 783 | field &= 0x1f; |
| 784 | if (!field) |
| 785 | dev_cap->max_gso_sz = 0; |
| 786 | else |
| 787 | dev_cap->max_gso_sz = 1 << field; |
| 788 | |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 789 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSS_OFFSET); |
| 790 | if (field & 0x20) |
| 791 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_XOR; |
| 792 | if (field & 0x10) |
| 793 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS_TOP; |
| 794 | field &= 0xf; |
| 795 | if (field) { |
| 796 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RSS; |
| 797 | dev_cap->max_rss_tbl_sz = 1 << field; |
| 798 | } else |
| 799 | dev_cap->max_rss_tbl_sz = 0; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 800 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_RDMA_OFFSET); |
| 801 | dev_cap->max_rdma_global = 1 << (field & 0x3f); |
| 802 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ACK_DELAY_OFFSET); |
| 803 | dev_cap->local_ca_ack_delay = field & 0x1f; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 804 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 805 | dev_cap->num_ports = field & 0xf; |
Dotan Barak | 149983af | 2007-06-26 15:55:28 +0300 | [diff] [blame] | 806 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MSG_SZ_OFFSET); |
Eran Ben Elisha | fab9adf | 2015-04-21 15:46:34 +0300 | [diff] [blame] | 807 | dev_cap->max_msg_sz = 1 << (field & 0x1f); |
Matan Barak | 0b13156 | 2015-03-30 17:45:25 +0300 | [diff] [blame] | 808 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_FLOWSTATS_COUNTERS_OFFSET); |
| 809 | if (field & 0x10) |
| 810 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FLOWSTATS_EN; |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 811 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 812 | if (field & 0x80) |
| 813 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FS_EN; |
| 814 | dev_cap->fs_log_max_ucast_qp_range_size = field & 0x1f; |
Marina Varshaver | 0e451e8 | 2016-02-18 18:31:06 +0200 | [diff] [blame] | 815 | if (field & 0x20) |
| 816 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_UC_MC_SNIFFER; |
Ido Shamay | 51af33c | 2015-04-02 16:31:20 +0300 | [diff] [blame] | 817 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PORT_BEACON_OFFSET); |
| 818 | if (field & 0x80) |
| 819 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_BEACON; |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 820 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
| 821 | if (field & 0x80) |
| 822 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DMFS_IPOIB; |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 823 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FLOW_STEERING_MAX_QP_OFFSET); |
| 824 | dev_cap->fs_max_num_qp_per_entry = field; |
Shani Michaeli | d237baa | 2015-03-05 20:16:12 +0200 | [diff] [blame] | 825 | MLX4_GET(field, outbox, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); |
| 826 | if (field & 0x1) |
| 827 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QCN; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 828 | MLX4_GET(stat_rate, outbox, QUERY_DEV_CAP_RATE_SUPPORT_OFFSET); |
| 829 | dev_cap->stat_rate_support = stat_rate; |
Eugenia Emantayev | d998735 | 2013-04-23 06:06:47 +0000 | [diff] [blame] | 830 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 831 | if (field & 0x80) |
| 832 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_TS; |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 833 | MLX4_GET(ext_flags, outbox, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
Or Gerlitz | 52eafc6 | 2011-06-15 14:41:42 +0000 | [diff] [blame] | 834 | MLX4_GET(flags, outbox, QUERY_DEV_CAP_FLAGS_OFFSET); |
Or Gerlitz | ccf8632 | 2011-07-07 19:19:29 +0000 | [diff] [blame] | 835 | dev_cap->flags = flags | (u64)ext_flags << 32; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 836 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_UAR_OFFSET); |
| 837 | dev_cap->reserved_uars = field >> 4; |
| 838 | MLX4_GET(field, outbox, QUERY_DEV_CAP_UAR_SZ_OFFSET); |
| 839 | dev_cap->uar_size = 1 << ((field & 0x3f) + 20); |
| 840 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PAGE_SZ_OFFSET); |
| 841 | dev_cap->min_page_sz = 1 << field; |
| 842 | |
| 843 | MLX4_GET(field, outbox, QUERY_DEV_CAP_BF_OFFSET); |
| 844 | if (field & 0x80) { |
| 845 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_BF_REG_SZ_OFFSET); |
| 846 | dev_cap->bf_reg_size = 1 << (field & 0x1f); |
| 847 | MLX4_GET(field, outbox, QUERY_DEV_CAP_LOG_MAX_BF_REGS_PER_PAGE_OFFSET); |
Roland Dreier | f5a4953 | 2011-01-10 17:42:05 -0800 | [diff] [blame] | 848 | if ((1 << (field & 0x3f)) > (PAGE_SIZE / dev_cap->bf_reg_size)) |
Eli Cohen | 58d74bb | 2010-11-10 12:52:37 +0000 | [diff] [blame] | 849 | field = 3; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 850 | dev_cap->bf_regs_per_page = 1 << (field & 0x3f); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 851 | } else { |
| 852 | dev_cap->bf_reg_size = 0; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 853 | } |
| 854 | |
| 855 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_SQ_OFFSET); |
| 856 | dev_cap->max_sq_sg = field; |
| 857 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_SQ_OFFSET); |
| 858 | dev_cap->max_sq_desc_sz = size; |
| 859 | |
| 860 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_MCG_OFFSET); |
| 861 | dev_cap->max_qp_per_mcg = 1 << field; |
| 862 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_MCG_OFFSET); |
| 863 | dev_cap->reserved_mgms = field & 0xf; |
| 864 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_MCG_OFFSET); |
| 865 | dev_cap->max_mcgs = 1 << field; |
| 866 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_PD_OFFSET); |
| 867 | dev_cap->reserved_pds = field >> 4; |
| 868 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PD_OFFSET); |
| 869 | dev_cap->max_pds = 1 << (field & 0x3f); |
Linus Torvalds | f470f8d | 2011-11-01 10:51:38 -0700 | [diff] [blame] | 870 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSVD_XRC_OFFSET); |
| 871 | dev_cap->reserved_xrcds = field >> 4; |
Dotan Barak | 426dd00 | 2012-08-23 14:09:04 +0000 | [diff] [blame] | 872 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_XRC_OFFSET); |
Linus Torvalds | f470f8d | 2011-11-01 10:51:38 -0700 | [diff] [blame] | 873 | dev_cap->max_xrcds = 1 << (field & 0x1f); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 874 | |
| 875 | MLX4_GET(size, outbox, QUERY_DEV_CAP_RDMARC_ENTRY_SZ_OFFSET); |
| 876 | dev_cap->rdmarc_entry_sz = size; |
| 877 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QPC_ENTRY_SZ_OFFSET); |
| 878 | dev_cap->qpc_entry_sz = size; |
| 879 | MLX4_GET(size, outbox, QUERY_DEV_CAP_AUX_ENTRY_SZ_OFFSET); |
| 880 | dev_cap->aux_entry_sz = size; |
| 881 | MLX4_GET(size, outbox, QUERY_DEV_CAP_ALTC_ENTRY_SZ_OFFSET); |
| 882 | dev_cap->altc_entry_sz = size; |
| 883 | MLX4_GET(size, outbox, QUERY_DEV_CAP_EQC_ENTRY_SZ_OFFSET); |
| 884 | dev_cap->eqc_entry_sz = size; |
| 885 | MLX4_GET(size, outbox, QUERY_DEV_CAP_CQC_ENTRY_SZ_OFFSET); |
| 886 | dev_cap->cqc_entry_sz = size; |
| 887 | MLX4_GET(size, outbox, QUERY_DEV_CAP_SRQ_ENTRY_SZ_OFFSET); |
| 888 | dev_cap->srq_entry_sz = size; |
| 889 | MLX4_GET(size, outbox, QUERY_DEV_CAP_C_MPT_ENTRY_SZ_OFFSET); |
| 890 | dev_cap->cmpt_entry_sz = size; |
| 891 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MTT_ENTRY_SZ_OFFSET); |
| 892 | dev_cap->mtt_entry_sz = size; |
| 893 | MLX4_GET(size, outbox, QUERY_DEV_CAP_D_MPT_ENTRY_SZ_OFFSET); |
| 894 | dev_cap->dmpt_entry_sz = size; |
| 895 | |
| 896 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SRQ_SZ_OFFSET); |
| 897 | dev_cap->max_srq_sz = 1 << field; |
| 898 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_QP_SZ_OFFSET); |
| 899 | dev_cap->max_qp_sz = 1 << field; |
| 900 | MLX4_GET(field, outbox, QUERY_DEV_CAP_RSZ_SRQ_OFFSET); |
| 901 | dev_cap->resize_srq = field & 1; |
| 902 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_SG_RQ_OFFSET); |
| 903 | dev_cap->max_rq_sg = field; |
| 904 | MLX4_GET(size, outbox, QUERY_DEV_CAP_MAX_DESC_SZ_RQ_OFFSET); |
| 905 | dev_cap->max_rq_desc_sz = size; |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 906 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); |
Ido Shamay | d019fcb | 2015-04-02 16:31:13 +0300 | [diff] [blame] | 907 | if (field & (1 << 4)) |
| 908 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QOS_VPP; |
Saeed Mahameed | adbc7ac | 2014-10-27 11:37:37 +0200 | [diff] [blame] | 909 | if (field & (1 << 5)) |
| 910 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_PROT_CTRL; |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 911 | if (field & (1 << 6)) |
| 912 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CQE_STRIDE; |
| 913 | if (field & (1 << 7)) |
| 914 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_EQE_STRIDE; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 915 | MLX4_GET(dev_cap->bmme_flags, outbox, |
| 916 | QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
Moni Shoua | d8ae914 | 2016-01-14 17:50:32 +0200 | [diff] [blame] | 917 | if (dev_cap->bmme_flags & MLX4_FLAG_ROCE_V1_V2) |
| 918 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ROCE_V1_V2; |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 919 | if (dev_cap->bmme_flags & MLX4_FLAG_PORT_REMAP) |
| 920 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PORT_REMAP; |
Matan Barak | d475c95 | 2014-11-02 16:26:17 +0200 | [diff] [blame] | 921 | MLX4_GET(field, outbox, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); |
| 922 | if (field & 0x20) |
| 923 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_CONFIG_DEV; |
Muhammad Mahajna | 78500b8 | 2015-04-02 16:31:22 +0300 | [diff] [blame] | 924 | if (field & (1 << 2)) |
| 925 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_IGNORE_FCS; |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 926 | MLX4_GET(field, outbox, QUERY_DEV_CAP_PHV_EN_OFFSET); |
| 927 | if (field & 0x80) |
| 928 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_PHV_EN; |
| 929 | if (field & 0x40) |
| 930 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN; |
| 931 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 932 | MLX4_GET(dev_cap->reserved_lkey, outbox, |
| 933 | QUERY_DEV_CAP_RSVD_LKEY_OFFSET); |
Saeed Mahameed | a53e3e8 | 2014-10-27 11:37:38 +0200 | [diff] [blame] | 934 | MLX4_GET(field32, outbox, QUERY_DEV_CAP_ETH_BACKPL_OFFSET); |
| 935 | if (field32 & (1 << 0)) |
| 936 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETH_BACKPL_AN_REP; |
Jack Morgenstein | be6a6b4 | 2015-01-27 15:57:59 +0200 | [diff] [blame] | 937 | if (field32 & (1 << 7)) |
| 938 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT; |
Mark Bloch | c7c122e | 2016-07-19 20:54:56 +0300 | [diff] [blame] | 939 | MLX4_GET(field32, outbox, QUERY_DEV_CAP_DIAG_RPRT_PER_PORT); |
| 940 | if (field32 & (1 << 17)) |
| 941 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_DIAG_PER_PORT; |
Matan Barak | 955154f | 2013-01-30 23:07:10 +0000 | [diff] [blame] | 942 | MLX4_GET(field, outbox, QUERY_DEV_CAP_FW_REASSIGN_MAC); |
| 943 | if (field & 1<<6) |
Or Gerlitz | 5930e8d | 2013-10-15 16:55:22 +0200 | [diff] [blame] | 944 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_REASSIGN_MAC_EN; |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 945 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VXLAN); |
| 946 | if (field & 1<<3) |
| 947 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS; |
Ido Shamay | 3742cc6 | 2015-04-02 16:31:17 +0300 | [diff] [blame] | 948 | if (field & (1 << 5)) |
| 949 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_ETS_CFG; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 950 | MLX4_GET(dev_cap->max_icm_sz, outbox, |
| 951 | QUERY_DEV_CAP_MAX_ICM_SZ_OFFSET); |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 952 | if (dev_cap->flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
| 953 | MLX4_GET(dev_cap->max_counters, outbox, |
| 954 | QUERY_DEV_CAP_MAX_COUNTERS_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 955 | |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 956 | MLX4_GET(field32, outbox, |
| 957 | QUERY_DEV_CAP_MAD_DEMUX_OFFSET); |
| 958 | if (field32 & (1 << 0)) |
| 959 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_MAD_DEMUX; |
| 960 | |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 961 | MLX4_GET(dev_cap->dmfs_high_rate_qpn_base, outbox, |
| 962 | QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_BASE_OFFSET); |
| 963 | dev_cap->dmfs_high_rate_qpn_base &= MGM_QPN_MASK; |
| 964 | MLX4_GET(dev_cap->dmfs_high_rate_qpn_range, outbox, |
| 965 | QUERY_DEV_CAP_DMFS_HIGH_RATE_QPN_RANGE_OFFSET); |
| 966 | dev_cap->dmfs_high_rate_qpn_range &= MGM_QPN_MASK; |
| 967 | |
Or Gerlitz | fc31e25 | 2015-03-18 14:57:34 +0200 | [diff] [blame] | 968 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); |
| 969 | dev_cap->rl_caps.num_rates = size; |
| 970 | if (dev_cap->rl_caps.num_rates) { |
| 971 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT; |
| 972 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MAX_OFFSET); |
| 973 | dev_cap->rl_caps.max_val = size & 0xfff; |
| 974 | dev_cap->rl_caps.max_unit = size >> 14; |
| 975 | MLX4_GET(size, outbox, QUERY_DEV_CAP_QP_RATE_LIMIT_MIN_OFFSET); |
| 976 | dev_cap->rl_caps.min_val = size & 0xfff; |
| 977 | dev_cap->rl_caps.min_unit = size >> 14; |
| 978 | } |
| 979 | |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 980 | MLX4_GET(field32, outbox, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
Jack Morgenstein | b01978c | 2013-06-27 19:05:21 +0300 | [diff] [blame] | 981 | if (field32 & (1 << 16)) |
| 982 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP; |
Maor Gottlieb | 9a89283 | 2015-10-15 14:44:38 +0300 | [diff] [blame] | 983 | if (field32 & (1 << 18)) |
| 984 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_UPDATE_QP_SRC_CHECK_LB; |
| 985 | if (field32 & (1 << 19)) |
| 986 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_LB_SRC_CHK; |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 987 | if (field32 & (1 << 26)) |
| 988 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_VLAN_CONTROL; |
Rony Efraim | e6b6a23 | 2013-04-25 05:22:29 +0000 | [diff] [blame] | 989 | if (field32 & (1 << 20)) |
| 990 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_FSM; |
Matan Barak | de966c5 | 2014-11-13 14:45:33 +0200 | [diff] [blame] | 991 | if (field32 & (1 << 21)) |
| 992 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_80_VFS; |
Rony Efraim | 3f7fb02 | 2013-04-25 05:22:28 +0000 | [diff] [blame] | 993 | |
Matan Barak | 431df8c | 2014-12-11 10:57:59 +0200 | [diff] [blame] | 994 | for (i = 1; i <= dev_cap->num_ports; i++) { |
| 995 | err = mlx4_QUERY_PORT(dev, i, dev_cap->port_cap + i); |
| 996 | if (err) |
| 997 | goto out; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 998 | } |
| 999 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1000 | /* |
| 1001 | * Each UAR has 4 EQ doorbells; so if a UAR is reserved, then |
| 1002 | * we can't use any EQs whose doorbell falls on that page, |
| 1003 | * even if the EQ itself isn't reserved. |
| 1004 | */ |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 1005 | if (dev_cap->num_sys_eqs == 0) |
| 1006 | dev_cap->reserved_eqs = max(dev_cap->reserved_uars * 4, |
| 1007 | dev_cap->reserved_eqs); |
| 1008 | else |
| 1009 | dev_cap->flags2 |= MLX4_DEV_CAP_FLAG2_SYS_EQS; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1010 | |
Or Gerlitz | c78e25e | 2014-12-14 16:18:05 +0200 | [diff] [blame] | 1011 | out: |
| 1012 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1013 | return err; |
| 1014 | } |
| 1015 | |
| 1016 | void mlx4_dev_cap_dump(struct mlx4_dev *dev, struct mlx4_dev_cap *dev_cap) |
| 1017 | { |
| 1018 | if (dev_cap->bf_reg_size > 0) |
| 1019 | mlx4_dbg(dev, "BlueFlame available (reg size %d, regs/page %d)\n", |
| 1020 | dev_cap->bf_reg_size, dev_cap->bf_regs_per_page); |
| 1021 | else |
| 1022 | mlx4_dbg(dev, "BlueFlame not available\n"); |
| 1023 | |
| 1024 | mlx4_dbg(dev, "Base MM extensions: flags %08x, rsvd L_Key %08x\n", |
| 1025 | dev_cap->bmme_flags, dev_cap->reserved_lkey); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1026 | mlx4_dbg(dev, "Max ICM size %lld MB\n", |
| 1027 | (unsigned long long) dev_cap->max_icm_sz >> 20); |
| 1028 | mlx4_dbg(dev, "Max QPs: %d, reserved QPs: %d, entry size: %d\n", |
| 1029 | dev_cap->max_qps, dev_cap->reserved_qps, dev_cap->qpc_entry_sz); |
| 1030 | mlx4_dbg(dev, "Max SRQs: %d, reserved SRQs: %d, entry size: %d\n", |
| 1031 | dev_cap->max_srqs, dev_cap->reserved_srqs, dev_cap->srq_entry_sz); |
| 1032 | mlx4_dbg(dev, "Max CQs: %d, reserved CQs: %d, entry size: %d\n", |
| 1033 | dev_cap->max_cqs, dev_cap->reserved_cqs, dev_cap->cqc_entry_sz); |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 1034 | mlx4_dbg(dev, "Num sys EQs: %d, max EQs: %d, reserved EQs: %d, entry size: %d\n", |
| 1035 | dev_cap->num_sys_eqs, dev_cap->max_eqs, dev_cap->reserved_eqs, |
| 1036 | dev_cap->eqc_entry_sz); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1037 | mlx4_dbg(dev, "reserved MPTs: %d, reserved MTTs: %d\n", |
| 1038 | dev_cap->reserved_mrws, dev_cap->reserved_mtts); |
| 1039 | mlx4_dbg(dev, "Max PDs: %d, reserved PDs: %d, reserved UARs: %d\n", |
| 1040 | dev_cap->max_pds, dev_cap->reserved_pds, dev_cap->reserved_uars); |
| 1041 | mlx4_dbg(dev, "Max QP/MCG: %d, reserved MGMs: %d\n", |
| 1042 | dev_cap->max_pds, dev_cap->reserved_mgms); |
| 1043 | mlx4_dbg(dev, "Max CQEs: %d, max WQEs: %d, max SRQ WQEs: %d\n", |
| 1044 | dev_cap->max_cq_sz, dev_cap->max_qp_sz, dev_cap->max_srq_sz); |
| 1045 | mlx4_dbg(dev, "Local CA ACK delay: %d, max MTU: %d, port width cap: %d\n", |
Matan Barak | 431df8c | 2014-12-11 10:57:59 +0200 | [diff] [blame] | 1046 | dev_cap->local_ca_ack_delay, 128 << dev_cap->port_cap[1].ib_mtu, |
| 1047 | dev_cap->port_cap[1].max_port_width); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1048 | mlx4_dbg(dev, "Max SQ desc size: %d, max SQ S/G: %d\n", |
| 1049 | dev_cap->max_sq_desc_sz, dev_cap->max_sq_sg); |
| 1050 | mlx4_dbg(dev, "Max RQ desc size: %d, max RQ S/G: %d\n", |
| 1051 | dev_cap->max_rq_desc_sz, dev_cap->max_rq_sg); |
Eli Cohen | b832be1 | 2008-04-16 21:09:27 -0700 | [diff] [blame] | 1052 | mlx4_dbg(dev, "Max GSO size: %d\n", dev_cap->max_gso_sz); |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 1053 | mlx4_dbg(dev, "Max counters: %d\n", dev_cap->max_counters); |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 1054 | mlx4_dbg(dev, "Max RSS Table size: %d\n", dev_cap->max_rss_tbl_sz); |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 1055 | mlx4_dbg(dev, "DMFS high rate steer QPn base: %d\n", |
| 1056 | dev_cap->dmfs_high_rate_qpn_base); |
| 1057 | mlx4_dbg(dev, "DMFS high rate steer QPn range: %d\n", |
| 1058 | dev_cap->dmfs_high_rate_qpn_range); |
Or Gerlitz | fc31e25 | 2015-03-18 14:57:34 +0200 | [diff] [blame] | 1059 | |
| 1060 | if (dev_cap->flags2 & MLX4_DEV_CAP_FLAG2_QP_RATE_LIMIT) { |
| 1061 | struct mlx4_rate_limit_caps *rl_caps = &dev_cap->rl_caps; |
| 1062 | |
| 1063 | mlx4_dbg(dev, "QP Rate-Limit: #rates %d, unit/val max %d/%d, min %d/%d\n", |
| 1064 | rl_caps->num_rates, rl_caps->max_unit, rl_caps->max_val, |
| 1065 | rl_caps->min_unit, rl_caps->min_val); |
| 1066 | } |
| 1067 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1068 | dump_dev_cap_flags(dev, dev_cap->flags); |
Shlomo Pongratz | b3416f4 | 2012-04-29 17:04:25 +0300 | [diff] [blame] | 1069 | dump_dev_cap_flags2(dev, dev_cap->flags2); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1070 | } |
| 1071 | |
Matan Barak | 431df8c | 2014-12-11 10:57:59 +0200 | [diff] [blame] | 1072 | int mlx4_QUERY_PORT(struct mlx4_dev *dev, int port, struct mlx4_port_cap *port_cap) |
| 1073 | { |
| 1074 | struct mlx4_cmd_mailbox *mailbox; |
| 1075 | u32 *outbox; |
| 1076 | u8 field; |
| 1077 | u32 field32; |
| 1078 | int err; |
| 1079 | |
| 1080 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1081 | if (IS_ERR(mailbox)) |
| 1082 | return PTR_ERR(mailbox); |
| 1083 | outbox = mailbox->buf; |
| 1084 | |
| 1085 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
| 1086 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
| 1087 | MLX4_CMD_TIME_CLASS_A, |
| 1088 | MLX4_CMD_NATIVE); |
| 1089 | |
| 1090 | if (err) |
| 1091 | goto out; |
| 1092 | |
| 1093 | MLX4_GET(field, outbox, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 1094 | port_cap->max_vl = field >> 4; |
| 1095 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MTU_WIDTH_OFFSET); |
| 1096 | port_cap->ib_mtu = field >> 4; |
| 1097 | port_cap->max_port_width = field & 0xf; |
| 1098 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_GID_OFFSET); |
| 1099 | port_cap->max_gids = 1 << (field & 0xf); |
| 1100 | MLX4_GET(field, outbox, QUERY_DEV_CAP_MAX_PKEY_OFFSET); |
| 1101 | port_cap->max_pkeys = 1 << (field & 0xf); |
| 1102 | } else { |
| 1103 | #define QUERY_PORT_SUPPORTED_TYPE_OFFSET 0x00 |
| 1104 | #define QUERY_PORT_MTU_OFFSET 0x01 |
| 1105 | #define QUERY_PORT_ETH_MTU_OFFSET 0x02 |
| 1106 | #define QUERY_PORT_WIDTH_OFFSET 0x06 |
| 1107 | #define QUERY_PORT_MAX_GID_PKEY_OFFSET 0x07 |
| 1108 | #define QUERY_PORT_MAX_MACVLAN_OFFSET 0x0a |
| 1109 | #define QUERY_PORT_MAX_VL_OFFSET 0x0b |
| 1110 | #define QUERY_PORT_MAC_OFFSET 0x10 |
| 1111 | #define QUERY_PORT_TRANS_VENDOR_OFFSET 0x18 |
| 1112 | #define QUERY_PORT_WAVELENGTH_OFFSET 0x1c |
| 1113 | #define QUERY_PORT_TRANS_CODE_OFFSET 0x20 |
| 1114 | |
| 1115 | err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, MLX4_CMD_QUERY_PORT, |
| 1116 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 1117 | if (err) |
| 1118 | goto out; |
| 1119 | |
| 1120 | MLX4_GET(field, outbox, QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
Or Gerlitz | e34305c | 2015-12-06 18:07:38 +0200 | [diff] [blame] | 1121 | port_cap->link_state = (field & 0x80) >> 7; |
Matan Barak | 431df8c | 2014-12-11 10:57:59 +0200 | [diff] [blame] | 1122 | port_cap->supported_port_types = field & 3; |
| 1123 | port_cap->suggested_type = (field >> 3) & 1; |
| 1124 | port_cap->default_sense = (field >> 4) & 1; |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 1125 | port_cap->dmfs_optimized_state = (field >> 5) & 1; |
Matan Barak | 431df8c | 2014-12-11 10:57:59 +0200 | [diff] [blame] | 1126 | MLX4_GET(field, outbox, QUERY_PORT_MTU_OFFSET); |
| 1127 | port_cap->ib_mtu = field & 0xf; |
| 1128 | MLX4_GET(field, outbox, QUERY_PORT_WIDTH_OFFSET); |
| 1129 | port_cap->max_port_width = field & 0xf; |
| 1130 | MLX4_GET(field, outbox, QUERY_PORT_MAX_GID_PKEY_OFFSET); |
| 1131 | port_cap->max_gids = 1 << (field >> 4); |
| 1132 | port_cap->max_pkeys = 1 << (field & 0xf); |
| 1133 | MLX4_GET(field, outbox, QUERY_PORT_MAX_VL_OFFSET); |
| 1134 | port_cap->max_vl = field & 0xf; |
Rana Shahout | af7d518 | 2016-06-21 12:43:59 +0300 | [diff] [blame] | 1135 | port_cap->max_tc_eth = field >> 4; |
Matan Barak | 431df8c | 2014-12-11 10:57:59 +0200 | [diff] [blame] | 1136 | MLX4_GET(field, outbox, QUERY_PORT_MAX_MACVLAN_OFFSET); |
| 1137 | port_cap->log_max_macs = field & 0xf; |
| 1138 | port_cap->log_max_vlans = field >> 4; |
| 1139 | MLX4_GET(port_cap->eth_mtu, outbox, QUERY_PORT_ETH_MTU_OFFSET); |
| 1140 | MLX4_GET(port_cap->def_mac, outbox, QUERY_PORT_MAC_OFFSET); |
| 1141 | MLX4_GET(field32, outbox, QUERY_PORT_TRANS_VENDOR_OFFSET); |
| 1142 | port_cap->trans_type = field32 >> 24; |
| 1143 | port_cap->vendor_oui = field32 & 0xffffff; |
| 1144 | MLX4_GET(port_cap->wavelength, outbox, QUERY_PORT_WAVELENGTH_OFFSET); |
| 1145 | MLX4_GET(port_cap->trans_code, outbox, QUERY_PORT_TRANS_CODE_OFFSET); |
| 1146 | } |
| 1147 | |
| 1148 | out: |
| 1149 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1150 | return err; |
| 1151 | } |
| 1152 | |
Matan Barak | 0b13156 | 2015-03-30 17:45:25 +0300 | [diff] [blame] | 1153 | #define DEV_CAP_EXT_2_FLAG_PFC_COUNTERS (1 << 28) |
Or Gerlitz | 383677d | 2014-12-11 10:57:52 +0200 | [diff] [blame] | 1154 | #define DEV_CAP_EXT_2_FLAG_VLAN_CONTROL (1 << 26) |
| 1155 | #define DEV_CAP_EXT_2_FLAG_80_VFS (1 << 21) |
| 1156 | #define DEV_CAP_EXT_2_FLAG_FSM (1 << 20) |
| 1157 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1158 | int mlx4_QUERY_DEV_CAP_wrapper(struct mlx4_dev *dev, int slave, |
| 1159 | struct mlx4_vhcr *vhcr, |
| 1160 | struct mlx4_cmd_mailbox *inbox, |
| 1161 | struct mlx4_cmd_mailbox *outbox, |
| 1162 | struct mlx4_cmd_info *cmd) |
| 1163 | { |
Jack Morgenstein | 2a4fae1 | 2012-08-03 08:40:50 +0000 | [diff] [blame] | 1164 | u64 flags; |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1165 | int err = 0; |
| 1166 | u8 field; |
Or Gerlitz | fc31e25 | 2015-03-18 14:57:34 +0200 | [diff] [blame] | 1167 | u16 field16; |
Or Gerlitz | 383677d | 2014-12-11 10:57:52 +0200 | [diff] [blame] | 1168 | u32 bmme_flags, field32; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1169 | int real_port; |
| 1170 | int slave_port; |
| 1171 | int first_port; |
| 1172 | struct mlx4_active_ports actv_ports; |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1173 | |
| 1174 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_DEV_CAP, |
| 1175 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1176 | if (err) |
| 1177 | return err; |
| 1178 | |
Moni Shoua | d8ae914 | 2016-01-14 17:50:32 +0200 | [diff] [blame] | 1179 | disable_unsupported_roce_caps(outbox->buf); |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 1180 | /* add port mng change event capability and disable mw type 1 |
| 1181 | * unconditionally to slaves |
| 1182 | */ |
Jack Morgenstein | 2a4fae1 | 2012-08-03 08:40:50 +0000 | [diff] [blame] | 1183 | MLX4_GET(flags, outbox->buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 1184 | flags |= MLX4_DEV_CAP_FLAG_PORT_MNG_CHG_EV; |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 1185 | flags &= ~MLX4_DEV_CAP_FLAG_MEM_WINDOW; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1186 | actv_ports = mlx4_get_active_ports(dev, slave); |
| 1187 | first_port = find_first_bit(actv_ports.ports, dev->caps.num_ports); |
| 1188 | for (slave_port = 0, real_port = first_port; |
| 1189 | real_port < first_port + |
| 1190 | bitmap_weight(actv_ports.ports, dev->caps.num_ports); |
| 1191 | ++real_port, ++slave_port) { |
| 1192 | if (flags & (MLX4_DEV_CAP_FLAG_WOL_PORT1 << real_port)) |
| 1193 | flags |= MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port; |
| 1194 | else |
| 1195 | flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); |
| 1196 | } |
| 1197 | for (; slave_port < dev->caps.num_ports; ++slave_port) |
| 1198 | flags &= ~(MLX4_DEV_CAP_FLAG_WOL_PORT1 << slave_port); |
Ido Shamay | 802f42a | 2015-04-02 16:31:06 +0300 | [diff] [blame] | 1199 | |
| 1200 | /* Not exposing RSS IP fragments to guests */ |
| 1201 | flags &= ~MLX4_DEV_CAP_FLAG_RSS_IP_FRAG; |
Jack Morgenstein | 2a4fae1 | 2012-08-03 08:40:50 +0000 | [diff] [blame] | 1202 | MLX4_PUT(outbox->buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 1203 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1204 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 1205 | field &= ~0x0F; |
| 1206 | field |= bitmap_weight(actv_ports.ports, dev->caps.num_ports) & 0x0F; |
| 1207 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VL_PORT_OFFSET); |
| 1208 | |
Amir Vadai | 30b40c3 | 2013-04-25 05:22:23 +0000 | [diff] [blame] | 1209 | /* For guests, disable timestamp */ |
| 1210 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 1211 | field &= 0x7f; |
| 1212 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_TS_SUPPORT_OFFSET); |
| 1213 | |
Ido Shamay | 3742cc6 | 2015-04-02 16:31:17 +0300 | [diff] [blame] | 1214 | /* For guests, disable vxlan tunneling and QoS support */ |
Amir Vadai | 57352ef | 2014-03-06 18:28:16 +0200 | [diff] [blame] | 1215 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_VXLAN); |
Ido Shamay | 3742cc6 | 2015-04-02 16:31:17 +0300 | [diff] [blame] | 1216 | field &= 0xd7; |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1217 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_VXLAN); |
| 1218 | |
Ido Shamay | 51af33c | 2015-04-02 16:31:20 +0300 | [diff] [blame] | 1219 | /* For guests, disable port BEACON */ |
| 1220 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_PORT_BEACON_OFFSET); |
| 1221 | field &= 0x7f; |
| 1222 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_PORT_BEACON_OFFSET); |
| 1223 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1224 | /* For guests, report Blueflame disabled */ |
| 1225 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_BF_OFFSET); |
| 1226 | field &= 0x7f; |
| 1227 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_BF_OFFSET); |
| 1228 | |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 1229 | /* For guests, disable mw type 2 and port remap*/ |
Amir Vadai | 57352ef | 2014-03-06 18:28:16 +0200 | [diff] [blame] | 1230 | MLX4_GET(bmme_flags, outbox->buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 1231 | bmme_flags &= ~MLX4_BMME_FLAG_TYPE_2_WIN; |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 1232 | bmme_flags &= ~MLX4_FLAG_PORT_REMAP; |
Shani Michaeli | cc1ade9 | 2013-02-06 16:19:10 +0000 | [diff] [blame] | 1233 | MLX4_PUT(outbox->buf, bmme_flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 1234 | |
Jack Morgenstein | 0081c8f | 2013-03-07 03:46:53 +0000 | [diff] [blame] | 1235 | /* turn off device-managed steering capability if not enabled */ |
| 1236 | if (dev->caps.steering_mode != MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 1237 | MLX4_GET(field, outbox->buf, |
| 1238 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 1239 | field &= 0x7f; |
| 1240 | MLX4_PUT(outbox->buf, field, |
| 1241 | QUERY_DEV_CAP_FLOW_STEERING_RANGE_EN_OFFSET); |
| 1242 | } |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 1243 | |
| 1244 | /* turn off ipoib managed steering for guests */ |
Amir Vadai | 57352ef | 2014-03-06 18:28:16 +0200 | [diff] [blame] | 1245 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
Matan Barak | 4de6580 | 2013-11-07 15:25:14 +0200 | [diff] [blame] | 1246 | field &= ~0x80; |
| 1247 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_FLOW_STEERING_IPOIB_OFFSET); |
| 1248 | |
Or Gerlitz | 383677d | 2014-12-11 10:57:52 +0200 | [diff] [blame] | 1249 | /* turn off host side virt features (VST, FSM, etc) for guests */ |
| 1250 | MLX4_GET(field32, outbox->buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
| 1251 | field32 &= ~(DEV_CAP_EXT_2_FLAG_VLAN_CONTROL | DEV_CAP_EXT_2_FLAG_80_VFS | |
Matan Barak | 0b13156 | 2015-03-30 17:45:25 +0300 | [diff] [blame] | 1252 | DEV_CAP_EXT_2_FLAG_FSM | DEV_CAP_EXT_2_FLAG_PFC_COUNTERS); |
Or Gerlitz | 383677d | 2014-12-11 10:57:52 +0200 | [diff] [blame] | 1253 | MLX4_PUT(outbox->buf, field32, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
| 1254 | |
Shani Michaeli | d237baa | 2015-03-05 20:16:12 +0200 | [diff] [blame] | 1255 | /* turn off QCN for guests */ |
| 1256 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); |
| 1257 | field &= 0xfe; |
| 1258 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_ECN_QCN_VER_OFFSET); |
| 1259 | |
Or Gerlitz | fc31e25 | 2015-03-18 14:57:34 +0200 | [diff] [blame] | 1260 | /* turn off QP max-rate limiting for guests */ |
| 1261 | field16 = 0; |
| 1262 | MLX4_PUT(outbox->buf, field16, QUERY_DEV_CAP_QP_RATE_LIMIT_NUM_OFFSET); |
| 1263 | |
Ido Shamay | d019fcb | 2015-04-02 16:31:13 +0300 | [diff] [blame] | 1264 | /* turn off QoS per VF support for guests */ |
| 1265 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); |
| 1266 | field &= 0xef; |
| 1267 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CQ_EQ_CACHE_LINE_STRIDE); |
| 1268 | |
Muhammad Mahajna | 78500b8 | 2015-04-02 16:31:22 +0300 | [diff] [blame] | 1269 | /* turn off ignore FCS feature for guests */ |
| 1270 | MLX4_GET(field, outbox->buf, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); |
| 1271 | field &= 0xfb; |
| 1272 | MLX4_PUT(outbox->buf, field, QUERY_DEV_CAP_CONFIG_DEV_OFFSET); |
| 1273 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1274 | return 0; |
| 1275 | } |
| 1276 | |
Moni Shoua | d8ae914 | 2016-01-14 17:50:32 +0200 | [diff] [blame] | 1277 | static void disable_unsupported_roce_caps(void *buf) |
| 1278 | { |
| 1279 | u32 flags; |
| 1280 | |
| 1281 | MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 1282 | flags &= ~(1UL << 31); |
| 1283 | MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_FLAGS_OFFSET); |
| 1284 | MLX4_GET(flags, buf, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
| 1285 | flags &= ~(1UL << 24); |
| 1286 | MLX4_PUT(buf, flags, QUERY_DEV_CAP_EXT_2_FLAGS_OFFSET); |
| 1287 | MLX4_GET(flags, buf, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 1288 | flags &= ~(MLX4_FLAG_ROCE_V1_V2); |
| 1289 | MLX4_PUT(buf, flags, QUERY_DEV_CAP_BMME_FLAGS_OFFSET); |
| 1290 | } |
| 1291 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1292 | int mlx4_QUERY_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 1293 | struct mlx4_vhcr *vhcr, |
| 1294 | struct mlx4_cmd_mailbox *inbox, |
| 1295 | struct mlx4_cmd_mailbox *outbox, |
| 1296 | struct mlx4_cmd_info *cmd) |
| 1297 | { |
Rony Efraim | 0eb62b9 | 2013-04-25 05:22:26 +0000 | [diff] [blame] | 1298 | struct mlx4_priv *priv = mlx4_priv(dev); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1299 | u64 def_mac; |
| 1300 | u8 port_type; |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1301 | u16 short_field; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1302 | int err; |
Rony Efraim | 948e306 | 2013-06-13 13:19:11 +0300 | [diff] [blame] | 1303 | int admin_link_state; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1304 | int port = mlx4_slave_convert_port(dev, slave, |
| 1305 | vhcr->in_modifier & 0xFF); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1306 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 1307 | #define MLX4_VF_PORT_NO_LINK_SENSE_MASK 0xE0 |
Rony Efraim | 948e306 | 2013-06-13 13:19:11 +0300 | [diff] [blame] | 1308 | #define MLX4_PORT_LINK_UP_MASK 0x80 |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1309 | #define QUERY_PORT_CUR_MAX_PKEY_OFFSET 0x0c |
| 1310 | #define QUERY_PORT_CUR_MAX_GID_OFFSET 0x0e |
Yevgeny Petrilin | 95f56e7 | 2011-12-29 07:42:39 +0000 | [diff] [blame] | 1311 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1312 | if (port < 0) |
| 1313 | return -EINVAL; |
| 1314 | |
Jack Morgenstein | a7401b9 | 2014-09-30 12:03:49 +0300 | [diff] [blame] | 1315 | /* Protect against untrusted guests: enforce that this is the |
| 1316 | * QUERY_PORT general query. |
| 1317 | */ |
| 1318 | if (vhcr->op_modifier || vhcr->in_modifier & ~0xFF) |
| 1319 | return -EINVAL; |
| 1320 | |
| 1321 | vhcr->in_modifier = port; |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1322 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1323 | err = mlx4_cmd_box(dev, 0, outbox->dma, vhcr->in_modifier, 0, |
| 1324 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, |
| 1325 | MLX4_CMD_NATIVE); |
| 1326 | |
| 1327 | if (!err && dev->caps.function != slave) { |
Or Gerlitz | 0508ad6 | 2013-08-01 19:55:00 +0300 | [diff] [blame] | 1328 | def_mac = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.mac; |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1329 | MLX4_PUT(outbox->buf, def_mac, QUERY_PORT_MAC_OFFSET); |
| 1330 | |
| 1331 | /* get port type - currently only eth is enabled */ |
| 1332 | MLX4_GET(port_type, outbox->buf, |
| 1333 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
| 1334 | |
Jack Morgenstein | 105c320 | 2012-06-19 11:21:43 +0300 | [diff] [blame] | 1335 | /* No link sensing allowed */ |
| 1336 | port_type &= MLX4_VF_PORT_NO_LINK_SENSE_MASK; |
| 1337 | /* set port type to currently operating port type */ |
| 1338 | port_type |= (dev->caps.port_type[vhcr->in_modifier] & 0x3); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1339 | |
Rony Efraim | 948e306 | 2013-06-13 13:19:11 +0300 | [diff] [blame] | 1340 | admin_link_state = priv->mfunc.master.vf_oper[slave].vport[vhcr->in_modifier].state.link_state; |
| 1341 | if (IFLA_VF_LINK_STATE_ENABLE == admin_link_state) |
| 1342 | port_type |= MLX4_PORT_LINK_UP_MASK; |
| 1343 | else if (IFLA_VF_LINK_STATE_DISABLE == admin_link_state) |
| 1344 | port_type &= ~MLX4_PORT_LINK_UP_MASK; |
Or Gerlitz | e34305c | 2015-12-06 18:07:38 +0200 | [diff] [blame] | 1345 | else if (IFLA_VF_LINK_STATE_AUTO == admin_link_state && mlx4_is_bonded(dev)) { |
| 1346 | int other_port = (port == 1) ? 2 : 1; |
| 1347 | struct mlx4_port_cap port_cap; |
| 1348 | |
| 1349 | err = mlx4_QUERY_PORT(dev, other_port, &port_cap); |
| 1350 | if (err) |
| 1351 | goto out; |
| 1352 | port_type |= (port_cap.link_state << 7); |
| 1353 | } |
Rony Efraim | 948e306 | 2013-06-13 13:19:11 +0300 | [diff] [blame] | 1354 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1355 | MLX4_PUT(outbox->buf, port_type, |
| 1356 | QUERY_PORT_SUPPORTED_TYPE_OFFSET); |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1357 | |
Jack Morgenstein | b6ffaef | 2014-03-12 12:00:39 +0200 | [diff] [blame] | 1358 | if (dev->caps.port_type[vhcr->in_modifier] == MLX4_PORT_TYPE_ETH) |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 1359 | short_field = mlx4_get_slave_num_gids(dev, slave, port); |
Jack Morgenstein | b6ffaef | 2014-03-12 12:00:39 +0200 | [diff] [blame] | 1360 | else |
| 1361 | short_field = 1; /* slave max gids */ |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1362 | MLX4_PUT(outbox->buf, short_field, |
| 1363 | QUERY_PORT_CUR_MAX_GID_OFFSET); |
| 1364 | |
| 1365 | short_field = dev->caps.pkey_table_len[vhcr->in_modifier]; |
| 1366 | MLX4_PUT(outbox->buf, short_field, |
| 1367 | QUERY_PORT_CUR_MAX_PKEY_OFFSET); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1368 | } |
Or Gerlitz | e34305c | 2015-12-06 18:07:38 +0200 | [diff] [blame] | 1369 | out: |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1370 | return err; |
| 1371 | } |
| 1372 | |
Jack Morgenstein | 6634961 | 2012-06-19 11:21:44 +0300 | [diff] [blame] | 1373 | int mlx4_get_slave_pkey_gid_tbl_len(struct mlx4_dev *dev, u8 port, |
| 1374 | int *gid_tbl_len, int *pkey_tbl_len) |
| 1375 | { |
| 1376 | struct mlx4_cmd_mailbox *mailbox; |
| 1377 | u32 *outbox; |
| 1378 | u16 field; |
| 1379 | int err; |
| 1380 | |
| 1381 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1382 | if (IS_ERR(mailbox)) |
| 1383 | return PTR_ERR(mailbox); |
| 1384 | |
| 1385 | err = mlx4_cmd_box(dev, 0, mailbox->dma, port, 0, |
| 1386 | MLX4_CMD_QUERY_PORT, MLX4_CMD_TIME_CLASS_B, |
| 1387 | MLX4_CMD_WRAPPED); |
| 1388 | if (err) |
| 1389 | goto out; |
| 1390 | |
| 1391 | outbox = mailbox->buf; |
| 1392 | |
| 1393 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_GID_OFFSET); |
| 1394 | *gid_tbl_len = field; |
| 1395 | |
| 1396 | MLX4_GET(field, outbox, QUERY_PORT_CUR_MAX_PKEY_OFFSET); |
| 1397 | *pkey_tbl_len = field; |
| 1398 | |
| 1399 | out: |
| 1400 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1401 | return err; |
| 1402 | } |
| 1403 | EXPORT_SYMBOL(mlx4_get_slave_pkey_gid_tbl_len); |
| 1404 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1405 | int mlx4_map_cmd(struct mlx4_dev *dev, u16 op, struct mlx4_icm *icm, u64 virt) |
| 1406 | { |
| 1407 | struct mlx4_cmd_mailbox *mailbox; |
| 1408 | struct mlx4_icm_iter iter; |
| 1409 | __be64 *pages; |
| 1410 | int lg; |
| 1411 | int nent = 0; |
| 1412 | int i; |
| 1413 | int err = 0; |
| 1414 | int ts = 0, tc = 0; |
| 1415 | |
| 1416 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1417 | if (IS_ERR(mailbox)) |
| 1418 | return PTR_ERR(mailbox); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1419 | pages = mailbox->buf; |
| 1420 | |
| 1421 | for (mlx4_icm_first(icm, &iter); |
| 1422 | !mlx4_icm_last(&iter); |
| 1423 | mlx4_icm_next(&iter)) { |
| 1424 | /* |
| 1425 | * We have to pass pages that are aligned to their |
| 1426 | * size, so find the least significant 1 in the |
| 1427 | * address or size and use that as our log2 size. |
| 1428 | */ |
| 1429 | lg = ffs(mlx4_icm_addr(&iter) | mlx4_icm_size(&iter)) - 1; |
| 1430 | if (lg < MLX4_ICM_PAGE_SHIFT) { |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1431 | mlx4_warn(dev, "Got FW area not aligned to %d (%llx/%lx)\n", |
| 1432 | MLX4_ICM_PAGE_SIZE, |
| 1433 | (unsigned long long) mlx4_icm_addr(&iter), |
| 1434 | mlx4_icm_size(&iter)); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1435 | err = -EINVAL; |
| 1436 | goto out; |
| 1437 | } |
| 1438 | |
| 1439 | for (i = 0; i < mlx4_icm_size(&iter) >> lg; ++i) { |
| 1440 | if (virt != -1) { |
| 1441 | pages[nent * 2] = cpu_to_be64(virt); |
| 1442 | virt += 1 << lg; |
| 1443 | } |
| 1444 | |
| 1445 | pages[nent * 2 + 1] = |
| 1446 | cpu_to_be64((mlx4_icm_addr(&iter) + (i << lg)) | |
| 1447 | (lg - MLX4_ICM_PAGE_SHIFT)); |
| 1448 | ts += 1 << (lg - 10); |
| 1449 | ++tc; |
| 1450 | |
| 1451 | if (++nent == MLX4_MAILBOX_SIZE / 16) { |
| 1452 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1453 | MLX4_CMD_TIME_CLASS_B, |
| 1454 | MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1455 | if (err) |
| 1456 | goto out; |
| 1457 | nent = 0; |
| 1458 | } |
| 1459 | } |
| 1460 | } |
| 1461 | |
| 1462 | if (nent) |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1463 | err = mlx4_cmd(dev, mailbox->dma, nent, 0, op, |
| 1464 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1465 | if (err) |
| 1466 | goto out; |
| 1467 | |
| 1468 | switch (op) { |
| 1469 | case MLX4_CMD_MAP_FA: |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1470 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for FW\n", tc, ts); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1471 | break; |
| 1472 | case MLX4_CMD_MAP_ICM_AUX: |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1473 | mlx4_dbg(dev, "Mapped %d chunks/%d KB for ICM aux\n", tc, ts); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1474 | break; |
| 1475 | case MLX4_CMD_MAP_ICM: |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1476 | mlx4_dbg(dev, "Mapped %d chunks/%d KB at %llx for ICM\n", |
| 1477 | tc, ts, (unsigned long long) virt - (ts << 10)); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1478 | break; |
| 1479 | } |
| 1480 | |
| 1481 | out: |
| 1482 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1483 | return err; |
| 1484 | } |
| 1485 | |
| 1486 | int mlx4_MAP_FA(struct mlx4_dev *dev, struct mlx4_icm *icm) |
| 1487 | { |
| 1488 | return mlx4_map_cmd(dev, MLX4_CMD_MAP_FA, icm, -1); |
| 1489 | } |
| 1490 | |
| 1491 | int mlx4_UNMAP_FA(struct mlx4_dev *dev) |
| 1492 | { |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1493 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_UNMAP_FA, |
| 1494 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1495 | } |
| 1496 | |
| 1497 | |
| 1498 | int mlx4_RUN_FW(struct mlx4_dev *dev) |
| 1499 | { |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1500 | return mlx4_cmd(dev, 0, 0, 0, MLX4_CMD_RUN_FW, |
| 1501 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1502 | } |
| 1503 | |
| 1504 | int mlx4_QUERY_FW(struct mlx4_dev *dev) |
| 1505 | { |
| 1506 | struct mlx4_fw *fw = &mlx4_priv(dev)->fw; |
| 1507 | struct mlx4_cmd *cmd = &mlx4_priv(dev)->cmd; |
| 1508 | struct mlx4_cmd_mailbox *mailbox; |
| 1509 | u32 *outbox; |
| 1510 | int err = 0; |
| 1511 | u64 fw_ver; |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1512 | u16 cmd_if_rev; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1513 | u8 lg; |
| 1514 | |
| 1515 | #define QUERY_FW_OUT_SIZE 0x100 |
| 1516 | #define QUERY_FW_VER_OFFSET 0x00 |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1517 | #define QUERY_FW_PPF_ID 0x09 |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1518 | #define QUERY_FW_CMD_IF_REV_OFFSET 0x0a |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1519 | #define QUERY_FW_MAX_CMD_OFFSET 0x0f |
| 1520 | #define QUERY_FW_ERR_START_OFFSET 0x30 |
| 1521 | #define QUERY_FW_ERR_SIZE_OFFSET 0x38 |
| 1522 | #define QUERY_FW_ERR_BAR_OFFSET 0x3c |
| 1523 | |
| 1524 | #define QUERY_FW_SIZE_OFFSET 0x00 |
| 1525 | #define QUERY_FW_CLR_INT_BASE_OFFSET 0x20 |
| 1526 | #define QUERY_FW_CLR_INT_BAR_OFFSET 0x28 |
| 1527 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1528 | #define QUERY_FW_COMM_BASE_OFFSET 0x40 |
| 1529 | #define QUERY_FW_COMM_BAR_OFFSET 0x48 |
| 1530 | |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1531 | #define QUERY_FW_CLOCK_OFFSET 0x50 |
| 1532 | #define QUERY_FW_CLOCK_BAR 0x58 |
| 1533 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1534 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1535 | if (IS_ERR(mailbox)) |
| 1536 | return PTR_ERR(mailbox); |
| 1537 | outbox = mailbox->buf; |
| 1538 | |
| 1539 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_FW, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1540 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1541 | if (err) |
| 1542 | goto out; |
| 1543 | |
| 1544 | MLX4_GET(fw_ver, outbox, QUERY_FW_VER_OFFSET); |
| 1545 | /* |
Roland Dreier | 3e1db33 | 2007-06-03 19:47:10 -0700 | [diff] [blame] | 1546 | * FW subminor version is at more significant bits than minor |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1547 | * version, so swap here. |
| 1548 | */ |
| 1549 | dev->caps.fw_ver = (fw_ver & 0xffff00000000ull) | |
| 1550 | ((fw_ver & 0xffff0000ull) >> 16) | |
| 1551 | ((fw_ver & 0x0000ffffull) << 16); |
| 1552 | |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 1553 | MLX4_GET(lg, outbox, QUERY_FW_PPF_ID); |
| 1554 | dev->caps.function = lg; |
| 1555 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1556 | if (mlx4_is_slave(dev)) |
| 1557 | goto out; |
| 1558 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1559 | |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1560 | MLX4_GET(cmd_if_rev, outbox, QUERY_FW_CMD_IF_REV_OFFSET); |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1561 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_MIN_REV || |
| 1562 | cmd_if_rev > MLX4_COMMAND_INTERFACE_MAX_REV) { |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1563 | mlx4_err(dev, "Installed FW has unsupported command interface revision %d\n", |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1564 | cmd_if_rev); |
| 1565 | mlx4_err(dev, "(Installed FW version is %d.%d.%03d)\n", |
| 1566 | (int) (dev->caps.fw_ver >> 32), |
| 1567 | (int) (dev->caps.fw_ver >> 16) & 0xffff, |
| 1568 | (int) dev->caps.fw_ver & 0xffff); |
Joe Perches | 1a91de2 | 2014-05-07 12:52:57 -0700 | [diff] [blame] | 1569 | mlx4_err(dev, "This driver version supports only revisions %d to %d\n", |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1570 | MLX4_COMMAND_INTERFACE_MIN_REV, MLX4_COMMAND_INTERFACE_MAX_REV); |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1571 | err = -ENODEV; |
| 1572 | goto out; |
| 1573 | } |
| 1574 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 1575 | if (cmd_if_rev < MLX4_COMMAND_INTERFACE_NEW_PORT_CMDS) |
| 1576 | dev->flags |= MLX4_FLAG_OLD_PORT_CMDS; |
| 1577 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1578 | MLX4_GET(lg, outbox, QUERY_FW_MAX_CMD_OFFSET); |
| 1579 | cmd->max_cmds = 1 << lg; |
| 1580 | |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1581 | mlx4_dbg(dev, "FW version %d.%d.%03d (cmd intf rev %d), max commands %d\n", |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1582 | (int) (dev->caps.fw_ver >> 32), |
| 1583 | (int) (dev->caps.fw_ver >> 16) & 0xffff, |
| 1584 | (int) dev->caps.fw_ver & 0xffff, |
Roland Dreier | fe40900 | 2007-06-07 23:24:36 -0700 | [diff] [blame] | 1585 | cmd_if_rev, cmd->max_cmds); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1586 | |
| 1587 | MLX4_GET(fw->catas_offset, outbox, QUERY_FW_ERR_START_OFFSET); |
| 1588 | MLX4_GET(fw->catas_size, outbox, QUERY_FW_ERR_SIZE_OFFSET); |
| 1589 | MLX4_GET(fw->catas_bar, outbox, QUERY_FW_ERR_BAR_OFFSET); |
| 1590 | fw->catas_bar = (fw->catas_bar >> 6) * 2; |
| 1591 | |
| 1592 | mlx4_dbg(dev, "Catastrophic error buffer at 0x%llx, size 0x%x, BAR %d\n", |
| 1593 | (unsigned long long) fw->catas_offset, fw->catas_size, fw->catas_bar); |
| 1594 | |
| 1595 | MLX4_GET(fw->fw_pages, outbox, QUERY_FW_SIZE_OFFSET); |
| 1596 | MLX4_GET(fw->clr_int_base, outbox, QUERY_FW_CLR_INT_BASE_OFFSET); |
| 1597 | MLX4_GET(fw->clr_int_bar, outbox, QUERY_FW_CLR_INT_BAR_OFFSET); |
| 1598 | fw->clr_int_bar = (fw->clr_int_bar >> 6) * 2; |
| 1599 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1600 | MLX4_GET(fw->comm_base, outbox, QUERY_FW_COMM_BASE_OFFSET); |
| 1601 | MLX4_GET(fw->comm_bar, outbox, QUERY_FW_COMM_BAR_OFFSET); |
| 1602 | fw->comm_bar = (fw->comm_bar >> 6) * 2; |
| 1603 | mlx4_dbg(dev, "Communication vector bar:%d offset:0x%llx\n", |
| 1604 | fw->comm_bar, fw->comm_base); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1605 | mlx4_dbg(dev, "FW size %d KB\n", fw->fw_pages >> 2); |
| 1606 | |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1607 | MLX4_GET(fw->clock_offset, outbox, QUERY_FW_CLOCK_OFFSET); |
| 1608 | MLX4_GET(fw->clock_bar, outbox, QUERY_FW_CLOCK_BAR); |
| 1609 | fw->clock_bar = (fw->clock_bar >> 6) * 2; |
| 1610 | mlx4_dbg(dev, "Internal clock bar:%d offset:0x%llx\n", |
| 1611 | fw->clock_bar, fw->clock_offset); |
| 1612 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1613 | /* |
| 1614 | * Round up number of system pages needed in case |
| 1615 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. |
| 1616 | */ |
| 1617 | fw->fw_pages = |
| 1618 | ALIGN(fw->fw_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> |
| 1619 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); |
| 1620 | |
| 1621 | mlx4_dbg(dev, "Clear int @ %llx, BAR %d\n", |
| 1622 | (unsigned long long) fw->clr_int_base, fw->clr_int_bar); |
| 1623 | |
| 1624 | out: |
| 1625 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1626 | return err; |
| 1627 | } |
| 1628 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1629 | int mlx4_QUERY_FW_wrapper(struct mlx4_dev *dev, int slave, |
| 1630 | struct mlx4_vhcr *vhcr, |
| 1631 | struct mlx4_cmd_mailbox *inbox, |
| 1632 | struct mlx4_cmd_mailbox *outbox, |
| 1633 | struct mlx4_cmd_info *cmd) |
| 1634 | { |
| 1635 | u8 *outbuf; |
| 1636 | int err; |
| 1637 | |
| 1638 | outbuf = outbox->buf; |
| 1639 | err = mlx4_cmd_box(dev, 0, outbox->dma, 0, 0, MLX4_CMD_QUERY_FW, |
| 1640 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 1641 | if (err) |
| 1642 | return err; |
| 1643 | |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 1644 | /* for slaves, set pci PPF ID to invalid and zero out everything |
| 1645 | * else except FW version */ |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1646 | outbuf[0] = outbuf[1] = 0; |
| 1647 | memset(&outbuf[8], 0, QUERY_FW_OUT_SIZE - 8); |
Jack Morgenstein | 752a50c | 2012-06-19 11:21:33 +0300 | [diff] [blame] | 1648 | outbuf[QUERY_FW_PPF_ID] = MLX4_INVALID_SLAVE_ID; |
| 1649 | |
Jack Morgenstein | b91cb3e | 2012-05-30 09:14:53 +0000 | [diff] [blame] | 1650 | return 0; |
| 1651 | } |
| 1652 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1653 | static void get_board_id(void *vsd, char *board_id) |
| 1654 | { |
| 1655 | int i; |
| 1656 | |
| 1657 | #define VSD_OFFSET_SIG1 0x00 |
| 1658 | #define VSD_OFFSET_SIG2 0xde |
| 1659 | #define VSD_OFFSET_MLX_BOARD_ID 0xd0 |
| 1660 | #define VSD_OFFSET_TS_BOARD_ID 0x20 |
| 1661 | |
| 1662 | #define VSD_SIGNATURE_TOPSPIN 0x5ad |
| 1663 | |
| 1664 | memset(board_id, 0, MLX4_BOARD_ID_LEN); |
| 1665 | |
| 1666 | if (be16_to_cpup(vsd + VSD_OFFSET_SIG1) == VSD_SIGNATURE_TOPSPIN && |
| 1667 | be16_to_cpup(vsd + VSD_OFFSET_SIG2) == VSD_SIGNATURE_TOPSPIN) { |
| 1668 | strlcpy(board_id, vsd + VSD_OFFSET_TS_BOARD_ID, MLX4_BOARD_ID_LEN); |
| 1669 | } else { |
| 1670 | /* |
| 1671 | * The board ID is a string but the firmware byte |
| 1672 | * swaps each 4-byte word before passing it back to |
| 1673 | * us. Therefore we need to swab it before printing. |
| 1674 | */ |
David Ahern | 17d5ceb | 2015-04-29 16:52:51 -0400 | [diff] [blame] | 1675 | u32 *bid_u32 = (u32 *)board_id; |
| 1676 | |
| 1677 | for (i = 0; i < 4; ++i) { |
| 1678 | u32 *addr; |
| 1679 | u32 val; |
| 1680 | |
| 1681 | addr = (u32 *) (vsd + VSD_OFFSET_MLX_BOARD_ID + i * 4); |
| 1682 | val = get_unaligned(addr); |
| 1683 | val = swab32(val); |
| 1684 | put_unaligned(val, &bid_u32[i]); |
| 1685 | } |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1686 | } |
| 1687 | } |
| 1688 | |
| 1689 | int mlx4_QUERY_ADAPTER(struct mlx4_dev *dev, struct mlx4_adapter *adapter) |
| 1690 | { |
| 1691 | struct mlx4_cmd_mailbox *mailbox; |
| 1692 | u32 *outbox; |
| 1693 | int err; |
| 1694 | |
| 1695 | #define QUERY_ADAPTER_OUT_SIZE 0x100 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1696 | #define QUERY_ADAPTER_INTA_PIN_OFFSET 0x10 |
| 1697 | #define QUERY_ADAPTER_VSD_OFFSET 0x20 |
| 1698 | |
| 1699 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1700 | if (IS_ERR(mailbox)) |
| 1701 | return PTR_ERR(mailbox); |
| 1702 | outbox = mailbox->buf; |
| 1703 | |
| 1704 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, MLX4_CMD_QUERY_ADAPTER, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 1705 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1706 | if (err) |
| 1707 | goto out; |
| 1708 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1709 | MLX4_GET(adapter->inta_pin, outbox, QUERY_ADAPTER_INTA_PIN_OFFSET); |
| 1710 | |
| 1711 | get_board_id(outbox + QUERY_ADAPTER_VSD_OFFSET / 4, |
| 1712 | adapter->board_id); |
| 1713 | |
| 1714 | out: |
| 1715 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1716 | return err; |
| 1717 | } |
| 1718 | |
| 1719 | int mlx4_INIT_HCA(struct mlx4_dev *dev, struct mlx4_init_hca_param *param) |
| 1720 | { |
| 1721 | struct mlx4_cmd_mailbox *mailbox; |
| 1722 | __be32 *inbox; |
| 1723 | int err; |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 1724 | static const u8 a0_dmfs_hw_steering[] = { |
| 1725 | [MLX4_STEERING_DMFS_A0_DEFAULT] = 0, |
| 1726 | [MLX4_STEERING_DMFS_A0_DYNAMIC] = 1, |
| 1727 | [MLX4_STEERING_DMFS_A0_STATIC] = 2, |
| 1728 | [MLX4_STEERING_DMFS_A0_DISABLE] = 3 |
| 1729 | }; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1730 | |
| 1731 | #define INIT_HCA_IN_SIZE 0x200 |
| 1732 | #define INIT_HCA_VERSION_OFFSET 0x000 |
| 1733 | #define INIT_HCA_VERSION 2 |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1734 | #define INIT_HCA_VXLAN_OFFSET 0x0c |
Eli Cohen | c57e20dcf | 2009-09-24 11:03:03 -0700 | [diff] [blame] | 1735 | #define INIT_HCA_CACHELINE_SZ_OFFSET 0x0e |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1736 | #define INIT_HCA_FLAGS_OFFSET 0x014 |
Jack Morgenstein | be6a6b4 | 2015-01-27 15:57:59 +0200 | [diff] [blame] | 1737 | #define INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET 0x018 |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1738 | #define INIT_HCA_QPC_OFFSET 0x020 |
| 1739 | #define INIT_HCA_QPC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x10) |
| 1740 | #define INIT_HCA_LOG_QP_OFFSET (INIT_HCA_QPC_OFFSET + 0x17) |
| 1741 | #define INIT_HCA_SRQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x28) |
| 1742 | #define INIT_HCA_LOG_SRQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x2f) |
| 1743 | #define INIT_HCA_CQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x30) |
| 1744 | #define INIT_HCA_LOG_CQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x37) |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 1745 | #define INIT_HCA_EQE_CQE_OFFSETS (INIT_HCA_QPC_OFFSET + 0x38) |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 1746 | #define INIT_HCA_EQE_CQE_STRIDE_OFFSET (INIT_HCA_QPC_OFFSET + 0x3b) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1747 | #define INIT_HCA_ALTC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x40) |
| 1748 | #define INIT_HCA_AUXC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x50) |
| 1749 | #define INIT_HCA_EQC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x60) |
| 1750 | #define INIT_HCA_LOG_EQ_OFFSET (INIT_HCA_QPC_OFFSET + 0x67) |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 1751 | #define INIT_HCA_NUM_SYS_EQS_OFFSET (INIT_HCA_QPC_OFFSET + 0x6a) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1752 | #define INIT_HCA_RDMARC_BASE_OFFSET (INIT_HCA_QPC_OFFSET + 0x70) |
| 1753 | #define INIT_HCA_LOG_RD_OFFSET (INIT_HCA_QPC_OFFSET + 0x77) |
| 1754 | #define INIT_HCA_MCAST_OFFSET 0x0c0 |
| 1755 | #define INIT_HCA_MC_BASE_OFFSET (INIT_HCA_MCAST_OFFSET + 0x00) |
| 1756 | #define INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x12) |
| 1757 | #define INIT_HCA_LOG_MC_HASH_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x16) |
Yevgeny Petrilin | 1679200 | 2011-03-22 22:38:31 +0000 | [diff] [blame] | 1758 | #define INIT_HCA_UC_STEERING_OFFSET (INIT_HCA_MCAST_OFFSET + 0x18) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1759 | #define INIT_HCA_LOG_MC_TABLE_SZ_OFFSET (INIT_HCA_MCAST_OFFSET + 0x1b) |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1760 | #define INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN 0x6 |
| 1761 | #define INIT_HCA_FS_PARAM_OFFSET 0x1d0 |
| 1762 | #define INIT_HCA_FS_BASE_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x00) |
| 1763 | #define INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x12) |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 1764 | #define INIT_HCA_FS_A0_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x18) |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1765 | #define INIT_HCA_FS_LOG_TABLE_SZ_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x1b) |
| 1766 | #define INIT_HCA_FS_ETH_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x21) |
| 1767 | #define INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x22) |
| 1768 | #define INIT_HCA_FS_IB_BITS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x25) |
| 1769 | #define INIT_HCA_FS_IB_NUM_ADDRS_OFFSET (INIT_HCA_FS_PARAM_OFFSET + 0x26) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1770 | #define INIT_HCA_TPT_OFFSET 0x0f0 |
| 1771 | #define INIT_HCA_DMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x00) |
Shani Michaeli | e448834 | 2013-02-06 16:19:11 +0000 | [diff] [blame] | 1772 | #define INIT_HCA_TPT_MW_OFFSET (INIT_HCA_TPT_OFFSET + 0x08) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1773 | #define INIT_HCA_LOG_MPT_SZ_OFFSET (INIT_HCA_TPT_OFFSET + 0x0b) |
| 1774 | #define INIT_HCA_MTT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x10) |
| 1775 | #define INIT_HCA_CMPT_BASE_OFFSET (INIT_HCA_TPT_OFFSET + 0x18) |
| 1776 | #define INIT_HCA_UAR_OFFSET 0x120 |
| 1777 | #define INIT_HCA_LOG_UAR_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0a) |
| 1778 | #define INIT_HCA_UAR_PAGE_SZ_OFFSET (INIT_HCA_UAR_OFFSET + 0x0b) |
| 1779 | |
| 1780 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1781 | if (IS_ERR(mailbox)) |
| 1782 | return PTR_ERR(mailbox); |
| 1783 | inbox = mailbox->buf; |
| 1784 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1785 | *((u8 *) mailbox->buf + INIT_HCA_VERSION_OFFSET) = INIT_HCA_VERSION; |
| 1786 | |
Eli Cohen | c57e20dcf | 2009-09-24 11:03:03 -0700 | [diff] [blame] | 1787 | *((u8 *) mailbox->buf + INIT_HCA_CACHELINE_SZ_OFFSET) = |
| 1788 | (ilog2(cache_line_size()) - 4) << 5; |
| 1789 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1790 | #if defined(__LITTLE_ENDIAN) |
| 1791 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) &= ~cpu_to_be32(1 << 1); |
| 1792 | #elif defined(__BIG_ENDIAN) |
| 1793 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 1); |
| 1794 | #else |
| 1795 | #error Host endianness not defined |
| 1796 | #endif |
| 1797 | /* Check port for UD address vector: */ |
| 1798 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1); |
| 1799 | |
Eli Cohen | 8ff095e | 2008-04-16 21:01:10 -0700 | [diff] [blame] | 1800 | /* Enable IPoIB checksumming if we can: */ |
| 1801 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_IPOIB_CSUM) |
| 1802 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 3); |
| 1803 | |
Jack Morgenstein | 51f5f0e | 2008-07-22 14:19:37 -0700 | [diff] [blame] | 1804 | /* Enable QoS support if module parameter set */ |
Ido Shamay | 38438f7 | 2015-04-02 16:31:18 +0300 | [diff] [blame] | 1805 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_ETS_CFG && enable_qos) |
Jack Morgenstein | 51f5f0e | 2008-07-22 14:19:37 -0700 | [diff] [blame] | 1806 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 2); |
| 1807 | |
Or Gerlitz | f2a3f6a | 2011-06-15 14:47:14 +0000 | [diff] [blame] | 1808 | /* enable counters */ |
| 1809 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_COUNTERS) |
| 1810 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 4); |
| 1811 | |
Ido Shamay | 802f42a | 2015-04-02 16:31:06 +0300 | [diff] [blame] | 1812 | /* Enable RSS spread to fragmented IP packets when supported */ |
| 1813 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_RSS_IP_FRAG) |
| 1814 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= cpu_to_be32(1 << 13); |
| 1815 | |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 1816 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
| 1817 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_EQE) { |
| 1818 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 29); |
| 1819 | dev->caps.eqe_size = 64; |
| 1820 | dev->caps.eqe_factor = 1; |
| 1821 | } else { |
| 1822 | dev->caps.eqe_size = 32; |
| 1823 | dev->caps.eqe_factor = 0; |
| 1824 | } |
| 1825 | |
| 1826 | if (dev->caps.flags & MLX4_DEV_CAP_FLAG_64B_CQE) { |
| 1827 | *(inbox + INIT_HCA_EQE_CQE_OFFSETS / 4) |= cpu_to_be32(1 << 30); |
| 1828 | dev->caps.cqe_size = 64; |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 1829 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 1830 | } else { |
| 1831 | dev->caps.cqe_size = 32; |
| 1832 | } |
| 1833 | |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 1834 | /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ |
| 1835 | if ((dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_EQE_STRIDE) && |
| 1836 | (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CQE_STRIDE)) { |
| 1837 | dev->caps.eqe_size = cache_line_size(); |
| 1838 | dev->caps.cqe_size = cache_line_size(); |
| 1839 | dev->caps.eqe_factor = 0; |
| 1840 | MLX4_PUT(inbox, (u8)((ilog2(dev->caps.eqe_size) - 5) << 4 | |
| 1841 | (ilog2(dev->caps.eqe_size) - 5)), |
| 1842 | INIT_HCA_EQE_CQE_STRIDE_OFFSET); |
| 1843 | |
| 1844 | /* User still need to know to support CQE > 32B */ |
| 1845 | dev->caps.userspace_caps |= MLX4_USER_DEV_CAP_LARGE_CQE; |
| 1846 | } |
| 1847 | |
Jack Morgenstein | be6a6b4 | 2015-01-27 15:57:59 +0200 | [diff] [blame] | 1848 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_RECOVERABLE_ERROR_EVENT) |
| 1849 | *(inbox + INIT_HCA_RECOVERABLE_ERROR_EVENT_OFFSET / 4) |= cpu_to_be32(1 << 31); |
| 1850 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1851 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
| 1852 | |
| 1853 | MLX4_PUT(inbox, param->qpc_base, INIT_HCA_QPC_BASE_OFFSET); |
| 1854 | MLX4_PUT(inbox, param->log_num_qps, INIT_HCA_LOG_QP_OFFSET); |
| 1855 | MLX4_PUT(inbox, param->srqc_base, INIT_HCA_SRQC_BASE_OFFSET); |
| 1856 | MLX4_PUT(inbox, param->log_num_srqs, INIT_HCA_LOG_SRQ_OFFSET); |
| 1857 | MLX4_PUT(inbox, param->cqc_base, INIT_HCA_CQC_BASE_OFFSET); |
| 1858 | MLX4_PUT(inbox, param->log_num_cqs, INIT_HCA_LOG_CQ_OFFSET); |
| 1859 | MLX4_PUT(inbox, param->altc_base, INIT_HCA_ALTC_BASE_OFFSET); |
| 1860 | MLX4_PUT(inbox, param->auxc_base, INIT_HCA_AUXC_BASE_OFFSET); |
| 1861 | MLX4_PUT(inbox, param->eqc_base, INIT_HCA_EQC_BASE_OFFSET); |
| 1862 | MLX4_PUT(inbox, param->log_num_eqs, INIT_HCA_LOG_EQ_OFFSET); |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 1863 | MLX4_PUT(inbox, param->num_sys_eqs, INIT_HCA_NUM_SYS_EQS_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1864 | MLX4_PUT(inbox, param->rdmarc_base, INIT_HCA_RDMARC_BASE_OFFSET); |
| 1865 | MLX4_PUT(inbox, param->log_rd_per_qp, INIT_HCA_LOG_RD_OFFSET); |
| 1866 | |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1867 | /* steering attributes */ |
| 1868 | if (dev->caps.steering_mode == |
| 1869 | MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 1870 | *(inbox + INIT_HCA_FLAGS_OFFSET / 4) |= |
| 1871 | cpu_to_be32(1 << |
| 1872 | INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1873 | |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1874 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_FS_BASE_OFFSET); |
| 1875 | MLX4_PUT(inbox, param->log_mc_entry_sz, |
| 1876 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); |
| 1877 | MLX4_PUT(inbox, param->log_mc_table_sz, |
| 1878 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); |
| 1879 | /* Enable Ethernet flow steering |
| 1880 | * with udp unicast and tcp unicast |
| 1881 | */ |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 1882 | if (dev->caps.dmfs_high_steer_mode != |
| 1883 | MLX4_STEERING_DMFS_A0_STATIC) |
| 1884 | MLX4_PUT(inbox, |
| 1885 | (u8)(MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
| 1886 | INIT_HCA_FS_ETH_BITS_OFFSET); |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1887 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, |
| 1888 | INIT_HCA_FS_ETH_NUM_ADDRS_OFFSET); |
| 1889 | /* Enable IPoIB flow steering |
| 1890 | * with udp unicast and tcp unicast |
| 1891 | */ |
Hadar Hen Zion | 23537b7 | 2013-01-30 23:07:09 +0000 | [diff] [blame] | 1892 | MLX4_PUT(inbox, (u8) (MLX4_FS_UDP_UC_EN | MLX4_FS_TCP_UC_EN), |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1893 | INIT_HCA_FS_IB_BITS_OFFSET); |
| 1894 | MLX4_PUT(inbox, (u16) MLX4_FS_NUM_OF_L2_ADDR, |
| 1895 | INIT_HCA_FS_IB_NUM_ADDRS_OFFSET); |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 1896 | |
| 1897 | if (dev->caps.dmfs_high_steer_mode != |
| 1898 | MLX4_STEERING_DMFS_A0_NOT_SUPPORTED) |
| 1899 | MLX4_PUT(inbox, |
| 1900 | ((u8)(a0_dmfs_hw_steering[dev->caps.dmfs_high_steer_mode] |
| 1901 | << 6)), |
| 1902 | INIT_HCA_FS_A0_OFFSET); |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 1903 | } else { |
| 1904 | MLX4_PUT(inbox, param->mc_base, INIT_HCA_MC_BASE_OFFSET); |
| 1905 | MLX4_PUT(inbox, param->log_mc_entry_sz, |
| 1906 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); |
| 1907 | MLX4_PUT(inbox, param->log_mc_hash_sz, |
| 1908 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); |
| 1909 | MLX4_PUT(inbox, param->log_mc_table_sz, |
| 1910 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
| 1911 | if (dev->caps.steering_mode == MLX4_STEERING_MODE_B0) |
| 1912 | MLX4_PUT(inbox, (u8) (1 << 3), |
| 1913 | INIT_HCA_UC_STEERING_OFFSET); |
| 1914 | } |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1915 | |
| 1916 | /* TPT attributes */ |
| 1917 | |
| 1918 | MLX4_PUT(inbox, param->dmpt_base, INIT_HCA_DMPT_BASE_OFFSET); |
Shani Michaeli | e448834 | 2013-02-06 16:19:11 +0000 | [diff] [blame] | 1919 | MLX4_PUT(inbox, param->mw_enabled, INIT_HCA_TPT_MW_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1920 | MLX4_PUT(inbox, param->log_mpt_sz, INIT_HCA_LOG_MPT_SZ_OFFSET); |
| 1921 | MLX4_PUT(inbox, param->mtt_base, INIT_HCA_MTT_BASE_OFFSET); |
| 1922 | MLX4_PUT(inbox, param->cmpt_base, INIT_HCA_CMPT_BASE_OFFSET); |
| 1923 | |
| 1924 | /* UAR attributes */ |
| 1925 | |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1926 | MLX4_PUT(inbox, param->uar_page_sz, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1927 | MLX4_PUT(inbox, param->log_uar_sz, INIT_HCA_LOG_UAR_SZ_OFFSET); |
| 1928 | |
Or Gerlitz | 7ffdf72 | 2013-12-23 16:09:43 +0200 | [diff] [blame] | 1929 | /* set parser VXLAN attributes */ |
| 1930 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_VXLAN_OFFLOADS) { |
| 1931 | u8 parser_params = 0; |
| 1932 | MLX4_PUT(inbox, parser_params, INIT_HCA_VXLAN_OFFSET); |
| 1933 | } |
| 1934 | |
Jack Morgenstein | 5a03108 | 2015-01-27 15:58:02 +0200 | [diff] [blame] | 1935 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_INIT_HCA, |
| 1936 | MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 1937 | |
| 1938 | if (err) |
| 1939 | mlx4_err(dev, "INIT_HCA returns %d\n", err); |
| 1940 | |
| 1941 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 1942 | return err; |
| 1943 | } |
| 1944 | |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1945 | int mlx4_QUERY_HCA(struct mlx4_dev *dev, |
| 1946 | struct mlx4_init_hca_param *param) |
| 1947 | { |
| 1948 | struct mlx4_cmd_mailbox *mailbox; |
| 1949 | __be32 *outbox; |
Jack Morgenstein | 7b8157b | 2012-12-06 17:11:59 +0000 | [diff] [blame] | 1950 | u32 dword_field; |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1951 | int err; |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 1952 | u8 byte_field; |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 1953 | static const u8 a0_dmfs_query_hw_steering[] = { |
| 1954 | [0] = MLX4_STEERING_DMFS_A0_DEFAULT, |
| 1955 | [1] = MLX4_STEERING_DMFS_A0_DYNAMIC, |
| 1956 | [2] = MLX4_STEERING_DMFS_A0_STATIC, |
| 1957 | [3] = MLX4_STEERING_DMFS_A0_DISABLE |
| 1958 | }; |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1959 | |
| 1960 | #define QUERY_HCA_GLOBAL_CAPS_OFFSET 0x04 |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1961 | #define QUERY_HCA_CORE_CLOCK_OFFSET 0x0c |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1962 | |
| 1963 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 1964 | if (IS_ERR(mailbox)) |
| 1965 | return PTR_ERR(mailbox); |
| 1966 | outbox = mailbox->buf; |
| 1967 | |
| 1968 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 1969 | MLX4_CMD_QUERY_HCA, |
| 1970 | MLX4_CMD_TIME_CLASS_B, |
| 1971 | !mlx4_is_slave(dev)); |
| 1972 | if (err) |
| 1973 | goto out; |
| 1974 | |
| 1975 | MLX4_GET(param->global_caps, outbox, QUERY_HCA_GLOBAL_CAPS_OFFSET); |
Eugenia Emantayev | ddd8a6c | 2013-04-23 06:06:48 +0000 | [diff] [blame] | 1976 | MLX4_GET(param->hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1977 | |
| 1978 | /* QPC/EEC/CQC/EQC/RDMARC attributes */ |
| 1979 | |
| 1980 | MLX4_GET(param->qpc_base, outbox, INIT_HCA_QPC_BASE_OFFSET); |
| 1981 | MLX4_GET(param->log_num_qps, outbox, INIT_HCA_LOG_QP_OFFSET); |
| 1982 | MLX4_GET(param->srqc_base, outbox, INIT_HCA_SRQC_BASE_OFFSET); |
| 1983 | MLX4_GET(param->log_num_srqs, outbox, INIT_HCA_LOG_SRQ_OFFSET); |
| 1984 | MLX4_GET(param->cqc_base, outbox, INIT_HCA_CQC_BASE_OFFSET); |
| 1985 | MLX4_GET(param->log_num_cqs, outbox, INIT_HCA_LOG_CQ_OFFSET); |
| 1986 | MLX4_GET(param->altc_base, outbox, INIT_HCA_ALTC_BASE_OFFSET); |
| 1987 | MLX4_GET(param->auxc_base, outbox, INIT_HCA_AUXC_BASE_OFFSET); |
| 1988 | MLX4_GET(param->eqc_base, outbox, INIT_HCA_EQC_BASE_OFFSET); |
| 1989 | MLX4_GET(param->log_num_eqs, outbox, INIT_HCA_LOG_EQ_OFFSET); |
Matan Barak | 7ae0e40 | 2014-11-13 14:45:32 +0200 | [diff] [blame] | 1990 | MLX4_GET(param->num_sys_eqs, outbox, INIT_HCA_NUM_SYS_EQS_OFFSET); |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 1991 | MLX4_GET(param->rdmarc_base, outbox, INIT_HCA_RDMARC_BASE_OFFSET); |
| 1992 | MLX4_GET(param->log_rd_per_qp, outbox, INIT_HCA_LOG_RD_OFFSET); |
| 1993 | |
Jack Morgenstein | 7b8157b | 2012-12-06 17:11:59 +0000 | [diff] [blame] | 1994 | MLX4_GET(dword_field, outbox, INIT_HCA_FLAGS_OFFSET); |
| 1995 | if (dword_field & (1 << INIT_HCA_DEVICE_MANAGED_FLOW_STEERING_EN)) { |
| 1996 | param->steering_mode = MLX4_STEERING_MODE_DEVICE_MANAGED; |
| 1997 | } else { |
| 1998 | MLX4_GET(byte_field, outbox, INIT_HCA_UC_STEERING_OFFSET); |
| 1999 | if (byte_field & 0x8) |
| 2000 | param->steering_mode = MLX4_STEERING_MODE_B0; |
| 2001 | else |
| 2002 | param->steering_mode = MLX4_STEERING_MODE_A0; |
| 2003 | } |
Ido Shamay | 802f42a | 2015-04-02 16:31:06 +0300 | [diff] [blame] | 2004 | |
| 2005 | if (dword_field & (1 << 13)) |
| 2006 | param->rss_ip_frags = 1; |
| 2007 | |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 2008 | /* steering attributes */ |
Jack Morgenstein | 7b8157b | 2012-12-06 17:11:59 +0000 | [diff] [blame] | 2009 | if (param->steering_mode == MLX4_STEERING_MODE_DEVICE_MANAGED) { |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 2010 | MLX4_GET(param->mc_base, outbox, INIT_HCA_FS_BASE_OFFSET); |
| 2011 | MLX4_GET(param->log_mc_entry_sz, outbox, |
| 2012 | INIT_HCA_FS_LOG_ENTRY_SZ_OFFSET); |
| 2013 | MLX4_GET(param->log_mc_table_sz, outbox, |
| 2014 | INIT_HCA_FS_LOG_TABLE_SZ_OFFSET); |
Matan Barak | 7d077cd | 2014-12-11 10:58:00 +0200 | [diff] [blame] | 2015 | MLX4_GET(byte_field, outbox, |
| 2016 | INIT_HCA_FS_A0_OFFSET); |
| 2017 | param->dmfs_high_steer_mode = |
| 2018 | a0_dmfs_query_hw_steering[(byte_field >> 6) & 3]; |
Hadar Hen Zion | 0ff1fb6 | 2012-07-05 04:03:46 +0000 | [diff] [blame] | 2019 | } else { |
| 2020 | MLX4_GET(param->mc_base, outbox, INIT_HCA_MC_BASE_OFFSET); |
| 2021 | MLX4_GET(param->log_mc_entry_sz, outbox, |
| 2022 | INIT_HCA_LOG_MC_ENTRY_SZ_OFFSET); |
| 2023 | MLX4_GET(param->log_mc_hash_sz, outbox, |
| 2024 | INIT_HCA_LOG_MC_HASH_SZ_OFFSET); |
| 2025 | MLX4_GET(param->log_mc_table_sz, outbox, |
| 2026 | INIT_HCA_LOG_MC_TABLE_SZ_OFFSET); |
| 2027 | } |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 2028 | |
Or Gerlitz | 08ff323 | 2012-10-21 14:59:24 +0000 | [diff] [blame] | 2029 | /* CX3 is capable of extending CQEs/EQEs from 32 to 64 bytes */ |
| 2030 | MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_OFFSETS); |
| 2031 | if (byte_field & 0x20) /* 64-bytes eqe enabled */ |
| 2032 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_EQE_ENABLED; |
| 2033 | if (byte_field & 0x40) /* 64-bytes cqe enabled */ |
| 2034 | param->dev_cap_enabled |= MLX4_DEV_CAP_64B_CQE_ENABLED; |
| 2035 | |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 2036 | /* CX3 is capable of extending CQEs\EQEs to strides larger than 64B */ |
| 2037 | MLX4_GET(byte_field, outbox, INIT_HCA_EQE_CQE_STRIDE_OFFSET); |
| 2038 | if (byte_field) { |
Ido Shamay | c3f2511 | 2014-12-16 13:28:54 +0200 | [diff] [blame] | 2039 | param->dev_cap_enabled |= MLX4_DEV_CAP_EQE_STRIDE_ENABLED; |
| 2040 | param->dev_cap_enabled |= MLX4_DEV_CAP_CQE_STRIDE_ENABLED; |
Ido Shamay | 77507aa | 2014-09-18 11:50:59 +0300 | [diff] [blame] | 2041 | param->cqe_size = 1 << ((byte_field & |
| 2042 | MLX4_CQE_SIZE_MASK_STRIDE) + 5); |
| 2043 | param->eqe_size = 1 << (((byte_field & |
| 2044 | MLX4_EQE_SIZE_MASK_STRIDE) >> 4) + 5); |
| 2045 | } |
| 2046 | |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 2047 | /* TPT attributes */ |
| 2048 | |
| 2049 | MLX4_GET(param->dmpt_base, outbox, INIT_HCA_DMPT_BASE_OFFSET); |
Shani Michaeli | e448834 | 2013-02-06 16:19:11 +0000 | [diff] [blame] | 2050 | MLX4_GET(param->mw_enabled, outbox, INIT_HCA_TPT_MW_OFFSET); |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 2051 | MLX4_GET(param->log_mpt_sz, outbox, INIT_HCA_LOG_MPT_SZ_OFFSET); |
| 2052 | MLX4_GET(param->mtt_base, outbox, INIT_HCA_MTT_BASE_OFFSET); |
| 2053 | MLX4_GET(param->cmpt_base, outbox, INIT_HCA_CMPT_BASE_OFFSET); |
| 2054 | |
| 2055 | /* UAR attributes */ |
| 2056 | |
| 2057 | MLX4_GET(param->uar_page_sz, outbox, INIT_HCA_UAR_PAGE_SZ_OFFSET); |
| 2058 | MLX4_GET(param->log_uar_sz, outbox, INIT_HCA_LOG_UAR_SZ_OFFSET); |
| 2059 | |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 2060 | /* phv_check enable */ |
| 2061 | MLX4_GET(byte_field, outbox, INIT_HCA_CACHELINE_SZ_OFFSET); |
| 2062 | if (byte_field & 0x2) |
| 2063 | param->phv_check_en = 1; |
Jack Morgenstein | ab9c17a | 2011-12-13 04:18:30 +0000 | [diff] [blame] | 2064 | out: |
| 2065 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2066 | |
| 2067 | return err; |
| 2068 | } |
| 2069 | |
Majd Dibbiny | 6d6e996 | 2015-01-27 15:58:09 +0200 | [diff] [blame] | 2070 | static int mlx4_hca_core_clock_update(struct mlx4_dev *dev) |
| 2071 | { |
| 2072 | struct mlx4_cmd_mailbox *mailbox; |
| 2073 | __be32 *outbox; |
| 2074 | int err; |
| 2075 | |
| 2076 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2077 | if (IS_ERR(mailbox)) { |
| 2078 | mlx4_warn(dev, "hca_core_clock mailbox allocation failed\n"); |
| 2079 | return PTR_ERR(mailbox); |
| 2080 | } |
| 2081 | outbox = mailbox->buf; |
| 2082 | |
| 2083 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 2084 | MLX4_CMD_QUERY_HCA, |
| 2085 | MLX4_CMD_TIME_CLASS_B, |
| 2086 | !mlx4_is_slave(dev)); |
| 2087 | if (err) { |
| 2088 | mlx4_warn(dev, "hca_core_clock update failed\n"); |
| 2089 | goto out; |
| 2090 | } |
| 2091 | |
| 2092 | MLX4_GET(dev->caps.hca_core_clock, outbox, QUERY_HCA_CORE_CLOCK_OFFSET); |
| 2093 | |
| 2094 | out: |
| 2095 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2096 | |
| 2097 | return err; |
| 2098 | } |
| 2099 | |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 2100 | /* for IB-type ports only in SRIOV mode. Checks that both proxy QP0 |
| 2101 | * and real QP0 are active, so that the paravirtualized QP0 is ready |
| 2102 | * to operate */ |
| 2103 | static int check_qp0_state(struct mlx4_dev *dev, int function, int port) |
| 2104 | { |
| 2105 | struct mlx4_priv *priv = mlx4_priv(dev); |
| 2106 | /* irrelevant if not infiniband */ |
| 2107 | if (priv->mfunc.master.qp0_state[port].proxy_qp0_active && |
| 2108 | priv->mfunc.master.qp0_state[port].qp0_active) |
| 2109 | return 1; |
| 2110 | return 0; |
| 2111 | } |
| 2112 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 2113 | int mlx4_INIT_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 2114 | struct mlx4_vhcr *vhcr, |
| 2115 | struct mlx4_cmd_mailbox *inbox, |
| 2116 | struct mlx4_cmd_mailbox *outbox, |
| 2117 | struct mlx4_cmd_info *cmd) |
| 2118 | { |
| 2119 | struct mlx4_priv *priv = mlx4_priv(dev); |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 2120 | int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 2121 | int err; |
| 2122 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 2123 | if (port < 0) |
| 2124 | return -EINVAL; |
| 2125 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 2126 | if (priv->mfunc.master.slave_state[slave].init_port_mask & (1 << port)) |
| 2127 | return 0; |
| 2128 | |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 2129 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
| 2130 | /* Enable port only if it was previously disabled */ |
| 2131 | if (!priv->mfunc.master.init_port_ref[port]) { |
| 2132 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 2133 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2134 | if (err) |
| 2135 | return err; |
| 2136 | } |
| 2137 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 2138 | } else { |
| 2139 | if (slave == mlx4_master_func_num(dev)) { |
| 2140 | if (check_qp0_state(dev, slave, port) && |
| 2141 | !priv->mfunc.master.qp0_state[port].port_active) { |
| 2142 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
| 2143 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2144 | if (err) |
| 2145 | return err; |
| 2146 | priv->mfunc.master.qp0_state[port].port_active = 1; |
| 2147 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
| 2148 | } |
| 2149 | } else |
| 2150 | priv->mfunc.master.slave_state[slave].init_port_mask |= (1 << port); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 2151 | } |
| 2152 | ++priv->mfunc.master.init_port_ref[port]; |
| 2153 | return 0; |
| 2154 | } |
| 2155 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 2156 | int mlx4_INIT_PORT(struct mlx4_dev *dev, int port) |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2157 | { |
| 2158 | struct mlx4_cmd_mailbox *mailbox; |
| 2159 | u32 *inbox; |
| 2160 | int err; |
| 2161 | u32 flags; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 2162 | u16 field; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2163 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 2164 | if (dev->flags & MLX4_FLAG_OLD_PORT_CMDS) { |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2165 | #define INIT_PORT_IN_SIZE 256 |
| 2166 | #define INIT_PORT_FLAGS_OFFSET 0x00 |
| 2167 | #define INIT_PORT_FLAG_SIG (1 << 18) |
| 2168 | #define INIT_PORT_FLAG_NG (1 << 17) |
| 2169 | #define INIT_PORT_FLAG_G0 (1 << 16) |
| 2170 | #define INIT_PORT_VL_SHIFT 4 |
| 2171 | #define INIT_PORT_PORT_WIDTH_SHIFT 8 |
| 2172 | #define INIT_PORT_MTU_OFFSET 0x04 |
| 2173 | #define INIT_PORT_MAX_GID_OFFSET 0x06 |
| 2174 | #define INIT_PORT_MAX_PKEY_OFFSET 0x0a |
| 2175 | #define INIT_PORT_GUID0_OFFSET 0x10 |
| 2176 | #define INIT_PORT_NODE_GUID_OFFSET 0x18 |
| 2177 | #define INIT_PORT_SI_GUID_OFFSET 0x20 |
| 2178 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 2179 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2180 | if (IS_ERR(mailbox)) |
| 2181 | return PTR_ERR(mailbox); |
| 2182 | inbox = mailbox->buf; |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2183 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 2184 | flags = 0; |
| 2185 | flags |= (dev->caps.vl_cap[port] & 0xf) << INIT_PORT_VL_SHIFT; |
| 2186 | flags |= (dev->caps.port_width_cap[port] & 0xf) << INIT_PORT_PORT_WIDTH_SHIFT; |
| 2187 | MLX4_PUT(inbox, flags, INIT_PORT_FLAGS_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2188 | |
Yevgeny Petrilin | b79acb4 | 2008-10-22 10:56:48 -0700 | [diff] [blame] | 2189 | field = 128 << dev->caps.ib_mtu_cap[port]; |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 2190 | MLX4_PUT(inbox, field, INIT_PORT_MTU_OFFSET); |
| 2191 | field = dev->caps.gid_table_len[port]; |
| 2192 | MLX4_PUT(inbox, field, INIT_PORT_MAX_GID_OFFSET); |
| 2193 | field = dev->caps.pkey_table_len[port]; |
| 2194 | MLX4_PUT(inbox, field, INIT_PORT_MAX_PKEY_OFFSET); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2195 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 2196 | err = mlx4_cmd(dev, mailbox->dma, port, 0, MLX4_CMD_INIT_PORT, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 2197 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2198 | |
Roland Dreier | 5ae2a7a | 2007-06-18 08:15:02 -0700 | [diff] [blame] | 2199 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2200 | } else |
| 2201 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_INIT_PORT, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 2202 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2203 | |
Majd Dibbiny | 6d6e996 | 2015-01-27 15:58:09 +0200 | [diff] [blame] | 2204 | if (!err) |
| 2205 | mlx4_hca_core_clock_update(dev); |
| 2206 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2207 | return err; |
| 2208 | } |
| 2209 | EXPORT_SYMBOL_GPL(mlx4_INIT_PORT); |
| 2210 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 2211 | int mlx4_CLOSE_PORT_wrapper(struct mlx4_dev *dev, int slave, |
| 2212 | struct mlx4_vhcr *vhcr, |
| 2213 | struct mlx4_cmd_mailbox *inbox, |
| 2214 | struct mlx4_cmd_mailbox *outbox, |
| 2215 | struct mlx4_cmd_info *cmd) |
| 2216 | { |
| 2217 | struct mlx4_priv *priv = mlx4_priv(dev); |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 2218 | int port = mlx4_slave_convert_port(dev, slave, vhcr->in_modifier); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 2219 | int err; |
| 2220 | |
Matan Barak | 449fc48 | 2014-03-19 18:11:52 +0200 | [diff] [blame] | 2221 | if (port < 0) |
| 2222 | return -EINVAL; |
| 2223 | |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 2224 | if (!(priv->mfunc.master.slave_state[slave].init_port_mask & |
| 2225 | (1 << port))) |
| 2226 | return 0; |
| 2227 | |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 2228 | if (dev->caps.port_mask[port] != MLX4_PORT_TYPE_IB) { |
| 2229 | if (priv->mfunc.master.init_port_ref[port] == 1) { |
| 2230 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
Jack Morgenstein | 5a03108 | 2015-01-27 15:58:02 +0200 | [diff] [blame] | 2231 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 2232 | if (err) |
| 2233 | return err; |
| 2234 | } |
| 2235 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 2236 | } else { |
| 2237 | /* infiniband port */ |
| 2238 | if (slave == mlx4_master_func_num(dev)) { |
| 2239 | if (!priv->mfunc.master.qp0_state[port].qp0_active && |
| 2240 | priv->mfunc.master.qp0_state[port].port_active) { |
| 2241 | err = mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
Jack Morgenstein | 5a03108 | 2015-01-27 15:58:02 +0200 | [diff] [blame] | 2242 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Jack Morgenstein | 980e900 | 2012-08-03 08:40:53 +0000 | [diff] [blame] | 2243 | if (err) |
| 2244 | return err; |
| 2245 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
| 2246 | priv->mfunc.master.qp0_state[port].port_active = 0; |
| 2247 | } |
| 2248 | } else |
| 2249 | priv->mfunc.master.slave_state[slave].init_port_mask &= ~(1 << port); |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 2250 | } |
Marcel Apfelbaum | 5cc914f | 2011-12-13 04:12:40 +0000 | [diff] [blame] | 2251 | --priv->mfunc.master.init_port_ref[port]; |
| 2252 | return 0; |
| 2253 | } |
| 2254 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2255 | int mlx4_CLOSE_PORT(struct mlx4_dev *dev, int port) |
| 2256 | { |
Jack Morgenstein | 5a03108 | 2015-01-27 15:58:02 +0200 | [diff] [blame] | 2257 | return mlx4_cmd(dev, 0, port, 0, MLX4_CMD_CLOSE_PORT, |
| 2258 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_WRAPPED); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2259 | } |
| 2260 | EXPORT_SYMBOL_GPL(mlx4_CLOSE_PORT); |
| 2261 | |
| 2262 | int mlx4_CLOSE_HCA(struct mlx4_dev *dev, int panic) |
| 2263 | { |
Jack Morgenstein | 5a03108 | 2015-01-27 15:58:02 +0200 | [diff] [blame] | 2264 | return mlx4_cmd(dev, 0, 0, panic, MLX4_CMD_CLOSE_HCA, |
| 2265 | MLX4_CMD_TIME_CLASS_C, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2266 | } |
| 2267 | |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 2268 | struct mlx4_config_dev { |
| 2269 | __be32 update_flags; |
Matan Barak | d475c95 | 2014-11-02 16:26:17 +0200 | [diff] [blame] | 2270 | __be32 rsvd1[3]; |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 2271 | __be16 vxlan_udp_dport; |
| 2272 | __be16 rsvd2; |
Moni Shoua | fca8300 | 2016-01-14 17:50:36 +0200 | [diff] [blame] | 2273 | __be16 roce_v2_entropy; |
| 2274 | __be16 roce_v2_udp_dport; |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 2275 | __be32 roce_flags; |
| 2276 | __be32 rsvd4[25]; |
| 2277 | __be16 rsvd5; |
| 2278 | u8 rsvd6; |
Matan Barak | d475c95 | 2014-11-02 16:26:17 +0200 | [diff] [blame] | 2279 | u8 rx_checksum_val; |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 2280 | }; |
| 2281 | |
| 2282 | #define MLX4_VXLAN_UDP_DPORT (1 << 0) |
Moni Shoua | fca8300 | 2016-01-14 17:50:36 +0200 | [diff] [blame] | 2283 | #define MLX4_ROCE_V2_UDP_DPORT BIT(3) |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 2284 | #define MLX4_DISABLE_RX_PORT BIT(18) |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 2285 | |
Matan Barak | d475c95 | 2014-11-02 16:26:17 +0200 | [diff] [blame] | 2286 | static int mlx4_CONFIG_DEV_set(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 2287 | { |
| 2288 | int err; |
| 2289 | struct mlx4_cmd_mailbox *mailbox; |
| 2290 | |
| 2291 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2292 | if (IS_ERR(mailbox)) |
| 2293 | return PTR_ERR(mailbox); |
| 2294 | |
| 2295 | memcpy(mailbox->buf, config_dev, sizeof(*config_dev)); |
| 2296 | |
| 2297 | err = mlx4_cmd(dev, mailbox->dma, 0, 0, MLX4_CMD_CONFIG_DEV, |
| 2298 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2299 | |
| 2300 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2301 | return err; |
| 2302 | } |
| 2303 | |
Matan Barak | d475c95 | 2014-11-02 16:26:17 +0200 | [diff] [blame] | 2304 | static int mlx4_CONFIG_DEV_get(struct mlx4_dev *dev, struct mlx4_config_dev *config_dev) |
| 2305 | { |
| 2306 | int err; |
| 2307 | struct mlx4_cmd_mailbox *mailbox; |
| 2308 | |
| 2309 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2310 | if (IS_ERR(mailbox)) |
| 2311 | return PTR_ERR(mailbox); |
| 2312 | |
| 2313 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 1, MLX4_CMD_CONFIG_DEV, |
| 2314 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
| 2315 | |
| 2316 | if (!err) |
| 2317 | memcpy(config_dev, mailbox->buf, sizeof(*config_dev)); |
| 2318 | |
| 2319 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2320 | return err; |
| 2321 | } |
| 2322 | |
| 2323 | /* Conversion between the HW values and the actual functionality. |
| 2324 | * The value represented by the array index, |
| 2325 | * and the functionality determined by the flags. |
| 2326 | */ |
| 2327 | static const u8 config_dev_csum_flags[] = { |
| 2328 | [0] = 0, |
| 2329 | [1] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP, |
| 2330 | [2] = MLX4_RX_CSUM_MODE_VAL_NON_TCP_UDP | |
| 2331 | MLX4_RX_CSUM_MODE_L4, |
| 2332 | [3] = MLX4_RX_CSUM_MODE_L4 | |
| 2333 | MLX4_RX_CSUM_MODE_IP_OK_IP_NON_TCP_UDP | |
| 2334 | MLX4_RX_CSUM_MODE_MULTI_VLAN |
| 2335 | }; |
| 2336 | |
| 2337 | int mlx4_config_dev_retrieval(struct mlx4_dev *dev, |
| 2338 | struct mlx4_config_dev_params *params) |
| 2339 | { |
Maor Gottlieb | 6af0a52 | 2015-02-03 17:57:16 +0200 | [diff] [blame] | 2340 | struct mlx4_config_dev config_dev = {0}; |
Matan Barak | d475c95 | 2014-11-02 16:26:17 +0200 | [diff] [blame] | 2341 | int err; |
| 2342 | u8 csum_mask; |
| 2343 | |
| 2344 | #define CONFIG_DEV_RX_CSUM_MODE_MASK 0x7 |
| 2345 | #define CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET 0 |
| 2346 | #define CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET 4 |
| 2347 | |
| 2348 | if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_CONFIG_DEV)) |
| 2349 | return -ENOTSUPP; |
| 2350 | |
| 2351 | err = mlx4_CONFIG_DEV_get(dev, &config_dev); |
| 2352 | if (err) |
| 2353 | return err; |
| 2354 | |
| 2355 | csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT1_BIT_OFFSET) & |
| 2356 | CONFIG_DEV_RX_CSUM_MODE_MASK; |
| 2357 | |
| 2358 | if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) |
| 2359 | return -EINVAL; |
| 2360 | params->rx_csum_flags_port_1 = config_dev_csum_flags[csum_mask]; |
| 2361 | |
| 2362 | csum_mask = (config_dev.rx_checksum_val >> CONFIG_DEV_RX_CSUM_MODE_PORT2_BIT_OFFSET) & |
| 2363 | CONFIG_DEV_RX_CSUM_MODE_MASK; |
| 2364 | |
| 2365 | if (csum_mask >= sizeof(config_dev_csum_flags)/sizeof(config_dev_csum_flags[0])) |
| 2366 | return -EINVAL; |
| 2367 | params->rx_csum_flags_port_2 = config_dev_csum_flags[csum_mask]; |
| 2368 | |
| 2369 | params->vxlan_udp_dport = be16_to_cpu(config_dev.vxlan_udp_dport); |
| 2370 | |
| 2371 | return 0; |
| 2372 | } |
| 2373 | EXPORT_SYMBOL_GPL(mlx4_config_dev_retrieval); |
| 2374 | |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 2375 | int mlx4_config_vxlan_port(struct mlx4_dev *dev, __be16 udp_port) |
| 2376 | { |
| 2377 | struct mlx4_config_dev config_dev; |
| 2378 | |
| 2379 | memset(&config_dev, 0, sizeof(config_dev)); |
| 2380 | config_dev.update_flags = cpu_to_be32(MLX4_VXLAN_UDP_DPORT); |
| 2381 | config_dev.vxlan_udp_dport = udp_port; |
| 2382 | |
Matan Barak | d475c95 | 2014-11-02 16:26:17 +0200 | [diff] [blame] | 2383 | return mlx4_CONFIG_DEV_set(dev, &config_dev); |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 2384 | } |
| 2385 | EXPORT_SYMBOL_GPL(mlx4_config_vxlan_port); |
| 2386 | |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 2387 | #define CONFIG_DISABLE_RX_PORT BIT(15) |
| 2388 | int mlx4_disable_rx_port_check(struct mlx4_dev *dev, bool dis) |
| 2389 | { |
| 2390 | struct mlx4_config_dev config_dev; |
| 2391 | |
| 2392 | memset(&config_dev, 0, sizeof(config_dev)); |
| 2393 | config_dev.update_flags = cpu_to_be32(MLX4_DISABLE_RX_PORT); |
| 2394 | if (dis) |
| 2395 | config_dev.roce_flags = |
| 2396 | cpu_to_be32(CONFIG_DISABLE_RX_PORT); |
| 2397 | |
| 2398 | return mlx4_CONFIG_DEV_set(dev, &config_dev); |
| 2399 | } |
| 2400 | |
Moni Shoua | fca8300 | 2016-01-14 17:50:36 +0200 | [diff] [blame] | 2401 | int mlx4_config_roce_v2_port(struct mlx4_dev *dev, u16 udp_port) |
| 2402 | { |
| 2403 | struct mlx4_config_dev config_dev; |
| 2404 | |
| 2405 | memset(&config_dev, 0, sizeof(config_dev)); |
| 2406 | config_dev.update_flags = cpu_to_be32(MLX4_ROCE_V2_UDP_DPORT); |
| 2407 | config_dev.roce_v2_udp_dport = cpu_to_be16(udp_port); |
| 2408 | |
| 2409 | return mlx4_CONFIG_DEV_set(dev, &config_dev); |
| 2410 | } |
| 2411 | EXPORT_SYMBOL_GPL(mlx4_config_roce_v2_port); |
| 2412 | |
Moni Shoua | 59e14e3 | 2015-02-03 16:48:32 +0200 | [diff] [blame] | 2413 | int mlx4_virt2phy_port_map(struct mlx4_dev *dev, u32 port1, u32 port2) |
| 2414 | { |
| 2415 | struct mlx4_cmd_mailbox *mailbox; |
| 2416 | struct { |
| 2417 | __be32 v_port1; |
| 2418 | __be32 v_port2; |
| 2419 | } *v2p; |
| 2420 | int err; |
| 2421 | |
| 2422 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2423 | if (IS_ERR(mailbox)) |
| 2424 | return -ENOMEM; |
| 2425 | |
| 2426 | v2p = mailbox->buf; |
| 2427 | v2p->v_port1 = cpu_to_be32(port1); |
| 2428 | v2p->v_port2 = cpu_to_be32(port2); |
| 2429 | |
| 2430 | err = mlx4_cmd(dev, mailbox->dma, 0, |
| 2431 | MLX4_SET_PORT_VIRT2PHY, MLX4_CMD_VIRT_PORT_MAP, |
| 2432 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2433 | |
| 2434 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2435 | return err; |
| 2436 | } |
| 2437 | |
Or Gerlitz | d18f141 | 2014-03-27 14:02:03 +0200 | [diff] [blame] | 2438 | |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2439 | int mlx4_SET_ICM_SIZE(struct mlx4_dev *dev, u64 icm_size, u64 *aux_pages) |
| 2440 | { |
| 2441 | int ret = mlx4_cmd_imm(dev, icm_size, aux_pages, 0, 0, |
| 2442 | MLX4_CMD_SET_ICM_SIZE, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 2443 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2444 | if (ret) |
| 2445 | return ret; |
| 2446 | |
| 2447 | /* |
| 2448 | * Round up number of system pages needed in case |
| 2449 | * MLX4_ICM_PAGE_SIZE < PAGE_SIZE. |
| 2450 | */ |
| 2451 | *aux_pages = ALIGN(*aux_pages, PAGE_SIZE / MLX4_ICM_PAGE_SIZE) >> |
| 2452 | (PAGE_SHIFT - MLX4_ICM_PAGE_SHIFT); |
| 2453 | |
| 2454 | return 0; |
| 2455 | } |
| 2456 | |
| 2457 | int mlx4_NOP(struct mlx4_dev *dev) |
| 2458 | { |
| 2459 | /* Input modifier of 0x1f means "finish as soon as possible." */ |
Jack Morgenstein | 5a03108 | 2015-01-27 15:58:02 +0200 | [diff] [blame] | 2460 | return mlx4_cmd(dev, 0, 0x1f, 0, MLX4_CMD_NOP, MLX4_CMD_TIME_CLASS_A, |
| 2461 | MLX4_CMD_NATIVE); |
Roland Dreier | 225c7b1 | 2007-05-08 18:00:38 -0700 | [diff] [blame] | 2462 | } |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 2463 | |
Mark Bloch | bfaf316 | 2016-07-19 20:54:57 +0300 | [diff] [blame] | 2464 | int mlx4_query_diag_counters(struct mlx4_dev *dev, u8 op_modifier, |
| 2465 | const u32 offset[], |
| 2466 | u32 value[], size_t array_len, u8 port) |
| 2467 | { |
| 2468 | struct mlx4_cmd_mailbox *mailbox; |
| 2469 | u32 *outbox; |
| 2470 | size_t i; |
| 2471 | int ret; |
| 2472 | |
| 2473 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2474 | if (IS_ERR(mailbox)) |
| 2475 | return PTR_ERR(mailbox); |
| 2476 | |
| 2477 | outbox = mailbox->buf; |
| 2478 | |
| 2479 | ret = mlx4_cmd_box(dev, 0, mailbox->dma, port, op_modifier, |
| 2480 | MLX4_CMD_DIAG_RPRT, MLX4_CMD_TIME_CLASS_A, |
| 2481 | MLX4_CMD_NATIVE); |
| 2482 | if (ret) |
| 2483 | goto out; |
| 2484 | |
| 2485 | for (i = 0; i < array_len; i++) { |
| 2486 | if (offset[i] > MLX4_MAILBOX_SIZE) { |
| 2487 | ret = -EINVAL; |
| 2488 | goto out; |
| 2489 | } |
| 2490 | |
| 2491 | MLX4_GET(value[i], outbox, offset[i]); |
| 2492 | } |
| 2493 | |
| 2494 | out: |
| 2495 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2496 | return ret; |
| 2497 | } |
| 2498 | EXPORT_SYMBOL(mlx4_query_diag_counters); |
| 2499 | |
Hadar Hen Zion | 8e1a28e | 2013-12-19 21:20:12 +0200 | [diff] [blame] | 2500 | int mlx4_get_phys_port_id(struct mlx4_dev *dev) |
| 2501 | { |
| 2502 | u8 port; |
| 2503 | u32 *outbox; |
| 2504 | struct mlx4_cmd_mailbox *mailbox; |
| 2505 | u32 in_mod; |
| 2506 | u32 guid_hi, guid_lo; |
| 2507 | int err, ret = 0; |
| 2508 | #define MOD_STAT_CFG_PORT_OFFSET 8 |
| 2509 | #define MOD_STAT_CFG_GUID_H 0X14 |
| 2510 | #define MOD_STAT_CFG_GUID_L 0X1c |
| 2511 | |
| 2512 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2513 | if (IS_ERR(mailbox)) |
| 2514 | return PTR_ERR(mailbox); |
| 2515 | outbox = mailbox->buf; |
| 2516 | |
| 2517 | for (port = 1; port <= dev->caps.num_ports; port++) { |
| 2518 | in_mod = port << MOD_STAT_CFG_PORT_OFFSET; |
| 2519 | err = mlx4_cmd_box(dev, 0, mailbox->dma, in_mod, 0x2, |
| 2520 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
| 2521 | MLX4_CMD_NATIVE); |
| 2522 | if (err) { |
| 2523 | mlx4_err(dev, "Fail to get port %d uplink guid\n", |
| 2524 | port); |
| 2525 | ret = err; |
| 2526 | } else { |
| 2527 | MLX4_GET(guid_hi, outbox, MOD_STAT_CFG_GUID_H); |
| 2528 | MLX4_GET(guid_lo, outbox, MOD_STAT_CFG_GUID_L); |
| 2529 | dev->caps.phys_port_id[port] = (u64)guid_lo | |
| 2530 | (u64)guid_hi << 32; |
| 2531 | } |
| 2532 | } |
| 2533 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2534 | return ret; |
| 2535 | } |
| 2536 | |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 2537 | #define MLX4_WOL_SETUP_MODE (5 << 28) |
| 2538 | int mlx4_wol_read(struct mlx4_dev *dev, u64 *config, int port) |
| 2539 | { |
| 2540 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; |
| 2541 | |
| 2542 | return mlx4_cmd_imm(dev, 0, config, in_mod, 0x3, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 2543 | MLX4_CMD_MOD_STAT_CFG, MLX4_CMD_TIME_CLASS_A, |
| 2544 | MLX4_CMD_NATIVE); |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 2545 | } |
| 2546 | EXPORT_SYMBOL_GPL(mlx4_wol_read); |
| 2547 | |
| 2548 | int mlx4_wol_write(struct mlx4_dev *dev, u64 config, int port) |
| 2549 | { |
| 2550 | u32 in_mod = MLX4_WOL_SETUP_MODE | port << 8; |
| 2551 | |
| 2552 | return mlx4_cmd(dev, config, in_mod, 0x1, MLX4_CMD_MOD_STAT_CFG, |
Jack Morgenstein | f9baff5 | 2011-12-13 04:10:51 +0000 | [diff] [blame] | 2553 | MLX4_CMD_TIME_CLASS_A, MLX4_CMD_NATIVE); |
Yevgeny Petrilin | 14c07b1 | 2011-03-22 22:37:59 +0000 | [diff] [blame] | 2554 | } |
| 2555 | EXPORT_SYMBOL_GPL(mlx4_wol_write); |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 2556 | |
| 2557 | enum { |
| 2558 | ADD_TO_MCG = 0x26, |
| 2559 | }; |
| 2560 | |
| 2561 | |
| 2562 | void mlx4_opreq_action(struct work_struct *work) |
| 2563 | { |
| 2564 | struct mlx4_priv *priv = container_of(work, struct mlx4_priv, |
| 2565 | opreq_task); |
| 2566 | struct mlx4_dev *dev = &priv->dev; |
| 2567 | int num_tasks = atomic_read(&priv->opreq_count); |
| 2568 | struct mlx4_cmd_mailbox *mailbox; |
| 2569 | struct mlx4_mgm *mgm; |
| 2570 | u32 *outbox; |
| 2571 | u32 modifier; |
| 2572 | u16 token; |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 2573 | u16 type; |
| 2574 | int err; |
| 2575 | u32 num_qps; |
| 2576 | struct mlx4_qp qp; |
| 2577 | int i; |
| 2578 | u8 rem_mcg; |
| 2579 | u8 prot; |
| 2580 | |
| 2581 | #define GET_OP_REQ_MODIFIER_OFFSET 0x08 |
| 2582 | #define GET_OP_REQ_TOKEN_OFFSET 0x14 |
| 2583 | #define GET_OP_REQ_TYPE_OFFSET 0x1a |
| 2584 | #define GET_OP_REQ_DATA_OFFSET 0x20 |
| 2585 | |
| 2586 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2587 | if (IS_ERR(mailbox)) { |
| 2588 | mlx4_err(dev, "Failed to allocate mailbox for GET_OP_REQ\n"); |
| 2589 | return; |
| 2590 | } |
| 2591 | outbox = mailbox->buf; |
| 2592 | |
| 2593 | while (num_tasks) { |
| 2594 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0, 0, |
| 2595 | MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, |
| 2596 | MLX4_CMD_NATIVE); |
| 2597 | if (err) { |
Masanari Iida | 6d3be30 | 2013-09-30 23:19:09 +0900 | [diff] [blame] | 2598 | mlx4_err(dev, "Failed to retrieve required operation: %d\n", |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 2599 | err); |
| 2600 | return; |
| 2601 | } |
| 2602 | MLX4_GET(modifier, outbox, GET_OP_REQ_MODIFIER_OFFSET); |
| 2603 | MLX4_GET(token, outbox, GET_OP_REQ_TOKEN_OFFSET); |
| 2604 | MLX4_GET(type, outbox, GET_OP_REQ_TYPE_OFFSET); |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 2605 | type &= 0xfff; |
| 2606 | |
| 2607 | switch (type) { |
| 2608 | case ADD_TO_MCG: |
| 2609 | if (dev->caps.steering_mode == |
| 2610 | MLX4_STEERING_MODE_DEVICE_MANAGED) { |
| 2611 | mlx4_warn(dev, "ADD MCG operation is not supported in DEVICE_MANAGED steering mode\n"); |
| 2612 | err = EPERM; |
| 2613 | break; |
| 2614 | } |
| 2615 | mgm = (struct mlx4_mgm *)((u8 *)(outbox) + |
| 2616 | GET_OP_REQ_DATA_OFFSET); |
| 2617 | num_qps = be32_to_cpu(mgm->members_count) & |
| 2618 | MGM_QPN_MASK; |
| 2619 | rem_mcg = ((u8 *)(&mgm->members_count))[0] & 1; |
| 2620 | prot = ((u8 *)(&mgm->members_count))[0] >> 6; |
| 2621 | |
| 2622 | for (i = 0; i < num_qps; i++) { |
| 2623 | qp.qpn = be32_to_cpu(mgm->qp[i]); |
| 2624 | if (rem_mcg) |
| 2625 | err = mlx4_multicast_detach(dev, &qp, |
| 2626 | mgm->gid, |
| 2627 | prot, 0); |
| 2628 | else |
| 2629 | err = mlx4_multicast_attach(dev, &qp, |
| 2630 | mgm->gid, |
| 2631 | mgm->gid[5] |
| 2632 | , 0, prot, |
| 2633 | NULL); |
| 2634 | if (err) |
| 2635 | break; |
| 2636 | } |
| 2637 | break; |
| 2638 | default: |
| 2639 | mlx4_warn(dev, "Bad type for required operation\n"); |
| 2640 | err = EINVAL; |
| 2641 | break; |
| 2642 | } |
Eyal Perry | 28d222b | 2014-03-02 10:25:03 +0200 | [diff] [blame] | 2643 | err = mlx4_cmd(dev, 0, ((u32) err | |
| 2644 | (__force u32)cpu_to_be32(token) << 16), |
Yevgeny Petrilin | fe6f700 | 2013-07-28 18:54:21 +0300 | [diff] [blame] | 2645 | 1, MLX4_CMD_GET_OP_REQ, MLX4_CMD_TIME_CLASS_A, |
| 2646 | MLX4_CMD_NATIVE); |
| 2647 | if (err) { |
| 2648 | mlx4_err(dev, "Failed to acknowledge required request: %d\n", |
| 2649 | err); |
| 2650 | goto out; |
| 2651 | } |
| 2652 | memset(outbox, 0, 0xffc); |
| 2653 | num_tasks = atomic_dec_return(&priv->opreq_count); |
| 2654 | } |
| 2655 | |
| 2656 | out: |
| 2657 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2658 | } |
Jack Morgenstein | 114840c | 2014-06-01 11:53:50 +0300 | [diff] [blame] | 2659 | |
| 2660 | static int mlx4_check_smp_firewall_active(struct mlx4_dev *dev, |
| 2661 | struct mlx4_cmd_mailbox *mailbox) |
| 2662 | { |
| 2663 | #define MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET 0x10 |
| 2664 | #define MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET 0x20 |
| 2665 | #define MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET 0x40 |
| 2666 | #define MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET 0x70 |
| 2667 | |
| 2668 | u32 set_attr_mask, getresp_attr_mask; |
| 2669 | u32 trap_attr_mask, traprepress_attr_mask; |
| 2670 | |
| 2671 | MLX4_GET(set_attr_mask, mailbox->buf, |
| 2672 | MLX4_CMD_MAD_DEMUX_SET_ATTR_OFFSET); |
| 2673 | mlx4_dbg(dev, "SMP firewall set_attribute_mask = 0x%x\n", |
| 2674 | set_attr_mask); |
| 2675 | |
| 2676 | MLX4_GET(getresp_attr_mask, mailbox->buf, |
| 2677 | MLX4_CMD_MAD_DEMUX_GETRESP_ATTR_OFFSET); |
| 2678 | mlx4_dbg(dev, "SMP firewall getresp_attribute_mask = 0x%x\n", |
| 2679 | getresp_attr_mask); |
| 2680 | |
| 2681 | MLX4_GET(trap_attr_mask, mailbox->buf, |
| 2682 | MLX4_CMD_MAD_DEMUX_TRAP_ATTR_OFFSET); |
| 2683 | mlx4_dbg(dev, "SMP firewall trap_attribute_mask = 0x%x\n", |
| 2684 | trap_attr_mask); |
| 2685 | |
| 2686 | MLX4_GET(traprepress_attr_mask, mailbox->buf, |
| 2687 | MLX4_CMD_MAD_DEMUX_TRAP_REPRESS_ATTR_OFFSET); |
| 2688 | mlx4_dbg(dev, "SMP firewall traprepress_attribute_mask = 0x%x\n", |
| 2689 | traprepress_attr_mask); |
| 2690 | |
| 2691 | if (set_attr_mask && getresp_attr_mask && trap_attr_mask && |
| 2692 | traprepress_attr_mask) |
| 2693 | return 1; |
| 2694 | |
| 2695 | return 0; |
| 2696 | } |
| 2697 | |
| 2698 | int mlx4_config_mad_demux(struct mlx4_dev *dev) |
| 2699 | { |
| 2700 | struct mlx4_cmd_mailbox *mailbox; |
| 2701 | int secure_host_active; |
| 2702 | int err; |
| 2703 | |
| 2704 | /* Check if mad_demux is supported */ |
| 2705 | if (!(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_MAD_DEMUX)) |
| 2706 | return 0; |
| 2707 | |
| 2708 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2709 | if (IS_ERR(mailbox)) { |
| 2710 | mlx4_warn(dev, "Failed to allocate mailbox for cmd MAD_DEMUX"); |
| 2711 | return -ENOMEM; |
| 2712 | } |
| 2713 | |
| 2714 | /* Query mad_demux to find out which MADs are handled by internal sma */ |
| 2715 | err = mlx4_cmd_box(dev, 0, mailbox->dma, 0x01 /* subn mgmt class */, |
| 2716 | MLX4_CMD_MAD_DEMUX_QUERY_RESTR, MLX4_CMD_MAD_DEMUX, |
| 2717 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2718 | if (err) { |
| 2719 | mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: query restrictions failed (%d)\n", |
| 2720 | err); |
| 2721 | goto out; |
| 2722 | } |
| 2723 | |
| 2724 | secure_host_active = mlx4_check_smp_firewall_active(dev, mailbox); |
| 2725 | |
| 2726 | /* Config mad_demux to handle all MADs returned by the query above */ |
| 2727 | err = mlx4_cmd(dev, mailbox->dma, 0x01 /* subn mgmt class */, |
| 2728 | MLX4_CMD_MAD_DEMUX_CONFIG, MLX4_CMD_MAD_DEMUX, |
| 2729 | MLX4_CMD_TIME_CLASS_B, MLX4_CMD_NATIVE); |
| 2730 | if (err) { |
| 2731 | mlx4_warn(dev, "MLX4_CMD_MAD_DEMUX: configure failed (%d)\n", err); |
| 2732 | goto out; |
| 2733 | } |
| 2734 | |
| 2735 | if (secure_host_active) |
| 2736 | mlx4_warn(dev, "HCA operating in secure-host mode. SMP firewall activated.\n"); |
| 2737 | out: |
| 2738 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2739 | return err; |
| 2740 | } |
Saeed Mahameed | adbc7ac | 2014-10-27 11:37:37 +0200 | [diff] [blame] | 2741 | |
| 2742 | /* Access Reg commands */ |
| 2743 | enum mlx4_access_reg_masks { |
| 2744 | MLX4_ACCESS_REG_STATUS_MASK = 0x7f, |
| 2745 | MLX4_ACCESS_REG_METHOD_MASK = 0x7f, |
| 2746 | MLX4_ACCESS_REG_LEN_MASK = 0x7ff |
| 2747 | }; |
| 2748 | |
| 2749 | struct mlx4_access_reg { |
| 2750 | __be16 constant1; |
| 2751 | u8 status; |
| 2752 | u8 resrvd1; |
| 2753 | __be16 reg_id; |
| 2754 | u8 method; |
| 2755 | u8 constant2; |
| 2756 | __be32 resrvd2[2]; |
| 2757 | __be16 len_const; |
| 2758 | __be16 resrvd3; |
| 2759 | #define MLX4_ACCESS_REG_HEADER_SIZE (20) |
| 2760 | u8 reg_data[MLX4_MAILBOX_SIZE-MLX4_ACCESS_REG_HEADER_SIZE]; |
| 2761 | } __attribute__((__packed__)); |
| 2762 | |
| 2763 | /** |
| 2764 | * mlx4_ACCESS_REG - Generic access reg command. |
| 2765 | * @dev: mlx4_dev. |
| 2766 | * @reg_id: register ID to access. |
| 2767 | * @method: Access method Read/Write. |
| 2768 | * @reg_len: register length to Read/Write in bytes. |
| 2769 | * @reg_data: reg_data pointer to Read/Write From/To. |
| 2770 | * |
| 2771 | * Access ConnectX registers FW command. |
| 2772 | * Returns 0 on success and copies outbox mlx4_access_reg data |
| 2773 | * field into reg_data or a negative error code. |
| 2774 | */ |
| 2775 | static int mlx4_ACCESS_REG(struct mlx4_dev *dev, u16 reg_id, |
| 2776 | enum mlx4_access_reg_method method, |
| 2777 | u16 reg_len, void *reg_data) |
| 2778 | { |
| 2779 | struct mlx4_cmd_mailbox *inbox, *outbox; |
| 2780 | struct mlx4_access_reg *inbuf, *outbuf; |
| 2781 | int err; |
| 2782 | |
| 2783 | inbox = mlx4_alloc_cmd_mailbox(dev); |
| 2784 | if (IS_ERR(inbox)) |
| 2785 | return PTR_ERR(inbox); |
| 2786 | |
| 2787 | outbox = mlx4_alloc_cmd_mailbox(dev); |
| 2788 | if (IS_ERR(outbox)) { |
| 2789 | mlx4_free_cmd_mailbox(dev, inbox); |
| 2790 | return PTR_ERR(outbox); |
| 2791 | } |
| 2792 | |
| 2793 | inbuf = inbox->buf; |
| 2794 | outbuf = outbox->buf; |
| 2795 | |
| 2796 | inbuf->constant1 = cpu_to_be16(0x1<<11 | 0x4); |
| 2797 | inbuf->constant2 = 0x1; |
| 2798 | inbuf->reg_id = cpu_to_be16(reg_id); |
| 2799 | inbuf->method = method & MLX4_ACCESS_REG_METHOD_MASK; |
| 2800 | |
| 2801 | reg_len = min(reg_len, (u16)(sizeof(inbuf->reg_data))); |
| 2802 | inbuf->len_const = |
| 2803 | cpu_to_be16(((reg_len/4 + 1) & MLX4_ACCESS_REG_LEN_MASK) | |
| 2804 | ((0x3) << 12)); |
| 2805 | |
| 2806 | memcpy(inbuf->reg_data, reg_data, reg_len); |
| 2807 | err = mlx4_cmd_box(dev, inbox->dma, outbox->dma, 0, 0, |
| 2808 | MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, |
Saeed Mahameed | 6e80669 | 2014-11-02 16:26:13 +0200 | [diff] [blame] | 2809 | MLX4_CMD_WRAPPED); |
Saeed Mahameed | adbc7ac | 2014-10-27 11:37:37 +0200 | [diff] [blame] | 2810 | if (err) |
| 2811 | goto out; |
| 2812 | |
| 2813 | if (outbuf->status & MLX4_ACCESS_REG_STATUS_MASK) { |
| 2814 | err = outbuf->status & MLX4_ACCESS_REG_STATUS_MASK; |
| 2815 | mlx4_err(dev, |
| 2816 | "MLX4_CMD_ACCESS_REG(%x) returned REG status (%x)\n", |
| 2817 | reg_id, err); |
| 2818 | goto out; |
| 2819 | } |
| 2820 | |
| 2821 | memcpy(reg_data, outbuf->reg_data, reg_len); |
| 2822 | out: |
| 2823 | mlx4_free_cmd_mailbox(dev, inbox); |
| 2824 | mlx4_free_cmd_mailbox(dev, outbox); |
| 2825 | return err; |
| 2826 | } |
| 2827 | |
| 2828 | /* ConnectX registers IDs */ |
| 2829 | enum mlx4_reg_id { |
| 2830 | MLX4_REG_ID_PTYS = 0x5004, |
| 2831 | }; |
| 2832 | |
| 2833 | /** |
| 2834 | * mlx4_ACCESS_PTYS_REG - Access PTYs (Port Type and Speed) |
| 2835 | * register |
| 2836 | * @dev: mlx4_dev. |
| 2837 | * @method: Access method Read/Write. |
| 2838 | * @ptys_reg: PTYS register data pointer. |
| 2839 | * |
| 2840 | * Access ConnectX PTYS register, to Read/Write Port Type/Speed |
| 2841 | * configuration |
| 2842 | * Returns 0 on success or a negative error code. |
| 2843 | */ |
| 2844 | int mlx4_ACCESS_PTYS_REG(struct mlx4_dev *dev, |
| 2845 | enum mlx4_access_reg_method method, |
| 2846 | struct mlx4_ptys_reg *ptys_reg) |
| 2847 | { |
| 2848 | return mlx4_ACCESS_REG(dev, MLX4_REG_ID_PTYS, |
| 2849 | method, sizeof(*ptys_reg), ptys_reg); |
| 2850 | } |
| 2851 | EXPORT_SYMBOL_GPL(mlx4_ACCESS_PTYS_REG); |
Saeed Mahameed | 6e80669 | 2014-11-02 16:26:13 +0200 | [diff] [blame] | 2852 | |
| 2853 | int mlx4_ACCESS_REG_wrapper(struct mlx4_dev *dev, int slave, |
| 2854 | struct mlx4_vhcr *vhcr, |
| 2855 | struct mlx4_cmd_mailbox *inbox, |
| 2856 | struct mlx4_cmd_mailbox *outbox, |
| 2857 | struct mlx4_cmd_info *cmd) |
| 2858 | { |
| 2859 | struct mlx4_access_reg *inbuf = inbox->buf; |
| 2860 | u8 method = inbuf->method & MLX4_ACCESS_REG_METHOD_MASK; |
| 2861 | u16 reg_id = be16_to_cpu(inbuf->reg_id); |
| 2862 | |
| 2863 | if (slave != mlx4_master_func_num(dev) && |
| 2864 | method == MLX4_ACCESS_REG_WRITE) |
| 2865 | return -EPERM; |
| 2866 | |
| 2867 | if (reg_id == MLX4_REG_ID_PTYS) { |
| 2868 | struct mlx4_ptys_reg *ptys_reg = |
| 2869 | (struct mlx4_ptys_reg *)inbuf->reg_data; |
| 2870 | |
| 2871 | ptys_reg->local_port = |
| 2872 | mlx4_slave_convert_port(dev, slave, |
| 2873 | ptys_reg->local_port); |
| 2874 | } |
| 2875 | |
| 2876 | return mlx4_cmd_box(dev, inbox->dma, outbox->dma, vhcr->in_modifier, |
| 2877 | 0, MLX4_CMD_ACCESS_REG, MLX4_CMD_TIME_CLASS_C, |
| 2878 | MLX4_CMD_NATIVE); |
| 2879 | } |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 2880 | |
| 2881 | static int mlx4_SET_PORT_phv_bit(struct mlx4_dev *dev, u8 port, u8 phv_bit) |
| 2882 | { |
| 2883 | #define SET_PORT_GEN_PHV_VALID 0x10 |
| 2884 | #define SET_PORT_GEN_PHV_EN 0x80 |
| 2885 | |
| 2886 | struct mlx4_cmd_mailbox *mailbox; |
| 2887 | struct mlx4_set_port_general_context *context; |
| 2888 | u32 in_mod; |
| 2889 | int err; |
| 2890 | |
| 2891 | mailbox = mlx4_alloc_cmd_mailbox(dev); |
| 2892 | if (IS_ERR(mailbox)) |
| 2893 | return PTR_ERR(mailbox); |
| 2894 | context = mailbox->buf; |
| 2895 | |
| 2896 | context->v_ignore_fcs |= SET_PORT_GEN_PHV_VALID; |
| 2897 | if (phv_bit) |
| 2898 | context->phv_en |= SET_PORT_GEN_PHV_EN; |
| 2899 | |
| 2900 | in_mod = MLX4_SET_PORT_GENERAL << 8 | port; |
| 2901 | err = mlx4_cmd(dev, mailbox->dma, in_mod, MLX4_SET_PORT_ETH_OPCODE, |
| 2902 | MLX4_CMD_SET_PORT, MLX4_CMD_TIME_CLASS_B, |
| 2903 | MLX4_CMD_NATIVE); |
| 2904 | |
| 2905 | mlx4_free_cmd_mailbox(dev, mailbox); |
| 2906 | return err; |
| 2907 | } |
| 2908 | |
| 2909 | int get_phv_bit(struct mlx4_dev *dev, u8 port, int *phv) |
| 2910 | { |
| 2911 | int err; |
| 2912 | struct mlx4_func_cap func_cap; |
| 2913 | |
| 2914 | memset(&func_cap, 0, sizeof(func_cap)); |
Amir Vadai | 35e455f | 2015-07-28 13:19:19 +0300 | [diff] [blame] | 2915 | err = mlx4_QUERY_FUNC_CAP(dev, port, &func_cap); |
Hadar Hen Zion | 77fc29c | 2015-07-27 14:46:31 +0300 | [diff] [blame] | 2916 | if (!err) |
| 2917 | *phv = func_cap.flags & QUERY_FUNC_CAP_PHV_BIT; |
| 2918 | return err; |
| 2919 | } |
| 2920 | EXPORT_SYMBOL(get_phv_bit); |
| 2921 | |
| 2922 | int set_phv_bit(struct mlx4_dev *dev, u8 port, int new_val) |
| 2923 | { |
| 2924 | int ret; |
| 2925 | |
| 2926 | if (mlx4_is_slave(dev)) |
| 2927 | return -EPERM; |
| 2928 | |
| 2929 | if (dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_PHV_EN && |
| 2930 | !(dev->caps.flags2 & MLX4_DEV_CAP_FLAG2_SKIP_OUTER_VLAN)) { |
| 2931 | ret = mlx4_SET_PORT_phv_bit(dev, port, new_val); |
| 2932 | if (!ret) |
| 2933 | dev->caps.phv_bit[port] = new_val; |
| 2934 | return ret; |
| 2935 | } |
| 2936 | |
| 2937 | return -EOPNOTSUPP; |
| 2938 | } |
| 2939 | EXPORT_SYMBOL(set_phv_bit); |
Jack Morgenstein | 2b3ddf2 | 2015-10-14 17:43:48 +0300 | [diff] [blame] | 2940 | |
| 2941 | void mlx4_replace_zero_macs(struct mlx4_dev *dev) |
| 2942 | { |
| 2943 | int i; |
| 2944 | u8 mac_addr[ETH_ALEN]; |
| 2945 | |
| 2946 | dev->port_random_macs = 0; |
| 2947 | for (i = 1; i <= dev->caps.num_ports; ++i) |
| 2948 | if (!dev->caps.def_mac[i] && |
| 2949 | dev->caps.port_type[i] == MLX4_PORT_TYPE_ETH) { |
| 2950 | eth_random_addr(mac_addr); |
| 2951 | dev->port_random_macs |= 1 << i; |
| 2952 | dev->caps.def_mac[i] = mlx4_mac_to_u64(mac_addr); |
| 2953 | } |
| 2954 | } |
| 2955 | EXPORT_SYMBOL_GPL(mlx4_replace_zero_macs); |