Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1 | /* |
| 2 | * drivers/mtd/nand/fsmc_nand.c |
| 3 | * |
| 4 | * ST Microelectronics |
| 5 | * Flexible Static Memory Controller (FSMC) |
| 6 | * Driver for NAND portions |
| 7 | * |
| 8 | * Copyright © 2010 ST Microelectronics |
| 9 | * Vipin Kumar <vipin.kumar@st.com> |
| 10 | * Ashish Priyadarshi |
| 11 | * |
| 12 | * Based on drivers/mtd/nand/nomadik_nand.c |
| 13 | * |
| 14 | * This file is licensed under the terms of the GNU General Public |
| 15 | * License version 2. This program is licensed "as is" without any |
| 16 | * warranty of any kind, whether express or implied. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/clk.h> |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 20 | #include <linux/completion.h> |
| 21 | #include <linux/dmaengine.h> |
| 22 | #include <linux/dma-direction.h> |
| 23 | #include <linux/dma-mapping.h> |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 24 | #include <linux/err.h> |
| 25 | #include <linux/init.h> |
| 26 | #include <linux/module.h> |
| 27 | #include <linux/resource.h> |
| 28 | #include <linux/sched.h> |
| 29 | #include <linux/types.h> |
| 30 | #include <linux/mtd/mtd.h> |
| 31 | #include <linux/mtd/nand.h> |
| 32 | #include <linux/mtd/nand_ecc.h> |
| 33 | #include <linux/platform_device.h> |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 34 | #include <linux/of.h> |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 35 | #include <linux/mtd/partitions.h> |
| 36 | #include <linux/io.h> |
| 37 | #include <linux/slab.h> |
| 38 | #include <linux/mtd/fsmc.h> |
Linus Walleij | 593cd87 | 2010-11-29 13:52:19 +0100 | [diff] [blame] | 39 | #include <linux/amba/bus.h> |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 40 | #include <mtd/mtd-abi.h> |
| 41 | |
Boris Brezillon | 22b4695 | 2016-02-03 20:01:42 +0100 | [diff] [blame] | 42 | static int fsmc_ecc1_ooblayout_ecc(struct mtd_info *mtd, int section, |
| 43 | struct mtd_oob_region *oobregion) |
| 44 | { |
| 45 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 46 | |
| 47 | if (section >= chip->ecc.steps) |
| 48 | return -ERANGE; |
| 49 | |
| 50 | oobregion->offset = (section * 16) + 2; |
| 51 | oobregion->length = 3; |
| 52 | |
| 53 | return 0; |
| 54 | } |
| 55 | |
| 56 | static int fsmc_ecc1_ooblayout_free(struct mtd_info *mtd, int section, |
| 57 | struct mtd_oob_region *oobregion) |
| 58 | { |
| 59 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 60 | |
| 61 | if (section >= chip->ecc.steps) |
| 62 | return -ERANGE; |
| 63 | |
| 64 | oobregion->offset = (section * 16) + 8; |
| 65 | |
| 66 | if (section < chip->ecc.steps - 1) |
| 67 | oobregion->length = 8; |
| 68 | else |
| 69 | oobregion->length = mtd->oobsize - oobregion->offset; |
| 70 | |
| 71 | return 0; |
| 72 | } |
| 73 | |
| 74 | static const struct mtd_ooblayout_ops fsmc_ecc1_ooblayout_ops = { |
| 75 | .ecc = fsmc_ecc1_ooblayout_ecc, |
| 76 | .free = fsmc_ecc1_ooblayout_free, |
| 77 | }; |
| 78 | |
Boris Brezillon | 04a123a | 2016-02-09 15:01:21 +0100 | [diff] [blame] | 79 | /* |
| 80 | * ECC placement definitions in oobfree type format. |
| 81 | * There are 13 bytes of ecc for every 512 byte block and it has to be read |
| 82 | * consecutively and immediately after the 512 byte data block for hardware to |
| 83 | * generate the error bit offsets in 512 byte data. |
| 84 | */ |
Boris Brezillon | 22b4695 | 2016-02-03 20:01:42 +0100 | [diff] [blame] | 85 | static int fsmc_ecc4_ooblayout_ecc(struct mtd_info *mtd, int section, |
| 86 | struct mtd_oob_region *oobregion) |
| 87 | { |
| 88 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 89 | |
| 90 | if (section >= chip->ecc.steps) |
| 91 | return -ERANGE; |
| 92 | |
| 93 | oobregion->length = chip->ecc.bytes; |
| 94 | |
| 95 | if (!section && mtd->writesize <= 512) |
| 96 | oobregion->offset = 0; |
| 97 | else |
| 98 | oobregion->offset = (section * 16) + 2; |
| 99 | |
| 100 | return 0; |
| 101 | } |
| 102 | |
| 103 | static int fsmc_ecc4_ooblayout_free(struct mtd_info *mtd, int section, |
| 104 | struct mtd_oob_region *oobregion) |
| 105 | { |
| 106 | struct nand_chip *chip = mtd_to_nand(mtd); |
| 107 | |
| 108 | if (section >= chip->ecc.steps) |
| 109 | return -ERANGE; |
| 110 | |
| 111 | oobregion->offset = (section * 16) + 15; |
| 112 | |
| 113 | if (section < chip->ecc.steps - 1) |
| 114 | oobregion->length = 3; |
| 115 | else |
| 116 | oobregion->length = mtd->oobsize - oobregion->offset; |
| 117 | |
| 118 | return 0; |
| 119 | } |
| 120 | |
| 121 | static const struct mtd_ooblayout_ops fsmc_ecc4_ooblayout_ops = { |
| 122 | .ecc = fsmc_ecc4_ooblayout_ecc, |
| 123 | .free = fsmc_ecc4_ooblayout_free, |
| 124 | }; |
| 125 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 126 | /** |
Linus Walleij | 593cd87 | 2010-11-29 13:52:19 +0100 | [diff] [blame] | 127 | * struct fsmc_nand_data - structure for FSMC NAND device state |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 128 | * |
Linus Walleij | 593cd87 | 2010-11-29 13:52:19 +0100 | [diff] [blame] | 129 | * @pid: Part ID on the AMBA PrimeCell format |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 130 | * @mtd: MTD info for a NAND flash. |
| 131 | * @nand: Chip related info for a NAND flash. |
Vipin Kumar | 7147032 | 2012-03-14 11:47:07 +0530 | [diff] [blame] | 132 | * @partitions: Partition info for a NAND Flash. |
| 133 | * @nr_partitions: Total number of partition of a NAND flash. |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 134 | * |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 135 | * @bank: Bank number for probed device. |
| 136 | * @clk: Clock structure for FSMC. |
| 137 | * |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 138 | * @read_dma_chan: DMA channel for read access |
| 139 | * @write_dma_chan: DMA channel for write access to NAND |
| 140 | * @dma_access_complete: Completion structure |
| 141 | * |
| 142 | * @data_pa: NAND Physical port for Data. |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 143 | * @data_va: NAND port for Data. |
| 144 | * @cmd_va: NAND port for Command. |
| 145 | * @addr_va: NAND port for Address. |
| 146 | * @regs_va: FSMC regs base address. |
| 147 | */ |
| 148 | struct fsmc_nand_data { |
Linus Walleij | 593cd87 | 2010-11-29 13:52:19 +0100 | [diff] [blame] | 149 | u32 pid; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 150 | struct nand_chip nand; |
Vipin Kumar | 7147032 | 2012-03-14 11:47:07 +0530 | [diff] [blame] | 151 | struct mtd_partition *partitions; |
| 152 | unsigned int nr_partitions; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 153 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 154 | unsigned int bank; |
Vipin Kumar | 712c4ad | 2012-03-14 11:47:16 +0530 | [diff] [blame] | 155 | struct device *dev; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 156 | enum access_mode mode; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 157 | struct clk *clk; |
| 158 | |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 159 | /* DMA related objects */ |
| 160 | struct dma_chan *read_dma_chan; |
| 161 | struct dma_chan *write_dma_chan; |
| 162 | struct completion dma_access_complete; |
| 163 | |
Vipin Kumar | e2f6bce | 2012-03-14 11:47:14 +0530 | [diff] [blame] | 164 | struct fsmc_nand_timings *dev_timings; |
| 165 | |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 166 | dma_addr_t data_pa; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 167 | void __iomem *data_va; |
| 168 | void __iomem *cmd_va; |
| 169 | void __iomem *addr_va; |
| 170 | void __iomem *regs_va; |
| 171 | |
| 172 | void (*select_chip)(uint32_t bank, uint32_t busw); |
| 173 | }; |
| 174 | |
Boris BREZILLON | 277af42 | 2015-12-10 08:59:46 +0100 | [diff] [blame] | 175 | static inline struct fsmc_nand_data *mtd_to_fsmc(struct mtd_info *mtd) |
| 176 | { |
Boris BREZILLON | bdf3a55 | 2015-12-10 09:00:05 +0100 | [diff] [blame] | 177 | return container_of(mtd_to_nand(mtd), struct fsmc_nand_data, nand); |
Boris BREZILLON | 277af42 | 2015-12-10 08:59:46 +0100 | [diff] [blame] | 178 | } |
| 179 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 180 | /* Assert CS signal based on chipnr */ |
| 181 | static void fsmc_select_chip(struct mtd_info *mtd, int chipnr) |
| 182 | { |
Boris BREZILLON | 4bd4ebc | 2015-12-01 12:03:04 +0100 | [diff] [blame] | 183 | struct nand_chip *chip = mtd_to_nand(mtd); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 184 | struct fsmc_nand_data *host; |
| 185 | |
Boris BREZILLON | 277af42 | 2015-12-10 08:59:46 +0100 | [diff] [blame] | 186 | host = mtd_to_fsmc(mtd); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 187 | |
| 188 | switch (chipnr) { |
| 189 | case -1: |
| 190 | chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE); |
| 191 | break; |
| 192 | case 0: |
| 193 | case 1: |
| 194 | case 2: |
| 195 | case 3: |
| 196 | if (host->select_chip) |
| 197 | host->select_chip(chipnr, |
| 198 | chip->options & NAND_BUSWIDTH_16); |
| 199 | break; |
| 200 | |
| 201 | default: |
Stefan Roese | 6efadcf | 2015-10-02 12:40:21 +0200 | [diff] [blame] | 202 | dev_err(host->dev, "unsupported chip-select %d\n", chipnr); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 203 | } |
| 204 | } |
| 205 | |
| 206 | /* |
| 207 | * fsmc_cmd_ctrl - For facilitaing Hardware access |
| 208 | * This routine allows hardware specific access to control-lines(ALE,CLE) |
| 209 | */ |
| 210 | static void fsmc_cmd_ctrl(struct mtd_info *mtd, int cmd, unsigned int ctrl) |
| 211 | { |
Boris BREZILLON | 4bd4ebc | 2015-12-01 12:03:04 +0100 | [diff] [blame] | 212 | struct nand_chip *this = mtd_to_nand(mtd); |
Boris BREZILLON | 277af42 | 2015-12-10 08:59:46 +0100 | [diff] [blame] | 213 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
Vipin Kumar | 605add7 | 2012-10-09 16:14:43 +0530 | [diff] [blame] | 214 | void __iomem *regs = host->regs_va; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 215 | unsigned int bank = host->bank; |
| 216 | |
| 217 | if (ctrl & NAND_CTRL_CHANGE) { |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 218 | u32 pc; |
| 219 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 220 | if (ctrl & NAND_CLE) { |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 221 | this->IO_ADDR_R = host->cmd_va; |
| 222 | this->IO_ADDR_W = host->cmd_va; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 223 | } else if (ctrl & NAND_ALE) { |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 224 | this->IO_ADDR_R = host->addr_va; |
| 225 | this->IO_ADDR_W = host->addr_va; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 226 | } else { |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 227 | this->IO_ADDR_R = host->data_va; |
| 228 | this->IO_ADDR_W = host->data_va; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 229 | } |
| 230 | |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 231 | pc = readl(FSMC_NAND_REG(regs, bank, PC)); |
| 232 | if (ctrl & NAND_NCE) |
| 233 | pc |= FSMC_ENABLE; |
| 234 | else |
| 235 | pc &= ~FSMC_ENABLE; |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 236 | writel_relaxed(pc, FSMC_NAND_REG(regs, bank, PC)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 237 | } |
| 238 | |
| 239 | mb(); |
| 240 | |
| 241 | if (cmd != NAND_CMD_NONE) |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 242 | writeb_relaxed(cmd, this->IO_ADDR_W); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 243 | } |
| 244 | |
| 245 | /* |
| 246 | * fsmc_nand_setup - FSMC (Flexible Static Memory Controller) init routine |
| 247 | * |
| 248 | * This routine initializes timing parameters related to NAND memory access in |
| 249 | * FSMC registers |
| 250 | */ |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 251 | static void fsmc_nand_setup(void __iomem *regs, uint32_t bank, |
Vipin Kumar | e2f6bce | 2012-03-14 11:47:14 +0530 | [diff] [blame] | 252 | uint32_t busw, struct fsmc_nand_timings *timings) |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 253 | { |
| 254 | uint32_t value = FSMC_DEVTYPE_NAND | FSMC_ENABLE | FSMC_WAITON; |
Vipin Kumar | e2f6bce | 2012-03-14 11:47:14 +0530 | [diff] [blame] | 255 | uint32_t tclr, tar, thiz, thold, twait, tset; |
| 256 | struct fsmc_nand_timings *tims; |
| 257 | struct fsmc_nand_timings default_timings = { |
| 258 | .tclr = FSMC_TCLR_1, |
| 259 | .tar = FSMC_TAR_1, |
| 260 | .thiz = FSMC_THIZ_1, |
| 261 | .thold = FSMC_THOLD_4, |
| 262 | .twait = FSMC_TWAIT_6, |
| 263 | .tset = FSMC_TSET_0, |
| 264 | }; |
| 265 | |
| 266 | if (timings) |
| 267 | tims = timings; |
| 268 | else |
| 269 | tims = &default_timings; |
| 270 | |
| 271 | tclr = (tims->tclr & FSMC_TCLR_MASK) << FSMC_TCLR_SHIFT; |
| 272 | tar = (tims->tar & FSMC_TAR_MASK) << FSMC_TAR_SHIFT; |
| 273 | thiz = (tims->thiz & FSMC_THIZ_MASK) << FSMC_THIZ_SHIFT; |
| 274 | thold = (tims->thold & FSMC_THOLD_MASK) << FSMC_THOLD_SHIFT; |
| 275 | twait = (tims->twait & FSMC_TWAIT_MASK) << FSMC_TWAIT_SHIFT; |
| 276 | tset = (tims->tset & FSMC_TSET_MASK) << FSMC_TSET_SHIFT; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 277 | |
| 278 | if (busw) |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 279 | writel_relaxed(value | FSMC_DEVWID_16, |
| 280 | FSMC_NAND_REG(regs, bank, PC)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 281 | else |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 282 | writel_relaxed(value | FSMC_DEVWID_8, |
| 283 | FSMC_NAND_REG(regs, bank, PC)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 284 | |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 285 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | tclr | tar, |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 286 | FSMC_NAND_REG(regs, bank, PC)); |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 287 | writel_relaxed(thiz | thold | twait | tset, |
| 288 | FSMC_NAND_REG(regs, bank, COMM)); |
| 289 | writel_relaxed(thiz | thold | twait | tset, |
| 290 | FSMC_NAND_REG(regs, bank, ATTRIB)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 291 | } |
| 292 | |
| 293 | /* |
| 294 | * fsmc_enable_hwecc - Enables Hardware ECC through FSMC registers |
| 295 | */ |
| 296 | static void fsmc_enable_hwecc(struct mtd_info *mtd, int mode) |
| 297 | { |
Boris BREZILLON | 277af42 | 2015-12-10 08:59:46 +0100 | [diff] [blame] | 298 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 299 | void __iomem *regs = host->regs_va; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 300 | uint32_t bank = host->bank; |
| 301 | |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 302 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCPLEN_256, |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 303 | FSMC_NAND_REG(regs, bank, PC)); |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 304 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) & ~FSMC_ECCEN, |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 305 | FSMC_NAND_REG(regs, bank, PC)); |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 306 | writel_relaxed(readl(FSMC_NAND_REG(regs, bank, PC)) | FSMC_ECCEN, |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 307 | FSMC_NAND_REG(regs, bank, PC)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 308 | } |
| 309 | |
| 310 | /* |
| 311 | * fsmc_read_hwecc_ecc4 - Hardware ECC calculator for ecc4 option supported by |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 312 | * FSMC. ECC is 13 bytes for 512 bytes of data (supports error correction up to |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 313 | * max of 8-bits) |
| 314 | */ |
| 315 | static int fsmc_read_hwecc_ecc4(struct mtd_info *mtd, const uint8_t *data, |
| 316 | uint8_t *ecc) |
| 317 | { |
Boris BREZILLON | 277af42 | 2015-12-10 08:59:46 +0100 | [diff] [blame] | 318 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 319 | void __iomem *regs = host->regs_va; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 320 | uint32_t bank = host->bank; |
| 321 | uint32_t ecc_tmp; |
| 322 | unsigned long deadline = jiffies + FSMC_BUSY_WAIT_TIMEOUT; |
| 323 | |
| 324 | do { |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 325 | if (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) & FSMC_CODE_RDY) |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 326 | break; |
| 327 | else |
| 328 | cond_resched(); |
| 329 | } while (!time_after_eq(jiffies, deadline)); |
| 330 | |
Vipin Kumar | 712c4ad | 2012-03-14 11:47:16 +0530 | [diff] [blame] | 331 | if (time_after_eq(jiffies, deadline)) { |
| 332 | dev_err(host->dev, "calculate ecc timed out\n"); |
| 333 | return -ETIMEDOUT; |
| 334 | } |
| 335 | |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 336 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 337 | ecc[0] = (uint8_t) (ecc_tmp >> 0); |
| 338 | ecc[1] = (uint8_t) (ecc_tmp >> 8); |
| 339 | ecc[2] = (uint8_t) (ecc_tmp >> 16); |
| 340 | ecc[3] = (uint8_t) (ecc_tmp >> 24); |
| 341 | |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 342 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 343 | ecc[4] = (uint8_t) (ecc_tmp >> 0); |
| 344 | ecc[5] = (uint8_t) (ecc_tmp >> 8); |
| 345 | ecc[6] = (uint8_t) (ecc_tmp >> 16); |
| 346 | ecc[7] = (uint8_t) (ecc_tmp >> 24); |
| 347 | |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 348 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 349 | ecc[8] = (uint8_t) (ecc_tmp >> 0); |
| 350 | ecc[9] = (uint8_t) (ecc_tmp >> 8); |
| 351 | ecc[10] = (uint8_t) (ecc_tmp >> 16); |
| 352 | ecc[11] = (uint8_t) (ecc_tmp >> 24); |
| 353 | |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 354 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, STS)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 355 | ecc[12] = (uint8_t) (ecc_tmp >> 16); |
| 356 | |
| 357 | return 0; |
| 358 | } |
| 359 | |
| 360 | /* |
| 361 | * fsmc_read_hwecc_ecc1 - Hardware ECC calculator for ecc1 option supported by |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 362 | * FSMC. ECC is 3 bytes for 512 bytes of data (supports error correction up to |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 363 | * max of 1-bit) |
| 364 | */ |
| 365 | static int fsmc_read_hwecc_ecc1(struct mtd_info *mtd, const uint8_t *data, |
| 366 | uint8_t *ecc) |
| 367 | { |
Boris BREZILLON | 277af42 | 2015-12-10 08:59:46 +0100 | [diff] [blame] | 368 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 369 | void __iomem *regs = host->regs_va; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 370 | uint32_t bank = host->bank; |
| 371 | uint32_t ecc_tmp; |
| 372 | |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 373 | ecc_tmp = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 374 | ecc[0] = (uint8_t) (ecc_tmp >> 0); |
| 375 | ecc[1] = (uint8_t) (ecc_tmp >> 8); |
| 376 | ecc[2] = (uint8_t) (ecc_tmp >> 16); |
| 377 | |
| 378 | return 0; |
| 379 | } |
| 380 | |
Vipin Kumar | 519300c | 2012-03-07 17:00:49 +0530 | [diff] [blame] | 381 | /* Count the number of 0's in buff upto a max of max_bits */ |
| 382 | static int count_written_bits(uint8_t *buff, int size, int max_bits) |
| 383 | { |
| 384 | int k, written_bits = 0; |
| 385 | |
| 386 | for (k = 0; k < size; k++) { |
| 387 | written_bits += hweight8(~buff[k]); |
| 388 | if (written_bits > max_bits) |
| 389 | break; |
| 390 | } |
| 391 | |
| 392 | return written_bits; |
| 393 | } |
| 394 | |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 395 | static void dma_complete(void *param) |
| 396 | { |
| 397 | struct fsmc_nand_data *host = param; |
| 398 | |
| 399 | complete(&host->dma_access_complete); |
| 400 | } |
| 401 | |
| 402 | static int dma_xfer(struct fsmc_nand_data *host, void *buffer, int len, |
| 403 | enum dma_data_direction direction) |
| 404 | { |
| 405 | struct dma_chan *chan; |
| 406 | struct dma_device *dma_dev; |
| 407 | struct dma_async_tx_descriptor *tx; |
| 408 | dma_addr_t dma_dst, dma_src, dma_addr; |
| 409 | dma_cookie_t cookie; |
| 410 | unsigned long flags = DMA_CTRL_ACK | DMA_PREP_INTERRUPT; |
| 411 | int ret; |
Nicholas Mc Guire | 818a45b | 2015-03-13 07:54:46 -0400 | [diff] [blame] | 412 | unsigned long time_left; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 413 | |
| 414 | if (direction == DMA_TO_DEVICE) |
| 415 | chan = host->write_dma_chan; |
| 416 | else if (direction == DMA_FROM_DEVICE) |
| 417 | chan = host->read_dma_chan; |
| 418 | else |
| 419 | return -EINVAL; |
| 420 | |
| 421 | dma_dev = chan->device; |
| 422 | dma_addr = dma_map_single(dma_dev->dev, buffer, len, direction); |
| 423 | |
| 424 | if (direction == DMA_TO_DEVICE) { |
| 425 | dma_src = dma_addr; |
| 426 | dma_dst = host->data_pa; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 427 | } else { |
| 428 | dma_src = host->data_pa; |
| 429 | dma_dst = dma_addr; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 430 | } |
| 431 | |
| 432 | tx = dma_dev->device_prep_dma_memcpy(chan, dma_dst, dma_src, |
| 433 | len, flags); |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 434 | if (!tx) { |
| 435 | dev_err(host->dev, "device_prep_dma_memcpy error\n"); |
Bartlomiej Zolnierkiewicz | d1806a5 | 2012-11-05 10:00:14 +0000 | [diff] [blame] | 436 | ret = -EIO; |
| 437 | goto unmap_dma; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 438 | } |
| 439 | |
| 440 | tx->callback = dma_complete; |
| 441 | tx->callback_param = host; |
| 442 | cookie = tx->tx_submit(tx); |
| 443 | |
| 444 | ret = dma_submit_error(cookie); |
| 445 | if (ret) { |
| 446 | dev_err(host->dev, "dma_submit_error %d\n", cookie); |
Bartlomiej Zolnierkiewicz | d1806a5 | 2012-11-05 10:00:14 +0000 | [diff] [blame] | 447 | goto unmap_dma; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 448 | } |
| 449 | |
| 450 | dma_async_issue_pending(chan); |
| 451 | |
Nicholas Mc Guire | 818a45b | 2015-03-13 07:54:46 -0400 | [diff] [blame] | 452 | time_left = |
Vipin Kumar | 928aa2a | 2012-10-09 16:14:48 +0530 | [diff] [blame] | 453 | wait_for_completion_timeout(&host->dma_access_complete, |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 454 | msecs_to_jiffies(3000)); |
Nicholas Mc Guire | 818a45b | 2015-03-13 07:54:46 -0400 | [diff] [blame] | 455 | if (time_left == 0) { |
Vinod Koul | b177ea3 | 2014-10-11 21:10:32 +0530 | [diff] [blame] | 456 | dmaengine_terminate_all(chan); |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 457 | dev_err(host->dev, "wait_for_completion_timeout\n"); |
Nicholas Mc Guire | 0bda3e1 | 2015-03-13 07:54:45 -0400 | [diff] [blame] | 458 | ret = -ETIMEDOUT; |
Bartlomiej Zolnierkiewicz | d1806a5 | 2012-11-05 10:00:14 +0000 | [diff] [blame] | 459 | goto unmap_dma; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 460 | } |
| 461 | |
Bartlomiej Zolnierkiewicz | d1806a5 | 2012-11-05 10:00:14 +0000 | [diff] [blame] | 462 | ret = 0; |
| 463 | |
| 464 | unmap_dma: |
| 465 | dma_unmap_single(dma_dev->dev, dma_addr, len, direction); |
| 466 | |
| 467 | return ret; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 468 | } |
| 469 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 470 | /* |
Vipin Kumar | 604e754 | 2012-03-14 11:47:17 +0530 | [diff] [blame] | 471 | * fsmc_write_buf - write buffer to chip |
| 472 | * @mtd: MTD device structure |
| 473 | * @buf: data buffer |
| 474 | * @len: number of bytes to write |
| 475 | */ |
| 476 | static void fsmc_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len) |
| 477 | { |
| 478 | int i; |
Boris BREZILLON | 4bd4ebc | 2015-12-01 12:03:04 +0100 | [diff] [blame] | 479 | struct nand_chip *chip = mtd_to_nand(mtd); |
Vipin Kumar | 604e754 | 2012-03-14 11:47:17 +0530 | [diff] [blame] | 480 | |
| 481 | if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) && |
| 482 | IS_ALIGNED(len, sizeof(uint32_t))) { |
| 483 | uint32_t *p = (uint32_t *)buf; |
| 484 | len = len >> 2; |
| 485 | for (i = 0; i < len; i++) |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 486 | writel_relaxed(p[i], chip->IO_ADDR_W); |
Vipin Kumar | 604e754 | 2012-03-14 11:47:17 +0530 | [diff] [blame] | 487 | } else { |
| 488 | for (i = 0; i < len; i++) |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 489 | writeb_relaxed(buf[i], chip->IO_ADDR_W); |
Vipin Kumar | 604e754 | 2012-03-14 11:47:17 +0530 | [diff] [blame] | 490 | } |
| 491 | } |
| 492 | |
| 493 | /* |
| 494 | * fsmc_read_buf - read chip data into buffer |
| 495 | * @mtd: MTD device structure |
| 496 | * @buf: buffer to store date |
| 497 | * @len: number of bytes to read |
| 498 | */ |
| 499 | static void fsmc_read_buf(struct mtd_info *mtd, uint8_t *buf, int len) |
| 500 | { |
| 501 | int i; |
Boris BREZILLON | 4bd4ebc | 2015-12-01 12:03:04 +0100 | [diff] [blame] | 502 | struct nand_chip *chip = mtd_to_nand(mtd); |
Vipin Kumar | 604e754 | 2012-03-14 11:47:17 +0530 | [diff] [blame] | 503 | |
| 504 | if (IS_ALIGNED((uint32_t)buf, sizeof(uint32_t)) && |
| 505 | IS_ALIGNED(len, sizeof(uint32_t))) { |
| 506 | uint32_t *p = (uint32_t *)buf; |
| 507 | len = len >> 2; |
| 508 | for (i = 0; i < len; i++) |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 509 | p[i] = readl_relaxed(chip->IO_ADDR_R); |
Vipin Kumar | 604e754 | 2012-03-14 11:47:17 +0530 | [diff] [blame] | 510 | } else { |
| 511 | for (i = 0; i < len; i++) |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 512 | buf[i] = readb_relaxed(chip->IO_ADDR_R); |
Vipin Kumar | 604e754 | 2012-03-14 11:47:17 +0530 | [diff] [blame] | 513 | } |
| 514 | } |
| 515 | |
| 516 | /* |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 517 | * fsmc_read_buf_dma - read chip data into buffer |
| 518 | * @mtd: MTD device structure |
| 519 | * @buf: buffer to store date |
| 520 | * @len: number of bytes to read |
| 521 | */ |
| 522 | static void fsmc_read_buf_dma(struct mtd_info *mtd, uint8_t *buf, int len) |
| 523 | { |
Boris BREZILLON | 277af42 | 2015-12-10 08:59:46 +0100 | [diff] [blame] | 524 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 525 | |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 526 | dma_xfer(host, buf, len, DMA_FROM_DEVICE); |
| 527 | } |
| 528 | |
| 529 | /* |
| 530 | * fsmc_write_buf_dma - write buffer to chip |
| 531 | * @mtd: MTD device structure |
| 532 | * @buf: data buffer |
| 533 | * @len: number of bytes to write |
| 534 | */ |
| 535 | static void fsmc_write_buf_dma(struct mtd_info *mtd, const uint8_t *buf, |
| 536 | int len) |
| 537 | { |
Boris BREZILLON | 277af42 | 2015-12-10 08:59:46 +0100 | [diff] [blame] | 538 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 539 | |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 540 | dma_xfer(host, (void *)buf, len, DMA_TO_DEVICE); |
| 541 | } |
| 542 | |
| 543 | /* |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 544 | * fsmc_read_page_hwecc |
| 545 | * @mtd: mtd info structure |
| 546 | * @chip: nand chip info structure |
| 547 | * @buf: buffer to store read data |
Brian Norris | 1fbb938 | 2012-05-02 10:14:55 -0700 | [diff] [blame] | 548 | * @oob_required: caller expects OOB data read to chip->oob_poi |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 549 | * @page: page number to read |
| 550 | * |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 551 | * This routine is needed for fsmc version 8 as reading from NAND chip has to be |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 552 | * performed in a strict sequence as follows: |
| 553 | * data(512 byte) -> ecc(13 byte) |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 554 | * After this read, fsmc hardware generates and reports error data bits(up to a |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 555 | * max of 8 bits) |
| 556 | */ |
| 557 | static int fsmc_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip, |
Brian Norris | 1fbb938 | 2012-05-02 10:14:55 -0700 | [diff] [blame] | 558 | uint8_t *buf, int oob_required, int page) |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 559 | { |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 560 | int i, j, s, stat, eccsize = chip->ecc.size; |
| 561 | int eccbytes = chip->ecc.bytes; |
| 562 | int eccsteps = chip->ecc.steps; |
| 563 | uint8_t *p = buf; |
| 564 | uint8_t *ecc_calc = chip->buffers->ecccalc; |
| 565 | uint8_t *ecc_code = chip->buffers->ecccode; |
| 566 | int off, len, group = 0; |
| 567 | /* |
| 568 | * ecc_oob is intentionally taken as uint16_t. In 16bit devices, we |
| 569 | * end up reading 14 bytes (7 words) from oob. The local array is |
| 570 | * to maintain word alignment |
| 571 | */ |
| 572 | uint16_t ecc_oob[7]; |
| 573 | uint8_t *oob = (uint8_t *)&ecc_oob[0]; |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 574 | unsigned int max_bitflips = 0; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 575 | |
| 576 | for (i = 0, s = 0; s < eccsteps; s++, i += eccbytes, p += eccsize) { |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 577 | chip->cmdfunc(mtd, NAND_CMD_READ0, s * eccsize, page); |
| 578 | chip->ecc.hwctl(mtd, NAND_ECC_READ); |
| 579 | chip->read_buf(mtd, p, eccsize); |
| 580 | |
| 581 | for (j = 0; j < eccbytes;) { |
Boris Brezillon | 04a123a | 2016-02-09 15:01:21 +0100 | [diff] [blame] | 582 | struct mtd_oob_region oobregion; |
| 583 | int ret; |
| 584 | |
| 585 | ret = mtd_ooblayout_ecc(mtd, group++, &oobregion); |
| 586 | if (ret) |
| 587 | return ret; |
| 588 | |
| 589 | off = oobregion.offset; |
| 590 | len = oobregion.length; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 591 | |
| 592 | /* |
Vipin Kumar | 4cbe1bf0 | 2012-03-14 11:47:09 +0530 | [diff] [blame] | 593 | * length is intentionally kept a higher multiple of 2 |
| 594 | * to read at least 13 bytes even in case of 16 bit NAND |
| 595 | * devices |
| 596 | */ |
Vipin Kumar | aea686b | 2012-03-14 11:47:10 +0530 | [diff] [blame] | 597 | if (chip->options & NAND_BUSWIDTH_16) |
| 598 | len = roundup(len, 2); |
| 599 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 600 | chip->cmdfunc(mtd, NAND_CMD_READOOB, off, page); |
| 601 | chip->read_buf(mtd, oob + j, len); |
| 602 | j += len; |
| 603 | } |
| 604 | |
Vipin Kumar | 519300c | 2012-03-07 17:00:49 +0530 | [diff] [blame] | 605 | memcpy(&ecc_code[i], oob, chip->ecc.bytes); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 606 | chip->ecc.calculate(mtd, p, &ecc_calc[i]); |
| 607 | |
| 608 | stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]); |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 609 | if (stat < 0) { |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 610 | mtd->ecc_stats.failed++; |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 611 | } else { |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 612 | mtd->ecc_stats.corrected += stat; |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 613 | max_bitflips = max_t(unsigned int, max_bitflips, stat); |
| 614 | } |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 615 | } |
| 616 | |
Mike Dunn | 3f91e94 | 2012-04-25 12:06:09 -0700 | [diff] [blame] | 617 | return max_bitflips; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 618 | } |
| 619 | |
| 620 | /* |
Armando Visconti | 753e013 | 2012-03-07 17:00:54 +0530 | [diff] [blame] | 621 | * fsmc_bch8_correct_data |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 622 | * @mtd: mtd info structure |
| 623 | * @dat: buffer of read data |
| 624 | * @read_ecc: ecc read from device spare area |
| 625 | * @calc_ecc: ecc calculated from read data |
| 626 | * |
| 627 | * calc_ecc is a 104 bit information containing maximum of 8 error |
| 628 | * offset informations of 13 bits each in 512 bytes of read data. |
| 629 | */ |
Armando Visconti | 753e013 | 2012-03-07 17:00:54 +0530 | [diff] [blame] | 630 | static int fsmc_bch8_correct_data(struct mtd_info *mtd, uint8_t *dat, |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 631 | uint8_t *read_ecc, uint8_t *calc_ecc) |
| 632 | { |
Boris BREZILLON | 4bd4ebc | 2015-12-01 12:03:04 +0100 | [diff] [blame] | 633 | struct nand_chip *chip = mtd_to_nand(mtd); |
Boris BREZILLON | 277af42 | 2015-12-10 08:59:46 +0100 | [diff] [blame] | 634 | struct fsmc_nand_data *host = mtd_to_fsmc(mtd); |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 635 | void __iomem *regs = host->regs_va; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 636 | unsigned int bank = host->bank; |
Armando Visconti | a612c2a | 2012-03-07 17:00:53 +0530 | [diff] [blame] | 637 | uint32_t err_idx[8]; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 638 | uint32_t num_err, i; |
Armando Visconti | 753e013 | 2012-03-07 17:00:54 +0530 | [diff] [blame] | 639 | uint32_t ecc1, ecc2, ecc3, ecc4; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 640 | |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 641 | num_err = (readl_relaxed(FSMC_NAND_REG(regs, bank, STS)) >> 10) & 0xF; |
Vipin Kumar | 519300c | 2012-03-07 17:00:49 +0530 | [diff] [blame] | 642 | |
| 643 | /* no bit flipping */ |
| 644 | if (likely(num_err == 0)) |
| 645 | return 0; |
| 646 | |
| 647 | /* too many errors */ |
| 648 | if (unlikely(num_err > 8)) { |
| 649 | /* |
| 650 | * This is a temporary erase check. A newly erased page read |
| 651 | * would result in an ecc error because the oob data is also |
| 652 | * erased to FF and the calculated ecc for an FF data is not |
| 653 | * FF..FF. |
| 654 | * This is a workaround to skip performing correction in case |
| 655 | * data is FF..FF |
| 656 | * |
| 657 | * Logic: |
| 658 | * For every page, each bit written as 0 is counted until these |
| 659 | * number of bits are greater than 8 (the maximum correction |
| 660 | * capability of FSMC for each 512 + 13 bytes) |
| 661 | */ |
| 662 | |
| 663 | int bits_ecc = count_written_bits(read_ecc, chip->ecc.bytes, 8); |
| 664 | int bits_data = count_written_bits(dat, chip->ecc.size, 8); |
| 665 | |
| 666 | if ((bits_ecc + bits_data) <= 8) { |
| 667 | if (bits_data) |
| 668 | memset(dat, 0xff, chip->ecc.size); |
| 669 | return bits_data; |
| 670 | } |
| 671 | |
| 672 | return -EBADMSG; |
| 673 | } |
| 674 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 675 | /* |
| 676 | * ------------------- calc_ecc[] bit wise -----------|--13 bits--| |
| 677 | * |---idx[7]--|--.....-----|---idx[2]--||---idx[1]--||---idx[0]--| |
| 678 | * |
| 679 | * calc_ecc is a 104 bit information containing maximum of 8 error |
| 680 | * offset informations of 13 bits each. calc_ecc is copied into a |
| 681 | * uint64_t array and error offset indexes are populated in err_idx |
| 682 | * array |
| 683 | */ |
Vipin Kumar | a4742d5 | 2012-10-09 16:14:50 +0530 | [diff] [blame] | 684 | ecc1 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC1)); |
| 685 | ecc2 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC2)); |
| 686 | ecc3 = readl_relaxed(FSMC_NAND_REG(regs, bank, ECC3)); |
| 687 | ecc4 = readl_relaxed(FSMC_NAND_REG(regs, bank, STS)); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 688 | |
Armando Visconti | 753e013 | 2012-03-07 17:00:54 +0530 | [diff] [blame] | 689 | err_idx[0] = (ecc1 >> 0) & 0x1FFF; |
| 690 | err_idx[1] = (ecc1 >> 13) & 0x1FFF; |
| 691 | err_idx[2] = (((ecc2 >> 0) & 0x7F) << 6) | ((ecc1 >> 26) & 0x3F); |
| 692 | err_idx[3] = (ecc2 >> 7) & 0x1FFF; |
| 693 | err_idx[4] = (((ecc3 >> 0) & 0x1) << 12) | ((ecc2 >> 20) & 0xFFF); |
| 694 | err_idx[5] = (ecc3 >> 1) & 0x1FFF; |
| 695 | err_idx[6] = (ecc3 >> 14) & 0x1FFF; |
| 696 | err_idx[7] = (((ecc4 >> 16) & 0xFF) << 5) | ((ecc3 >> 27) & 0x1F); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 697 | |
| 698 | i = 0; |
| 699 | while (num_err--) { |
| 700 | change_bit(0, (unsigned long *)&err_idx[i]); |
| 701 | change_bit(1, (unsigned long *)&err_idx[i]); |
| 702 | |
Vipin Kumar | b533f8d | 2012-03-14 11:47:11 +0530 | [diff] [blame] | 703 | if (err_idx[i] < chip->ecc.size * 8) { |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 704 | change_bit(err_idx[i], (unsigned long *)dat); |
| 705 | i++; |
| 706 | } |
| 707 | } |
| 708 | return i; |
| 709 | } |
| 710 | |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 711 | static bool filter(struct dma_chan *chan, void *slave) |
| 712 | { |
| 713 | chan->private = slave; |
| 714 | return true; |
| 715 | } |
| 716 | |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 717 | #ifdef CONFIG_OF |
Bill Pemberton | 06f2551 | 2012-11-19 13:23:07 -0500 | [diff] [blame] | 718 | static int fsmc_nand_probe_config_dt(struct platform_device *pdev, |
Greg Kroah-Hartman | d892994 | 2012-12-21 13:19:05 -0800 | [diff] [blame] | 719 | struct device_node *np) |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 720 | { |
| 721 | struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); |
| 722 | u32 val; |
Stefan Roese | 62b57f4 | 2015-03-19 14:34:29 +0100 | [diff] [blame] | 723 | int ret; |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 724 | |
| 725 | /* Set default NAND width to 8 bits */ |
| 726 | pdata->width = 8; |
| 727 | if (!of_property_read_u32(np, "bank-width", &val)) { |
| 728 | if (val == 2) { |
| 729 | pdata->width = 16; |
| 730 | } else if (val != 1) { |
| 731 | dev_err(&pdev->dev, "invalid bank-width %u\n", val); |
| 732 | return -EINVAL; |
| 733 | } |
| 734 | } |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 735 | if (of_get_property(np, "nand-skip-bbtscan", NULL)) |
| 736 | pdata->options = NAND_SKIP_BBTSCAN; |
| 737 | |
Mian Yousaf Kaukab | 64ddba4 | 2013-04-29 14:07:48 +0200 | [diff] [blame] | 738 | pdata->nand_timings = devm_kzalloc(&pdev->dev, |
| 739 | sizeof(*pdata->nand_timings), GFP_KERNEL); |
Jingoo Han | d9a21ae | 2013-12-26 12:16:38 +0900 | [diff] [blame] | 740 | if (!pdata->nand_timings) |
Mian Yousaf Kaukab | 64ddba4 | 2013-04-29 14:07:48 +0200 | [diff] [blame] | 741 | return -ENOMEM; |
Stefan Roese | 62b57f4 | 2015-03-19 14:34:29 +0100 | [diff] [blame] | 742 | ret = of_property_read_u8_array(np, "timings", (u8 *)pdata->nand_timings, |
Mian Yousaf Kaukab | 64ddba4 | 2013-04-29 14:07:48 +0200 | [diff] [blame] | 743 | sizeof(*pdata->nand_timings)); |
Stefan Roese | 62b57f4 | 2015-03-19 14:34:29 +0100 | [diff] [blame] | 744 | if (ret) { |
| 745 | dev_info(&pdev->dev, "No timings in dts specified, using default timings!\n"); |
| 746 | pdata->nand_timings = NULL; |
| 747 | } |
Mian Yousaf Kaukab | 64ddba4 | 2013-04-29 14:07:48 +0200 | [diff] [blame] | 748 | |
| 749 | /* Set default NAND bank to 0 */ |
| 750 | pdata->bank = 0; |
| 751 | if (!of_property_read_u32(np, "bank", &val)) { |
| 752 | if (val > 3) { |
| 753 | dev_err(&pdev->dev, "invalid bank %u\n", val); |
| 754 | return -EINVAL; |
| 755 | } |
| 756 | pdata->bank = val; |
| 757 | } |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 758 | return 0; |
| 759 | } |
| 760 | #else |
Bill Pemberton | 06f2551 | 2012-11-19 13:23:07 -0500 | [diff] [blame] | 761 | static int fsmc_nand_probe_config_dt(struct platform_device *pdev, |
Greg Kroah-Hartman | d892994 | 2012-12-21 13:19:05 -0800 | [diff] [blame] | 762 | struct device_node *np) |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 763 | { |
| 764 | return -ENOSYS; |
| 765 | } |
| 766 | #endif |
| 767 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 768 | /* |
| 769 | * fsmc_nand_probe - Probe function |
| 770 | * @pdev: platform device structure |
| 771 | */ |
| 772 | static int __init fsmc_nand_probe(struct platform_device *pdev) |
| 773 | { |
| 774 | struct fsmc_nand_platform_data *pdata = dev_get_platdata(&pdev->dev); |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 775 | struct device_node __maybe_unused *np = pdev->dev.of_node; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 776 | struct fsmc_nand_data *host; |
| 777 | struct mtd_info *mtd; |
| 778 | struct nand_chip *nand; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 779 | struct resource *res; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 780 | dma_cap_mask_t mask; |
Linus Walleij | 4ad916b | 2010-11-29 13:52:06 +0100 | [diff] [blame] | 781 | int ret = 0; |
Linus Walleij | 593cd87 | 2010-11-29 13:52:19 +0100 | [diff] [blame] | 782 | u32 pid; |
| 783 | int i; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 784 | |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 785 | if (np) { |
| 786 | pdata = devm_kzalloc(&pdev->dev, sizeof(*pdata), GFP_KERNEL); |
| 787 | pdev->dev.platform_data = pdata; |
| 788 | ret = fsmc_nand_probe_config_dt(pdev, np); |
| 789 | if (ret) { |
| 790 | dev_err(&pdev->dev, "no platform data\n"); |
| 791 | return -ENODEV; |
| 792 | } |
| 793 | } |
| 794 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 795 | if (!pdata) { |
| 796 | dev_err(&pdev->dev, "platform data is NULL\n"); |
| 797 | return -EINVAL; |
| 798 | } |
| 799 | |
| 800 | /* Allocate memory for the device structure (and zero it) */ |
Vipin Kumar | 82b9dbe | 2012-03-14 11:47:15 +0530 | [diff] [blame] | 801 | host = devm_kzalloc(&pdev->dev, sizeof(*host), GFP_KERNEL); |
Jingoo Han | d9a21ae | 2013-12-26 12:16:38 +0900 | [diff] [blame] | 802 | if (!host) |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 803 | return -ENOMEM; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 804 | |
| 805 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_data"); |
Thierry Reding | b0de774 | 2013-01-21 11:09:12 +0100 | [diff] [blame] | 806 | host->data_va = devm_ioremap_resource(&pdev->dev, res); |
| 807 | if (IS_ERR(host->data_va)) |
| 808 | return PTR_ERR(host->data_va); |
Stefan Roese | cbf29b8 | 2015-10-02 12:40:20 +0200 | [diff] [blame] | 809 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d7b42a | 2012-10-04 15:14:16 +0200 | [diff] [blame] | 810 | host->data_pa = (dma_addr_t)res->start; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 811 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d7b42a | 2012-10-04 15:14:16 +0200 | [diff] [blame] | 812 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_addr"); |
Thierry Reding | b0de774 | 2013-01-21 11:09:12 +0100 | [diff] [blame] | 813 | host->addr_va = devm_ioremap_resource(&pdev->dev, res); |
| 814 | if (IS_ERR(host->addr_va)) |
| 815 | return PTR_ERR(host->addr_va); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 816 | |
Jean-Christophe PLAGNIOL-VILLARD | 6d7b42a | 2012-10-04 15:14:16 +0200 | [diff] [blame] | 817 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "nand_cmd"); |
Thierry Reding | b0de774 | 2013-01-21 11:09:12 +0100 | [diff] [blame] | 818 | host->cmd_va = devm_ioremap_resource(&pdev->dev, res); |
| 819 | if (IS_ERR(host->cmd_va)) |
| 820 | return PTR_ERR(host->cmd_va); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 821 | |
| 822 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "fsmc_regs"); |
Thierry Reding | b0de774 | 2013-01-21 11:09:12 +0100 | [diff] [blame] | 823 | host->regs_va = devm_ioremap_resource(&pdev->dev, res); |
| 824 | if (IS_ERR(host->regs_va)) |
| 825 | return PTR_ERR(host->regs_va); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 826 | |
| 827 | host->clk = clk_get(&pdev->dev, NULL); |
| 828 | if (IS_ERR(host->clk)) { |
| 829 | dev_err(&pdev->dev, "failed to fetch block clock\n"); |
Vipin Kumar | 82b9dbe | 2012-03-14 11:47:15 +0530 | [diff] [blame] | 830 | return PTR_ERR(host->clk); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 831 | } |
| 832 | |
Viresh Kumar | e25da1c | 2012-04-17 17:07:57 +0530 | [diff] [blame] | 833 | ret = clk_prepare_enable(host->clk); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 834 | if (ret) |
Viresh Kumar | e25da1c | 2012-04-17 17:07:57 +0530 | [diff] [blame] | 835 | goto err_clk_prepare_enable; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 836 | |
Linus Walleij | 593cd87 | 2010-11-29 13:52:19 +0100 | [diff] [blame] | 837 | /* |
| 838 | * This device ID is actually a common AMBA ID as used on the |
| 839 | * AMBA PrimeCell bus. However it is not a PrimeCell. |
| 840 | */ |
| 841 | for (pid = 0, i = 0; i < 4; i++) |
| 842 | pid |= (readl(host->regs_va + resource_size(res) - 0x20 + 4 * i) & 255) << (i * 8); |
| 843 | host->pid = pid; |
| 844 | dev_info(&pdev->dev, "FSMC device partno %03x, manufacturer %02x, " |
| 845 | "revision %02x, config %02x\n", |
| 846 | AMBA_PART_BITS(pid), AMBA_MANF_BITS(pid), |
| 847 | AMBA_REV_BITS(pid), AMBA_CONFIG_BITS(pid)); |
| 848 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 849 | host->bank = pdata->bank; |
| 850 | host->select_chip = pdata->select_bank; |
Vipin Kumar | 7147032 | 2012-03-14 11:47:07 +0530 | [diff] [blame] | 851 | host->partitions = pdata->partitions; |
| 852 | host->nr_partitions = pdata->nr_partitions; |
Vipin Kumar | 712c4ad | 2012-03-14 11:47:16 +0530 | [diff] [blame] | 853 | host->dev = &pdev->dev; |
Vipin Kumar | e2f6bce | 2012-03-14 11:47:14 +0530 | [diff] [blame] | 854 | host->dev_timings = pdata->nand_timings; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 855 | host->mode = pdata->mode; |
| 856 | |
| 857 | if (host->mode == USE_DMA_ACCESS) |
| 858 | init_completion(&host->dma_access_complete); |
| 859 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 860 | /* Link all private pointers */ |
Boris BREZILLON | bdf3a55 | 2015-12-10 09:00:05 +0100 | [diff] [blame] | 861 | mtd = nand_to_mtd(&host->nand); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 862 | nand = &host->nand; |
Boris BREZILLON | d699ed2 | 2015-12-10 09:00:41 +0100 | [diff] [blame] | 863 | nand_set_controller_data(nand, host); |
Brian Norris | a61ae81 | 2015-10-30 20:33:25 -0700 | [diff] [blame] | 864 | nand_set_flash_node(nand, np); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 865 | |
Boris BREZILLON | bdf3a55 | 2015-12-10 09:00:05 +0100 | [diff] [blame] | 866 | mtd->dev.parent = &pdev->dev; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 867 | nand->IO_ADDR_R = host->data_va; |
| 868 | nand->IO_ADDR_W = host->data_va; |
| 869 | nand->cmd_ctrl = fsmc_cmd_ctrl; |
| 870 | nand->chip_delay = 30; |
| 871 | |
Stefan Roese | e278fc7 | 2015-10-19 08:40:13 +0200 | [diff] [blame] | 872 | /* |
| 873 | * Setup default ECC mode. nand_dt_init() called from nand_scan_ident() |
| 874 | * can overwrite this value if the DT provides a different value. |
| 875 | */ |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 876 | nand->ecc.mode = NAND_ECC_HW; |
| 877 | nand->ecc.hwctl = fsmc_enable_hwecc; |
| 878 | nand->ecc.size = 512; |
| 879 | nand->options = pdata->options; |
| 880 | nand->select_chip = fsmc_select_chip; |
Vipin Kumar | 467e6e7 | 2012-03-14 11:47:12 +0530 | [diff] [blame] | 881 | nand->badblockbits = 7; |
Brian Norris | 6375219 | 2015-10-30 20:33:23 -0700 | [diff] [blame] | 882 | nand_set_flash_node(nand, np); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 883 | |
| 884 | if (pdata->width == FSMC_NAND_BW16) |
| 885 | nand->options |= NAND_BUSWIDTH_16; |
| 886 | |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 887 | switch (host->mode) { |
| 888 | case USE_DMA_ACCESS: |
| 889 | dma_cap_zero(mask); |
| 890 | dma_cap_set(DMA_MEMCPY, mask); |
| 891 | host->read_dma_chan = dma_request_channel(mask, filter, |
| 892 | pdata->read_dma_priv); |
| 893 | if (!host->read_dma_chan) { |
| 894 | dev_err(&pdev->dev, "Unable to get read dma channel\n"); |
| 895 | goto err_req_read_chnl; |
| 896 | } |
| 897 | host->write_dma_chan = dma_request_channel(mask, filter, |
| 898 | pdata->write_dma_priv); |
| 899 | if (!host->write_dma_chan) { |
| 900 | dev_err(&pdev->dev, "Unable to get write dma channel\n"); |
| 901 | goto err_req_write_chnl; |
| 902 | } |
| 903 | nand->read_buf = fsmc_read_buf_dma; |
| 904 | nand->write_buf = fsmc_write_buf_dma; |
| 905 | break; |
| 906 | |
| 907 | default: |
| 908 | case USE_WORD_ACCESS: |
Vipin Kumar | 604e754 | 2012-03-14 11:47:17 +0530 | [diff] [blame] | 909 | nand->read_buf = fsmc_read_buf; |
| 910 | nand->write_buf = fsmc_write_buf; |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 911 | break; |
Vipin Kumar | 604e754 | 2012-03-14 11:47:17 +0530 | [diff] [blame] | 912 | } |
| 913 | |
Vipin Kumar | 2a5dbead | 2012-03-14 11:47:19 +0530 | [diff] [blame] | 914 | fsmc_nand_setup(host->regs_va, host->bank, |
| 915 | nand->options & NAND_BUSWIDTH_16, |
Vipin Kumar | e2f6bce | 2012-03-14 11:47:14 +0530 | [diff] [blame] | 916 | host->dev_timings); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 917 | |
Linus Walleij | 593cd87 | 2010-11-29 13:52:19 +0100 | [diff] [blame] | 918 | if (AMBA_REV_BITS(host->pid) >= 8) { |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 919 | nand->ecc.read_page = fsmc_read_page_hwecc; |
| 920 | nand->ecc.calculate = fsmc_read_hwecc_ecc4; |
Armando Visconti | 753e013 | 2012-03-07 17:00:54 +0530 | [diff] [blame] | 921 | nand->ecc.correct = fsmc_bch8_correct_data; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 922 | nand->ecc.bytes = 13; |
Mike Dunn | 6a918ba | 2012-03-11 14:21:11 -0700 | [diff] [blame] | 923 | nand->ecc.strength = 8; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 924 | } |
| 925 | |
| 926 | /* |
Lucas De Marchi | 25985ed | 2011-03-30 22:57:33 -0300 | [diff] [blame] | 927 | * Scan to find existence of the device |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 928 | */ |
Boris BREZILLON | bdf3a55 | 2015-12-10 09:00:05 +0100 | [diff] [blame] | 929 | if (nand_scan_ident(mtd, 1, NULL)) { |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 930 | ret = -ENXIO; |
| 931 | dev_err(&pdev->dev, "No NAND Device found!\n"); |
Vipin Kumar | 82b9dbe | 2012-03-14 11:47:15 +0530 | [diff] [blame] | 932 | goto err_scan_ident; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 933 | } |
| 934 | |
Linus Walleij | 593cd87 | 2010-11-29 13:52:19 +0100 | [diff] [blame] | 935 | if (AMBA_REV_BITS(host->pid) >= 8) { |
Boris BREZILLON | bdf3a55 | 2015-12-10 09:00:05 +0100 | [diff] [blame] | 936 | switch (mtd->oobsize) { |
Bhavna Yadav | e29ee57 | 2012-03-07 17:00:50 +0530 | [diff] [blame] | 937 | case 16: |
Bhavna Yadav | e29ee57 | 2012-03-07 17:00:50 +0530 | [diff] [blame] | 938 | case 64: |
Bhavna Yadav | e29ee57 | 2012-03-07 17:00:50 +0530 | [diff] [blame] | 939 | case 128: |
Armando Visconti | 0c78e93 | 2012-03-07 17:00:55 +0530 | [diff] [blame] | 940 | case 224: |
Bhavna Yadav | e29ee57 | 2012-03-07 17:00:50 +0530 | [diff] [blame] | 941 | case 256: |
Bhavna Yadav | e29ee57 | 2012-03-07 17:00:50 +0530 | [diff] [blame] | 942 | break; |
| 943 | default: |
Jingoo Han | 67b19a6 | 2013-12-26 12:31:25 +0900 | [diff] [blame] | 944 | dev_warn(&pdev->dev, "No oob scheme defined for oobsize %d\n", |
| 945 | mtd->oobsize); |
Stefan Roese | 6efadcf | 2015-10-02 12:40:21 +0200 | [diff] [blame] | 946 | ret = -EINVAL; |
| 947 | goto err_probe; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 948 | } |
Boris Brezillon | 22b4695 | 2016-02-03 20:01:42 +0100 | [diff] [blame] | 949 | |
| 950 | mtd_set_ooblayout(mtd, &fsmc_ecc4_ooblayout_ops); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 951 | } else { |
Stefan Roese | e278fc7 | 2015-10-19 08:40:13 +0200 | [diff] [blame] | 952 | switch (nand->ecc.mode) { |
| 953 | case NAND_ECC_HW: |
| 954 | dev_info(&pdev->dev, "Using 1-bit HW ECC scheme\n"); |
| 955 | nand->ecc.calculate = fsmc_read_hwecc_ecc1; |
| 956 | nand->ecc.correct = nand_correct_data; |
| 957 | nand->ecc.bytes = 3; |
| 958 | nand->ecc.strength = 1; |
Bhavna Yadav | e29ee57 | 2012-03-07 17:00:50 +0530 | [diff] [blame] | 959 | break; |
Stefan Roese | e278fc7 | 2015-10-19 08:40:13 +0200 | [diff] [blame] | 960 | |
Rafał Miłecki | ef296dc | 2016-04-17 22:53:04 +0200 | [diff] [blame] | 961 | case NAND_ECC_SOFT: |
Rafał Miłecki | ef296dc | 2016-04-17 22:53:04 +0200 | [diff] [blame] | 962 | if (nand->ecc.algo == NAND_ECC_BCH) { |
| 963 | dev_info(&pdev->dev, "Using 4-bit SW BCH ECC scheme\n"); |
| 964 | break; |
| 965 | } |
Stefan Roese | e278fc7 | 2015-10-19 08:40:13 +0200 | [diff] [blame] | 966 | |
Bhavna Yadav | e29ee57 | 2012-03-07 17:00:50 +0530 | [diff] [blame] | 967 | default: |
Stefan Roese | e278fc7 | 2015-10-19 08:40:13 +0200 | [diff] [blame] | 968 | dev_err(&pdev->dev, "Unsupported ECC mode!\n"); |
Stefan Roese | 6efadcf | 2015-10-02 12:40:21 +0200 | [diff] [blame] | 969 | goto err_probe; |
Bhavna Yadav | e29ee57 | 2012-03-07 17:00:50 +0530 | [diff] [blame] | 970 | } |
Stefan Roese | e278fc7 | 2015-10-19 08:40:13 +0200 | [diff] [blame] | 971 | |
| 972 | /* |
| 973 | * Don't set layout for BCH4 SW ECC. This will be |
| 974 | * generated later in nand_bch_init() later. |
| 975 | */ |
Rafał Miłecki | e4225ae | 2016-04-17 22:53:07 +0200 | [diff] [blame] | 976 | if (nand->ecc.mode == NAND_ECC_HW) { |
Boris BREZILLON | bdf3a55 | 2015-12-10 09:00:05 +0100 | [diff] [blame] | 977 | switch (mtd->oobsize) { |
Stefan Roese | e278fc7 | 2015-10-19 08:40:13 +0200 | [diff] [blame] | 978 | case 16: |
Stefan Roese | e278fc7 | 2015-10-19 08:40:13 +0200 | [diff] [blame] | 979 | case 64: |
Stefan Roese | e278fc7 | 2015-10-19 08:40:13 +0200 | [diff] [blame] | 980 | case 128: |
Boris Brezillon | 22b4695 | 2016-02-03 20:01:42 +0100 | [diff] [blame] | 981 | mtd_set_ooblayout(mtd, |
| 982 | &fsmc_ecc1_ooblayout_ops); |
Stefan Roese | e278fc7 | 2015-10-19 08:40:13 +0200 | [diff] [blame] | 983 | break; |
| 984 | default: |
| 985 | dev_warn(&pdev->dev, |
| 986 | "No oob scheme defined for oobsize %d\n", |
| 987 | mtd->oobsize); |
| 988 | ret = -EINVAL; |
| 989 | goto err_probe; |
| 990 | } |
| 991 | } |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 992 | } |
| 993 | |
| 994 | /* Second stage of scan to fill MTD data-structures */ |
Boris BREZILLON | bdf3a55 | 2015-12-10 09:00:05 +0100 | [diff] [blame] | 995 | if (nand_scan_tail(mtd)) { |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 996 | ret = -ENXIO; |
| 997 | goto err_probe; |
| 998 | } |
| 999 | |
| 1000 | /* |
| 1001 | * The partition information can is accessed by (in the same precedence) |
| 1002 | * |
| 1003 | * command line through Bootloader, |
| 1004 | * platform data, |
| 1005 | * default partition information present in driver. |
| 1006 | */ |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1007 | /* |
Dmitry Eremin-Solenikov | 8d3f8bb | 2011-05-29 20:16:57 +0400 | [diff] [blame] | 1008 | * Check for partition info passed |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1009 | */ |
Boris BREZILLON | bdf3a55 | 2015-12-10 09:00:05 +0100 | [diff] [blame] | 1010 | mtd->name = "nand"; |
| 1011 | ret = mtd_device_register(mtd, host->partitions, host->nr_partitions); |
Jamie Iles | 99335d0 | 2011-05-23 10:23:23 +0100 | [diff] [blame] | 1012 | if (ret) |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1013 | goto err_probe; |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1014 | |
| 1015 | platform_set_drvdata(pdev, host); |
| 1016 | dev_info(&pdev->dev, "FSMC NAND driver registration successful\n"); |
| 1017 | return 0; |
| 1018 | |
| 1019 | err_probe: |
Vipin Kumar | 82b9dbe | 2012-03-14 11:47:15 +0530 | [diff] [blame] | 1020 | err_scan_ident: |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 1021 | if (host->mode == USE_DMA_ACCESS) |
| 1022 | dma_release_channel(host->write_dma_chan); |
| 1023 | err_req_write_chnl: |
| 1024 | if (host->mode == USE_DMA_ACCESS) |
| 1025 | dma_release_channel(host->read_dma_chan); |
| 1026 | err_req_read_chnl: |
Viresh Kumar | e25da1c | 2012-04-17 17:07:57 +0530 | [diff] [blame] | 1027 | clk_disable_unprepare(host->clk); |
| 1028 | err_clk_prepare_enable: |
Vipin Kumar | 82b9dbe | 2012-03-14 11:47:15 +0530 | [diff] [blame] | 1029 | clk_put(host->clk); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1030 | return ret; |
| 1031 | } |
| 1032 | |
| 1033 | /* |
| 1034 | * Clean up routine |
| 1035 | */ |
| 1036 | static int fsmc_nand_remove(struct platform_device *pdev) |
| 1037 | { |
| 1038 | struct fsmc_nand_data *host = platform_get_drvdata(pdev); |
| 1039 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1040 | if (host) { |
Boris BREZILLON | bdf3a55 | 2015-12-10 09:00:05 +0100 | [diff] [blame] | 1041 | nand_release(nand_to_mtd(&host->nand)); |
Vipin Kumar | 4774fb0 | 2012-03-14 11:47:18 +0530 | [diff] [blame] | 1042 | |
| 1043 | if (host->mode == USE_DMA_ACCESS) { |
| 1044 | dma_release_channel(host->write_dma_chan); |
| 1045 | dma_release_channel(host->read_dma_chan); |
| 1046 | } |
Viresh Kumar | e25da1c | 2012-04-17 17:07:57 +0530 | [diff] [blame] | 1047 | clk_disable_unprepare(host->clk); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1048 | clk_put(host->clk); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1049 | } |
Vipin Kumar | 82b9dbe | 2012-03-14 11:47:15 +0530 | [diff] [blame] | 1050 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1051 | return 0; |
| 1052 | } |
| 1053 | |
Jingoo Han | 80ce4dd | 2013-03-26 15:53:48 +0900 | [diff] [blame] | 1054 | #ifdef CONFIG_PM_SLEEP |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1055 | static int fsmc_nand_suspend(struct device *dev) |
| 1056 | { |
| 1057 | struct fsmc_nand_data *host = dev_get_drvdata(dev); |
| 1058 | if (host) |
Viresh Kumar | e25da1c | 2012-04-17 17:07:57 +0530 | [diff] [blame] | 1059 | clk_disable_unprepare(host->clk); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1060 | return 0; |
| 1061 | } |
| 1062 | |
| 1063 | static int fsmc_nand_resume(struct device *dev) |
| 1064 | { |
| 1065 | struct fsmc_nand_data *host = dev_get_drvdata(dev); |
Shiraz Hashim | f63acb7 | 2012-03-14 11:47:13 +0530 | [diff] [blame] | 1066 | if (host) { |
Viresh Kumar | e25da1c | 2012-04-17 17:07:57 +0530 | [diff] [blame] | 1067 | clk_prepare_enable(host->clk); |
Shiraz Hashim | f63acb7 | 2012-03-14 11:47:13 +0530 | [diff] [blame] | 1068 | fsmc_nand_setup(host->regs_va, host->bank, |
Vipin Kumar | e2f6bce | 2012-03-14 11:47:14 +0530 | [diff] [blame] | 1069 | host->nand.options & NAND_BUSWIDTH_16, |
| 1070 | host->dev_timings); |
Shiraz Hashim | f63acb7 | 2012-03-14 11:47:13 +0530 | [diff] [blame] | 1071 | } |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1072 | return 0; |
| 1073 | } |
Jingoo Han | 80ce4dd | 2013-03-26 15:53:48 +0900 | [diff] [blame] | 1074 | #endif |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1075 | |
Shiraz Hashim | f63acb7 | 2012-03-14 11:47:13 +0530 | [diff] [blame] | 1076 | static SIMPLE_DEV_PM_OPS(fsmc_nand_pm_ops, fsmc_nand_suspend, fsmc_nand_resume); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1077 | |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 1078 | #ifdef CONFIG_OF |
| 1079 | static const struct of_device_id fsmc_nand_id_table[] = { |
| 1080 | { .compatible = "st,spear600-fsmc-nand" }, |
Linus Walleij | ba78520 | 2013-01-05 22:28:32 +0100 | [diff] [blame] | 1081 | { .compatible = "stericsson,fsmc-nand" }, |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 1082 | {} |
| 1083 | }; |
| 1084 | MODULE_DEVICE_TABLE(of, fsmc_nand_id_table); |
| 1085 | #endif |
| 1086 | |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1087 | static struct platform_driver fsmc_nand_driver = { |
| 1088 | .remove = fsmc_nand_remove, |
| 1089 | .driver = { |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1090 | .name = "fsmc-nand", |
Stefan Roese | eea6281 | 2012-03-16 10:19:31 +0100 | [diff] [blame] | 1091 | .of_match_table = of_match_ptr(fsmc_nand_id_table), |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1092 | .pm = &fsmc_nand_pm_ops, |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1093 | }, |
| 1094 | }; |
| 1095 | |
Jingoo Han | 307d2a51 | 2013-03-05 13:30:36 +0900 | [diff] [blame] | 1096 | module_platform_driver_probe(fsmc_nand_driver, fsmc_nand_probe); |
Linus Walleij | 6c009ab | 2010-09-13 00:35:22 +0200 | [diff] [blame] | 1097 | |
| 1098 | MODULE_LICENSE("GPL"); |
| 1099 | MODULE_AUTHOR("Vipin Kumar <vipin.kumar@st.com>, Ashish Priyadarshi"); |
| 1100 | MODULE_DESCRIPTION("NAND driver for SPEAr Platforms"); |