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gerrit-public.fairphone.software / kernel / msm-5.4 / 0b81c23d2e3a8589514fa69b2f153f006a4ad773 / . / drivers / net / wireless / b43 / phy_n.c
blob: 9769483156e7990567df34e037415bc889fddb71 [file] [log] [blame]
Michael Buesch424047e2008-01-09 16:13:56 +0100[diff] [blame]1/*
2
3 Broadcom B43 wireless driver
4 IEEE 802.11n PHY support
5
6 Copyright (c) 2008 Michael Buesch <mb@bu3sch.de>
7
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 2 of the License, or
11 (at your option) any later version.
12
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
17
18 You should have received a copy of the GNU General Public License
19 along with this program; see the file COPYING. If not, write to
20 the Free Software Foundation, Inc., 51 Franklin Steet, Fifth Floor,
21 Boston, MA 02110-1301, USA.
22
23*/
24
John W. Linville819d7722008-01-17 16:57:10 -0500[diff] [blame]25#include <linux/delay.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +0900[diff] [blame]26#include <linux/slab.h>
John W. Linville819d7722008-01-17 16:57:10 -0500[diff] [blame]27#include <linux/types.h>
28
Michael Buesch424047e2008-01-09 16:13:56 +0100[diff] [blame]29#include "b43.h"
Michael Buesch3d0da752008-08-30 02:27:19 +0200[diff] [blame]30#include "phy_n.h"
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]31#include "tables_nphy.h"
Rafał Miłecki6db507f2010-10-14 19:33:36 +0200[diff] [blame]32#include "radio_2055.h"
Rafał Miłecki5161bec2010-10-14 21:16:33 +0200[diff] [blame]33#include "radio_2056.h"
Rafał Miłeckibbec3982010-01-15 14:31:39 +0100[diff] [blame]34#include "main.h"
Michael Buesch424047e2008-01-09 16:13:56 +0100[diff] [blame]35
Rafał Miłeckif8187b52010-01-15 12:34:21 +0100[diff] [blame]36struct nphy_txgains {
37 u16 txgm[2];
38 u16 pga[2];
39 u16 pad[2];
40 u16 ipa[2];
41};
42
43struct nphy_iqcal_params {
44 u16 txgm;
45 u16 pga;
46 u16 pad;
47 u16 ipa;
48 u16 cal_gain;
49 u16 ncorr[5];
50};
51
52struct nphy_iq_est {
53 s32 iq0_prod;
54 u32 i0_pwr;
55 u32 q0_pwr;
56 s32 iq1_prod;
57 u32 i1_pwr;
58 u32 q1_pwr;
59};
Michael Buesch424047e2008-01-09 16:13:56 +0100[diff] [blame]60
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100[diff] [blame]61enum b43_nphy_rf_sequence {
62 B43_RFSEQ_RX2TX,
63 B43_RFSEQ_TX2RX,
64 B43_RFSEQ_RESET2RX,
65 B43_RFSEQ_UPDATE_GAINH,
66 B43_RFSEQ_UPDATE_GAINL,
67 B43_RFSEQ_UPDATE_GAINU,
68};
69
Rafał Miłecki9501fef2010-01-30 20:18:07 +0100[diff] [blame]70static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
71 u8 *events, u8 *delays, u8 length);
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100[diff] [blame]72static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
73 enum b43_nphy_rf_sequence seq);
Rafał Miłecki67cbc3e2010-02-04 12:23:08 +0100[diff] [blame]74static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
75 u16 value, u8 core, bool off);
76static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
77 u16 value, u8 core);
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100[diff] [blame]78
Rafał Miłeckie5c407f2010-10-11 03:11:02 +0200[diff] [blame]79static inline bool b43_channel_type_is_40mhz(
80 enum nl80211_channel_type channel_type)
Rafał Miłecki902db912010-02-27 13:03:37 +0100[diff] [blame]81{
Rafał Miłeckie5c407f2010-10-11 03:11:02 +0200[diff] [blame]82 return (channel_type == NL80211_CHAN_HT40MINUS ||
83 channel_type == NL80211_CHAN_HT40PLUS);
Rafał Miłecki902db912010-02-27 13:03:37 +0100[diff] [blame]84}
85
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]86void b43_nphy_set_rxantenna(struct b43_wldev *dev, int antenna)
87{//TODO
88}
89
Michael Buesch18c8ade2008-08-28 19:33:40 +0200[diff] [blame]90static void b43_nphy_op_adjust_txpower(struct b43_wldev *dev)
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]91{//TODO
92}
93
Michael Buesch18c8ade2008-08-28 19:33:40 +0200[diff] [blame]94static enum b43_txpwr_result b43_nphy_op_recalc_txpower(struct b43_wldev *dev,
95 bool ignore_tssi)
96{//TODO
97 return B43_TXPWR_RES_DONE;
98}
99
Michael Bueschd1591312008-01-14 00:05:57 +0100[diff] [blame]100static void b43_chantab_radio_upload(struct b43_wldev *dev,
Rafał Miłeckif19ebe72010-03-29 00:53:15 +0200[diff] [blame]101 const struct b43_nphy_channeltab_entry_rev2 *e)
Michael Bueschd1591312008-01-14 00:05:57 +0100[diff] [blame]102{
Rafał Miłeckie5255ccc2010-02-27 13:03:35 +0100[diff] [blame]103 b43_radio_write(dev, B2055_PLL_REF, e->radio_pll_ref);
104 b43_radio_write(dev, B2055_RF_PLLMOD0, e->radio_rf_pllmod0);
105 b43_radio_write(dev, B2055_RF_PLLMOD1, e->radio_rf_pllmod1);
106 b43_radio_write(dev, B2055_VCO_CAPTAIL, e->radio_vco_captail);
107 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
108
109 b43_radio_write(dev, B2055_VCO_CAL1, e->radio_vco_cal1);
110 b43_radio_write(dev, B2055_VCO_CAL2, e->radio_vco_cal2);
111 b43_radio_write(dev, B2055_PLL_LFC1, e->radio_pll_lfc1);
112 b43_radio_write(dev, B2055_PLL_LFR1, e->radio_pll_lfr1);
113 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
114
115 b43_radio_write(dev, B2055_PLL_LFC2, e->radio_pll_lfc2);
116 b43_radio_write(dev, B2055_LGBUF_CENBUF, e->radio_lgbuf_cenbuf);
117 b43_radio_write(dev, B2055_LGEN_TUNE1, e->radio_lgen_tune1);
118 b43_radio_write(dev, B2055_LGEN_TUNE2, e->radio_lgen_tune2);
119 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
120
121 b43_radio_write(dev, B2055_C1_LGBUF_ATUNE, e->radio_c1_lgbuf_atune);
122 b43_radio_write(dev, B2055_C1_LGBUF_GTUNE, e->radio_c1_lgbuf_gtune);
123 b43_radio_write(dev, B2055_C1_RX_RFR1, e->radio_c1_rx_rfr1);
124 b43_radio_write(dev, B2055_C1_TX_PGAPADTN, e->radio_c1_tx_pgapadtn);
125 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
126
127 b43_radio_write(dev, B2055_C1_TX_MXBGTRIM, e->radio_c1_tx_mxbgtrim);
128 b43_radio_write(dev, B2055_C2_LGBUF_ATUNE, e->radio_c2_lgbuf_atune);
129 b43_radio_write(dev, B2055_C2_LGBUF_GTUNE, e->radio_c2_lgbuf_gtune);
130 b43_radio_write(dev, B2055_C2_RX_RFR1, e->radio_c2_rx_rfr1);
131 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
132
133 b43_radio_write(dev, B2055_C2_TX_PGAPADTN, e->radio_c2_tx_pgapadtn);
134 b43_radio_write(dev, B2055_C2_TX_MXBGTRIM, e->radio_c2_tx_mxbgtrim);
Michael Bueschd1591312008-01-14 00:05:57 +0100[diff] [blame]135}
136
137static void b43_chantab_phy_upload(struct b43_wldev *dev,
Rafał Miłeckib15b3032010-03-29 00:53:13 +0200[diff] [blame]138 const struct b43_phy_n_sfo_cfg *e)
Michael Bueschd1591312008-01-14 00:05:57 +0100[diff] [blame]139{
140 b43_phy_write(dev, B43_NPHY_BW1A, e->phy_bw1a);
141 b43_phy_write(dev, B43_NPHY_BW2, e->phy_bw2);
142 b43_phy_write(dev, B43_NPHY_BW3, e->phy_bw3);
143 b43_phy_write(dev, B43_NPHY_BW4, e->phy_bw4);
144 b43_phy_write(dev, B43_NPHY_BW5, e->phy_bw5);
145 b43_phy_write(dev, B43_NPHY_BW6, e->phy_bw6);
146}
147
148static void b43_nphy_tx_power_fix(struct b43_wldev *dev)
149{
150 //TODO
151}
152
Rafał Miłecki7955de02010-02-27 13:03:39 +0100[diff] [blame]153
154/* http://bcm-v4.sipsolutions.net/802.11/PHY/Radio/2055Setup */
155static void b43_radio_2055_setup(struct b43_wldev *dev,
Rafał Miłeckif19ebe72010-03-29 00:53:15 +0200[diff] [blame]156 const struct b43_nphy_channeltab_entry_rev2 *e)
Rafał Miłecki7955de02010-02-27 13:03:39 +0100[diff] [blame]157{
158 B43_WARN_ON(dev->phy.rev >= 3);
159
160 b43_chantab_radio_upload(dev, e);
161 udelay(50);
Rafał Miłeckie58b1252010-03-29 00:53:16 +0200[diff] [blame]162 b43_radio_write(dev, B2055_VCO_CAL10, 0x05);
163 b43_radio_write(dev, B2055_VCO_CAL10, 0x45);
Rafał Miłecki7955de02010-02-27 13:03:39 +0100[diff] [blame]164 b43_read32(dev, B43_MMIO_MACCTL); /* flush writes */
Rafał Miłeckie58b1252010-03-29 00:53:16 +0200[diff] [blame]165 b43_radio_write(dev, B2055_VCO_CAL10, 0x65);
Rafał Miłecki7955de02010-02-27 13:03:39 +0100[diff] [blame]166 udelay(300);
167}
168
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]169static void b43_radio_init2055_pre(struct b43_wldev *dev)
170{
171 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
172 ~B43_NPHY_RFCTL_CMD_PORFORCE);
173 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
174 B43_NPHY_RFCTL_CMD_CHIP0PU |
175 B43_NPHY_RFCTL_CMD_OEPORFORCE);
176 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
177 B43_NPHY_RFCTL_CMD_PORFORCE);
178}
179
180static void b43_radio_init2055_post(struct b43_wldev *dev)
181{
Rafał Miłecki036cafe2010-02-27 13:03:36 +0100[diff] [blame]182 struct b43_phy_n *nphy = dev->phy.n;
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]183 struct ssb_sprom *sprom = &(dev->dev->bus->sprom);
184 struct ssb_boardinfo *binfo = &(dev->dev->bus->boardinfo);
185 int i;
186 u16 val;
Rafał Miłecki036cafe2010-02-27 13:03:36 +0100[diff] [blame]187 bool workaround = false;
188
189 if (sprom->revision < 4)
190 workaround = (binfo->vendor != PCI_VENDOR_ID_BROADCOM ||
191 binfo->type != 0x46D ||
192 binfo->rev < 0x41);
193 else
Rafał Miłecki7a4db8f2010-10-22 17:43:48 +0200[diff] [blame]194 workaround =
195 !(sprom->boardflags2_lo & B43_BFL2_RXBB_INT_REG_DIS);
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]196
197 b43_radio_mask(dev, B2055_MASTER1, 0xFFF3);
Rafał Miłecki036cafe2010-02-27 13:03:36 +0100[diff] [blame]198 if (workaround) {
199 b43_radio_mask(dev, B2055_C1_RX_BB_REG, 0x7F);
200 b43_radio_mask(dev, B2055_C2_RX_BB_REG, 0x7F);
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]201 }
Rafał Miłecki036cafe2010-02-27 13:03:36 +0100[diff] [blame]202 b43_radio_maskset(dev, B2055_RRCCAL_NOPTSEL, 0xFFC0, 0x2C);
203 b43_radio_write(dev, B2055_CAL_MISC, 0x3C);
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]204 b43_radio_mask(dev, B2055_CAL_MISC, 0xFFBE);
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]205 b43_radio_set(dev, B2055_CAL_LPOCTL, 0x80);
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]206 b43_radio_set(dev, B2055_CAL_MISC, 0x1);
207 msleep(1);
208 b43_radio_set(dev, B2055_CAL_MISC, 0x40);
Rafał Miłecki036cafe2010-02-27 13:03:36 +0100[diff] [blame]209 for (i = 0; i < 200; i++) {
210 val = b43_radio_read(dev, B2055_CAL_COUT2);
211 if (val & 0x80) {
212 i = 0;
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]213 break;
Rafał Miłecki036cafe2010-02-27 13:03:36 +0100[diff] [blame]214 }
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]215 udelay(10);
216 }
Rafał Miłecki036cafe2010-02-27 13:03:36 +0100[diff] [blame]217 if (i)
218 b43err(dev->wl, "radio post init timeout\n");
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]219 b43_radio_mask(dev, B2055_CAL_LPOCTL, 0xFF7F);
Rafał Miłecki78159782010-10-06 07:50:08 +0200[diff] [blame]220 b43_switch_channel(dev, dev->phy.channel);
Rafał Miłecki036cafe2010-02-27 13:03:36 +0100[diff] [blame]221 b43_radio_write(dev, B2055_C1_RX_BB_LPF, 0x9);
222 b43_radio_write(dev, B2055_C2_RX_BB_LPF, 0x9);
223 b43_radio_write(dev, B2055_C1_RX_BB_MIDACHP, 0x83);
224 b43_radio_write(dev, B2055_C2_RX_BB_MIDACHP, 0x83);
225 b43_radio_maskset(dev, B2055_C1_LNA_GAINBST, 0xFFF8, 0x6);
226 b43_radio_maskset(dev, B2055_C2_LNA_GAINBST, 0xFFF8, 0x6);
227 if (!nphy->gain_boost) {
228 b43_radio_set(dev, B2055_C1_RX_RFSPC1, 0x2);
229 b43_radio_set(dev, B2055_C2_RX_RFSPC1, 0x2);
230 } else {
231 b43_radio_mask(dev, B2055_C1_RX_RFSPC1, 0xFFFD);
232 b43_radio_mask(dev, B2055_C2_RX_RFSPC1, 0xFFFD);
233 }
234 udelay(2);
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]235}
236
Rafał Miłeckic2b7aef2010-02-27 13:03:34 +0100[diff] [blame]237/*
238 * Initialize a Broadcom 2055 N-radio
239 * http://bcm-v4.sipsolutions.net/802.11/Radio/2055/Init
240 */
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]241static void b43_radio_init2055(struct b43_wldev *dev)
242{
243 b43_radio_init2055_pre(dev);
Rafał Miłeckia2d9bc62010-10-22 17:43:49 +0200[diff] [blame]244 if (b43_status(dev) < B43_STAT_INITIALIZED) {
245 /* Follow wl, not specs. Do not force uploading all regs */
246 b2055_upload_inittab(dev, 0, 0);
247 } else {
248 bool ghz5 = b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ;
249 b2055_upload_inittab(dev, ghz5, 0);
250 }
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]251 b43_radio_init2055_post(dev);
252}
253
Rafał Miłecki4772ae12010-01-15 12:18:21 +0100[diff] [blame]254/*
Rafał Miłeckid817f4e2010-03-29 00:53:12 +0200[diff] [blame]255 * Initialize a Broadcom 2056 N-radio
256 * http://bcm-v4.sipsolutions.net/802.11/Radio/2056/Init
257 */
258static void b43_radio_init2056(struct b43_wldev *dev)
259{
260 /* TODO */
261}
262
263
264/*
Rafał Miłecki4772ae12010-01-15 12:18:21 +0100[diff] [blame]265 * Upload the N-PHY tables.
266 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/InitTables
267 */
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]268static void b43_nphy_tables_init(struct b43_wldev *dev)
269{
Rafał Miłecki4772ae12010-01-15 12:18:21 +0100[diff] [blame]270 if (dev->phy.rev < 3)
271 b43_nphy_rev0_1_2_tables_init(dev);
272 else
273 b43_nphy_rev3plus_tables_init(dev);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]274}
275
Rafał Miłeckie50cbcf2010-01-15 15:02:38 +0100[diff] [blame]276/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PA%20override */
277static void b43_nphy_pa_override(struct b43_wldev *dev, bool enable)
278{
279 struct b43_phy_n *nphy = dev->phy.n;
280 enum ieee80211_band band;
281 u16 tmp;
282
283 if (!enable) {
284 nphy->rfctrl_intc1_save = b43_phy_read(dev,
285 B43_NPHY_RFCTL_INTC1);
286 nphy->rfctrl_intc2_save = b43_phy_read(dev,
287 B43_NPHY_RFCTL_INTC2);
288 band = b43_current_band(dev->wl);
289 if (dev->phy.rev >= 3) {
290 if (band == IEEE80211_BAND_5GHZ)
291 tmp = 0x600;
292 else
293 tmp = 0x480;
294 } else {
295 if (band == IEEE80211_BAND_5GHZ)
296 tmp = 0x180;
297 else
298 tmp = 0x120;
299 }
300 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
301 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
302 } else {
303 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1,
304 nphy->rfctrl_intc1_save);
305 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2,
306 nphy->rfctrl_intc2_save);
307 }
308}
309
Rafał Miłeckife3e46e2010-01-15 15:51:55 +0100[diff] [blame]310/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxLpFbw */
311static void b43_nphy_tx_lp_fbw(struct b43_wldev *dev)
312{
313 struct b43_phy_n *nphy = dev->phy.n;
314 u16 tmp;
315 enum ieee80211_band band = b43_current_band(dev->wl);
316 bool ipa = (nphy->ipa2g_on && band == IEEE80211_BAND_2GHZ) ||
317 (nphy->ipa5g_on && band == IEEE80211_BAND_5GHZ);
318
319 if (dev->phy.rev >= 3) {
320 if (ipa) {
321 tmp = 4;
322 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S2,
323 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
324 }
325
326 tmp = 1;
327 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S2,
328 (((((tmp << 3) | tmp) << 3) | tmp) << 3) | tmp);
329 }
330}
331
Rafał Miłecki4a933c82010-01-15 13:36:43 +0100[diff] [blame]332/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BmacPhyClkFgc */
333static void b43_nphy_bmac_clock_fgc(struct b43_wldev *dev, bool force)
334{
335 u32 tmslow;
336
337 if (dev->phy.type != B43_PHYTYPE_N)
338 return;
339
340 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
341 if (force)
342 tmslow |= SSB_TMSLOW_FGC;
343 else
344 tmslow &= ~SSB_TMSLOW_FGC;
345 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
346}
347
348/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CCA */
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]349static void b43_nphy_reset_cca(struct b43_wldev *dev)
350{
351 u16 bbcfg;
352
Rafał Miłecki4a933c82010-01-15 13:36:43 +0100[diff] [blame]353 b43_nphy_bmac_clock_fgc(dev, 1);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]354 bbcfg = b43_phy_read(dev, B43_NPHY_BBCFG);
Rafał Miłecki4a933c82010-01-15 13:36:43 +0100[diff] [blame]355 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg | B43_NPHY_BBCFG_RSTCCA);
356 udelay(1);
357 b43_phy_write(dev, B43_NPHY_BBCFG, bbcfg & ~B43_NPHY_BBCFG_RSTCCA);
358 b43_nphy_bmac_clock_fgc(dev, 0);
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100[diff] [blame]359 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]360}
361
Rafał Miłeckiad9716e2010-01-17 13:03:40 +0100[diff] [blame]362/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MIMOConfig */
363static void b43_nphy_update_mimo_config(struct b43_wldev *dev, s32 preamble)
364{
365 u16 mimocfg = b43_phy_read(dev, B43_NPHY_MIMOCFG);
366
367 mimocfg |= B43_NPHY_MIMOCFG_AUTO;
368 if (preamble == 1)
369 mimocfg |= B43_NPHY_MIMOCFG_GFMIX;
370 else
371 mimocfg &= ~B43_NPHY_MIMOCFG_GFMIX;
372
373 b43_phy_write(dev, B43_NPHY_MIMOCFG, mimocfg);
374}
375
Rafał Miłecki4f4ab6c2010-01-17 13:03:55 +0100[diff] [blame]376/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Chains */
377static void b43_nphy_update_txrx_chain(struct b43_wldev *dev)
378{
379 struct b43_phy_n *nphy = dev->phy.n;
380
381 bool override = false;
382 u16 chain = 0x33;
383
384 if (nphy->txrx_chain == 0) {
385 chain = 0x11;
386 override = true;
387 } else if (nphy->txrx_chain == 1) {
388 chain = 0x22;
389 override = true;
390 }
391
392 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
393 ~(B43_NPHY_RFSEQCA_TXEN | B43_NPHY_RFSEQCA_RXEN),
394 chain);
395
396 if (override)
397 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
398 B43_NPHY_RFSEQMODE_CAOVER);
399 else
400 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
401 ~B43_NPHY_RFSEQMODE_CAOVER);
402}
403
Rafał Miłecki2faa6b82010-01-15 15:26:12 +0100[diff] [blame]404/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqEst */
405static void b43_nphy_rx_iq_est(struct b43_wldev *dev, struct nphy_iq_est *est,
406 u16 samps, u8 time, bool wait)
407{
408 int i;
409 u16 tmp;
410
411 b43_phy_write(dev, B43_NPHY_IQEST_SAMCNT, samps);
412 b43_phy_maskset(dev, B43_NPHY_IQEST_WT, ~B43_NPHY_IQEST_WT_VAL, time);
413 if (wait)
414 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_MODE);
415 else
416 b43_phy_mask(dev, B43_NPHY_IQEST_CMD, ~B43_NPHY_IQEST_CMD_MODE);
417
418 b43_phy_set(dev, B43_NPHY_IQEST_CMD, B43_NPHY_IQEST_CMD_START);
419
420 for (i = 1000; i; i--) {
421 tmp = b43_phy_read(dev, B43_NPHY_IQEST_CMD);
422 if (!(tmp & B43_NPHY_IQEST_CMD_START)) {
423 est->i0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI0) << 16) |
424 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO0);
425 est->q0_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI0) << 16) |
426 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO0);
427 est->iq0_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI0) << 16) |
428 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO0);
429
430 est->i1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_IPACC_HI1) << 16) |
431 b43_phy_read(dev, B43_NPHY_IQEST_IPACC_LO1);
432 est->q1_pwr = (b43_phy_read(dev, B43_NPHY_IQEST_QPACC_HI1) << 16) |
433 b43_phy_read(dev, B43_NPHY_IQEST_QPACC_LO1);
434 est->iq1_prod = (b43_phy_read(dev, B43_NPHY_IQEST_IQACC_HI1) << 16) |
435 b43_phy_read(dev, B43_NPHY_IQEST_IQACC_LO1);
436 return;
437 }
438 udelay(10);
439 }
440 memset(est, 0, sizeof(*est));
441}
442
Rafał Miłeckia67162a2010-01-15 15:16:25 +0100[diff] [blame]443/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxIqCoeffs */
444static void b43_nphy_rx_iq_coeffs(struct b43_wldev *dev, bool write,
445 struct b43_phy_n_iq_comp *pcomp)
446{
447 if (write) {
448 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPA0, pcomp->a0);
449 b43_phy_write(dev, B43_NPHY_C1_RXIQ_COMPB0, pcomp->b0);
450 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPA1, pcomp->a1);
451 b43_phy_write(dev, B43_NPHY_C2_RXIQ_COMPB1, pcomp->b1);
452 } else {
453 pcomp->a0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPA0);
454 pcomp->b0 = b43_phy_read(dev, B43_NPHY_C1_RXIQ_COMPB0);
455 pcomp->a1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPA1);
456 pcomp->b1 = b43_phy_read(dev, B43_NPHY_C2_RXIQ_COMPB1);
457 }
458}
459
Rafał Miłecki026816f2010-01-17 13:03:28 +0100[diff] [blame]460/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhyCleanup */
461static void b43_nphy_rx_cal_phy_cleanup(struct b43_wldev *dev, u8 core)
462{
463 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
464
465 b43_phy_write(dev, B43_NPHY_RFSEQCA, regs[0]);
466 if (core == 0) {
467 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[1]);
468 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
469 } else {
470 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
471 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
472 }
473 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[3]);
474 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[4]);
475 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, regs[5]);
476 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, regs[6]);
477 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, regs[7]);
478 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, regs[8]);
479 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
480 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
481}
482
483/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCalPhySetup */
484static void b43_nphy_rx_cal_phy_setup(struct b43_wldev *dev, u8 core)
485{
486 u8 rxval, txval;
487 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
488
489 regs[0] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
490 if (core == 0) {
491 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
492 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
493 } else {
494 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
495 regs[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
496 }
497 regs[3] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
498 regs[4] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
499 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
500 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
501 regs[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S1);
502 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
503 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
504 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
505
506 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
507 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
508
Larry Fingeracd82aa2010-07-21 11:48:05 -0500[diff] [blame]509 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
510 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
Rafał Miłecki026816f2010-01-17 13:03:28 +0100[diff] [blame]511 ((1 - core) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
512 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
513 ((1 - core) << B43_NPHY_RFSEQCA_TXEN_SHIFT));
514 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
515 (core << B43_NPHY_RFSEQCA_RXEN_SHIFT));
516 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXDIS,
517 (core << B43_NPHY_RFSEQCA_TXDIS_SHIFT));
518
519 if (core == 0) {
520 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, ~0x0007);
521 b43_phy_set(dev, B43_NPHY_AFECTL_OVER1, 0x0007);
522 } else {
523 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, ~0x0007);
524 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0007);
525 }
526
Rafał Miłecki67cbc3e2010-02-04 12:23:08 +0100[diff] [blame]527 b43_nphy_rf_control_intc_override(dev, 2, 0, 3);
528 b43_nphy_rf_control_override(dev, 8, 0, 3, false);
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100[diff] [blame]529 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
Rafał Miłecki026816f2010-01-17 13:03:28 +0100[diff] [blame]530
531 if (core == 0) {
532 rxval = 1;
533 txval = 8;
534 } else {
535 rxval = 4;
536 txval = 2;
537 }
Rafał Miłecki67cbc3e2010-02-04 12:23:08 +0100[diff] [blame]538 b43_nphy_rf_control_intc_override(dev, 1, rxval, (core + 1));
539 b43_nphy_rf_control_intc_override(dev, 1, txval, (2 - core));
Rafał Miłecki026816f2010-01-17 13:03:28 +0100[diff] [blame]540}
541
Rafał Miłecki34a56f22010-01-15 15:29:05 +0100[diff] [blame]542/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalcRxIqComp */
543static void b43_nphy_calc_rx_iq_comp(struct b43_wldev *dev, u8 mask)
544{
545 int i;
546 s32 iq;
547 u32 ii;
548 u32 qq;
549 int iq_nbits, qq_nbits;
550 int arsh, brsh;
551 u16 tmp, a, b;
552
553 struct nphy_iq_est est;
554 struct b43_phy_n_iq_comp old;
555 struct b43_phy_n_iq_comp new = { };
556 bool error = false;
557
558 if (mask == 0)
559 return;
560
561 b43_nphy_rx_iq_coeffs(dev, false, &old);
562 b43_nphy_rx_iq_coeffs(dev, true, &new);
563 b43_nphy_rx_iq_est(dev, &est, 0x4000, 32, false);
564 new = old;
565
566 for (i = 0; i < 2; i++) {
567 if (i == 0 && (mask & 1)) {
568 iq = est.iq0_prod;
569 ii = est.i0_pwr;
570 qq = est.q0_pwr;
571 } else if (i == 1 && (mask & 2)) {
572 iq = est.iq1_prod;
573 ii = est.i1_pwr;
574 qq = est.q1_pwr;
575 } else {
Rafał Miłecki34a56f22010-01-15 15:29:05 +0100[diff] [blame]576 continue;
577 }
578
579 if (ii + qq < 2) {
580 error = true;
581 break;
582 }
583
584 iq_nbits = fls(abs(iq));
585 qq_nbits = fls(qq);
586
587 arsh = iq_nbits - 20;
588 if (arsh >= 0) {
589 a = -((iq << (30 - iq_nbits)) + (ii >> (1 + arsh)));
590 tmp = ii >> arsh;
591 } else {
592 a = -((iq << (30 - iq_nbits)) + (ii << (-1 - arsh)));
593 tmp = ii << -arsh;
594 }
595 if (tmp == 0) {
596 error = true;
597 break;
598 }
599 a /= tmp;
600
601 brsh = qq_nbits - 11;
602 if (brsh >= 0) {
603 b = (qq << (31 - qq_nbits));
604 tmp = ii >> brsh;
605 } else {
606 b = (qq << (31 - qq_nbits));
607 tmp = ii << -brsh;
608 }
609 if (tmp == 0) {
610 error = true;
611 break;
612 }
613 b = int_sqrt(b / tmp - a * a) - (1 << 10);
614
615 if (i == 0 && (mask & 0x1)) {
616 if (dev->phy.rev >= 3) {
617 new.a0 = a & 0x3FF;
618 new.b0 = b & 0x3FF;
619 } else {
620 new.a0 = b & 0x3FF;
621 new.b0 = a & 0x3FF;
622 }
623 } else if (i == 1 && (mask & 0x2)) {
624 if (dev->phy.rev >= 3) {
625 new.a1 = a & 0x3FF;
626 new.b1 = b & 0x3FF;
627 } else {
628 new.a1 = b & 0x3FF;
629 new.b1 = a & 0x3FF;
630 }
631 }
632 }
633
634 if (error)
635 new = old;
636
637 b43_nphy_rx_iq_coeffs(dev, true, &new);
638}
639
Rafał Miłecki09146402010-01-15 15:17:10 +0100[diff] [blame]640/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxIqWar */
641static void b43_nphy_tx_iq_workaround(struct b43_wldev *dev)
642{
643 u16 array[4];
644 int i;
645
646 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x3C50);
647 for (i = 0; i < 4; i++)
648 array[i] = b43_phy_read(dev, B43_NPHY_TABLE_DATALO);
649
650 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW0, array[0]);
651 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW1, array[1]);
652 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW2, array[2]);
653 b43_shm_write16(dev, B43_SHM_SHARED, B43_SHM_SH_NPHY_TXIQW3, array[3]);
654}
655
Rafał Miłeckibbec3982010-01-15 14:31:39 +0100[diff] [blame]656/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
Joe Perches20407ed2010-11-20 18:38:57 -0800[diff] [blame]657static void b43_nphy_write_clip_detection(struct b43_wldev *dev,
658 const u16 *clip_st)
Rafał Miłeckibbec3982010-01-15 14:31:39 +0100[diff] [blame]659{
660 b43_phy_write(dev, B43_NPHY_C1_CLIP1THRES, clip_st[0]);
661 b43_phy_write(dev, B43_NPHY_C2_CLIP1THRES, clip_st[1]);
662}
663
664/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/clip-detection */
665static void b43_nphy_read_clip_detection(struct b43_wldev *dev, u16 *clip_st)
666{
667 clip_st[0] = b43_phy_read(dev, B43_NPHY_C1_CLIP1THRES);
668 clip_st[1] = b43_phy_read(dev, B43_NPHY_C2_CLIP1THRES);
669}
670
Rafał Miłecki8987a9e2010-02-27 13:03:33 +0100[diff] [blame]671/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SuperSwitchInit */
672static void b43_nphy_superswitch_init(struct b43_wldev *dev, bool init)
673{
674 if (dev->phy.rev >= 3) {
675 if (!init)
676 return;
677 if (0 /* FIXME */) {
678 b43_ntab_write(dev, B43_NTAB16(9, 2), 0x211);
679 b43_ntab_write(dev, B43_NTAB16(9, 3), 0x222);
680 b43_ntab_write(dev, B43_NTAB16(9, 8), 0x144);
681 b43_ntab_write(dev, B43_NTAB16(9, 12), 0x188);
682 }
683 } else {
684 b43_phy_write(dev, B43_NPHY_GPIO_LOOEN, 0);
685 b43_phy_write(dev, B43_NPHY_GPIO_HIOEN, 0);
686
687 ssb_chipco_gpio_control(&dev->dev->bus->chipco, 0xFC00,
688 0xFC00);
689 b43_write32(dev, B43_MMIO_MACCTL,
690 b43_read32(dev, B43_MMIO_MACCTL) &
691 ~B43_MACCTL_GPOUTSMSK);
692 b43_write16(dev, B43_MMIO_GPIO_MASK,
693 b43_read16(dev, B43_MMIO_GPIO_MASK) | 0xFC00);
694 b43_write16(dev, B43_MMIO_GPIO_CONTROL,
695 b43_read16(dev, B43_MMIO_GPIO_CONTROL) & ~0xFC00);
696
697 if (init) {
698 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
699 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
700 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
701 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
702 }
703 }
704}
705
Rafał Miłeckibbec3982010-01-15 14:31:39 +0100[diff] [blame]706/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/classifier */
707static u16 b43_nphy_classifier(struct b43_wldev *dev, u16 mask, u16 val)
708{
709 u16 tmp;
710
711 if (dev->dev->id.revision == 16)
712 b43_mac_suspend(dev);
713
714 tmp = b43_phy_read(dev, B43_NPHY_CLASSCTL);
715 tmp &= (B43_NPHY_CLASSCTL_CCKEN | B43_NPHY_CLASSCTL_OFDMEN |
716 B43_NPHY_CLASSCTL_WAITEDEN);
717 tmp &= ~mask;
718 tmp |= (val & mask);
719 b43_phy_maskset(dev, B43_NPHY_CLASSCTL, 0xFFF8, tmp);
720
721 if (dev->dev->id.revision == 16)
722 b43_mac_enable(dev);
723
724 return tmp;
725}
726
Rafał Miłecki5c1a1402010-01-15 15:10:54 +0100[diff] [blame]727/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/carriersearch */
728static void b43_nphy_stay_in_carrier_search(struct b43_wldev *dev, bool enable)
729{
730 struct b43_phy *phy = &dev->phy;
731 struct b43_phy_n *nphy = phy->n;
732
733 if (enable) {
Joe Perches20407ed2010-11-20 18:38:57 -0800[diff] [blame]734 static const u16 clip[] = { 0xFFFF, 0xFFFF };
Rafał Miłecki5c1a1402010-01-15 15:10:54 +0100[diff] [blame]735 if (nphy->deaf_count++ == 0) {
736 nphy->classifier_state = b43_nphy_classifier(dev, 0, 0);
737 b43_nphy_classifier(dev, 0x7, 0);
738 b43_nphy_read_clip_detection(dev, nphy->clip_state);
739 b43_nphy_write_clip_detection(dev, clip);
740 }
741 b43_nphy_reset_cca(dev);
742 } else {
743 if (--nphy->deaf_count == 0) {
744 b43_nphy_classifier(dev, 0x7, nphy->classifier_state);
745 b43_nphy_write_clip_detection(dev, nphy->clip_state);
746 }
747 }
748}
749
Rafał Miłecki53ae8e82010-01-17 13:03:48 +0100[diff] [blame]750/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/stop-playback */
751static void b43_nphy_stop_playback(struct b43_wldev *dev)
752{
753 struct b43_phy_n *nphy = dev->phy.n;
754 u16 tmp;
755
756 if (nphy->hang_avoid)
757 b43_nphy_stay_in_carrier_search(dev, 1);
758
759 tmp = b43_phy_read(dev, B43_NPHY_SAMP_STAT);
760 if (tmp & 0x1)
761 b43_phy_set(dev, B43_NPHY_SAMP_CMD, B43_NPHY_SAMP_CMD_STOP);
762 else if (tmp & 0x2)
Larry Fingeracd82aa2010-07-21 11:48:05 -0500[diff] [blame]763 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
Rafał Miłecki53ae8e82010-01-17 13:03:48 +0100[diff] [blame]764
765 b43_phy_mask(dev, B43_NPHY_SAMP_CMD, ~0x0004);
766
767 if (nphy->bb_mult_save & 0x80000000) {
768 tmp = nphy->bb_mult_save & 0xFFFF;
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100[diff] [blame]769 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
Rafał Miłecki53ae8e82010-01-17 13:03:48 +0100[diff] [blame]770 nphy->bb_mult_save = 0;
771 }
772
773 if (nphy->hang_avoid)
774 b43_nphy_stay_in_carrier_search(dev, 0);
775}
776
Rafał Miłecki9442e5b2010-02-04 12:23:12 +0100[diff] [blame]777/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SpurWar */
778static void b43_nphy_spur_workaround(struct b43_wldev *dev)
779{
780 struct b43_phy_n *nphy = dev->phy.n;
781
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]782 u8 channel = dev->phy.channel;
Rafał Miłecki9442e5b2010-02-04 12:23:12 +0100[diff] [blame]783 int tone[2] = { 57, 58 };
784 u32 noise[2] = { 0x3FF, 0x3FF };
785
786 B43_WARN_ON(dev->phy.rev < 3);
787
788 if (nphy->hang_avoid)
789 b43_nphy_stay_in_carrier_search(dev, 1);
790
Rafał Miłecki9442e5b2010-02-04 12:23:12 +0100[diff] [blame]791 if (nphy->gband_spurwar_en) {
792 /* TODO: N PHY Adjust Analog Pfbw (7) */
793 if (channel == 11 && dev->phy.is_40mhz)
794 ; /* TODO: N PHY Adjust Min Noise Var(2, tone, noise)*/
795 else
796 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
797 /* TODO: N PHY Adjust CRS Min Power (0x1E) */
798 }
799
800 if (nphy->aband_spurwar_en) {
801 if (channel == 54) {
802 tone[0] = 0x20;
803 noise[0] = 0x25F;
804 } else if (channel == 38 || channel == 102 || channel == 118) {
805 if (0 /* FIXME */) {
806 tone[0] = 0x20;
807 noise[0] = 0x21F;
808 } else {
809 tone[0] = 0;
810 noise[0] = 0;
811 }
812 } else if (channel == 134) {
813 tone[0] = 0x20;
814 noise[0] = 0x21F;
815 } else if (channel == 151) {
816 tone[0] = 0x10;
817 noise[0] = 0x23F;
818 } else if (channel == 153 || channel == 161) {
819 tone[0] = 0x30;
820 noise[0] = 0x23F;
821 } else {
822 tone[0] = 0;
823 noise[0] = 0;
824 }
825
826 if (!tone[0] && !noise[0])
827 ; /* TODO: N PHY Adjust Min Noise Var(1, tone, noise)*/
828 else
829 ; /* TODO: N PHY Adjust Min Noise Var(0, NULL, NULL)*/
830 }
831
832 if (nphy->hang_avoid)
833 b43_nphy_stay_in_carrier_search(dev, 0);
834}
835
Rafał Miłeckid24019a2010-02-27 13:03:38 +0100[diff] [blame]836/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/AdjustLnaGainTbl */
837static void b43_nphy_adjust_lna_gain_table(struct b43_wldev *dev)
838{
839 struct b43_phy_n *nphy = dev->phy.n;
840
841 u8 i;
842 s16 tmp;
843 u16 data[4];
844 s16 gain[2];
845 u16 minmax[2];
Joe Perches20407ed2010-11-20 18:38:57 -0800[diff] [blame]846 static const u16 lna_gain[4] = { -2, 10, 19, 25 };
Rafał Miłeckid24019a2010-02-27 13:03:38 +0100[diff] [blame]847
848 if (nphy->hang_avoid)
849 b43_nphy_stay_in_carrier_search(dev, 1);
850
851 if (nphy->gain_boost) {
852 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
853 gain[0] = 6;
854 gain[1] = 6;
855 } else {
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]856 tmp = 40370 - 315 * dev->phy.channel;
Rafał Miłeckid24019a2010-02-27 13:03:38 +0100[diff] [blame]857 gain[0] = ((tmp >> 13) + ((tmp >> 12) & 1));
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]858 tmp = 23242 - 224 * dev->phy.channel;
Rafał Miłeckid24019a2010-02-27 13:03:38 +0100[diff] [blame]859 gain[1] = ((tmp >> 13) + ((tmp >> 12) & 1));
860 }
861 } else {
862 gain[0] = 0;
863 gain[1] = 0;
864 }
865
866 for (i = 0; i < 2; i++) {
867 if (nphy->elna_gain_config) {
868 data[0] = 19 + gain[i];
869 data[1] = 25 + gain[i];
870 data[2] = 25 + gain[i];
871 data[3] = 25 + gain[i];
872 } else {
873 data[0] = lna_gain[0] + gain[i];
874 data[1] = lna_gain[1] + gain[i];
875 data[2] = lna_gain[2] + gain[i];
876 data[3] = lna_gain[3] + gain[i];
877 }
Rafał Miłeckic0f05b92010-11-18 13:27:58 +0100[diff] [blame]878 b43_ntab_write_bulk(dev, B43_NTAB16(i, 8), 4, data);
Rafał Miłeckid24019a2010-02-27 13:03:38 +0100[diff] [blame]879
880 minmax[i] = 23 + gain[i];
881 }
882
883 b43_phy_maskset(dev, B43_NPHY_C1_MINMAX_GAIN, ~B43_NPHY_C1_MINGAIN,
884 minmax[0] << B43_NPHY_C1_MINGAIN_SHIFT);
885 b43_phy_maskset(dev, B43_NPHY_C2_MINMAX_GAIN, ~B43_NPHY_C2_MINGAIN,
886 minmax[1] << B43_NPHY_C2_MINGAIN_SHIFT);
887
888 if (nphy->hang_avoid)
889 b43_nphy_stay_in_carrier_search(dev, 0);
890}
891
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]892/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/WorkaroundsGainCtrl */
Gábor Stefanike723ef32010-08-16 22:39:15 +0200[diff] [blame]893static void b43_nphy_gain_ctrl_workarounds(struct b43_wldev *dev)
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]894{
895 struct b43_phy_n *nphy = dev->phy.n;
896 u8 i, j;
897 u8 code;
Rafał Miłeckic0f05b92010-11-18 13:27:58 +0100[diff] [blame]898 u16 tmp;
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]899
900 /* TODO: for PHY >= 3
901 s8 *lna1_gain, *lna2_gain;
902 u8 *gain_db, *gain_bits;
903 u16 *rfseq_init;
904 u8 lpf_gain[6] = { 0x00, 0x06, 0x0C, 0x12, 0x12, 0x12 };
905 u8 lpf_bits[6] = { 0, 1, 2, 3, 3, 3 };
906 */
907
908 u8 rfseq_events[3] = { 6, 8, 7 };
909 u8 rfseq_delays[3] = { 10, 30, 1 };
910
911 if (dev->phy.rev >= 3) {
912 /* TODO */
913 } else {
914 /* Set Clip 2 detect */
915 b43_phy_set(dev, B43_NPHY_C1_CGAINI,
916 B43_NPHY_C1_CGAINI_CL2DETECT);
917 b43_phy_set(dev, B43_NPHY_C2_CGAINI,
918 B43_NPHY_C2_CGAINI_CL2DETECT);
919
920 /* Set narrowband clip threshold */
Rafał Miłeckia5d35982010-11-18 13:27:59 +0100[diff] [blame]921 b43_phy_write(dev, B43_NPHY_C1_NBCLIPTHRES, 0x84);
922 b43_phy_write(dev, B43_NPHY_C2_NBCLIPTHRES, 0x84);
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]923
924 if (!dev->phy.is_40mhz) {
925 /* Set dwell lengths */
Rafał Miłeckia5d35982010-11-18 13:27:59 +0100[diff] [blame]926 b43_phy_write(dev, B43_NPHY_CLIP1_NBDWELL_LEN, 0x002B);
927 b43_phy_write(dev, B43_NPHY_CLIP2_NBDWELL_LEN, 0x002B);
928 b43_phy_write(dev, B43_NPHY_W1CLIP1_DWELL_LEN, 0x0009);
929 b43_phy_write(dev, B43_NPHY_W1CLIP2_DWELL_LEN, 0x0009);
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]930 }
931
932 /* Set wideband clip 2 threshold */
933 b43_phy_maskset(dev, B43_NPHY_C1_CLIPWBTHRES,
934 ~B43_NPHY_C1_CLIPWBTHRES_CLIP2,
935 21);
936 b43_phy_maskset(dev, B43_NPHY_C2_CLIPWBTHRES,
937 ~B43_NPHY_C2_CLIPWBTHRES_CLIP2,
938 21);
939
940 if (!dev->phy.is_40mhz) {
941 b43_phy_maskset(dev, B43_NPHY_C1_CGAINI,
942 ~B43_NPHY_C1_CGAINI_GAINBKOFF, 0x1);
943 b43_phy_maskset(dev, B43_NPHY_C2_CGAINI,
944 ~B43_NPHY_C2_CGAINI_GAINBKOFF, 0x1);
945 b43_phy_maskset(dev, B43_NPHY_C1_CCK_CGAINI,
946 ~B43_NPHY_C1_CCK_CGAINI_GAINBKOFF, 0x1);
947 b43_phy_maskset(dev, B43_NPHY_C2_CCK_CGAINI,
948 ~B43_NPHY_C2_CCK_CGAINI_GAINBKOFF, 0x1);
949 }
950
Rafał Miłeckia5d35982010-11-18 13:27:59 +0100[diff] [blame]951 b43_phy_write(dev, B43_NPHY_CCK_SHIFTB_REF, 0x809C);
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]952
953 if (nphy->gain_boost) {
954 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ &&
955 dev->phy.is_40mhz)
956 code = 4;
957 else
958 code = 5;
959 } else {
960 code = dev->phy.is_40mhz ? 6 : 7;
961 }
962
963 /* Set HPVGA2 index */
964 b43_phy_maskset(dev, B43_NPHY_C1_INITGAIN,
965 ~B43_NPHY_C1_INITGAIN_HPVGA2,
966 code << B43_NPHY_C1_INITGAIN_HPVGA2_SHIFT);
967 b43_phy_maskset(dev, B43_NPHY_C2_INITGAIN,
968 ~B43_NPHY_C2_INITGAIN_HPVGA2,
969 code << B43_NPHY_C2_INITGAIN_HPVGA2_SHIFT);
970
971 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
Rafał Miłeckia5d35982010-11-18 13:27:59 +0100[diff] [blame]972 /* specs say about 2 loops, but wl does 4 */
973 for (i = 0; i < 4; i++)
974 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
975 (code << 8 | 0x7C));
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]976
Rafał Miłeckid24019a2010-02-27 13:03:38 +0100[diff] [blame]977 b43_nphy_adjust_lna_gain_table(dev);
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]978
979 if (nphy->elna_gain_config) {
980 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0808);
981 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
982 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
983 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
984 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
985
986 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x0C08);
987 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0);
988 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
989 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
990 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x1);
991
992 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x1D06);
Rafał Miłeckia5d35982010-11-18 13:27:59 +0100[diff] [blame]993 /* specs say about 2 loops, but wl does 4 */
994 for (i = 0; i < 4; i++)
995 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
996 (code << 8 | 0x74));
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]997 }
998
999 if (dev->phy.rev == 2) {
1000 for (i = 0; i < 4; i++) {
1001 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1002 (0x0400 * i) + 0x0020);
Rafał Miłeckic0f05b92010-11-18 13:27:58 +0100[diff] [blame]1003 for (j = 0; j < 21; j++) {
1004 tmp = j * (i < 2 ? 3 : 1);
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]1005 b43_phy_write(dev,
Rafał Miłeckic0f05b92010-11-18 13:27:58 +0100[diff] [blame]1006 B43_NPHY_TABLE_DATALO, tmp);
1007 }
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]1008 }
1009
Rafał Miłecki9501fef2010-01-30 20:18:07 +0100[diff] [blame]1010 b43_nphy_set_rf_sequence(dev, 5,
1011 rfseq_events, rfseq_delays, 3);
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]1012 b43_phy_maskset(dev, B43_NPHY_OVER_DGAIN1,
Larry Fingeracd82aa2010-07-21 11:48:05 -0500[diff] [blame]1013 ~B43_NPHY_OVER_DGAIN_CCKDGECV & 0xFFFF,
Rafał Miłeckief5127a2010-01-30 00:12:20 +0100[diff] [blame]1014 0x5A << B43_NPHY_OVER_DGAIN_CCKDGECV_SHIFT);
1015
1016 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
1017 b43_phy_maskset(dev, B43_PHY_N(0xC5D),
1018 0xFF80, 4);
1019 }
1020 }
1021}
1022
Rafał Miłecki28fd7da2010-01-30 00:12:19 +0100[diff] [blame]1023/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/Workarounds */
1024static void b43_nphy_workarounds(struct b43_wldev *dev)
1025{
1026 struct ssb_bus *bus = dev->dev->bus;
1027 struct b43_phy *phy = &dev->phy;
1028 struct b43_phy_n *nphy = phy->n;
1029
1030 u8 events1[7] = { 0x0, 0x1, 0x2, 0x8, 0x4, 0x5, 0x3 };
1031 u8 delays1[7] = { 0x8, 0x6, 0x6, 0x2, 0x4, 0x3C, 0x1 };
1032
1033 u8 events2[7] = { 0x0, 0x3, 0x5, 0x4, 0x2, 0x1, 0x8 };
1034 u8 delays2[7] = { 0x8, 0x6, 0x2, 0x4, 0x4, 0x6, 0x1 };
1035
Rafał Miłeckia5d35982010-11-18 13:27:59 +0100[diff] [blame]1036 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
Rafał Miłecki28fd7da2010-01-30 00:12:19 +0100[diff] [blame]1037 b43_nphy_classifier(dev, 1, 0);
1038 else
1039 b43_nphy_classifier(dev, 1, 1);
1040
1041 if (nphy->hang_avoid)
1042 b43_nphy_stay_in_carrier_search(dev, 1);
1043
1044 b43_phy_set(dev, B43_NPHY_IQFLIP,
1045 B43_NPHY_IQFLIP_ADC1 | B43_NPHY_IQFLIP_ADC2);
1046
1047 if (dev->phy.rev >= 3) {
1048 /* TODO */
1049 } else {
1050 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ &&
1051 nphy->band5g_pwrgain) {
1052 b43_radio_mask(dev, B2055_C1_TX_RF_SPARE, ~0x8);
1053 b43_radio_mask(dev, B2055_C2_TX_RF_SPARE, ~0x8);
1054 } else {
1055 b43_radio_set(dev, B2055_C1_TX_RF_SPARE, 0x8);
1056 b43_radio_set(dev, B2055_C2_TX_RF_SPARE, 0x8);
1057 }
1058
1059 /* TODO: convert to b43_ntab_write? */
1060 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2000);
1061 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1062 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2010);
1063 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x000A);
1064 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2002);
1065 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1066 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2012);
1067 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0xCDAA);
1068
1069 if (dev->phy.rev < 2) {
1070 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2008);
1071 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1072 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2018);
1073 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0000);
1074 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2007);
1075 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1076 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2017);
1077 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x7AAB);
1078 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2006);
1079 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1080 b43_phy_write(dev, B43_NPHY_TABLE_ADDR, 0x2016);
1081 b43_phy_write(dev, B43_NPHY_TABLE_DATALO, 0x0800);
1082 }
1083
1084 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO1, 0x2D8);
1085 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0x301);
1086 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_LO2, 0x2D8);
1087 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0x301);
1088
1089 if (bus->sprom.boardflags2_lo & 0x100 &&
1090 bus->boardinfo.type == 0x8B) {
1091 delays1[0] = 0x1;
1092 delays1[5] = 0x14;
1093 }
Rafał Miłecki9501fef2010-01-30 20:18:07 +0100[diff] [blame]1094 b43_nphy_set_rf_sequence(dev, 0, events1, delays1, 7);
1095 b43_nphy_set_rf_sequence(dev, 1, events2, delays2, 7);
Rafał Miłecki28fd7da2010-01-30 00:12:19 +0100[diff] [blame]1096
Gábor Stefanike723ef32010-08-16 22:39:15 +0200[diff] [blame]1097 b43_nphy_gain_ctrl_workarounds(dev);
Rafał Miłecki28fd7da2010-01-30 00:12:19 +0100[diff] [blame]1098
1099 if (dev->phy.rev < 2) {
1100 if (b43_phy_read(dev, B43_NPHY_RXCTL) & 0x2)
Gábor Stefanike7f45d32010-08-16 22:39:14 +0200[diff] [blame]1101 b43_hf_write(dev, b43_hf_read(dev) |
1102 B43_HF_MLADVW);
Rafał Miłecki28fd7da2010-01-30 00:12:19 +0100[diff] [blame]1103 } else if (dev->phy.rev == 2) {
1104 b43_phy_write(dev, B43_NPHY_CRSCHECK2, 0);
1105 b43_phy_write(dev, B43_NPHY_CRSCHECK3, 0);
1106 }
1107
1108 if (dev->phy.rev < 2)
1109 b43_phy_mask(dev, B43_NPHY_SCRAM_SIGCTL,
1110 ~B43_NPHY_SCRAM_SIGCTL_SCM);
1111
1112 /* Set phase track alpha and beta */
1113 b43_phy_write(dev, B43_NPHY_PHASETR_A0, 0x125);
1114 b43_phy_write(dev, B43_NPHY_PHASETR_A1, 0x1B3);
1115 b43_phy_write(dev, B43_NPHY_PHASETR_A2, 0x105);
1116 b43_phy_write(dev, B43_NPHY_PHASETR_B0, 0x16E);
1117 b43_phy_write(dev, B43_NPHY_PHASETR_B1, 0xCD);
1118 b43_phy_write(dev, B43_NPHY_PHASETR_B2, 0x20);
1119
1120 b43_phy_mask(dev, B43_NPHY_PIL_DW1,
Larry Fingeracd82aa2010-07-21 11:48:05 -0500[diff] [blame]1121 ~B43_NPHY_PIL_DW_64QAM & 0xFFFF);
Rafał Miłecki28fd7da2010-01-30 00:12:19 +0100[diff] [blame]1122 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B1, 0xB5);
1123 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B2, 0xA4);
1124 b43_phy_write(dev, B43_NPHY_TXF_20CO_S2B3, 0x00);
1125
1126 if (dev->phy.rev == 2)
1127 b43_phy_set(dev, B43_NPHY_FINERX2_CGC,
1128 B43_NPHY_FINERX2_CGC_DECGC);
1129 }
1130
1131 if (nphy->hang_avoid)
1132 b43_nphy_stay_in_carrier_search(dev, 0);
1133}
1134
Rafał Miłecki5f6393e2010-02-04 13:08:08 +0100[diff] [blame]1135/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/LoadSampleTable */
1136static int b43_nphy_load_samples(struct b43_wldev *dev,
1137 struct b43_c32 *samples, u16 len) {
1138 struct b43_phy_n *nphy = dev->phy.n;
1139 u16 i;
1140 u32 *data;
1141
1142 data = kzalloc(len * sizeof(u32), GFP_KERNEL);
1143 if (!data) {
1144 b43err(dev->wl, "allocation for samples loading failed\n");
1145 return -ENOMEM;
1146 }
1147 if (nphy->hang_avoid)
1148 b43_nphy_stay_in_carrier_search(dev, 1);
1149
1150 for (i = 0; i < len; i++) {
1151 data[i] = (samples[i].i & 0x3FF << 10);
1152 data[i] |= samples[i].q & 0x3FF;
1153 }
1154 b43_ntab_write_bulk(dev, B43_NTAB32(17, 0), len, data);
1155
1156 kfree(data);
1157 if (nphy->hang_avoid)
1158 b43_nphy_stay_in_carrier_search(dev, 0);
1159 return 0;
1160}
1161
Rafał Miłecki59af0992010-01-22 01:53:16 +0100[diff] [blame]1162/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GenLoadSamples */
1163static u16 b43_nphy_gen_load_samples(struct b43_wldev *dev, u32 freq, u16 max,
1164 bool test)
1165{
1166 int i;
Rafał Miłeckif2982182010-01-25 19:00:01 +0100[diff] [blame]1167 u16 bw, len, rot, angle;
Larry Fingerda860472010-01-26 16:42:02 -0600[diff] [blame]1168 struct b43_c32 *samples;
Rafał Miłeckif2982182010-01-25 19:00:01 +0100[diff] [blame]1169
Rafał Miłecki59af0992010-01-22 01:53:16 +0100[diff] [blame]1170
1171 bw = (dev->phy.is_40mhz) ? 40 : 20;
1172 len = bw << 3;
1173
1174 if (test) {
1175 if (b43_phy_read(dev, B43_NPHY_BBCFG) & B43_NPHY_BBCFG_RSTRX)
1176 bw = 82;
1177 else
1178 bw = 80;
1179
1180 if (dev->phy.is_40mhz)
1181 bw <<= 1;
1182
1183 len = bw << 1;
1184 }
1185
Joe Perchesbaeb2ff2010-08-11 07:02:48 +0000[diff] [blame]1186 samples = kcalloc(len, sizeof(struct b43_c32), GFP_KERNEL);
Rafał Miłecki40bd5202010-02-04 13:11:54 +0100[diff] [blame]1187 if (!samples) {
1188 b43err(dev->wl, "allocation for samples generation failed\n");
1189 return 0;
1190 }
Rafał Miłecki59af0992010-01-22 01:53:16 +0100[diff] [blame]1191 rot = (((freq * 36) / bw) << 16) / 100;
1192 angle = 0;
1193
Rafał Miłeckif2982182010-01-25 19:00:01 +0100[diff] [blame]1194 for (i = 0; i < len; i++) {
1195 samples[i] = b43_cordic(angle);
1196 angle += rot;
1197 samples[i].q = CORDIC_CONVERT(samples[i].q * max);
1198 samples[i].i = CORDIC_CONVERT(samples[i].i * max);
Rafał Miłecki59af0992010-01-22 01:53:16 +0100[diff] [blame]1199 }
1200
Rafał Miłecki5f6393e2010-02-04 13:08:08 +0100[diff] [blame]1201 i = b43_nphy_load_samples(dev, samples, len);
Rafał Miłeckif2982182010-01-25 19:00:01 +0100[diff] [blame]1202 kfree(samples);
Rafał Miłecki5f6393e2010-02-04 13:08:08 +0100[diff] [blame]1203 return (i < 0) ? 0 : len;
Rafał Miłecki59af0992010-01-22 01:53:16 +0100[diff] [blame]1204}
1205
Rafał Miłecki10a79872010-01-22 01:53:14 +0100[diff] [blame]1206/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RunSamples */
1207static void b43_nphy_run_samples(struct b43_wldev *dev, u16 samps, u16 loops,
1208 u16 wait, bool iqmode, bool dac_test)
1209{
1210 struct b43_phy_n *nphy = dev->phy.n;
1211 int i;
1212 u16 seq_mode;
1213 u32 tmp;
1214
1215 if (nphy->hang_avoid)
1216 b43_nphy_stay_in_carrier_search(dev, true);
1217
1218 if ((nphy->bb_mult_save & 0x80000000) == 0) {
1219 tmp = b43_ntab_read(dev, B43_NTAB16(15, 87));
1220 nphy->bb_mult_save = (tmp & 0xFFFF) | 0x80000000;
1221 }
1222
1223 if (!dev->phy.is_40mhz)
1224 tmp = 0x6464;
1225 else
1226 tmp = 0x4747;
1227 b43_ntab_write(dev, B43_NTAB16(15, 87), tmp);
1228
1229 if (nphy->hang_avoid)
1230 b43_nphy_stay_in_carrier_search(dev, false);
1231
1232 b43_phy_write(dev, B43_NPHY_SAMP_DEPCNT, (samps - 1));
1233
1234 if (loops != 0xFFFF)
1235 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, (loops - 1));
1236 else
1237 b43_phy_write(dev, B43_NPHY_SAMP_LOOPCNT, loops);
1238
1239 b43_phy_write(dev, B43_NPHY_SAMP_WAITCNT, wait);
1240
1241 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
1242
1243 b43_phy_set(dev, B43_NPHY_RFSEQMODE, B43_NPHY_RFSEQMODE_CAOVER);
1244 if (iqmode) {
1245 b43_phy_mask(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x7FFF);
1246 b43_phy_set(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8000);
1247 } else {
1248 if (dac_test)
1249 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 5);
1250 else
1251 b43_phy_write(dev, B43_NPHY_SAMP_CMD, 1);
1252 }
1253 for (i = 0; i < 100; i++) {
1254 if (b43_phy_read(dev, B43_NPHY_RFSEQST) & 1) {
1255 i = 0;
1256 break;
1257 }
1258 udelay(10);
1259 }
1260 if (i)
1261 b43err(dev->wl, "run samples timeout\n");
1262
1263 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
1264}
1265
Rafał Miłecki59af0992010-01-22 01:53:16 +0100[diff] [blame]1266/*
1267 * Transmits a known value for LO calibration
1268 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/TXTone
1269 */
1270static int b43_nphy_tx_tone(struct b43_wldev *dev, u32 freq, u16 max_val,
1271 bool iqmode, bool dac_test)
1272{
1273 u16 samp = b43_nphy_gen_load_samples(dev, freq, max_val, dac_test);
1274 if (samp == 0)
1275 return -1;
1276 b43_nphy_run_samples(dev, samp, 0xFFFF, 0, iqmode, dac_test);
1277 return 0;
1278}
1279
Rafał Miłecki6dcd9d92010-01-15 16:24:57 +0100[diff] [blame]1280/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxPwrCtrlCoefSetup */
1281static void b43_nphy_tx_pwr_ctrl_coef_setup(struct b43_wldev *dev)
1282{
1283 struct b43_phy_n *nphy = dev->phy.n;
1284 int i, j;
1285 u32 tmp;
1286 u32 cur_real, cur_imag, real_part, imag_part;
1287
1288 u16 buffer[7];
1289
1290 if (nphy->hang_avoid)
1291 b43_nphy_stay_in_carrier_search(dev, true);
1292
Rafał Miłecki91458342010-01-18 00:21:35 +0100[diff] [blame]1293 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
Rafał Miłecki6dcd9d92010-01-15 16:24:57 +0100[diff] [blame]1294
1295 for (i = 0; i < 2; i++) {
1296 tmp = ((buffer[i * 2] & 0x3FF) << 10) |
1297 (buffer[i * 2 + 1] & 0x3FF);
1298 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1299 (((i + 26) << 10) | 320));
1300 for (j = 0; j < 128; j++) {
1301 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1302 ((tmp >> 16) & 0xFFFF));
1303 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1304 (tmp & 0xFFFF));
1305 }
1306 }
1307
1308 for (i = 0; i < 2; i++) {
1309 tmp = buffer[5 + i];
1310 real_part = (tmp >> 8) & 0xFF;
1311 imag_part = (tmp & 0xFF);
1312 b43_phy_write(dev, B43_NPHY_TABLE_ADDR,
1313 (((i + 26) << 10) | 448));
1314
1315 if (dev->phy.rev >= 3) {
1316 cur_real = real_part;
1317 cur_imag = imag_part;
1318 tmp = ((cur_real & 0xFF) << 8) | (cur_imag & 0xFF);
1319 }
1320
1321 for (j = 0; j < 128; j++) {
1322 if (dev->phy.rev < 3) {
1323 cur_real = (real_part * loscale[j] + 128) >> 8;
1324 cur_imag = (imag_part * loscale[j] + 128) >> 8;
1325 tmp = ((cur_real & 0xFF) << 8) |
1326 (cur_imag & 0xFF);
1327 }
1328 b43_phy_write(dev, B43_NPHY_TABLE_DATAHI,
1329 ((tmp >> 16) & 0xFFFF));
1330 b43_phy_write(dev, B43_NPHY_TABLE_DATALO,
1331 (tmp & 0xFFFF));
1332 }
1333 }
1334
1335 if (dev->phy.rev >= 3) {
1336 b43_shm_write16(dev, B43_SHM_SHARED,
1337 B43_SHM_SH_NPHY_TXPWR_INDX0, 0xFFFF);
1338 b43_shm_write16(dev, B43_SHM_SHARED,
1339 B43_SHM_SH_NPHY_TXPWR_INDX1, 0xFFFF);
1340 }
1341
1342 if (nphy->hang_avoid)
1343 b43_nphy_stay_in_carrier_search(dev, false);
1344}
1345
Rafał Miłecki9501fef2010-01-30 20:18:07 +0100[diff] [blame]1346/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRfSeq */
1347static void b43_nphy_set_rf_sequence(struct b43_wldev *dev, u8 cmd,
1348 u8 *events, u8 *delays, u8 length)
1349{
1350 struct b43_phy_n *nphy = dev->phy.n;
1351 u8 i;
1352 u8 end = (dev->phy.rev >= 3) ? 0x1F : 0x0F;
1353 u16 offset1 = cmd << 4;
1354 u16 offset2 = offset1 + 0x80;
1355
1356 if (nphy->hang_avoid)
1357 b43_nphy_stay_in_carrier_search(dev, true);
1358
1359 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset1), length, events);
1360 b43_ntab_write_bulk(dev, B43_NTAB8(7, offset2), length, delays);
1361
1362 for (i = length; i < 16; i++) {
1363 b43_ntab_write(dev, B43_NTAB8(7, offset1 + i), end);
1364 b43_ntab_write(dev, B43_NTAB8(7, offset2 + i), 1);
1365 }
1366
1367 if (nphy->hang_avoid)
1368 b43_nphy_stay_in_carrier_search(dev, false);
1369}
1370
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100[diff] [blame]1371/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ForceRFSeq */
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]1372static void b43_nphy_force_rf_sequence(struct b43_wldev *dev,
1373 enum b43_nphy_rf_sequence seq)
1374{
1375 static const u16 trigger[] = {
1376 [B43_RFSEQ_RX2TX] = B43_NPHY_RFSEQTR_RX2TX,
1377 [B43_RFSEQ_TX2RX] = B43_NPHY_RFSEQTR_TX2RX,
1378 [B43_RFSEQ_RESET2RX] = B43_NPHY_RFSEQTR_RST2RX,
1379 [B43_RFSEQ_UPDATE_GAINH] = B43_NPHY_RFSEQTR_UPGH,
1380 [B43_RFSEQ_UPDATE_GAINL] = B43_NPHY_RFSEQTR_UPGL,
1381 [B43_RFSEQ_UPDATE_GAINU] = B43_NPHY_RFSEQTR_UPGU,
1382 };
1383 int i;
Rafał Miłeckic57199b2010-01-17 13:04:08 +0100[diff] [blame]1384 u16 seq_mode = b43_phy_read(dev, B43_NPHY_RFSEQMODE);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]1385
1386 B43_WARN_ON(seq >= ARRAY_SIZE(trigger));
1387
1388 b43_phy_set(dev, B43_NPHY_RFSEQMODE,
1389 B43_NPHY_RFSEQMODE_CAOVER | B43_NPHY_RFSEQMODE_TROVER);
1390 b43_phy_set(dev, B43_NPHY_RFSEQTR, trigger[seq]);
1391 for (i = 0; i < 200; i++) {
1392 if (!(b43_phy_read(dev, B43_NPHY_RFSEQST) & trigger[seq]))
1393 goto ok;
1394 msleep(1);
1395 }
1396 b43err(dev->wl, "RF sequence status timeout\n");
1397ok:
Rafał Miłeckic57199b2010-01-17 13:04:08 +0100[diff] [blame]1398 b43_phy_write(dev, B43_NPHY_RFSEQMODE, seq_mode);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]1399}
1400
Rafał Miłecki75377b22010-01-22 01:53:13 +0100[diff] [blame]1401/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlOverride */
1402static void b43_nphy_rf_control_override(struct b43_wldev *dev, u16 field,
1403 u16 value, u8 core, bool off)
1404{
1405 int i;
1406 u8 index = fls(field);
1407 u8 addr, en_addr, val_addr;
1408 /* we expect only one bit set */
Rafał Miłecki3ed0fac2010-01-25 18:59:58 +0100[diff] [blame]1409 B43_WARN_ON(field & (~(1 << (index - 1))));
Rafał Miłecki75377b22010-01-22 01:53:13 +0100[diff] [blame]1410
1411 if (dev->phy.rev >= 3) {
1412 const struct nphy_rf_control_override_rev3 *rf_ctrl;
1413 for (i = 0; i < 2; i++) {
1414 if (index == 0 || index == 16) {
1415 b43err(dev->wl,
1416 "Unsupported RF Ctrl Override call\n");
1417 return;
1418 }
1419
1420 rf_ctrl = &tbl_rf_control_override_rev3[index - 1];
1421 en_addr = B43_PHY_N((i == 0) ?
1422 rf_ctrl->en_addr0 : rf_ctrl->en_addr1);
1423 val_addr = B43_PHY_N((i == 0) ?
1424 rf_ctrl->val_addr0 : rf_ctrl->val_addr1);
1425
1426 if (off) {
1427 b43_phy_mask(dev, en_addr, ~(field));
1428 b43_phy_mask(dev, val_addr,
1429 ~(rf_ctrl->val_mask));
1430 } else {
1431 if (core == 0 || ((1 << core) & i) != 0) {
1432 b43_phy_set(dev, en_addr, field);
1433 b43_phy_maskset(dev, val_addr,
1434 ~(rf_ctrl->val_mask),
1435 (value << rf_ctrl->val_shift));
1436 }
1437 }
1438 }
1439 } else {
1440 const struct nphy_rf_control_override_rev2 *rf_ctrl;
1441 if (off) {
1442 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, ~(field));
1443 value = 0;
1444 } else {
1445 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, field);
1446 }
1447
1448 for (i = 0; i < 2; i++) {
1449 if (index <= 1 || index == 16) {
1450 b43err(dev->wl,
1451 "Unsupported RF Ctrl Override call\n");
1452 return;
1453 }
1454
1455 if (index == 2 || index == 10 ||
1456 (index >= 13 && index <= 15)) {
1457 core = 1;
1458 }
1459
1460 rf_ctrl = &tbl_rf_control_override_rev2[index - 2];
1461 addr = B43_PHY_N((i == 0) ?
1462 rf_ctrl->addr0 : rf_ctrl->addr1);
1463
1464 if ((core & (1 << i)) != 0)
1465 b43_phy_maskset(dev, addr, ~(rf_ctrl->bmask),
1466 (value << rf_ctrl->shift));
1467
1468 b43_phy_set(dev, B43_NPHY_RFCTL_OVER, 0x1);
1469 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1470 B43_NPHY_RFCTL_CMD_START);
1471 udelay(1);
1472 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER, 0xFFFE);
1473 }
1474 }
1475}
1476
Rafał Miłecki67cbc3e2010-02-04 12:23:08 +0100[diff] [blame]1477/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RFCtrlIntcOverride */
1478static void b43_nphy_rf_control_intc_override(struct b43_wldev *dev, u8 field,
1479 u16 value, u8 core)
1480{
1481 u8 i, j;
1482 u16 reg, tmp, val;
1483
1484 B43_WARN_ON(dev->phy.rev < 3);
1485 B43_WARN_ON(field > 4);
1486
1487 for (i = 0; i < 2; i++) {
1488 if ((core == 1 && i == 1) || (core == 2 && !i))
1489 continue;
1490
1491 reg = (i == 0) ?
1492 B43_NPHY_RFCTL_INTC1 : B43_NPHY_RFCTL_INTC2;
1493 b43_phy_mask(dev, reg, 0xFBFF);
1494
1495 switch (field) {
1496 case 0:
1497 b43_phy_write(dev, reg, 0);
1498 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
1499 break;
1500 case 1:
1501 if (!i) {
1502 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC1,
1503 0xFC3F, (value << 6));
1504 b43_phy_maskset(dev, B43_NPHY_TXF_40CO_B1S1,
1505 0xFFFE, 1);
1506 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1507 B43_NPHY_RFCTL_CMD_START);
1508 for (j = 0; j < 100; j++) {
1509 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_START) {
1510 j = 0;
1511 break;
1512 }
1513 udelay(10);
1514 }
1515 if (j)
1516 b43err(dev->wl,
1517 "intc override timeout\n");
1518 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S1,
1519 0xFFFE);
1520 } else {
1521 b43_phy_maskset(dev, B43_NPHY_RFCTL_INTC2,
1522 0xFC3F, (value << 6));
1523 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1524 0xFFFE, 1);
1525 b43_phy_set(dev, B43_NPHY_RFCTL_CMD,
1526 B43_NPHY_RFCTL_CMD_RXTX);
1527 for (j = 0; j < 100; j++) {
1528 if (b43_phy_read(dev, B43_NPHY_RFCTL_CMD) & B43_NPHY_RFCTL_CMD_RXTX) {
1529 j = 0;
1530 break;
1531 }
1532 udelay(10);
1533 }
1534 if (j)
1535 b43err(dev->wl,
1536 "intc override timeout\n");
1537 b43_phy_mask(dev, B43_NPHY_RFCTL_OVER,
1538 0xFFFE);
1539 }
1540 break;
1541 case 2:
1542 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1543 tmp = 0x0020;
1544 val = value << 5;
1545 } else {
1546 tmp = 0x0010;
1547 val = value << 4;
1548 }
1549 b43_phy_maskset(dev, reg, ~tmp, val);
1550 break;
1551 case 3:
1552 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1553 tmp = 0x0001;
1554 val = value;
1555 } else {
1556 tmp = 0x0004;
1557 val = value << 2;
1558 }
1559 b43_phy_maskset(dev, reg, ~tmp, val);
1560 break;
1561 case 4:
1562 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
1563 tmp = 0x0002;
1564 val = value << 1;
1565 } else {
1566 tmp = 0x0008;
1567 val = value << 3;
1568 }
1569 b43_phy_maskset(dev, reg, ~tmp, val);
1570 break;
1571 }
1572 }
1573}
1574
Rafał Miłeckibec18642010-11-18 13:28:00 +0100[diff] [blame]1575/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/BPHYInit */
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]1576static void b43_nphy_bphy_init(struct b43_wldev *dev)
1577{
1578 unsigned int i;
1579 u16 val;
1580
1581 val = 0x1E1F;
Rafał Miłeckifee613b2010-11-18 21:11:41 +0100[diff] [blame]1582 for (i = 0; i < 16; i++) {
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]1583 b43_phy_write(dev, B43_PHY_N_BMODE(0x88 + i), val);
1584 val -= 0x202;
1585 }
1586 val = 0x3E3F;
1587 for (i = 0; i < 16; i++) {
Rafał Miłeckifee613b2010-11-18 21:11:41 +0100[diff] [blame]1588 b43_phy_write(dev, B43_PHY_N_BMODE(0x98 + i), val);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]1589 val -= 0x202;
1590 }
1591 b43_phy_write(dev, B43_PHY_N_BMODE(0x38), 0x668);
1592}
1593
Rafał Miłecki3c956272010-01-15 14:38:32 +0100[diff] [blame]1594/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ScaleOffsetRssi */
1595static void b43_nphy_scale_offset_rssi(struct b43_wldev *dev, u16 scale,
1596 s8 offset, u8 core, u8 rail, u8 type)
1597{
1598 u16 tmp;
1599 bool core1or5 = (core == 1) || (core == 5);
1600 bool core2or5 = (core == 2) || (core == 5);
1601
1602 offset = clamp_val(offset, -32, 31);
1603 tmp = ((scale & 0x3F) << 8) | (offset & 0x3F);
1604
1605 if (core1or5 && (rail == 0) && (type == 2))
1606 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, tmp);
1607 if (core1or5 && (rail == 1) && (type == 2))
1608 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, tmp);
1609 if (core2or5 && (rail == 0) && (type == 2))
1610 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, tmp);
1611 if (core2or5 && (rail == 1) && (type == 2))
1612 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, tmp);
1613 if (core1or5 && (rail == 0) && (type == 0))
1614 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, tmp);
1615 if (core1or5 && (rail == 1) && (type == 0))
1616 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, tmp);
1617 if (core2or5 && (rail == 0) && (type == 0))
1618 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, tmp);
1619 if (core2or5 && (rail == 1) && (type == 0))
1620 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, tmp);
1621 if (core1or5 && (rail == 0) && (type == 1))
1622 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, tmp);
1623 if (core1or5 && (rail == 1) && (type == 1))
1624 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, tmp);
1625 if (core2or5 && (rail == 0) && (type == 1))
1626 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, tmp);
1627 if (core2or5 && (rail == 1) && (type == 1))
1628 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, tmp);
1629 if (core1or5 && (rail == 0) && (type == 6))
1630 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TBD, tmp);
1631 if (core1or5 && (rail == 1) && (type == 6))
1632 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TBD, tmp);
1633 if (core2or5 && (rail == 0) && (type == 6))
1634 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TBD, tmp);
1635 if (core2or5 && (rail == 1) && (type == 6))
1636 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TBD, tmp);
1637 if (core1or5 && (rail == 0) && (type == 3))
1638 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_PWRDET, tmp);
1639 if (core1or5 && (rail == 1) && (type == 3))
1640 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_PWRDET, tmp);
1641 if (core2or5 && (rail == 0) && (type == 3))
1642 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_PWRDET, tmp);
1643 if (core2or5 && (rail == 1) && (type == 3))
1644 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_PWRDET, tmp);
1645 if (core1or5 && (type == 4))
1646 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_TSSI, tmp);
1647 if (core2or5 && (type == 4))
1648 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_TSSI, tmp);
1649 if (core1or5 && (type == 5))
1650 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_TSSI, tmp);
1651 if (core2or5 && (type == 5))
1652 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_TSSI, tmp);
1653}
1654
Rafał Miłecki99b82c42010-01-30 20:18:03 +0100[diff] [blame]1655static void b43_nphy_rev2_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
Rafał Miłecki3c956272010-01-15 14:38:32 +0100[diff] [blame]1656{
1657 u16 val;
1658
Rafał Miłecki99b82c42010-01-30 20:18:03 +0100[diff] [blame]1659 if (type < 3)
1660 val = 0;
1661 else if (type == 6)
1662 val = 1;
1663 else if (type == 3)
1664 val = 2;
1665 else
1666 val = 3;
Rafał Miłecki3c956272010-01-15 14:38:32 +0100[diff] [blame]1667
Rafał Miłecki99b82c42010-01-30 20:18:03 +0100[diff] [blame]1668 val = (val << 12) | (val << 14);
1669 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, val);
1670 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, val);
Rafał Miłecki3c956272010-01-15 14:38:32 +0100[diff] [blame]1671
Rafał Miłecki99b82c42010-01-30 20:18:03 +0100[diff] [blame]1672 if (type < 3) {
1673 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO1, 0xFFCF,
1674 (type + 1) << 4);
1675 b43_phy_maskset(dev, B43_NPHY_RFCTL_RSSIO2, 0xFFCF,
1676 (type + 1) << 4);
1677 }
1678
1679 /* TODO use some definitions */
1680 if (code == 0) {
1681 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF, 0);
Rafał Miłecki3c956272010-01-15 14:38:32 +0100[diff] [blame]1682 if (type < 3) {
Rafał Miłecki99b82c42010-01-30 20:18:03 +0100[diff] [blame]1683 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFEC7, 0);
1684 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xEFDC, 0);
1685 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0);
1686 udelay(20);
1687 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
Rafał Miłecki3c956272010-01-15 14:38:32 +0100[diff] [blame]1688 }
Rafał Miłecki99b82c42010-01-30 20:18:03 +0100[diff] [blame]1689 } else {
1690 b43_phy_maskset(dev, B43_NPHY_AFECTL_OVER, 0xCFFF,
1691 0x3000);
1692 if (type < 3) {
1693 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD,
1694 0xFEC7, 0x0180);
1695 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER,
1696 0xEFDC, (code << 1 | 0x1021));
1697 b43_phy_maskset(dev, B43_NPHY_RFCTL_CMD, 0xFFFE, 0x1);
1698 udelay(20);
1699 b43_phy_maskset(dev, B43_NPHY_RFCTL_OVER, 0xFFFE, 0);
Rafał Miłecki3c956272010-01-15 14:38:32 +0100[diff] [blame]1700 }
1701 }
1702}
1703
Rafał Miłecki99b82c42010-01-30 20:18:03 +0100[diff] [blame]1704static void b43_nphy_rev3_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1705{
Rafał Miłecki6e3b15a2010-01-30 20:18:04 +0100[diff] [blame]1706 struct b43_phy_n *nphy = dev->phy.n;
1707 u8 i;
1708 u16 reg, val;
1709
1710 if (code == 0) {
1711 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER1, 0xFDFF);
1712 b43_phy_mask(dev, B43_NPHY_AFECTL_OVER, 0xFDFF);
1713 b43_phy_mask(dev, B43_NPHY_AFECTL_C1, 0xFCFF);
1714 b43_phy_mask(dev, B43_NPHY_AFECTL_C2, 0xFCFF);
1715 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B1S0, 0xFFDF);
1716 b43_phy_mask(dev, B43_NPHY_TXF_40CO_B32S1, 0xFFDF);
1717 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1, 0xFFC3);
1718 b43_phy_mask(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2, 0xFFC3);
1719 } else {
1720 for (i = 0; i < 2; i++) {
1721 if ((code == 1 && i == 1) || (code == 2 && !i))
1722 continue;
1723
1724 reg = (i == 0) ?
1725 B43_NPHY_AFECTL_OVER1 : B43_NPHY_AFECTL_OVER;
1726 b43_phy_maskset(dev, reg, 0xFDFF, 0x0200);
1727
1728 if (type < 3) {
1729 reg = (i == 0) ?
1730 B43_NPHY_AFECTL_C1 :
1731 B43_NPHY_AFECTL_C2;
1732 b43_phy_maskset(dev, reg, 0xFCFF, 0);
1733
1734 reg = (i == 0) ?
1735 B43_NPHY_RFCTL_LUT_TRSW_UP1 :
1736 B43_NPHY_RFCTL_LUT_TRSW_UP2;
1737 b43_phy_maskset(dev, reg, 0xFFC3, 0);
1738
1739 if (type == 0)
1740 val = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ? 4 : 8;
1741 else if (type == 1)
1742 val = 16;
1743 else
1744 val = 32;
1745 b43_phy_set(dev, reg, val);
1746
1747 reg = (i == 0) ?
1748 B43_NPHY_TXF_40CO_B1S0 :
1749 B43_NPHY_TXF_40CO_B32S1;
1750 b43_phy_set(dev, reg, 0x0020);
1751 } else {
1752 if (type == 6)
1753 val = 0x0100;
1754 else if (type == 3)
1755 val = 0x0200;
1756 else
1757 val = 0x0300;
1758
1759 reg = (i == 0) ?
1760 B43_NPHY_AFECTL_C1 :
1761 B43_NPHY_AFECTL_C2;
1762
1763 b43_phy_maskset(dev, reg, 0xFCFF, val);
1764 b43_phy_maskset(dev, reg, 0xF3FF, val << 2);
1765
1766 if (type != 3 && type != 6) {
1767 enum ieee80211_band band =
1768 b43_current_band(dev->wl);
1769
1770 if ((nphy->ipa2g_on &&
1771 band == IEEE80211_BAND_2GHZ) ||
1772 (nphy->ipa5g_on &&
1773 band == IEEE80211_BAND_5GHZ))
1774 val = (band == IEEE80211_BAND_5GHZ) ? 0xC : 0xE;
1775 else
1776 val = 0x11;
1777 reg = (i == 0) ? 0x2000 : 0x3000;
1778 reg |= B2055_PADDRV;
1779 b43_radio_write16(dev, reg, val);
1780
1781 reg = (i == 0) ?
1782 B43_NPHY_AFECTL_OVER1 :
1783 B43_NPHY_AFECTL_OVER;
1784 b43_phy_set(dev, reg, 0x0200);
1785 }
1786 }
1787 }
1788 }
Rafał Miłecki99b82c42010-01-30 20:18:03 +0100[diff] [blame]1789}
1790
1791/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSISel */
1792static void b43_nphy_rssi_select(struct b43_wldev *dev, u8 code, u8 type)
1793{
1794 if (dev->phy.rev >= 3)
1795 b43_nphy_rev3_rssi_select(dev, code, type);
1796 else
1797 b43_nphy_rev2_rssi_select(dev, code, type);
1798}
1799
Rafał Miłeckidfb4aa52010-01-15 14:45:13 +0100[diff] [blame]1800/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetRssi2055Vcm */
1801static void b43_nphy_set_rssi_2055_vcm(struct b43_wldev *dev, u8 type, u8 *buf)
1802{
1803 int i;
1804 for (i = 0; i < 2; i++) {
1805 if (type == 2) {
1806 if (i == 0) {
1807 b43_radio_maskset(dev, B2055_C1_B0NB_RSSIVCM,
1808 0xFC, buf[0]);
1809 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1810 0xFC, buf[1]);
1811 } else {
1812 b43_radio_maskset(dev, B2055_C2_B0NB_RSSIVCM,
1813 0xFC, buf[2 * i]);
1814 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1815 0xFC, buf[2 * i + 1]);
1816 }
1817 } else {
1818 if (i == 0)
1819 b43_radio_maskset(dev, B2055_C1_RX_BB_RSSICTL5,
1820 0xF3, buf[0] << 2);
1821 else
1822 b43_radio_maskset(dev, B2055_C2_RX_BB_RSSICTL5,
1823 0xF3, buf[2 * i + 1] << 2);
1824 }
1825 }
1826}
1827
1828/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/PollRssi */
1829static int b43_nphy_poll_rssi(struct b43_wldev *dev, u8 type, s32 *buf,
1830 u8 nsamp)
1831{
1832 int i;
1833 int out;
1834 u16 save_regs_phy[9];
1835 u16 s[2];
1836
1837 if (dev->phy.rev >= 3) {
1838 save_regs_phy[0] = b43_phy_read(dev,
1839 B43_NPHY_RFCTL_LUT_TRSW_UP1);
1840 save_regs_phy[1] = b43_phy_read(dev,
1841 B43_NPHY_RFCTL_LUT_TRSW_UP2);
1842 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1843 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1844 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
1845 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1846 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B1S0);
1847 save_regs_phy[7] = b43_phy_read(dev, B43_NPHY_TXF_40CO_B32S1);
Rafał Miłeckia529cec2010-11-18 21:11:42 +0100[diff] [blame]1848 } else if (dev->phy.rev == 2) {
1849 save_regs_phy[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
1850 save_regs_phy[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
1851 save_regs_phy[2] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
1852 save_regs_phy[3] = b43_phy_read(dev, B43_NPHY_RFCTL_CMD);
1853 save_regs_phy[4] = b43_phy_read(dev, B43_NPHY_RFCTL_OVER);
1854 save_regs_phy[5] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO1);
1855 save_regs_phy[6] = b43_phy_read(dev, B43_NPHY_RFCTL_RSSIO2);
Rafał Miłeckidfb4aa52010-01-15 14:45:13 +0100[diff] [blame]1856 }
1857
1858 b43_nphy_rssi_select(dev, 5, type);
1859
1860 if (dev->phy.rev < 2) {
1861 save_regs_phy[8] = b43_phy_read(dev, B43_NPHY_GPIO_SEL);
1862 b43_phy_write(dev, B43_NPHY_GPIO_SEL, 5);
1863 }
1864
1865 for (i = 0; i < 4; i++)
1866 buf[i] = 0;
1867
1868 for (i = 0; i < nsamp; i++) {
1869 if (dev->phy.rev < 2) {
1870 s[0] = b43_phy_read(dev, B43_NPHY_GPIO_LOOUT);
1871 s[1] = b43_phy_read(dev, B43_NPHY_GPIO_HIOUT);
1872 } else {
1873 s[0] = b43_phy_read(dev, B43_NPHY_RSSI1);
1874 s[1] = b43_phy_read(dev, B43_NPHY_RSSI2);
1875 }
1876
1877 buf[0] += ((s8)((s[0] & 0x3F) << 2)) >> 2;
1878 buf[1] += ((s8)(((s[0] >> 8) & 0x3F) << 2)) >> 2;
1879 buf[2] += ((s8)((s[1] & 0x3F) << 2)) >> 2;
1880 buf[3] += ((s8)(((s[1] >> 8) & 0x3F) << 2)) >> 2;
1881 }
1882 out = (buf[0] & 0xFF) << 24 | (buf[1] & 0xFF) << 16 |
1883 (buf[2] & 0xFF) << 8 | (buf[3] & 0xFF);
1884
1885 if (dev->phy.rev < 2)
1886 b43_phy_write(dev, B43_NPHY_GPIO_SEL, save_regs_phy[8]);
1887
1888 if (dev->phy.rev >= 3) {
1889 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP1,
1890 save_regs_phy[0]);
1891 b43_phy_write(dev, B43_NPHY_RFCTL_LUT_TRSW_UP2,
1892 save_regs_phy[1]);
1893 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[2]);
1894 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[3]);
1895 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, save_regs_phy[4]);
1896 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[5]);
1897 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, save_regs_phy[6]);
1898 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, save_regs_phy[7]);
Rafał Miłeckia529cec2010-11-18 21:11:42 +0100[diff] [blame]1899 } else if (dev->phy.rev == 2) {
1900 b43_phy_write(dev, B43_NPHY_AFECTL_C1, save_regs_phy[0]);
1901 b43_phy_write(dev, B43_NPHY_AFECTL_C2, save_regs_phy[1]);
1902 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, save_regs_phy[2]);
1903 b43_phy_write(dev, B43_NPHY_RFCTL_CMD, save_regs_phy[3]);
1904 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, save_regs_phy[4]);
1905 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO1, save_regs_phy[5]);
1906 b43_phy_write(dev, B43_NPHY_RFCTL_RSSIO2, save_regs_phy[6]);
Rafał Miłeckidfb4aa52010-01-15 14:45:13 +0100[diff] [blame]1907 }
1908
1909 return out;
1910}
1911
Rafał Miłecki4cb99772010-01-15 13:40:58 +0100[diff] [blame]1912/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal */
1913static void b43_nphy_rev2_rssi_cal(struct b43_wldev *dev, u8 type)
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]1914{
Rafał Miłecki90b97382010-01-15 14:48:21 +0100[diff] [blame]1915 int i, j;
1916 u8 state[4];
1917 u8 code, val;
1918 u16 class, override;
1919 u8 regs_save_radio[2];
1920 u16 regs_save_phy[2];
1921 s8 offset[4];
1922
1923 u16 clip_state[2];
1924 u16 clip_off[2] = { 0xFFFF, 0xFFFF };
1925 s32 results_min[4] = { };
1926 u8 vcm_final[4] = { };
1927 s32 results[4][4] = { };
1928 s32 miniq[4][2] = { };
1929
1930 if (type == 2) {
1931 code = 0;
1932 val = 6;
1933 } else if (type < 2) {
1934 code = 25;
1935 val = 4;
1936 } else {
1937 B43_WARN_ON(1);
1938 return;
1939 }
1940
1941 class = b43_nphy_classifier(dev, 0, 0);
1942 b43_nphy_classifier(dev, 7, 4);
1943 b43_nphy_read_clip_detection(dev, clip_state);
1944 b43_nphy_write_clip_detection(dev, clip_off);
1945
1946 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
1947 override = 0x140;
1948 else
1949 override = 0x110;
1950
1951 regs_save_phy[0] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
1952 regs_save_radio[0] = b43_radio_read16(dev, B2055_C1_PD_RXTX);
1953 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, override);
1954 b43_radio_write16(dev, B2055_C1_PD_RXTX, val);
1955
1956 regs_save_phy[1] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
1957 regs_save_radio[1] = b43_radio_read16(dev, B2055_C2_PD_RXTX);
1958 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, override);
1959 b43_radio_write16(dev, B2055_C2_PD_RXTX, val);
1960
1961 state[0] = b43_radio_read16(dev, B2055_C1_PD_RSSIMISC) & 0x07;
1962 state[1] = b43_radio_read16(dev, B2055_C2_PD_RSSIMISC) & 0x07;
1963 b43_radio_mask(dev, B2055_C1_PD_RSSIMISC, 0xF8);
1964 b43_radio_mask(dev, B2055_C2_PD_RSSIMISC, 0xF8);
1965 state[2] = b43_radio_read16(dev, B2055_C1_SP_RSSI) & 0x07;
1966 state[3] = b43_radio_read16(dev, B2055_C2_SP_RSSI) & 0x07;
1967
1968 b43_nphy_rssi_select(dev, 5, type);
1969 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 0, type);
1970 b43_nphy_scale_offset_rssi(dev, 0, 0, 5, 1, type);
1971
1972 for (i = 0; i < 4; i++) {
1973 u8 tmp[4];
1974 for (j = 0; j < 4; j++)
1975 tmp[j] = i;
1976 if (type != 1)
1977 b43_nphy_set_rssi_2055_vcm(dev, type, tmp);
1978 b43_nphy_poll_rssi(dev, type, results[i], 8);
1979 if (type < 2)
1980 for (j = 0; j < 2; j++)
1981 miniq[i][j] = min(results[i][2 * j],
1982 results[i][2 * j + 1]);
1983 }
1984
1985 for (i = 0; i < 4; i++) {
1986 s32 mind = 40;
1987 u8 minvcm = 0;
1988 s32 minpoll = 249;
1989 s32 curr;
1990 for (j = 0; j < 4; j++) {
1991 if (type == 2)
1992 curr = abs(results[j][i]);
1993 else
1994 curr = abs(miniq[j][i / 2] - code * 8);
1995
1996 if (curr < mind) {
1997 mind = curr;
1998 minvcm = j;
1999 }
2000
2001 if (results[j][i] < minpoll)
2002 minpoll = results[j][i];
2003 }
2004 results_min[i] = minpoll;
2005 vcm_final[i] = minvcm;
2006 }
2007
2008 if (type != 1)
2009 b43_nphy_set_rssi_2055_vcm(dev, type, vcm_final);
2010
2011 for (i = 0; i < 4; i++) {
2012 offset[i] = (code * 8) - results[vcm_final[i]][i];
2013
2014 if (offset[i] < 0)
2015 offset[i] = -((abs(offset[i]) + 4) / 8);
2016 else
2017 offset[i] = (offset[i] + 4) / 8;
2018
2019 if (results_min[i] == 248)
2020 offset[i] = code - 32;
2021
2022 if (i % 2 == 0)
2023 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 1, 0,
2024 type);
2025 else
2026 b43_nphy_scale_offset_rssi(dev, 0, offset[i], 2, 1,
2027 type);
2028 }
2029
2030 b43_radio_maskset(dev, B2055_C1_PD_RSSIMISC, 0xF8, state[0]);
Rafał Miłecki0b81c232010-11-18 21:11:43 +0100[diff] [blame^]2031 b43_radio_maskset(dev, B2055_C2_PD_RSSIMISC, 0xF8, state[1]);
Rafał Miłecki90b97382010-01-15 14:48:21 +0100[diff] [blame]2032
2033 switch (state[2]) {
2034 case 1:
2035 b43_nphy_rssi_select(dev, 1, 2);
2036 break;
2037 case 4:
2038 b43_nphy_rssi_select(dev, 1, 0);
2039 break;
2040 case 2:
2041 b43_nphy_rssi_select(dev, 1, 1);
2042 break;
2043 default:
2044 b43_nphy_rssi_select(dev, 1, 1);
2045 break;
2046 }
2047
2048 switch (state[3]) {
2049 case 1:
2050 b43_nphy_rssi_select(dev, 2, 2);
2051 break;
2052 case 4:
2053 b43_nphy_rssi_select(dev, 2, 0);
2054 break;
2055 default:
2056 b43_nphy_rssi_select(dev, 2, 1);
2057 break;
2058 }
2059
2060 b43_nphy_rssi_select(dev, 0, type);
2061
2062 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs_save_phy[0]);
2063 b43_radio_write16(dev, B2055_C1_PD_RXTX, regs_save_radio[0]);
2064 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs_save_phy[1]);
2065 b43_radio_write16(dev, B2055_C2_PD_RXTX, regs_save_radio[1]);
2066
2067 b43_nphy_classifier(dev, 7, class);
2068 b43_nphy_write_clip_detection(dev, clip_state);
Rafał Miłecki4cb99772010-01-15 13:40:58 +0100[diff] [blame]2069}
2070
2071/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICalRev3 */
2072static void b43_nphy_rev3_rssi_cal(struct b43_wldev *dev)
2073{
2074 /* TODO */
2075}
2076
2077/*
2078 * RSSI Calibration
2079 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RSSICal
2080 */
2081static void b43_nphy_rssi_cal(struct b43_wldev *dev)
2082{
2083 if (dev->phy.rev >= 3) {
2084 b43_nphy_rev3_rssi_cal(dev);
2085 } else {
2086 b43_nphy_rev2_rssi_cal(dev, 2);
2087 b43_nphy_rev2_rssi_cal(dev, 0);
2088 b43_nphy_rev2_rssi_cal(dev, 1);
2089 }
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]2090}
2091
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]2092/*
Rafał Miłecki42e15472010-01-15 15:06:47 +0100[diff] [blame]2093 * Restore RSSI Calibration
2094 * http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreRssiCal
2095 */
2096static void b43_nphy_restore_rssi_cal(struct b43_wldev *dev)
2097{
2098 struct b43_phy_n *nphy = dev->phy.n;
2099
2100 u16 *rssical_radio_regs = NULL;
2101 u16 *rssical_phy_regs = NULL;
2102
2103 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]2104 if (!nphy->rssical_chanspec_2G.center_freq)
Rafał Miłecki42e15472010-01-15 15:06:47 +0100[diff] [blame]2105 return;
2106 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_2G;
2107 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_2G;
2108 } else {
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]2109 if (!nphy->rssical_chanspec_5G.center_freq)
Rafał Miłecki42e15472010-01-15 15:06:47 +0100[diff] [blame]2110 return;
2111 rssical_radio_regs = nphy->rssical_cache.rssical_radio_regs_5G;
2112 rssical_phy_regs = nphy->rssical_cache.rssical_phy_regs_5G;
2113 }
2114
2115 /* TODO use some definitions */
2116 b43_radio_maskset(dev, 0x602B, 0xE3, rssical_radio_regs[0]);
2117 b43_radio_maskset(dev, 0x702B, 0xE3, rssical_radio_regs[1]);
2118
2119 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Z, rssical_phy_regs[0]);
2120 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Z, rssical_phy_regs[1]);
2121 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Z, rssical_phy_regs[2]);
2122 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Z, rssical_phy_regs[3]);
2123
2124 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_X, rssical_phy_regs[4]);
2125 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_X, rssical_phy_regs[5]);
2126 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_X, rssical_phy_regs[6]);
2127 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_X, rssical_phy_regs[7]);
2128
2129 b43_phy_write(dev, B43_NPHY_RSSIMC_0I_RSSI_Y, rssical_phy_regs[8]);
2130 b43_phy_write(dev, B43_NPHY_RSSIMC_0Q_RSSI_Y, rssical_phy_regs[9]);
2131 b43_phy_write(dev, B43_NPHY_RSSIMC_1I_RSSI_Y, rssical_phy_regs[10]);
2132 b43_phy_write(dev, B43_NPHY_RSSIMC_1Q_RSSI_Y, rssical_phy_regs[11]);
2133}
2134
Rafał Miłecki2f258b72010-01-15 15:18:35 +0100[diff] [blame]2135/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetIpaGainTbl */
2136static const u32 *b43_nphy_get_ipa_gain_table(struct b43_wldev *dev)
2137{
2138 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2139 if (dev->phy.rev >= 6) {
2140 /* TODO If the chip is 47162
2141 return txpwrctrl_tx_gain_ipa_rev5 */
2142 return txpwrctrl_tx_gain_ipa_rev6;
2143 } else if (dev->phy.rev >= 5) {
2144 return txpwrctrl_tx_gain_ipa_rev5;
2145 } else {
2146 return txpwrctrl_tx_gain_ipa;
2147 }
2148 } else {
2149 return txpwrctrl_tx_gain_ipa_5g;
2150 }
2151}
2152
Rafał Miłeckic4a92002010-01-15 15:55:18 +0100[diff] [blame]2153/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalRadioSetup */
2154static void b43_nphy_tx_cal_radio_setup(struct b43_wldev *dev)
2155{
2156 struct b43_phy_n *nphy = dev->phy.n;
2157 u16 *save = nphy->tx_rx_cal_radio_saveregs;
Rafał Miłecki52cb5e92010-01-30 20:18:06 +0100[diff] [blame]2158 u16 tmp;
2159 u8 offset, i;
Rafał Miłeckic4a92002010-01-15 15:55:18 +0100[diff] [blame]2160
2161 if (dev->phy.rev >= 3) {
Rafał Miłecki52cb5e92010-01-30 20:18:06 +0100[diff] [blame]2162 for (i = 0; i < 2; i++) {
2163 tmp = (i == 0) ? 0x2000 : 0x3000;
2164 offset = i * 11;
2165
2166 save[offset + 0] = b43_radio_read16(dev, B2055_CAL_RVARCTL);
2167 save[offset + 1] = b43_radio_read16(dev, B2055_CAL_LPOCTL);
2168 save[offset + 2] = b43_radio_read16(dev, B2055_CAL_TS);
2169 save[offset + 3] = b43_radio_read16(dev, B2055_CAL_RCCALRTS);
2170 save[offset + 4] = b43_radio_read16(dev, B2055_CAL_RCALRTS);
2171 save[offset + 5] = b43_radio_read16(dev, B2055_PADDRV);
2172 save[offset + 6] = b43_radio_read16(dev, B2055_XOCTL1);
2173 save[offset + 7] = b43_radio_read16(dev, B2055_XOCTL2);
2174 save[offset + 8] = b43_radio_read16(dev, B2055_XOREGUL);
2175 save[offset + 9] = b43_radio_read16(dev, B2055_XOMISC);
2176 save[offset + 10] = b43_radio_read16(dev, B2055_PLL_LFC1);
2177
2178 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2179 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x0A);
2180 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2181 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2182 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2183 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2184 if (nphy->ipa5g_on) {
2185 b43_radio_write16(dev, tmp | B2055_PADDRV, 4);
2186 b43_radio_write16(dev, tmp | B2055_XOCTL1, 1);
2187 } else {
2188 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2189 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0x2F);
2190 }
2191 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2192 } else {
2193 b43_radio_write16(dev, tmp | B2055_CAL_RVARCTL, 0x06);
2194 b43_radio_write16(dev, tmp | B2055_CAL_LPOCTL, 0x40);
2195 b43_radio_write16(dev, tmp | B2055_CAL_TS, 0x55);
2196 b43_radio_write16(dev, tmp | B2055_CAL_RCCALRTS, 0);
2197 b43_radio_write16(dev, tmp | B2055_CAL_RCALRTS, 0);
2198 b43_radio_write16(dev, tmp | B2055_XOCTL1, 0);
2199 if (nphy->ipa2g_on) {
2200 b43_radio_write16(dev, tmp | B2055_PADDRV, 6);
2201 b43_radio_write16(dev, tmp | B2055_XOCTL2,
2202 (dev->phy.rev < 5) ? 0x11 : 0x01);
2203 } else {
2204 b43_radio_write16(dev, tmp | B2055_PADDRV, 0);
2205 b43_radio_write16(dev, tmp | B2055_XOCTL2, 0);
2206 }
2207 }
2208 b43_radio_write16(dev, tmp | B2055_XOREGUL, 0);
2209 b43_radio_write16(dev, tmp | B2055_XOMISC, 0);
2210 b43_radio_write16(dev, tmp | B2055_PLL_LFC1, 0);
2211 }
Rafał Miłeckic4a92002010-01-15 15:55:18 +0100[diff] [blame]2212 } else {
2213 save[0] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL1);
2214 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL1, 0x29);
2215
2216 save[1] = b43_radio_read16(dev, B2055_C1_TX_RF_IQCAL2);
2217 b43_radio_write16(dev, B2055_C1_TX_RF_IQCAL2, 0x54);
2218
2219 save[2] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL1);
2220 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL1, 0x29);
2221
2222 save[3] = b43_radio_read16(dev, B2055_C2_TX_RF_IQCAL2);
2223 b43_radio_write16(dev, B2055_C2_TX_RF_IQCAL2, 0x54);
2224
2225 save[3] = b43_radio_read16(dev, B2055_C1_PWRDET_RXTX);
2226 save[4] = b43_radio_read16(dev, B2055_C2_PWRDET_RXTX);
2227
2228 if (!(b43_phy_read(dev, B43_NPHY_BANDCTL) &
2229 B43_NPHY_BANDCTL_5GHZ)) {
2230 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x04);
2231 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x04);
2232 } else {
2233 b43_radio_write16(dev, B2055_C1_PWRDET_RXTX, 0x20);
2234 b43_radio_write16(dev, B2055_C2_PWRDET_RXTX, 0x20);
2235 }
2236
2237 if (dev->phy.rev < 2) {
2238 b43_radio_set(dev, B2055_C1_TX_BB_MXGM, 0x20);
2239 b43_radio_set(dev, B2055_C2_TX_BB_MXGM, 0x20);
2240 } else {
2241 b43_radio_mask(dev, B2055_C1_TX_BB_MXGM, ~0x20);
2242 b43_radio_mask(dev, B2055_C2_TX_BB_MXGM, ~0x20);
2243 }
2244 }
2245}
2246
Rafał Miłeckie9762492010-01-15 16:08:25 +0100[diff] [blame]2247/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IqCalGainParams */
2248static void b43_nphy_iq_cal_gain_params(struct b43_wldev *dev, u16 core,
2249 struct nphy_txgains target,
2250 struct nphy_iqcal_params *params)
2251{
2252 int i, j, indx;
2253 u16 gain;
2254
2255 if (dev->phy.rev >= 3) {
2256 params->txgm = target.txgm[core];
2257 params->pga = target.pga[core];
2258 params->pad = target.pad[core];
2259 params->ipa = target.ipa[core];
2260 params->cal_gain = (params->txgm << 12) | (params->pga << 8) |
2261 (params->pad << 4) | (params->ipa);
2262 for (j = 0; j < 5; j++)
2263 params->ncorr[j] = 0x79;
2264 } else {
2265 gain = (target.pad[core]) | (target.pga[core] << 4) |
2266 (target.txgm[core] << 8);
2267
2268 indx = (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) ?
2269 1 : 0;
2270 for (i = 0; i < 9; i++)
2271 if (tbl_iqcal_gainparams[indx][i][0] == gain)
2272 break;
2273 i = min(i, 8);
2274
2275 params->txgm = tbl_iqcal_gainparams[indx][i][1];
2276 params->pga = tbl_iqcal_gainparams[indx][i][2];
2277 params->pad = tbl_iqcal_gainparams[indx][i][3];
2278 params->cal_gain = (params->txgm << 7) | (params->pga << 4) |
2279 (params->pad << 2);
2280 for (j = 0; j < 4; j++)
2281 params->ncorr[j] = tbl_iqcal_gainparams[indx][i][4 + j];
2282 }
2283}
2284
Rafał Miłeckide7ed0c2010-01-15 16:06:35 +0100[diff] [blame]2285/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/UpdateTxCalLadder */
2286static void b43_nphy_update_tx_cal_ladder(struct b43_wldev *dev, u16 core)
2287{
2288 struct b43_phy_n *nphy = dev->phy.n;
2289 int i;
2290 u16 scale, entry;
2291
2292 u16 tmp = nphy->txcal_bbmult;
2293 if (core == 0)
2294 tmp >>= 8;
2295 tmp &= 0xff;
2296
2297 for (i = 0; i < 18; i++) {
2298 scale = (ladder_lo[i].percent * tmp) / 100;
2299 entry = ((scale & 0xFF) << 8) | ladder_lo[i].g_env;
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100[diff] [blame]2300 b43_ntab_write(dev, B43_NTAB16(15, i), entry);
Rafał Miłeckide7ed0c2010-01-15 16:06:35 +0100[diff] [blame]2301
2302 scale = (ladder_iq[i].percent * tmp) / 100;
2303 entry = ((scale & 0xFF) << 8) | ladder_iq[i].g_env;
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100[diff] [blame]2304 b43_ntab_write(dev, B43_NTAB16(15, i + 32), entry);
Rafał Miłeckide7ed0c2010-01-15 16:06:35 +0100[diff] [blame]2305 }
2306}
2307
Rafał Miłecki45ca6972010-01-22 01:53:15 +0100[diff] [blame]2308/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ExtPaSetTxDigiFilts */
2309static void b43_nphy_ext_pa_set_tx_dig_filters(struct b43_wldev *dev)
2310{
2311 int i;
2312 for (i = 0; i < 15; i++)
2313 b43_phy_write(dev, B43_PHY_N(0x2C5 + i),
2314 tbl_tx_filter_coef_rev4[2][i]);
2315}
2316
2317/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/IpaSetTxDigiFilts */
2318static void b43_nphy_int_pa_set_tx_dig_filters(struct b43_wldev *dev)
2319{
2320 int i, j;
2321 /* B43_NPHY_TXF_20CO_S0A1, B43_NPHY_TXF_40CO_S0A1, unknown */
Joe Perches20407ed2010-11-20 18:38:57 -0800[diff] [blame]2322 static const u16 offset[] = { 0x186, 0x195, 0x2C5 };
Rafał Miłecki45ca6972010-01-22 01:53:15 +0100[diff] [blame]2323
2324 for (i = 0; i < 3; i++)
2325 for (j = 0; j < 15; j++)
2326 b43_phy_write(dev, B43_PHY_N(offset[i] + j),
2327 tbl_tx_filter_coef_rev4[i][j]);
2328
2329 if (dev->phy.is_40mhz) {
2330 for (j = 0; j < 15; j++)
2331 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2332 tbl_tx_filter_coef_rev4[3][j]);
2333 } else if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ) {
2334 for (j = 0; j < 15; j++)
2335 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2336 tbl_tx_filter_coef_rev4[5][j]);
2337 }
2338
2339 if (dev->phy.channel == 14)
2340 for (j = 0; j < 15; j++)
2341 b43_phy_write(dev, B43_PHY_N(offset[0] + j),
2342 tbl_tx_filter_coef_rev4[6][j]);
2343}
2344
Rafał Miłeckib0022e12010-01-15 15:40:50 +0100[diff] [blame]2345/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/GetTxGain */
2346static struct nphy_txgains b43_nphy_get_tx_gains(struct b43_wldev *dev)
2347{
2348 struct b43_phy_n *nphy = dev->phy.n;
2349
2350 u16 curr_gain[2];
2351 struct nphy_txgains target;
2352 const u32 *table = NULL;
2353
2354 if (nphy->txpwrctrl == 0) {
2355 int i;
2356
2357 if (nphy->hang_avoid)
2358 b43_nphy_stay_in_carrier_search(dev, true);
Rafał Miłecki91458342010-01-18 00:21:35 +0100[diff] [blame]2359 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, curr_gain);
Rafał Miłeckib0022e12010-01-15 15:40:50 +0100[diff] [blame]2360 if (nphy->hang_avoid)
2361 b43_nphy_stay_in_carrier_search(dev, false);
2362
2363 for (i = 0; i < 2; ++i) {
2364 if (dev->phy.rev >= 3) {
2365 target.ipa[i] = curr_gain[i] & 0x000F;
2366 target.pad[i] = (curr_gain[i] & 0x00F0) >> 4;
2367 target.pga[i] = (curr_gain[i] & 0x0F00) >> 8;
2368 target.txgm[i] = (curr_gain[i] & 0x7000) >> 12;
2369 } else {
2370 target.ipa[i] = curr_gain[i] & 0x0003;
2371 target.pad[i] = (curr_gain[i] & 0x000C) >> 2;
2372 target.pga[i] = (curr_gain[i] & 0x0070) >> 4;
2373 target.txgm[i] = (curr_gain[i] & 0x0380) >> 7;
2374 }
2375 }
2376 } else {
2377 int i;
2378 u16 index[2];
2379 index[0] = (b43_phy_read(dev, B43_NPHY_C1_TXPCTL_STAT) &
2380 B43_NPHY_TXPCTL_STAT_BIDX) >>
2381 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2382 index[1] = (b43_phy_read(dev, B43_NPHY_C2_TXPCTL_STAT) &
2383 B43_NPHY_TXPCTL_STAT_BIDX) >>
2384 B43_NPHY_TXPCTL_STAT_BIDX_SHIFT;
2385
2386 for (i = 0; i < 2; ++i) {
2387 if (dev->phy.rev >= 3) {
2388 enum ieee80211_band band =
2389 b43_current_band(dev->wl);
2390
2391 if ((nphy->ipa2g_on &&
2392 band == IEEE80211_BAND_2GHZ) ||
2393 (nphy->ipa5g_on &&
2394 band == IEEE80211_BAND_5GHZ)) {
2395 table = b43_nphy_get_ipa_gain_table(dev);
2396 } else {
2397 if (band == IEEE80211_BAND_5GHZ) {
2398 if (dev->phy.rev == 3)
2399 table = b43_ntab_tx_gain_rev3_5ghz;
2400 else if (dev->phy.rev == 4)
2401 table = b43_ntab_tx_gain_rev4_5ghz;
2402 else
2403 table = b43_ntab_tx_gain_rev5plus_5ghz;
2404 } else {
2405 table = b43_ntab_tx_gain_rev3plus_2ghz;
2406 }
2407 }
2408
2409 target.ipa[i] = (table[index[i]] >> 16) & 0xF;
2410 target.pad[i] = (table[index[i]] >> 20) & 0xF;
2411 target.pga[i] = (table[index[i]] >> 24) & 0xF;
2412 target.txgm[i] = (table[index[i]] >> 28) & 0xF;
2413 } else {
2414 table = b43_ntab_tx_gain_rev0_1_2;
2415
2416 target.ipa[i] = (table[index[i]] >> 16) & 0x3;
2417 target.pad[i] = (table[index[i]] >> 18) & 0x3;
2418 target.pga[i] = (table[index[i]] >> 20) & 0x7;
2419 target.txgm[i] = (table[index[i]] >> 23) & 0x7;
2420 }
2421 }
2422 }
2423
2424 return target;
2425}
2426
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2427/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhyCleanup */
2428static void b43_nphy_tx_cal_phy_cleanup(struct b43_wldev *dev)
2429{
2430 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2431
2432 if (dev->phy.rev >= 3) {
2433 b43_phy_write(dev, B43_NPHY_AFECTL_C1, regs[0]);
2434 b43_phy_write(dev, B43_NPHY_AFECTL_C2, regs[1]);
2435 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, regs[2]);
2436 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[3]);
2437 b43_phy_write(dev, B43_NPHY_BBCFG, regs[4]);
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100[diff] [blame]2438 b43_ntab_write(dev, B43_NTAB16(8, 3), regs[5]);
2439 b43_ntab_write(dev, B43_NTAB16(8, 19), regs[6]);
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2440 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[7]);
2441 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[8]);
2442 b43_phy_write(dev, B43_NPHY_PAPD_EN0, regs[9]);
2443 b43_phy_write(dev, B43_NPHY_PAPD_EN1, regs[10]);
2444 b43_nphy_reset_cca(dev);
2445 } else {
2446 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, regs[0]);
2447 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, regs[1]);
2448 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, regs[2]);
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100[diff] [blame]2449 b43_ntab_write(dev, B43_NTAB16(8, 2), regs[3]);
2450 b43_ntab_write(dev, B43_NTAB16(8, 18), regs[4]);
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2451 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, regs[5]);
2452 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, regs[6]);
2453 }
2454}
2455
2456/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/TxCalPhySetup */
2457static void b43_nphy_tx_cal_phy_setup(struct b43_wldev *dev)
2458{
2459 u16 *regs = dev->phy.n->tx_rx_cal_phy_saveregs;
2460 u16 tmp;
2461
2462 regs[0] = b43_phy_read(dev, B43_NPHY_AFECTL_C1);
2463 regs[1] = b43_phy_read(dev, B43_NPHY_AFECTL_C2);
2464 if (dev->phy.rev >= 3) {
2465 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0xF0FF, 0x0A00);
2466 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0xF0FF, 0x0A00);
2467
2468 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER1);
2469 regs[2] = tmp;
2470 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, tmp | 0x0600);
2471
2472 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2473 regs[3] = tmp;
2474 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x0600);
2475
2476 regs[4] = b43_phy_read(dev, B43_NPHY_BBCFG);
Larry Fingeracd82aa2010-07-21 11:48:05 -0500[diff] [blame]2477 b43_phy_mask(dev, B43_NPHY_BBCFG,
2478 ~B43_NPHY_BBCFG_RSTRX & 0xFFFF);
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2479
Rafał Miłeckic643a662010-01-18 00:21:27 +0100[diff] [blame]2480 tmp = b43_ntab_read(dev, B43_NTAB16(8, 3));
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2481 regs[5] = tmp;
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100[diff] [blame]2482 b43_ntab_write(dev, B43_NTAB16(8, 3), 0);
Rafał Miłeckic643a662010-01-18 00:21:27 +0100[diff] [blame]2483
2484 tmp = b43_ntab_read(dev, B43_NTAB16(8, 19));
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2485 regs[6] = tmp;
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100[diff] [blame]2486 b43_ntab_write(dev, B43_NTAB16(8, 19), 0);
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2487 regs[7] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2488 regs[8] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2489
Rafał Miłecki67cbc3e2010-02-04 12:23:08 +0100[diff] [blame]2490 b43_nphy_rf_control_intc_override(dev, 2, 1, 3);
2491 b43_nphy_rf_control_intc_override(dev, 1, 2, 1);
2492 b43_nphy_rf_control_intc_override(dev, 1, 8, 2);
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2493
2494 regs[9] = b43_phy_read(dev, B43_NPHY_PAPD_EN0);
2495 regs[10] = b43_phy_read(dev, B43_NPHY_PAPD_EN1);
2496 b43_phy_mask(dev, B43_NPHY_PAPD_EN0, ~0x0001);
2497 b43_phy_mask(dev, B43_NPHY_PAPD_EN1, ~0x0001);
2498 } else {
2499 b43_phy_maskset(dev, B43_NPHY_AFECTL_C1, 0x0FFF, 0xA000);
2500 b43_phy_maskset(dev, B43_NPHY_AFECTL_C2, 0x0FFF, 0xA000);
2501 tmp = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2502 regs[2] = tmp;
2503 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp | 0x3000);
Rafał Miłeckic643a662010-01-18 00:21:27 +0100[diff] [blame]2504 tmp = b43_ntab_read(dev, B43_NTAB16(8, 2));
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2505 regs[3] = tmp;
2506 tmp |= 0x2000;
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100[diff] [blame]2507 b43_ntab_write(dev, B43_NTAB16(8, 2), tmp);
Rafał Miłeckic643a662010-01-18 00:21:27 +0100[diff] [blame]2508 tmp = b43_ntab_read(dev, B43_NTAB16(8, 18));
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2509 regs[4] = tmp;
2510 tmp |= 0x2000;
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100[diff] [blame]2511 b43_ntab_write(dev, B43_NTAB16(8, 18), tmp);
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2512 regs[5] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC1);
2513 regs[6] = b43_phy_read(dev, B43_NPHY_RFCTL_INTC2);
2514 if (b43_current_band(dev->wl) == IEEE80211_BAND_5GHZ)
2515 tmp = 0x0180;
2516 else
2517 tmp = 0x0120;
2518 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, tmp);
2519 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, tmp);
2520 }
2521}
2522
Rafał Miłeckibbc6dc12010-02-04 12:23:11 +0100[diff] [blame]2523/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SaveCal */
2524static void b43_nphy_save_cal(struct b43_wldev *dev)
2525{
2526 struct b43_phy_n *nphy = dev->phy.n;
2527
2528 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2529 u16 *txcal_radio_regs = NULL;
Rafał Miłecki902db912010-02-27 13:03:37 +0100[diff] [blame]2530 struct b43_chanspec *iqcal_chanspec;
Rafał Miłeckibbc6dc12010-02-04 12:23:11 +0100[diff] [blame]2531 u16 *table = NULL;
2532
2533 if (nphy->hang_avoid)
2534 b43_nphy_stay_in_carrier_search(dev, 1);
2535
2536 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2537 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2538 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2539 iqcal_chanspec = &nphy->iqcal_chanspec_2G;
2540 table = nphy->cal_cache.txcal_coeffs_2G;
2541 } else {
2542 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2543 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2544 iqcal_chanspec = &nphy->iqcal_chanspec_5G;
2545 table = nphy->cal_cache.txcal_coeffs_5G;
2546 }
2547
2548 b43_nphy_rx_iq_coeffs(dev, false, rxcal_coeffs);
2549 /* TODO use some definitions */
2550 if (dev->phy.rev >= 3) {
2551 txcal_radio_regs[0] = b43_radio_read(dev, 0x2021);
2552 txcal_radio_regs[1] = b43_radio_read(dev, 0x2022);
2553 txcal_radio_regs[2] = b43_radio_read(dev, 0x3021);
2554 txcal_radio_regs[3] = b43_radio_read(dev, 0x3022);
2555 txcal_radio_regs[4] = b43_radio_read(dev, 0x2023);
2556 txcal_radio_regs[5] = b43_radio_read(dev, 0x2024);
2557 txcal_radio_regs[6] = b43_radio_read(dev, 0x3023);
2558 txcal_radio_regs[7] = b43_radio_read(dev, 0x3024);
2559 } else {
2560 txcal_radio_regs[0] = b43_radio_read(dev, 0x8B);
2561 txcal_radio_regs[1] = b43_radio_read(dev, 0xBA);
2562 txcal_radio_regs[2] = b43_radio_read(dev, 0x8D);
2563 txcal_radio_regs[3] = b43_radio_read(dev, 0xBC);
2564 }
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]2565 iqcal_chanspec->center_freq = dev->phy.channel_freq;
2566 iqcal_chanspec->channel_type = dev->phy.channel_type;
Rafał Miłecki5818e982010-10-14 19:33:35 +0200[diff] [blame]2567 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 8, table);
Rafał Miłeckibbc6dc12010-02-04 12:23:11 +0100[diff] [blame]2568
2569 if (nphy->hang_avoid)
2570 b43_nphy_stay_in_carrier_search(dev, 0);
2571}
2572
Rafał Miłecki2f258b72010-01-15 15:18:35 +0100[diff] [blame]2573/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RestoreCal */
2574static void b43_nphy_restore_cal(struct b43_wldev *dev)
2575{
2576 struct b43_phy_n *nphy = dev->phy.n;
2577
2578 u16 coef[4];
2579 u16 *loft = NULL;
2580 u16 *table = NULL;
2581
2582 int i;
2583 u16 *txcal_radio_regs = NULL;
2584 struct b43_phy_n_iq_comp *rxcal_coeffs = NULL;
2585
2586 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]2587 if (!nphy->iqcal_chanspec_2G.center_freq)
Rafał Miłecki2f258b72010-01-15 15:18:35 +0100[diff] [blame]2588 return;
2589 table = nphy->cal_cache.txcal_coeffs_2G;
2590 loft = &nphy->cal_cache.txcal_coeffs_2G[5];
2591 } else {
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]2592 if (!nphy->iqcal_chanspec_5G.center_freq)
Rafał Miłecki2f258b72010-01-15 15:18:35 +0100[diff] [blame]2593 return;
2594 table = nphy->cal_cache.txcal_coeffs_5G;
2595 loft = &nphy->cal_cache.txcal_coeffs_5G[5];
2596 }
2597
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]2598 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4, table);
Rafał Miłecki2f258b72010-01-15 15:18:35 +0100[diff] [blame]2599
2600 for (i = 0; i < 4; i++) {
2601 if (dev->phy.rev >= 3)
2602 table[i] = coef[i];
2603 else
2604 coef[i] = 0;
2605 }
2606
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]2607 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4, coef);
2608 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2, loft);
2609 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2, loft);
Rafał Miłecki2f258b72010-01-15 15:18:35 +0100[diff] [blame]2610
2611 if (dev->phy.rev < 2)
2612 b43_nphy_tx_iq_workaround(dev);
2613
2614 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
2615 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_2G;
2616 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_2G;
2617 } else {
2618 txcal_radio_regs = nphy->cal_cache.txcal_radio_regs_5G;
2619 rxcal_coeffs = &nphy->cal_cache.rxcal_coeffs_5G;
2620 }
2621
2622 /* TODO use some definitions */
2623 if (dev->phy.rev >= 3) {
2624 b43_radio_write(dev, 0x2021, txcal_radio_regs[0]);
2625 b43_radio_write(dev, 0x2022, txcal_radio_regs[1]);
2626 b43_radio_write(dev, 0x3021, txcal_radio_regs[2]);
2627 b43_radio_write(dev, 0x3022, txcal_radio_regs[3]);
2628 b43_radio_write(dev, 0x2023, txcal_radio_regs[4]);
2629 b43_radio_write(dev, 0x2024, txcal_radio_regs[5]);
2630 b43_radio_write(dev, 0x3023, txcal_radio_regs[6]);
2631 b43_radio_write(dev, 0x3024, txcal_radio_regs[7]);
2632 } else {
2633 b43_radio_write(dev, 0x8B, txcal_radio_regs[0]);
2634 b43_radio_write(dev, 0xBA, txcal_radio_regs[1]);
2635 b43_radio_write(dev, 0x8D, txcal_radio_regs[2]);
2636 b43_radio_write(dev, 0xBC, txcal_radio_regs[3]);
2637 }
2638 b43_nphy_rx_iq_coeffs(dev, true, rxcal_coeffs);
2639}
2640
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2641/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalTxIqlo */
2642static int b43_nphy_cal_tx_iq_lo(struct b43_wldev *dev,
2643 struct nphy_txgains target,
2644 bool full, bool mphase)
2645{
2646 struct b43_phy_n *nphy = dev->phy.n;
2647 int i;
2648 int error = 0;
2649 int freq;
2650 bool avoid = false;
2651 u8 length;
2652 u16 tmp, core, type, count, max, numb, last, cmd;
2653 const u16 *table;
2654 bool phy6or5x;
2655
2656 u16 buffer[11];
2657 u16 diq_start = 0;
2658 u16 save[2];
2659 u16 gain[2];
2660 struct nphy_iqcal_params params[2];
2661 bool updated[2] = { };
2662
2663 b43_nphy_stay_in_carrier_search(dev, true);
2664
2665 if (dev->phy.rev >= 4) {
2666 avoid = nphy->hang_avoid;
2667 nphy->hang_avoid = 0;
2668 }
2669
Rafał Miłecki91458342010-01-18 00:21:35 +0100[diff] [blame]2670 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2671
2672 for (i = 0; i < 2; i++) {
2673 b43_nphy_iq_cal_gain_params(dev, i, target, &params[i]);
2674 gain[i] = params[i].cal_gain;
2675 }
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]2676
2677 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2678
2679 b43_nphy_tx_cal_radio_setup(dev);
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2680 b43_nphy_tx_cal_phy_setup(dev);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2681
2682 phy6or5x = dev->phy.rev >= 6 ||
2683 (dev->phy.rev == 5 && nphy->ipa2g_on &&
2684 b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ);
2685 if (phy6or5x) {
Rafał Miłecki38bb9022010-01-30 20:18:05 +0100[diff] [blame]2686 if (dev->phy.is_40mhz) {
2687 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2688 tbl_tx_iqlo_cal_loft_ladder_40);
2689 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2690 tbl_tx_iqlo_cal_iqimb_ladder_40);
2691 } else {
2692 b43_ntab_write_bulk(dev, B43_NTAB16(15, 0), 18,
2693 tbl_tx_iqlo_cal_loft_ladder_20);
2694 b43_ntab_write_bulk(dev, B43_NTAB16(15, 32), 18,
2695 tbl_tx_iqlo_cal_iqimb_ladder_20);
2696 }
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2697 }
2698
2699 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0x8AA9);
2700
Rafał Miłeckiaa4c7b22010-01-22 01:53:12 +0100[diff] [blame]2701 if (!dev->phy.is_40mhz)
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2702 freq = 2500;
2703 else
2704 freq = 5000;
2705
2706 if (nphy->mphase_cal_phase_id > 2)
Rafał Miłecki10a79872010-01-22 01:53:14 +0100[diff] [blame]2707 b43_nphy_run_samples(dev, (dev->phy.is_40mhz ? 40 : 20) * 8,
2708 0xFFFF, 0, true, false);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2709 else
Rafał Miłecki59af0992010-01-22 01:53:16 +0100[diff] [blame]2710 error = b43_nphy_tx_tone(dev, freq, 250, true, false);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2711
2712 if (error == 0) {
2713 if (nphy->mphase_cal_phase_id > 2) {
2714 table = nphy->mphase_txcal_bestcoeffs;
2715 length = 11;
2716 if (dev->phy.rev < 3)
2717 length -= 2;
2718 } else {
2719 if (!full && nphy->txiqlocal_coeffsvalid) {
2720 table = nphy->txiqlocal_bestc;
2721 length = 11;
2722 if (dev->phy.rev < 3)
2723 length -= 2;
2724 } else {
2725 full = true;
2726 if (dev->phy.rev >= 3) {
2727 table = tbl_tx_iqlo_cal_startcoefs_nphyrev3;
2728 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS_REV3;
2729 } else {
2730 table = tbl_tx_iqlo_cal_startcoefs;
2731 length = B43_NTAB_TX_IQLO_CAL_STARTCOEFS;
2732 }
2733 }
2734 }
2735
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]2736 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length, table);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2737
2738 if (full) {
2739 if (dev->phy.rev >= 3)
2740 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL_REV3;
2741 else
2742 max = B43_NTAB_TX_IQLO_CAL_CMDS_FULLCAL;
2743 } else {
2744 if (dev->phy.rev >= 3)
2745 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL_REV3;
2746 else
2747 max = B43_NTAB_TX_IQLO_CAL_CMDS_RECAL;
2748 }
2749
2750 if (mphase) {
2751 count = nphy->mphase_txcal_cmdidx;
2752 numb = min(max,
2753 (u16)(count + nphy->mphase_txcal_numcmds));
2754 } else {
2755 count = 0;
2756 numb = max;
2757 }
2758
2759 for (; count < numb; count++) {
2760 if (full) {
2761 if (dev->phy.rev >= 3)
2762 cmd = tbl_tx_iqlo_cal_cmds_fullcal_nphyrev3[count];
2763 else
2764 cmd = tbl_tx_iqlo_cal_cmds_fullcal[count];
2765 } else {
2766 if (dev->phy.rev >= 3)
2767 cmd = tbl_tx_iqlo_cal_cmds_recal_nphyrev3[count];
2768 else
2769 cmd = tbl_tx_iqlo_cal_cmds_recal[count];
2770 }
2771
2772 core = (cmd & 0x3000) >> 12;
2773 type = (cmd & 0x0F00) >> 8;
2774
2775 if (phy6or5x && updated[core] == 0) {
2776 b43_nphy_update_tx_cal_ladder(dev, core);
2777 updated[core] = 1;
2778 }
2779
2780 tmp = (params[core].ncorr[type] << 8) | 0x66;
2781 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDNNUM, tmp);
2782
2783 if (type == 1 || type == 3 || type == 4) {
Rafał Miłeckic643a662010-01-18 00:21:27 +0100[diff] [blame]2784 buffer[0] = b43_ntab_read(dev,
2785 B43_NTAB16(15, 69 + core));
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2786 diq_start = buffer[0];
2787 buffer[0] = 0;
Rafał Miłeckid41a3552010-01-18 00:21:17 +0100[diff] [blame]2788 b43_ntab_write(dev, B43_NTAB16(15, 69 + core),
2789 0);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2790 }
2791
2792 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMD, cmd);
2793 for (i = 0; i < 2000; i++) {
2794 tmp = b43_phy_read(dev, B43_NPHY_IQLOCAL_CMD);
2795 if (tmp & 0xC000)
2796 break;
2797 udelay(10);
2798 }
2799
Rafał Miłecki91458342010-01-18 00:21:35 +0100[diff] [blame]2800 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2801 buffer);
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]2802 b43_ntab_write_bulk(dev, B43_NTAB16(15, 64), length,
2803 buffer);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2804
2805 if (type == 1 || type == 3 || type == 4)
2806 buffer[0] = diq_start;
2807 }
2808
2809 if (mphase)
2810 nphy->mphase_txcal_cmdidx = (numb >= max) ? 0 : numb;
2811
2812 last = (dev->phy.rev < 3) ? 6 : 7;
2813
2814 if (!mphase || nphy->mphase_cal_phase_id == last) {
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]2815 b43_ntab_write_bulk(dev, B43_NTAB16(15, 96), 4, buffer);
Rafał Miłecki91458342010-01-18 00:21:35 +0100[diff] [blame]2816 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 4, buffer);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2817 if (dev->phy.rev < 3) {
2818 buffer[0] = 0;
2819 buffer[1] = 0;
2820 buffer[2] = 0;
2821 buffer[3] = 0;
2822 }
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]2823 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2824 buffer);
Rafał Miłeckibc53e512010-04-01 23:11:10 +0200[diff] [blame]2825 b43_ntab_read_bulk(dev, B43_NTAB16(15, 101), 2,
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]2826 buffer);
2827 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2828 buffer);
2829 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2830 buffer);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2831 length = 11;
2832 if (dev->phy.rev < 3)
2833 length -= 2;
Rafał Miłecki91458342010-01-18 00:21:35 +0100[diff] [blame]2834 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2835 nphy->txiqlocal_bestc);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2836 nphy->txiqlocal_coeffsvalid = true;
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]2837 nphy->txiqlocal_chanspec.center_freq =
2838 dev->phy.channel_freq;
2839 nphy->txiqlocal_chanspec.channel_type =
2840 dev->phy.channel_type;
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2841 } else {
2842 length = 11;
2843 if (dev->phy.rev < 3)
2844 length -= 2;
Rafał Miłecki91458342010-01-18 00:21:35 +0100[diff] [blame]2845 b43_ntab_read_bulk(dev, B43_NTAB16(15, 96), length,
2846 nphy->mphase_txcal_bestcoeffs);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2847 }
2848
Rafał Miłecki53ae8e82010-01-17 13:03:48 +0100[diff] [blame]2849 b43_nphy_stop_playback(dev);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2850 b43_phy_write(dev, B43_NPHY_IQLOCAL_CMDGCTL, 0);
2851 }
2852
Rafał Miłeckie53de672010-01-17 13:03:32 +0100[diff] [blame]2853 b43_nphy_tx_cal_phy_cleanup(dev);
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]2854 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, save);
Rafał Miłeckifb43b8e2010-01-15 16:10:48 +0100[diff] [blame]2855
2856 if (dev->phy.rev < 2 && (!mphase || nphy->mphase_cal_phase_id == last))
2857 b43_nphy_tx_iq_workaround(dev);
2858
2859 if (dev->phy.rev >= 4)
2860 nphy->hang_avoid = avoid;
2861
2862 b43_nphy_stay_in_carrier_search(dev, false);
2863
2864 return error;
2865}
2866
Rafał Miłecki984ff4f2010-02-04 12:23:10 +0100[diff] [blame]2867/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ReapplyTxCalCoeffs */
2868static void b43_nphy_reapply_tx_cal_coeffs(struct b43_wldev *dev)
2869{
2870 struct b43_phy_n *nphy = dev->phy.n;
2871 u8 i;
2872 u16 buffer[7];
2873 bool equal = true;
2874
Rafał Miłecki902db912010-02-27 13:03:37 +0100[diff] [blame]2875 if (!nphy->txiqlocal_coeffsvalid ||
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]2876 nphy->txiqlocal_chanspec.center_freq != dev->phy.channel_freq ||
2877 nphy->txiqlocal_chanspec.channel_type != dev->phy.channel_type)
Rafał Miłecki984ff4f2010-02-04 12:23:10 +0100[diff] [blame]2878 return;
2879
2880 b43_ntab_read_bulk(dev, B43_NTAB16(15, 80), 7, buffer);
2881 for (i = 0; i < 4; i++) {
2882 if (buffer[i] != nphy->txiqlocal_bestc[i]) {
2883 equal = false;
2884 break;
2885 }
2886 }
2887
2888 if (!equal) {
2889 b43_ntab_write_bulk(dev, B43_NTAB16(15, 80), 4,
2890 nphy->txiqlocal_bestc);
2891 for (i = 0; i < 4; i++)
2892 buffer[i] = 0;
2893 b43_ntab_write_bulk(dev, B43_NTAB16(15, 88), 4,
2894 buffer);
2895 b43_ntab_write_bulk(dev, B43_NTAB16(15, 85), 2,
2896 &nphy->txiqlocal_bestc[5]);
2897 b43_ntab_write_bulk(dev, B43_NTAB16(15, 93), 2,
2898 &nphy->txiqlocal_bestc[5]);
2899 }
2900}
2901
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]2902/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIqRev2 */
2903static int b43_nphy_rev2_cal_rx_iq(struct b43_wldev *dev,
2904 struct nphy_txgains target, u8 type, bool debug)
2905{
2906 struct b43_phy_n *nphy = dev->phy.n;
2907 int i, j, index;
2908 u8 rfctl[2];
2909 u8 afectl_core;
2910 u16 tmp[6];
2911 u16 cur_hpf1, cur_hpf2, cur_lna;
2912 u32 real, imag;
2913 enum ieee80211_band band;
2914
2915 u8 use;
2916 u16 cur_hpf;
2917 u16 lna[3] = { 3, 3, 1 };
2918 u16 hpf1[3] = { 7, 2, 0 };
2919 u16 hpf2[3] = { 2, 0, 0 };
Rafał Miłeckide9a47f2010-01-18 00:21:49 +0100[diff] [blame]2920 u32 power[3] = { };
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]2921 u16 gain_save[2];
2922 u16 cal_gain[2];
2923 struct nphy_iqcal_params cal_params[2];
2924 struct nphy_iq_est est;
2925 int ret = 0;
2926 bool playtone = true;
2927 int desired = 13;
2928
2929 b43_nphy_stay_in_carrier_search(dev, 1);
2930
2931 if (dev->phy.rev < 2)
Rafał Miłecki984ff4f2010-02-04 12:23:10 +0100[diff] [blame]2932 b43_nphy_reapply_tx_cal_coeffs(dev);
Rafał Miłecki91458342010-01-18 00:21:35 +0100[diff] [blame]2933 b43_ntab_read_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]2934 for (i = 0; i < 2; i++) {
2935 b43_nphy_iq_cal_gain_params(dev, i, target, &cal_params[i]);
2936 cal_gain[i] = cal_params[i].cal_gain;
2937 }
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]2938 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, cal_gain);
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]2939
2940 for (i = 0; i < 2; i++) {
2941 if (i == 0) {
2942 rfctl[0] = B43_NPHY_RFCTL_INTC1;
2943 rfctl[1] = B43_NPHY_RFCTL_INTC2;
2944 afectl_core = B43_NPHY_AFECTL_C1;
2945 } else {
2946 rfctl[0] = B43_NPHY_RFCTL_INTC2;
2947 rfctl[1] = B43_NPHY_RFCTL_INTC1;
2948 afectl_core = B43_NPHY_AFECTL_C2;
2949 }
2950
2951 tmp[1] = b43_phy_read(dev, B43_NPHY_RFSEQCA);
2952 tmp[2] = b43_phy_read(dev, afectl_core);
2953 tmp[3] = b43_phy_read(dev, B43_NPHY_AFECTL_OVER);
2954 tmp[4] = b43_phy_read(dev, rfctl[0]);
2955 tmp[5] = b43_phy_read(dev, rfctl[1]);
2956
2957 b43_phy_maskset(dev, B43_NPHY_RFSEQCA,
Larry Fingeracd82aa2010-07-21 11:48:05 -0500[diff] [blame]2958 ~B43_NPHY_RFSEQCA_RXDIS & 0xFFFF,
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]2959 ((1 - i) << B43_NPHY_RFSEQCA_RXDIS_SHIFT));
2960 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_TXEN,
2961 (1 - i));
2962 b43_phy_set(dev, afectl_core, 0x0006);
2963 b43_phy_set(dev, B43_NPHY_AFECTL_OVER, 0x0006);
2964
2965 band = b43_current_band(dev->wl);
2966
2967 if (nphy->rxcalparams & 0xFF000000) {
2968 if (band == IEEE80211_BAND_5GHZ)
2969 b43_phy_write(dev, rfctl[0], 0x140);
2970 else
2971 b43_phy_write(dev, rfctl[0], 0x110);
2972 } else {
2973 if (band == IEEE80211_BAND_5GHZ)
2974 b43_phy_write(dev, rfctl[0], 0x180);
2975 else
2976 b43_phy_write(dev, rfctl[0], 0x120);
2977 }
2978
2979 if (band == IEEE80211_BAND_5GHZ)
2980 b43_phy_write(dev, rfctl[1], 0x148);
2981 else
2982 b43_phy_write(dev, rfctl[1], 0x114);
2983
2984 if (nphy->rxcalparams & 0x10000) {
2985 b43_radio_maskset(dev, B2055_C1_GENSPARE2, 0xFC,
2986 (i + 1));
2987 b43_radio_maskset(dev, B2055_C2_GENSPARE2, 0xFC,
2988 (2 - i));
2989 }
2990
Rafał Miłecki30115c22010-10-22 17:43:45 +0200[diff] [blame]2991 for (j = 0; j < 4; j++) {
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]2992 if (j < 3) {
2993 cur_lna = lna[j];
2994 cur_hpf1 = hpf1[j];
2995 cur_hpf2 = hpf2[j];
2996 } else {
2997 if (power[1] > 10000) {
2998 use = 1;
2999 cur_hpf = cur_hpf1;
3000 index = 2;
3001 } else {
3002 if (power[0] > 10000) {
3003 use = 1;
3004 cur_hpf = cur_hpf1;
3005 index = 1;
3006 } else {
3007 index = 0;
3008 use = 2;
3009 cur_hpf = cur_hpf2;
3010 }
3011 }
3012 cur_lna = lna[index];
3013 cur_hpf1 = hpf1[index];
3014 cur_hpf2 = hpf2[index];
3015 cur_hpf += desired - hweight32(power[index]);
3016 cur_hpf = clamp_val(cur_hpf, 0, 10);
3017 if (use == 1)
3018 cur_hpf1 = cur_hpf;
3019 else
3020 cur_hpf2 = cur_hpf;
3021 }
3022
3023 tmp[0] = ((cur_hpf2 << 8) | (cur_hpf1 << 4) |
3024 (cur_lna << 2));
Rafał Miłecki75377b22010-01-22 01:53:13 +0100[diff] [blame]3025 b43_nphy_rf_control_override(dev, 0x400, tmp[0], 3,
3026 false);
Rafał Miłeckide9a47f2010-01-18 00:21:49 +0100[diff] [blame]3027 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Rafał Miłecki53ae8e82010-01-17 13:03:48 +0100[diff] [blame]3028 b43_nphy_stop_playback(dev);
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]3029
3030 if (playtone) {
Rafał Miłecki59af0992010-01-22 01:53:16 +0100[diff] [blame]3031 ret = b43_nphy_tx_tone(dev, 4000,
3032 (nphy->rxcalparams & 0xFFFF),
3033 false, false);
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]3034 playtone = false;
3035 } else {
Rafał Miłecki10a79872010-01-22 01:53:14 +0100[diff] [blame]3036 b43_nphy_run_samples(dev, 160, 0xFFFF, 0,
3037 false, false);
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]3038 }
3039
3040 if (ret == 0) {
3041 if (j < 3) {
3042 b43_nphy_rx_iq_est(dev, &est, 1024, 32,
3043 false);
3044 if (i == 0) {
3045 real = est.i0_pwr;
3046 imag = est.q0_pwr;
3047 } else {
3048 real = est.i1_pwr;
3049 imag = est.q1_pwr;
3050 }
3051 power[i] = ((real + imag) / 1024) + 1;
3052 } else {
3053 b43_nphy_calc_rx_iq_comp(dev, 1 << i);
3054 }
Rafał Miłecki53ae8e82010-01-17 13:03:48 +0100[diff] [blame]3055 b43_nphy_stop_playback(dev);
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]3056 }
3057
3058 if (ret != 0)
3059 break;
3060 }
3061
3062 b43_radio_mask(dev, B2055_C1_GENSPARE2, 0xFC);
3063 b43_radio_mask(dev, B2055_C2_GENSPARE2, 0xFC);
3064 b43_phy_write(dev, rfctl[1], tmp[5]);
3065 b43_phy_write(dev, rfctl[0], tmp[4]);
3066 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, tmp[3]);
3067 b43_phy_write(dev, afectl_core, tmp[2]);
3068 b43_phy_write(dev, B43_NPHY_RFSEQCA, tmp[1]);
3069
3070 if (ret != 0)
3071 break;
3072 }
3073
Rafał Miłecki75377b22010-01-22 01:53:13 +0100[diff] [blame]3074 b43_nphy_rf_control_override(dev, 0x400, 0, 3, true);
Rafał Miłecki67c0d6e2010-01-17 13:04:02 +0100[diff] [blame]3075 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]3076 b43_ntab_write_bulk(dev, B43_NTAB16(7, 0x110), 2, gain_save);
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]3077
3078 b43_nphy_stay_in_carrier_search(dev, 0);
3079
3080 return ret;
3081}
3082
3083static int b43_nphy_rev3_cal_rx_iq(struct b43_wldev *dev,
3084 struct nphy_txgains target, u8 type, bool debug)
3085{
3086 return -1;
3087}
3088
3089/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/CalRxIq */
3090static int b43_nphy_cal_rx_iq(struct b43_wldev *dev,
3091 struct nphy_txgains target, u8 type, bool debug)
3092{
3093 if (dev->phy.rev >= 3)
3094 return b43_nphy_rev3_cal_rx_iq(dev, target, type, debug);
3095 else
3096 return b43_nphy_rev2_cal_rx_iq(dev, target, type, debug);
3097}
3098
Gábor Stefanikd2730b22010-08-16 22:39:16 +0200[diff] [blame]3099/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/MacPhyClkSet */
3100static void b43_nphy_mac_phy_clock_set(struct b43_wldev *dev, bool on)
3101{
3102 u32 tmslow = ssb_read32(dev->dev, SSB_TMSLOW);
3103 if (on)
3104 tmslow |= SSB_TMSLOW_PHYCLK;
3105 else
3106 tmslow &= ~SSB_TMSLOW_PHYCLK;
3107 ssb_write32(dev->dev, SSB_TMSLOW, tmslow);
3108}
3109
Gábor Stefanik4e687b22010-08-16 22:39:17 +0200[diff] [blame]3110/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/RxCoreSetState */
3111static void b43_nphy_set_rx_core_state(struct b43_wldev *dev, u8 mask)
3112{
3113 struct b43_phy *phy = &dev->phy;
3114 struct b43_phy_n *nphy = phy->n;
Rafał Miłecki0b81c232010-11-18 21:11:43 +0100[diff] [blame^]3115 /* u16 buf[16]; it's rev3+ */
Gábor Stefanik4e687b22010-08-16 22:39:17 +0200[diff] [blame]3116
Rafał Miłecki049fbfe2010-08-22 21:47:32 +0200[diff] [blame]3117 nphy->phyrxchain = mask;
3118
Gábor Stefanik4e687b22010-08-16 22:39:17 +0200[diff] [blame]3119 if (0 /* FIXME clk */)
3120 return;
3121
3122 b43_mac_suspend(dev);
3123
3124 if (nphy->hang_avoid)
3125 b43_nphy_stay_in_carrier_search(dev, true);
3126
3127 b43_phy_maskset(dev, B43_NPHY_RFSEQCA, ~B43_NPHY_RFSEQCA_RXEN,
3128 (mask & 0x3) << B43_NPHY_RFSEQCA_RXEN_SHIFT);
3129
Rafał Miłecki049fbfe2010-08-22 21:47:32 +0200[diff] [blame]3130 if ((mask & 0x3) != 0x3) {
Gábor Stefanik4e687b22010-08-16 22:39:17 +0200[diff] [blame]3131 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 1);
3132 if (dev->phy.rev >= 3) {
3133 /* TODO */
3134 }
3135 } else {
3136 b43_phy_write(dev, B43_NPHY_HPANT_SWTHRES, 0x1E);
3137 if (dev->phy.rev >= 3) {
3138 /* TODO */
3139 }
3140 }
3141
3142 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
3143
3144 if (nphy->hang_avoid)
3145 b43_nphy_stay_in_carrier_search(dev, false);
3146
3147 b43_mac_enable(dev);
3148}
3149
Rafał Miłecki42e15472010-01-15 15:06:47 +0100[diff] [blame]3150/*
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3151 * Init N-PHY
3152 * http://bcm-v4.sipsolutions.net/802.11/PHY/Init/N
3153 */
Michael Buesch424047e2008-01-09 16:13:56 +0100[diff] [blame]3154int b43_phy_initn(struct b43_wldev *dev)
3155{
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3156 struct ssb_bus *bus = dev->dev->bus;
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3157 struct b43_phy *phy = &dev->phy;
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3158 struct b43_phy_n *nphy = phy->n;
3159 u8 tx_pwr_state;
3160 struct nphy_txgains target;
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3161 u16 tmp;
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3162 enum ieee80211_band tmp2;
3163 bool do_rssi_cal;
Michael Buesch424047e2008-01-09 16:13:56 +0100[diff] [blame]3164
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3165 u16 clip[2];
3166 bool do_cal = false;
3167
3168 if ((dev->phy.rev >= 3) &&
3169 (bus->sprom.boardflags_lo & B43_BFL_EXTLNA) &&
3170 (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)) {
3171 chipco_set32(&dev->dev->bus->chipco, SSB_CHIPCO_CHIPCTL, 0x40);
3172 }
3173 nphy->deaf_count = 0;
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3174 b43_nphy_tables_init(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3175 nphy->crsminpwr_adjusted = false;
3176 nphy->noisevars_adjusted = false;
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3177
3178 /* Clear all overrides */
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3179 if (dev->phy.rev >= 3) {
3180 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S1, 0);
3181 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3182 b43_phy_write(dev, B43_NPHY_TXF_40CO_B1S0, 0);
3183 b43_phy_write(dev, B43_NPHY_TXF_40CO_B32S1, 0);
3184 } else {
3185 b43_phy_write(dev, B43_NPHY_RFCTL_OVER, 0);
3186 }
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3187 b43_phy_write(dev, B43_NPHY_RFCTL_INTC1, 0);
3188 b43_phy_write(dev, B43_NPHY_RFCTL_INTC2, 0);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3189 if (dev->phy.rev < 6) {
3190 b43_phy_write(dev, B43_NPHY_RFCTL_INTC3, 0);
3191 b43_phy_write(dev, B43_NPHY_RFCTL_INTC4, 0);
3192 }
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3193 b43_phy_mask(dev, B43_NPHY_RFSEQMODE,
3194 ~(B43_NPHY_RFSEQMODE_CAOVER |
3195 B43_NPHY_RFSEQMODE_TROVER));
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3196 if (dev->phy.rev >= 3)
3197 b43_phy_write(dev, B43_NPHY_AFECTL_OVER1, 0);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3198 b43_phy_write(dev, B43_NPHY_AFECTL_OVER, 0);
3199
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3200 if (dev->phy.rev <= 2) {
3201 tmp = (dev->phy.rev == 2) ? 0x3B : 0x40;
3202 b43_phy_maskset(dev, B43_NPHY_BPHY_CTL3,
3203 ~B43_NPHY_BPHY_CTL3_SCALE,
3204 tmp << B43_NPHY_BPHY_CTL3_SCALE_SHIFT);
3205 }
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3206 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_20M, 0x20);
3207 b43_phy_write(dev, B43_NPHY_AFESEQ_TX2RX_PUD_40M, 0x20);
3208
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3209 if (bus->sprom.boardflags2_lo & 0x100 ||
3210 (bus->boardinfo.vendor == PCI_VENDOR_ID_APPLE &&
3211 bus->boardinfo.type == 0x8B))
3212 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xA0);
3213 else
3214 b43_phy_write(dev, B43_NPHY_TXREALFD, 0xB8);
3215 b43_phy_write(dev, B43_NPHY_MIMO_CRSTXEXT, 0xC8);
3216 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x50);
3217 b43_phy_write(dev, B43_NPHY_TXRIFS_FRDEL, 0x30);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3218
Rafał Miłeckiad9716e2010-01-17 13:03:40 +0100[diff] [blame]3219 b43_nphy_update_mimo_config(dev, nphy->preamble_override);
Rafał Miłecki4f4ab6c2010-01-17 13:03:55 +0100[diff] [blame]3220 b43_nphy_update_txrx_chain(dev);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3221
3222 if (phy->rev < 2) {
3223 b43_phy_write(dev, B43_NPHY_DUP40_GFBL, 0xAA8);
3224 b43_phy_write(dev, B43_NPHY_DUP40_BL, 0x9A4);
3225 }
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3226
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3227 tmp2 = b43_current_band(dev->wl);
3228 if ((nphy->ipa2g_on && tmp2 == IEEE80211_BAND_2GHZ) ||
3229 (nphy->ipa5g_on && tmp2 == IEEE80211_BAND_5GHZ)) {
3230 b43_phy_set(dev, B43_NPHY_PAPD_EN0, 0x1);
3231 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ0, 0x007F,
3232 nphy->papd_epsilon_offset[0] << 7);
3233 b43_phy_set(dev, B43_NPHY_PAPD_EN1, 0x1);
3234 b43_phy_maskset(dev, B43_NPHY_EPS_TABLE_ADJ1, 0x007F,
3235 nphy->papd_epsilon_offset[1] << 7);
Rafał Miłecki45ca6972010-01-22 01:53:15 +0100[diff] [blame]3236 b43_nphy_int_pa_set_tx_dig_filters(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3237 } else if (phy->rev >= 5) {
Rafał Miłecki45ca6972010-01-22 01:53:15 +0100[diff] [blame]3238 b43_nphy_ext_pa_set_tx_dig_filters(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3239 }
3240
3241 b43_nphy_workarounds(dev);
3242
3243 /* Reset CCA, in init code it differs a little from standard way */
Rafał Miłecki730dd702010-01-15 16:38:07 +0100[diff] [blame]3244 b43_nphy_bmac_clock_fgc(dev, 1);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3245 tmp = b43_phy_read(dev, B43_NPHY_BBCFG);
3246 b43_phy_write(dev, B43_NPHY_BBCFG, tmp | B43_NPHY_BBCFG_RSTCCA);
3247 b43_phy_write(dev, B43_NPHY_BBCFG, tmp & ~B43_NPHY_BBCFG_RSTCCA);
Rafał Miłecki730dd702010-01-15 16:38:07 +0100[diff] [blame]3248 b43_nphy_bmac_clock_fgc(dev, 0);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3249
Gábor Stefanikd2730b22010-08-16 22:39:16 +0200[diff] [blame]3250 b43_nphy_mac_phy_clock_set(dev, true);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3251
Rafał Miłeckie50cbcf2010-01-15 15:02:38 +0100[diff] [blame]3252 b43_nphy_pa_override(dev, false);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3253 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RX2TX);
3254 b43_nphy_force_rf_sequence(dev, B43_RFSEQ_RESET2RX);
Rafał Miłeckie50cbcf2010-01-15 15:02:38 +0100[diff] [blame]3255 b43_nphy_pa_override(dev, true);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3256
Rafał Miłeckibbec3982010-01-15 14:31:39 +0100[diff] [blame]3257 b43_nphy_classifier(dev, 0, 0);
3258 b43_nphy_read_clip_detection(dev, clip);
Rafał Miłeckibec18642010-11-18 13:28:00 +0100[diff] [blame]3259 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3260 b43_nphy_bphy_init(dev);
3261
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3262 tx_pwr_state = nphy->txpwrctrl;
3263 /* TODO N PHY TX power control with argument 0
3264 (turning off power control) */
3265 /* TODO Fix the TX Power Settings */
3266 /* TODO N PHY TX Power Control Idle TSSI */
3267 /* TODO N PHY TX Power Control Setup */
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3268
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3269 if (phy->rev >= 3) {
3270 /* TODO */
3271 } else {
Rafał Miłecki2581b142010-01-18 00:21:21 +0100[diff] [blame]3272 b43_ntab_write_bulk(dev, B43_NTAB32(26, 192), 128,
3273 b43_ntab_tx_gain_rev0_1_2);
3274 b43_ntab_write_bulk(dev, B43_NTAB32(27, 192), 128,
3275 b43_ntab_tx_gain_rev0_1_2);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3276 }
3277
3278 if (nphy->phyrxchain != 3)
Gábor Stefanik4e687b22010-08-16 22:39:17 +0200[diff] [blame]3279 b43_nphy_set_rx_core_state(dev, nphy->phyrxchain);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3280 if (nphy->mphase_cal_phase_id > 0)
3281 ;/* TODO PHY Periodic Calibration Multi-Phase Restart */
3282
3283 do_rssi_cal = false;
3284 if (phy->rev >= 3) {
3285 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]3286 do_rssi_cal = !nphy->rssical_chanspec_2G.center_freq;
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3287 else
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]3288 do_rssi_cal = !nphy->rssical_chanspec_5G.center_freq;
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3289
3290 if (do_rssi_cal)
Rafał Miłecki4cb99772010-01-15 13:40:58 +0100[diff] [blame]3291 b43_nphy_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3292 else
Rafał Miłecki42e15472010-01-15 15:06:47 +0100[diff] [blame]3293 b43_nphy_restore_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3294 } else {
Rafał Miłecki4cb99772010-01-15 13:40:58 +0100[diff] [blame]3295 b43_nphy_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3296 }
3297
3298 if (!((nphy->measure_hold & 0x6) != 0)) {
3299 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]3300 do_cal = !nphy->iqcal_chanspec_2G.center_freq;
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3301 else
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]3302 do_cal = !nphy->iqcal_chanspec_5G.center_freq;
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3303
3304 if (nphy->mute)
3305 do_cal = false;
3306
3307 if (do_cal) {
Rafał Miłeckib0022e12010-01-15 15:40:50 +0100[diff] [blame]3308 target = b43_nphy_get_tx_gains(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3309
3310 if (nphy->antsel_type == 2)
Rafał Miłecki8987a9e2010-02-27 13:03:33 +0100[diff] [blame]3311 b43_nphy_superswitch_init(dev, true);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3312 if (nphy->perical != 2) {
Rafał Miłecki90b97382010-01-15 14:48:21 +0100[diff] [blame]3313 b43_nphy_rssi_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3314 if (phy->rev >= 3) {
3315 nphy->cal_orig_pwr_idx[0] =
3316 nphy->txpwrindex[0].index_internal;
3317 nphy->cal_orig_pwr_idx[1] =
3318 nphy->txpwrindex[1].index_internal;
3319 /* TODO N PHY Pre Calibrate TX Gain */
Rafał Miłeckib0022e12010-01-15 15:40:50 +0100[diff] [blame]3320 target = b43_nphy_get_tx_gains(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3321 }
3322 }
3323 }
3324 }
3325
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3326 if (!b43_nphy_cal_tx_iq_lo(dev, target, true, false)) {
3327 if (b43_nphy_cal_rx_iq(dev, target, 2, 0) == 0)
Rafał Miłeckibbc6dc12010-02-04 12:23:11 +0100[diff] [blame]3328 b43_nphy_save_cal(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3329 else if (nphy->mphase_cal_phase_id == 0)
Rafał Miłecki15931e32010-01-15 16:20:56 +0100[diff] [blame]3330 ;/* N PHY Periodic Calibration with argument 3 */
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3331 } else {
3332 b43_nphy_restore_cal(dev);
3333 }
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3334
Rafał Miłecki6dcd9d92010-01-15 16:24:57 +0100[diff] [blame]3335 b43_nphy_tx_pwr_ctrl_coef_setup(dev);
Rafał Miłecki0988a7a2010-01-15 13:27:29 +0100[diff] [blame]3336 /* TODO N PHY TX Power Control Enable with argument tx_pwr_state */
3337 b43_phy_write(dev, B43_NPHY_TXMACIF_HOLDOFF, 0x0015);
3338 b43_phy_write(dev, B43_NPHY_TXMACDELAY, 0x0320);
3339 if (phy->rev >= 3 && phy->rev <= 6)
3340 b43_phy_write(dev, B43_NPHY_PLOAD_CSENSE_EXTLEN, 0x0014);
Rafał Miłeckife3e46e2010-01-15 15:51:55 +0100[diff] [blame]3341 b43_nphy_tx_lp_fbw(dev);
Rafał Miłecki9442e5b2010-02-04 12:23:12 +0100[diff] [blame]3342 if (phy->rev >= 3)
3343 b43_nphy_spur_workaround(dev);
Michael Buesch95b66ba2008-01-18 01:09:25 +0100[diff] [blame]3344
3345 b43err(dev->wl, "IEEE 802.11n devices are not supported, yet.\n");
Michael Buesch53a6e232008-01-13 21:23:44 +0100[diff] [blame]3346 return 0;
Michael Buesch424047e2008-01-09 16:13:56 +0100[diff] [blame]3347}
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3348
Rafał Miłecki1b69ec72010-02-27 13:03:40 +0100[diff] [blame]3349/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/ChanspecSetup */
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3350static void b43_nphy_channel_setup(struct b43_wldev *dev,
Rafał Miłeckib15b3032010-03-29 00:53:13 +0200[diff] [blame]3351 const struct b43_phy_n_sfo_cfg *e,
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3352 struct ieee80211_channel *new_channel)
Rafał Miłecki1b69ec72010-02-27 13:03:40 +0100[diff] [blame]3353{
3354 struct b43_phy *phy = &dev->phy;
3355 struct b43_phy_n *nphy = dev->phy.n;
3356
Rafał Miłecki087de742010-10-11 03:11:03 +0200[diff] [blame]3357 u16 old_band_5ghz;
Rafał Miłecki1b69ec72010-02-27 13:03:40 +0100[diff] [blame]3358 u32 tmp32;
3359
Rafał Miłecki087de742010-10-11 03:11:03 +0200[diff] [blame]3360 old_band_5ghz =
3361 b43_phy_read(dev, B43_NPHY_BANDCTL) & B43_NPHY_BANDCTL_5GHZ;
3362 if (new_channel->band == IEEE80211_BAND_5GHZ && !old_band_5ghz) {
Rafał Miłecki1b69ec72010-02-27 13:03:40 +0100[diff] [blame]3363 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3364 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
3365 b43_phy_set(dev, B43_PHY_B_BBCFG, 0xC000);
3366 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3367 b43_phy_set(dev, B43_NPHY_BANDCTL, B43_NPHY_BANDCTL_5GHZ);
Rafał Miłecki087de742010-10-11 03:11:03 +0200[diff] [blame]3368 } else if (new_channel->band == IEEE80211_BAND_2GHZ && old_band_5ghz) {
Rafał Miłecki1b69ec72010-02-27 13:03:40 +0100[diff] [blame]3369 b43_phy_mask(dev, B43_NPHY_BANDCTL, ~B43_NPHY_BANDCTL_5GHZ);
3370 tmp32 = b43_read32(dev, B43_MMIO_PSM_PHY_HDR);
3371 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32 | 4);
Larry Fingeracd82aa2010-07-21 11:48:05 -0500[diff] [blame]3372 b43_phy_mask(dev, B43_PHY_B_BBCFG, 0x3FFF);
Rafał Miłecki1b69ec72010-02-27 13:03:40 +0100[diff] [blame]3373 b43_write32(dev, B43_MMIO_PSM_PHY_HDR, tmp32);
3374 }
3375
3376 b43_chantab_phy_upload(dev, e);
3377
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3378 if (new_channel->hw_value == 14) {
Rafał Miłecki1b69ec72010-02-27 13:03:40 +0100[diff] [blame]3379 b43_nphy_classifier(dev, 2, 0);
3380 b43_phy_set(dev, B43_PHY_B_TEST, 0x0800);
3381 } else {
3382 b43_nphy_classifier(dev, 2, 2);
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3383 if (new_channel->band == IEEE80211_BAND_2GHZ)
Rafał Miłecki1b69ec72010-02-27 13:03:40 +0100[diff] [blame]3384 b43_phy_mask(dev, B43_PHY_B_TEST, ~0x840);
3385 }
3386
3387 if (nphy->txpwrctrl)
3388 b43_nphy_tx_power_fix(dev);
3389
3390 if (dev->phy.rev < 3)
3391 b43_nphy_adjust_lna_gain_table(dev);
3392
3393 b43_nphy_tx_lp_fbw(dev);
3394
3395 if (dev->phy.rev >= 3 && 0) {
3396 /* TODO */
3397 }
3398
3399 b43_phy_write(dev, B43_NPHY_NDATAT_DUP40, 0x3830);
3400
3401 if (phy->rev >= 3)
3402 b43_nphy_spur_workaround(dev);
3403}
3404
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3405/* http://bcm-v4.sipsolutions.net/802.11/PHY/N/SetChanspec */
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3406static int b43_nphy_set_channel(struct b43_wldev *dev,
3407 struct ieee80211_channel *channel,
3408 enum nl80211_channel_type channel_type)
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3409{
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3410 struct b43_phy *phy = &dev->phy;
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3411
Rafał Miłeckif19ebe72010-03-29 00:53:15 +0200[diff] [blame]3412 const struct b43_nphy_channeltab_entry_rev2 *tabent_r2;
3413 const struct b43_nphy_channeltab_entry_rev3 *tabent_r3;
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3414
3415 u8 tmp;
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3416
3417 if (dev->phy.rev >= 3) {
Rafał Miłeckif2a6d6a2010-10-11 03:19:22 +0200[diff] [blame]3418 tabent_r3 = b43_nphy_get_chantabent_rev3(dev,
3419 channel->center_freq);
Rafał Miłeckif19ebe72010-03-29 00:53:15 +0200[diff] [blame]3420 tabent_r3 = NULL;
3421 if (!tabent_r3)
3422 return -ESRCH;
Rafał Miłeckiffd2d9b2010-03-29 00:53:14 +0200[diff] [blame]3423 } else {
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3424 tabent_r2 = b43_nphy_get_chantabent_rev2(dev,
3425 channel->hw_value);
Rafał Miłeckif19ebe72010-03-29 00:53:15 +0200[diff] [blame]3426 if (!tabent_r2)
Rafał Miłeckiffd2d9b2010-03-29 00:53:14 +0200[diff] [blame]3427 return -ESRCH;
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3428 }
3429
Rafał Miłecki204a6652010-10-14 19:33:34 +0200[diff] [blame]3430 /* Channel is set later in common code, but we need to set it on our
3431 own to let this function's subcalls work properly. */
3432 phy->channel = channel->hw_value;
3433 phy->channel_freq = channel->center_freq;
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3434
Rafał Miłeckie5c407f2010-10-11 03:11:02 +0200[diff] [blame]3435 if (b43_channel_type_is_40mhz(phy->channel_type) !=
3436 b43_channel_type_is_40mhz(channel_type))
3437 ; /* TODO: BMAC BW Set (channel_type) */
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3438
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3439 if (channel_type == NL80211_CHAN_HT40PLUS)
3440 b43_phy_set(dev, B43_NPHY_RXCTL,
3441 B43_NPHY_RXCTL_BSELU20);
3442 else if (channel_type == NL80211_CHAN_HT40MINUS)
3443 b43_phy_mask(dev, B43_NPHY_RXCTL,
3444 ~B43_NPHY_RXCTL_BSELU20);
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3445
3446 if (dev->phy.rev >= 3) {
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3447 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 4 : 0;
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3448 b43_radio_maskset(dev, 0x08, 0xFFFB, tmp);
Rafał Miłeckif19ebe72010-03-29 00:53:15 +0200[diff] [blame]3449 /* TODO: PHY Radio2056 Setup (dev, tabent_r3); */
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3450 b43_nphy_channel_setup(dev, &(tabent_r3->phy_regs), channel);
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3451 } else {
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3452 tmp = (channel->band == IEEE80211_BAND_5GHZ) ? 0x0020 : 0x0050;
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3453 b43_radio_maskset(dev, B2055_MASTER1, 0xFF8F, tmp);
Rafał Miłeckif19ebe72010-03-29 00:53:15 +0200[diff] [blame]3454 b43_radio_2055_setup(dev, tabent_r2);
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3455 b43_nphy_channel_setup(dev, &(tabent_r2->phy_regs), channel);
Rafał Miłeckieff66c52010-02-27 13:03:41 +0100[diff] [blame]3456 }
3457
3458 return 0;
3459}
3460
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3461static int b43_nphy_op_allocate(struct b43_wldev *dev)
3462{
3463 struct b43_phy_n *nphy;
3464
3465 nphy = kzalloc(sizeof(*nphy), GFP_KERNEL);
3466 if (!nphy)
3467 return -ENOMEM;
3468 dev->phy.n = nphy;
3469
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3470 return 0;
3471}
3472
Michael Bueschfb111372008-09-02 13:00:34 +0200[diff] [blame]3473static void b43_nphy_op_prepare_structs(struct b43_wldev *dev)
3474{
3475 struct b43_phy *phy = &dev->phy;
3476 struct b43_phy_n *nphy = phy->n;
3477
3478 memset(nphy, 0, sizeof(*nphy));
3479
Rafał Miłecki0b81c232010-11-18 21:11:43 +0100[diff] [blame^]3480 nphy->gain_boost = true; /* this way we follow wl, assume it is true */
3481 nphy->txrx_chain = 2; /* sth different than 0 and 1 for now */
3482 nphy->phyrxchain = 3; /* to avoid b43_nphy_set_rx_core_state like wl */
Michael Bueschfb111372008-09-02 13:00:34 +0200[diff] [blame]3483}
3484
3485static void b43_nphy_op_free(struct b43_wldev *dev)
3486{
3487 struct b43_phy *phy = &dev->phy;
3488 struct b43_phy_n *nphy = phy->n;
3489
3490 kfree(nphy);
3491 phy->n = NULL;
3492}
3493
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3494static int b43_nphy_op_init(struct b43_wldev *dev)
3495{
Michael Bueschfb111372008-09-02 13:00:34 +0200[diff] [blame]3496 return b43_phy_initn(dev);
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3497}
3498
3499static inline void check_phyreg(struct b43_wldev *dev, u16 offset)
3500{
3501#if B43_DEBUG
3502 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_OFDM_GPHY) {
3503 /* OFDM registers are onnly available on A/G-PHYs */
3504 b43err(dev->wl, "Invalid OFDM PHY access at "
3505 "0x%04X on N-PHY\n", offset);
3506 dump_stack();
3507 }
3508 if ((offset & B43_PHYROUTE) == B43_PHYROUTE_EXT_GPHY) {
3509 /* Ext-G registers are only available on G-PHYs */
3510 b43err(dev->wl, "Invalid EXT-G PHY access at "
3511 "0x%04X on N-PHY\n", offset);
3512 dump_stack();
3513 }
3514#endif /* B43_DEBUG */
3515}
3516
3517static u16 b43_nphy_op_read(struct b43_wldev *dev, u16 reg)
3518{
3519 check_phyreg(dev, reg);
3520 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3521 return b43_read16(dev, B43_MMIO_PHY_DATA);
3522}
3523
3524static void b43_nphy_op_write(struct b43_wldev *dev, u16 reg, u16 value)
3525{
3526 check_phyreg(dev, reg);
3527 b43_write16(dev, B43_MMIO_PHY_CONTROL, reg);
3528 b43_write16(dev, B43_MMIO_PHY_DATA, value);
3529}
3530
3531static u16 b43_nphy_op_radio_read(struct b43_wldev *dev, u16 reg)
3532{
3533 /* Register 1 is a 32-bit register. */
3534 B43_WARN_ON(reg == 1);
3535 /* N-PHY needs 0x100 for read access */
3536 reg |= 0x100;
3537
3538 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3539 return b43_read16(dev, B43_MMIO_RADIO_DATA_LOW);
3540}
3541
3542static void b43_nphy_op_radio_write(struct b43_wldev *dev, u16 reg, u16 value)
3543{
3544 /* Register 1 is a 32-bit register. */
3545 B43_WARN_ON(reg == 1);
3546
3547 b43_write16(dev, B43_MMIO_RADIO_CONTROL, reg);
3548 b43_write16(dev, B43_MMIO_RADIO_DATA_LOW, value);
3549}
3550
Rafał Miłeckic2b7aef2010-02-27 13:03:34 +0100[diff] [blame]3551/* http://bcm-v4.sipsolutions.net/802.11/Radio/Switch%20Radio */
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3552static void b43_nphy_op_software_rfkill(struct b43_wldev *dev,
Johannes Berg19d337d2009-06-02 13:01:37 +0200[diff] [blame]3553 bool blocked)
Rafał Miłeckic2b7aef2010-02-27 13:03:34 +0100[diff] [blame]3554{
3555 if (b43_read32(dev, B43_MMIO_MACCTL) & B43_MACCTL_ENABLED)
3556 b43err(dev->wl, "MAC not suspended\n");
3557
3558 if (blocked) {
3559 b43_phy_mask(dev, B43_NPHY_RFCTL_CMD,
3560 ~B43_NPHY_RFCTL_CMD_CHIP0PU);
3561 if (dev->phy.rev >= 3) {
3562 b43_radio_mask(dev, 0x09, ~0x2);
3563
3564 b43_radio_write(dev, 0x204D, 0);
3565 b43_radio_write(dev, 0x2053, 0);
3566 b43_radio_write(dev, 0x2058, 0);
3567 b43_radio_write(dev, 0x205E, 0);
3568 b43_radio_mask(dev, 0x2062, ~0xF0);
3569 b43_radio_write(dev, 0x2064, 0);
3570
3571 b43_radio_write(dev, 0x304D, 0);
3572 b43_radio_write(dev, 0x3053, 0);
3573 b43_radio_write(dev, 0x3058, 0);
3574 b43_radio_write(dev, 0x305E, 0);
3575 b43_radio_mask(dev, 0x3062, ~0xF0);
3576 b43_radio_write(dev, 0x3064, 0);
3577 }
3578 } else {
3579 if (dev->phy.rev >= 3) {
Rafał Miłeckid817f4e2010-03-29 00:53:12 +0200[diff] [blame]3580 b43_radio_init2056(dev);
Rafał Miłecki78159782010-10-06 07:50:08 +0200[diff] [blame]3581 b43_switch_channel(dev, dev->phy.channel);
Rafał Miłeckic2b7aef2010-02-27 13:03:34 +0100[diff] [blame]3582 } else {
3583 b43_radio_init2055(dev);
3584 }
3585 }
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3586}
3587
Michael Bueschcb24f572008-09-03 12:12:20 +0200[diff] [blame]3588static void b43_nphy_op_switch_analog(struct b43_wldev *dev, bool on)
3589{
3590 b43_phy_write(dev, B43_NPHY_AFECTL_OVER,
3591 on ? 0 : 0x7FFF);
3592}
3593
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3594static int b43_nphy_op_switch_channel(struct b43_wldev *dev,
3595 unsigned int new_channel)
3596{
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3597 struct ieee80211_channel *channel = dev->wl->hw->conf.channel;
3598 enum nl80211_channel_type channel_type = dev->wl->hw->conf.channel_type;
Rafał Miłecki5e7ee092010-10-06 07:50:06 +0200[diff] [blame]3599
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3600 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ) {
3601 if ((new_channel < 1) || (new_channel > 14))
3602 return -EINVAL;
3603 } else {
3604 if (new_channel > 200)
3605 return -EINVAL;
3606 }
3607
Rafał Miłeckia656b6a2010-10-11 03:11:01 +0200[diff] [blame]3608 return b43_nphy_set_channel(dev, channel, channel_type);
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3609}
3610
3611static unsigned int b43_nphy_op_get_default_chan(struct b43_wldev *dev)
3612{
3613 if (b43_current_band(dev->wl) == IEEE80211_BAND_2GHZ)
3614 return 1;
3615 return 36;
3616}
3617
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3618const struct b43_phy_operations b43_phyops_n = {
3619 .allocate = b43_nphy_op_allocate,
Michael Bueschfb111372008-09-02 13:00:34 +0200[diff] [blame]3620 .free = b43_nphy_op_free,
3621 .prepare_structs = b43_nphy_op_prepare_structs,
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3622 .init = b43_nphy_op_init,
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3623 .phy_read = b43_nphy_op_read,
3624 .phy_write = b43_nphy_op_write,
3625 .radio_read = b43_nphy_op_radio_read,
3626 .radio_write = b43_nphy_op_radio_write,
3627 .software_rfkill = b43_nphy_op_software_rfkill,
Michael Bueschcb24f572008-09-03 12:12:20 +0200[diff] [blame]3628 .switch_analog = b43_nphy_op_switch_analog,
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3629 .switch_channel = b43_nphy_op_switch_channel,
3630 .get_default_chan = b43_nphy_op_get_default_chan,
Michael Buesch18c8ade2008-08-28 19:33:40 +0200[diff] [blame]3631 .recalc_txpower = b43_nphy_op_recalc_txpower,
3632 .adjust_txpower = b43_nphy_op_adjust_txpower,
Michael Bueschef1a6282008-08-27 18:53:02 +0200[diff] [blame]3633};