blob: f0206f63617ec6f3132dce0aaf715c329799124a [file] [log] [blame]
Dave Airlie0d6aa602006-01-02 20:14:23 +11001/* i915_irq.c -- IRQ support for the I915 -*- linux-c -*-
Linus Torvalds1da177e2005-04-16 15:20:36 -07002 */
Dave Airlie0d6aa602006-01-02 20:14:23 +11003/*
Linus Torvalds1da177e2005-04-16 15:20:36 -07004 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas.
5 * All Rights Reserved.
Dave Airliebc54fd12005-06-23 22:46:46 +10006 *
7 * Permission is hereby granted, free of charge, to any person obtaining a
8 * copy of this software and associated documentation files (the
9 * "Software"), to deal in the Software without restriction, including
10 * without limitation the rights to use, copy, modify, merge, publish,
11 * distribute, sub license, and/or sell copies of the Software, and to
12 * permit persons to whom the Software is furnished to do so, subject to
13 * the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the
16 * next paragraph) shall be included in all copies or substantial portions
17 * of the Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
20 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
21 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
22 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
23 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
24 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
25 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 *
Dave Airlie0d6aa602006-01-02 20:14:23 +110027 */
Linus Torvalds1da177e2005-04-16 15:20:36 -070028
Joe Perchesa70491c2012-03-18 13:00:11 -070029#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
30
Jesse Barnes63eeaf32009-06-18 16:56:52 -070031#include <linux/sysrq.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090032#include <linux/slab.h>
Damien Lespiaub2c88f52013-10-15 18:55:29 +010033#include <linux/circ_buf.h>
David Howells760285e2012-10-02 18:01:07 +010034#include <drm/drmP.h>
35#include <drm/i915_drm.h>
Linus Torvalds1da177e2005-04-16 15:20:36 -070036#include "i915_drv.h"
Chris Wilson1c5d22f2009-08-25 11:15:50 +010037#include "i915_trace.h"
Jesse Barnes79e53942008-11-07 14:24:08 -080038#include "intel_drv.h"
Linus Torvalds1da177e2005-04-16 15:20:36 -070039
Daniel Vetterfca52a52014-09-30 10:56:45 +020040/**
41 * DOC: interrupt handling
42 *
43 * These functions provide the basic support for enabling and disabling the
44 * interrupt handling support. There's a lot more functionality in i915_irq.c
45 * and related files, but that will be described in separate chapters.
46 */
47
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020048static const u32 hpd_ibx[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050049 [HPD_CRT] = SDE_CRT_HOTPLUG,
50 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG,
51 [HPD_PORT_B] = SDE_PORTB_HOTPLUG,
52 [HPD_PORT_C] = SDE_PORTC_HOTPLUG,
53 [HPD_PORT_D] = SDE_PORTD_HOTPLUG
54};
55
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020056static const u32 hpd_cpt[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050057 [HPD_CRT] = SDE_CRT_HOTPLUG_CPT,
Daniel Vetter73c352a2013-03-26 22:38:43 +010058 [HPD_SDVO_B] = SDE_SDVOB_HOTPLUG_CPT,
Egbert Eiche5868a32013-02-28 04:17:12 -050059 [HPD_PORT_B] = SDE_PORTB_HOTPLUG_CPT,
60 [HPD_PORT_C] = SDE_PORTC_HOTPLUG_CPT,
61 [HPD_PORT_D] = SDE_PORTD_HOTPLUG_CPT
62};
63
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020064static const u32 hpd_mask_i915[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050065 [HPD_CRT] = CRT_HOTPLUG_INT_EN,
66 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_EN,
67 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_EN,
68 [HPD_PORT_B] = PORTB_HOTPLUG_INT_EN,
69 [HPD_PORT_C] = PORTC_HOTPLUG_INT_EN,
70 [HPD_PORT_D] = PORTD_HOTPLUG_INT_EN
71};
72
Ville Syrjälä7c7e10d2015-01-09 14:21:12 +020073static const u32 hpd_status_g4x[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050074 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
75 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_G4X,
76 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_G4X,
77 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
78 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
79 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
80};
81
Ville Syrjälä4bca26d2015-05-11 20:49:10 +030082static const u32 hpd_status_i915[HPD_NUM_PINS] = {
Egbert Eiche5868a32013-02-28 04:17:12 -050083 [HPD_CRT] = CRT_HOTPLUG_INT_STATUS,
84 [HPD_SDVO_B] = SDVOB_HOTPLUG_INT_STATUS_I915,
85 [HPD_SDVO_C] = SDVOC_HOTPLUG_INT_STATUS_I915,
86 [HPD_PORT_B] = PORTB_HOTPLUG_INT_STATUS,
87 [HPD_PORT_C] = PORTC_HOTPLUG_INT_STATUS,
88 [HPD_PORT_D] = PORTD_HOTPLUG_INT_STATUS
89};
90
Shashank Sharmae0a20ad2015-03-27 14:54:14 +020091/* BXT hpd list */
92static const u32 hpd_bxt[HPD_NUM_PINS] = {
93 [HPD_PORT_B] = BXT_DE_PORT_HP_DDIB,
94 [HPD_PORT_C] = BXT_DE_PORT_HP_DDIC
95};
96
Paulo Zanoni5c502442014-04-01 15:37:11 -030097/* IIR can theoretically queue up two events. Be paranoid. */
Paulo Zanonif86f3fb2014-04-01 15:37:14 -030098#define GEN8_IRQ_RESET_NDX(type, which) do { \
Paulo Zanoni5c502442014-04-01 15:37:11 -030099 I915_WRITE(GEN8_##type##_IMR(which), 0xffffffff); \
100 POSTING_READ(GEN8_##type##_IMR(which)); \
101 I915_WRITE(GEN8_##type##_IER(which), 0); \
102 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
103 POSTING_READ(GEN8_##type##_IIR(which)); \
104 I915_WRITE(GEN8_##type##_IIR(which), 0xffffffff); \
105 POSTING_READ(GEN8_##type##_IIR(which)); \
106} while (0)
107
Paulo Zanonif86f3fb2014-04-01 15:37:14 -0300108#define GEN5_IRQ_RESET(type) do { \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300109 I915_WRITE(type##IMR, 0xffffffff); \
Paulo Zanoni5c502442014-04-01 15:37:11 -0300110 POSTING_READ(type##IMR); \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300111 I915_WRITE(type##IER, 0); \
Paulo Zanoni5c502442014-04-01 15:37:11 -0300112 I915_WRITE(type##IIR, 0xffffffff); \
113 POSTING_READ(type##IIR); \
114 I915_WRITE(type##IIR, 0xffffffff); \
115 POSTING_READ(type##IIR); \
Paulo Zanonia9d356a2014-04-01 15:37:09 -0300116} while (0)
117
Paulo Zanoni337ba012014-04-01 15:37:16 -0300118/*
119 * We should clear IMR at preinstall/uninstall, and just check at postinstall.
120 */
121#define GEN5_ASSERT_IIR_IS_ZERO(reg) do { \
122 u32 val = I915_READ(reg); \
123 if (val) { \
124 WARN(1, "Interrupt register 0x%x is not zero: 0x%08x\n", \
125 (reg), val); \
126 I915_WRITE((reg), 0xffffffff); \
127 POSTING_READ(reg); \
128 I915_WRITE((reg), 0xffffffff); \
129 POSTING_READ(reg); \
130 } \
131} while (0)
132
Paulo Zanoni35079892014-04-01 15:37:15 -0300133#define GEN8_IRQ_INIT_NDX(type, which, imr_val, ier_val) do { \
Paulo Zanoni337ba012014-04-01 15:37:16 -0300134 GEN5_ASSERT_IIR_IS_ZERO(GEN8_##type##_IIR(which)); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300135 I915_WRITE(GEN8_##type##_IER(which), (ier_val)); \
Ville Syrjälä7d1bd5392014-10-30 19:42:50 +0200136 I915_WRITE(GEN8_##type##_IMR(which), (imr_val)); \
137 POSTING_READ(GEN8_##type##_IMR(which)); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300138} while (0)
139
140#define GEN5_IRQ_INIT(type, imr_val, ier_val) do { \
Paulo Zanoni337ba012014-04-01 15:37:16 -0300141 GEN5_ASSERT_IIR_IS_ZERO(type##IIR); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300142 I915_WRITE(type##IER, (ier_val)); \
Ville Syrjälä7d1bd5392014-10-30 19:42:50 +0200143 I915_WRITE(type##IMR, (imr_val)); \
144 POSTING_READ(type##IMR); \
Paulo Zanoni35079892014-04-01 15:37:15 -0300145} while (0)
146
Imre Deakc9a9a262014-11-05 20:48:37 +0200147static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir);
148
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800149/* For display hotplug interrupt */
Daniel Vetter47339cd2014-09-30 10:56:46 +0200150void
Jani Nikula2d1013d2014-03-31 14:27:17 +0300151ironlake_enable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800152{
Daniel Vetter4bc9d432013-06-27 13:44:58 +0200153 assert_spin_locked(&dev_priv->irq_lock);
154
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700155 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300156 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300157
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000158 if ((dev_priv->irq_mask & mask) != 0) {
159 dev_priv->irq_mask &= ~mask;
160 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000161 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800162 }
163}
164
Daniel Vetter47339cd2014-09-30 10:56:46 +0200165void
Jani Nikula2d1013d2014-03-31 14:27:17 +0300166ironlake_disable_display_irq(struct drm_i915_private *dev_priv, u32 mask)
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800167{
Daniel Vetter4bc9d432013-06-27 13:44:58 +0200168 assert_spin_locked(&dev_priv->irq_lock);
169
Paulo Zanoni06ffc772014-07-17 17:43:46 -0300170 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300171 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300172
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000173 if ((dev_priv->irq_mask & mask) != mask) {
174 dev_priv->irq_mask |= mask;
175 I915_WRITE(DEIMR, dev_priv->irq_mask);
Chris Wilson3143a2b2010-11-16 15:55:10 +0000176 POSTING_READ(DEIMR);
Zhenyu Wang036a4a72009-06-08 14:40:19 +0800177 }
178}
179
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300180/**
181 * ilk_update_gt_irq - update GTIMR
182 * @dev_priv: driver private
183 * @interrupt_mask: mask of interrupt bits to update
184 * @enabled_irq_mask: mask of interrupt bits to enable
185 */
186static void ilk_update_gt_irq(struct drm_i915_private *dev_priv,
187 uint32_t interrupt_mask,
188 uint32_t enabled_irq_mask)
189{
190 assert_spin_locked(&dev_priv->irq_lock);
191
Daniel Vetter15a17aa2014-12-08 16:30:00 +0100192 WARN_ON(enabled_irq_mask & ~interrupt_mask);
193
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700194 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300195 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300196
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300197 dev_priv->gt_irq_mask &= ~interrupt_mask;
198 dev_priv->gt_irq_mask |= (~enabled_irq_mask & interrupt_mask);
199 I915_WRITE(GTIMR, dev_priv->gt_irq_mask);
200 POSTING_READ(GTIMR);
201}
202
Daniel Vetter480c8032014-07-16 09:49:40 +0200203void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300204{
205 ilk_update_gt_irq(dev_priv, mask, mask);
206}
207
Daniel Vetter480c8032014-07-16 09:49:40 +0200208void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoni43eaea12013-08-06 18:57:12 -0300209{
210 ilk_update_gt_irq(dev_priv, mask, 0);
211}
212
Imre Deakb900b942014-11-05 20:48:48 +0200213static u32 gen6_pm_iir(struct drm_i915_private *dev_priv)
214{
215 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IIR(2) : GEN6_PMIIR;
216}
217
Imre Deaka72fbc32014-11-05 20:48:31 +0200218static u32 gen6_pm_imr(struct drm_i915_private *dev_priv)
219{
220 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IMR(2) : GEN6_PMIMR;
221}
222
Imre Deakb900b942014-11-05 20:48:48 +0200223static u32 gen6_pm_ier(struct drm_i915_private *dev_priv)
224{
225 return INTEL_INFO(dev_priv)->gen >= 8 ? GEN8_GT_IER(2) : GEN6_PMIER;
226}
227
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300228/**
229 * snb_update_pm_irq - update GEN6_PMIMR
230 * @dev_priv: driver private
231 * @interrupt_mask: mask of interrupt bits to update
232 * @enabled_irq_mask: mask of interrupt bits to enable
233 */
234static void snb_update_pm_irq(struct drm_i915_private *dev_priv,
235 uint32_t interrupt_mask,
236 uint32_t enabled_irq_mask)
237{
Paulo Zanoni605cd252013-08-06 18:57:15 -0300238 uint32_t new_val;
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300239
Daniel Vetter15a17aa2014-12-08 16:30:00 +0100240 WARN_ON(enabled_irq_mask & ~interrupt_mask);
241
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300242 assert_spin_locked(&dev_priv->irq_lock);
243
Paulo Zanoni605cd252013-08-06 18:57:15 -0300244 new_val = dev_priv->pm_irq_mask;
Paulo Zanonif52ecbc2013-08-06 18:57:14 -0300245 new_val &= ~interrupt_mask;
246 new_val |= (~enabled_irq_mask & interrupt_mask);
247
Paulo Zanoni605cd252013-08-06 18:57:15 -0300248 if (new_val != dev_priv->pm_irq_mask) {
249 dev_priv->pm_irq_mask = new_val;
Imre Deaka72fbc32014-11-05 20:48:31 +0200250 I915_WRITE(gen6_pm_imr(dev_priv), dev_priv->pm_irq_mask);
251 POSTING_READ(gen6_pm_imr(dev_priv));
Paulo Zanonif52ecbc2013-08-06 18:57:14 -0300252 }
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300253}
254
Daniel Vetter480c8032014-07-16 09:49:40 +0200255void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300256{
Imre Deak9939fba2014-11-20 23:01:47 +0200257 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
258 return;
259
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300260 snb_update_pm_irq(dev_priv, mask, mask);
261}
262
Imre Deak9939fba2014-11-20 23:01:47 +0200263static void __gen6_disable_pm_irq(struct drm_i915_private *dev_priv,
264 uint32_t mask)
265{
266 snb_update_pm_irq(dev_priv, mask, 0);
267}
268
Daniel Vetter480c8032014-07-16 09:49:40 +0200269void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask)
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300270{
Imre Deak9939fba2014-11-20 23:01:47 +0200271 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
272 return;
273
274 __gen6_disable_pm_irq(dev_priv, mask);
Paulo Zanoniedbfdb42013-08-06 18:57:13 -0300275}
276
Imre Deak3cc134e2014-11-19 15:30:03 +0200277void gen6_reset_rps_interrupts(struct drm_device *dev)
278{
279 struct drm_i915_private *dev_priv = dev->dev_private;
280 uint32_t reg = gen6_pm_iir(dev_priv);
281
282 spin_lock_irq(&dev_priv->irq_lock);
283 I915_WRITE(reg, dev_priv->pm_rps_events);
284 I915_WRITE(reg, dev_priv->pm_rps_events);
285 POSTING_READ(reg);
Imre Deak096fad92015-03-23 19:11:35 +0200286 dev_priv->rps.pm_iir = 0;
Imre Deak3cc134e2014-11-19 15:30:03 +0200287 spin_unlock_irq(&dev_priv->irq_lock);
288}
289
Imre Deakb900b942014-11-05 20:48:48 +0200290void gen6_enable_rps_interrupts(struct drm_device *dev)
291{
292 struct drm_i915_private *dev_priv = dev->dev_private;
293
294 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak78e68d32014-12-15 18:59:27 +0200295
Imre Deakb900b942014-11-05 20:48:48 +0200296 WARN_ON(dev_priv->rps.pm_iir);
Imre Deak3cc134e2014-11-19 15:30:03 +0200297 WARN_ON(I915_READ(gen6_pm_iir(dev_priv)) & dev_priv->pm_rps_events);
Imre Deakd4d70aa2014-11-19 15:30:04 +0200298 dev_priv->rps.interrupts_enabled = true;
Imre Deak78e68d32014-12-15 18:59:27 +0200299 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) |
300 dev_priv->pm_rps_events);
Imre Deakb900b942014-11-05 20:48:48 +0200301 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
Imre Deak78e68d32014-12-15 18:59:27 +0200302
Imre Deakb900b942014-11-05 20:48:48 +0200303 spin_unlock_irq(&dev_priv->irq_lock);
304}
305
Imre Deak59d02a12014-12-19 19:33:26 +0200306u32 gen6_sanitize_rps_pm_mask(struct drm_i915_private *dev_priv, u32 mask)
307{
308 /*
Imre Deakf24eeb12014-12-19 19:33:27 +0200309 * SNB,IVB can while VLV,CHV may hard hang on looping batchbuffer
Imre Deak59d02a12014-12-19 19:33:26 +0200310 * if GEN6_PM_UP_EI_EXPIRED is masked.
Imre Deakf24eeb12014-12-19 19:33:27 +0200311 *
312 * TODO: verify if this can be reproduced on VLV,CHV.
Imre Deak59d02a12014-12-19 19:33:26 +0200313 */
314 if (INTEL_INFO(dev_priv)->gen <= 7 && !IS_HASWELL(dev_priv))
315 mask &= ~GEN6_PM_RP_UP_EI_EXPIRED;
316
317 if (INTEL_INFO(dev_priv)->gen >= 8)
318 mask &= ~GEN8_PMINTR_REDIRECT_TO_NON_DISP;
319
320 return mask;
321}
322
Imre Deakb900b942014-11-05 20:48:48 +0200323void gen6_disable_rps_interrupts(struct drm_device *dev)
324{
325 struct drm_i915_private *dev_priv = dev->dev_private;
326
Imre Deakd4d70aa2014-11-19 15:30:04 +0200327 spin_lock_irq(&dev_priv->irq_lock);
328 dev_priv->rps.interrupts_enabled = false;
329 spin_unlock_irq(&dev_priv->irq_lock);
330
331 cancel_work_sync(&dev_priv->rps.work);
332
Imre Deak9939fba2014-11-20 23:01:47 +0200333 spin_lock_irq(&dev_priv->irq_lock);
334
Imre Deak59d02a12014-12-19 19:33:26 +0200335 I915_WRITE(GEN6_PMINTRMSK, gen6_sanitize_rps_pm_mask(dev_priv, ~0));
Imre Deak9939fba2014-11-20 23:01:47 +0200336
337 __gen6_disable_pm_irq(dev_priv, dev_priv->pm_rps_events);
Imre Deakb900b942014-11-05 20:48:48 +0200338 I915_WRITE(gen6_pm_ier(dev_priv), I915_READ(gen6_pm_ier(dev_priv)) &
339 ~dev_priv->pm_rps_events);
Imre Deak58072cc2015-03-23 19:11:34 +0200340
341 spin_unlock_irq(&dev_priv->irq_lock);
342
343 synchronize_irq(dev->irq);
Imre Deakb900b942014-11-05 20:48:48 +0200344}
345
Ben Widawsky09610212014-05-15 20:58:08 +0300346/**
Daniel Vetterfee884e2013-07-04 23:35:21 +0200347 * ibx_display_interrupt_update - update SDEIMR
348 * @dev_priv: driver private
349 * @interrupt_mask: mask of interrupt bits to update
350 * @enabled_irq_mask: mask of interrupt bits to enable
351 */
Daniel Vetter47339cd2014-09-30 10:56:46 +0200352void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
353 uint32_t interrupt_mask,
354 uint32_t enabled_irq_mask)
Daniel Vetterfee884e2013-07-04 23:35:21 +0200355{
356 uint32_t sdeimr = I915_READ(SDEIMR);
357 sdeimr &= ~interrupt_mask;
358 sdeimr |= (~enabled_irq_mask & interrupt_mask);
359
Daniel Vetter15a17aa2014-12-08 16:30:00 +0100360 WARN_ON(enabled_irq_mask & ~interrupt_mask);
361
Daniel Vetterfee884e2013-07-04 23:35:21 +0200362 assert_spin_locked(&dev_priv->irq_lock);
363
Jesse Barnes9df7575f2014-06-20 09:29:20 -0700364 if (WARN_ON(!intel_irqs_enabled(dev_priv)))
Paulo Zanonic67a4702013-08-19 13:18:09 -0300365 return;
Paulo Zanonic67a4702013-08-19 13:18:09 -0300366
Daniel Vetterfee884e2013-07-04 23:35:21 +0200367 I915_WRITE(SDEIMR, sdeimr);
368 POSTING_READ(SDEIMR);
369}
Paulo Zanoni86642812013-04-12 17:57:57 -0300370
Daniel Vetterb5ea6422014-03-02 21:18:00 +0100371static void
Imre Deak755e9012014-02-10 18:42:47 +0200372__i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
373 u32 enable_mask, u32 status_mask)
Keith Packard7c463582008-11-04 02:03:27 -0800374{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200375 u32 reg = PIPESTAT(pipe);
Imre Deak755e9012014-02-10 18:42:47 +0200376 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
Keith Packard7c463582008-11-04 02:03:27 -0800377
Daniel Vetterb79480b2013-06-27 17:52:10 +0200378 assert_spin_locked(&dev_priv->irq_lock);
Daniel Vetterd518ce52014-08-27 10:43:37 +0200379 WARN_ON(!intel_irqs_enabled(dev_priv));
Daniel Vetterb79480b2013-06-27 17:52:10 +0200380
Ville Syrjälä04feced2014-04-03 13:28:33 +0300381 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
382 status_mask & ~PIPESTAT_INT_STATUS_MASK,
383 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
384 pipe_name(pipe), enable_mask, status_mask))
Imre Deak755e9012014-02-10 18:42:47 +0200385 return;
386
387 if ((pipestat & enable_mask) == enable_mask)
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200388 return;
389
Imre Deak91d181d2014-02-10 18:42:49 +0200390 dev_priv->pipestat_irq_mask[pipe] |= status_mask;
391
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200392 /* Enable the interrupt, clear any pending status */
Imre Deak755e9012014-02-10 18:42:47 +0200393 pipestat |= enable_mask | status_mask;
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200394 I915_WRITE(reg, pipestat);
395 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800396}
397
Daniel Vetterb5ea6422014-03-02 21:18:00 +0100398static void
Imre Deak755e9012014-02-10 18:42:47 +0200399__i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
400 u32 enable_mask, u32 status_mask)
Keith Packard7c463582008-11-04 02:03:27 -0800401{
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200402 u32 reg = PIPESTAT(pipe);
Imre Deak755e9012014-02-10 18:42:47 +0200403 u32 pipestat = I915_READ(reg) & PIPESTAT_INT_ENABLE_MASK;
Keith Packard7c463582008-11-04 02:03:27 -0800404
Daniel Vetterb79480b2013-06-27 17:52:10 +0200405 assert_spin_locked(&dev_priv->irq_lock);
Daniel Vetterd518ce52014-08-27 10:43:37 +0200406 WARN_ON(!intel_irqs_enabled(dev_priv));
Daniel Vetterb79480b2013-06-27 17:52:10 +0200407
Ville Syrjälä04feced2014-04-03 13:28:33 +0300408 if (WARN_ONCE(enable_mask & ~PIPESTAT_INT_ENABLE_MASK ||
409 status_mask & ~PIPESTAT_INT_STATUS_MASK,
410 "pipe %c: enable_mask=0x%x, status_mask=0x%x\n",
411 pipe_name(pipe), enable_mask, status_mask))
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200412 return;
413
Imre Deak755e9012014-02-10 18:42:47 +0200414 if ((pipestat & enable_mask) == 0)
415 return;
416
Imre Deak91d181d2014-02-10 18:42:49 +0200417 dev_priv->pipestat_irq_mask[pipe] &= ~status_mask;
418
Imre Deak755e9012014-02-10 18:42:47 +0200419 pipestat &= ~enable_mask;
Ville Syrjälä46c06a32013-02-20 21:16:18 +0200420 I915_WRITE(reg, pipestat);
421 POSTING_READ(reg);
Keith Packard7c463582008-11-04 02:03:27 -0800422}
423
Imre Deak10c59c52014-02-10 18:42:48 +0200424static u32 vlv_get_pipestat_enable_mask(struct drm_device *dev, u32 status_mask)
425{
426 u32 enable_mask = status_mask << 16;
427
428 /*
Ville Syrjälä724a6902014-04-09 13:28:48 +0300429 * On pipe A we don't support the PSR interrupt yet,
430 * on pipe B and C the same bit MBZ.
Imre Deak10c59c52014-02-10 18:42:48 +0200431 */
432 if (WARN_ON_ONCE(status_mask & PIPE_A_PSR_STATUS_VLV))
433 return 0;
Ville Syrjälä724a6902014-04-09 13:28:48 +0300434 /*
435 * On pipe B and C we don't support the PSR interrupt yet, on pipe
436 * A the same bit is for perf counters which we don't use either.
437 */
438 if (WARN_ON_ONCE(status_mask & PIPE_B_PSR_STATUS_VLV))
439 return 0;
Imre Deak10c59c52014-02-10 18:42:48 +0200440
441 enable_mask &= ~(PIPE_FIFO_UNDERRUN_STATUS |
442 SPRITE0_FLIP_DONE_INT_EN_VLV |
443 SPRITE1_FLIP_DONE_INT_EN_VLV);
444 if (status_mask & SPRITE0_FLIP_DONE_INT_STATUS_VLV)
445 enable_mask |= SPRITE0_FLIP_DONE_INT_EN_VLV;
446 if (status_mask & SPRITE1_FLIP_DONE_INT_STATUS_VLV)
447 enable_mask |= SPRITE1_FLIP_DONE_INT_EN_VLV;
448
449 return enable_mask;
450}
451
Imre Deak755e9012014-02-10 18:42:47 +0200452void
453i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
454 u32 status_mask)
455{
456 u32 enable_mask;
457
Imre Deak10c59c52014-02-10 18:42:48 +0200458 if (IS_VALLEYVIEW(dev_priv->dev))
459 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
460 status_mask);
461 else
462 enable_mask = status_mask << 16;
Imre Deak755e9012014-02-10 18:42:47 +0200463 __i915_enable_pipestat(dev_priv, pipe, enable_mask, status_mask);
464}
465
466void
467i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
468 u32 status_mask)
469{
470 u32 enable_mask;
471
Imre Deak10c59c52014-02-10 18:42:48 +0200472 if (IS_VALLEYVIEW(dev_priv->dev))
473 enable_mask = vlv_get_pipestat_enable_mask(dev_priv->dev,
474 status_mask);
475 else
476 enable_mask = status_mask << 16;
Imre Deak755e9012014-02-10 18:42:47 +0200477 __i915_disable_pipestat(dev_priv, pipe, enable_mask, status_mask);
478}
479
=?utf-8?q?Michel_D=C3=A4nzer?=a6b54f32006-10-24 23:37:43 +1000480/**
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300481 * i915_enable_asle_pipestat - enable ASLE pipestat for OpRegion
Zhao Yakui01c66882009-10-28 05:10:00 +0000482 */
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300483static void i915_enable_asle_pipestat(struct drm_device *dev)
Zhao Yakui01c66882009-10-28 05:10:00 +0000484{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300485 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000486
Jani Nikulaf49e38d2013-04-29 13:02:54 +0300487 if (!dev_priv->opregion.asle || !IS_MOBILE(dev))
488 return;
489
Daniel Vetter13321782014-09-15 14:55:29 +0200490 spin_lock_irq(&dev_priv->irq_lock);
Zhao Yakui01c66882009-10-28 05:10:00 +0000491
Imre Deak755e9012014-02-10 18:42:47 +0200492 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_LEGACY_BLC_EVENT_STATUS);
Jani Nikulaf8987802013-04-29 13:02:53 +0300493 if (INTEL_INFO(dev)->gen >= 4)
Daniel Vetter3b6c42e2013-10-21 18:04:35 +0200494 i915_enable_pipestat(dev_priv, PIPE_A,
Imre Deak755e9012014-02-10 18:42:47 +0200495 PIPE_LEGACY_BLC_EVENT_STATUS);
Chris Wilson1ec14ad2010-12-04 11:30:53 +0000496
Daniel Vetter13321782014-09-15 14:55:29 +0200497 spin_unlock_irq(&dev_priv->irq_lock);
Zhao Yakui01c66882009-10-28 05:10:00 +0000498}
499
Ville Syrjäläf75f3742014-05-15 20:20:36 +0300500/*
501 * This timing diagram depicts the video signal in and
502 * around the vertical blanking period.
503 *
504 * Assumptions about the fictitious mode used in this example:
505 * vblank_start >= 3
506 * vsync_start = vblank_start + 1
507 * vsync_end = vblank_start + 2
508 * vtotal = vblank_start + 3
509 *
510 * start of vblank:
511 * latch double buffered registers
512 * increment frame counter (ctg+)
513 * generate start of vblank interrupt (gen4+)
514 * |
515 * | frame start:
516 * | generate frame start interrupt (aka. vblank interrupt) (gmch)
517 * | may be shifted forward 1-3 extra lines via PIPECONF
518 * | |
519 * | | start of vsync:
520 * | | generate vsync interrupt
521 * | | |
522 * ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx___ ___xxxx
523 * . \hs/ . \hs/ \hs/ \hs/ . \hs/
524 * ----va---> <-----------------vb--------------------> <--------va-------------
525 * | | <----vs-----> |
526 * -vbs-----> <---vbs+1---> <---vbs+2---> <-----0-----> <-----1-----> <-----2--- (scanline counter gen2)
527 * -vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2---> <-----0--- (scanline counter gen3+)
528 * -vbs-2---> <---vbs-2---> <---vbs-1---> <---vbs-----> <---vbs+1---> <---vbs+2- (scanline counter hsw+ hdmi)
529 * | | |
530 * last visible pixel first visible pixel
531 * | increment frame counter (gen3/4)
532 * pixel counter = vblank_start * htotal pixel counter = 0 (gen3/4)
533 *
534 * x = horizontal active
535 * _ = horizontal blanking
536 * hs = horizontal sync
537 * va = vertical active
538 * vb = vertical blanking
539 * vs = vertical sync
540 * vbs = vblank_start (number)
541 *
542 * Summary:
543 * - most events happen at the start of horizontal sync
544 * - frame start happens at the start of horizontal blank, 1-4 lines
545 * (depending on PIPECONF settings) after the start of vblank
546 * - gen3/4 pixel and frame counter are synchronized with the start
547 * of horizontal active on the first line of vertical active
548 */
549
Ville Syrjälä4cdb83e2013-10-11 21:52:44 +0300550static u32 i8xx_get_vblank_counter(struct drm_device *dev, int pipe)
551{
552 /* Gen2 doesn't have a hardware frame counter */
553 return 0;
554}
555
Keith Packard42f52ef2008-10-18 19:39:29 -0700556/* Called from drm generic code, passed a 'crtc', which
557 * we use as a pipe index
558 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700559static u32 i915_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700560{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300561 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700562 unsigned long high_frame;
563 unsigned long low_frame;
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300564 u32 high1, high2, low, pixel, vbl_start, hsync_start, htotal;
Daniel Vetterf3a5c3f2015-02-13 21:03:44 +0100565 struct intel_crtc *intel_crtc =
566 to_intel_crtc(dev_priv->pipe_to_crtc_mapping[pipe]);
567 const struct drm_display_mode *mode =
568 &intel_crtc->config->base.adjusted_mode;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700569
Daniel Vetterf3a5c3f2015-02-13 21:03:44 +0100570 htotal = mode->crtc_htotal;
571 hsync_start = mode->crtc_hsync_start;
572 vbl_start = mode->crtc_vblank_start;
573 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
574 vbl_start = DIV_ROUND_UP(vbl_start, 2);
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300575
Ville Syrjälä0b2a8e02014-04-29 13:35:50 +0300576 /* Convert to pixel count */
577 vbl_start *= htotal;
578
579 /* Start of vblank event occurs at start of hsync */
580 vbl_start -= htotal - hsync_start;
581
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800582 high_frame = PIPEFRAME(pipe);
583 low_frame = PIPEFRAMEPIXEL(pipe);
Chris Wilson5eddb702010-09-11 13:48:45 +0100584
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700585 /*
586 * High & low register fields aren't synchronized, so make sure
587 * we get a low value that's stable across two reads of the high
588 * register.
589 */
590 do {
Chris Wilson5eddb702010-09-11 13:48:45 +0100591 high1 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300592 low = I915_READ(low_frame);
Chris Wilson5eddb702010-09-11 13:48:45 +0100593 high2 = I915_READ(high_frame) & PIPE_FRAME_HIGH_MASK;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700594 } while (high1 != high2);
595
Chris Wilson5eddb702010-09-11 13:48:45 +0100596 high1 >>= PIPE_FRAME_HIGH_SHIFT;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300597 pixel = low & PIPE_PIXEL_MASK;
Chris Wilson5eddb702010-09-11 13:48:45 +0100598 low >>= PIPE_FRAME_LOW_SHIFT;
Ville Syrjälä391f75e2013-09-25 19:55:26 +0300599
600 /*
601 * The frame counter increments at beginning of active.
602 * Cook up a vblank counter by also checking the pixel
603 * counter against vblank start.
604 */
Ville Syrjäläedc08d02013-11-06 13:56:27 -0200605 return (((high1 << 8) | low) + (pixel >= vbl_start)) & 0xffffff;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -0700606}
607
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700608static u32 gm45_get_vblank_counter(struct drm_device *dev, int pipe)
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800609{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300610 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800611 int reg = PIPE_FRMCOUNT_GM45(pipe);
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800612
Jesse Barnes9880b7a2009-02-06 10:22:41 -0800613 return I915_READ(reg);
614}
615
Mario Kleinerad3543e2013-10-30 05:13:08 +0100616/* raw reads, only for fast reads of display block, no need for forcewake etc. */
617#define __raw_i915_read32(dev_priv__, reg__) readl((dev_priv__)->regs + (reg__))
Mario Kleinerad3543e2013-10-30 05:13:08 +0100618
Ville Syrjäläa225f072014-04-29 13:35:45 +0300619static int __intel_get_crtc_scanline(struct intel_crtc *crtc)
620{
621 struct drm_device *dev = crtc->base.dev;
622 struct drm_i915_private *dev_priv = dev->dev_private;
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200623 const struct drm_display_mode *mode = &crtc->config->base.adjusted_mode;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300624 enum pipe pipe = crtc->pipe;
Ville Syrjälä80715b22014-05-15 20:23:23 +0300625 int position, vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300626
Ville Syrjälä80715b22014-05-15 20:23:23 +0300627 vtotal = mode->crtc_vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300628 if (mode->flags & DRM_MODE_FLAG_INTERLACE)
629 vtotal /= 2;
630
631 if (IS_GEN2(dev))
632 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN2;
633 else
634 position = __raw_i915_read32(dev_priv, PIPEDSL(pipe)) & DSL_LINEMASK_GEN3;
635
636 /*
Ville Syrjälä80715b22014-05-15 20:23:23 +0300637 * See update_scanline_offset() for the details on the
638 * scanline_offset adjustment.
Ville Syrjäläa225f072014-04-29 13:35:45 +0300639 */
Ville Syrjälä80715b22014-05-15 20:23:23 +0300640 return (position + crtc->scanline_offset) % vtotal;
Ville Syrjäläa225f072014-04-29 13:35:45 +0300641}
642
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700643static int i915_get_crtc_scanoutpos(struct drm_device *dev, int pipe,
Ville Syrjäläabca9e42013-10-28 20:50:48 +0200644 unsigned int flags, int *vpos, int *hpos,
645 ktime_t *stime, ktime_t *etime)
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100646{
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300647 struct drm_i915_private *dev_priv = dev->dev_private;
648 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[pipe];
649 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200650 const struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300651 int position;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300652 int vbl_start, vbl_end, hsync_start, htotal, vtotal;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100653 bool in_vbl = true;
654 int ret = 0;
Mario Kleinerad3543e2013-10-30 05:13:08 +0100655 unsigned long irqflags;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100656
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300657 if (!intel_crtc->active) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100658 DRM_DEBUG_DRIVER("trying to get scanoutpos for disabled "
Jesse Barnes9db4a9c2011-02-07 12:26:52 -0800659 "pipe %c\n", pipe_name(pipe));
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100660 return 0;
661 }
662
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300663 htotal = mode->crtc_htotal;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300664 hsync_start = mode->crtc_hsync_start;
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300665 vtotal = mode->crtc_vtotal;
666 vbl_start = mode->crtc_vblank_start;
667 vbl_end = mode->crtc_vblank_end;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100668
Ville Syrjäläd31faf62013-10-28 16:31:41 +0200669 if (mode->flags & DRM_MODE_FLAG_INTERLACE) {
670 vbl_start = DIV_ROUND_UP(vbl_start, 2);
671 vbl_end /= 2;
672 vtotal /= 2;
673 }
674
Ville Syrjäläc2baf4b2013-09-23 14:48:50 +0300675 ret |= DRM_SCANOUTPOS_VALID | DRM_SCANOUTPOS_ACCURATE;
676
Mario Kleinerad3543e2013-10-30 05:13:08 +0100677 /*
678 * Lock uncore.lock, as we will do multiple timing critical raw
679 * register reads, potentially with preemption disabled, so the
680 * following code must not block on uncore.lock.
681 */
682 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300683
Mario Kleinerad3543e2013-10-30 05:13:08 +0100684 /* preempt_disable_rt() should go right here in PREEMPT_RT patchset. */
685
686 /* Get optional system timestamp before query. */
687 if (stime)
688 *stime = ktime_get();
689
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300690 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100691 /* No obvious pixelcount register. Only query vertical
692 * scanout position from Display scan line register.
693 */
Ville Syrjäläa225f072014-04-29 13:35:45 +0300694 position = __intel_get_crtc_scanline(intel_crtc);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100695 } else {
696 /* Have access to pixelcount since start of frame.
697 * We can split this into vertical and horizontal
698 * scanout position.
699 */
Mario Kleinerad3543e2013-10-30 05:13:08 +0100700 position = (__raw_i915_read32(dev_priv, PIPEFRAMEPIXEL(pipe)) & PIPE_PIXEL_MASK) >> PIPE_PIXEL_SHIFT;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100701
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300702 /* convert to pixel counts */
703 vbl_start *= htotal;
704 vbl_end *= htotal;
705 vtotal *= htotal;
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300706
707 /*
Ville Syrjälä7e78f1cb2014-04-29 13:35:49 +0300708 * In interlaced modes, the pixel counter counts all pixels,
709 * so one field will have htotal more pixels. In order to avoid
710 * the reported position from jumping backwards when the pixel
711 * counter is beyond the length of the shorter field, just
712 * clamp the position the length of the shorter field. This
713 * matches how the scanline counter based position works since
714 * the scanline counter doesn't count the two half lines.
715 */
716 if (position >= vtotal)
717 position = vtotal - 1;
718
719 /*
Ville Syrjälä78e8fc62014-04-29 13:35:44 +0300720 * Start of vblank interrupt is triggered at start of hsync,
721 * just prior to the first active line of vblank. However we
722 * consider lines to start at the leading edge of horizontal
723 * active. So, should we get here before we've crossed into
724 * the horizontal active of the first line in vblank, we would
725 * not set the DRM_SCANOUTPOS_INVBL flag. In order to fix that,
726 * always add htotal-hsync_start to the current pixel position.
727 */
728 position = (position + htotal - hsync_start) % vtotal;
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300729 }
730
Mario Kleinerad3543e2013-10-30 05:13:08 +0100731 /* Get optional system timestamp after query. */
732 if (etime)
733 *etime = ktime_get();
734
735 /* preempt_enable_rt() should go right here in PREEMPT_RT patchset. */
736
737 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
738
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300739 in_vbl = position >= vbl_start && position < vbl_end;
740
741 /*
742 * While in vblank, position will be negative
743 * counting up towards 0 at vbl_end. And outside
744 * vblank, position will be positive counting
745 * up since vbl_end.
746 */
747 if (position >= vbl_start)
748 position -= vbl_end;
749 else
750 position += vtotal - vbl_end;
751
Ville Syrjälä7c06b082013-10-11 21:52:43 +0300752 if (IS_GEN2(dev) || IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
Ville Syrjälä3aa18df2013-10-11 19:10:32 +0300753 *vpos = position;
754 *hpos = 0;
755 } else {
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100756 *vpos = position / htotal;
757 *hpos = position - (*vpos * htotal);
758 }
759
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100760 /* In vblank? */
761 if (in_vbl)
Daniel Vetter3d3cbd82014-09-10 17:36:11 +0200762 ret |= DRM_SCANOUTPOS_IN_VBLANK;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100763
764 return ret;
765}
766
Ville Syrjäläa225f072014-04-29 13:35:45 +0300767int intel_get_crtc_scanline(struct intel_crtc *crtc)
768{
769 struct drm_i915_private *dev_priv = crtc->base.dev->dev_private;
770 unsigned long irqflags;
771 int position;
772
773 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
774 position = __intel_get_crtc_scanline(crtc);
775 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
776
777 return position;
778}
779
Jesse Barnesf71d4af2011-06-28 13:00:41 -0700780static int i915_get_vblank_timestamp(struct drm_device *dev, int pipe,
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100781 int *max_error,
782 struct timeval *vblank_time,
783 unsigned flags)
784{
Chris Wilson4041b852011-01-22 10:07:56 +0000785 struct drm_crtc *crtc;
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100786
Ben Widawsky7eb552a2013-03-13 14:05:41 -0700787 if (pipe < 0 || pipe >= INTEL_INFO(dev)->num_pipes) {
Chris Wilson4041b852011-01-22 10:07:56 +0000788 DRM_ERROR("Invalid crtc %d\n", pipe);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100789 return -EINVAL;
790 }
791
792 /* Get drm_crtc to timestamp: */
Chris Wilson4041b852011-01-22 10:07:56 +0000793 crtc = intel_get_crtc_for_pipe(dev, pipe);
794 if (crtc == NULL) {
795 DRM_ERROR("Invalid crtc %d\n", pipe);
796 return -EINVAL;
797 }
798
Matt Roper83d65732015-02-25 13:12:16 -0800799 if (!crtc->state->enable) {
Chris Wilson4041b852011-01-22 10:07:56 +0000800 DRM_DEBUG_KMS("crtc %d is disabled\n", pipe);
801 return -EBUSY;
802 }
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100803
804 /* Helper routine in DRM core does all the work: */
Chris Wilson4041b852011-01-22 10:07:56 +0000805 return drm_calc_vbltimestamp_from_scanoutpos(dev, pipe, max_error,
806 vblank_time, flags,
Ville Syrjälä7da903e2013-10-26 17:57:31 +0300807 crtc,
Ander Conselvan de Oliveira6e3c9712015-01-15 14:55:25 +0200808 &to_intel_crtc(crtc)->config->base.adjusted_mode);
Mario Kleiner0af7e4d2010-12-08 04:07:19 +0100809}
810
Jani Nikula67c347f2013-09-17 14:26:34 +0300811static bool intel_hpd_irq_event(struct drm_device *dev,
812 struct drm_connector *connector)
Egbert Eich321a1b32013-04-11 16:00:26 +0200813{
814 enum drm_connector_status old_status;
815
816 WARN_ON(!mutex_is_locked(&dev->mode_config.mutex));
817 old_status = connector->status;
818
819 connector->status = connector->funcs->detect(connector, false);
Jani Nikula67c347f2013-09-17 14:26:34 +0300820 if (old_status == connector->status)
821 return false;
822
823 DRM_DEBUG_KMS("[CONNECTOR:%d:%s] status updated from %s to %s\n",
Egbert Eich321a1b32013-04-11 16:00:26 +0200824 connector->base.id,
Jani Nikulac23cc412014-06-03 14:56:17 +0300825 connector->name,
Jani Nikula67c347f2013-09-17 14:26:34 +0300826 drm_get_connector_status_name(old_status),
827 drm_get_connector_status_name(connector->status));
828
829 return true;
Egbert Eich321a1b32013-04-11 16:00:26 +0200830}
831
Dave Airlie13cf5502014-06-18 11:29:35 +1000832static void i915_digport_work_func(struct work_struct *work)
833{
834 struct drm_i915_private *dev_priv =
835 container_of(work, struct drm_i915_private, dig_port_work);
Dave Airlie13cf5502014-06-18 11:29:35 +1000836 u32 long_port_mask, short_port_mask;
837 struct intel_digital_port *intel_dig_port;
Daniel Vetterb2c5c182015-01-23 06:00:31 +0100838 int i;
Dave Airlie13cf5502014-06-18 11:29:35 +1000839 u32 old_bits = 0;
840
Daniel Vetter4cb21832014-09-15 14:55:26 +0200841 spin_lock_irq(&dev_priv->irq_lock);
Dave Airlie13cf5502014-06-18 11:29:35 +1000842 long_port_mask = dev_priv->long_hpd_port_mask;
843 dev_priv->long_hpd_port_mask = 0;
844 short_port_mask = dev_priv->short_hpd_port_mask;
845 dev_priv->short_hpd_port_mask = 0;
Daniel Vetter4cb21832014-09-15 14:55:26 +0200846 spin_unlock_irq(&dev_priv->irq_lock);
Dave Airlie13cf5502014-06-18 11:29:35 +1000847
848 for (i = 0; i < I915_MAX_PORTS; i++) {
849 bool valid = false;
850 bool long_hpd = false;
851 intel_dig_port = dev_priv->hpd_irq_port[i];
852 if (!intel_dig_port || !intel_dig_port->hpd_pulse)
853 continue;
854
855 if (long_port_mask & (1 << i)) {
856 valid = true;
857 long_hpd = true;
858 } else if (short_port_mask & (1 << i))
859 valid = true;
860
861 if (valid) {
Daniel Vetterb2c5c182015-01-23 06:00:31 +0100862 enum irqreturn ret;
863
Dave Airlie13cf5502014-06-18 11:29:35 +1000864 ret = intel_dig_port->hpd_pulse(intel_dig_port, long_hpd);
Daniel Vetterb2c5c182015-01-23 06:00:31 +0100865 if (ret == IRQ_NONE) {
866 /* fall back to old school hpd */
Dave Airlie13cf5502014-06-18 11:29:35 +1000867 old_bits |= (1 << intel_dig_port->base.hpd_pin);
868 }
869 }
870 }
871
872 if (old_bits) {
Daniel Vetter4cb21832014-09-15 14:55:26 +0200873 spin_lock_irq(&dev_priv->irq_lock);
Dave Airlie13cf5502014-06-18 11:29:35 +1000874 dev_priv->hpd_event_bits |= old_bits;
Daniel Vetter4cb21832014-09-15 14:55:26 +0200875 spin_unlock_irq(&dev_priv->irq_lock);
Dave Airlie13cf5502014-06-18 11:29:35 +1000876 schedule_work(&dev_priv->hotplug_work);
877 }
878}
879
Jesse Barnes5ca58282009-03-31 14:11:15 -0700880/*
881 * Handle hotplug events outside the interrupt handler proper.
882 */
Egbert Eichac4c16c2013-04-16 13:36:58 +0200883#define I915_REENABLE_HOTPLUG_DELAY (2*60*1000)
884
Jesse Barnes5ca58282009-03-31 14:11:15 -0700885static void i915_hotplug_work_func(struct work_struct *work)
886{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300887 struct drm_i915_private *dev_priv =
888 container_of(work, struct drm_i915_private, hotplug_work);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700889 struct drm_device *dev = dev_priv->dev;
Keith Packardc31c4ba2009-05-06 11:48:58 -0700890 struct drm_mode_config *mode_config = &dev->mode_config;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200891 struct intel_connector *intel_connector;
892 struct intel_encoder *intel_encoder;
893 struct drm_connector *connector;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200894 bool hpd_disabled = false;
Egbert Eich321a1b32013-04-11 16:00:26 +0200895 bool changed = false;
Egbert Eich142e2392013-04-11 15:57:57 +0200896 u32 hpd_event_bits;
Jesse Barnes5ca58282009-03-31 14:11:15 -0700897
Keith Packarda65e34c2011-07-25 10:04:56 -0700898 mutex_lock(&mode_config->mutex);
Jesse Barnese67189ab2011-02-11 14:44:51 -0800899 DRM_DEBUG_KMS("running encoder hotplug functions\n");
900
Daniel Vetter4cb21832014-09-15 14:55:26 +0200901 spin_lock_irq(&dev_priv->irq_lock);
Egbert Eich142e2392013-04-11 15:57:57 +0200902
903 hpd_event_bits = dev_priv->hpd_event_bits;
904 dev_priv->hpd_event_bits = 0;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200905 list_for_each_entry(connector, &mode_config->connector_list, head) {
906 intel_connector = to_intel_connector(connector);
Dave Airlie36cd7442014-05-02 13:44:18 +1000907 if (!intel_connector->encoder)
908 continue;
Egbert Eichcd569ae2013-04-16 13:36:57 +0200909 intel_encoder = intel_connector->encoder;
910 if (intel_encoder->hpd_pin > HPD_NONE &&
911 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_MARK_DISABLED &&
912 connector->polled == DRM_CONNECTOR_POLL_HPD) {
913 DRM_INFO("HPD interrupt storm detected on connector %s: "
914 "switching from hotplug detection to polling\n",
Jani Nikulac23cc412014-06-03 14:56:17 +0300915 connector->name);
Egbert Eichcd569ae2013-04-16 13:36:57 +0200916 dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark = HPD_DISABLED;
917 connector->polled = DRM_CONNECTOR_POLL_CONNECT
918 | DRM_CONNECTOR_POLL_DISCONNECT;
919 hpd_disabled = true;
920 }
Egbert Eich142e2392013-04-11 15:57:57 +0200921 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
922 DRM_DEBUG_KMS("Connector %s (pin %i) received hotplug event.\n",
Jani Nikulac23cc412014-06-03 14:56:17 +0300923 connector->name, intel_encoder->hpd_pin);
Egbert Eich142e2392013-04-11 15:57:57 +0200924 }
Egbert Eichcd569ae2013-04-16 13:36:57 +0200925 }
926 /* if there were no outputs to poll, poll was disabled,
927 * therefore make sure it's enabled when disabling HPD on
928 * some connectors */
Egbert Eichac4c16c2013-04-16 13:36:58 +0200929 if (hpd_disabled) {
Egbert Eichcd569ae2013-04-16 13:36:57 +0200930 drm_kms_helper_poll_enable(dev);
Imre Deak63237512014-08-18 15:37:02 +0300931 mod_delayed_work(system_wq, &dev_priv->hotplug_reenable_work,
932 msecs_to_jiffies(I915_REENABLE_HOTPLUG_DELAY));
Egbert Eichac4c16c2013-04-16 13:36:58 +0200933 }
Egbert Eichcd569ae2013-04-16 13:36:57 +0200934
Daniel Vetter4cb21832014-09-15 14:55:26 +0200935 spin_unlock_irq(&dev_priv->irq_lock);
Egbert Eichcd569ae2013-04-16 13:36:57 +0200936
Egbert Eich321a1b32013-04-11 16:00:26 +0200937 list_for_each_entry(connector, &mode_config->connector_list, head) {
938 intel_connector = to_intel_connector(connector);
Dave Airlie36cd7442014-05-02 13:44:18 +1000939 if (!intel_connector->encoder)
940 continue;
Egbert Eich321a1b32013-04-11 16:00:26 +0200941 intel_encoder = intel_connector->encoder;
942 if (hpd_event_bits & (1 << intel_encoder->hpd_pin)) {
943 if (intel_encoder->hot_plug)
944 intel_encoder->hot_plug(intel_encoder);
945 if (intel_hpd_irq_event(dev, connector))
946 changed = true;
947 }
948 }
Keith Packard40ee3382011-07-28 15:31:19 -0700949 mutex_unlock(&mode_config->mutex);
950
Egbert Eich321a1b32013-04-11 16:00:26 +0200951 if (changed)
952 drm_kms_helper_hotplug_event(dev);
Jesse Barnes5ca58282009-03-31 14:11:15 -0700953}
954
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200955static void ironlake_rps_change_irq_handler(struct drm_device *dev)
Jesse Barnesf97108d2010-01-29 11:27:07 -0800956{
Jani Nikula2d1013d2014-03-31 14:27:17 +0300957 struct drm_i915_private *dev_priv = dev->dev_private;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000958 u32 busy_up, busy_down, max_avg, min_avg;
Daniel Vetter92703882012-08-09 16:46:01 +0200959 u8 new_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200960
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200961 spin_lock(&mchdev_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800962
Daniel Vetter73edd18f2012-08-08 23:35:37 +0200963 I915_WRITE16(MEMINTRSTS, I915_READ(MEMINTRSTS));
964
Daniel Vetter20e4d402012-08-08 23:35:39 +0200965 new_delay = dev_priv->ips.cur_delay;
Daniel Vetter92703882012-08-09 16:46:01 +0200966
Jesse Barnes7648fa92010-05-20 14:28:11 -0700967 I915_WRITE16(MEMINTRSTS, MEMINT_EVAL_CHG);
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000968 busy_up = I915_READ(RCPREVBSYTUPAVG);
969 busy_down = I915_READ(RCPREVBSYTDNAVG);
Jesse Barnesf97108d2010-01-29 11:27:07 -0800970 max_avg = I915_READ(RCBMAXAVG);
971 min_avg = I915_READ(RCBMINAVG);
972
973 /* Handle RCS change request from hw */
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000974 if (busy_up > max_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200975 if (dev_priv->ips.cur_delay != dev_priv->ips.max_delay)
976 new_delay = dev_priv->ips.cur_delay - 1;
977 if (new_delay < dev_priv->ips.max_delay)
978 new_delay = dev_priv->ips.max_delay;
Matthew Garrettb5b72e82010-02-02 18:30:47 +0000979 } else if (busy_down < min_avg) {
Daniel Vetter20e4d402012-08-08 23:35:39 +0200980 if (dev_priv->ips.cur_delay != dev_priv->ips.min_delay)
981 new_delay = dev_priv->ips.cur_delay + 1;
982 if (new_delay > dev_priv->ips.min_delay)
983 new_delay = dev_priv->ips.min_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800984 }
985
Jesse Barnes7648fa92010-05-20 14:28:11 -0700986 if (ironlake_set_drps(dev, new_delay))
Daniel Vetter20e4d402012-08-08 23:35:39 +0200987 dev_priv->ips.cur_delay = new_delay;
Jesse Barnesf97108d2010-01-29 11:27:07 -0800988
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +0200989 spin_unlock(&mchdev_lock);
Daniel Vetter92703882012-08-09 16:46:01 +0200990
Jesse Barnesf97108d2010-01-29 11:27:07 -0800991 return;
992}
993
Chris Wilson74cdb332015-04-07 16:21:05 +0100994static void notify_ring(struct intel_engine_cs *ring)
Chris Wilson549f7362010-10-19 11:19:32 +0100995{
Oscar Mateo93b0a4e2014-05-22 14:13:36 +0100996 if (!intel_ring_initialized(ring))
Chris Wilson475553d2011-01-20 09:52:56 +0000997 return;
998
John Harrisonbcfcc8b2014-12-05 13:49:36 +0000999 trace_i915_gem_request_notify(ring);
Chris Wilson9862e602011-01-04 22:22:17 +00001000
Chris Wilson549f7362010-10-19 11:19:32 +01001001 wake_up_all(&ring->irq_queue);
Chris Wilson549f7362010-10-19 11:19:32 +01001002}
1003
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001004static void vlv_c0_read(struct drm_i915_private *dev_priv,
1005 struct intel_rps_ei *ei)
Deepak S31685c22014-07-03 17:33:01 -04001006{
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001007 ei->cz_clock = vlv_punit_read(dev_priv, PUNIT_REG_CZ_TIMESTAMP);
1008 ei->render_c0 = I915_READ(VLV_RENDER_C0_COUNT);
1009 ei->media_c0 = I915_READ(VLV_MEDIA_C0_COUNT);
Deepak S31685c22014-07-03 17:33:01 -04001010}
1011
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001012static bool vlv_c0_above(struct drm_i915_private *dev_priv,
1013 const struct intel_rps_ei *old,
1014 const struct intel_rps_ei *now,
1015 int threshold)
Deepak S31685c22014-07-03 17:33:01 -04001016{
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001017 u64 time, c0;
Deepak S31685c22014-07-03 17:33:01 -04001018
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001019 if (old->cz_clock == 0)
1020 return false;
Deepak S31685c22014-07-03 17:33:01 -04001021
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001022 time = now->cz_clock - old->cz_clock;
1023 time *= threshold * dev_priv->mem_freq;
Deepak S31685c22014-07-03 17:33:01 -04001024
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001025 /* Workload can be split between render + media, e.g. SwapBuffers
1026 * being blitted in X after being rendered in mesa. To account for
1027 * this we need to combine both engines into our activity counter.
1028 */
1029 c0 = now->render_c0 - old->render_c0;
1030 c0 += now->media_c0 - old->media_c0;
1031 c0 *= 100 * VLV_CZ_CLOCK_TO_MILLI_SEC * 4 / 1000;
Deepak S31685c22014-07-03 17:33:01 -04001032
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001033 return c0 >= time;
1034}
Deepak S31685c22014-07-03 17:33:01 -04001035
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001036void gen6_rps_reset_ei(struct drm_i915_private *dev_priv)
1037{
1038 vlv_c0_read(dev_priv, &dev_priv->rps.down_ei);
1039 dev_priv->rps.up_ei = dev_priv->rps.down_ei;
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001040}
1041
1042static u32 vlv_wa_c0_ei(struct drm_i915_private *dev_priv, u32 pm_iir)
1043{
1044 struct intel_rps_ei now;
1045 u32 events = 0;
1046
Chris Wilson6f4b12f82015-03-18 09:48:23 +00001047 if ((pm_iir & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED)) == 0)
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001048 return 0;
1049
1050 vlv_c0_read(dev_priv, &now);
1051 if (now.cz_clock == 0)
1052 return 0;
Deepak S31685c22014-07-03 17:33:01 -04001053
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001054 if (pm_iir & GEN6_PM_RP_DOWN_EI_EXPIRED) {
1055 if (!vlv_c0_above(dev_priv,
1056 &dev_priv->rps.down_ei, &now,
Chris Wilson8fb55192015-04-07 16:20:28 +01001057 dev_priv->rps.down_threshold))
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001058 events |= GEN6_PM_RP_DOWN_THRESHOLD;
1059 dev_priv->rps.down_ei = now;
Deepak S31685c22014-07-03 17:33:01 -04001060 }
1061
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001062 if (pm_iir & GEN6_PM_RP_UP_EI_EXPIRED) {
1063 if (vlv_c0_above(dev_priv,
1064 &dev_priv->rps.up_ei, &now,
Chris Wilson8fb55192015-04-07 16:20:28 +01001065 dev_priv->rps.up_threshold))
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001066 events |= GEN6_PM_RP_UP_THRESHOLD;
1067 dev_priv->rps.up_ei = now;
1068 }
1069
1070 return events;
Deepak S31685c22014-07-03 17:33:01 -04001071}
1072
Chris Wilsonf5a4c672015-04-27 13:41:23 +01001073static bool any_waiters(struct drm_i915_private *dev_priv)
1074{
1075 struct intel_engine_cs *ring;
1076 int i;
1077
1078 for_each_ring(ring, dev_priv, i)
1079 if (ring->irq_refcount)
1080 return true;
1081
1082 return false;
1083}
1084
Ben Widawsky4912d042011-04-25 11:25:20 -07001085static void gen6_pm_rps_work(struct work_struct *work)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001086{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001087 struct drm_i915_private *dev_priv =
1088 container_of(work, struct drm_i915_private, rps.work);
Chris Wilson8d3afd72015-05-21 21:01:47 +01001089 bool client_boost;
1090 int new_delay, adj, min, max;
Paulo Zanoniedbfdb42013-08-06 18:57:13 -03001091 u32 pm_iir;
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001092
Daniel Vetter59cdb632013-07-04 23:35:28 +02001093 spin_lock_irq(&dev_priv->irq_lock);
Imre Deakd4d70aa2014-11-19 15:30:04 +02001094 /* Speed up work cancelation during disabling rps interrupts. */
1095 if (!dev_priv->rps.interrupts_enabled) {
1096 spin_unlock_irq(&dev_priv->irq_lock);
1097 return;
1098 }
Daniel Vetterc6a828d2012-08-08 23:35:35 +02001099 pm_iir = dev_priv->rps.pm_iir;
1100 dev_priv->rps.pm_iir = 0;
Imre Deaka72fbc32014-11-05 20:48:31 +02001101 /* Make sure not to corrupt PMIMR state used by ringbuffer on GEN6 */
1102 gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events);
Chris Wilson8d3afd72015-05-21 21:01:47 +01001103 client_boost = dev_priv->rps.client_boost;
1104 dev_priv->rps.client_boost = false;
Daniel Vetter59cdb632013-07-04 23:35:28 +02001105 spin_unlock_irq(&dev_priv->irq_lock);
Ben Widawsky4912d042011-04-25 11:25:20 -07001106
Paulo Zanoni60611c12013-08-15 11:50:01 -03001107 /* Make sure we didn't queue anything we're not going to process. */
Deepak Sa6706b42014-03-15 20:23:22 +05301108 WARN_ON(pm_iir & ~dev_priv->pm_rps_events);
Paulo Zanoni60611c12013-08-15 11:50:01 -03001109
Chris Wilson8d3afd72015-05-21 21:01:47 +01001110 if ((pm_iir & dev_priv->pm_rps_events) == 0 && !client_boost)
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001111 return;
1112
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001113 mutex_lock(&dev_priv->rps.hw_lock);
Chris Wilson7b9e0ae2012-04-28 08:56:39 +01001114
Chris Wilson43cf3bf2015-03-18 09:48:22 +00001115 pm_iir |= vlv_wa_c0_ei(dev_priv, pm_iir);
1116
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001117 adj = dev_priv->rps.last_adj;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001118 new_delay = dev_priv->rps.cur_freq;
Chris Wilson8d3afd72015-05-21 21:01:47 +01001119 min = dev_priv->rps.min_freq_softlimit;
1120 max = dev_priv->rps.max_freq_softlimit;
1121
1122 if (client_boost) {
1123 new_delay = dev_priv->rps.max_freq_softlimit;
1124 adj = 0;
1125 } else if (pm_iir & GEN6_PM_RP_UP_THRESHOLD) {
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001126 if (adj > 0)
1127 adj *= 2;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001128 else /* CHV needs even encode values */
1129 adj = IS_CHERRYVIEW(dev_priv) ? 2 : 1;
Ville Syrjälä74250342013-06-25 21:38:11 +03001130 /*
1131 * For better performance, jump directly
1132 * to RPe if we're below it.
1133 */
Chris Wilsonedcf2842015-04-07 16:20:29 +01001134 if (new_delay < dev_priv->rps.efficient_freq - adj) {
Ben Widawskyb39fb292014-03-19 18:31:11 -07001135 new_delay = dev_priv->rps.efficient_freq;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001136 adj = 0;
1137 }
Chris Wilsonf5a4c672015-04-27 13:41:23 +01001138 } else if (any_waiters(dev_priv)) {
1139 adj = 0;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001140 } else if (pm_iir & GEN6_PM_RP_DOWN_TIMEOUT) {
Ben Widawskyb39fb292014-03-19 18:31:11 -07001141 if (dev_priv->rps.cur_freq > dev_priv->rps.efficient_freq)
1142 new_delay = dev_priv->rps.efficient_freq;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001143 else
Ben Widawskyb39fb292014-03-19 18:31:11 -07001144 new_delay = dev_priv->rps.min_freq_softlimit;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001145 adj = 0;
1146 } else if (pm_iir & GEN6_PM_RP_DOWN_THRESHOLD) {
1147 if (adj < 0)
1148 adj *= 2;
Chris Wilsonedcf2842015-04-07 16:20:29 +01001149 else /* CHV needs even encode values */
1150 adj = IS_CHERRYVIEW(dev_priv) ? -2 : -1;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001151 } else { /* unknown event */
Chris Wilsonedcf2842015-04-07 16:20:29 +01001152 adj = 0;
Chris Wilsondd75fdc2013-09-25 17:34:57 +01001153 }
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001154
Chris Wilsonedcf2842015-04-07 16:20:29 +01001155 dev_priv->rps.last_adj = adj;
1156
Ben Widawsky79249632012-09-07 19:43:42 -07001157 /* sysfs frequency interfaces may have snuck in while servicing the
1158 * interrupt
1159 */
Chris Wilsonedcf2842015-04-07 16:20:29 +01001160 new_delay += adj;
Chris Wilson8d3afd72015-05-21 21:01:47 +01001161 new_delay = clamp_t(int, new_delay, min, max);
Deepak S27544362014-01-27 21:35:05 +05301162
Ville Syrjäläffe02b42015-02-02 19:09:50 +02001163 intel_set_rps(dev_priv->dev, new_delay);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001164
Jesse Barnes4fc688c2012-11-02 11:14:01 -07001165 mutex_unlock(&dev_priv->rps.hw_lock);
Jesse Barnes3b8d8d92010-12-17 14:19:02 -08001166}
1167
Ben Widawskye3689192012-05-25 16:56:22 -07001168
1169/**
1170 * ivybridge_parity_work - Workqueue called when a parity error interrupt
1171 * occurred.
1172 * @work: workqueue struct
1173 *
1174 * Doesn't actually do anything except notify userspace. As a consequence of
1175 * this event, userspace should try to remap the bad rows since statistically
1176 * it is likely the same row is more likely to go bad again.
1177 */
1178static void ivybridge_parity_work(struct work_struct *work)
1179{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001180 struct drm_i915_private *dev_priv =
1181 container_of(work, struct drm_i915_private, l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -07001182 u32 error_status, row, bank, subbank;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001183 char *parity_event[6];
Ben Widawskye3689192012-05-25 16:56:22 -07001184 uint32_t misccpctl;
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001185 uint8_t slice = 0;
Ben Widawskye3689192012-05-25 16:56:22 -07001186
1187 /* We must turn off DOP level clock gating to access the L3 registers.
1188 * In order to prevent a get/put style interface, acquire struct mutex
1189 * any time we access those registers.
1190 */
1191 mutex_lock(&dev_priv->dev->struct_mutex);
1192
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001193 /* If we've screwed up tracking, just let the interrupt fire again */
1194 if (WARN_ON(!dev_priv->l3_parity.which_slice))
1195 goto out;
1196
Ben Widawskye3689192012-05-25 16:56:22 -07001197 misccpctl = I915_READ(GEN7_MISCCPCTL);
1198 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
1199 POSTING_READ(GEN7_MISCCPCTL);
1200
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001201 while ((slice = ffs(dev_priv->l3_parity.which_slice)) != 0) {
1202 u32 reg;
Ben Widawskye3689192012-05-25 16:56:22 -07001203
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001204 slice--;
1205 if (WARN_ON_ONCE(slice >= NUM_L3_SLICES(dev_priv->dev)))
1206 break;
1207
1208 dev_priv->l3_parity.which_slice &= ~(1<<slice);
1209
1210 reg = GEN7_L3CDERRST1 + (slice * 0x200);
1211
1212 error_status = I915_READ(reg);
1213 row = GEN7_PARITY_ERROR_ROW(error_status);
1214 bank = GEN7_PARITY_ERROR_BANK(error_status);
1215 subbank = GEN7_PARITY_ERROR_SUBBANK(error_status);
1216
1217 I915_WRITE(reg, GEN7_PARITY_ERROR_VALID | GEN7_L3CDERRST1_ENABLE);
1218 POSTING_READ(reg);
1219
1220 parity_event[0] = I915_L3_PARITY_UEVENT "=1";
1221 parity_event[1] = kasprintf(GFP_KERNEL, "ROW=%d", row);
1222 parity_event[2] = kasprintf(GFP_KERNEL, "BANK=%d", bank);
1223 parity_event[3] = kasprintf(GFP_KERNEL, "SUBBANK=%d", subbank);
1224 parity_event[4] = kasprintf(GFP_KERNEL, "SLICE=%d", slice);
1225 parity_event[5] = NULL;
1226
Dave Airlie5bdebb12013-10-11 14:07:25 +10001227 kobject_uevent_env(&dev_priv->dev->primary->kdev->kobj,
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001228 KOBJ_CHANGE, parity_event);
1229
1230 DRM_DEBUG("Parity error: Slice = %d, Row = %d, Bank = %d, Sub bank = %d.\n",
1231 slice, row, bank, subbank);
1232
1233 kfree(parity_event[4]);
1234 kfree(parity_event[3]);
1235 kfree(parity_event[2]);
1236 kfree(parity_event[1]);
1237 }
Ben Widawskye3689192012-05-25 16:56:22 -07001238
1239 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
1240
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001241out:
1242 WARN_ON(dev_priv->l3_parity.which_slice);
Daniel Vetter4cb21832014-09-15 14:55:26 +02001243 spin_lock_irq(&dev_priv->irq_lock);
Daniel Vetter480c8032014-07-16 09:49:40 +02001244 gen5_enable_gt_irq(dev_priv, GT_PARITY_ERROR(dev_priv->dev));
Daniel Vetter4cb21832014-09-15 14:55:26 +02001245 spin_unlock_irq(&dev_priv->irq_lock);
Ben Widawskye3689192012-05-25 16:56:22 -07001246
1247 mutex_unlock(&dev_priv->dev->struct_mutex);
Ben Widawskye3689192012-05-25 16:56:22 -07001248}
1249
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001250static void ivybridge_parity_error_irq_handler(struct drm_device *dev, u32 iir)
Ben Widawskye3689192012-05-25 16:56:22 -07001251{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001252 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskye3689192012-05-25 16:56:22 -07001253
Ben Widawsky040d2ba2013-09-19 11:01:40 -07001254 if (!HAS_L3_DPF(dev))
Ben Widawskye3689192012-05-25 16:56:22 -07001255 return;
1256
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001257 spin_lock(&dev_priv->irq_lock);
Daniel Vetter480c8032014-07-16 09:49:40 +02001258 gen5_disable_gt_irq(dev_priv, GT_PARITY_ERROR(dev));
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001259 spin_unlock(&dev_priv->irq_lock);
Ben Widawskye3689192012-05-25 16:56:22 -07001260
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001261 iir &= GT_PARITY_ERROR(dev);
1262 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT_S1)
1263 dev_priv->l3_parity.which_slice |= 1 << 1;
1264
1265 if (iir & GT_RENDER_L3_PARITY_ERROR_INTERRUPT)
1266 dev_priv->l3_parity.which_slice |= 1 << 0;
1267
Daniel Vettera4da4fa2012-11-02 19:55:07 +01001268 queue_work(dev_priv->wq, &dev_priv->l3_parity.error_work);
Ben Widawskye3689192012-05-25 16:56:22 -07001269}
1270
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001271static void ilk_gt_irq_handler(struct drm_device *dev,
1272 struct drm_i915_private *dev_priv,
1273 u32 gt_iir)
1274{
1275 if (gt_iir &
1276 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001277 notify_ring(&dev_priv->ring[RCS]);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001278 if (gt_iir & ILK_BSD_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01001279 notify_ring(&dev_priv->ring[VCS]);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03001280}
1281
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001282static void snb_gt_irq_handler(struct drm_device *dev,
1283 struct drm_i915_private *dev_priv,
1284 u32 gt_iir)
1285{
1286
Ben Widawskycc609d52013-05-28 19:22:29 -07001287 if (gt_iir &
1288 (GT_RENDER_USER_INTERRUPT | GT_RENDER_PIPECTL_NOTIFY_INTERRUPT))
Chris Wilson74cdb332015-04-07 16:21:05 +01001289 notify_ring(&dev_priv->ring[RCS]);
Ben Widawskycc609d52013-05-28 19:22:29 -07001290 if (gt_iir & GT_BSD_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01001291 notify_ring(&dev_priv->ring[VCS]);
Ben Widawskycc609d52013-05-28 19:22:29 -07001292 if (gt_iir & GT_BLT_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01001293 notify_ring(&dev_priv->ring[BCS]);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001294
Ben Widawskycc609d52013-05-28 19:22:29 -07001295 if (gt_iir & (GT_BLT_CS_ERROR_INTERRUPT |
1296 GT_BSD_CS_ERROR_INTERRUPT |
Daniel Vetteraaecdf62014-11-04 15:52:22 +01001297 GT_RENDER_CS_MASTER_ERROR_INTERRUPT))
1298 DRM_DEBUG("Command parser error, gt_iir 0x%08x\n", gt_iir);
Ben Widawskye3689192012-05-25 16:56:22 -07001299
Ben Widawsky35a85ac2013-09-19 11:13:41 -07001300 if (gt_iir & GT_PARITY_ERROR(dev))
1301 ivybridge_parity_error_irq_handler(dev, gt_iir);
Daniel Vettere7b4c6b2012-03-30 20:24:35 +02001302}
1303
Chris Wilson74cdb332015-04-07 16:21:05 +01001304static irqreturn_t gen8_gt_irq_handler(struct drm_i915_private *dev_priv,
Ben Widawskyabd58f02013-11-02 21:07:09 -07001305 u32 master_ctl)
1306{
Ben Widawskyabd58f02013-11-02 21:07:09 -07001307 irqreturn_t ret = IRQ_NONE;
1308
1309 if (master_ctl & (GEN8_GT_RCS_IRQ | GEN8_GT_BCS_IRQ)) {
Chris Wilson74cdb332015-04-07 16:21:05 +01001310 u32 tmp = I915_READ_FW(GEN8_GT_IIR(0));
Ben Widawskyabd58f02013-11-02 21:07:09 -07001311 if (tmp) {
Chris Wilsoncb0d2052015-04-07 16:21:04 +01001312 I915_WRITE_FW(GEN8_GT_IIR(0), tmp);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001313 ret = IRQ_HANDLED;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001314
Chris Wilson74cdb332015-04-07 16:21:05 +01001315 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1316 intel_lrc_irq_handler(&dev_priv->ring[RCS]);
1317 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT))
1318 notify_ring(&dev_priv->ring[RCS]);
Thomas Daniele981e7b2014-07-24 17:04:39 +01001319
Chris Wilson74cdb332015-04-07 16:21:05 +01001320 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1321 intel_lrc_irq_handler(&dev_priv->ring[BCS]);
1322 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT))
1323 notify_ring(&dev_priv->ring[BCS]);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001324 } else
1325 DRM_ERROR("The master control interrupt lied (GT0)!\n");
1326 }
1327
Zhao Yakui85f9b5f2014-04-17 10:37:38 +08001328 if (master_ctl & (GEN8_GT_VCS1_IRQ | GEN8_GT_VCS2_IRQ)) {
Chris Wilson74cdb332015-04-07 16:21:05 +01001329 u32 tmp = I915_READ_FW(GEN8_GT_IIR(1));
Ben Widawskyabd58f02013-11-02 21:07:09 -07001330 if (tmp) {
Chris Wilsoncb0d2052015-04-07 16:21:04 +01001331 I915_WRITE_FW(GEN8_GT_IIR(1), tmp);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001332 ret = IRQ_HANDLED;
Thomas Daniele981e7b2014-07-24 17:04:39 +01001333
Chris Wilson74cdb332015-04-07 16:21:05 +01001334 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1335 intel_lrc_irq_handler(&dev_priv->ring[VCS]);
1336 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT))
1337 notify_ring(&dev_priv->ring[VCS]);
Thomas Daniele981e7b2014-07-24 17:04:39 +01001338
Chris Wilson74cdb332015-04-07 16:21:05 +01001339 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1340 intel_lrc_irq_handler(&dev_priv->ring[VCS2]);
1341 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT))
1342 notify_ring(&dev_priv->ring[VCS2]);
Ben Widawskyabd58f02013-11-02 21:07:09 -07001343 } else
1344 DRM_ERROR("The master control interrupt lied (GT1)!\n");
1345 }
1346
Chris Wilson74cdb332015-04-07 16:21:05 +01001347 if (master_ctl & GEN8_GT_VECS_IRQ) {
1348 u32 tmp = I915_READ_FW(GEN8_GT_IIR(3));
1349 if (tmp) {
1350 I915_WRITE_FW(GEN8_GT_IIR(3), tmp);
1351 ret = IRQ_HANDLED;
1352
1353 if (tmp & (GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1354 intel_lrc_irq_handler(&dev_priv->ring[VECS]);
1355 if (tmp & (GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT))
1356 notify_ring(&dev_priv->ring[VECS]);
1357 } else
1358 DRM_ERROR("The master control interrupt lied (GT3)!\n");
1359 }
1360
Ben Widawsky09610212014-05-15 20:58:08 +03001361 if (master_ctl & GEN8_GT_PM_IRQ) {
Chris Wilson74cdb332015-04-07 16:21:05 +01001362 u32 tmp = I915_READ_FW(GEN8_GT_IIR(2));
Ben Widawsky09610212014-05-15 20:58:08 +03001363 if (tmp & dev_priv->pm_rps_events) {
Chris Wilsoncb0d2052015-04-07 16:21:04 +01001364 I915_WRITE_FW(GEN8_GT_IIR(2),
1365 tmp & dev_priv->pm_rps_events);
Oscar Mateo38cc46d2014-06-16 16:10:59 +01001366 ret = IRQ_HANDLED;
Imre Deakc9a9a262014-11-05 20:48:37 +02001367 gen6_rps_irq_handler(dev_priv, tmp);
Ben Widawsky09610212014-05-15 20:58:08 +03001368 } else
1369 DRM_ERROR("The master control interrupt lied (PM)!\n");
1370 }
1371
Ben Widawskyabd58f02013-11-02 21:07:09 -07001372 return ret;
1373}
1374
Egbert Eichb543fb02013-04-16 13:36:54 +02001375#define HPD_STORM_DETECT_PERIOD 1000
1376#define HPD_STORM_THRESHOLD 5
1377
Jani Nikula07c338c2014-10-02 11:16:32 +03001378static int pch_port_to_hotplug_shift(enum port port)
Dave Airlie13cf5502014-06-18 11:29:35 +10001379{
1380 switch (port) {
1381 case PORT_A:
1382 case PORT_E:
1383 default:
1384 return -1;
1385 case PORT_B:
1386 return 0;
1387 case PORT_C:
1388 return 8;
1389 case PORT_D:
1390 return 16;
1391 }
1392}
1393
Jani Nikula07c338c2014-10-02 11:16:32 +03001394static int i915_port_to_hotplug_shift(enum port port)
Dave Airlie13cf5502014-06-18 11:29:35 +10001395{
1396 switch (port) {
1397 case PORT_A:
1398 case PORT_E:
1399 default:
1400 return -1;
1401 case PORT_B:
1402 return 17;
1403 case PORT_C:
1404 return 19;
1405 case PORT_D:
1406 return 21;
1407 }
1408}
1409
Ville Syrjälä8fc3b422015-05-11 20:49:09 +03001410static enum port get_port_from_pin(enum hpd_pin pin)
Dave Airlie13cf5502014-06-18 11:29:35 +10001411{
1412 switch (pin) {
1413 case HPD_PORT_B:
1414 return PORT_B;
1415 case HPD_PORT_C:
1416 return PORT_C;
1417 case HPD_PORT_D:
1418 return PORT_D;
1419 default:
1420 return PORT_A; /* no hpd */
1421 }
1422}
1423
Ville Syrjälä8fc3b422015-05-11 20:49:09 +03001424static void intel_hpd_irq_handler(struct drm_device *dev,
1425 u32 hotplug_trigger,
1426 u32 dig_hotplug_reg,
1427 const u32 hpd[HPD_NUM_PINS])
Egbert Eichb543fb02013-04-16 13:36:54 +02001428{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001429 struct drm_i915_private *dev_priv = dev->dev_private;
Egbert Eichb543fb02013-04-16 13:36:54 +02001430 int i;
Dave Airlie13cf5502014-06-18 11:29:35 +10001431 enum port port;
Daniel Vetter10a504d2013-06-27 17:52:12 +02001432 bool storm_detected = false;
Dave Airlie13cf5502014-06-18 11:29:35 +10001433 bool queue_dig = false, queue_hp = false;
1434 u32 dig_shift;
1435 u32 dig_port_mask = 0;
Egbert Eichb543fb02013-04-16 13:36:54 +02001436
Daniel Vetter91d131d2013-06-27 17:52:14 +02001437 if (!hotplug_trigger)
1438 return;
1439
Dave Airlie13cf5502014-06-18 11:29:35 +10001440 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x, dig 0x%08x\n",
1441 hotplug_trigger, dig_hotplug_reg);
Imre Deakcc9bd492014-01-16 19:56:54 +02001442
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02001443 spin_lock(&dev_priv->irq_lock);
Egbert Eichb543fb02013-04-16 13:36:54 +02001444 for (i = 1; i < HPD_NUM_PINS; i++) {
Dave Airlie13cf5502014-06-18 11:29:35 +10001445 if (!(hpd[i] & hotplug_trigger))
1446 continue;
Egbert Eich821450c2013-04-16 13:36:55 +02001447
Dave Airlie13cf5502014-06-18 11:29:35 +10001448 port = get_port_from_pin(i);
1449 if (port && dev_priv->hpd_irq_port[port]) {
1450 bool long_hpd;
1451
Imre Deak6b5ad422015-03-27 17:22:34 +02001452 if (!HAS_GMCH_DISPLAY(dev_priv)) {
Jani Nikula07c338c2014-10-02 11:16:32 +03001453 dig_shift = pch_port_to_hotplug_shift(port);
Dave Airlie13cf5502014-06-18 11:29:35 +10001454 long_hpd = (dig_hotplug_reg >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
Jani Nikula07c338c2014-10-02 11:16:32 +03001455 } else {
1456 dig_shift = i915_port_to_hotplug_shift(port);
1457 long_hpd = (hotplug_trigger >> dig_shift) & PORTB_HOTPLUG_LONG_DETECT;
Dave Airlie13cf5502014-06-18 11:29:35 +10001458 }
1459
Ville Syrjälä26fbb772014-08-11 18:37:37 +03001460 DRM_DEBUG_DRIVER("digital hpd port %c - %s\n",
1461 port_name(port),
1462 long_hpd ? "long" : "short");
Dave Airlie13cf5502014-06-18 11:29:35 +10001463 /* for long HPD pulses we want to have the digital queue happen,
1464 but we still want HPD storm detection to function. */
1465 if (long_hpd) {
1466 dev_priv->long_hpd_port_mask |= (1 << port);
1467 dig_port_mask |= hpd[i];
1468 } else {
1469 /* for short HPD just trigger the digital queue */
1470 dev_priv->short_hpd_port_mask |= (1 << port);
1471 hotplug_trigger &= ~hpd[i];
1472 }
1473 queue_dig = true;
1474 }
1475 }
1476
1477 for (i = 1; i < HPD_NUM_PINS; i++) {
Daniel Vetter3ff04a162014-04-24 12:03:17 +02001478 if (hpd[i] & hotplug_trigger &&
1479 dev_priv->hpd_stats[i].hpd_mark == HPD_DISABLED) {
1480 /*
1481 * On GMCH platforms the interrupt mask bits only
1482 * prevent irq generation, not the setting of the
1483 * hotplug bits itself. So only WARN about unexpected
1484 * interrupts on saner platforms.
1485 */
1486 WARN_ONCE(INTEL_INFO(dev)->gen >= 5 && !IS_VALLEYVIEW(dev),
1487 "Received HPD interrupt (0x%08x) on pin %d (0x%08x) although disabled\n",
1488 hotplug_trigger, i, hpd[i]);
1489
1490 continue;
1491 }
Egbert Eichb8f102e2013-07-26 14:14:24 +02001492
Egbert Eichb543fb02013-04-16 13:36:54 +02001493 if (!(hpd[i] & hotplug_trigger) ||
1494 dev_priv->hpd_stats[i].hpd_mark != HPD_ENABLED)
1495 continue;
1496
Dave Airlie13cf5502014-06-18 11:29:35 +10001497 if (!(dig_port_mask & hpd[i])) {
1498 dev_priv->hpd_event_bits |= (1 << i);
1499 queue_hp = true;
1500 }
1501
Egbert Eichb543fb02013-04-16 13:36:54 +02001502 if (!time_in_range(jiffies, dev_priv->hpd_stats[i].hpd_last_jiffies,
1503 dev_priv->hpd_stats[i].hpd_last_jiffies
1504 + msecs_to_jiffies(HPD_STORM_DETECT_PERIOD))) {
1505 dev_priv->hpd_stats[i].hpd_last_jiffies = jiffies;
1506 dev_priv->hpd_stats[i].hpd_cnt = 0;
Egbert Eichb8f102e2013-07-26 14:14:24 +02001507 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: 0\n", i);
Egbert Eichb543fb02013-04-16 13:36:54 +02001508 } else if (dev_priv->hpd_stats[i].hpd_cnt > HPD_STORM_THRESHOLD) {
1509 dev_priv->hpd_stats[i].hpd_mark = HPD_MARK_DISABLED;
Egbert Eich142e2392013-04-11 15:57:57 +02001510 dev_priv->hpd_event_bits &= ~(1 << i);
Egbert Eichb543fb02013-04-16 13:36:54 +02001511 DRM_DEBUG_KMS("HPD interrupt storm detected on PIN %d\n", i);
Daniel Vetter10a504d2013-06-27 17:52:12 +02001512 storm_detected = true;
Egbert Eichb543fb02013-04-16 13:36:54 +02001513 } else {
1514 dev_priv->hpd_stats[i].hpd_cnt++;
Egbert Eichb8f102e2013-07-26 14:14:24 +02001515 DRM_DEBUG_KMS("Received HPD interrupt on PIN %d - cnt: %d\n", i,
1516 dev_priv->hpd_stats[i].hpd_cnt);
Egbert Eichb543fb02013-04-16 13:36:54 +02001517 }
1518 }
1519
Daniel Vetter10a504d2013-06-27 17:52:12 +02001520 if (storm_detected)
1521 dev_priv->display.hpd_irq_setup(dev);
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02001522 spin_unlock(&dev_priv->irq_lock);
Daniel Vetter5876fa02013-06-27 17:52:13 +02001523
Daniel Vetter645416f2013-09-02 16:22:25 +02001524 /*
1525 * Our hotplug handler can grab modeset locks (by calling down into the
1526 * fb helpers). Hence it must not be run on our own dev-priv->wq work
1527 * queue for otherwise the flush_work in the pageflip code will
1528 * deadlock.
1529 */
Dave Airlie13cf5502014-06-18 11:29:35 +10001530 if (queue_dig)
Dave Airlie0e32b392014-05-02 14:02:48 +10001531 queue_work(dev_priv->dp_wq, &dev_priv->dig_port_work);
Dave Airlie13cf5502014-06-18 11:29:35 +10001532 if (queue_hp)
1533 schedule_work(&dev_priv->hotplug_work);
Egbert Eichb543fb02013-04-16 13:36:54 +02001534}
1535
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001536static void gmbus_irq_handler(struct drm_device *dev)
1537{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001538 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter28c70f12012-12-01 13:53:45 +01001539
Daniel Vetter28c70f12012-12-01 13:53:45 +01001540 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001541}
1542
Daniel Vetterce99c252012-12-01 13:53:47 +01001543static void dp_aux_irq_handler(struct drm_device *dev)
1544{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001545 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001546
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01001547 wake_up_all(&dev_priv->gmbus_wait_queue);
Daniel Vetterce99c252012-12-01 13:53:47 +01001548}
1549
Shuang He8bf1e9f2013-10-15 18:55:27 +01001550#if defined(CONFIG_DEBUG_FS)
Daniel Vetter277de952013-10-18 16:37:07 +02001551static void display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1552 uint32_t crc0, uint32_t crc1,
1553 uint32_t crc2, uint32_t crc3,
1554 uint32_t crc4)
Shuang He8bf1e9f2013-10-15 18:55:27 +01001555{
1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557 struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe];
1558 struct intel_pipe_crc_entry *entry;
Damien Lespiauac2300d2013-10-15 18:55:30 +01001559 int head, tail;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001560
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001561 spin_lock(&pipe_crc->lock);
1562
Damien Lespiau0c912c72013-10-15 18:55:37 +01001563 if (!pipe_crc->entries) {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001564 spin_unlock(&pipe_crc->lock);
Daniel Vetter34273622014-11-26 16:29:04 +01001565 DRM_DEBUG_KMS("spurious interrupt\n");
Damien Lespiau0c912c72013-10-15 18:55:37 +01001566 return;
1567 }
1568
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001569 head = pipe_crc->head;
1570 tail = pipe_crc->tail;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001571
1572 if (CIRC_SPACE(head, tail, INTEL_PIPE_CRC_ENTRIES_NR) < 1) {
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001573 spin_unlock(&pipe_crc->lock);
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001574 DRM_ERROR("CRC buffer overflowing\n");
1575 return;
1576 }
1577
1578 entry = &pipe_crc->entries[head];
Shuang He8bf1e9f2013-10-15 18:55:27 +01001579
Daniel Vetter8bc5e952013-10-16 22:55:49 +02001580 entry->frame = dev->driver->get_vblank_counter(dev, pipe);
Daniel Vettereba94eb2013-10-16 22:55:46 +02001581 entry->crc[0] = crc0;
1582 entry->crc[1] = crc1;
1583 entry->crc[2] = crc2;
1584 entry->crc[3] = crc3;
1585 entry->crc[4] = crc4;
Damien Lespiaub2c88f52013-10-15 18:55:29 +01001586
1587 head = (head + 1) & (INTEL_PIPE_CRC_ENTRIES_NR - 1);
Damien Lespiaud538bbd2013-10-21 14:29:30 +01001588 pipe_crc->head = head;
1589
1590 spin_unlock(&pipe_crc->lock);
Damien Lespiau07144422013-10-15 18:55:40 +01001591
1592 wake_up_interruptible(&pipe_crc->wq);
Shuang He8bf1e9f2013-10-15 18:55:27 +01001593}
Daniel Vetter277de952013-10-18 16:37:07 +02001594#else
1595static inline void
1596display_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe,
1597 uint32_t crc0, uint32_t crc1,
1598 uint32_t crc2, uint32_t crc3,
1599 uint32_t crc4) {}
1600#endif
Daniel Vettereba94eb2013-10-16 22:55:46 +02001601
Daniel Vetter277de952013-10-18 16:37:07 +02001602
1603static void hsw_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
Daniel Vetter5a69b892013-10-16 22:55:52 +02001604{
1605 struct drm_i915_private *dev_priv = dev->dev_private;
1606
Daniel Vetter277de952013-10-18 16:37:07 +02001607 display_pipe_crc_irq_handler(dev, pipe,
1608 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1609 0, 0, 0, 0);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001610}
1611
Daniel Vetter277de952013-10-18 16:37:07 +02001612static void ivb_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
Daniel Vettereba94eb2013-10-16 22:55:46 +02001613{
1614 struct drm_i915_private *dev_priv = dev->dev_private;
1615
Daniel Vetter277de952013-10-18 16:37:07 +02001616 display_pipe_crc_irq_handler(dev, pipe,
1617 I915_READ(PIPE_CRC_RES_1_IVB(pipe)),
1618 I915_READ(PIPE_CRC_RES_2_IVB(pipe)),
1619 I915_READ(PIPE_CRC_RES_3_IVB(pipe)),
1620 I915_READ(PIPE_CRC_RES_4_IVB(pipe)),
1621 I915_READ(PIPE_CRC_RES_5_IVB(pipe)));
Daniel Vettereba94eb2013-10-16 22:55:46 +02001622}
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001623
Daniel Vetter277de952013-10-18 16:37:07 +02001624static void i9xx_pipe_crc_irq_handler(struct drm_device *dev, enum pipe pipe)
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001625{
1626 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter0b5c5ed2013-10-16 22:55:53 +02001627 uint32_t res1, res2;
1628
1629 if (INTEL_INFO(dev)->gen >= 3)
1630 res1 = I915_READ(PIPE_CRC_RES_RES1_I915(pipe));
1631 else
1632 res1 = 0;
1633
1634 if (INTEL_INFO(dev)->gen >= 5 || IS_G4X(dev))
1635 res2 = I915_READ(PIPE_CRC_RES_RES2_G4X(pipe));
1636 else
1637 res2 = 0;
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001638
Daniel Vetter277de952013-10-18 16:37:07 +02001639 display_pipe_crc_irq_handler(dev, pipe,
1640 I915_READ(PIPE_CRC_RES_RED(pipe)),
1641 I915_READ(PIPE_CRC_RES_GREEN(pipe)),
1642 I915_READ(PIPE_CRC_RES_BLUE(pipe)),
1643 res1, res2);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02001644}
Shuang He8bf1e9f2013-10-15 18:55:27 +01001645
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001646/* The RPS events need forcewake, so we add them to a work queue and mask their
1647 * IMR bits until the work is done. Other interrupts can be processed without
1648 * the work queue. */
1649static void gen6_rps_irq_handler(struct drm_i915_private *dev_priv, u32 pm_iir)
Ben Widawskybaf02a12013-05-28 19:22:24 -07001650{
Deepak Sa6706b42014-03-15 20:23:22 +05301651 if (pm_iir & dev_priv->pm_rps_events) {
Daniel Vetter59cdb632013-07-04 23:35:28 +02001652 spin_lock(&dev_priv->irq_lock);
Daniel Vetter480c8032014-07-16 09:49:40 +02001653 gen6_disable_pm_irq(dev_priv, pm_iir & dev_priv->pm_rps_events);
Imre Deakd4d70aa2014-11-19 15:30:04 +02001654 if (dev_priv->rps.interrupts_enabled) {
1655 dev_priv->rps.pm_iir |= pm_iir & dev_priv->pm_rps_events;
1656 queue_work(dev_priv->wq, &dev_priv->rps.work);
1657 }
Daniel Vetter59cdb632013-07-04 23:35:28 +02001658 spin_unlock(&dev_priv->irq_lock);
Ben Widawskybaf02a12013-05-28 19:22:24 -07001659 }
Ben Widawskybaf02a12013-05-28 19:22:24 -07001660
Imre Deakc9a9a262014-11-05 20:48:37 +02001661 if (INTEL_INFO(dev_priv)->gen >= 8)
1662 return;
1663
Paulo Zanoni1403c0d2013-08-15 11:51:32 -03001664 if (HAS_VEBOX(dev_priv->dev)) {
1665 if (pm_iir & PM_VEBOX_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01001666 notify_ring(&dev_priv->ring[VECS]);
Ben Widawsky12638c52013-05-28 19:22:31 -07001667
Daniel Vetteraaecdf62014-11-04 15:52:22 +01001668 if (pm_iir & PM_VEBOX_CS_ERROR_INTERRUPT)
1669 DRM_DEBUG("Command parser error, pm_iir 0x%08x\n", pm_iir);
Ben Widawsky12638c52013-05-28 19:22:31 -07001670 }
Ben Widawskybaf02a12013-05-28 19:22:24 -07001671}
1672
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03001673static bool intel_pipe_handle_vblank(struct drm_device *dev, enum pipe pipe)
1674{
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03001675 if (!drm_handle_vblank(dev, pipe))
1676 return false;
1677
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03001678 return true;
1679}
1680
Imre Deakc1874ed2014-02-04 21:35:46 +02001681static void valleyview_pipestat_irq_handler(struct drm_device *dev, u32 iir)
1682{
1683 struct drm_i915_private *dev_priv = dev->dev_private;
Imre Deak91d181d2014-02-10 18:42:49 +02001684 u32 pipe_stats[I915_MAX_PIPES] = { };
Imre Deakc1874ed2014-02-04 21:35:46 +02001685 int pipe;
1686
Imre Deak58ead0d2014-02-04 21:35:47 +02001687 spin_lock(&dev_priv->irq_lock);
Damien Lespiau055e3932014-08-18 13:49:10 +01001688 for_each_pipe(dev_priv, pipe) {
Imre Deak91d181d2014-02-10 18:42:49 +02001689 int reg;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001690 u32 mask, iir_bit = 0;
Imre Deak91d181d2014-02-10 18:42:49 +02001691
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001692 /*
1693 * PIPESTAT bits get signalled even when the interrupt is
1694 * disabled with the mask bits, and some of the status bits do
1695 * not generate interrupts at all (like the underrun bit). Hence
1696 * we need to be careful that we only handle what we want to
1697 * handle.
1698 */
Daniel Vetter0f239f42014-09-30 10:56:49 +02001699
1700 /* fifo underruns are filterered in the underrun handler. */
1701 mask = PIPE_FIFO_UNDERRUN_STATUS;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001702
1703 switch (pipe) {
1704 case PIPE_A:
1705 iir_bit = I915_DISPLAY_PIPE_A_EVENT_INTERRUPT;
1706 break;
1707 case PIPE_B:
1708 iir_bit = I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
1709 break;
Ville Syrjälä3278f672014-04-09 13:28:49 +03001710 case PIPE_C:
1711 iir_bit = I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
1712 break;
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001713 }
1714 if (iir & iir_bit)
1715 mask |= dev_priv->pipestat_irq_mask[pipe];
1716
1717 if (!mask)
Imre Deak91d181d2014-02-10 18:42:49 +02001718 continue;
1719
1720 reg = PIPESTAT(pipe);
Daniel Vetterbbb5eeb2014-02-12 17:55:36 +01001721 mask |= PIPESTAT_INT_ENABLE_MASK;
1722 pipe_stats[pipe] = I915_READ(reg) & mask;
Imre Deakc1874ed2014-02-04 21:35:46 +02001723
1724 /*
1725 * Clear the PIPE*STAT regs before the IIR
1726 */
Imre Deak91d181d2014-02-10 18:42:49 +02001727 if (pipe_stats[pipe] & (PIPE_FIFO_UNDERRUN_STATUS |
1728 PIPESTAT_INT_STATUS_MASK))
Imre Deakc1874ed2014-02-04 21:35:46 +02001729 I915_WRITE(reg, pipe_stats[pipe]);
1730 }
Imre Deak58ead0d2014-02-04 21:35:47 +02001731 spin_unlock(&dev_priv->irq_lock);
Imre Deakc1874ed2014-02-04 21:35:46 +02001732
Damien Lespiau055e3932014-08-18 13:49:10 +01001733 for_each_pipe(dev_priv, pipe) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01001734 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
1735 intel_pipe_handle_vblank(dev, pipe))
1736 intel_check_page_flip(dev, pipe);
Imre Deakc1874ed2014-02-04 21:35:46 +02001737
Imre Deak579a9b02014-02-04 21:35:48 +02001738 if (pipe_stats[pipe] & PLANE_FLIP_DONE_INT_STATUS_VLV) {
Imre Deakc1874ed2014-02-04 21:35:46 +02001739 intel_prepare_page_flip(dev, pipe);
1740 intel_finish_page_flip(dev, pipe);
1741 }
1742
1743 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
1744 i9xx_pipe_crc_irq_handler(dev, pipe);
1745
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001746 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
1747 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Imre Deakc1874ed2014-02-04 21:35:46 +02001748 }
1749
1750 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
1751 gmbus_irq_handler(dev);
1752}
1753
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001754static void i9xx_hpd_irq_handler(struct drm_device *dev)
1755{
1756 struct drm_i915_private *dev_priv = dev->dev_private;
1757 u32 hotplug_status = I915_READ(PORT_HOTPLUG_STAT);
1758
Jani Nikula0d2e4292015-05-27 15:03:39 +03001759 if (!hotplug_status)
1760 return;
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001761
Jani Nikula0d2e4292015-05-27 15:03:39 +03001762 I915_WRITE(PORT_HOTPLUG_STAT, hotplug_status);
1763 /*
1764 * Make sure hotplug status is cleared before we clear IIR, or else we
1765 * may miss hotplug events.
1766 */
1767 POSTING_READ(PORT_HOTPLUG_STAT);
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001768
Jani Nikula0d2e4292015-05-27 15:03:39 +03001769 if (IS_G4X(dev) || IS_VALLEYVIEW(dev)) {
1770 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_G4X;
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001771
Jani Nikula0d2e4292015-05-27 15:03:39 +03001772 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_g4x);
1773 } else {
1774 u32 hotplug_trigger = hotplug_status & HOTPLUG_INT_STATUS_I915;
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001775
Jani Nikula0d2e4292015-05-27 15:03:39 +03001776 intel_hpd_irq_handler(dev, hotplug_trigger, 0, hpd_status_i915);
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001777 }
Jani Nikula0d2e4292015-05-27 15:03:39 +03001778
1779 if ((IS_G4X(dev) || IS_VALLEYVIEW(dev)) &&
1780 hotplug_status & DP_AUX_CHANNEL_MASK_INT_STATUS_G4X)
1781 dp_aux_irq_handler(dev);
Ville Syrjälä16c6c562014-04-01 10:54:36 +03001782}
1783
Daniel Vetterff1f5252012-10-02 15:10:55 +02001784static irqreturn_t valleyview_irq_handler(int irq, void *arg)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001785{
Daniel Vetter45a83f82014-05-12 19:17:55 +02001786 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03001787 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001788 u32 iir, gt_iir, pm_iir;
1789 irqreturn_t ret = IRQ_NONE;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001790
Imre Deak2dd2a882015-02-24 11:14:30 +02001791 if (!intel_irqs_enabled(dev_priv))
1792 return IRQ_NONE;
1793
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001794 while (true) {
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001795 /* Find, clear, then process each source of interrupt */
1796
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001797 gt_iir = I915_READ(GTIIR);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001798 if (gt_iir)
1799 I915_WRITE(GTIIR, gt_iir);
1800
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001801 pm_iir = I915_READ(GEN6_PMIIR);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001802 if (pm_iir)
1803 I915_WRITE(GEN6_PMIIR, pm_iir);
1804
1805 iir = I915_READ(VLV_IIR);
1806 if (iir) {
1807 /* Consume port before clearing IIR or we'll miss events */
1808 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1809 i9xx_hpd_irq_handler(dev);
1810 I915_WRITE(VLV_IIR, iir);
1811 }
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001812
1813 if (gt_iir == 0 && pm_iir == 0 && iir == 0)
1814 goto out;
1815
1816 ret = IRQ_HANDLED;
1817
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001818 if (gt_iir)
1819 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Paulo Zanoni60611c12013-08-15 11:50:01 -03001820 if (pm_iir)
Daniel Vetterd0ecd7e2013-07-04 23:35:25 +02001821 gen6_rps_irq_handler(dev_priv, pm_iir);
Oscar Mateo3ff60f82014-06-16 16:10:58 +01001822 /* Call regardless, as some status bits might not be
1823 * signalled in iir */
1824 valleyview_pipestat_irq_handler(dev, iir);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07001825 }
1826
1827out:
1828 return ret;
1829}
1830
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001831static irqreturn_t cherryview_irq_handler(int irq, void *arg)
1832{
Daniel Vetter45a83f82014-05-12 19:17:55 +02001833 struct drm_device *dev = arg;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001834 struct drm_i915_private *dev_priv = dev->dev_private;
1835 u32 master_ctl, iir;
1836 irqreturn_t ret = IRQ_NONE;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001837
Imre Deak2dd2a882015-02-24 11:14:30 +02001838 if (!intel_irqs_enabled(dev_priv))
1839 return IRQ_NONE;
1840
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001841 for (;;) {
1842 master_ctl = I915_READ(GEN8_MASTER_IRQ) & ~GEN8_MASTER_IRQ_CONTROL;
1843 iir = I915_READ(VLV_IIR);
Ville Syrjälä3278f672014-04-09 13:28:49 +03001844
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001845 if (master_ctl == 0 && iir == 0)
1846 break;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001847
Oscar Mateo27b6c122014-06-16 16:11:00 +01001848 ret = IRQ_HANDLED;
1849
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001850 I915_WRITE(GEN8_MASTER_IRQ, 0);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001851
Oscar Mateo27b6c122014-06-16 16:11:00 +01001852 /* Find, clear, then process each source of interrupt */
1853
1854 if (iir) {
1855 /* Consume port before clearing IIR or we'll miss events */
1856 if (iir & I915_DISPLAY_PORT_INTERRUPT)
1857 i9xx_hpd_irq_handler(dev);
1858 I915_WRITE(VLV_IIR, iir);
1859 }
1860
Chris Wilson74cdb332015-04-07 16:21:05 +01001861 gen8_gt_irq_handler(dev_priv, master_ctl);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001862
Oscar Mateo27b6c122014-06-16 16:11:00 +01001863 /* Call regardless, as some status bits might not be
1864 * signalled in iir */
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001865 valleyview_pipestat_irq_handler(dev, iir);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001866
Ville Syrjälä8e5fd592014-04-09 13:28:50 +03001867 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
1868 POSTING_READ(GEN8_MASTER_IRQ);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001869 }
1870
Ville Syrjälä43f328d2014-04-09 20:40:52 +03001871 return ret;
1872}
1873
Adam Jackson23e81d62012-06-06 15:45:44 -04001874static void ibx_irq_handler(struct drm_device *dev, u32 pch_iir)
Jesse Barnes776ad802011-01-04 15:09:39 -08001875{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001876 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001877 int pipe;
Egbert Eichb543fb02013-04-16 13:36:54 +02001878 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK;
Dave Airlie13cf5502014-06-18 11:29:35 +10001879 u32 dig_hotplug_reg;
Jesse Barnes776ad802011-01-04 15:09:39 -08001880
Dave Airlie13cf5502014-06-18 11:29:35 +10001881 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1882 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1883
1884 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_ibx);
Daniel Vetter91d131d2013-06-27 17:52:14 +02001885
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001886 if (pch_iir & SDE_AUDIO_POWER_MASK) {
1887 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK) >>
1888 SDE_AUDIO_POWER_SHIFT);
Jesse Barnes776ad802011-01-04 15:09:39 -08001889 DRM_DEBUG_DRIVER("PCH audio power change on port %d\n",
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001890 port_name(port));
1891 }
Jesse Barnes776ad802011-01-04 15:09:39 -08001892
Daniel Vetterce99c252012-12-01 13:53:47 +01001893 if (pch_iir & SDE_AUX_MASK)
1894 dp_aux_irq_handler(dev);
1895
Jesse Barnes776ad802011-01-04 15:09:39 -08001896 if (pch_iir & SDE_GMBUS)
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001897 gmbus_irq_handler(dev);
Jesse Barnes776ad802011-01-04 15:09:39 -08001898
1899 if (pch_iir & SDE_AUDIO_HDCP_MASK)
1900 DRM_DEBUG_DRIVER("PCH HDCP audio interrupt\n");
1901
1902 if (pch_iir & SDE_AUDIO_TRANS_MASK)
1903 DRM_DEBUG_DRIVER("PCH transcoder audio interrupt\n");
1904
1905 if (pch_iir & SDE_POISON)
1906 DRM_ERROR("PCH poison interrupt\n");
1907
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001908 if (pch_iir & SDE_FDI_MASK)
Damien Lespiau055e3932014-08-18 13:49:10 +01001909 for_each_pipe(dev_priv, pipe)
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08001910 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
1911 pipe_name(pipe),
1912 I915_READ(FDI_RX_IIR(pipe)));
Jesse Barnes776ad802011-01-04 15:09:39 -08001913
1914 if (pch_iir & (SDE_TRANSB_CRC_DONE | SDE_TRANSA_CRC_DONE))
1915 DRM_DEBUG_DRIVER("PCH transcoder CRC done interrupt\n");
1916
1917 if (pch_iir & (SDE_TRANSB_CRC_ERR | SDE_TRANSA_CRC_ERR))
1918 DRM_DEBUG_DRIVER("PCH transcoder CRC error interrupt\n");
1919
Jesse Barnes776ad802011-01-04 15:09:39 -08001920 if (pch_iir & SDE_TRANSA_FIFO_UNDER)
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001921 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
Paulo Zanoni86642812013-04-12 17:57:57 -03001922
1923 if (pch_iir & SDE_TRANSB_FIFO_UNDER)
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001924 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
Paulo Zanoni86642812013-04-12 17:57:57 -03001925}
1926
1927static void ivb_err_int_handler(struct drm_device *dev)
1928{
1929 struct drm_i915_private *dev_priv = dev->dev_private;
1930 u32 err_int = I915_READ(GEN7_ERR_INT);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001931 enum pipe pipe;
Paulo Zanoni86642812013-04-12 17:57:57 -03001932
Paulo Zanonide032bf2013-04-12 17:57:58 -03001933 if (err_int & ERR_INT_POISON)
1934 DRM_ERROR("Poison interrupt\n");
1935
Damien Lespiau055e3932014-08-18 13:49:10 +01001936 for_each_pipe(dev_priv, pipe) {
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001937 if (err_int & ERR_INT_FIFO_UNDERRUN(pipe))
1938 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Paulo Zanoni86642812013-04-12 17:57:57 -03001939
Daniel Vetter5a69b892013-10-16 22:55:52 +02001940 if (err_int & ERR_INT_PIPE_CRC_DONE(pipe)) {
1941 if (IS_IVYBRIDGE(dev))
Daniel Vetter277de952013-10-18 16:37:07 +02001942 ivb_pipe_crc_irq_handler(dev, pipe);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001943 else
Daniel Vetter277de952013-10-18 16:37:07 +02001944 hsw_pipe_crc_irq_handler(dev, pipe);
Daniel Vetter5a69b892013-10-16 22:55:52 +02001945 }
1946 }
Shuang He8bf1e9f2013-10-15 18:55:27 +01001947
Paulo Zanoni86642812013-04-12 17:57:57 -03001948 I915_WRITE(GEN7_ERR_INT, err_int);
1949}
1950
1951static void cpt_serr_int_handler(struct drm_device *dev)
1952{
1953 struct drm_i915_private *dev_priv = dev->dev_private;
1954 u32 serr_int = I915_READ(SERR_INT);
1955
Paulo Zanonide032bf2013-04-12 17:57:58 -03001956 if (serr_int & SERR_INT_POISON)
1957 DRM_ERROR("PCH poison interrupt\n");
1958
Paulo Zanoni86642812013-04-12 17:57:57 -03001959 if (serr_int & SERR_INT_TRANS_A_FIFO_UNDERRUN)
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001960 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_A);
Paulo Zanoni86642812013-04-12 17:57:57 -03001961
1962 if (serr_int & SERR_INT_TRANS_B_FIFO_UNDERRUN)
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001963 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_B);
Paulo Zanoni86642812013-04-12 17:57:57 -03001964
1965 if (serr_int & SERR_INT_TRANS_C_FIFO_UNDERRUN)
Daniel Vetter1f7247c2014-09-30 10:56:48 +02001966 intel_pch_fifo_underrun_irq_handler(dev_priv, TRANSCODER_C);
Paulo Zanoni86642812013-04-12 17:57:57 -03001967
1968 I915_WRITE(SERR_INT, serr_int);
Jesse Barnes776ad802011-01-04 15:09:39 -08001969}
1970
Adam Jackson23e81d62012-06-06 15:45:44 -04001971static void cpt_irq_handler(struct drm_device *dev, u32 pch_iir)
1972{
Jani Nikula2d1013d2014-03-31 14:27:17 +03001973 struct drm_i915_private *dev_priv = dev->dev_private;
Adam Jackson23e81d62012-06-06 15:45:44 -04001974 int pipe;
Egbert Eichb543fb02013-04-16 13:36:54 +02001975 u32 hotplug_trigger = pch_iir & SDE_HOTPLUG_MASK_CPT;
Dave Airlie13cf5502014-06-18 11:29:35 +10001976 u32 dig_hotplug_reg;
Adam Jackson23e81d62012-06-06 15:45:44 -04001977
Dave Airlie13cf5502014-06-18 11:29:35 +10001978 dig_hotplug_reg = I915_READ(PCH_PORT_HOTPLUG);
1979 I915_WRITE(PCH_PORT_HOTPLUG, dig_hotplug_reg);
1980
1981 intel_hpd_irq_handler(dev, hotplug_trigger, dig_hotplug_reg, hpd_cpt);
Daniel Vetter91d131d2013-06-27 17:52:14 +02001982
Ville Syrjäläcfc33bf2013-04-17 17:48:48 +03001983 if (pch_iir & SDE_AUDIO_POWER_MASK_CPT) {
1984 int port = ffs((pch_iir & SDE_AUDIO_POWER_MASK_CPT) >>
1985 SDE_AUDIO_POWER_SHIFT_CPT);
1986 DRM_DEBUG_DRIVER("PCH audio power change on port %c\n",
1987 port_name(port));
1988 }
Adam Jackson23e81d62012-06-06 15:45:44 -04001989
1990 if (pch_iir & SDE_AUX_MASK_CPT)
Daniel Vetterce99c252012-12-01 13:53:47 +01001991 dp_aux_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001992
1993 if (pch_iir & SDE_GMBUS_CPT)
Daniel Vetter515ac2b2012-12-01 13:53:44 +01001994 gmbus_irq_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04001995
1996 if (pch_iir & SDE_AUDIO_CP_REQ_CPT)
1997 DRM_DEBUG_DRIVER("Audio CP request interrupt\n");
1998
1999 if (pch_iir & SDE_AUDIO_CP_CHG_CPT)
2000 DRM_DEBUG_DRIVER("Audio CP change interrupt\n");
2001
2002 if (pch_iir & SDE_FDI_MASK_CPT)
Damien Lespiau055e3932014-08-18 13:49:10 +01002003 for_each_pipe(dev_priv, pipe)
Adam Jackson23e81d62012-06-06 15:45:44 -04002004 DRM_DEBUG_DRIVER(" pipe %c FDI IIR: 0x%08x\n",
2005 pipe_name(pipe),
2006 I915_READ(FDI_RX_IIR(pipe)));
Paulo Zanoni86642812013-04-12 17:57:57 -03002007
2008 if (pch_iir & SDE_ERROR_CPT)
2009 cpt_serr_int_handler(dev);
Adam Jackson23e81d62012-06-06 15:45:44 -04002010}
2011
Paulo Zanonic008bc62013-07-12 16:35:10 -03002012static void ilk_display_irq_handler(struct drm_device *dev, u32 de_iir)
2013{
2014 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter40da17c22013-10-21 18:04:36 +02002015 enum pipe pipe;
Paulo Zanonic008bc62013-07-12 16:35:10 -03002016
2017 if (de_iir & DE_AUX_CHANNEL_A)
2018 dp_aux_irq_handler(dev);
2019
2020 if (de_iir & DE_GSE)
2021 intel_opregion_asle_intr(dev);
2022
Paulo Zanonic008bc62013-07-12 16:35:10 -03002023 if (de_iir & DE_POISON)
2024 DRM_ERROR("Poison interrupt\n");
2025
Damien Lespiau055e3932014-08-18 13:49:10 +01002026 for_each_pipe(dev_priv, pipe) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01002027 if (de_iir & DE_PIPE_VBLANK(pipe) &&
2028 intel_pipe_handle_vblank(dev, pipe))
2029 intel_check_page_flip(dev, pipe);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002030
Daniel Vetter40da17c22013-10-21 18:04:36 +02002031 if (de_iir & DE_PIPE_FIFO_UNDERRUN(pipe))
Daniel Vetter1f7247c2014-09-30 10:56:48 +02002032 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Paulo Zanonic008bc62013-07-12 16:35:10 -03002033
Daniel Vetter40da17c22013-10-21 18:04:36 +02002034 if (de_iir & DE_PIPE_CRC_DONE(pipe))
2035 i9xx_pipe_crc_irq_handler(dev, pipe);
Daniel Vetter5b3a8562013-10-16 22:55:48 +02002036
Daniel Vetter40da17c22013-10-21 18:04:36 +02002037 /* plane/pipes map 1:1 on ilk+ */
2038 if (de_iir & DE_PLANE_FLIP_DONE(pipe)) {
2039 intel_prepare_page_flip(dev, pipe);
2040 intel_finish_page_flip_plane(dev, pipe);
2041 }
Paulo Zanonic008bc62013-07-12 16:35:10 -03002042 }
2043
2044 /* check event from PCH */
2045 if (de_iir & DE_PCH_EVENT) {
2046 u32 pch_iir = I915_READ(SDEIIR);
2047
2048 if (HAS_PCH_CPT(dev))
2049 cpt_irq_handler(dev, pch_iir);
2050 else
2051 ibx_irq_handler(dev, pch_iir);
2052
2053 /* should clear PCH hotplug event before clear CPU irq */
2054 I915_WRITE(SDEIIR, pch_iir);
2055 }
2056
2057 if (IS_GEN5(dev) && de_iir & DE_PCU_EVENT)
2058 ironlake_rps_change_irq_handler(dev);
2059}
2060
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002061static void ivb_display_irq_handler(struct drm_device *dev, u32 de_iir)
2062{
2063 struct drm_i915_private *dev_priv = dev->dev_private;
Damien Lespiau07d27e22014-03-03 17:31:46 +00002064 enum pipe pipe;
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002065
2066 if (de_iir & DE_ERR_INT_IVB)
2067 ivb_err_int_handler(dev);
2068
2069 if (de_iir & DE_AUX_CHANNEL_A_IVB)
2070 dp_aux_irq_handler(dev);
2071
2072 if (de_iir & DE_GSE_IVB)
2073 intel_opregion_asle_intr(dev);
2074
Damien Lespiau055e3932014-08-18 13:49:10 +01002075 for_each_pipe(dev_priv, pipe) {
Chris Wilsond6bbafa2014-09-05 07:13:24 +01002076 if (de_iir & (DE_PIPE_VBLANK_IVB(pipe)) &&
2077 intel_pipe_handle_vblank(dev, pipe))
2078 intel_check_page_flip(dev, pipe);
Daniel Vetter40da17c22013-10-21 18:04:36 +02002079
2080 /* plane/pipes map 1:1 on ilk+ */
Damien Lespiau07d27e22014-03-03 17:31:46 +00002081 if (de_iir & DE_PLANE_FLIP_DONE_IVB(pipe)) {
2082 intel_prepare_page_flip(dev, pipe);
2083 intel_finish_page_flip_plane(dev, pipe);
Paulo Zanoni9719fb92013-07-12 16:35:11 -03002084 }
2085 }
2086
2087 /* check event from PCH */
2088 if (!HAS_PCH_NOP(dev) && (de_iir & DE_PCH_EVENT_IVB)) {
2089 u32 pch_iir = I915_READ(SDEIIR);
2090
2091 cpt_irq_handler(dev, pch_iir);
2092
2093 /* clear PCH hotplug event before clear CPU irq */
2094 I915_WRITE(SDEIIR, pch_iir);
2095 }
2096}
2097
Oscar Mateo72c90f62014-06-16 16:10:57 +01002098/*
2099 * To handle irqs with the minimum potential races with fresh interrupts, we:
2100 * 1 - Disable Master Interrupt Control.
2101 * 2 - Find the source(s) of the interrupt.
2102 * 3 - Clear the Interrupt Identity bits (IIR).
2103 * 4 - Process the interrupt(s) that had bits set in the IIRs.
2104 * 5 - Re-enable Master Interrupt Control.
2105 */
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002106static irqreturn_t ironlake_irq_handler(int irq, void *arg)
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002107{
Daniel Vetter45a83f82014-05-12 19:17:55 +02002108 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03002109 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002110 u32 de_iir, gt_iir, de_ier, sde_ier = 0;
Chris Wilson0e434062012-05-09 21:45:44 +01002111 irqreturn_t ret = IRQ_NONE;
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002112
Imre Deak2dd2a882015-02-24 11:14:30 +02002113 if (!intel_irqs_enabled(dev_priv))
2114 return IRQ_NONE;
2115
Paulo Zanoni86642812013-04-12 17:57:57 -03002116 /* We get interrupts on unclaimed registers, so check for this before we
2117 * do any I915_{READ,WRITE}. */
Chris Wilson907b28c2013-07-19 20:36:52 +01002118 intel_uncore_check_errors(dev);
Paulo Zanoni86642812013-04-12 17:57:57 -03002119
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002120 /* disable master interrupt before clearing iir */
2121 de_ier = I915_READ(DEIER);
2122 I915_WRITE(DEIER, de_ier & ~DE_MASTER_IRQ_CONTROL);
Paulo Zanoni23a78512013-07-12 16:35:14 -03002123 POSTING_READ(DEIER);
Chris Wilson0e434062012-05-09 21:45:44 +01002124
Paulo Zanoni44498ae2013-02-22 17:05:28 -03002125 /* Disable south interrupts. We'll only write to SDEIIR once, so further
2126 * interrupts will will be stored on its back queue, and then we'll be
2127 * able to process them after we restore SDEIER (as soon as we restore
2128 * it, we'll get an interrupt if SDEIIR still has something to process
2129 * due to its back queue). */
Ben Widawskyab5c6082013-04-05 13:12:41 -07002130 if (!HAS_PCH_NOP(dev)) {
2131 sde_ier = I915_READ(SDEIER);
2132 I915_WRITE(SDEIER, 0);
2133 POSTING_READ(SDEIER);
2134 }
Paulo Zanoni44498ae2013-02-22 17:05:28 -03002135
Oscar Mateo72c90f62014-06-16 16:10:57 +01002136 /* Find, clear, then process each source of interrupt */
2137
Chris Wilson0e434062012-05-09 21:45:44 +01002138 gt_iir = I915_READ(GTIIR);
2139 if (gt_iir) {
Oscar Mateo72c90f62014-06-16 16:10:57 +01002140 I915_WRITE(GTIIR, gt_iir);
2141 ret = IRQ_HANDLED;
Paulo Zanonid8fc8a42013-07-19 18:57:55 -03002142 if (INTEL_INFO(dev)->gen >= 6)
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002143 snb_gt_irq_handler(dev, dev_priv, gt_iir);
Paulo Zanonid8fc8a42013-07-19 18:57:55 -03002144 else
2145 ilk_gt_irq_handler(dev, dev_priv, gt_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01002146 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002147
2148 de_iir = I915_READ(DEIIR);
Chris Wilson0e434062012-05-09 21:45:44 +01002149 if (de_iir) {
Oscar Mateo72c90f62014-06-16 16:10:57 +01002150 I915_WRITE(DEIIR, de_iir);
2151 ret = IRQ_HANDLED;
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002152 if (INTEL_INFO(dev)->gen >= 7)
2153 ivb_display_irq_handler(dev, de_iir);
2154 else
2155 ilk_display_irq_handler(dev, de_iir);
Chris Wilson0e434062012-05-09 21:45:44 +01002156 }
2157
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002158 if (INTEL_INFO(dev)->gen >= 6) {
2159 u32 pm_iir = I915_READ(GEN6_PMIIR);
2160 if (pm_iir) {
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002161 I915_WRITE(GEN6_PMIIR, pm_iir);
2162 ret = IRQ_HANDLED;
Oscar Mateo72c90f62014-06-16 16:10:57 +01002163 gen6_rps_irq_handler(dev_priv, pm_iir);
Paulo Zanonif1af8fc2013-07-12 19:56:30 -03002164 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002165 }
2166
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002167 I915_WRITE(DEIER, de_ier);
2168 POSTING_READ(DEIER);
Ben Widawskyab5c6082013-04-05 13:12:41 -07002169 if (!HAS_PCH_NOP(dev)) {
2170 I915_WRITE(SDEIER, sde_ier);
2171 POSTING_READ(SDEIER);
2172 }
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002173
2174 return ret;
2175}
2176
Shashank Sharmad04a4922014-08-22 17:40:41 +05302177static void bxt_hpd_handler(struct drm_device *dev, uint32_t iir_status)
2178{
2179 struct drm_i915_private *dev_priv = dev->dev_private;
2180 uint32_t hp_control;
2181 uint32_t hp_trigger;
2182
2183 /* Get the status */
2184 hp_trigger = iir_status & BXT_DE_PORT_HOTPLUG_MASK;
2185 hp_control = I915_READ(BXT_HOTPLUG_CTL);
2186
2187 /* Hotplug not enabled ? */
2188 if (!(hp_control & BXT_HOTPLUG_CTL_MASK)) {
2189 DRM_ERROR("Interrupt when HPD disabled\n");
2190 return;
2191 }
2192
2193 DRM_DEBUG_DRIVER("hotplug event received, stat 0x%08x\n",
2194 hp_control & BXT_HOTPLUG_CTL_MASK);
2195
2196 /* Check for HPD storm and schedule bottom half */
2197 intel_hpd_irq_handler(dev, hp_trigger, hp_control, hpd_bxt);
2198
2199 /*
2200 * FIXME: Save the hot plug status for bottom half before
2201 * clearing the sticky status bits, else the status will be
2202 * lost.
2203 */
2204
2205 /* Clear sticky bits in hpd status */
2206 I915_WRITE(BXT_HOTPLUG_CTL, hp_control);
2207}
2208
Ben Widawskyabd58f02013-11-02 21:07:09 -07002209static irqreturn_t gen8_irq_handler(int irq, void *arg)
2210{
2211 struct drm_device *dev = arg;
2212 struct drm_i915_private *dev_priv = dev->dev_private;
2213 u32 master_ctl;
2214 irqreturn_t ret = IRQ_NONE;
2215 uint32_t tmp = 0;
Daniel Vetterc42664c2013-11-07 11:05:40 +01002216 enum pipe pipe;
Jesse Barnes88e04702014-11-13 17:51:48 +00002217 u32 aux_mask = GEN8_AUX_CHANNEL_A;
2218
Imre Deak2dd2a882015-02-24 11:14:30 +02002219 if (!intel_irqs_enabled(dev_priv))
2220 return IRQ_NONE;
2221
Jesse Barnes88e04702014-11-13 17:51:48 +00002222 if (IS_GEN9(dev))
2223 aux_mask |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
2224 GEN9_AUX_CHANNEL_D;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002225
Chris Wilsoncb0d2052015-04-07 16:21:04 +01002226 master_ctl = I915_READ_FW(GEN8_MASTER_IRQ);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002227 master_ctl &= ~GEN8_MASTER_IRQ_CONTROL;
2228 if (!master_ctl)
2229 return IRQ_NONE;
2230
Chris Wilsoncb0d2052015-04-07 16:21:04 +01002231 I915_WRITE_FW(GEN8_MASTER_IRQ, 0);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002232
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002233 /* Find, clear, then process each source of interrupt */
2234
Chris Wilson74cdb332015-04-07 16:21:05 +01002235 ret = gen8_gt_irq_handler(dev_priv, master_ctl);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002236
2237 if (master_ctl & GEN8_DE_MISC_IRQ) {
2238 tmp = I915_READ(GEN8_DE_MISC_IIR);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002239 if (tmp) {
2240 I915_WRITE(GEN8_DE_MISC_IIR, tmp);
2241 ret = IRQ_HANDLED;
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002242 if (tmp & GEN8_DE_MISC_GSE)
2243 intel_opregion_asle_intr(dev);
2244 else
2245 DRM_ERROR("Unexpected DE Misc interrupt\n");
Ben Widawskyabd58f02013-11-02 21:07:09 -07002246 }
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002247 else
2248 DRM_ERROR("The master control interrupt lied (DE MISC)!\n");
Ben Widawskyabd58f02013-11-02 21:07:09 -07002249 }
2250
Daniel Vetter6d766f02013-11-07 14:49:55 +01002251 if (master_ctl & GEN8_DE_PORT_IRQ) {
2252 tmp = I915_READ(GEN8_DE_PORT_IIR);
Daniel Vetter6d766f02013-11-07 14:49:55 +01002253 if (tmp) {
Shashank Sharmad04a4922014-08-22 17:40:41 +05302254 bool found = false;
2255
Daniel Vetter6d766f02013-11-07 14:49:55 +01002256 I915_WRITE(GEN8_DE_PORT_IIR, tmp);
2257 ret = IRQ_HANDLED;
Jesse Barnes88e04702014-11-13 17:51:48 +00002258
Shashank Sharmad04a4922014-08-22 17:40:41 +05302259 if (tmp & aux_mask) {
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002260 dp_aux_irq_handler(dev);
Shashank Sharmad04a4922014-08-22 17:40:41 +05302261 found = true;
2262 }
2263
2264 if (IS_BROXTON(dev) && tmp & BXT_DE_PORT_HOTPLUG_MASK) {
2265 bxt_hpd_handler(dev, tmp);
2266 found = true;
2267 }
2268
Shashank Sharma9e637432014-08-22 17:40:43 +05302269 if (IS_BROXTON(dev) && (tmp & BXT_DE_PORT_GMBUS)) {
2270 gmbus_irq_handler(dev);
2271 found = true;
2272 }
2273
Shashank Sharmad04a4922014-08-22 17:40:41 +05302274 if (!found)
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002275 DRM_ERROR("Unexpected DE Port interrupt\n");
Daniel Vetter6d766f02013-11-07 14:49:55 +01002276 }
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002277 else
2278 DRM_ERROR("The master control interrupt lied (DE PORT)!\n");
Daniel Vetter6d766f02013-11-07 14:49:55 +01002279 }
2280
Damien Lespiau055e3932014-08-18 13:49:10 +01002281 for_each_pipe(dev_priv, pipe) {
Damien Lespiau770de832014-03-20 20:45:01 +00002282 uint32_t pipe_iir, flip_done = 0, fault_errors = 0;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002283
Daniel Vetterc42664c2013-11-07 11:05:40 +01002284 if (!(master_ctl & GEN8_DE_PIPE_IRQ(pipe)))
2285 continue;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002286
Daniel Vetterc42664c2013-11-07 11:05:40 +01002287 pipe_iir = I915_READ(GEN8_DE_PIPE_IIR(pipe));
Daniel Vetterc42664c2013-11-07 11:05:40 +01002288 if (pipe_iir) {
2289 ret = IRQ_HANDLED;
2290 I915_WRITE(GEN8_DE_PIPE_IIR(pipe), pipe_iir);
Damien Lespiau770de832014-03-20 20:45:01 +00002291
Chris Wilsond6bbafa2014-09-05 07:13:24 +01002292 if (pipe_iir & GEN8_PIPE_VBLANK &&
2293 intel_pipe_handle_vblank(dev, pipe))
2294 intel_check_page_flip(dev, pipe);
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002295
Damien Lespiau770de832014-03-20 20:45:01 +00002296 if (IS_GEN9(dev))
2297 flip_done = pipe_iir & GEN9_PIPE_PLANE1_FLIP_DONE;
2298 else
2299 flip_done = pipe_iir & GEN8_PIPE_PRIMARY_FLIP_DONE;
2300
2301 if (flip_done) {
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002302 intel_prepare_page_flip(dev, pipe);
2303 intel_finish_page_flip_plane(dev, pipe);
2304 }
2305
2306 if (pipe_iir & GEN8_PIPE_CDCLK_CRC_DONE)
2307 hsw_pipe_crc_irq_handler(dev, pipe);
2308
Daniel Vetter1f7247c2014-09-30 10:56:48 +02002309 if (pipe_iir & GEN8_PIPE_FIFO_UNDERRUN)
2310 intel_cpu_fifo_underrun_irq_handler(dev_priv,
2311 pipe);
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002312
Damien Lespiau770de832014-03-20 20:45:01 +00002313
2314 if (IS_GEN9(dev))
2315 fault_errors = pipe_iir & GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
2316 else
2317 fault_errors = pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
2318
2319 if (fault_errors)
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002320 DRM_ERROR("Fault errors on pipe %c\n: 0x%08x",
2321 pipe_name(pipe),
2322 pipe_iir & GEN8_DE_PIPE_IRQ_FAULT_ERRORS);
Daniel Vetterc42664c2013-11-07 11:05:40 +01002323 } else
Ben Widawskyabd58f02013-11-02 21:07:09 -07002324 DRM_ERROR("The master control interrupt lied (DE PIPE)!\n");
2325 }
2326
Shashank Sharma266ea3d2014-08-22 17:40:42 +05302327 if (HAS_PCH_SPLIT(dev) && !HAS_PCH_NOP(dev) &&
2328 master_ctl & GEN8_DE_PCH_IRQ) {
Daniel Vetter92d03a82013-11-07 11:05:43 +01002329 /*
2330 * FIXME(BDW): Assume for now that the new interrupt handling
2331 * scheme also closed the SDE interrupt handling race we've seen
2332 * on older pch-split platforms. But this needs testing.
2333 */
2334 u32 pch_iir = I915_READ(SDEIIR);
Daniel Vetter92d03a82013-11-07 11:05:43 +01002335 if (pch_iir) {
2336 I915_WRITE(SDEIIR, pch_iir);
2337 ret = IRQ_HANDLED;
Oscar Mateo38cc46d2014-06-16 16:10:59 +01002338 cpt_irq_handler(dev, pch_iir);
2339 } else
2340 DRM_ERROR("The master control interrupt lied (SDE)!\n");
2341
Daniel Vetter92d03a82013-11-07 11:05:43 +01002342 }
2343
Chris Wilsoncb0d2052015-04-07 16:21:04 +01002344 I915_WRITE_FW(GEN8_MASTER_IRQ, GEN8_MASTER_IRQ_CONTROL);
2345 POSTING_READ_FW(GEN8_MASTER_IRQ);
Ben Widawskyabd58f02013-11-02 21:07:09 -07002346
2347 return ret;
2348}
2349
Daniel Vetter17e1df02013-09-08 21:57:13 +02002350static void i915_error_wake_up(struct drm_i915_private *dev_priv,
2351 bool reset_completed)
2352{
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002353 struct intel_engine_cs *ring;
Daniel Vetter17e1df02013-09-08 21:57:13 +02002354 int i;
2355
2356 /*
2357 * Notify all waiters for GPU completion events that reset state has
2358 * been changed, and that they need to restart their wait after
2359 * checking for potential errors (and bail out to drop locks if there is
2360 * a gpu reset pending so that i915_error_work_func can acquire them).
2361 */
2362
2363 /* Wake up __wait_seqno, potentially holding dev->struct_mutex. */
2364 for_each_ring(ring, dev_priv, i)
2365 wake_up_all(&ring->irq_queue);
2366
2367 /* Wake up intel_crtc_wait_for_pending_flips, holding crtc->mutex. */
2368 wake_up_all(&dev_priv->pending_flip_queue);
2369
2370 /*
2371 * Signal tasks blocked in i915_gem_wait_for_error that the pending
2372 * reset state is cleared.
2373 */
2374 if (reset_completed)
2375 wake_up_all(&dev_priv->gpu_error.reset_queue);
2376}
2377
Jesse Barnes8a905232009-07-11 16:48:03 -04002378/**
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002379 * i915_reset_and_wakeup - do process context error handling work
Jesse Barnes8a905232009-07-11 16:48:03 -04002380 *
2381 * Fire an error uevent so userspace can see that a hang or error
2382 * was detected.
2383 */
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002384static void i915_reset_and_wakeup(struct drm_device *dev)
Jesse Barnes8a905232009-07-11 16:48:03 -04002385{
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002386 struct drm_i915_private *dev_priv = to_i915(dev);
2387 struct i915_gpu_error *error = &dev_priv->gpu_error;
Ben Widawskycce723e2013-07-19 09:16:42 -07002388 char *error_event[] = { I915_ERROR_UEVENT "=1", NULL };
2389 char *reset_event[] = { I915_RESET_UEVENT "=1", NULL };
2390 char *reset_done_event[] = { I915_ERROR_UEVENT "=0", NULL };
Daniel Vetter17e1df02013-09-08 21:57:13 +02002391 int ret;
Jesse Barnes8a905232009-07-11 16:48:03 -04002392
Dave Airlie5bdebb12013-10-11 14:07:25 +10002393 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE, error_event);
Jesse Barnes8a905232009-07-11 16:48:03 -04002394
Daniel Vetter7db0ba22012-12-06 16:23:37 +01002395 /*
2396 * Note that there's only one work item which does gpu resets, so we
2397 * need not worry about concurrent gpu resets potentially incrementing
2398 * error->reset_counter twice. We only need to take care of another
2399 * racing irq/hangcheck declaring the gpu dead for a second time. A
2400 * quick check for that is good enough: schedule_work ensures the
2401 * correct ordering between hang detection and this work item, and since
2402 * the reset in-progress bit is only ever set by code outside of this
2403 * work we don't need to worry about any other races.
2404 */
2405 if (i915_reset_in_progress(error) && !i915_terminally_wedged(error)) {
Chris Wilsonf803aa52010-09-19 12:38:26 +01002406 DRM_DEBUG_DRIVER("resetting chip\n");
Dave Airlie5bdebb12013-10-11 14:07:25 +10002407 kobject_uevent_env(&dev->primary->kdev->kobj, KOBJ_CHANGE,
Daniel Vetter7db0ba22012-12-06 16:23:37 +01002408 reset_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002409
Daniel Vetter17e1df02013-09-08 21:57:13 +02002410 /*
Imre Deakf454c692014-04-23 01:09:04 +03002411 * In most cases it's guaranteed that we get here with an RPM
2412 * reference held, for example because there is a pending GPU
2413 * request that won't finish until the reset is done. This
2414 * isn't the case at least when we get here by doing a
2415 * simulated reset via debugs, so get an RPM reference.
2416 */
2417 intel_runtime_pm_get(dev_priv);
Ville Syrjälä75147472014-11-24 18:28:11 +02002418
2419 intel_prepare_reset(dev);
2420
Imre Deakf454c692014-04-23 01:09:04 +03002421 /*
Daniel Vetter17e1df02013-09-08 21:57:13 +02002422 * All state reset _must_ be completed before we update the
2423 * reset counter, for otherwise waiters might miss the reset
2424 * pending state and not properly drop locks, resulting in
2425 * deadlocks with the reset work.
2426 */
Daniel Vetterf69061b2012-12-06 09:01:42 +01002427 ret = i915_reset(dev);
2428
Ville Syrjälä75147472014-11-24 18:28:11 +02002429 intel_finish_reset(dev);
Daniel Vetter17e1df02013-09-08 21:57:13 +02002430
Imre Deakf454c692014-04-23 01:09:04 +03002431 intel_runtime_pm_put(dev_priv);
2432
Daniel Vetterf69061b2012-12-06 09:01:42 +01002433 if (ret == 0) {
2434 /*
2435 * After all the gem state is reset, increment the reset
2436 * counter and wake up everyone waiting for the reset to
2437 * complete.
2438 *
2439 * Since unlock operations are a one-sided barrier only,
2440 * we need to insert a barrier here to order any seqno
2441 * updates before
2442 * the counter increment.
2443 */
Peter Zijlstra4e857c52014-03-17 18:06:10 +01002444 smp_mb__before_atomic();
Daniel Vetterf69061b2012-12-06 09:01:42 +01002445 atomic_inc(&dev_priv->gpu_error.reset_counter);
2446
Dave Airlie5bdebb12013-10-11 14:07:25 +10002447 kobject_uevent_env(&dev->primary->kdev->kobj,
Daniel Vetterf69061b2012-12-06 09:01:42 +01002448 KOBJ_CHANGE, reset_done_event);
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002449 } else {
Mika Kuoppala2ac0f452013-11-12 14:44:19 +02002450 atomic_set_mask(I915_WEDGED, &error->reset_counter);
Ben Gamarif316a422009-09-14 17:48:46 -04002451 }
Daniel Vetter1f83fee2012-11-15 17:17:22 +01002452
Daniel Vetter17e1df02013-09-08 21:57:13 +02002453 /*
2454 * Note: The wake_up also serves as a memory barrier so that
2455 * waiters see the update value of the reset counter atomic_t.
2456 */
2457 i915_error_wake_up(dev_priv, true);
Ben Gamarif316a422009-09-14 17:48:46 -04002458 }
Jesse Barnes8a905232009-07-11 16:48:03 -04002459}
2460
Chris Wilson35aed2e2010-05-27 13:18:12 +01002461static void i915_report_and_clear_eir(struct drm_device *dev)
Jesse Barnes8a905232009-07-11 16:48:03 -04002462{
2463 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskybd9854f2012-08-23 15:18:09 -07002464 uint32_t instdone[I915_NUM_INSTDONE_REG];
Jesse Barnes8a905232009-07-11 16:48:03 -04002465 u32 eir = I915_READ(EIR);
Ben Widawsky050ee912012-08-22 11:32:15 -07002466 int pipe, i;
Jesse Barnes8a905232009-07-11 16:48:03 -04002467
Chris Wilson35aed2e2010-05-27 13:18:12 +01002468 if (!eir)
2469 return;
Jesse Barnes8a905232009-07-11 16:48:03 -04002470
Joe Perchesa70491c2012-03-18 13:00:11 -07002471 pr_err("render error detected, EIR: 0x%08x\n", eir);
Jesse Barnes8a905232009-07-11 16:48:03 -04002472
Ben Widawskybd9854f2012-08-23 15:18:09 -07002473 i915_get_extra_instdone(dev, instdone);
2474
Jesse Barnes8a905232009-07-11 16:48:03 -04002475 if (IS_G4X(dev)) {
2476 if (eir & (GM45_ERROR_MEM_PRIV | GM45_ERROR_CP_PRIV)) {
2477 u32 ipeir = I915_READ(IPEIR_I965);
2478
Joe Perchesa70491c2012-03-18 13:00:11 -07002479 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2480 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Ben Widawsky050ee912012-08-22 11:32:15 -07002481 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2482 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Joe Perchesa70491c2012-03-18 13:00:11 -07002483 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07002484 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04002485 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002486 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04002487 }
2488 if (eir & GM45_ERROR_PAGE_TABLE) {
2489 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07002490 pr_err("page table error\n");
2491 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04002492 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002493 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04002494 }
2495 }
2496
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002497 if (!IS_GEN2(dev)) {
Jesse Barnes8a905232009-07-11 16:48:03 -04002498 if (eir & I915_ERROR_PAGE_TABLE) {
2499 u32 pgtbl_err = I915_READ(PGTBL_ER);
Joe Perchesa70491c2012-03-18 13:00:11 -07002500 pr_err("page table error\n");
2501 pr_err(" PGTBL_ER: 0x%08x\n", pgtbl_err);
Jesse Barnes8a905232009-07-11 16:48:03 -04002502 I915_WRITE(PGTBL_ER, pgtbl_err);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002503 POSTING_READ(PGTBL_ER);
Jesse Barnes8a905232009-07-11 16:48:03 -04002504 }
2505 }
2506
2507 if (eir & I915_ERROR_MEMORY_REFRESH) {
Joe Perchesa70491c2012-03-18 13:00:11 -07002508 pr_err("memory refresh error:\n");
Damien Lespiau055e3932014-08-18 13:49:10 +01002509 for_each_pipe(dev_priv, pipe)
Joe Perchesa70491c2012-03-18 13:00:11 -07002510 pr_err("pipe %c stat: 0x%08x\n",
Jesse Barnes9db4a9c2011-02-07 12:26:52 -08002511 pipe_name(pipe), I915_READ(PIPESTAT(pipe)));
Jesse Barnes8a905232009-07-11 16:48:03 -04002512 /* pipestat has already been acked */
2513 }
2514 if (eir & I915_ERROR_INSTRUCTION) {
Joe Perchesa70491c2012-03-18 13:00:11 -07002515 pr_err("instruction error\n");
2516 pr_err(" INSTPM: 0x%08x\n", I915_READ(INSTPM));
Ben Widawsky050ee912012-08-22 11:32:15 -07002517 for (i = 0; i < ARRAY_SIZE(instdone); i++)
2518 pr_err(" INSTDONE_%d: 0x%08x\n", i, instdone[i]);
Chris Wilsona6c45cf2010-09-17 00:32:17 +01002519 if (INTEL_INFO(dev)->gen < 4) {
Jesse Barnes8a905232009-07-11 16:48:03 -04002520 u32 ipeir = I915_READ(IPEIR);
2521
Joe Perchesa70491c2012-03-18 13:00:11 -07002522 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR));
2523 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR));
Joe Perchesa70491c2012-03-18 13:00:11 -07002524 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD));
Jesse Barnes8a905232009-07-11 16:48:03 -04002525 I915_WRITE(IPEIR, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002526 POSTING_READ(IPEIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04002527 } else {
2528 u32 ipeir = I915_READ(IPEIR_I965);
2529
Joe Perchesa70491c2012-03-18 13:00:11 -07002530 pr_err(" IPEIR: 0x%08x\n", I915_READ(IPEIR_I965));
2531 pr_err(" IPEHR: 0x%08x\n", I915_READ(IPEHR_I965));
Joe Perchesa70491c2012-03-18 13:00:11 -07002532 pr_err(" INSTPS: 0x%08x\n", I915_READ(INSTPS));
Joe Perchesa70491c2012-03-18 13:00:11 -07002533 pr_err(" ACTHD: 0x%08x\n", I915_READ(ACTHD_I965));
Jesse Barnes8a905232009-07-11 16:48:03 -04002534 I915_WRITE(IPEIR_I965, ipeir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002535 POSTING_READ(IPEIR_I965);
Jesse Barnes8a905232009-07-11 16:48:03 -04002536 }
2537 }
2538
2539 I915_WRITE(EIR, eir);
Chris Wilson3143a2b2010-11-16 15:55:10 +00002540 POSTING_READ(EIR);
Jesse Barnes8a905232009-07-11 16:48:03 -04002541 eir = I915_READ(EIR);
2542 if (eir) {
2543 /*
2544 * some errors might have become stuck,
2545 * mask them.
2546 */
2547 DRM_ERROR("EIR stuck: 0x%08x, masking\n", eir);
2548 I915_WRITE(EMR, I915_READ(EMR) | eir);
2549 I915_WRITE(IIR, I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
2550 }
Chris Wilson35aed2e2010-05-27 13:18:12 +01002551}
2552
2553/**
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002554 * i915_handle_error - handle a gpu error
Chris Wilson35aed2e2010-05-27 13:18:12 +01002555 * @dev: drm device
2556 *
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002557 * Do some basic checking of regsiter state at error time and
Chris Wilson35aed2e2010-05-27 13:18:12 +01002558 * dump it to the syslog. Also call i915_capture_error_state() to make
2559 * sure we get a record and make it available in debugfs. Fire a uevent
2560 * so userspace knows something bad happened (should trigger collection
2561 * of a ring dump etc.).
2562 */
Mika Kuoppala58174462014-02-25 17:11:26 +02002563void i915_handle_error(struct drm_device *dev, bool wedged,
2564 const char *fmt, ...)
Chris Wilson35aed2e2010-05-27 13:18:12 +01002565{
2566 struct drm_i915_private *dev_priv = dev->dev_private;
Mika Kuoppala58174462014-02-25 17:11:26 +02002567 va_list args;
2568 char error_msg[80];
Chris Wilson35aed2e2010-05-27 13:18:12 +01002569
Mika Kuoppala58174462014-02-25 17:11:26 +02002570 va_start(args, fmt);
2571 vscnprintf(error_msg, sizeof(error_msg), fmt, args);
2572 va_end(args);
2573
2574 i915_capture_error_state(dev, wedged, error_msg);
Chris Wilson35aed2e2010-05-27 13:18:12 +01002575 i915_report_and_clear_eir(dev);
Jesse Barnes8a905232009-07-11 16:48:03 -04002576
Ben Gamariba1234d2009-09-14 17:48:47 -04002577 if (wedged) {
Daniel Vetterf69061b2012-12-06 09:01:42 +01002578 atomic_set_mask(I915_RESET_IN_PROGRESS_FLAG,
2579 &dev_priv->gpu_error.reset_counter);
Ben Gamariba1234d2009-09-14 17:48:47 -04002580
Ben Gamari11ed50e2009-09-14 17:48:45 -04002581 /*
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002582 * Wakeup waiting processes so that the reset function
2583 * i915_reset_and_wakeup doesn't deadlock trying to grab
2584 * various locks. By bumping the reset counter first, the woken
Daniel Vetter17e1df02013-09-08 21:57:13 +02002585 * processes will see a reset in progress and back off,
2586 * releasing their locks and then wait for the reset completion.
2587 * We must do this for _all_ gpu waiters that might hold locks
2588 * that the reset work needs to acquire.
2589 *
2590 * Note: The wake_up serves as the required memory barrier to
2591 * ensure that the waiters see the updated value of the reset
2592 * counter atomic_t.
Ben Gamari11ed50e2009-09-14 17:48:45 -04002593 */
Daniel Vetter17e1df02013-09-08 21:57:13 +02002594 i915_error_wake_up(dev_priv, false);
Ben Gamari11ed50e2009-09-14 17:48:45 -04002595 }
2596
Mika Kuoppalab8d24a02015-01-28 17:03:14 +02002597 i915_reset_and_wakeup(dev);
Jesse Barnes8a905232009-07-11 16:48:03 -04002598}
2599
Keith Packard42f52ef2008-10-18 19:39:29 -07002600/* Called from drm generic code, passed 'crtc' which
2601 * we use as a pipe index
2602 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002603static int i915_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002604{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002605 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07002606 unsigned long irqflags;
Jesse Barnes71e0ffa2009-01-08 10:42:15 -08002607
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002608 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002609 if (INTEL_INFO(dev)->gen >= 4)
Keith Packard7c463582008-11-04 02:03:27 -08002610 i915_enable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002611 PIPE_START_VBLANK_INTERRUPT_STATUS);
Keith Packarde9d21d72008-10-16 11:31:38 -07002612 else
Keith Packard7c463582008-11-04 02:03:27 -08002613 i915_enable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002614 PIPE_VBLANK_INTERRUPT_STATUS);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002615 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
Chris Wilson8692d00e2011-02-05 10:08:21 +00002616
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002617 return 0;
2618}
2619
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002620static int ironlake_enable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002621{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002622 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf796cf82011-04-07 13:58:17 -07002623 unsigned long irqflags;
Paulo Zanonib5184212013-07-12 20:00:08 -03002624 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
Daniel Vetter40da17c22013-10-21 18:04:36 +02002625 DE_PIPE_VBLANK(pipe);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002626
Jesse Barnesf796cf82011-04-07 13:58:17 -07002627 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Paulo Zanonib5184212013-07-12 20:00:08 -03002628 ironlake_enable_display_irq(dev_priv, bit);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002629 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2630
2631 return 0;
2632}
2633
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002634static int valleyview_enable_vblank(struct drm_device *dev, int pipe)
2635{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002636 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002637 unsigned long irqflags;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002638
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002639 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002640 i915_enable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002641 PIPE_START_VBLANK_INTERRUPT_STATUS);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002642 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2643
2644 return 0;
2645}
2646
Ben Widawskyabd58f02013-11-02 21:07:09 -07002647static int gen8_enable_vblank(struct drm_device *dev, int pipe)
2648{
2649 struct drm_i915_private *dev_priv = dev->dev_private;
2650 unsigned long irqflags;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002651
Ben Widawskyabd58f02013-11-02 21:07:09 -07002652 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Daniel Vetter7167d7c2013-11-07 11:05:45 +01002653 dev_priv->de_irq_mask[pipe] &= ~GEN8_PIPE_VBLANK;
2654 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2655 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
Ben Widawskyabd58f02013-11-02 21:07:09 -07002656 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2657 return 0;
2658}
2659
Keith Packard42f52ef2008-10-18 19:39:29 -07002660/* Called from drm generic code, passed 'crtc' which
2661 * we use as a pipe index
2662 */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002663static void i915_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002664{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002665 struct drm_i915_private *dev_priv = dev->dev_private;
Keith Packarde9d21d72008-10-16 11:31:38 -07002666 unsigned long irqflags;
Jesse Barnes0a3e67a2008-09-30 12:14:26 -07002667
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002668 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002669 i915_disable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002670 PIPE_VBLANK_INTERRUPT_STATUS |
2671 PIPE_START_VBLANK_INTERRUPT_STATUS);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002672 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2673}
2674
Jesse Barnesf71d4af2011-06-28 13:00:41 -07002675static void ironlake_disable_vblank(struct drm_device *dev, int pipe)
Jesse Barnesf796cf82011-04-07 13:58:17 -07002676{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002677 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnesf796cf82011-04-07 13:58:17 -07002678 unsigned long irqflags;
Paulo Zanonib5184212013-07-12 20:00:08 -03002679 uint32_t bit = (INTEL_INFO(dev)->gen >= 7) ? DE_PIPE_VBLANK_IVB(pipe) :
Daniel Vetter40da17c22013-10-21 18:04:36 +02002680 DE_PIPE_VBLANK(pipe);
Jesse Barnesf796cf82011-04-07 13:58:17 -07002681
2682 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Paulo Zanonib5184212013-07-12 20:00:08 -03002683 ironlake_disable_display_irq(dev_priv, bit);
Jesse Barnesb1f14ad2011-04-06 12:13:38 -07002684 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2685}
2686
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002687static void valleyview_disable_vblank(struct drm_device *dev, int pipe)
2688{
Jani Nikula2d1013d2014-03-31 14:27:17 +03002689 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002690 unsigned long irqflags;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002691
2692 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Jesse Barnes31acc7f2012-06-20 10:53:11 -07002693 i915_disable_pipestat(dev_priv, pipe,
Imre Deak755e9012014-02-10 18:42:47 +02002694 PIPE_START_VBLANK_INTERRUPT_STATUS);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07002695 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2696}
2697
Ben Widawskyabd58f02013-11-02 21:07:09 -07002698static void gen8_disable_vblank(struct drm_device *dev, int pipe)
2699{
2700 struct drm_i915_private *dev_priv = dev->dev_private;
2701 unsigned long irqflags;
Ben Widawskyabd58f02013-11-02 21:07:09 -07002702
Ben Widawskyabd58f02013-11-02 21:07:09 -07002703 spin_lock_irqsave(&dev_priv->irq_lock, irqflags);
Daniel Vetter7167d7c2013-11-07 11:05:45 +01002704 dev_priv->de_irq_mask[pipe] |= GEN8_PIPE_VBLANK;
2705 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]);
2706 POSTING_READ(GEN8_DE_PIPE_IMR(pipe));
Ben Widawskyabd58f02013-11-02 21:07:09 -07002707 spin_unlock_irqrestore(&dev_priv->irq_lock, irqflags);
2708}
2709
John Harrison44cdd6d2014-11-24 18:49:40 +00002710static struct drm_i915_gem_request *
2711ring_last_request(struct intel_engine_cs *ring)
Zou Nan hai852835f2010-05-21 09:08:56 +08002712{
Chris Wilson893eead2010-10-27 14:44:35 +01002713 return list_entry(ring->request_list.prev,
John Harrison44cdd6d2014-11-24 18:49:40 +00002714 struct drm_i915_gem_request, list);
Chris Wilson893eead2010-10-27 14:44:35 +01002715}
2716
Chris Wilson9107e9d2013-06-10 11:20:20 +01002717static bool
John Harrison44cdd6d2014-11-24 18:49:40 +00002718ring_idle(struct intel_engine_cs *ring)
Chris Wilson893eead2010-10-27 14:44:35 +01002719{
Chris Wilson9107e9d2013-06-10 11:20:20 +01002720 return (list_empty(&ring->request_list) ||
John Harrison1b5a4332014-11-24 18:49:42 +00002721 i915_gem_request_completed(ring_last_request(ring), false));
Ben Gamarif65d9422009-09-14 17:48:44 -04002722}
2723
Daniel Vettera028c4b2014-03-15 00:08:56 +01002724static bool
2725ipehr_is_semaphore_wait(struct drm_device *dev, u32 ipehr)
2726{
2727 if (INTEL_INFO(dev)->gen >= 8) {
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002728 return (ipehr >> 23) == 0x1c;
Daniel Vettera028c4b2014-03-15 00:08:56 +01002729 } else {
2730 ipehr &= ~MI_SEMAPHORE_SYNC_MASK;
2731 return ipehr == (MI_SEMAPHORE_MBOX | MI_SEMAPHORE_COMPARE |
2732 MI_SEMAPHORE_REGISTER);
2733 }
2734}
2735
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002736static struct intel_engine_cs *
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002737semaphore_wait_to_signaller_ring(struct intel_engine_cs *ring, u32 ipehr, u64 offset)
Daniel Vetter921d42e2014-03-18 10:26:04 +01002738{
2739 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002740 struct intel_engine_cs *signaller;
Daniel Vetter921d42e2014-03-18 10:26:04 +01002741 int i;
2742
2743 if (INTEL_INFO(dev_priv->dev)->gen >= 8) {
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002744 for_each_ring(signaller, dev_priv, i) {
2745 if (ring == signaller)
2746 continue;
2747
2748 if (offset == signaller->semaphore.signal_ggtt[ring->id])
2749 return signaller;
2750 }
Daniel Vetter921d42e2014-03-18 10:26:04 +01002751 } else {
2752 u32 sync_bits = ipehr & MI_SEMAPHORE_SYNC_MASK;
2753
2754 for_each_ring(signaller, dev_priv, i) {
2755 if(ring == signaller)
2756 continue;
2757
Ben Widawskyebc348b2014-04-29 14:52:28 -07002758 if (sync_bits == signaller->semaphore.mbox.wait[ring->id])
Daniel Vetter921d42e2014-03-18 10:26:04 +01002759 return signaller;
2760 }
2761 }
2762
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002763 DRM_ERROR("No signaller ring found for ring %i, ipehr 0x%08x, offset 0x%016llx\n",
2764 ring->id, ipehr, offset);
Daniel Vetter921d42e2014-03-18 10:26:04 +01002765
2766 return NULL;
2767}
2768
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002769static struct intel_engine_cs *
2770semaphore_waits_for(struct intel_engine_cs *ring, u32 *seqno)
Chris Wilsona24a11e2013-03-14 17:52:05 +02002771{
2772 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Daniel Vetter88fe4292014-03-15 00:08:55 +01002773 u32 cmd, ipehr, head;
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002774 u64 offset = 0;
2775 int i, backwards;
Chris Wilsona24a11e2013-03-14 17:52:05 +02002776
2777 ipehr = I915_READ(RING_IPEHR(ring->mmio_base));
Daniel Vettera028c4b2014-03-15 00:08:56 +01002778 if (!ipehr_is_semaphore_wait(ring->dev, ipehr))
Chris Wilson6274f212013-06-10 11:20:21 +01002779 return NULL;
Chris Wilsona24a11e2013-03-14 17:52:05 +02002780
Daniel Vetter88fe4292014-03-15 00:08:55 +01002781 /*
2782 * HEAD is likely pointing to the dword after the actual command,
2783 * so scan backwards until we find the MBOX. But limit it to just 3
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002784 * or 4 dwords depending on the semaphore wait command size.
2785 * Note that we don't care about ACTHD here since that might
Daniel Vetter88fe4292014-03-15 00:08:55 +01002786 * point at at batch, and semaphores are always emitted into the
2787 * ringbuffer itself.
Chris Wilsona24a11e2013-03-14 17:52:05 +02002788 */
Daniel Vetter88fe4292014-03-15 00:08:55 +01002789 head = I915_READ_HEAD(ring) & HEAD_ADDR;
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002790 backwards = (INTEL_INFO(ring->dev)->gen >= 8) ? 5 : 4;
Daniel Vetter88fe4292014-03-15 00:08:55 +01002791
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002792 for (i = backwards; i; --i) {
Daniel Vetter88fe4292014-03-15 00:08:55 +01002793 /*
2794 * Be paranoid and presume the hw has gone off into the wild -
2795 * our ring is smaller than what the hardware (and hence
2796 * HEAD_ADDR) allows. Also handles wrap-around.
2797 */
Oscar Mateoee1b1e52014-05-22 14:13:35 +01002798 head &= ring->buffer->size - 1;
Daniel Vetter88fe4292014-03-15 00:08:55 +01002799
2800 /* This here seems to blow up */
Oscar Mateoee1b1e52014-05-22 14:13:35 +01002801 cmd = ioread32(ring->buffer->virtual_start + head);
Chris Wilsona24a11e2013-03-14 17:52:05 +02002802 if (cmd == ipehr)
2803 break;
2804
Daniel Vetter88fe4292014-03-15 00:08:55 +01002805 head -= 4;
2806 }
Chris Wilsona24a11e2013-03-14 17:52:05 +02002807
Daniel Vetter88fe4292014-03-15 00:08:55 +01002808 if (!i)
2809 return NULL;
2810
Oscar Mateoee1b1e52014-05-22 14:13:35 +01002811 *seqno = ioread32(ring->buffer->virtual_start + head + 4) + 1;
Rodrigo Vivia6cdb932014-06-30 09:53:39 -07002812 if (INTEL_INFO(ring->dev)->gen >= 8) {
2813 offset = ioread32(ring->buffer->virtual_start + head + 12);
2814 offset <<= 32;
2815 offset = ioread32(ring->buffer->virtual_start + head + 8);
2816 }
2817 return semaphore_wait_to_signaller_ring(ring, ipehr, offset);
Chris Wilsona24a11e2013-03-14 17:52:05 +02002818}
2819
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002820static int semaphore_passed(struct intel_engine_cs *ring)
Chris Wilson6274f212013-06-10 11:20:21 +01002821{
2822 struct drm_i915_private *dev_priv = ring->dev->dev_private;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002823 struct intel_engine_cs *signaller;
Chris Wilsona0d036b2014-07-19 12:40:42 +01002824 u32 seqno;
Chris Wilson6274f212013-06-10 11:20:21 +01002825
Chris Wilson4be17382014-06-06 10:22:29 +01002826 ring->hangcheck.deadlock++;
Chris Wilson6274f212013-06-10 11:20:21 +01002827
2828 signaller = semaphore_waits_for(ring, &seqno);
Chris Wilson4be17382014-06-06 10:22:29 +01002829 if (signaller == NULL)
2830 return -1;
2831
2832 /* Prevent pathological recursion due to driver bugs */
2833 if (signaller->hangcheck.deadlock >= I915_NUM_RINGS)
Chris Wilson6274f212013-06-10 11:20:21 +01002834 return -1;
2835
Chris Wilson4be17382014-06-06 10:22:29 +01002836 if (i915_seqno_passed(signaller->get_seqno(signaller, false), seqno))
2837 return 1;
2838
Chris Wilsona0d036b2014-07-19 12:40:42 +01002839 /* cursory check for an unkickable deadlock */
2840 if (I915_READ_CTL(signaller) & RING_WAIT_SEMAPHORE &&
2841 semaphore_passed(signaller) < 0)
Chris Wilson4be17382014-06-06 10:22:29 +01002842 return -1;
2843
2844 return 0;
Chris Wilson6274f212013-06-10 11:20:21 +01002845}
2846
2847static void semaphore_clear_deadlocks(struct drm_i915_private *dev_priv)
2848{
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002849 struct intel_engine_cs *ring;
Chris Wilson6274f212013-06-10 11:20:21 +01002850 int i;
2851
2852 for_each_ring(ring, dev_priv, i)
Chris Wilson4be17382014-06-06 10:22:29 +01002853 ring->hangcheck.deadlock = 0;
Chris Wilson6274f212013-06-10 11:20:21 +01002854}
2855
Mika Kuoppalaad8beae2013-06-12 12:35:32 +03002856static enum intel_ring_hangcheck_action
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002857ring_stuck(struct intel_engine_cs *ring, u64 acthd)
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002858{
2859 struct drm_device *dev = ring->dev;
2860 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002861 u32 tmp;
2862
Mika Kuoppalaf260fe72014-08-05 17:16:26 +03002863 if (acthd != ring->hangcheck.acthd) {
2864 if (acthd > ring->hangcheck.max_acthd) {
2865 ring->hangcheck.max_acthd = acthd;
2866 return HANGCHECK_ACTIVE;
2867 }
2868
2869 return HANGCHECK_ACTIVE_LOOP;
2870 }
Chris Wilson6274f212013-06-10 11:20:21 +01002871
Chris Wilson9107e9d2013-06-10 11:20:20 +01002872 if (IS_GEN2(dev))
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002873 return HANGCHECK_HUNG;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002874
2875 /* Is the chip hanging on a WAIT_FOR_EVENT?
2876 * If so we can simply poke the RB_WAIT bit
2877 * and break the hang. This should work on
2878 * all but the second generation chipsets.
2879 */
2880 tmp = I915_READ_CTL(ring);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002881 if (tmp & RING_WAIT) {
Mika Kuoppala58174462014-02-25 17:11:26 +02002882 i915_handle_error(dev, false,
2883 "Kicking stuck wait on %s",
2884 ring->name);
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002885 I915_WRITE_CTL(ring, tmp);
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002886 return HANGCHECK_KICK;
Chris Wilson1ec14ad2010-12-04 11:30:53 +00002887 }
Chris Wilsona24a11e2013-03-14 17:52:05 +02002888
Chris Wilson6274f212013-06-10 11:20:21 +01002889 if (INTEL_INFO(dev)->gen >= 6 && tmp & RING_WAIT_SEMAPHORE) {
2890 switch (semaphore_passed(ring)) {
2891 default:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002892 return HANGCHECK_HUNG;
Chris Wilson6274f212013-06-10 11:20:21 +01002893 case 1:
Mika Kuoppala58174462014-02-25 17:11:26 +02002894 i915_handle_error(dev, false,
2895 "Kicking stuck semaphore on %s",
2896 ring->name);
Chris Wilson6274f212013-06-10 11:20:21 +01002897 I915_WRITE_CTL(ring, tmp);
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002898 return HANGCHECK_KICK;
Chris Wilson6274f212013-06-10 11:20:21 +01002899 case 0:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002900 return HANGCHECK_WAIT;
Chris Wilson6274f212013-06-10 11:20:21 +01002901 }
Chris Wilson9107e9d2013-06-10 11:20:20 +01002902 }
Mika Kuoppalaed5cbb02013-05-13 16:32:11 +03002903
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002904 return HANGCHECK_HUNG;
Mika Kuoppalaed5cbb02013-05-13 16:32:11 +03002905}
2906
Chris Wilson737b1502015-01-26 18:03:03 +02002907/*
Ben Gamarif65d9422009-09-14 17:48:44 -04002908 * This is called when the chip hasn't reported back with completed
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002909 * batchbuffers in a long time. We keep track per ring seqno progress and
2910 * if there are no progress, hangcheck score for that ring is increased.
2911 * Further, acthd is inspected to see if the ring is stuck. On stuck case
2912 * we kick the ring. If we see no progress on three subsequent calls
2913 * we assume chip is wedged and try to fix it by resetting the chip.
Ben Gamarif65d9422009-09-14 17:48:44 -04002914 */
Chris Wilson737b1502015-01-26 18:03:03 +02002915static void i915_hangcheck_elapsed(struct work_struct *work)
Ben Gamarif65d9422009-09-14 17:48:44 -04002916{
Chris Wilson737b1502015-01-26 18:03:03 +02002917 struct drm_i915_private *dev_priv =
2918 container_of(work, typeof(*dev_priv),
2919 gpu_error.hangcheck_work.work);
2920 struct drm_device *dev = dev_priv->dev;
Oscar Mateoa4872ba2014-05-22 14:13:33 +01002921 struct intel_engine_cs *ring;
Chris Wilsonb4519512012-05-11 14:29:30 +01002922 int i;
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002923 int busy_count = 0, rings_hung = 0;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002924 bool stuck[I915_NUM_RINGS] = { 0 };
2925#define BUSY 1
2926#define KICK 5
2927#define HUNG 20
Chris Wilson893eead2010-10-27 14:44:35 +01002928
Jani Nikulad330a952014-01-21 11:24:25 +02002929 if (!i915.enable_hangcheck)
Ben Widawsky3e0dc6b2011-06-29 10:26:42 -07002930 return;
2931
Chris Wilsonb4519512012-05-11 14:29:30 +01002932 for_each_ring(ring, dev_priv, i) {
Chris Wilson50877442014-03-21 12:41:53 +00002933 u64 acthd;
2934 u32 seqno;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002935 bool busy = true;
Chris Wilsonb4519512012-05-11 14:29:30 +01002936
Chris Wilson6274f212013-06-10 11:20:21 +01002937 semaphore_clear_deadlocks(dev_priv);
2938
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002939 seqno = ring->get_seqno(ring, false);
2940 acthd = intel_ring_get_active_head(ring);
Chris Wilsond1e61e72012-04-10 17:00:41 +01002941
Chris Wilson9107e9d2013-06-10 11:20:20 +01002942 if (ring->hangcheck.seqno == seqno) {
John Harrison44cdd6d2014-11-24 18:49:40 +00002943 if (ring_idle(ring)) {
Mika Kuoppalada661462013-09-06 16:03:28 +03002944 ring->hangcheck.action = HANGCHECK_IDLE;
2945
Chris Wilson9107e9d2013-06-10 11:20:20 +01002946 if (waitqueue_active(&ring->irq_queue)) {
2947 /* Issue a wake-up to catch stuck h/w. */
Chris Wilson094f9a52013-09-25 17:34:55 +01002948 if (!test_and_set_bit(ring->id, &dev_priv->gpu_error.missed_irq_rings)) {
Daniel Vetterf4adcd22013-10-28 09:24:13 +01002949 if (!(dev_priv->gpu_error.test_irq_rings & intel_ring_flag(ring)))
2950 DRM_ERROR("Hangcheck timer elapsed... %s idle\n",
2951 ring->name);
2952 else
2953 DRM_INFO("Fake missed irq on %s\n",
2954 ring->name);
Chris Wilson094f9a52013-09-25 17:34:55 +01002955 wake_up_all(&ring->irq_queue);
2956 }
2957 /* Safeguard against driver failure */
2958 ring->hangcheck.score += BUSY;
Chris Wilson9107e9d2013-06-10 11:20:20 +01002959 } else
2960 busy = false;
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002961 } else {
Chris Wilson6274f212013-06-10 11:20:21 +01002962 /* We always increment the hangcheck score
2963 * if the ring is busy and still processing
2964 * the same request, so that no single request
2965 * can run indefinitely (such as a chain of
2966 * batches). The only time we do not increment
2967 * the hangcheck score on this ring, if this
2968 * ring is in a legitimate wait for another
2969 * ring. In that case the waiting ring is a
2970 * victim and we want to be sure we catch the
2971 * right culprit. Then every time we do kick
2972 * the ring, add a small increment to the
2973 * score so that we can catch a batch that is
2974 * being repeatedly kicked and so responsible
2975 * for stalling the machine.
2976 */
Mika Kuoppalaad8beae2013-06-12 12:35:32 +03002977 ring->hangcheck.action = ring_stuck(ring,
2978 acthd);
2979
2980 switch (ring->hangcheck.action) {
Mika Kuoppalada661462013-09-06 16:03:28 +03002981 case HANGCHECK_IDLE:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002982 case HANGCHECK_WAIT:
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002983 case HANGCHECK_ACTIVE:
Mika Kuoppalaf260fe72014-08-05 17:16:26 +03002984 break;
2985 case HANGCHECK_ACTIVE_LOOP:
Jani Nikulaea04cb32013-08-11 12:44:02 +03002986 ring->hangcheck.score += BUSY;
Chris Wilson6274f212013-06-10 11:20:21 +01002987 break;
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002988 case HANGCHECK_KICK:
Jani Nikulaea04cb32013-08-11 12:44:02 +03002989 ring->hangcheck.score += KICK;
Chris Wilson6274f212013-06-10 11:20:21 +01002990 break;
Jani Nikulaf2f4d822013-08-11 12:44:01 +03002991 case HANGCHECK_HUNG:
Jani Nikulaea04cb32013-08-11 12:44:02 +03002992 ring->hangcheck.score += HUNG;
Chris Wilson6274f212013-06-10 11:20:21 +01002993 stuck[i] = true;
2994 break;
2995 }
Mika Kuoppala05407ff2013-05-30 09:04:29 +03002996 }
Chris Wilson9107e9d2013-06-10 11:20:20 +01002997 } else {
Mika Kuoppalada661462013-09-06 16:03:28 +03002998 ring->hangcheck.action = HANGCHECK_ACTIVE;
2999
Chris Wilson9107e9d2013-06-10 11:20:20 +01003000 /* Gradually reduce the count so that we catch DoS
3001 * attempts across multiple batches.
3002 */
3003 if (ring->hangcheck.score > 0)
3004 ring->hangcheck.score--;
Mika Kuoppalaf260fe72014-08-05 17:16:26 +03003005
3006 ring->hangcheck.acthd = ring->hangcheck.max_acthd = 0;
Chris Wilsond1e61e72012-04-10 17:00:41 +01003007 }
3008
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003009 ring->hangcheck.seqno = seqno;
3010 ring->hangcheck.acthd = acthd;
Chris Wilson9107e9d2013-06-10 11:20:20 +01003011 busy_count += busy;
Chris Wilson893eead2010-10-27 14:44:35 +01003012 }
Eric Anholtb9201c12010-01-08 14:25:16 -08003013
Mika Kuoppala92cab732013-05-24 17:16:07 +03003014 for_each_ring(ring, dev_priv, i) {
Mika Kuoppalab6b0fac2014-01-30 19:04:43 +02003015 if (ring->hangcheck.score >= HANGCHECK_SCORE_RING_HUNG) {
Daniel Vetterb8d88d12013-08-28 10:57:59 +02003016 DRM_INFO("%s on %s\n",
3017 stuck[i] ? "stuck" : "no progress",
3018 ring->name);
Chris Wilsona43adf02013-06-10 11:20:22 +01003019 rings_hung++;
Mika Kuoppala92cab732013-05-24 17:16:07 +03003020 }
3021 }
3022
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003023 if (rings_hung)
Mika Kuoppala58174462014-02-25 17:11:26 +02003024 return i915_handle_error(dev, true, "Ring hung");
Ben Gamarif65d9422009-09-14 17:48:44 -04003025
Mika Kuoppala05407ff2013-05-30 09:04:29 +03003026 if (busy_count)
3027 /* Reset timer case chip hangs without another request
3028 * being added */
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03003029 i915_queue_hangcheck(dev);
3030}
3031
3032void i915_queue_hangcheck(struct drm_device *dev)
3033{
Chris Wilson737b1502015-01-26 18:03:03 +02003034 struct i915_gpu_error *e = &to_i915(dev)->gpu_error;
Chris Wilson672e7b72014-11-19 09:47:19 +00003035
Jani Nikulad330a952014-01-21 11:24:25 +02003036 if (!i915.enable_hangcheck)
Mika Kuoppala10cd45b2013-07-03 17:22:08 +03003037 return;
3038
Chris Wilson737b1502015-01-26 18:03:03 +02003039 /* Don't continually defer the hangcheck so that it is always run at
3040 * least once after work has been scheduled on any ring. Otherwise,
3041 * we will ignore a hung ring if a second ring is kept busy.
3042 */
3043
3044 queue_delayed_work(e->hangcheck_wq, &e->hangcheck_work,
3045 round_jiffies_up_relative(DRM_I915_HANGCHECK_JIFFIES));
Ben Gamarif65d9422009-09-14 17:48:44 -04003046}
3047
Paulo Zanoni1c69eb42014-04-01 15:37:23 -03003048static void ibx_irq_reset(struct drm_device *dev)
Paulo Zanoni91738a92013-06-05 14:21:51 -03003049{
3050 struct drm_i915_private *dev_priv = dev->dev_private;
3051
3052 if (HAS_PCH_NOP(dev))
3053 return;
3054
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003055 GEN5_IRQ_RESET(SDE);
Paulo Zanoni105b1222014-04-01 15:37:17 -03003056
3057 if (HAS_PCH_CPT(dev) || HAS_PCH_LPT(dev))
3058 I915_WRITE(SERR_INT, 0xffffffff);
Paulo Zanoni622364b2014-04-01 15:37:22 -03003059}
Paulo Zanoni105b1222014-04-01 15:37:17 -03003060
Paulo Zanoni622364b2014-04-01 15:37:22 -03003061/*
3062 * SDEIER is also touched by the interrupt handler to work around missed PCH
3063 * interrupts. Hence we can't update it after the interrupt handler is enabled -
3064 * instead we unconditionally enable all PCH interrupt sources here, but then
3065 * only unmask them as needed with SDEIMR.
3066 *
3067 * This function needs to be called before interrupts are enabled.
3068 */
3069static void ibx_irq_pre_postinstall(struct drm_device *dev)
3070{
3071 struct drm_i915_private *dev_priv = dev->dev_private;
3072
3073 if (HAS_PCH_NOP(dev))
3074 return;
3075
3076 WARN_ON(I915_READ(SDEIER) != 0);
Paulo Zanoni91738a92013-06-05 14:21:51 -03003077 I915_WRITE(SDEIER, 0xffffffff);
3078 POSTING_READ(SDEIER);
3079}
3080
Paulo Zanoni7c4d6642014-04-01 15:37:19 -03003081static void gen5_gt_irq_reset(struct drm_device *dev)
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02003082{
3083 struct drm_i915_private *dev_priv = dev->dev_private;
3084
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003085 GEN5_IRQ_RESET(GT);
Paulo Zanonia9d356a2014-04-01 15:37:09 -03003086 if (INTEL_INFO(dev)->gen >= 6)
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003087 GEN5_IRQ_RESET(GEN6_PM);
Daniel Vetterd18ea1b2013-07-12 22:43:25 +02003088}
3089
Linus Torvalds1da177e2005-04-16 15:20:36 -07003090/* drm_dma.h hooks
3091*/
Paulo Zanonibe30b292014-04-01 15:37:25 -03003092static void ironlake_irq_reset(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003093{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003094 struct drm_i915_private *dev_priv = dev->dev_private;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003095
Paulo Zanoni0c841212014-04-01 15:37:27 -03003096 I915_WRITE(HWSTAM, 0xffffffff);
Daniel Vetterbdfcdb62012-01-05 01:05:26 +01003097
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003098 GEN5_IRQ_RESET(DE);
Paulo Zanonic6d954c2014-04-01 15:37:18 -03003099 if (IS_GEN7(dev))
3100 I915_WRITE(GEN7_ERR_INT, 0xffffffff);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003101
Paulo Zanoni7c4d6642014-04-01 15:37:19 -03003102 gen5_gt_irq_reset(dev);
Zhenyu Wangc6501562009-11-03 18:57:21 +00003103
Paulo Zanoni1c69eb42014-04-01 15:37:23 -03003104 ibx_irq_reset(dev);
Ben Widawsky7d991632013-05-28 19:22:25 -07003105}
3106
Ville Syrjälä70591a42014-10-30 19:42:58 +02003107static void vlv_display_irq_reset(struct drm_i915_private *dev_priv)
3108{
3109 enum pipe pipe;
3110
3111 I915_WRITE(PORT_HOTPLUG_EN, 0);
3112 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3113
3114 for_each_pipe(dev_priv, pipe)
3115 I915_WRITE(PIPESTAT(pipe), 0xffff);
3116
3117 GEN5_IRQ_RESET(VLV_);
3118}
3119
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003120static void valleyview_irq_preinstall(struct drm_device *dev)
3121{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003122 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003123
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003124 /* VLV magic */
3125 I915_WRITE(VLV_IMR, 0);
3126 I915_WRITE(RING_IMR(RENDER_RING_BASE), 0);
3127 I915_WRITE(RING_IMR(GEN6_BSD_RING_BASE), 0);
3128 I915_WRITE(RING_IMR(BLT_RING_BASE), 0);
3129
Paulo Zanoni7c4d6642014-04-01 15:37:19 -03003130 gen5_gt_irq_reset(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003131
Ville Syrjälä7c4cde32014-10-30 19:42:51 +02003132 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003133
Ville Syrjälä70591a42014-10-30 19:42:58 +02003134 vlv_display_irq_reset(dev_priv);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003135}
3136
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003137static void gen8_gt_irq_reset(struct drm_i915_private *dev_priv)
3138{
3139 GEN8_IRQ_RESET_NDX(GT, 0);
3140 GEN8_IRQ_RESET_NDX(GT, 1);
3141 GEN8_IRQ_RESET_NDX(GT, 2);
3142 GEN8_IRQ_RESET_NDX(GT, 3);
3143}
3144
Paulo Zanoni823f6b32014-04-01 15:37:26 -03003145static void gen8_irq_reset(struct drm_device *dev)
Ben Widawskyabd58f02013-11-02 21:07:09 -07003146{
3147 struct drm_i915_private *dev_priv = dev->dev_private;
3148 int pipe;
3149
Ben Widawskyabd58f02013-11-02 21:07:09 -07003150 I915_WRITE(GEN8_MASTER_IRQ, 0);
3151 POSTING_READ(GEN8_MASTER_IRQ);
3152
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003153 gen8_gt_irq_reset(dev_priv);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003154
Damien Lespiau055e3932014-08-18 13:49:10 +01003155 for_each_pipe(dev_priv, pipe)
Daniel Vetterf458ebb2014-09-30 10:56:39 +02003156 if (intel_display_power_is_enabled(dev_priv,
3157 POWER_DOMAIN_PIPE(pipe)))
Paulo Zanoni813bde42014-07-04 11:50:29 -03003158 GEN8_IRQ_RESET_NDX(DE_PIPE, pipe);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003159
Paulo Zanonif86f3fb2014-04-01 15:37:14 -03003160 GEN5_IRQ_RESET(GEN8_DE_PORT_);
3161 GEN5_IRQ_RESET(GEN8_DE_MISC_);
3162 GEN5_IRQ_RESET(GEN8_PCU_);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003163
Shashank Sharma266ea3d2014-08-22 17:40:42 +05303164 if (HAS_PCH_SPLIT(dev))
3165 ibx_irq_reset(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003166}
Ben Widawskyabd58f02013-11-02 21:07:09 -07003167
Damien Lespiau4c6c03b2015-03-06 18:50:48 +00003168void gen8_irq_power_well_post_enable(struct drm_i915_private *dev_priv,
3169 unsigned int pipe_mask)
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003170{
Paulo Zanoni1180e202014-10-07 18:02:52 -03003171 uint32_t extra_ier = GEN8_PIPE_VBLANK | GEN8_PIPE_FIFO_UNDERRUN;
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003172
Daniel Vetter13321782014-09-15 14:55:29 +02003173 spin_lock_irq(&dev_priv->irq_lock);
Damien Lespiaud14c0342015-03-06 18:50:51 +00003174 if (pipe_mask & 1 << PIPE_A)
3175 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_A,
3176 dev_priv->de_irq_mask[PIPE_A],
3177 ~dev_priv->de_irq_mask[PIPE_A] | extra_ier);
Damien Lespiau4c6c03b2015-03-06 18:50:48 +00003178 if (pipe_mask & 1 << PIPE_B)
3179 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_B,
3180 dev_priv->de_irq_mask[PIPE_B],
3181 ~dev_priv->de_irq_mask[PIPE_B] | extra_ier);
3182 if (pipe_mask & 1 << PIPE_C)
3183 GEN8_IRQ_INIT_NDX(DE_PIPE, PIPE_C,
3184 dev_priv->de_irq_mask[PIPE_C],
3185 ~dev_priv->de_irq_mask[PIPE_C] | extra_ier);
Daniel Vetter13321782014-09-15 14:55:29 +02003186 spin_unlock_irq(&dev_priv->irq_lock);
Paulo Zanonid49bdb02014-07-04 11:50:31 -03003187}
3188
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003189static void cherryview_irq_preinstall(struct drm_device *dev)
3190{
3191 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003192
3193 I915_WRITE(GEN8_MASTER_IRQ, 0);
3194 POSTING_READ(GEN8_MASTER_IRQ);
3195
Daniel Vetterd6e3cca2014-05-22 22:18:22 +02003196 gen8_gt_irq_reset(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003197
3198 GEN5_IRQ_RESET(GEN8_PCU_);
3199
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003200 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK_CHV);
3201
Ville Syrjälä70591a42014-10-30 19:42:58 +02003202 vlv_display_irq_reset(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003203}
3204
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003205static void ibx_hpd_irq_setup(struct drm_device *dev)
Keith Packard7fe0b972011-09-19 13:31:02 -07003206{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003207 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003208 struct intel_encoder *intel_encoder;
Daniel Vetterfee884e2013-07-04 23:35:21 +02003209 u32 hotplug_irqs, hotplug, enabled_irqs = 0;
Keith Packard7fe0b972011-09-19 13:31:02 -07003210
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003211 if (HAS_PCH_IBX(dev)) {
Daniel Vetterfee884e2013-07-04 23:35:21 +02003212 hotplug_irqs = SDE_HOTPLUG_MASK;
Damien Lespiaub2784e12014-08-05 11:29:37 +01003213 for_each_intel_encoder(dev, intel_encoder)
Egbert Eichcd569ae2013-04-16 13:36:57 +02003214 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
Daniel Vetterfee884e2013-07-04 23:35:21 +02003215 enabled_irqs |= hpd_ibx[intel_encoder->hpd_pin];
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003216 } else {
Daniel Vetterfee884e2013-07-04 23:35:21 +02003217 hotplug_irqs = SDE_HOTPLUG_MASK_CPT;
Damien Lespiaub2784e12014-08-05 11:29:37 +01003218 for_each_intel_encoder(dev, intel_encoder)
Egbert Eichcd569ae2013-04-16 13:36:57 +02003219 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
Daniel Vetterfee884e2013-07-04 23:35:21 +02003220 enabled_irqs |= hpd_cpt[intel_encoder->hpd_pin];
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003221 }
3222
Daniel Vetterfee884e2013-07-04 23:35:21 +02003223 ibx_display_interrupt_update(dev_priv, hotplug_irqs, enabled_irqs);
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003224
3225 /*
3226 * Enable digital hotplug on the PCH, and configure the DP short pulse
3227 * duration to 2ms (which is the minimum in the Display Port spec)
3228 *
3229 * This register is the same on all known PCH chips.
3230 */
Keith Packard7fe0b972011-09-19 13:31:02 -07003231 hotplug = I915_READ(PCH_PORT_HOTPLUG);
3232 hotplug &= ~(PORTD_PULSE_DURATION_MASK|PORTC_PULSE_DURATION_MASK|PORTB_PULSE_DURATION_MASK);
3233 hotplug |= PORTD_HOTPLUG_ENABLE | PORTD_PULSE_DURATION_2ms;
3234 hotplug |= PORTC_HOTPLUG_ENABLE | PORTC_PULSE_DURATION_2ms;
3235 hotplug |= PORTB_HOTPLUG_ENABLE | PORTB_PULSE_DURATION_2ms;
3236 I915_WRITE(PCH_PORT_HOTPLUG, hotplug);
3237}
3238
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02003239static void bxt_hpd_irq_setup(struct drm_device *dev)
3240{
3241 struct drm_i915_private *dev_priv = dev->dev_private;
3242 struct intel_encoder *intel_encoder;
3243 u32 hotplug_port = 0;
3244 u32 hotplug_ctrl;
3245
3246 /* Now, enable HPD */
3247 for_each_intel_encoder(dev, intel_encoder) {
3248 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark
3249 == HPD_ENABLED)
3250 hotplug_port |= hpd_bxt[intel_encoder->hpd_pin];
3251 }
3252
3253 /* Mask all HPD control bits */
3254 hotplug_ctrl = I915_READ(BXT_HOTPLUG_CTL) & ~BXT_HOTPLUG_CTL_MASK;
3255
3256 /* Enable requested port in hotplug control */
3257 /* TODO: implement (short) HPD support on port A */
3258 WARN_ON_ONCE(hotplug_port & BXT_DE_PORT_HP_DDIA);
3259 if (hotplug_port & BXT_DE_PORT_HP_DDIB)
3260 hotplug_ctrl |= BXT_DDIB_HPD_ENABLE;
3261 if (hotplug_port & BXT_DE_PORT_HP_DDIC)
3262 hotplug_ctrl |= BXT_DDIC_HPD_ENABLE;
3263 I915_WRITE(BXT_HOTPLUG_CTL, hotplug_ctrl);
3264
3265 /* Unmask DDI hotplug in IMR */
3266 hotplug_ctrl = I915_READ(GEN8_DE_PORT_IMR) & ~hotplug_port;
3267 I915_WRITE(GEN8_DE_PORT_IMR, hotplug_ctrl);
3268
3269 /* Enable DDI hotplug in IER */
3270 hotplug_ctrl = I915_READ(GEN8_DE_PORT_IER) | hotplug_port;
3271 I915_WRITE(GEN8_DE_PORT_IER, hotplug_ctrl);
3272 POSTING_READ(GEN8_DE_PORT_IER);
3273}
3274
Paulo Zanonid46da432013-02-08 17:35:15 -02003275static void ibx_irq_postinstall(struct drm_device *dev)
3276{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003277 struct drm_i915_private *dev_priv = dev->dev_private;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01003278 u32 mask;
Paulo Zanonid46da432013-02-08 17:35:15 -02003279
Daniel Vetter692a04c2013-05-29 21:43:05 +02003280 if (HAS_PCH_NOP(dev))
3281 return;
3282
Paulo Zanoni105b1222014-04-01 15:37:17 -03003283 if (HAS_PCH_IBX(dev))
Daniel Vetter5c673b62014-03-07 20:34:46 +01003284 mask = SDE_GMBUS | SDE_AUX_MASK | SDE_POISON;
Paulo Zanoni105b1222014-04-01 15:37:17 -03003285 else
Daniel Vetter5c673b62014-03-07 20:34:46 +01003286 mask = SDE_GMBUS_CPT | SDE_AUX_MASK_CPT;
Paulo Zanoni86642812013-04-12 17:57:57 -03003287
Paulo Zanoni337ba012014-04-01 15:37:16 -03003288 GEN5_ASSERT_IIR_IS_ZERO(SDEIIR);
Paulo Zanonid46da432013-02-08 17:35:15 -02003289 I915_WRITE(SDEIMR, ~mask);
Paulo Zanonid46da432013-02-08 17:35:15 -02003290}
3291
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003292static void gen5_gt_irq_postinstall(struct drm_device *dev)
3293{
3294 struct drm_i915_private *dev_priv = dev->dev_private;
3295 u32 pm_irqs, gt_irqs;
3296
3297 pm_irqs = gt_irqs = 0;
3298
3299 dev_priv->gt_irq_mask = ~0;
Ben Widawsky040d2ba2013-09-19 11:01:40 -07003300 if (HAS_L3_DPF(dev)) {
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003301 /* L3 parity interrupt is always unmasked. */
Ben Widawsky35a85ac2013-09-19 11:13:41 -07003302 dev_priv->gt_irq_mask = ~GT_PARITY_ERROR(dev);
3303 gt_irqs |= GT_PARITY_ERROR(dev);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003304 }
3305
3306 gt_irqs |= GT_RENDER_USER_INTERRUPT;
3307 if (IS_GEN5(dev)) {
3308 gt_irqs |= GT_RENDER_PIPECTL_NOTIFY_INTERRUPT |
3309 ILK_BSD_USER_INTERRUPT;
3310 } else {
3311 gt_irqs |= GT_BLT_USER_INTERRUPT | GT_BSD_USER_INTERRUPT;
3312 }
3313
Paulo Zanoni35079892014-04-01 15:37:15 -03003314 GEN5_IRQ_INIT(GT, dev_priv->gt_irq_mask, gt_irqs);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003315
3316 if (INTEL_INFO(dev)->gen >= 6) {
Imre Deak78e68d32014-12-15 18:59:27 +02003317 /*
3318 * RPS interrupts will get enabled/disabled on demand when RPS
3319 * itself is enabled/disabled.
3320 */
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003321 if (HAS_VEBOX(dev))
3322 pm_irqs |= PM_VEBOX_USER_INTERRUPT;
3323
Paulo Zanoni605cd252013-08-06 18:57:15 -03003324 dev_priv->pm_irq_mask = 0xffffffff;
Paulo Zanoni35079892014-04-01 15:37:15 -03003325 GEN5_IRQ_INIT(GEN6_PM, dev_priv->pm_irq_mask, pm_irqs);
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003326 }
3327}
3328
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003329static int ironlake_irq_postinstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003330{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003331 struct drm_i915_private *dev_priv = dev->dev_private;
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003332 u32 display_mask, extra_mask;
3333
3334 if (INTEL_INFO(dev)->gen >= 7) {
3335 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE_IVB |
3336 DE_PCH_EVENT_IVB | DE_PLANEC_FLIP_DONE_IVB |
3337 DE_PLANEB_FLIP_DONE_IVB |
Daniel Vetter5c673b62014-03-07 20:34:46 +01003338 DE_PLANEA_FLIP_DONE_IVB | DE_AUX_CHANNEL_A_IVB);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003339 extra_mask = (DE_PIPEC_VBLANK_IVB | DE_PIPEB_VBLANK_IVB |
Daniel Vetter5c673b62014-03-07 20:34:46 +01003340 DE_PIPEA_VBLANK_IVB | DE_ERR_INT_IVB);
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003341 } else {
3342 display_mask = (DE_MASTER_IRQ_CONTROL | DE_GSE | DE_PCH_EVENT |
3343 DE_PLANEA_FLIP_DONE | DE_PLANEB_FLIP_DONE |
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003344 DE_AUX_CHANNEL_A |
Daniel Vetter5b3a8562013-10-16 22:55:48 +02003345 DE_PIPEB_CRC_DONE | DE_PIPEA_CRC_DONE |
3346 DE_POISON);
Daniel Vetter5c673b62014-03-07 20:34:46 +01003347 extra_mask = DE_PIPEA_VBLANK | DE_PIPEB_VBLANK | DE_PCU_EVENT |
3348 DE_PIPEB_FIFO_UNDERRUN | DE_PIPEA_FIFO_UNDERRUN;
Paulo Zanoni8e76f8d2013-07-12 20:01:56 -03003349 }
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003350
Chris Wilson1ec14ad2010-12-04 11:30:53 +00003351 dev_priv->irq_mask = ~display_mask;
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003352
Paulo Zanoni0c841212014-04-01 15:37:27 -03003353 I915_WRITE(HWSTAM, 0xeffe);
3354
Paulo Zanoni622364b2014-04-01 15:37:22 -03003355 ibx_irq_pre_postinstall(dev);
3356
Paulo Zanoni35079892014-04-01 15:37:15 -03003357 GEN5_IRQ_INIT(DE, dev_priv->irq_mask, display_mask | extra_mask);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003358
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003359 gen5_gt_irq_postinstall(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003360
Paulo Zanonid46da432013-02-08 17:35:15 -02003361 ibx_irq_postinstall(dev);
Keith Packard7fe0b972011-09-19 13:31:02 -07003362
Jesse Barnesf97108d2010-01-29 11:27:07 -08003363 if (IS_IRONLAKE_M(dev)) {
Daniel Vetter6005ce42013-06-27 13:44:59 +02003364 /* Enable PCU event interrupts
3365 *
3366 * spinlocking not required here for correctness since interrupt
Daniel Vetter4bc9d432013-06-27 13:44:58 +02003367 * setup is guaranteed to run in single-threaded context. But we
3368 * need it to make the assert_spin_locked happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003369 spin_lock_irq(&dev_priv->irq_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -08003370 ironlake_enable_display_irq(dev_priv, DE_PCU_EVENT);
Daniel Vetterd6207432014-09-15 14:55:27 +02003371 spin_unlock_irq(&dev_priv->irq_lock);
Jesse Barnesf97108d2010-01-29 11:27:07 -08003372 }
3373
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003374 return 0;
3375}
3376
Imre Deakf8b79e52014-03-04 19:23:07 +02003377static void valleyview_display_irqs_install(struct drm_i915_private *dev_priv)
3378{
3379 u32 pipestat_mask;
3380 u32 iir_mask;
Ville Syrjälä120dda42014-10-30 19:42:57 +02003381 enum pipe pipe;
Imre Deakf8b79e52014-03-04 19:23:07 +02003382
3383 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3384 PIPE_FIFO_UNDERRUN_STATUS;
3385
Ville Syrjälä120dda42014-10-30 19:42:57 +02003386 for_each_pipe(dev_priv, pipe)
3387 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003388 POSTING_READ(PIPESTAT(PIPE_A));
3389
3390 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3391 PIPE_CRC_DONE_INTERRUPT_STATUS;
3392
Ville Syrjälä120dda42014-10-30 19:42:57 +02003393 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3394 for_each_pipe(dev_priv, pipe)
3395 i915_enable_pipestat(dev_priv, pipe, pipestat_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003396
3397 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3398 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3399 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
Ville Syrjälä120dda42014-10-30 19:42:57 +02003400 if (IS_CHERRYVIEW(dev_priv))
3401 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
Imre Deakf8b79e52014-03-04 19:23:07 +02003402 dev_priv->irq_mask &= ~iir_mask;
3403
3404 I915_WRITE(VLV_IIR, iir_mask);
3405 I915_WRITE(VLV_IIR, iir_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003406 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
Ville Syrjälä76e41862014-10-30 19:42:54 +02003407 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3408 POSTING_READ(VLV_IMR);
Imre Deakf8b79e52014-03-04 19:23:07 +02003409}
3410
3411static void valleyview_display_irqs_uninstall(struct drm_i915_private *dev_priv)
3412{
3413 u32 pipestat_mask;
3414 u32 iir_mask;
Ville Syrjälä120dda42014-10-30 19:42:57 +02003415 enum pipe pipe;
Imre Deakf8b79e52014-03-04 19:23:07 +02003416
3417 iir_mask = I915_DISPLAY_PORT_INTERRUPT |
3418 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
Imre Deak6c7fba02014-03-10 19:44:48 +02003419 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT;
Ville Syrjälä120dda42014-10-30 19:42:57 +02003420 if (IS_CHERRYVIEW(dev_priv))
3421 iir_mask |= I915_DISPLAY_PIPE_C_EVENT_INTERRUPT;
Imre Deakf8b79e52014-03-04 19:23:07 +02003422
3423 dev_priv->irq_mask |= iir_mask;
Imre Deakf8b79e52014-03-04 19:23:07 +02003424 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
Ville Syrjälä76e41862014-10-30 19:42:54 +02003425 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003426 I915_WRITE(VLV_IIR, iir_mask);
3427 I915_WRITE(VLV_IIR, iir_mask);
3428 POSTING_READ(VLV_IIR);
3429
3430 pipestat_mask = PLANE_FLIP_DONE_INT_STATUS_VLV |
3431 PIPE_CRC_DONE_INTERRUPT_STATUS;
3432
Ville Syrjälä120dda42014-10-30 19:42:57 +02003433 i915_disable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
3434 for_each_pipe(dev_priv, pipe)
3435 i915_disable_pipestat(dev_priv, pipe, pipestat_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003436
3437 pipestat_mask = PIPESTAT_INT_STATUS_MASK |
3438 PIPE_FIFO_UNDERRUN_STATUS;
Ville Syrjälä120dda42014-10-30 19:42:57 +02003439
3440 for_each_pipe(dev_priv, pipe)
3441 I915_WRITE(PIPESTAT(pipe), pipestat_mask);
Imre Deakf8b79e52014-03-04 19:23:07 +02003442 POSTING_READ(PIPESTAT(PIPE_A));
3443}
3444
3445void valleyview_enable_display_irqs(struct drm_i915_private *dev_priv)
3446{
3447 assert_spin_locked(&dev_priv->irq_lock);
3448
3449 if (dev_priv->display_irqs_enabled)
3450 return;
3451
3452 dev_priv->display_irqs_enabled = true;
3453
Imre Deak950eaba2014-09-08 15:21:09 +03003454 if (intel_irqs_enabled(dev_priv))
Imre Deakf8b79e52014-03-04 19:23:07 +02003455 valleyview_display_irqs_install(dev_priv);
3456}
3457
3458void valleyview_disable_display_irqs(struct drm_i915_private *dev_priv)
3459{
3460 assert_spin_locked(&dev_priv->irq_lock);
3461
3462 if (!dev_priv->display_irqs_enabled)
3463 return;
3464
3465 dev_priv->display_irqs_enabled = false;
3466
Imre Deak950eaba2014-09-08 15:21:09 +03003467 if (intel_irqs_enabled(dev_priv))
Imre Deakf8b79e52014-03-04 19:23:07 +02003468 valleyview_display_irqs_uninstall(dev_priv);
3469}
3470
Ville Syrjälä0e6c9a92014-10-30 19:43:00 +02003471static void vlv_display_irq_postinstall(struct drm_i915_private *dev_priv)
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003472{
Imre Deakf8b79e52014-03-04 19:23:07 +02003473 dev_priv->irq_mask = ~0;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003474
Daniel Vetter20afbda2012-12-11 14:05:07 +01003475 I915_WRITE(PORT_HOTPLUG_EN, 0);
3476 POSTING_READ(PORT_HOTPLUG_EN);
3477
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003478 I915_WRITE(VLV_IIR, 0xffffffff);
Ville Syrjälä76e41862014-10-30 19:42:54 +02003479 I915_WRITE(VLV_IIR, 0xffffffff);
3480 I915_WRITE(VLV_IER, ~dev_priv->irq_mask);
3481 I915_WRITE(VLV_IMR, dev_priv->irq_mask);
3482 POSTING_READ(VLV_IMR);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003483
Daniel Vetterb79480b2013-06-27 17:52:10 +02003484 /* Interrupt setup is already guaranteed to be single-threaded, this is
3485 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003486 spin_lock_irq(&dev_priv->irq_lock);
Imre Deakf8b79e52014-03-04 19:23:07 +02003487 if (dev_priv->display_irqs_enabled)
3488 valleyview_display_irqs_install(dev_priv);
Daniel Vetterd6207432014-09-15 14:55:27 +02003489 spin_unlock_irq(&dev_priv->irq_lock);
Ville Syrjälä0e6c9a92014-10-30 19:43:00 +02003490}
3491
3492static int valleyview_irq_postinstall(struct drm_device *dev)
3493{
3494 struct drm_i915_private *dev_priv = dev->dev_private;
3495
3496 vlv_display_irq_postinstall(dev_priv);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003497
Daniel Vetter0a9a8c92013-07-12 22:43:26 +02003498 gen5_gt_irq_postinstall(dev);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003499
3500 /* ack & enable invalid PTE error interrupts */
3501#if 0 /* FIXME: add support to irq handler for checking these bits */
3502 I915_WRITE(DPINVGTT, DPINVGTT_STATUS_MASK);
3503 I915_WRITE(DPINVGTT, DPINVGTT_EN_MASK);
3504#endif
3505
3506 I915_WRITE(VLV_MASTER_IER, MASTER_INTERRUPT_ENABLE);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003507
3508 return 0;
3509}
3510
Ben Widawskyabd58f02013-11-02 21:07:09 -07003511static void gen8_gt_irq_postinstall(struct drm_i915_private *dev_priv)
3512{
Ben Widawskyabd58f02013-11-02 21:07:09 -07003513 /* These are interrupts we'll toggle with the ring mask register */
3514 uint32_t gt_interrupts[] = {
3515 GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003516 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT |
Ben Widawskyabd58f02013-11-02 21:07:09 -07003517 GT_RENDER_L3_PARITY_ERROR_INTERRUPT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003518 GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT |
3519 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT,
Ben Widawskyabd58f02013-11-02 21:07:09 -07003520 GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
Oscar Mateo73d477f2014-07-24 17:04:31 +01003521 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT |
3522 GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT |
3523 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT,
Ben Widawskyabd58f02013-11-02 21:07:09 -07003524 0,
Oscar Mateo73d477f2014-07-24 17:04:31 +01003525 GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT |
3526 GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT
Ben Widawskyabd58f02013-11-02 21:07:09 -07003527 };
3528
Ben Widawsky09610212014-05-15 20:58:08 +03003529 dev_priv->pm_irq_mask = 0xffffffff;
Deepak S9a2d2d82014-08-22 08:32:40 +05303530 GEN8_IRQ_INIT_NDX(GT, 0, ~gt_interrupts[0], gt_interrupts[0]);
3531 GEN8_IRQ_INIT_NDX(GT, 1, ~gt_interrupts[1], gt_interrupts[1]);
Imre Deak78e68d32014-12-15 18:59:27 +02003532 /*
3533 * RPS interrupts will get enabled/disabled on demand when RPS itself
3534 * is enabled/disabled.
3535 */
3536 GEN8_IRQ_INIT_NDX(GT, 2, dev_priv->pm_irq_mask, 0);
Deepak S9a2d2d82014-08-22 08:32:40 +05303537 GEN8_IRQ_INIT_NDX(GT, 3, ~gt_interrupts[3], gt_interrupts[3]);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003538}
3539
3540static void gen8_de_irq_postinstall(struct drm_i915_private *dev_priv)
3541{
Damien Lespiau770de832014-03-20 20:45:01 +00003542 uint32_t de_pipe_masked = GEN8_PIPE_CDCLK_CRC_DONE;
3543 uint32_t de_pipe_enables;
Ben Widawskyabd58f02013-11-02 21:07:09 -07003544 int pipe;
Shashank Sharma9e637432014-08-22 17:40:43 +05303545 u32 de_port_en = GEN8_AUX_CHANNEL_A;
Damien Lespiau770de832014-03-20 20:45:01 +00003546
Jesse Barnes88e04702014-11-13 17:51:48 +00003547 if (IS_GEN9(dev_priv)) {
Damien Lespiau770de832014-03-20 20:45:01 +00003548 de_pipe_masked |= GEN9_PIPE_PLANE1_FLIP_DONE |
3549 GEN9_DE_PIPE_IRQ_FAULT_ERRORS;
Shashank Sharma9e637432014-08-22 17:40:43 +05303550 de_port_en |= GEN9_AUX_CHANNEL_B | GEN9_AUX_CHANNEL_C |
Jesse Barnes88e04702014-11-13 17:51:48 +00003551 GEN9_AUX_CHANNEL_D;
Shashank Sharma9e637432014-08-22 17:40:43 +05303552
3553 if (IS_BROXTON(dev_priv))
3554 de_port_en |= BXT_DE_PORT_GMBUS;
Jesse Barnes88e04702014-11-13 17:51:48 +00003555 } else
Damien Lespiau770de832014-03-20 20:45:01 +00003556 de_pipe_masked |= GEN8_PIPE_PRIMARY_FLIP_DONE |
3557 GEN8_DE_PIPE_IRQ_FAULT_ERRORS;
3558
3559 de_pipe_enables = de_pipe_masked | GEN8_PIPE_VBLANK |
3560 GEN8_PIPE_FIFO_UNDERRUN;
3561
Daniel Vetter13b3a0a2013-11-07 15:31:52 +01003562 dev_priv->de_irq_mask[PIPE_A] = ~de_pipe_masked;
3563 dev_priv->de_irq_mask[PIPE_B] = ~de_pipe_masked;
3564 dev_priv->de_irq_mask[PIPE_C] = ~de_pipe_masked;
Ben Widawskyabd58f02013-11-02 21:07:09 -07003565
Damien Lespiau055e3932014-08-18 13:49:10 +01003566 for_each_pipe(dev_priv, pipe)
Daniel Vetterf458ebb2014-09-30 10:56:39 +02003567 if (intel_display_power_is_enabled(dev_priv,
Paulo Zanoni813bde42014-07-04 11:50:29 -03003568 POWER_DOMAIN_PIPE(pipe)))
3569 GEN8_IRQ_INIT_NDX(DE_PIPE, pipe,
3570 dev_priv->de_irq_mask[pipe],
3571 de_pipe_enables);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003572
Shashank Sharma9e637432014-08-22 17:40:43 +05303573 GEN5_IRQ_INIT(GEN8_DE_PORT_, ~de_port_en, de_port_en);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003574}
3575
3576static int gen8_irq_postinstall(struct drm_device *dev)
3577{
3578 struct drm_i915_private *dev_priv = dev->dev_private;
3579
Shashank Sharma266ea3d2014-08-22 17:40:42 +05303580 if (HAS_PCH_SPLIT(dev))
3581 ibx_irq_pre_postinstall(dev);
Paulo Zanoni622364b2014-04-01 15:37:22 -03003582
Ben Widawskyabd58f02013-11-02 21:07:09 -07003583 gen8_gt_irq_postinstall(dev_priv);
3584 gen8_de_irq_postinstall(dev_priv);
3585
Shashank Sharma266ea3d2014-08-22 17:40:42 +05303586 if (HAS_PCH_SPLIT(dev))
3587 ibx_irq_postinstall(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003588
3589 I915_WRITE(GEN8_MASTER_IRQ, DE_MASTER_IRQ_CONTROL);
3590 POSTING_READ(GEN8_MASTER_IRQ);
3591
3592 return 0;
3593}
3594
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003595static int cherryview_irq_postinstall(struct drm_device *dev)
3596{
3597 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003598
Ville Syrjäläc2b66792014-10-30 19:43:02 +02003599 vlv_display_irq_postinstall(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003600
3601 gen8_gt_irq_postinstall(dev_priv);
3602
3603 I915_WRITE(GEN8_MASTER_IRQ, MASTER_INTERRUPT_ENABLE);
3604 POSTING_READ(GEN8_MASTER_IRQ);
3605
3606 return 0;
3607}
3608
Ben Widawskyabd58f02013-11-02 21:07:09 -07003609static void gen8_irq_uninstall(struct drm_device *dev)
3610{
3611 struct drm_i915_private *dev_priv = dev->dev_private;
Ben Widawskyabd58f02013-11-02 21:07:09 -07003612
3613 if (!dev_priv)
3614 return;
3615
Paulo Zanoni823f6b32014-04-01 15:37:26 -03003616 gen8_irq_reset(dev);
Ben Widawskyabd58f02013-11-02 21:07:09 -07003617}
3618
Ville Syrjälä8ea0be42014-10-30 19:42:59 +02003619static void vlv_display_irq_uninstall(struct drm_i915_private *dev_priv)
3620{
3621 /* Interrupt setup is already guaranteed to be single-threaded, this is
3622 * just to make the assert_spin_locked check happy. */
3623 spin_lock_irq(&dev_priv->irq_lock);
3624 if (dev_priv->display_irqs_enabled)
3625 valleyview_display_irqs_uninstall(dev_priv);
3626 spin_unlock_irq(&dev_priv->irq_lock);
3627
3628 vlv_display_irq_reset(dev_priv);
3629
Imre Deakc352d1b2014-11-20 16:05:55 +02003630 dev_priv->irq_mask = ~0;
Ville Syrjälä8ea0be42014-10-30 19:42:59 +02003631}
3632
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003633static void valleyview_irq_uninstall(struct drm_device *dev)
3634{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003635 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003636
3637 if (!dev_priv)
3638 return;
3639
Imre Deak843d0e72014-04-14 20:24:23 +03003640 I915_WRITE(VLV_MASTER_IER, 0);
3641
Ville Syrjälä893fce82014-10-30 19:42:56 +02003642 gen5_gt_irq_reset(dev);
3643
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003644 I915_WRITE(HWSTAM, 0xffffffff);
Imre Deakf8b79e52014-03-04 19:23:07 +02003645
Ville Syrjälä8ea0be42014-10-30 19:42:59 +02003646 vlv_display_irq_uninstall(dev_priv);
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07003647}
3648
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003649static void cherryview_irq_uninstall(struct drm_device *dev)
3650{
3651 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003652
3653 if (!dev_priv)
3654 return;
3655
3656 I915_WRITE(GEN8_MASTER_IRQ, 0);
3657 POSTING_READ(GEN8_MASTER_IRQ);
3658
Ville Syrjäläa2c30fb2014-10-30 19:42:52 +02003659 gen8_gt_irq_reset(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003660
Ville Syrjäläa2c30fb2014-10-30 19:42:52 +02003661 GEN5_IRQ_RESET(GEN8_PCU_);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003662
Ville Syrjäläc2b66792014-10-30 19:43:02 +02003663 vlv_display_irq_uninstall(dev_priv);
Ville Syrjälä43f328d2014-04-09 20:40:52 +03003664}
3665
Jesse Barnesf71d4af2011-06-28 13:00:41 -07003666static void ironlake_irq_uninstall(struct drm_device *dev)
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003667{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003668 struct drm_i915_private *dev_priv = dev->dev_private;
Jesse Barnes46979952011-04-07 13:53:55 -07003669
3670 if (!dev_priv)
3671 return;
3672
Paulo Zanonibe30b292014-04-01 15:37:25 -03003673 ironlake_irq_reset(dev);
Zhenyu Wang036a4a72009-06-08 14:40:19 +08003674}
3675
Chris Wilsonc2798b12012-04-22 21:13:57 +01003676static void i8xx_irq_preinstall(struct drm_device * dev)
3677{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003678 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003679 int pipe;
3680
Damien Lespiau055e3932014-08-18 13:49:10 +01003681 for_each_pipe(dev_priv, pipe)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003682 I915_WRITE(PIPESTAT(pipe), 0);
3683 I915_WRITE16(IMR, 0xffff);
3684 I915_WRITE16(IER, 0x0);
3685 POSTING_READ16(IER);
3686}
3687
3688static int i8xx_irq_postinstall(struct drm_device *dev)
3689{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003690 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003691
Chris Wilsonc2798b12012-04-22 21:13:57 +01003692 I915_WRITE16(EMR,
3693 ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3694
3695 /* Unmask the interrupts that we always want on. */
3696 dev_priv->irq_mask =
3697 ~(I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3698 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3699 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
Daniel Vetter37ef01a2015-04-01 13:43:46 +02003700 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003701 I915_WRITE16(IMR, dev_priv->irq_mask);
3702
3703 I915_WRITE16(IER,
3704 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3705 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
Chris Wilsonc2798b12012-04-22 21:13:57 +01003706 I915_USER_INTERRUPT);
3707 POSTING_READ16(IER);
3708
Daniel Vetter379ef822013-10-16 22:55:56 +02003709 /* Interrupt setup is already guaranteed to be single-threaded, this is
3710 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003711 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02003712 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3713 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02003714 spin_unlock_irq(&dev_priv->irq_lock);
Daniel Vetter379ef822013-10-16 22:55:56 +02003715
Chris Wilsonc2798b12012-04-22 21:13:57 +01003716 return 0;
3717}
3718
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003719/*
3720 * Returns true when a page flip has completed.
3721 */
3722static bool i8xx_handle_vblank(struct drm_device *dev,
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003723 int plane, int pipe, u32 iir)
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003724{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003725 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003726 u16 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003727
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03003728 if (!intel_pipe_handle_vblank(dev, pipe))
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003729 return false;
3730
3731 if ((iir & flip_pending) == 0)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003732 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003733
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003734 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3735 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3736 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3737 * the flip is completed (no longer pending). Since this doesn't raise
3738 * an interrupt per se, we watch for the change at vblank.
3739 */
3740 if (I915_READ16(ISR) & flip_pending)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003741 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003742
Ville Syrjälä7d475592014-12-17 23:08:03 +02003743 intel_prepare_page_flip(dev, plane);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003744 intel_finish_page_flip(dev, pipe);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003745 return true;
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003746
3747check_page_flip:
3748 intel_check_page_flip(dev, pipe);
3749 return false;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003750}
3751
Daniel Vetterff1f5252012-10-02 15:10:55 +02003752static irqreturn_t i8xx_irq_handler(int irq, void *arg)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003753{
Daniel Vetter45a83f82014-05-12 19:17:55 +02003754 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03003755 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003756 u16 iir, new_iir;
3757 u32 pipe_stats[2];
Chris Wilsonc2798b12012-04-22 21:13:57 +01003758 int pipe;
3759 u16 flip_mask =
3760 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3761 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
3762
Imre Deak2dd2a882015-02-24 11:14:30 +02003763 if (!intel_irqs_enabled(dev_priv))
3764 return IRQ_NONE;
3765
Chris Wilsonc2798b12012-04-22 21:13:57 +01003766 iir = I915_READ16(IIR);
3767 if (iir == 0)
3768 return IRQ_NONE;
3769
3770 while (iir & ~flip_mask) {
3771 /* Can't rely on pipestat interrupt bit in iir as it might
3772 * have been cleared after the pipestat interrupt was received.
3773 * It doesn't set the bit in iir again, but it still produces
3774 * interrupts (for non-MSI).
3775 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02003776 spin_lock(&dev_priv->irq_lock);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003777 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Daniel Vetteraaecdf62014-11-04 15:52:22 +01003778 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003779
Damien Lespiau055e3932014-08-18 13:49:10 +01003780 for_each_pipe(dev_priv, pipe) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01003781 int reg = PIPESTAT(pipe);
3782 pipe_stats[pipe] = I915_READ(reg);
3783
3784 /*
3785 * Clear the PIPE*STAT regs before the IIR
3786 */
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02003787 if (pipe_stats[pipe] & 0x8000ffff)
Chris Wilsonc2798b12012-04-22 21:13:57 +01003788 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003789 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02003790 spin_unlock(&dev_priv->irq_lock);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003791
3792 I915_WRITE16(IIR, iir & ~flip_mask);
3793 new_iir = I915_READ16(IIR); /* Flush posted writes */
3794
Chris Wilsonc2798b12012-04-22 21:13:57 +01003795 if (iir & I915_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01003796 notify_ring(&dev_priv->ring[RCS]);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003797
Damien Lespiau055e3932014-08-18 13:49:10 +01003798 for_each_pipe(dev_priv, pipe) {
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003799 int plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01003800 if (HAS_FBC(dev))
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003801 plane = !plane;
3802
Daniel Vetter4356d582013-10-16 22:55:55 +02003803 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä1f1c2e22013-11-28 17:30:01 +02003804 i8xx_handle_vblank(dev, plane, pipe, iir))
3805 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
Chris Wilsonc2798b12012-04-22 21:13:57 +01003806
Daniel Vetter4356d582013-10-16 22:55:55 +02003807 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Daniel Vetter277de952013-10-18 16:37:07 +02003808 i9xx_pipe_crc_irq_handler(dev, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02003809
Daniel Vetter1f7247c2014-09-30 10:56:48 +02003810 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
3811 intel_cpu_fifo_underrun_irq_handler(dev_priv,
3812 pipe);
Daniel Vetter4356d582013-10-16 22:55:55 +02003813 }
Chris Wilsonc2798b12012-04-22 21:13:57 +01003814
3815 iir = new_iir;
3816 }
3817
3818 return IRQ_HANDLED;
3819}
3820
3821static void i8xx_irq_uninstall(struct drm_device * dev)
3822{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003823 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonc2798b12012-04-22 21:13:57 +01003824 int pipe;
3825
Damien Lespiau055e3932014-08-18 13:49:10 +01003826 for_each_pipe(dev_priv, pipe) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01003827 /* Clear enable bits; then clear status bits */
3828 I915_WRITE(PIPESTAT(pipe), 0);
3829 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
3830 }
3831 I915_WRITE16(IMR, 0xffff);
3832 I915_WRITE16(IER, 0x0);
3833 I915_WRITE16(IIR, I915_READ16(IIR));
3834}
3835
Chris Wilsona266c7d2012-04-24 22:59:44 +01003836static void i915_irq_preinstall(struct drm_device * dev)
3837{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003838 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003839 int pipe;
3840
Chris Wilsona266c7d2012-04-24 22:59:44 +01003841 if (I915_HAS_HOTPLUG(dev)) {
3842 I915_WRITE(PORT_HOTPLUG_EN, 0);
3843 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
3844 }
3845
Chris Wilson00d98eb2012-04-24 22:59:48 +01003846 I915_WRITE16(HWSTAM, 0xeffe);
Damien Lespiau055e3932014-08-18 13:49:10 +01003847 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003848 I915_WRITE(PIPESTAT(pipe), 0);
3849 I915_WRITE(IMR, 0xffffffff);
3850 I915_WRITE(IER, 0x0);
3851 POSTING_READ(IER);
3852}
3853
3854static int i915_irq_postinstall(struct drm_device *dev)
3855{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003856 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson38bde182012-04-24 22:59:50 +01003857 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003858
Chris Wilson38bde182012-04-24 22:59:50 +01003859 I915_WRITE(EMR, ~(I915_ERROR_PAGE_TABLE | I915_ERROR_MEMORY_REFRESH));
3860
3861 /* Unmask the interrupts that we always want on. */
3862 dev_priv->irq_mask =
3863 ~(I915_ASLE_INTERRUPT |
3864 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3865 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
3866 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
Daniel Vetter37ef01a2015-04-01 13:43:46 +02003867 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilson38bde182012-04-24 22:59:50 +01003868
3869 enable_mask =
3870 I915_ASLE_INTERRUPT |
3871 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
3872 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
Chris Wilson38bde182012-04-24 22:59:50 +01003873 I915_USER_INTERRUPT;
3874
Chris Wilsona266c7d2012-04-24 22:59:44 +01003875 if (I915_HAS_HOTPLUG(dev)) {
Daniel Vetter20afbda2012-12-11 14:05:07 +01003876 I915_WRITE(PORT_HOTPLUG_EN, 0);
3877 POSTING_READ(PORT_HOTPLUG_EN);
3878
Chris Wilsona266c7d2012-04-24 22:59:44 +01003879 /* Enable in IER... */
3880 enable_mask |= I915_DISPLAY_PORT_INTERRUPT;
3881 /* and unmask in IMR */
3882 dev_priv->irq_mask &= ~I915_DISPLAY_PORT_INTERRUPT;
3883 }
3884
Chris Wilsona266c7d2012-04-24 22:59:44 +01003885 I915_WRITE(IMR, dev_priv->irq_mask);
3886 I915_WRITE(IER, enable_mask);
3887 POSTING_READ(IER);
3888
Jani Nikulaf49e38d2013-04-29 13:02:54 +03003889 i915_enable_asle_pipestat(dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01003890
Daniel Vetter379ef822013-10-16 22:55:56 +02003891 /* Interrupt setup is already guaranteed to be single-threaded, this is
3892 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02003893 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02003894 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
3895 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02003896 spin_unlock_irq(&dev_priv->irq_lock);
Daniel Vetter379ef822013-10-16 22:55:56 +02003897
Daniel Vetter20afbda2012-12-11 14:05:07 +01003898 return 0;
3899}
3900
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003901/*
3902 * Returns true when a page flip has completed.
3903 */
3904static bool i915_handle_vblank(struct drm_device *dev,
3905 int plane, int pipe, u32 iir)
3906{
Jani Nikula2d1013d2014-03-31 14:27:17 +03003907 struct drm_i915_private *dev_priv = dev->dev_private;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003908 u32 flip_pending = DISPLAY_PLANE_FLIP_PENDING(plane);
3909
Ville Syrjälä8d7849d2014-04-29 13:35:46 +03003910 if (!intel_pipe_handle_vblank(dev, pipe))
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003911 return false;
3912
3913 if ((iir & flip_pending) == 0)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003914 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003915
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003916 /* We detect FlipDone by looking for the change in PendingFlip from '1'
3917 * to '0' on the following vblank, i.e. IIR has the Pendingflip
3918 * asserted following the MI_DISPLAY_FLIP, but ISR is deasserted, hence
3919 * the flip is completed (no longer pending). Since this doesn't raise
3920 * an interrupt per se, we watch for the change at vblank.
3921 */
3922 if (I915_READ(ISR) & flip_pending)
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003923 goto check_page_flip;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003924
Ville Syrjälä7d475592014-12-17 23:08:03 +02003925 intel_prepare_page_flip(dev, plane);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003926 intel_finish_page_flip(dev, pipe);
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003927 return true;
Chris Wilsond6bbafa2014-09-05 07:13:24 +01003928
3929check_page_flip:
3930 intel_check_page_flip(dev, pipe);
3931 return false;
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003932}
3933
Daniel Vetterff1f5252012-10-02 15:10:55 +02003934static irqreturn_t i915_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01003935{
Daniel Vetter45a83f82014-05-12 19:17:55 +02003936 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03003937 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilson8291ee92012-04-24 22:59:47 +01003938 u32 iir, new_iir, pipe_stats[I915_MAX_PIPES];
Chris Wilson38bde182012-04-24 22:59:50 +01003939 u32 flip_mask =
3940 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
3941 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilson38bde182012-04-24 22:59:50 +01003942 int pipe, ret = IRQ_NONE;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003943
Imre Deak2dd2a882015-02-24 11:14:30 +02003944 if (!intel_irqs_enabled(dev_priv))
3945 return IRQ_NONE;
3946
Chris Wilsona266c7d2012-04-24 22:59:44 +01003947 iir = I915_READ(IIR);
Chris Wilson38bde182012-04-24 22:59:50 +01003948 do {
3949 bool irq_received = (iir & ~flip_mask) != 0;
Chris Wilson8291ee92012-04-24 22:59:47 +01003950 bool blc_event = false;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003951
3952 /* Can't rely on pipestat interrupt bit in iir as it might
3953 * have been cleared after the pipestat interrupt was received.
3954 * It doesn't set the bit in iir again, but it still produces
3955 * interrupts (for non-MSI).
3956 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02003957 spin_lock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003958 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Daniel Vetteraaecdf62014-11-04 15:52:22 +01003959 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003960
Damien Lespiau055e3932014-08-18 13:49:10 +01003961 for_each_pipe(dev_priv, pipe) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01003962 int reg = PIPESTAT(pipe);
3963 pipe_stats[pipe] = I915_READ(reg);
3964
Chris Wilson38bde182012-04-24 22:59:50 +01003965 /* Clear the PIPE*STAT regs before the IIR */
Chris Wilsona266c7d2012-04-24 22:59:44 +01003966 if (pipe_stats[pipe] & 0x8000ffff) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01003967 I915_WRITE(reg, pipe_stats[pipe]);
Chris Wilson38bde182012-04-24 22:59:50 +01003968 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01003969 }
3970 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02003971 spin_unlock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003972
3973 if (!irq_received)
3974 break;
3975
Chris Wilsona266c7d2012-04-24 22:59:44 +01003976 /* Consume port. Then clear IIR or we'll miss events */
Ville Syrjälä16c6c562014-04-01 10:54:36 +03003977 if (I915_HAS_HOTPLUG(dev) &&
3978 iir & I915_DISPLAY_PORT_INTERRUPT)
3979 i9xx_hpd_irq_handler(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003980
Chris Wilson38bde182012-04-24 22:59:50 +01003981 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003982 new_iir = I915_READ(IIR); /* Flush posted writes */
3983
Chris Wilsona266c7d2012-04-24 22:59:44 +01003984 if (iir & I915_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01003985 notify_ring(&dev_priv->ring[RCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003986
Damien Lespiau055e3932014-08-18 13:49:10 +01003987 for_each_pipe(dev_priv, pipe) {
Chris Wilson38bde182012-04-24 22:59:50 +01003988 int plane = pipe;
Daniel Vetter3a77c4c2014-01-10 08:50:12 +01003989 if (HAS_FBC(dev))
Chris Wilson38bde182012-04-24 22:59:50 +01003990 plane = !plane;
Ville Syrjälä5e2032d2013-02-19 15:16:38 +02003991
Ville Syrjälä90a72f82013-02-19 23:16:44 +02003992 if (pipe_stats[pipe] & PIPE_VBLANK_INTERRUPT_STATUS &&
3993 i915_handle_vblank(dev, plane, pipe, iir))
3994 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(plane);
Chris Wilsona266c7d2012-04-24 22:59:44 +01003995
3996 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
3997 blc_event = true;
Daniel Vetter4356d582013-10-16 22:55:55 +02003998
3999 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Daniel Vetter277de952013-10-18 16:37:07 +02004000 i9xx_pipe_crc_irq_handler(dev, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004001
Daniel Vetter1f7247c2014-09-30 10:56:48 +02004002 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4003 intel_cpu_fifo_underrun_irq_handler(dev_priv,
4004 pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004005 }
4006
Chris Wilsona266c7d2012-04-24 22:59:44 +01004007 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4008 intel_opregion_asle_intr(dev);
4009
4010 /* With MSI, interrupts are only generated when iir
4011 * transitions from zero to nonzero. If another bit got
4012 * set while we were handling the existing iir bits, then
4013 * we would never get another interrupt.
4014 *
4015 * This is fine on non-MSI as well, as if we hit this path
4016 * we avoid exiting the interrupt handler only to generate
4017 * another one.
4018 *
4019 * Note that for MSI this could cause a stray interrupt report
4020 * if an interrupt landed in the time between writing IIR and
4021 * the posting read. This should be rare enough to never
4022 * trigger the 99% of 100,000 interrupts test for disabling
4023 * stray interrupts.
4024 */
Chris Wilson38bde182012-04-24 22:59:50 +01004025 ret = IRQ_HANDLED;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004026 iir = new_iir;
Chris Wilson38bde182012-04-24 22:59:50 +01004027 } while (iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004028
4029 return ret;
4030}
4031
4032static void i915_irq_uninstall(struct drm_device * dev)
4033{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004034 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004035 int pipe;
4036
Chris Wilsona266c7d2012-04-24 22:59:44 +01004037 if (I915_HAS_HOTPLUG(dev)) {
4038 I915_WRITE(PORT_HOTPLUG_EN, 0);
4039 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
4040 }
4041
Chris Wilson00d98eb2012-04-24 22:59:48 +01004042 I915_WRITE16(HWSTAM, 0xffff);
Damien Lespiau055e3932014-08-18 13:49:10 +01004043 for_each_pipe(dev_priv, pipe) {
Chris Wilson55b39752012-04-24 22:59:49 +01004044 /* Clear enable bits; then clear status bits */
Chris Wilsona266c7d2012-04-24 22:59:44 +01004045 I915_WRITE(PIPESTAT(pipe), 0);
Chris Wilson55b39752012-04-24 22:59:49 +01004046 I915_WRITE(PIPESTAT(pipe), I915_READ(PIPESTAT(pipe)));
4047 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01004048 I915_WRITE(IMR, 0xffffffff);
4049 I915_WRITE(IER, 0x0);
4050
Chris Wilsona266c7d2012-04-24 22:59:44 +01004051 I915_WRITE(IIR, I915_READ(IIR));
4052}
4053
4054static void i965_irq_preinstall(struct drm_device * dev)
4055{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004056 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004057 int pipe;
4058
Chris Wilsonadca4732012-05-11 18:01:31 +01004059 I915_WRITE(PORT_HOTPLUG_EN, 0);
4060 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01004061
4062 I915_WRITE(HWSTAM, 0xeffe);
Damien Lespiau055e3932014-08-18 13:49:10 +01004063 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004064 I915_WRITE(PIPESTAT(pipe), 0);
4065 I915_WRITE(IMR, 0xffffffff);
4066 I915_WRITE(IER, 0x0);
4067 POSTING_READ(IER);
4068}
4069
4070static int i965_irq_postinstall(struct drm_device *dev)
4071{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004072 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004073 u32 enable_mask;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004074 u32 error_mask;
4075
Chris Wilsona266c7d2012-04-24 22:59:44 +01004076 /* Unmask the interrupts that we always want on. */
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004077 dev_priv->irq_mask = ~(I915_ASLE_INTERRUPT |
Chris Wilsonadca4732012-05-11 18:01:31 +01004078 I915_DISPLAY_PORT_INTERRUPT |
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004079 I915_DISPLAY_PIPE_A_EVENT_INTERRUPT |
4080 I915_DISPLAY_PIPE_B_EVENT_INTERRUPT |
4081 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4082 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT |
4083 I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT);
4084
4085 enable_mask = ~dev_priv->irq_mask;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02004086 enable_mask &= ~(I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4087 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT);
Chris Wilsonbbba0a92012-04-24 22:59:51 +01004088 enable_mask |= I915_USER_INTERRUPT;
4089
4090 if (IS_G4X(dev))
4091 enable_mask |= I915_BSD_USER_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004092
Daniel Vetterb79480b2013-06-27 17:52:10 +02004093 /* Interrupt setup is already guaranteed to be single-threaded, this is
4094 * just to make the assert_spin_locked check happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02004095 spin_lock_irq(&dev_priv->irq_lock);
Imre Deak755e9012014-02-10 18:42:47 +02004096 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_GMBUS_INTERRUPT_STATUS);
4097 i915_enable_pipestat(dev_priv, PIPE_A, PIPE_CRC_DONE_INTERRUPT_STATUS);
4098 i915_enable_pipestat(dev_priv, PIPE_B, PIPE_CRC_DONE_INTERRUPT_STATUS);
Daniel Vetterd6207432014-09-15 14:55:27 +02004099 spin_unlock_irq(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004100
Chris Wilsona266c7d2012-04-24 22:59:44 +01004101 /*
4102 * Enable some error detection, note the instruction error mask
4103 * bit is reserved, so we leave it masked.
4104 */
4105 if (IS_G4X(dev)) {
4106 error_mask = ~(GM45_ERROR_PAGE_TABLE |
4107 GM45_ERROR_MEM_PRIV |
4108 GM45_ERROR_CP_PRIV |
4109 I915_ERROR_MEMORY_REFRESH);
4110 } else {
4111 error_mask = ~(I915_ERROR_PAGE_TABLE |
4112 I915_ERROR_MEMORY_REFRESH);
4113 }
4114 I915_WRITE(EMR, error_mask);
4115
4116 I915_WRITE(IMR, dev_priv->irq_mask);
4117 I915_WRITE(IER, enable_mask);
4118 POSTING_READ(IER);
4119
Daniel Vetter20afbda2012-12-11 14:05:07 +01004120 I915_WRITE(PORT_HOTPLUG_EN, 0);
4121 POSTING_READ(PORT_HOTPLUG_EN);
4122
Jani Nikulaf49e38d2013-04-29 13:02:54 +03004123 i915_enable_asle_pipestat(dev);
Daniel Vetter20afbda2012-12-11 14:05:07 +01004124
4125 return 0;
4126}
4127
Egbert Eichbac56d52013-02-25 12:06:51 -05004128static void i915_hpd_irq_setup(struct drm_device *dev)
Daniel Vetter20afbda2012-12-11 14:05:07 +01004129{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004130 struct drm_i915_private *dev_priv = dev->dev_private;
Egbert Eichcd569ae2013-04-16 13:36:57 +02004131 struct intel_encoder *intel_encoder;
Daniel Vetter20afbda2012-12-11 14:05:07 +01004132 u32 hotplug_en;
4133
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02004134 assert_spin_locked(&dev_priv->irq_lock);
4135
Ville Syrjälä778eb332015-01-09 14:21:13 +02004136 hotplug_en = I915_READ(PORT_HOTPLUG_EN);
4137 hotplug_en &= ~HOTPLUG_INT_EN_MASK;
4138 /* Note HDMI and DP share hotplug bits */
4139 /* enable bits are the same for all generations */
4140 for_each_intel_encoder(dev, intel_encoder)
4141 if (dev_priv->hpd_stats[intel_encoder->hpd_pin].hpd_mark == HPD_ENABLED)
4142 hotplug_en |= hpd_mask_i915[intel_encoder->hpd_pin];
4143 /* Programming the CRT detection parameters tends
4144 to generate a spurious hotplug event about three
4145 seconds later. So just do it once.
4146 */
4147 if (IS_G4X(dev))
4148 hotplug_en |= CRT_HOTPLUG_ACTIVATION_PERIOD_64;
4149 hotplug_en &= ~CRT_HOTPLUG_VOLTAGE_COMPARE_MASK;
4150 hotplug_en |= CRT_HOTPLUG_VOLTAGE_COMPARE_50;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004151
Ville Syrjälä778eb332015-01-09 14:21:13 +02004152 /* Ignore TV since it's buggy */
4153 I915_WRITE(PORT_HOTPLUG_EN, hotplug_en);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004154}
4155
Daniel Vetterff1f5252012-10-02 15:10:55 +02004156static irqreturn_t i965_irq_handler(int irq, void *arg)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004157{
Daniel Vetter45a83f82014-05-12 19:17:55 +02004158 struct drm_device *dev = arg;
Jani Nikula2d1013d2014-03-31 14:27:17 +03004159 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004160 u32 iir, new_iir;
4161 u32 pipe_stats[I915_MAX_PIPES];
Chris Wilsona266c7d2012-04-24 22:59:44 +01004162 int ret = IRQ_NONE, pipe;
Ville Syrjälä21ad8332013-02-19 15:16:39 +02004163 u32 flip_mask =
4164 I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT |
4165 I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004166
Imre Deak2dd2a882015-02-24 11:14:30 +02004167 if (!intel_irqs_enabled(dev_priv))
4168 return IRQ_NONE;
4169
Chris Wilsona266c7d2012-04-24 22:59:44 +01004170 iir = I915_READ(IIR);
4171
Chris Wilsona266c7d2012-04-24 22:59:44 +01004172 for (;;) {
Ville Syrjälä501e01d2014-01-17 11:35:15 +02004173 bool irq_received = (iir & ~flip_mask) != 0;
Chris Wilson2c8ba292012-04-24 22:59:46 +01004174 bool blc_event = false;
4175
Chris Wilsona266c7d2012-04-24 22:59:44 +01004176 /* Can't rely on pipestat interrupt bit in iir as it might
4177 * have been cleared after the pipestat interrupt was received.
4178 * It doesn't set the bit in iir again, but it still produces
4179 * interrupts (for non-MSI).
4180 */
Daniel Vetter222c7f52014-09-15 14:55:28 +02004181 spin_lock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004182 if (iir & I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT)
Daniel Vetteraaecdf62014-11-04 15:52:22 +01004183 DRM_DEBUG("Command parser error, iir 0x%08x\n", iir);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004184
Damien Lespiau055e3932014-08-18 13:49:10 +01004185 for_each_pipe(dev_priv, pipe) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004186 int reg = PIPESTAT(pipe);
4187 pipe_stats[pipe] = I915_READ(reg);
4188
4189 /*
4190 * Clear the PIPE*STAT regs before the IIR
4191 */
4192 if (pipe_stats[pipe] & 0x8000ffff) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004193 I915_WRITE(reg, pipe_stats[pipe]);
Ville Syrjälä501e01d2014-01-17 11:35:15 +02004194 irq_received = true;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004195 }
4196 }
Daniel Vetter222c7f52014-09-15 14:55:28 +02004197 spin_unlock(&dev_priv->irq_lock);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004198
4199 if (!irq_received)
4200 break;
4201
4202 ret = IRQ_HANDLED;
4203
4204 /* Consume port. Then clear IIR or we'll miss events */
Ville Syrjälä16c6c562014-04-01 10:54:36 +03004205 if (iir & I915_DISPLAY_PORT_INTERRUPT)
4206 i9xx_hpd_irq_handler(dev);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004207
Ville Syrjälä21ad8332013-02-19 15:16:39 +02004208 I915_WRITE(IIR, iir & ~flip_mask);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004209 new_iir = I915_READ(IIR); /* Flush posted writes */
4210
Chris Wilsona266c7d2012-04-24 22:59:44 +01004211 if (iir & I915_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01004212 notify_ring(&dev_priv->ring[RCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004213 if (iir & I915_BSD_USER_INTERRUPT)
Chris Wilson74cdb332015-04-07 16:21:05 +01004214 notify_ring(&dev_priv->ring[VCS]);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004215
Damien Lespiau055e3932014-08-18 13:49:10 +01004216 for_each_pipe(dev_priv, pipe) {
Chris Wilson2c8ba292012-04-24 22:59:46 +01004217 if (pipe_stats[pipe] & PIPE_START_VBLANK_INTERRUPT_STATUS &&
Ville Syrjälä90a72f82013-02-19 23:16:44 +02004218 i915_handle_vblank(dev, pipe, pipe, iir))
4219 flip_mask &= ~DISPLAY_PLANE_FLIP_PENDING(pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004220
4221 if (pipe_stats[pipe] & PIPE_LEGACY_BLC_EVENT_STATUS)
4222 blc_event = true;
Daniel Vetter4356d582013-10-16 22:55:55 +02004223
4224 if (pipe_stats[pipe] & PIPE_CRC_DONE_INTERRUPT_STATUS)
Daniel Vetter277de952013-10-18 16:37:07 +02004225 i9xx_pipe_crc_irq_handler(dev, pipe);
Chris Wilsona266c7d2012-04-24 22:59:44 +01004226
Daniel Vetter1f7247c2014-09-30 10:56:48 +02004227 if (pipe_stats[pipe] & PIPE_FIFO_UNDERRUN_STATUS)
4228 intel_cpu_fifo_underrun_irq_handler(dev_priv, pipe);
Ville Syrjälä2d9d2b02014-01-17 11:44:31 +02004229 }
Chris Wilsona266c7d2012-04-24 22:59:44 +01004230
4231 if (blc_event || (iir & I915_ASLE_INTERRUPT))
4232 intel_opregion_asle_intr(dev);
4233
Daniel Vetter515ac2b2012-12-01 13:53:44 +01004234 if (pipe_stats[0] & PIPE_GMBUS_INTERRUPT_STATUS)
4235 gmbus_irq_handler(dev);
4236
Chris Wilsona266c7d2012-04-24 22:59:44 +01004237 /* With MSI, interrupts are only generated when iir
4238 * transitions from zero to nonzero. If another bit got
4239 * set while we were handling the existing iir bits, then
4240 * we would never get another interrupt.
4241 *
4242 * This is fine on non-MSI as well, as if we hit this path
4243 * we avoid exiting the interrupt handler only to generate
4244 * another one.
4245 *
4246 * Note that for MSI this could cause a stray interrupt report
4247 * if an interrupt landed in the time between writing IIR and
4248 * the posting read. This should be rare enough to never
4249 * trigger the 99% of 100,000 interrupts test for disabling
4250 * stray interrupts.
4251 */
4252 iir = new_iir;
4253 }
4254
4255 return ret;
4256}
4257
4258static void i965_irq_uninstall(struct drm_device * dev)
4259{
Jani Nikula2d1013d2014-03-31 14:27:17 +03004260 struct drm_i915_private *dev_priv = dev->dev_private;
Chris Wilsona266c7d2012-04-24 22:59:44 +01004261 int pipe;
4262
4263 if (!dev_priv)
4264 return;
4265
Chris Wilsonadca4732012-05-11 18:01:31 +01004266 I915_WRITE(PORT_HOTPLUG_EN, 0);
4267 I915_WRITE(PORT_HOTPLUG_STAT, I915_READ(PORT_HOTPLUG_STAT));
Chris Wilsona266c7d2012-04-24 22:59:44 +01004268
4269 I915_WRITE(HWSTAM, 0xffffffff);
Damien Lespiau055e3932014-08-18 13:49:10 +01004270 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004271 I915_WRITE(PIPESTAT(pipe), 0);
4272 I915_WRITE(IMR, 0xffffffff);
4273 I915_WRITE(IER, 0x0);
4274
Damien Lespiau055e3932014-08-18 13:49:10 +01004275 for_each_pipe(dev_priv, pipe)
Chris Wilsona266c7d2012-04-24 22:59:44 +01004276 I915_WRITE(PIPESTAT(pipe),
4277 I915_READ(PIPESTAT(pipe)) & 0x8000ffff);
4278 I915_WRITE(IIR, I915_READ(IIR));
4279}
4280
Daniel Vetter4cb21832014-09-15 14:55:26 +02004281static void intel_hpd_irq_reenable_work(struct work_struct *work)
Egbert Eichac4c16c2013-04-16 13:36:58 +02004282{
Imre Deak63237512014-08-18 15:37:02 +03004283 struct drm_i915_private *dev_priv =
4284 container_of(work, typeof(*dev_priv),
4285 hotplug_reenable_work.work);
Egbert Eichac4c16c2013-04-16 13:36:58 +02004286 struct drm_device *dev = dev_priv->dev;
4287 struct drm_mode_config *mode_config = &dev->mode_config;
Egbert Eichac4c16c2013-04-16 13:36:58 +02004288 int i;
4289
Imre Deak63237512014-08-18 15:37:02 +03004290 intel_runtime_pm_get(dev_priv);
4291
Daniel Vetter4cb21832014-09-15 14:55:26 +02004292 spin_lock_irq(&dev_priv->irq_lock);
Egbert Eichac4c16c2013-04-16 13:36:58 +02004293 for (i = (HPD_NONE + 1); i < HPD_NUM_PINS; i++) {
4294 struct drm_connector *connector;
4295
4296 if (dev_priv->hpd_stats[i].hpd_mark != HPD_DISABLED)
4297 continue;
4298
4299 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4300
4301 list_for_each_entry(connector, &mode_config->connector_list, head) {
4302 struct intel_connector *intel_connector = to_intel_connector(connector);
4303
4304 if (intel_connector->encoder->hpd_pin == i) {
4305 if (connector->polled != intel_connector->polled)
4306 DRM_DEBUG_DRIVER("Reenabling HPD on connector %s\n",
Jani Nikulac23cc412014-06-03 14:56:17 +03004307 connector->name);
Egbert Eichac4c16c2013-04-16 13:36:58 +02004308 connector->polled = intel_connector->polled;
4309 if (!connector->polled)
4310 connector->polled = DRM_CONNECTOR_POLL_HPD;
4311 }
4312 }
4313 }
4314 if (dev_priv->display.hpd_irq_setup)
4315 dev_priv->display.hpd_irq_setup(dev);
Daniel Vetter4cb21832014-09-15 14:55:26 +02004316 spin_unlock_irq(&dev_priv->irq_lock);
Imre Deak63237512014-08-18 15:37:02 +03004317
4318 intel_runtime_pm_put(dev_priv);
Egbert Eichac4c16c2013-04-16 13:36:58 +02004319}
4320
Daniel Vetterfca52a52014-09-30 10:56:45 +02004321/**
4322 * intel_irq_init - initializes irq support
4323 * @dev_priv: i915 device instance
4324 *
4325 * This function initializes all the irq support including work items, timers
4326 * and all the vtables. It does not setup the interrupt itself though.
4327 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004328void intel_irq_init(struct drm_i915_private *dev_priv)
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004329{
Daniel Vetterb9632912014-09-30 10:56:44 +02004330 struct drm_device *dev = dev_priv->dev;
Chris Wilson8b2e3262012-04-24 22:59:41 +01004331
4332 INIT_WORK(&dev_priv->hotplug_work, i915_hotplug_work_func);
Dave Airlie13cf5502014-06-18 11:29:35 +10004333 INIT_WORK(&dev_priv->dig_port_work, i915_digport_work_func);
Daniel Vetterc6a828d2012-08-08 23:35:35 +02004334 INIT_WORK(&dev_priv->rps.work, gen6_pm_rps_work);
Daniel Vettera4da4fa2012-11-02 19:55:07 +01004335 INIT_WORK(&dev_priv->l3_parity.error_work, ivybridge_parity_work);
Chris Wilson8b2e3262012-04-24 22:59:41 +01004336
Deepak Sa6706b42014-03-15 20:23:22 +05304337 /* Let's track the enabled rps events */
Daniel Vetterb9632912014-09-30 10:56:44 +02004338 if (IS_VALLEYVIEW(dev_priv) && !IS_CHERRYVIEW(dev_priv))
Ville Syrjälä6c65a582014-08-29 14:14:07 +03004339 /* WaGsvRC0ResidencyMethod:vlv */
Chris Wilson6f4b12f82015-03-18 09:48:23 +00004340 dev_priv->pm_rps_events = GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED;
Deepak S31685c22014-07-03 17:33:01 -04004341 else
4342 dev_priv->pm_rps_events = GEN6_PM_RPS_EVENTS;
Deepak Sa6706b42014-03-15 20:23:22 +05304343
Chris Wilson737b1502015-01-26 18:03:03 +02004344 INIT_DELAYED_WORK(&dev_priv->gpu_error.hangcheck_work,
4345 i915_hangcheck_elapsed);
Imre Deak63237512014-08-18 15:37:02 +03004346 INIT_DELAYED_WORK(&dev_priv->hotplug_reenable_work,
Daniel Vetter4cb21832014-09-15 14:55:26 +02004347 intel_hpd_irq_reenable_work);
Daniel Vetter61bac782012-12-01 21:03:21 +01004348
Tomas Janousek97a19a22012-12-08 13:48:13 +01004349 pm_qos_add_request(&dev_priv->pm_qos, PM_QOS_CPU_DMA_LATENCY, PM_QOS_DEFAULT_VALUE);
Daniel Vetter9ee32fea2012-12-01 13:53:48 +01004350
Daniel Vetterb9632912014-09-30 10:56:44 +02004351 if (IS_GEN2(dev_priv)) {
Ville Syrjälä4cdb83e2013-10-11 21:52:44 +03004352 dev->max_vblank_count = 0;
4353 dev->driver->get_vblank_counter = i8xx_get_vblank_counter;
Daniel Vetterb9632912014-09-30 10:56:44 +02004354 } else if (IS_G4X(dev_priv) || INTEL_INFO(dev_priv)->gen >= 5) {
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004355 dev->max_vblank_count = 0xffffffff; /* full 32 bit counter */
4356 dev->driver->get_vblank_counter = gm45_get_vblank_counter;
Ville Syrjälä391f75e2013-09-25 19:55:26 +03004357 } else {
4358 dev->driver->get_vblank_counter = i915_get_vblank_counter;
4359 dev->max_vblank_count = 0xffffff; /* only 24 bits of frame count */
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004360 }
4361
Ville Syrjälä21da2702014-08-06 14:49:55 +03004362 /*
4363 * Opt out of the vblank disable timer on everything except gen2.
4364 * Gen2 doesn't have a hardware frame counter and so depends on
4365 * vblank interrupts to produce sane vblank seuquence numbers.
4366 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004367 if (!IS_GEN2(dev_priv))
Ville Syrjälä21da2702014-08-06 14:49:55 +03004368 dev->vblank_disable_immediate = true;
4369
Daniel Vetterf3a5c3f2015-02-13 21:03:44 +01004370 dev->driver->get_vblank_timestamp = i915_get_vblank_timestamp;
4371 dev->driver->get_scanout_position = i915_get_crtc_scanoutpos;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004372
Daniel Vetterb9632912014-09-30 10:56:44 +02004373 if (IS_CHERRYVIEW(dev_priv)) {
Ville Syrjälä43f328d2014-04-09 20:40:52 +03004374 dev->driver->irq_handler = cherryview_irq_handler;
4375 dev->driver->irq_preinstall = cherryview_irq_preinstall;
4376 dev->driver->irq_postinstall = cherryview_irq_postinstall;
4377 dev->driver->irq_uninstall = cherryview_irq_uninstall;
4378 dev->driver->enable_vblank = valleyview_enable_vblank;
4379 dev->driver->disable_vblank = valleyview_disable_vblank;
4380 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Daniel Vetterb9632912014-09-30 10:56:44 +02004381 } else if (IS_VALLEYVIEW(dev_priv)) {
Jesse Barnes7e231dbe2012-03-28 13:39:38 -07004382 dev->driver->irq_handler = valleyview_irq_handler;
4383 dev->driver->irq_preinstall = valleyview_irq_preinstall;
4384 dev->driver->irq_postinstall = valleyview_irq_postinstall;
4385 dev->driver->irq_uninstall = valleyview_irq_uninstall;
4386 dev->driver->enable_vblank = valleyview_enable_vblank;
4387 dev->driver->disable_vblank = valleyview_disable_vblank;
Egbert Eichfa00abe2013-02-25 12:06:48 -05004388 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Daniel Vetterb9632912014-09-30 10:56:44 +02004389 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
Ben Widawskyabd58f02013-11-02 21:07:09 -07004390 dev->driver->irq_handler = gen8_irq_handler;
Daniel Vetter723761b2014-05-22 17:56:34 +02004391 dev->driver->irq_preinstall = gen8_irq_reset;
Ben Widawskyabd58f02013-11-02 21:07:09 -07004392 dev->driver->irq_postinstall = gen8_irq_postinstall;
4393 dev->driver->irq_uninstall = gen8_irq_uninstall;
4394 dev->driver->enable_vblank = gen8_enable_vblank;
4395 dev->driver->disable_vblank = gen8_disable_vblank;
Shashank Sharmae0a20ad2015-03-27 14:54:14 +02004396 if (HAS_PCH_SPLIT(dev))
4397 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
4398 else
4399 dev_priv->display.hpd_irq_setup = bxt_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004400 } else if (HAS_PCH_SPLIT(dev)) {
4401 dev->driver->irq_handler = ironlake_irq_handler;
Daniel Vetter723761b2014-05-22 17:56:34 +02004402 dev->driver->irq_preinstall = ironlake_irq_reset;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004403 dev->driver->irq_postinstall = ironlake_irq_postinstall;
4404 dev->driver->irq_uninstall = ironlake_irq_uninstall;
4405 dev->driver->enable_vblank = ironlake_enable_vblank;
4406 dev->driver->disable_vblank = ironlake_disable_vblank;
Daniel Vetter82a28bc2013-03-27 15:55:01 +01004407 dev_priv->display.hpd_irq_setup = ibx_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004408 } else {
Daniel Vetterb9632912014-09-30 10:56:44 +02004409 if (INTEL_INFO(dev_priv)->gen == 2) {
Chris Wilsonc2798b12012-04-22 21:13:57 +01004410 dev->driver->irq_preinstall = i8xx_irq_preinstall;
4411 dev->driver->irq_postinstall = i8xx_irq_postinstall;
4412 dev->driver->irq_handler = i8xx_irq_handler;
4413 dev->driver->irq_uninstall = i8xx_irq_uninstall;
Daniel Vetterb9632912014-09-30 10:56:44 +02004414 } else if (INTEL_INFO(dev_priv)->gen == 3) {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004415 dev->driver->irq_preinstall = i915_irq_preinstall;
4416 dev->driver->irq_postinstall = i915_irq_postinstall;
4417 dev->driver->irq_uninstall = i915_irq_uninstall;
4418 dev->driver->irq_handler = i915_irq_handler;
Chris Wilsonc2798b12012-04-22 21:13:57 +01004419 } else {
Chris Wilsona266c7d2012-04-24 22:59:44 +01004420 dev->driver->irq_preinstall = i965_irq_preinstall;
4421 dev->driver->irq_postinstall = i965_irq_postinstall;
4422 dev->driver->irq_uninstall = i965_irq_uninstall;
4423 dev->driver->irq_handler = i965_irq_handler;
Chris Wilsonc2798b12012-04-22 21:13:57 +01004424 }
Ville Syrjälä778eb332015-01-09 14:21:13 +02004425 if (I915_HAS_HOTPLUG(dev_priv))
4426 dev_priv->display.hpd_irq_setup = i915_hpd_irq_setup;
Jesse Barnesf71d4af2011-06-28 13:00:41 -07004427 dev->driver->enable_vblank = i915_enable_vblank;
4428 dev->driver->disable_vblank = i915_disable_vblank;
4429 }
4430}
Daniel Vetter20afbda2012-12-11 14:05:07 +01004431
Daniel Vetterfca52a52014-09-30 10:56:45 +02004432/**
4433 * intel_hpd_init - initializes and enables hpd support
4434 * @dev_priv: i915 device instance
4435 *
4436 * This function enables the hotplug support. It requires that interrupts have
4437 * already been enabled with intel_irq_init_hw(). From this point on hotplug and
4438 * poll request can run concurrently to other code, so locking rules must be
4439 * obeyed.
4440 *
4441 * This is a separate step from interrupt enabling to simplify the locking rules
4442 * in the driver load and resume code.
4443 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004444void intel_hpd_init(struct drm_i915_private *dev_priv)
Daniel Vetter20afbda2012-12-11 14:05:07 +01004445{
Daniel Vetterb9632912014-09-30 10:56:44 +02004446 struct drm_device *dev = dev_priv->dev;
Egbert Eich821450c2013-04-16 13:36:55 +02004447 struct drm_mode_config *mode_config = &dev->mode_config;
4448 struct drm_connector *connector;
4449 int i;
Daniel Vetter20afbda2012-12-11 14:05:07 +01004450
Egbert Eich821450c2013-04-16 13:36:55 +02004451 for (i = 1; i < HPD_NUM_PINS; i++) {
4452 dev_priv->hpd_stats[i].hpd_cnt = 0;
4453 dev_priv->hpd_stats[i].hpd_mark = HPD_ENABLED;
4454 }
4455 list_for_each_entry(connector, &mode_config->connector_list, head) {
4456 struct intel_connector *intel_connector = to_intel_connector(connector);
4457 connector->polled = intel_connector->polled;
Dave Airlie0e32b392014-05-02 14:02:48 +10004458 if (connector->encoder && !connector->polled && I915_HAS_HOTPLUG(dev) && intel_connector->encoder->hpd_pin > HPD_NONE)
4459 connector->polled = DRM_CONNECTOR_POLL_HPD;
4460 if (intel_connector->mst_port)
Egbert Eich821450c2013-04-16 13:36:55 +02004461 connector->polled = DRM_CONNECTOR_POLL_HPD;
4462 }
Daniel Vetterb5ea2d52013-06-27 17:52:15 +02004463
4464 /* Interrupt setup is already guaranteed to be single-threaded, this is
4465 * just to make the assert_spin_locked checks happy. */
Daniel Vetterd6207432014-09-15 14:55:27 +02004466 spin_lock_irq(&dev_priv->irq_lock);
Daniel Vetter20afbda2012-12-11 14:05:07 +01004467 if (dev_priv->display.hpd_irq_setup)
4468 dev_priv->display.hpd_irq_setup(dev);
Daniel Vetterd6207432014-09-15 14:55:27 +02004469 spin_unlock_irq(&dev_priv->irq_lock);
Daniel Vetter20afbda2012-12-11 14:05:07 +01004470}
Paulo Zanonic67a4702013-08-19 13:18:09 -03004471
Daniel Vetterfca52a52014-09-30 10:56:45 +02004472/**
4473 * intel_irq_install - enables the hardware interrupt
4474 * @dev_priv: i915 device instance
4475 *
4476 * This function enables the hardware interrupt handling, but leaves the hotplug
4477 * handling still disabled. It is called after intel_irq_init().
4478 *
4479 * In the driver load and resume code we need working interrupts in a few places
4480 * but don't want to deal with the hassle of concurrent probe and hotplug
4481 * workers. Hence the split into this two-stage approach.
4482 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004483int intel_irq_install(struct drm_i915_private *dev_priv)
4484{
4485 /*
4486 * We enable some interrupt sources in our postinstall hooks, so mark
4487 * interrupts as enabled _before_ actually enabling them to avoid
4488 * special cases in our ordering checks.
4489 */
4490 dev_priv->pm.irqs_enabled = true;
4491
4492 return drm_irq_install(dev_priv->dev, dev_priv->dev->pdev->irq);
4493}
4494
Daniel Vetterfca52a52014-09-30 10:56:45 +02004495/**
4496 * intel_irq_uninstall - finilizes all irq handling
4497 * @dev_priv: i915 device instance
4498 *
4499 * This stops interrupt and hotplug handling and unregisters and frees all
4500 * resources acquired in the init functions.
4501 */
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004502void intel_irq_uninstall(struct drm_i915_private *dev_priv)
4503{
4504 drm_irq_uninstall(dev_priv->dev);
4505 intel_hpd_cancel_work(dev_priv);
4506 dev_priv->pm.irqs_enabled = false;
4507}
4508
Daniel Vetterfca52a52014-09-30 10:56:45 +02004509/**
4510 * intel_runtime_pm_disable_interrupts - runtime interrupt disabling
4511 * @dev_priv: i915 device instance
4512 *
4513 * This function is used to disable interrupts at runtime, both in the runtime
4514 * pm and the system suspend/resume code.
4515 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004516void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03004517{
Daniel Vetterb9632912014-09-30 10:56:44 +02004518 dev_priv->dev->driver->irq_uninstall(dev_priv->dev);
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004519 dev_priv->pm.irqs_enabled = false;
Imre Deak2dd2a882015-02-24 11:14:30 +02004520 synchronize_irq(dev_priv->dev->irq);
Paulo Zanonic67a4702013-08-19 13:18:09 -03004521}
4522
Daniel Vetterfca52a52014-09-30 10:56:45 +02004523/**
4524 * intel_runtime_pm_enable_interrupts - runtime interrupt enabling
4525 * @dev_priv: i915 device instance
4526 *
4527 * This function is used to enable interrupts at runtime, both in the runtime
4528 * pm and the system suspend/resume code.
4529 */
Daniel Vetterb9632912014-09-30 10:56:44 +02004530void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv)
Paulo Zanonic67a4702013-08-19 13:18:09 -03004531{
Daniel Vetter2aeb7d32014-09-30 10:56:43 +02004532 dev_priv->pm.irqs_enabled = true;
Daniel Vetterb9632912014-09-30 10:56:44 +02004533 dev_priv->dev->driver->irq_preinstall(dev_priv->dev);
4534 dev_priv->dev->driver->irq_postinstall(dev_priv->dev);
Paulo Zanonic67a4702013-08-19 13:18:09 -03004535}