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gerrit-public.fairphone.software / kernel / msm-5.4 / 1d4e06894824514a2854b252d49c63b81779aec7 / . / arch / arm / boot / dts / tegra20-harmony.dts
blob: 3fb1f50f6d4628a3bdc42214450e03ace2a41e2d [file] [log] [blame]
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]1/dts-v1/;
2
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]3#include <dt-bindings/input/input.h>
Stephen Warren1bd0bd42012-10-17 16:38:21 -0600[diff] [blame]4#include "tegra20.dtsi"
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]5
6/ {
Bryan Wu8fef5df2012-12-20 09:41:29 +0000[diff] [blame]7 model = "NVIDIA Tegra20 Harmony evaluation board";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]8 compatible = "nvidia,harmony", "nvidia,tegra20";
9
Stephen Warren553c0a22013-12-09 14:43:59 -0700[diff] [blame]10 aliases {
11 rtc0 = "/i2c@7000d000/tps6586x@34";
12 rtc1 = "/rtc@7000e000";
13 };
14
Stephen Warrenf9eb26a2012-05-11 16:17:47 -0600[diff] [blame]15 memory {
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]16 reg = <0x00000000 0x40000000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]17 };
18
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]19 host1x@50000000 {
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame^]20 dc@54200000 {
21 rgb {
22 status = "okay";
23
24 nvidia,panel = <&panel>;
25 };
26 };
27
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]28 hdmi@54280000 {
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]29 status = "okay";
30
31 vdd-supply = <&hdmi_vdd_reg>;
32 pll-supply = <&hdmi_pll_reg>;
33
34 nvidia,ddc-i2c-bus = <&hdmi_ddc>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]35 nvidia,hpd-gpio = <&gpio TEGRA_GPIO(N, 7)
36 GPIO_ACTIVE_HIGH>;
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]37 };
38 };
39
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]40 pinmux@70000014 {
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]41 pinctrl-names = "default";
42 pinctrl-0 = <&state_default>;
43
44 state_default: pinmux {
45 ata {
46 nvidia,pins = "ata";
47 nvidia,function = "ide";
48 };
49 atb {
50 nvidia,pins = "atb", "gma", "gme";
51 nvidia,function = "sdio4";
52 };
53 atc {
54 nvidia,pins = "atc";
55 nvidia,function = "nand";
56 };
57 atd {
58 nvidia,pins = "atd", "ate", "gmb", "gmd", "gpu",
59 "spia", "spib", "spic";
60 nvidia,function = "gmi";
61 };
62 cdev1 {
63 nvidia,pins = "cdev1";
64 nvidia,function = "plla_out";
65 };
66 cdev2 {
67 nvidia,pins = "cdev2";
68 nvidia,function = "pllp_out4";
69 };
70 crtp {
71 nvidia,pins = "crtp";
72 nvidia,function = "crt";
73 };
74 csus {
75 nvidia,pins = "csus";
76 nvidia,function = "vi_sensor_clk";
77 };
78 dap1 {
79 nvidia,pins = "dap1";
80 nvidia,function = "dap1";
81 };
82 dap2 {
83 nvidia,pins = "dap2";
84 nvidia,function = "dap2";
85 };
86 dap3 {
87 nvidia,pins = "dap3";
88 nvidia,function = "dap3";
89 };
90 dap4 {
91 nvidia,pins = "dap4";
92 nvidia,function = "dap4";
93 };
94 ddc {
95 nvidia,pins = "ddc";
96 nvidia,function = "i2c2";
97 };
98 dta {
99 nvidia,pins = "dta", "dtd";
100 nvidia,function = "sdio2";
101 };
102 dtb {
103 nvidia,pins = "dtb", "dtc", "dte";
104 nvidia,function = "rsvd1";
105 };
106 dtf {
107 nvidia,pins = "dtf";
108 nvidia,function = "i2c3";
109 };
110 gmc {
111 nvidia,pins = "gmc";
112 nvidia,function = "uartd";
113 };
114 gpu7 {
115 nvidia,pins = "gpu7";
116 nvidia,function = "rtck";
117 };
118 gpv {
119 nvidia,pins = "gpv", "slxa", "slxk";
120 nvidia,function = "pcie";
121 };
122 hdint {
123 nvidia,pins = "hdint", "pta";
124 nvidia,function = "hdmi";
125 };
126 i2cp {
127 nvidia,pins = "i2cp";
128 nvidia,function = "i2cp";
129 };
130 irrx {
131 nvidia,pins = "irrx", "irtx";
132 nvidia,function = "uarta";
133 };
134 kbca {
135 nvidia,pins = "kbca", "kbcb", "kbcc", "kbcd",
136 "kbce", "kbcf";
137 nvidia,function = "kbc";
138 };
139 lcsn {
140 nvidia,pins = "lcsn", "ld0", "ld1", "ld2",
141 "ld3", "ld4", "ld5", "ld6", "ld7",
142 "ld8", "ld9", "ld10", "ld11", "ld12",
143 "ld13", "ld14", "ld15", "ld16", "ld17",
144 "ldc", "ldi", "lhp0", "lhp1", "lhp2",
145 "lhs", "lm0", "lm1", "lpp", "lpw0",
146 "lpw1", "lpw2", "lsc0", "lsc1", "lsck",
147 "lsda", "lsdi", "lspi", "lvp0", "lvp1",
148 "lvs";
149 nvidia,function = "displaya";
150 };
151 owc {
152 nvidia,pins = "owc", "spdi", "spdo", "uac";
153 nvidia,function = "rsvd2";
154 };
155 pmc {
156 nvidia,pins = "pmc";
157 nvidia,function = "pwr_on";
158 };
159 rm {
160 nvidia,pins = "rm";
161 nvidia,function = "i2c1";
162 };
163 sdb {
164 nvidia,pins = "sdb", "sdc", "sdd";
165 nvidia,function = "pwm";
166 };
167 sdio1 {
168 nvidia,pins = "sdio1";
169 nvidia,function = "sdio1";
170 };
171 slxc {
172 nvidia,pins = "slxc", "slxd";
173 nvidia,function = "spdif";
174 };
175 spid {
176 nvidia,pins = "spid", "spie", "spif";
177 nvidia,function = "spi1";
178 };
179 spig {
180 nvidia,pins = "spig", "spih";
181 nvidia,function = "spi2_alt";
182 };
183 uaa {
184 nvidia,pins = "uaa", "uab", "uda";
185 nvidia,function = "ulpi";
186 };
187 uad {
188 nvidia,pins = "uad";
189 nvidia,function = "irda";
190 };
191 uca {
192 nvidia,pins = "uca", "ucb";
193 nvidia,function = "uartc";
194 };
195 conf_ata {
196 nvidia,pins = "ata", "atb", "atc", "atd", "ate",
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]197 "cdev1", "cdev2", "dap1", "dtb", "gma",
198 "gmb", "gmc", "gmd", "gme", "gpu7",
199 "gpv", "i2cp", "pta", "rm", "slxa",
200 "slxk", "spia", "spib", "uac";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]201 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
202 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]203 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]204 conf_ck32 {
205 nvidia,pins = "ck32", "ddrc", "pmca", "pmcb",
206 "pmcc", "pmcd", "pmce", "xm2c", "xm2d";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]207 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]208 };
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]209 conf_csus {
210 nvidia,pins = "csus", "spid", "spif";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]211 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
212 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]213 };
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]214 conf_crtp {
215 nvidia,pins = "crtp", "dap2", "dap3", "dap4",
216 "dtc", "dte", "dtf", "gpu", "sdio1",
217 "slxc", "slxd", "spdi", "spdo", "spig",
Stephen Warren563da212012-04-13 16:35:20 -0600[diff] [blame]218 "uda";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]219 nvidia,pull = <TEGRA_PIN_PULL_NONE>;
220 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]221 };
222 conf_ddc {
223 nvidia,pins = "ddc", "dta", "dtd", "kbca",
224 "kbcb", "kbcc", "kbcd", "kbce", "kbcf",
225 "sdc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]226 nvidia,pull = <TEGRA_PIN_PULL_UP>;
227 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]228 };
229 conf_hdint {
230 nvidia,pins = "hdint", "lcsn", "ldc", "lm1",
231 "lpw1", "lsc1", "lsck", "lsda", "lsdi",
232 "lvp0", "owc", "sdb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]233 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]234 };
235 conf_irrx {
236 nvidia,pins = "irrx", "irtx", "sdd", "spic",
237 "spie", "spih", "uaa", "uab", "uad",
238 "uca", "ucb";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]239 nvidia,pull = <TEGRA_PIN_PULL_UP>;
240 nvidia,tristate = <TEGRA_PIN_ENABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]241 };
242 conf_lc {
243 nvidia,pins = "lc", "ls";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]244 nvidia,pull = <TEGRA_PIN_PULL_UP>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]245 };
246 conf_ld0 {
247 nvidia,pins = "ld0", "ld1", "ld2", "ld3", "ld4",
248 "ld5", "ld6", "ld7", "ld8", "ld9",
249 "ld10", "ld11", "ld12", "ld13", "ld14",
250 "ld15", "ld16", "ld17", "ldi", "lhp0",
251 "lhp1", "lhp2", "lhs", "lm0", "lpp",
252 "lpw0", "lpw2", "lsc0", "lspi", "lvp1",
253 "lvs", "pmc";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]254 nvidia,tristate = <TEGRA_PIN_DISABLE>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]255 };
256 conf_ld17_0 {
257 nvidia,pins = "ld17_0", "ld19_18", "ld21_20",
258 "ld23_22";
Laxman Dewanganba4104e2013-12-05 16:14:08 +0530[diff] [blame]259 nvidia,pull = <TEGRA_PIN_PULL_DOWN>;
Stephen Warrenecc295b2012-03-15 16:27:36 -0600[diff] [blame]260 };
261 };
262 };
263
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]264 i2s@70002800 {
265 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]266 };
267
268 serial@70006300 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]269 status = "okay";
Stephen Warrenc04abb32012-05-11 17:03:26 -0600[diff] [blame]270 };
271
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame^]272 pwm: pwm@7000a000 {
273 status = "okay";
274 };
275
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]276 i2c@7000c000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]277 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]278 clock-frequency = <400000>;
279
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]280 wm8903: wm8903@1a {
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]281 compatible = "wlf,wm8903";
282 reg = <0x1a>;
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]283 interrupt-parent = <&gpio>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]284 interrupts = <TEGRA_GPIO(X, 3) IRQ_TYPE_LEVEL_HIGH>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]285
286 gpio-controller;
287 #gpio-cells = <2>;
288
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]289 micdet-cfg = <0>;
290 micdet-delay = <100>;
Stephen Warren95decf82012-05-11 16:11:38 -0600[diff] [blame]291 gpio-cfg = <0xffffffff 0xffffffff 0 0xffffffff 0xffffffff>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]292 };
293 };
294
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]295 hdmi_ddc: i2c@7000c400 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]296 status = "okay";
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]297 clock-frequency = <100000>;
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]298 };
299
300 i2c@7000c500 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]301 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]302 clock-frequency = <400000>;
303 };
304
305 i2c@7000d000 {
Stephen Warren2a5fdc92012-05-11 17:32:56 -0600[diff] [blame]306 status = "okay";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]307 clock-frequency = <400000>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]308
309 pmic: tps6586x@34 {
310 compatible = "ti,tps6586x";
311 reg = <0x34>;
Stephen Warren6cecf912013-02-13 12:51:51 -0700[diff] [blame]312 interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]313
Stephen Warrenbe972c32012-09-11 11:40:04 -0600[diff] [blame]314 ti,system-power-controller;
315
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]316 #gpio-cells = <2>;
317 gpio-controller;
318
319 sys-supply = <&vdd_5v0_reg>;
320 vin-sm0-supply = <&sys_reg>;
321 vin-sm1-supply = <&sys_reg>;
322 vin-sm2-supply = <&sys_reg>;
323 vinldo01-supply = <&sm2_reg>;
324 vinldo23-supply = <&sm2_reg>;
325 vinldo4-supply = <&sm2_reg>;
326 vinldo678-supply = <&sm2_reg>;
327 vinldo9-supply = <&sm2_reg>;
328
329 regulators {
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]330 sys_reg: sys {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]331 regulator-name = "vdd_sys";
332 regulator-always-on;
333 };
334
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]335 sm0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]336 regulator-name = "vdd_sm0,vdd_core";
337 regulator-min-microvolt = <1200000>;
338 regulator-max-microvolt = <1200000>;
339 regulator-always-on;
340 };
341
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]342 sm1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]343 regulator-name = "vdd_sm1,vdd_cpu";
344 regulator-min-microvolt = <1000000>;
345 regulator-max-microvolt = <1000000>;
346 regulator-always-on;
347 };
348
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]349 sm2_reg: sm2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]350 regulator-name = "vdd_sm2,vin_ldo*";
351 regulator-min-microvolt = <3700000>;
352 regulator-max-microvolt = <3700000>;
353 regulator-always-on;
354 };
355
Thierry Reding722afc12013-08-09 16:49:22 +0200[diff] [blame]356 pci_clk_reg: ldo0 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]357 regulator-name = "vdd_ldo0,vddio_pex_clk";
358 regulator-min-microvolt = <3300000>;
359 regulator-max-microvolt = <3300000>;
360 };
361
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]362 ldo1 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]363 regulator-name = "vdd_ldo1,avdd_pll*";
364 regulator-min-microvolt = <1100000>;
365 regulator-max-microvolt = <1100000>;
366 regulator-always-on;
367 };
368
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]369 ldo2 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]370 regulator-name = "vdd_ldo2,vdd_rtc";
371 regulator-min-microvolt = <1200000>;
372 regulator-max-microvolt = <1200000>;
373 };
374
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]375 ldo3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]376 regulator-name = "vdd_ldo3,avdd_usb*";
377 regulator-min-microvolt = <3300000>;
378 regulator-max-microvolt = <3300000>;
379 regulator-always-on;
380 };
381
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]382 ldo4 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]383 regulator-name = "vdd_ldo4,avdd_osc,vddio_sys";
384 regulator-min-microvolt = <1800000>;
385 regulator-max-microvolt = <1800000>;
386 regulator-always-on;
387 };
388
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]389 ldo5 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]390 regulator-name = "vdd_ldo5,vcore_mmc";
391 regulator-min-microvolt = <2850000>;
392 regulator-max-microvolt = <2850000>;
393 regulator-always-on;
394 };
395
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]396 ldo6 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]397 regulator-name = "vdd_ldo6,avdd_vdac";
398 regulator-min-microvolt = <1800000>;
399 regulator-max-microvolt = <1800000>;
400 };
401
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]402 hdmi_vdd_reg: ldo7 {
Stephen Warren740418e2012-09-20 15:20:39 -0600[diff] [blame]403 regulator-name = "vdd_ldo7,avdd_hdmi";
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]404 regulator-min-microvolt = <3300000>;
405 regulator-max-microvolt = <3300000>;
406 };
407
Stephen Warren20ffbd72012-11-09 16:58:11 -0700[diff] [blame]408 hdmi_pll_reg: ldo8 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]409 regulator-name = "vdd_ldo8,avdd_hdmi_pll";
410 regulator-min-microvolt = <1800000>;
411 regulator-max-microvolt = <1800000>;
412 };
413
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]414 ldo9 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]415 regulator-name = "vdd_ldo9,avdd_2v85,vdd_ddr_rx";
416 regulator-min-microvolt = <2850000>;
417 regulator-max-microvolt = <2850000>;
418 regulator-always-on;
419 };
420
Stephen Warrenb9c665d2012-09-20 17:04:06 -0600[diff] [blame]421 ldo_rtc {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]422 regulator-name = "vdd_rtc_out,vdd_cell";
423 regulator-min-microvolt = <3300000>;
424 regulator-max-microvolt = <3300000>;
425 regulator-always-on;
426 };
427 };
428 };
Thierry Reding42d25342012-11-09 22:58:43 +0100[diff] [blame]429
430 temperature-sensor@4c {
431 compatible = "adi,adt7461";
432 reg = <0x4c>;
433 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]434 };
435
Stephen Warren58ecb232013-11-25 17:53:16 -0700[diff] [blame]436 kbc@7000e200 {
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530[diff] [blame]437 status = "okay";
438 nvidia,debounce-delay-ms = <2>;
439 nvidia,repeat-delay-ms = <160>;
440 nvidia,kbc-row-pins = <0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15>;
441 nvidia,kbc-col-pins = <16 17 18 19 20 21 22 23>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]442 linux,keymap = <MATRIX_KEY(0x00, 0x02, KEY_W)
443 MATRIX_KEY(0x00, 0x03, KEY_S)
444 MATRIX_KEY(0x00, 0x04, KEY_A)
445 MATRIX_KEY(0x00, 0x05, KEY_Z)
446 MATRIX_KEY(0x00, 0x07, KEY_FN)
447 MATRIX_KEY(0x01, 0x07, KEY_MENU)
448 MATRIX_KEY(0x02, 0x06, KEY_LEFTALT)
449 MATRIX_KEY(0x02, 0x07, KEY_RIGHTALT)
450 MATRIX_KEY(0x03, 0x00, KEY_5)
451 MATRIX_KEY(0x03, 0x01, KEY_4)
452 MATRIX_KEY(0x03, 0x02, KEY_R)
453 MATRIX_KEY(0x03, 0x03, KEY_E)
454 MATRIX_KEY(0x03, 0x04, KEY_F)
455 MATRIX_KEY(0x03, 0x05, KEY_D)
456 MATRIX_KEY(0x03, 0x06, KEY_X)
457 MATRIX_KEY(0x04, 0x00, KEY_7)
458 MATRIX_KEY(0x04, 0x01, KEY_6)
459 MATRIX_KEY(0x04, 0x02, KEY_T)
460 MATRIX_KEY(0x04, 0x03, KEY_H)
461 MATRIX_KEY(0x04, 0x04, KEY_G)
462 MATRIX_KEY(0x04, 0x05, KEY_V)
463 MATRIX_KEY(0x04, 0x06, KEY_C)
464 MATRIX_KEY(0x04, 0x07, KEY_SPACE)
465 MATRIX_KEY(0x05, 0x00, KEY_9)
466 MATRIX_KEY(0x05, 0x01, KEY_8)
467 MATRIX_KEY(0x05, 0x02, KEY_U)
468 MATRIX_KEY(0x05, 0x03, KEY_Y)
469 MATRIX_KEY(0x05, 0x04, KEY_J)
470 MATRIX_KEY(0x05, 0x05, KEY_N)
471 MATRIX_KEY(0x05, 0x06, KEY_B)
472 MATRIX_KEY(0x05, 0x07, KEY_BACKSLASH)
473 MATRIX_KEY(0x06, 0x00, KEY_MINUS)
474 MATRIX_KEY(0x06, 0x01, KEY_0)
475 MATRIX_KEY(0x06, 0x02, KEY_O)
476 MATRIX_KEY(0x06, 0x03, KEY_I)
477 MATRIX_KEY(0x06, 0x04, KEY_L)
478 MATRIX_KEY(0x06, 0x05, KEY_K)
479 MATRIX_KEY(0x06, 0x06, KEY_COMMA)
480 MATRIX_KEY(0x06, 0x07, KEY_M)
481 MATRIX_KEY(0x07, 0x01, KEY_EQUAL)
482 MATRIX_KEY(0x07, 0x02, KEY_RIGHTBRACE)
483 MATRIX_KEY(0x07, 0x03, KEY_ENTER)
484 MATRIX_KEY(0x07, 0x07, KEY_MENU)
485 MATRIX_KEY(0x08, 0x04, KEY_LEFTSHIFT)
486 MATRIX_KEY(0x08, 0x05, KEY_RIGHTSHIFT)
487 MATRIX_KEY(0x09, 0x05, KEY_LEFTCTRL)
488 MATRIX_KEY(0x09, 0x07, KEY_RIGHTCTRL)
489 MATRIX_KEY(0x0B, 0x00, KEY_LEFTBRACE)
490 MATRIX_KEY(0x0B, 0x01, KEY_P)
491 MATRIX_KEY(0x0B, 0x02, KEY_APOSTROPHE)
492 MATRIX_KEY(0x0B, 0x03, KEY_SEMICOLON)
493 MATRIX_KEY(0x0B, 0x04, KEY_SLASH)
494 MATRIX_KEY(0x0B, 0x05, KEY_DOT)
495 MATRIX_KEY(0x0C, 0x00, KEY_F10)
496 MATRIX_KEY(0x0C, 0x01, KEY_F9)
497 MATRIX_KEY(0x0C, 0x02, KEY_BACKSPACE)
498 MATRIX_KEY(0x0C, 0x03, KEY_3)
499 MATRIX_KEY(0x0C, 0x04, KEY_2)
500 MATRIX_KEY(0x0C, 0x05, KEY_UP)
501 MATRIX_KEY(0x0C, 0x06, KEY_PRINT)
502 MATRIX_KEY(0x0C, 0x07, KEY_PAUSE)
503 MATRIX_KEY(0x0D, 0x00, KEY_INSERT)
504 MATRIX_KEY(0x0D, 0x01, KEY_DELETE)
505 MATRIX_KEY(0x0D, 0x03, KEY_PAGEUP )
506 MATRIX_KEY(0x0D, 0x04, KEY_PAGEDOWN)
507 MATRIX_KEY(0x0D, 0x05, KEY_RIGHT)
508 MATRIX_KEY(0x0D, 0x06, KEY_DOWN)
509 MATRIX_KEY(0x0D, 0x07, KEY_LEFT)
510 MATRIX_KEY(0x0E, 0x00, KEY_F11)
511 MATRIX_KEY(0x0E, 0x01, KEY_F12)
512 MATRIX_KEY(0x0E, 0x02, KEY_F8)
513 MATRIX_KEY(0x0E, 0x03, KEY_Q)
514 MATRIX_KEY(0x0E, 0x04, KEY_F4)
515 MATRIX_KEY(0x0E, 0x05, KEY_F3)
516 MATRIX_KEY(0x0E, 0x06, KEY_1)
517 MATRIX_KEY(0x0E, 0x07, KEY_F7)
518 MATRIX_KEY(0x0F, 0x00, KEY_ESC)
519 MATRIX_KEY(0x0F, 0x01, KEY_GRAVE)
520 MATRIX_KEY(0x0F, 0x02, KEY_F5)
521 MATRIX_KEY(0x0F, 0x03, KEY_TAB)
522 MATRIX_KEY(0x0F, 0x04, KEY_F1)
523 MATRIX_KEY(0x0F, 0x05, KEY_F2)
524 MATRIX_KEY(0x0F, 0x06, KEY_CAPSLOCK)
525 MATRIX_KEY(0x0F, 0x07, KEY_F6)
526 MATRIX_KEY(0x14, 0x00, KEY_KP7)
527 MATRIX_KEY(0x15, 0x00, KEY_KP9)
528 MATRIX_KEY(0x15, 0x01, KEY_KP8)
529 MATRIX_KEY(0x15, 0x02, KEY_KP4)
530 MATRIX_KEY(0x15, 0x04, KEY_KP1)
531 MATRIX_KEY(0x16, 0x01, KEY_KPSLASH)
532 MATRIX_KEY(0x16, 0x02, KEY_KP6)
533 MATRIX_KEY(0x16, 0x03, KEY_KP5)
534 MATRIX_KEY(0x16, 0x04, KEY_KP3)
535 MATRIX_KEY(0x16, 0x05, KEY_KP2)
536 MATRIX_KEY(0x16, 0x07, KEY_KP0)
537 MATRIX_KEY(0x1B, 0x01, KEY_KPASTERISK)
538 MATRIX_KEY(0x1B, 0x03, KEY_KPMINUS)
539 MATRIX_KEY(0x1B, 0x04, KEY_KPPLUS)
540 MATRIX_KEY(0x1B, 0x05, KEY_KPDOT)
541 MATRIX_KEY(0x1C, 0x05, KEY_VOLUMEUP)
542 MATRIX_KEY(0x1D, 0x03, KEY_HOME)
543 MATRIX_KEY(0x1D, 0x04, KEY_END)
544 MATRIX_KEY(0x1D, 0x05, KEY_BRIGHTNESSUP)
545 MATRIX_KEY(0x1D, 0x06, KEY_VOLUMEDOWN)
546 MATRIX_KEY(0x1D, 0x07, KEY_BRIGHTNESSDOWN)
547 MATRIX_KEY(0x1E, 0x00, KEY_NUMLOCK)
548 MATRIX_KEY(0x1E, 0x01, KEY_SCROLLLOCK)
549 MATRIX_KEY(0x1E, 0x02, KEY_MUTE)
550 MATRIX_KEY(0x1F, 0x04, KEY_QUESTION)>;
Laxman Dewanganc0967ce2013-01-21 23:14:05 +0530[diff] [blame]551 };
552
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]553 pmc@7000e400 {
554 nvidia,invert-interrupt;
555 nvidia,suspend-mode = <1>;
556 nvidia,cpu-pwr-good-time = <5000>;
557 nvidia,cpu-pwr-off-time = <5000>;
558 nvidia,core-pwr-good-time = <3845 3845>;
559 nvidia,core-pwr-off-time = <3875>;
560 nvidia,sys-clock-req-active-high;
561 };
562
563 pcie-controller@80003000 {
564 pex-clk-supply = <&pci_clk_reg>;
565 vdd-supply = <&pci_vdd_reg>;
566 status = "okay";
567
568 pci@1,0 {
569 status = "okay";
570 };
571
572 pci@2,0 {
573 status = "okay";
574 };
575 };
576
577 usb@c5000000 {
578 status = "okay";
579 };
580
581 usb-phy@c5000000 {
582 status = "okay";
583 };
584
585 usb@c5004000 {
586 status = "okay";
587 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
588 GPIO_ACTIVE_LOW>;
589 };
590
591 usb-phy@c5004000 {
592 status = "okay";
593 nvidia,phy-reset-gpio = <&gpio TEGRA_GPIO(V, 1)
594 GPIO_ACTIVE_LOW>;
595 };
596
597 usb@c5008000 {
598 status = "okay";
599 };
600
601 usb-phy@c5008000 {
602 status = "okay";
603 };
604
605 sdhci@c8000200 {
606 status = "okay";
607 cd-gpios = <&gpio TEGRA_GPIO(I, 5) GPIO_ACTIVE_LOW>;
608 wp-gpios = <&gpio TEGRA_GPIO(H, 1) GPIO_ACTIVE_HIGH>;
609 power-gpios = <&gpio TEGRA_GPIO(T, 3) GPIO_ACTIVE_HIGH>;
610 bus-width = <4>;
611 };
612
613 sdhci@c8000600 {
614 status = "okay";
615 cd-gpios = <&gpio TEGRA_GPIO(H, 2) GPIO_ACTIVE_LOW>;
616 wp-gpios = <&gpio TEGRA_GPIO(H, 3) GPIO_ACTIVE_HIGH>;
617 power-gpios = <&gpio TEGRA_GPIO(I, 6) GPIO_ACTIVE_HIGH>;
618 bus-width = <8>;
619 };
620
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame^]621 backlight: backlight {
622 compatible = "pwm-backlight";
623
624 enable-gpios = <&gpio TEGRA_GPIO(B, 5) GPIO_ACTIVE_HIGH>;
625 power-supply = <&vdd_bl_reg>;
626 pwms = <&pwm 0 5000000>;
627
628 brightness-levels = <0 4 8 16 32 64 128 255>;
629 default-brightness-level = <6>;
630 };
631
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]632 clocks {
633 compatible = "simple-bus";
634 #address-cells = <1>;
635 #size-cells = <0>;
636
637 clk32k_in: clock@0 {
638 compatible = "fixed-clock";
639 reg=<0>;
640 #clock-cells = <0>;
641 clock-frequency = <32768>;
642 };
643 };
644
645 gpio-keys {
646 compatible = "gpio-keys";
647
648 power {
649 label = "Power";
650 gpios = <&gpio TEGRA_GPIO(V, 2) GPIO_ACTIVE_LOW>;
Laxman Dewangan6bccbd52013-12-02 18:39:57 +0530[diff] [blame]651 linux,code = <KEY_POWER>;
Stephen Warren57899052013-11-26 14:43:45 -0700[diff] [blame]652 gpio-key,wakeup;
653 };
654 };
655
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame^]656 panel: panel {
657 compatible = "auo,b101aw03", "simple-panel";
658
659 power-supply = <&vdd_pnl_reg>;
660 enable-gpios = <&gpio TEGRA_GPIO(B, 2) GPIO_ACTIVE_HIGH>;
661
662 backlight = <&backlight>;
663 };
664
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]665 regulators {
666 compatible = "simple-bus";
667 #address-cells = <1>;
668 #size-cells = <0>;
669
670 vdd_5v0_reg: regulator@0 {
671 compatible = "regulator-fixed";
672 reg = <0>;
673 regulator-name = "vdd_5v0";
674 regulator-min-microvolt = <5000000>;
675 regulator-max-microvolt = <5000000>;
676 regulator-always-on;
677 };
678
679 regulator@1 {
680 compatible = "regulator-fixed";
681 reg = <1>;
682 regulator-name = "vdd_1v5";
683 regulator-min-microvolt = <1500000>;
684 regulator-max-microvolt = <1500000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]685 gpio = <&pmic 0 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]686 };
687
688 regulator@2 {
689 compatible = "regulator-fixed";
690 reg = <2>;
691 regulator-name = "vdd_1v2";
692 regulator-min-microvolt = <1200000>;
693 regulator-max-microvolt = <1200000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]694 gpio = <&pmic 1 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]695 enable-active-high;
696 };
697
Thierry Reding722afc12013-08-09 16:49:22 +0200[diff] [blame]698 pci_vdd_reg: regulator@3 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]699 compatible = "regulator-fixed";
700 reg = <3>;
701 regulator-name = "vdd_1v05";
702 regulator-min-microvolt = <1050000>;
703 regulator-max-microvolt = <1050000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]704 gpio = <&pmic 2 GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]705 enable-active-high;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]706 };
707
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame^]708 vdd_pnl_reg: regulator@4 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]709 compatible = "regulator-fixed";
710 reg = <4>;
711 regulator-name = "vdd_pnl";
712 regulator-min-microvolt = <2800000>;
713 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]714 gpio = <&gpio TEGRA_GPIO(C, 6) GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]715 enable-active-high;
716 };
717
Thierry Reding1d4e0682013-12-19 16:59:25 +0100[diff] [blame^]718 vdd_bl_reg: regulator@5 {
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]719 compatible = "regulator-fixed";
720 reg = <5>;
721 regulator-name = "vdd_bl";
722 regulator-min-microvolt = <2800000>;
723 regulator-max-microvolt = <2800000>;
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]724 gpio = <&gpio TEGRA_GPIO(W, 0) GPIO_ACTIVE_HIGH>;
Laxman Dewangan3cc404d2012-08-16 20:59:59 +0000[diff] [blame]725 enable-active-high;
726 };
727 };
728
Stephen Warren797acf72012-01-11 16:09:57 -0700[diff] [blame]729 sound {
730 compatible = "nvidia,tegra-audio-wm8903-harmony",
731 "nvidia,tegra-audio-wm8903";
732 nvidia,model = "NVIDIA Tegra Harmony";
733
734 nvidia,audio-routing =
735 "Headphone Jack", "HPOUTR",
736 "Headphone Jack", "HPOUTL",
737 "Int Spk", "ROP",
738 "Int Spk", "RON",
739 "Int Spk", "LOP",
740 "Int Spk", "LON",
741 "Mic Jack", "MICBIAS",
742 "IN1L", "Mic Jack";
743
744 nvidia,i2s-controller = <&tegra_i2s1>;
745 nvidia,audio-codec = <&wm8903>;
746
Stephen Warren3325f1b2013-02-12 17:25:15 -0700[diff] [blame]747 nvidia,spkr-en-gpios = <&wm8903 2 GPIO_ACTIVE_HIGH>;
748 nvidia,hp-det-gpios = <&gpio TEGRA_GPIO(W, 2)
749 GPIO_ACTIVE_HIGH>;
750 nvidia,int-mic-en-gpios = <&gpio TEGRA_GPIO(X, 0)
751 GPIO_ACTIVE_HIGH>;
752 nvidia,ext-mic-en-gpios = <&gpio TEGRA_GPIO(X, 1)
753 GPIO_ACTIVE_HIGH>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]754
Hiroshi Doyu885a8cf2013-05-22 19:45:32 +0300[diff] [blame]755 clocks = <&tegra_car TEGRA20_CLK_PLL_A>,
756 <&tegra_car TEGRA20_CLK_PLL_A_OUT0>,
757 <&tegra_car TEGRA20_CLK_CDEV1>;
Stephen Warrenf9cd2b32013-03-26 16:45:52 -0600[diff] [blame]758 clock-names = "pll_a", "pll_a_out0", "mclk";
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]759 };
Grant Likely8e267f32011-07-19 17:26:54 -0600[diff] [blame]760};