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Catalin Marinas9cce7a42012-03-05 11:49:28 +00001/*
2 * Based on arch/arm/include/asm/processor.h
3 *
4 * Copyright (C) 1995-1999 Russell King
5 * Copyright (C) 2012 ARM Ltd.
6 *
7 * This program is free software; you can redistribute it and/or modify
8 * it under the terms of the GNU General Public License version 2 as
9 * published by the Free Software Foundation.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 */
19#ifndef __ASM_PROCESSOR_H
20#define __ASM_PROCESSOR_H
21
Yury Noroveef94a32017-08-31 11:30:50 +030022#define TASK_SIZE_64 (UL(1) << VA_BITS)
23
Robin Murphy51369e32018-02-05 15:34:18 +000024#define KERNEL_DS UL(-1)
25#define USER_DS (TASK_SIZE_64 - 1)
26
Yury Noroveef94a32017-08-31 11:30:50 +030027#ifndef __ASSEMBLY__
28
Catalin Marinas9cce7a42012-03-05 11:49:28 +000029/*
30 * Default implementation of macro that returns current
31 * instruction pointer ("program counter").
32 */
33#define current_text_addr() ({ __label__ _l; _l: &&_l;})
34
35#ifdef __KERNEL__
36
37#include <linux/string.h>
38
Will Deaconcd5e10b2016-02-02 12:46:23 +000039#include <asm/alternative.h>
Dave Martinc0cda3b2018-03-26 15:12:28 +010040#include <asm/cpufeature.h>
Catalin Marinas9cce7a42012-03-05 11:49:28 +000041#include <asm/hw_breakpoint.h>
Will Deaconafb83cc2016-02-10 10:07:30 +000042#include <asm/lse.h>
Paul Walmsley2ec45602015-01-05 17:38:41 -070043#include <asm/pgtable-hwdef.h>
Catalin Marinas9cce7a42012-03-05 11:49:28 +000044#include <asm/ptrace.h>
45#include <asm/types.h>
46
Yury Noroveef94a32017-08-31 11:30:50 +030047/*
48 * TASK_SIZE - the maximum size of a user space task.
49 * TASK_UNMAPPED_BASE - the lower boundary of the mmap VM area.
50 */
51#ifdef CONFIG_COMPAT
52#define TASK_SIZE_32 UL(0x100000000)
53#define TASK_SIZE (test_thread_flag(TIF_32BIT) ? \
54 TASK_SIZE_32 : TASK_SIZE_64)
55#define TASK_SIZE_OF(tsk) (test_tsk_thread_flag(tsk, TIF_32BIT) ? \
56 TASK_SIZE_32 : TASK_SIZE_64)
57#else
58#define TASK_SIZE TASK_SIZE_64
59#endif /* CONFIG_COMPAT */
60
61#define TASK_UNMAPPED_BASE (PAGE_ALIGN(TASK_SIZE / 4))
62
Catalin Marinas9cce7a42012-03-05 11:49:28 +000063#define STACK_TOP_MAX TASK_SIZE_64
64#ifdef CONFIG_COMPAT
65#define AARCH32_VECTORS_BASE 0xffff0000
66#define STACK_TOP (test_thread_flag(TIF_32BIT) ? \
67 AARCH32_VECTORS_BASE : STACK_TOP_MAX)
68#else
69#define STACK_TOP STACK_TOP_MAX
70#endif /* CONFIG_COMPAT */
Will Deaconf483a852012-11-08 16:00:16 +000071
Catalin Marinasa1e50a82015-02-05 18:01:53 +000072extern phys_addr_t arm64_dma_phys_limit;
73#define ARCH_LOW_ADDRESS_LIMIT (arm64_dma_phys_limit - 1)
Catalin Marinas9cce7a42012-03-05 11:49:28 +000074
75struct debug_info {
Chris Redmonfda89d92017-03-16 18:10:43 -040076#ifdef CONFIG_HAVE_HW_BREAKPOINT
Catalin Marinas9cce7a42012-03-05 11:49:28 +000077 /* Have we suspended stepping by a debugger? */
78 int suspended_step;
79 /* Allow breakpoints and watchpoints to be disabled for this thread. */
80 int bps_disabled;
81 int wps_disabled;
82 /* Hardware breakpoints pinned to this task. */
83 struct perf_event *hbp_break[ARM_MAX_BRP];
84 struct perf_event *hbp_watch[ARM_MAX_WRP];
Chris Redmonfda89d92017-03-16 18:10:43 -040085#endif
Catalin Marinas9cce7a42012-03-05 11:49:28 +000086};
87
88struct cpu_context {
89 unsigned long x19;
90 unsigned long x20;
91 unsigned long x21;
92 unsigned long x22;
93 unsigned long x23;
94 unsigned long x24;
95 unsigned long x25;
96 unsigned long x26;
97 unsigned long x27;
98 unsigned long x28;
99 unsigned long fp;
100 unsigned long sp;
101 unsigned long pc;
102};
103
104struct thread_struct {
105 struct cpu_context cpu_context; /* cpu context */
Will Deacond00a3812015-05-27 15:39:40 +0100106 unsigned long tp_value; /* TLS register */
107#ifdef CONFIG_COMPAT
108 unsigned long tp2_value;
109#endif
Dave Martin20b85472018-03-28 10:50:48 +0100110 struct user_fpsimd_state fpsimd_state;
111 unsigned int fpsimd_cpu;
Dave Martinbc0ee472017-10-31 15:51:05 +0000112 void *sve_state; /* SVE registers, if any */
113 unsigned int sve_vl; /* SVE vector length */
Dave Martin79ab0472017-10-31 15:51:06 +0000114 unsigned int sve_vl_onexec; /* SVE vl after next exec */
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000115 unsigned long fault_address; /* fault info */
Catalin Marinas91413002014-04-06 23:04:12 +0100116 unsigned long fault_code; /* ESR_EL1 value */
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000117 struct debug_info debug; /* debugging */
118};
119
Kees Cook9e8084d2017-08-16 14:05:09 -0700120/*
121 * Everything usercopied to/from thread_struct is statically-sized, so
122 * no hardened usercopy whitelist is needed.
123 */
124static inline void arch_thread_struct_whitelist(unsigned long *offset,
125 unsigned long *size)
126{
127 *offset = *size = 0;
128}
129
Will Deacond00a3812015-05-27 15:39:40 +0100130#ifdef CONFIG_COMPAT
131#define task_user_tls(t) \
132({ \
133 unsigned long *__tls; \
134 if (is_compat_thread(task_thread_info(t))) \
135 __tls = &(t)->thread.tp2_value; \
136 else \
137 __tls = &(t)->thread.tp_value; \
138 __tls; \
139 })
140#else
141#define task_user_tls(t) (&(t)->thread.tp_value)
142#endif
143
Dave Martin936eb652017-06-21 16:00:44 +0100144/* Sync TPIDR_EL0 back to thread_struct for current */
145void tls_preserve_current_state(void);
146
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000147#define INIT_THREAD { }
148
149static inline void start_thread_common(struct pt_regs *regs, unsigned long pc)
150{
151 memset(regs, 0, sizeof(*regs));
Dave Martin17c28952017-08-01 15:35:54 +0100152 forget_syscall(regs);
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000153 regs->pc = pc;
154}
155
156static inline void start_thread(struct pt_regs *regs, unsigned long pc,
157 unsigned long sp)
158{
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000159 start_thread_common(regs, pc);
160 regs->pstate = PSR_MODE_EL0t;
161 regs->sp = sp;
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000162}
163
164#ifdef CONFIG_COMPAT
165static inline void compat_start_thread(struct pt_regs *regs, unsigned long pc,
166 unsigned long sp)
167{
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000168 start_thread_common(regs, pc);
169 regs->pstate = COMPAT_PSR_MODE_USR;
170 if (pc & 1)
171 regs->pstate |= COMPAT_PSR_T_BIT;
Will Deacona795a382013-10-11 14:52:12 +0100172
173#ifdef __AARCH64EB__
174 regs->pstate |= COMPAT_PSR_E_BIT;
175#endif
176
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000177 regs->compat_sp = sp;
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000178}
179#endif
180
181/* Forward declaration, a strange C thing */
182struct task_struct;
183
184/* Free all resources held by a thread. */
185extern void release_thread(struct task_struct *);
186
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000187unsigned long get_wchan(struct task_struct *p);
188
Peter Crosthwaite1baa82f2015-03-02 19:19:14 +0000189static inline void cpu_relax(void)
190{
191 asm volatile("yield" ::: "memory");
192}
193
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000194/* Thread switching */
195extern struct task_struct *cpu_switch_to(struct task_struct *prev,
196 struct task_struct *next);
197
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000198#define task_pt_regs(p) \
Ard Biesheuvel34be98f2017-07-20 17:15:45 +0100199 ((struct pt_regs *)(THREAD_SIZE + task_stack_page(p)) - 1)
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000200
Catalin Marinasebe61522014-07-10 11:37:40 +0100201#define KSTK_EIP(tsk) ((unsigned long)task_pt_regs(tsk)->pc)
Will Deacon3168a742014-08-29 16:11:10 +0100202#define KSTK_ESP(tsk) user_stack_pointer(task_pt_regs(tsk))
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000203
204/*
205 * Prefetching support
206 */
207#define ARCH_HAS_PREFETCH
208static inline void prefetch(const void *ptr)
209{
210 asm volatile("prfm pldl1keep, %a0\n" : : "p" (ptr));
211}
212
213#define ARCH_HAS_PREFETCHW
214static inline void prefetchw(const void *ptr)
215{
216 asm volatile("prfm pstl1keep, %a0\n" : : "p" (ptr));
217}
218
219#define ARCH_HAS_SPINLOCK_PREFETCH
Will Deaconcd5e10b2016-02-02 12:46:23 +0000220static inline void spin_lock_prefetch(const void *ptr)
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000221{
Will Deaconcd5e10b2016-02-02 12:46:23 +0000222 asm volatile(ARM64_LSE_ATOMIC_INSN(
223 "prfm pstl1strm, %a0",
224 "nop") : : "p" (ptr));
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000225}
226
227#define HAVE_ARCH_PICK_MMAP_LAYOUT
228
229#endif
230
Dave Martinc0cda3b2018-03-26 15:12:28 +0100231void cpu_enable_pan(const struct arm64_cpu_capabilities *__unused);
232void cpu_enable_cache_maint_trap(const struct arm64_cpu_capabilities *__unused);
233void cpu_clear_disr(const struct arm64_cpu_capabilities *__unused);
James Morse338d4f42015-07-22 19:05:54 +0100234
Dave Martin2d2123b2017-10-31 15:51:14 +0000235/* Userspace interface for PR_SVE_{SET,GET}_VL prctl()s: */
236#define SVE_SET_VL(arg) sve_set_current_vl(arg)
237#define SVE_GET_VL() sve_get_current_vl()
238
Yury Noroveef94a32017-08-31 11:30:50 +0300239#endif /* __ASSEMBLY__ */
Catalin Marinas9cce7a42012-03-05 11:49:28 +0000240#endif /* __ASM_PROCESSOR_H */