Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 1 | /* |
| 2 | * skl-topology.c - Implements Platform component ALSA controls/widget |
| 3 | * handlers. |
| 4 | * |
| 5 | * Copyright (C) 2014-2015 Intel Corp |
| 6 | * Author: Jeeja KP <jeeja.kp@intel.com> |
| 7 | * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ |
| 8 | * |
| 9 | * This program is free software; you can redistribute it and/or modify |
| 10 | * it under the terms of the GNU General Public License as version 2, as |
| 11 | * published by the Free Software Foundation. |
| 12 | * |
| 13 | * This program is distributed in the hope that it will be useful, but |
| 14 | * WITHOUT ANY WARRANTY; without even the implied warranty of |
| 15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU |
| 16 | * General Public License for more details. |
| 17 | */ |
| 18 | |
| 19 | #include <linux/slab.h> |
| 20 | #include <linux/types.h> |
| 21 | #include <linux/firmware.h> |
| 22 | #include <sound/soc.h> |
| 23 | #include <sound/soc-topology.h> |
| 24 | #include "skl-sst-dsp.h" |
| 25 | #include "skl-sst-ipc.h" |
| 26 | #include "skl-topology.h" |
| 27 | #include "skl.h" |
| 28 | #include "skl-tplg-interface.h" |
Dharageswari R | 6c5768b | 2015-12-03 23:29:50 +0530 | [diff] [blame] | 29 | #include "../common/sst-dsp.h" |
| 30 | #include "../common/sst-dsp-priv.h" |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 31 | |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 32 | #define SKL_CH_FIXUP_MASK (1 << 0) |
| 33 | #define SKL_RATE_FIXUP_MASK (1 << 1) |
| 34 | #define SKL_FMT_FIXUP_MASK (1 << 2) |
| 35 | |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 36 | /* |
| 37 | * SKL DSP driver modelling uses only few DAPM widgets so for rest we will |
| 38 | * ignore. This helpers checks if the SKL driver handles this widget type |
| 39 | */ |
| 40 | static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w) |
| 41 | { |
| 42 | switch (w->id) { |
| 43 | case snd_soc_dapm_dai_link: |
| 44 | case snd_soc_dapm_dai_in: |
| 45 | case snd_soc_dapm_aif_in: |
| 46 | case snd_soc_dapm_aif_out: |
| 47 | case snd_soc_dapm_dai_out: |
| 48 | case snd_soc_dapm_switch: |
| 49 | return false; |
| 50 | default: |
| 51 | return true; |
| 52 | } |
| 53 | } |
| 54 | |
| 55 | /* |
| 56 | * Each pipelines needs memory to be allocated. Check if we have free memory |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 57 | * from available pool. |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 58 | */ |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 59 | static bool skl_is_pipe_mem_avail(struct skl *skl, |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 60 | struct skl_module_cfg *mconfig) |
| 61 | { |
| 62 | struct skl_sst *ctx = skl->skl_sst; |
| 63 | |
| 64 | if (skl->resource.mem + mconfig->pipe->memory_pages > |
| 65 | skl->resource.max_mem) { |
| 66 | dev_err(ctx->dev, |
| 67 | "%s: module_id %d instance %d\n", __func__, |
| 68 | mconfig->id.module_id, |
| 69 | mconfig->id.instance_id); |
| 70 | dev_err(ctx->dev, |
| 71 | "exceeds ppl memory available %d mem %d\n", |
| 72 | skl->resource.max_mem, skl->resource.mem); |
| 73 | return false; |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 74 | } else { |
| 75 | return true; |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 76 | } |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 77 | } |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 78 | |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 79 | /* |
| 80 | * Add the mem to the mem pool. This is freed when pipe is deleted. |
| 81 | * Note: DSP does actual memory management we only keep track for complete |
| 82 | * pool |
| 83 | */ |
| 84 | static void skl_tplg_alloc_pipe_mem(struct skl *skl, |
| 85 | struct skl_module_cfg *mconfig) |
| 86 | { |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 87 | skl->resource.mem += mconfig->pipe->memory_pages; |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 88 | } |
| 89 | |
| 90 | /* |
| 91 | * Pipeline needs needs DSP CPU resources for computation, this is |
| 92 | * quantified in MCPS (Million Clocks Per Second) required for module/pipe |
| 93 | * |
| 94 | * Each pipelines needs mcps to be allocated. Check if we have mcps for this |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 95 | * pipe. |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 96 | */ |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 97 | |
| 98 | static bool skl_is_pipe_mcps_avail(struct skl *skl, |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 99 | struct skl_module_cfg *mconfig) |
| 100 | { |
| 101 | struct skl_sst *ctx = skl->skl_sst; |
| 102 | |
| 103 | if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) { |
| 104 | dev_err(ctx->dev, |
| 105 | "%s: module_id %d instance %d\n", __func__, |
| 106 | mconfig->id.module_id, mconfig->id.instance_id); |
| 107 | dev_err(ctx->dev, |
Guneshwor Singh | 7ca42f5 | 2016-02-03 17:59:46 +0530 | [diff] [blame] | 108 | "exceeds ppl mcps available %d > mem %d\n", |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 109 | skl->resource.max_mcps, skl->resource.mcps); |
| 110 | return false; |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 111 | } else { |
| 112 | return true; |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 113 | } |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 114 | } |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 115 | |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 116 | static void skl_tplg_alloc_pipe_mcps(struct skl *skl, |
| 117 | struct skl_module_cfg *mconfig) |
| 118 | { |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 119 | skl->resource.mcps += mconfig->mcps; |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 120 | } |
| 121 | |
| 122 | /* |
| 123 | * Free the mcps when tearing down |
| 124 | */ |
| 125 | static void |
| 126 | skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig) |
| 127 | { |
| 128 | skl->resource.mcps -= mconfig->mcps; |
| 129 | } |
| 130 | |
| 131 | /* |
| 132 | * Free the memory when tearing down |
| 133 | */ |
| 134 | static void |
| 135 | skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig) |
| 136 | { |
| 137 | skl->resource.mem -= mconfig->pipe->memory_pages; |
| 138 | } |
| 139 | |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 140 | |
| 141 | static void skl_dump_mconfig(struct skl_sst *ctx, |
| 142 | struct skl_module_cfg *mcfg) |
| 143 | { |
| 144 | dev_dbg(ctx->dev, "Dumping config\n"); |
| 145 | dev_dbg(ctx->dev, "Input Format:\n"); |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 146 | dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels); |
| 147 | dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq); |
| 148 | dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg); |
| 149 | dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth); |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 150 | dev_dbg(ctx->dev, "Output Format:\n"); |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 151 | dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels); |
| 152 | dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq); |
| 153 | dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth); |
| 154 | dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg); |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 155 | } |
| 156 | |
| 157 | static void skl_tplg_update_params(struct skl_module_fmt *fmt, |
| 158 | struct skl_pipe_params *params, int fixup) |
| 159 | { |
| 160 | if (fixup & SKL_RATE_FIXUP_MASK) |
| 161 | fmt->s_freq = params->s_freq; |
| 162 | if (fixup & SKL_CH_FIXUP_MASK) |
| 163 | fmt->channels = params->ch; |
Jeeja KP | 98256f8 | 2015-11-23 22:26:25 +0530 | [diff] [blame] | 164 | if (fixup & SKL_FMT_FIXUP_MASK) { |
| 165 | fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt); |
| 166 | |
| 167 | /* |
| 168 | * 16 bit is 16 bit container whereas 24 bit is in 32 bit |
| 169 | * container so update bit depth accordingly |
| 170 | */ |
| 171 | switch (fmt->valid_bit_depth) { |
| 172 | case SKL_DEPTH_16BIT: |
| 173 | fmt->bit_depth = fmt->valid_bit_depth; |
| 174 | break; |
| 175 | |
| 176 | default: |
| 177 | fmt->bit_depth = SKL_DEPTH_32BIT; |
| 178 | break; |
| 179 | } |
| 180 | } |
| 181 | |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 182 | } |
| 183 | |
| 184 | /* |
| 185 | * A pipeline may have modules which impact the pcm parameters, like SRC, |
| 186 | * channel converter, format converter. |
| 187 | * We need to calculate the output params by applying the 'fixup' |
| 188 | * Topology will tell driver which type of fixup is to be applied by |
| 189 | * supplying the fixup mask, so based on that we calculate the output |
| 190 | * |
| 191 | * Now In FE the pcm hw_params is source/target format. Same is applicable |
| 192 | * for BE with its hw_params invoked. |
| 193 | * here based on FE, BE pipeline and direction we calculate the input and |
| 194 | * outfix and then apply that for a module |
| 195 | */ |
| 196 | static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg, |
| 197 | struct skl_pipe_params *params, bool is_fe) |
| 198 | { |
| 199 | int in_fixup, out_fixup; |
| 200 | struct skl_module_fmt *in_fmt, *out_fmt; |
| 201 | |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 202 | /* Fixups will be applied to pin 0 only */ |
| 203 | in_fmt = &m_cfg->in_fmt[0]; |
| 204 | out_fmt = &m_cfg->out_fmt[0]; |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 205 | |
| 206 | if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 207 | if (is_fe) { |
| 208 | in_fixup = m_cfg->params_fixup; |
| 209 | out_fixup = (~m_cfg->converter) & |
| 210 | m_cfg->params_fixup; |
| 211 | } else { |
| 212 | out_fixup = m_cfg->params_fixup; |
| 213 | in_fixup = (~m_cfg->converter) & |
| 214 | m_cfg->params_fixup; |
| 215 | } |
| 216 | } else { |
| 217 | if (is_fe) { |
| 218 | out_fixup = m_cfg->params_fixup; |
| 219 | in_fixup = (~m_cfg->converter) & |
| 220 | m_cfg->params_fixup; |
| 221 | } else { |
| 222 | in_fixup = m_cfg->params_fixup; |
| 223 | out_fixup = (~m_cfg->converter) & |
| 224 | m_cfg->params_fixup; |
| 225 | } |
| 226 | } |
| 227 | |
| 228 | skl_tplg_update_params(in_fmt, params, in_fixup); |
| 229 | skl_tplg_update_params(out_fmt, params, out_fixup); |
| 230 | } |
| 231 | |
| 232 | /* |
| 233 | * A module needs input and output buffers, which are dependent upon pcm |
| 234 | * params, so once we have calculate params, we need buffer calculation as |
| 235 | * well. |
| 236 | */ |
| 237 | static void skl_tplg_update_buffer_size(struct skl_sst *ctx, |
| 238 | struct skl_module_cfg *mcfg) |
| 239 | { |
| 240 | int multiplier = 1; |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 241 | struct skl_module_fmt *in_fmt, *out_fmt; |
| 242 | |
| 243 | |
| 244 | /* Since fixups is applied to pin 0 only, ibs, obs needs |
| 245 | * change for pin 0 only |
| 246 | */ |
| 247 | in_fmt = &mcfg->in_fmt[0]; |
| 248 | out_fmt = &mcfg->out_fmt[0]; |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 249 | |
| 250 | if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT) |
| 251 | multiplier = 5; |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 252 | mcfg->ibs = (in_fmt->s_freq / 1000) * |
| 253 | (mcfg->in_fmt->channels) * |
| 254 | (mcfg->in_fmt->bit_depth >> 3) * |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 255 | multiplier; |
| 256 | |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 257 | mcfg->obs = (mcfg->out_fmt->s_freq / 1000) * |
| 258 | (mcfg->out_fmt->channels) * |
| 259 | (mcfg->out_fmt->bit_depth >> 3) * |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 260 | multiplier; |
| 261 | } |
| 262 | |
Jeeja KP | 2d1419a | 2016-02-05 12:19:10 +0530 | [diff] [blame] | 263 | static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w, |
| 264 | struct skl_sst *ctx) |
| 265 | { |
| 266 | struct skl_module_cfg *m_cfg = w->priv; |
| 267 | int link_type, dir; |
| 268 | u32 ch, s_freq, s_fmt; |
| 269 | struct nhlt_specific_cfg *cfg; |
| 270 | struct skl *skl = get_skl_ctx(ctx->dev); |
| 271 | |
| 272 | /* check if we already have blob */ |
| 273 | if (m_cfg->formats_config.caps_size > 0) |
| 274 | return 0; |
| 275 | |
Jeeja KP | c7c6c73 | 2016-03-01 07:59:10 +0530 | [diff] [blame] | 276 | dev_dbg(ctx->dev, "Applying default cfg blob\n"); |
Jeeja KP | 2d1419a | 2016-02-05 12:19:10 +0530 | [diff] [blame] | 277 | switch (m_cfg->dev_type) { |
| 278 | case SKL_DEVICE_DMIC: |
| 279 | link_type = NHLT_LINK_DMIC; |
Jeeja KP | c7c6c73 | 2016-03-01 07:59:10 +0530 | [diff] [blame] | 280 | dir = SNDRV_PCM_STREAM_CAPTURE; |
Jeeja KP | 2d1419a | 2016-02-05 12:19:10 +0530 | [diff] [blame] | 281 | s_freq = m_cfg->in_fmt[0].s_freq; |
| 282 | s_fmt = m_cfg->in_fmt[0].bit_depth; |
| 283 | ch = m_cfg->in_fmt[0].channels; |
| 284 | break; |
| 285 | |
| 286 | case SKL_DEVICE_I2S: |
| 287 | link_type = NHLT_LINK_SSP; |
| 288 | if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) { |
Jeeja KP | c7c6c73 | 2016-03-01 07:59:10 +0530 | [diff] [blame] | 289 | dir = SNDRV_PCM_STREAM_PLAYBACK; |
Jeeja KP | 2d1419a | 2016-02-05 12:19:10 +0530 | [diff] [blame] | 290 | s_freq = m_cfg->out_fmt[0].s_freq; |
| 291 | s_fmt = m_cfg->out_fmt[0].bit_depth; |
| 292 | ch = m_cfg->out_fmt[0].channels; |
Jeeja KP | c7c6c73 | 2016-03-01 07:59:10 +0530 | [diff] [blame] | 293 | } else { |
| 294 | dir = SNDRV_PCM_STREAM_CAPTURE; |
| 295 | s_freq = m_cfg->in_fmt[0].s_freq; |
| 296 | s_fmt = m_cfg->in_fmt[0].bit_depth; |
| 297 | ch = m_cfg->in_fmt[0].channels; |
Jeeja KP | 2d1419a | 2016-02-05 12:19:10 +0530 | [diff] [blame] | 298 | } |
| 299 | break; |
| 300 | |
| 301 | default: |
| 302 | return -EINVAL; |
| 303 | } |
| 304 | |
| 305 | /* update the blob based on virtual bus_id and default params */ |
| 306 | cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type, |
| 307 | s_fmt, ch, s_freq, dir); |
| 308 | if (cfg) { |
| 309 | m_cfg->formats_config.caps_size = cfg->size; |
| 310 | m_cfg->formats_config.caps = (u32 *) &cfg->caps; |
| 311 | } else { |
| 312 | dev_err(ctx->dev, "Blob NULL for id %x type %d dirn %d\n", |
| 313 | m_cfg->vbus_id, link_type, dir); |
| 314 | dev_err(ctx->dev, "PCM: ch %d, freq %d, fmt %d\n", |
| 315 | ch, s_freq, s_fmt); |
| 316 | return -EIO; |
| 317 | } |
| 318 | |
| 319 | return 0; |
| 320 | } |
| 321 | |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 322 | static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w, |
| 323 | struct skl_sst *ctx) |
| 324 | { |
| 325 | struct skl_module_cfg *m_cfg = w->priv; |
| 326 | struct skl_pipe_params *params = m_cfg->pipe->p_params; |
| 327 | int p_conn_type = m_cfg->pipe->conn_type; |
| 328 | bool is_fe; |
| 329 | |
| 330 | if (!m_cfg->params_fixup) |
| 331 | return; |
| 332 | |
| 333 | dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n", |
| 334 | w->name); |
| 335 | |
| 336 | skl_dump_mconfig(ctx, m_cfg); |
| 337 | |
| 338 | if (p_conn_type == SKL_PIPE_CONN_TYPE_FE) |
| 339 | is_fe = true; |
| 340 | else |
| 341 | is_fe = false; |
| 342 | |
| 343 | skl_tplg_update_params_fixup(m_cfg, params, is_fe); |
| 344 | skl_tplg_update_buffer_size(ctx, m_cfg); |
| 345 | |
| 346 | dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n", |
| 347 | w->name); |
| 348 | |
| 349 | skl_dump_mconfig(ctx, m_cfg); |
| 350 | } |
| 351 | |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 352 | /* |
| 353 | * A pipe can have multiple modules, each of them will be a DAPM widget as |
| 354 | * well. While managing a pipeline we need to get the list of all the |
| 355 | * widgets in a pipelines, so this helper - skl_tplg_get_pipe_widget() helps |
| 356 | * to get the SKL type widgets in that pipeline |
| 357 | */ |
| 358 | static int skl_tplg_alloc_pipe_widget(struct device *dev, |
| 359 | struct snd_soc_dapm_widget *w, struct skl_pipe *pipe) |
| 360 | { |
| 361 | struct skl_module_cfg *src_module = NULL; |
| 362 | struct snd_soc_dapm_path *p = NULL; |
| 363 | struct skl_pipe_module *p_module = NULL; |
| 364 | |
| 365 | p_module = devm_kzalloc(dev, sizeof(*p_module), GFP_KERNEL); |
| 366 | if (!p_module) |
| 367 | return -ENOMEM; |
| 368 | |
| 369 | p_module->w = w; |
| 370 | list_add_tail(&p_module->node, &pipe->w_list); |
| 371 | |
| 372 | snd_soc_dapm_widget_for_each_sink_path(w, p) { |
| 373 | if ((p->sink->priv == NULL) |
| 374 | && (!is_skl_dsp_widget_type(w))) |
| 375 | continue; |
| 376 | |
| 377 | if ((p->sink->priv != NULL) && p->connect |
| 378 | && is_skl_dsp_widget_type(p->sink)) { |
| 379 | |
| 380 | src_module = p->sink->priv; |
| 381 | if (pipe->ppl_id == src_module->pipe->ppl_id) |
| 382 | skl_tplg_alloc_pipe_widget(dev, |
| 383 | p->sink, pipe); |
| 384 | } |
| 385 | } |
| 386 | return 0; |
| 387 | } |
| 388 | |
| 389 | /* |
Jeeja KP | abb7400 | 2015-11-28 15:01:49 +0530 | [diff] [blame] | 390 | * some modules can have multiple params set from user control and |
| 391 | * need to be set after module is initialized. If set_param flag is |
| 392 | * set module params will be done after module is initialised. |
| 393 | */ |
| 394 | static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w, |
| 395 | struct skl_sst *ctx) |
| 396 | { |
| 397 | int i, ret; |
| 398 | struct skl_module_cfg *mconfig = w->priv; |
| 399 | const struct snd_kcontrol_new *k; |
| 400 | struct soc_bytes_ext *sb; |
| 401 | struct skl_algo_data *bc; |
| 402 | struct skl_specific_cfg *sp_cfg; |
| 403 | |
| 404 | if (mconfig->formats_config.caps_size > 0 && |
Jeeja KP | 4ced182 | 2015-12-03 23:29:53 +0530 | [diff] [blame] | 405 | mconfig->formats_config.set_params == SKL_PARAM_SET) { |
Jeeja KP | abb7400 | 2015-11-28 15:01:49 +0530 | [diff] [blame] | 406 | sp_cfg = &mconfig->formats_config; |
| 407 | ret = skl_set_module_params(ctx, sp_cfg->caps, |
| 408 | sp_cfg->caps_size, |
| 409 | sp_cfg->param_id, mconfig); |
| 410 | if (ret < 0) |
| 411 | return ret; |
| 412 | } |
| 413 | |
| 414 | for (i = 0; i < w->num_kcontrols; i++) { |
| 415 | k = &w->kcontrol_news[i]; |
| 416 | if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { |
| 417 | sb = (void *) k->private_value; |
| 418 | bc = (struct skl_algo_data *)sb->dobj.private; |
| 419 | |
Jeeja KP | 4ced182 | 2015-12-03 23:29:53 +0530 | [diff] [blame] | 420 | if (bc->set_params == SKL_PARAM_SET) { |
Jeeja KP | abb7400 | 2015-11-28 15:01:49 +0530 | [diff] [blame] | 421 | ret = skl_set_module_params(ctx, |
| 422 | (u32 *)bc->params, bc->max, |
| 423 | bc->param_id, mconfig); |
| 424 | if (ret < 0) |
| 425 | return ret; |
| 426 | } |
| 427 | } |
| 428 | } |
| 429 | |
| 430 | return 0; |
| 431 | } |
| 432 | |
| 433 | /* |
| 434 | * some module param can set from user control and this is required as |
| 435 | * when module is initailzed. if module param is required in init it is |
| 436 | * identifed by set_param flag. if set_param flag is not set, then this |
| 437 | * parameter needs to set as part of module init. |
| 438 | */ |
| 439 | static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w) |
| 440 | { |
| 441 | const struct snd_kcontrol_new *k; |
| 442 | struct soc_bytes_ext *sb; |
| 443 | struct skl_algo_data *bc; |
| 444 | struct skl_module_cfg *mconfig = w->priv; |
| 445 | int i; |
| 446 | |
| 447 | for (i = 0; i < w->num_kcontrols; i++) { |
| 448 | k = &w->kcontrol_news[i]; |
| 449 | if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { |
| 450 | sb = (struct soc_bytes_ext *)k->private_value; |
| 451 | bc = (struct skl_algo_data *)sb->dobj.private; |
| 452 | |
Jeeja KP | 4ced182 | 2015-12-03 23:29:53 +0530 | [diff] [blame] | 453 | if (bc->set_params != SKL_PARAM_INIT) |
Jeeja KP | abb7400 | 2015-11-28 15:01:49 +0530 | [diff] [blame] | 454 | continue; |
| 455 | |
| 456 | mconfig->formats_config.caps = (u32 *)&bc->params; |
| 457 | mconfig->formats_config.caps_size = bc->max; |
| 458 | |
| 459 | break; |
| 460 | } |
| 461 | } |
| 462 | |
| 463 | return 0; |
| 464 | } |
| 465 | |
| 466 | /* |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 467 | * Inside a pipe instance, we can have various modules. These modules need |
| 468 | * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by |
| 469 | * skl_init_module() routine, so invoke that for all modules in a pipeline |
| 470 | */ |
| 471 | static int |
| 472 | skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe) |
| 473 | { |
| 474 | struct skl_pipe_module *w_module; |
| 475 | struct snd_soc_dapm_widget *w; |
| 476 | struct skl_module_cfg *mconfig; |
| 477 | struct skl_sst *ctx = skl->skl_sst; |
| 478 | int ret = 0; |
| 479 | |
| 480 | list_for_each_entry(w_module, &pipe->w_list, node) { |
| 481 | w = w_module->w; |
| 482 | mconfig = w->priv; |
| 483 | |
| 484 | /* check resource available */ |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 485 | if (!skl_is_pipe_mcps_avail(skl, mconfig)) |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 486 | return -ENOMEM; |
| 487 | |
Dharageswari R | 6c5768b | 2015-12-03 23:29:50 +0530 | [diff] [blame] | 488 | if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) { |
| 489 | ret = ctx->dsp->fw_ops.load_mod(ctx->dsp, |
| 490 | mconfig->id.module_id, mconfig->guid); |
| 491 | if (ret < 0) |
| 492 | return ret; |
| 493 | } |
| 494 | |
Jeeja KP | 2d1419a | 2016-02-05 12:19:10 +0530 | [diff] [blame] | 495 | /* update blob if blob is null for be with default value */ |
| 496 | skl_tplg_update_be_blob(w, ctx); |
| 497 | |
Jeeja KP | f7590d4 | 2015-10-07 11:31:53 +0100 | [diff] [blame] | 498 | /* |
| 499 | * apply fix/conversion to module params based on |
| 500 | * FE/BE params |
| 501 | */ |
| 502 | skl_tplg_update_module_params(w, ctx); |
Jeeja KP | abb7400 | 2015-11-28 15:01:49 +0530 | [diff] [blame] | 503 | |
| 504 | skl_tplg_set_module_init_data(w); |
Jeeja KP | 9939a9c | 2015-11-28 15:01:47 +0530 | [diff] [blame] | 505 | ret = skl_init_module(ctx, mconfig); |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 506 | if (ret < 0) |
| 507 | return ret; |
Jeeja KP | abb7400 | 2015-11-28 15:01:49 +0530 | [diff] [blame] | 508 | |
| 509 | ret = skl_tplg_set_module_params(w, ctx); |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 510 | if (ret < 0) |
| 511 | return ret; |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 512 | skl_tplg_alloc_pipe_mcps(skl, mconfig); |
Jeeja KP | e4e2d2f | 2015-10-07 11:31:52 +0100 | [diff] [blame] | 513 | } |
| 514 | |
| 515 | return 0; |
| 516 | } |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 517 | |
Dharageswari R | 6c5768b | 2015-12-03 23:29:50 +0530 | [diff] [blame] | 518 | static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx, |
| 519 | struct skl_pipe *pipe) |
| 520 | { |
| 521 | struct skl_pipe_module *w_module = NULL; |
| 522 | struct skl_module_cfg *mconfig = NULL; |
| 523 | |
| 524 | list_for_each_entry(w_module, &pipe->w_list, node) { |
| 525 | mconfig = w_module->w->priv; |
| 526 | |
| 527 | if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod) |
| 528 | return ctx->dsp->fw_ops.unload_mod(ctx->dsp, |
| 529 | mconfig->id.module_id); |
| 530 | } |
| 531 | |
| 532 | /* no modules to unload in this path, so return */ |
| 533 | return 0; |
| 534 | } |
| 535 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 536 | /* |
| 537 | * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we |
| 538 | * need create the pipeline. So we do following: |
| 539 | * - check the resources |
| 540 | * - Create the pipeline |
| 541 | * - Initialize the modules in pipeline |
| 542 | * - finally bind all modules together |
| 543 | */ |
| 544 | static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w, |
| 545 | struct skl *skl) |
| 546 | { |
| 547 | int ret; |
| 548 | struct skl_module_cfg *mconfig = w->priv; |
| 549 | struct skl_pipe_module *w_module; |
| 550 | struct skl_pipe *s_pipe = mconfig->pipe; |
| 551 | struct skl_module_cfg *src_module = NULL, *dst_module; |
| 552 | struct skl_sst *ctx = skl->skl_sst; |
| 553 | |
| 554 | /* check resource available */ |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 555 | if (!skl_is_pipe_mcps_avail(skl, mconfig)) |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 556 | return -EBUSY; |
| 557 | |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 558 | if (!skl_is_pipe_mem_avail(skl, mconfig)) |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 559 | return -ENOMEM; |
| 560 | |
| 561 | /* |
| 562 | * Create a list of modules for pipe. |
| 563 | * This list contains modules from source to sink |
| 564 | */ |
| 565 | ret = skl_create_pipeline(ctx, mconfig->pipe); |
| 566 | if (ret < 0) |
| 567 | return ret; |
| 568 | |
| 569 | /* |
| 570 | * we create a w_list of all widgets in that pipe. This list is not |
| 571 | * freed on PMD event as widgets within a pipe are static. This |
| 572 | * saves us cycles to get widgets in pipe every time. |
| 573 | * |
| 574 | * So if we have already initialized all the widgets of a pipeline |
| 575 | * we skip, so check for list_empty and create the list if empty |
| 576 | */ |
| 577 | if (list_empty(&s_pipe->w_list)) { |
| 578 | ret = skl_tplg_alloc_pipe_widget(ctx->dev, w, s_pipe); |
| 579 | if (ret < 0) |
| 580 | return ret; |
| 581 | } |
| 582 | |
| 583 | /* Init all pipe modules from source to sink */ |
| 584 | ret = skl_tplg_init_pipe_modules(skl, s_pipe); |
| 585 | if (ret < 0) |
| 586 | return ret; |
| 587 | |
| 588 | /* Bind modules from source to sink */ |
| 589 | list_for_each_entry(w_module, &s_pipe->w_list, node) { |
| 590 | dst_module = w_module->w->priv; |
| 591 | |
| 592 | if (src_module == NULL) { |
| 593 | src_module = dst_module; |
| 594 | continue; |
| 595 | } |
| 596 | |
| 597 | ret = skl_bind_modules(ctx, src_module, dst_module); |
| 598 | if (ret < 0) |
| 599 | return ret; |
| 600 | |
| 601 | src_module = dst_module; |
| 602 | } |
| 603 | |
Dharageswari.R | 9ba8ffe | 2016-02-03 17:59:47 +0530 | [diff] [blame] | 604 | skl_tplg_alloc_pipe_mem(skl, mconfig); |
| 605 | skl_tplg_alloc_pipe_mcps(skl, mconfig); |
| 606 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 607 | return 0; |
| 608 | } |
| 609 | |
Jeeja KP | cc6a404 | 2016-02-05 12:19:08 +0530 | [diff] [blame] | 610 | /* |
| 611 | * Some modules require params to be set after the module is bound to |
| 612 | * all pins connected. |
| 613 | * |
| 614 | * The module provider initializes set_param flag for such modules and we |
| 615 | * send params after binding |
| 616 | */ |
| 617 | static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w, |
| 618 | struct skl_module_cfg *mcfg, struct skl_sst *ctx) |
| 619 | { |
| 620 | int i, ret; |
| 621 | struct skl_module_cfg *mconfig = w->priv; |
| 622 | const struct snd_kcontrol_new *k; |
| 623 | struct soc_bytes_ext *sb; |
| 624 | struct skl_algo_data *bc; |
| 625 | struct skl_specific_cfg *sp_cfg; |
| 626 | |
| 627 | /* |
| 628 | * check all out/in pins are in bind state. |
| 629 | * if so set the module param |
| 630 | */ |
| 631 | for (i = 0; i < mcfg->max_out_queue; i++) { |
| 632 | if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE) |
| 633 | return 0; |
| 634 | } |
| 635 | |
| 636 | for (i = 0; i < mcfg->max_in_queue; i++) { |
| 637 | if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE) |
| 638 | return 0; |
| 639 | } |
| 640 | |
| 641 | if (mconfig->formats_config.caps_size > 0 && |
| 642 | mconfig->formats_config.set_params == SKL_PARAM_BIND) { |
| 643 | sp_cfg = &mconfig->formats_config; |
| 644 | ret = skl_set_module_params(ctx, sp_cfg->caps, |
| 645 | sp_cfg->caps_size, |
| 646 | sp_cfg->param_id, mconfig); |
| 647 | if (ret < 0) |
| 648 | return ret; |
| 649 | } |
| 650 | |
| 651 | for (i = 0; i < w->num_kcontrols; i++) { |
| 652 | k = &w->kcontrol_news[i]; |
| 653 | if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { |
| 654 | sb = (void *) k->private_value; |
| 655 | bc = (struct skl_algo_data *)sb->dobj.private; |
| 656 | |
| 657 | if (bc->set_params == SKL_PARAM_BIND) { |
| 658 | ret = skl_set_module_params(ctx, |
| 659 | (u32 *)bc->params, bc->max, |
| 660 | bc->param_id, mconfig); |
| 661 | if (ret < 0) |
| 662 | return ret; |
| 663 | } |
| 664 | } |
| 665 | } |
| 666 | |
| 667 | return 0; |
| 668 | } |
| 669 | |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 670 | static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w, |
| 671 | struct skl *skl, |
Jeeja KP | 6bd4cf8 | 2016-02-03 17:59:51 +0530 | [diff] [blame] | 672 | struct snd_soc_dapm_widget *src_w, |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 673 | struct skl_module_cfg *src_mconfig) |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 674 | { |
| 675 | struct snd_soc_dapm_path *p; |
Jeeja KP | 0ed95d7 | 2015-11-13 19:22:11 +0530 | [diff] [blame] | 676 | struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL; |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 677 | struct skl_module_cfg *sink_mconfig; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 678 | struct skl_sst *ctx = skl->skl_sst; |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 679 | int ret; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 680 | |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 681 | snd_soc_dapm_widget_for_each_sink_path(w, p) { |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 682 | if (!p->connect) |
| 683 | continue; |
| 684 | |
| 685 | dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name); |
| 686 | dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name); |
| 687 | |
Jeeja KP | 0ed95d7 | 2015-11-13 19:22:11 +0530 | [diff] [blame] | 688 | next_sink = p->sink; |
Jeeja KP | 6bd4cf8 | 2016-02-03 17:59:51 +0530 | [diff] [blame] | 689 | |
| 690 | if (!is_skl_dsp_widget_type(p->sink)) |
| 691 | return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig); |
| 692 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 693 | /* |
| 694 | * here we will check widgets in sink pipelines, so that |
| 695 | * can be any widgets type and we are only interested if |
| 696 | * they are ones used for SKL so check that first |
| 697 | */ |
| 698 | if ((p->sink->priv != NULL) && |
| 699 | is_skl_dsp_widget_type(p->sink)) { |
| 700 | |
| 701 | sink = p->sink; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 702 | sink_mconfig = sink->priv; |
| 703 | |
Jeeja KP | cc6a404 | 2016-02-05 12:19:08 +0530 | [diff] [blame] | 704 | if (src_mconfig->m_state == SKL_MODULE_UNINIT || |
| 705 | sink_mconfig->m_state == SKL_MODULE_UNINIT) |
| 706 | continue; |
| 707 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 708 | /* Bind source to sink, mixin is always source */ |
| 709 | ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig); |
| 710 | if (ret) |
| 711 | return ret; |
| 712 | |
Jeeja KP | cc6a404 | 2016-02-05 12:19:08 +0530 | [diff] [blame] | 713 | /* set module params after bind */ |
| 714 | skl_tplg_set_module_bind_params(src_w, src_mconfig, ctx); |
| 715 | skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx); |
| 716 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 717 | /* Start sinks pipe first */ |
| 718 | if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) { |
Jeeja KP | d1730c3 | 2015-10-27 09:22:53 +0900 | [diff] [blame] | 719 | if (sink_mconfig->pipe->conn_type != |
| 720 | SKL_PIPE_CONN_TYPE_FE) |
| 721 | ret = skl_run_pipe(ctx, |
| 722 | sink_mconfig->pipe); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 723 | if (ret) |
| 724 | return ret; |
| 725 | } |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 726 | } |
| 727 | } |
| 728 | |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 729 | if (!sink) |
Jeeja KP | 6bd4cf8 | 2016-02-03 17:59:51 +0530 | [diff] [blame] | 730 | return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig); |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 731 | |
| 732 | return 0; |
| 733 | } |
| 734 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 735 | /* |
| 736 | * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA |
| 737 | * we need to do following: |
| 738 | * - Bind to sink pipeline |
| 739 | * Since the sink pipes can be running and we don't get mixer event on |
| 740 | * connect for already running mixer, we need to find the sink pipes |
| 741 | * here and bind to them. This way dynamic connect works. |
| 742 | * - Start sink pipeline, if not running |
| 743 | * - Then run current pipe |
| 744 | */ |
| 745 | static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w, |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 746 | struct skl *skl) |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 747 | { |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 748 | struct skl_module_cfg *src_mconfig; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 749 | struct skl_sst *ctx = skl->skl_sst; |
| 750 | int ret = 0; |
| 751 | |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 752 | src_mconfig = w->priv; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 753 | |
| 754 | /* |
| 755 | * find which sink it is connected to, bind with the sink, |
| 756 | * if sink is not started, start sink pipe first, then start |
| 757 | * this pipe |
| 758 | */ |
Jeeja KP | 6bd4cf8 | 2016-02-03 17:59:51 +0530 | [diff] [blame] | 759 | ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 760 | if (ret) |
| 761 | return ret; |
| 762 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 763 | /* Start source pipe last after starting all sinks */ |
Jeeja KP | d1730c3 | 2015-10-27 09:22:53 +0900 | [diff] [blame] | 764 | if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE) |
| 765 | return skl_run_pipe(ctx, src_mconfig->pipe); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 766 | |
| 767 | return 0; |
| 768 | } |
| 769 | |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 770 | static struct snd_soc_dapm_widget *skl_get_src_dsp_widget( |
| 771 | struct snd_soc_dapm_widget *w, struct skl *skl) |
| 772 | { |
| 773 | struct snd_soc_dapm_path *p; |
| 774 | struct snd_soc_dapm_widget *src_w = NULL; |
| 775 | struct skl_sst *ctx = skl->skl_sst; |
| 776 | |
| 777 | snd_soc_dapm_widget_for_each_source_path(w, p) { |
| 778 | src_w = p->source; |
| 779 | if (!p->connect) |
| 780 | continue; |
| 781 | |
| 782 | dev_dbg(ctx->dev, "sink widget=%s\n", w->name); |
| 783 | dev_dbg(ctx->dev, "src widget=%s\n", p->source->name); |
| 784 | |
| 785 | /* |
| 786 | * here we will check widgets in sink pipelines, so that can |
| 787 | * be any widgets type and we are only interested if they are |
| 788 | * ones used for SKL so check that first |
| 789 | */ |
| 790 | if ((p->source->priv != NULL) && |
| 791 | is_skl_dsp_widget_type(p->source)) { |
| 792 | return p->source; |
| 793 | } |
| 794 | } |
| 795 | |
| 796 | if (src_w != NULL) |
| 797 | return skl_get_src_dsp_widget(src_w, skl); |
| 798 | |
| 799 | return NULL; |
| 800 | } |
| 801 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 802 | /* |
| 803 | * in the Post-PMU event of mixer we need to do following: |
| 804 | * - Check if this pipe is running |
| 805 | * - if not, then |
| 806 | * - bind this pipeline to its source pipeline |
| 807 | * if source pipe is already running, this means it is a dynamic |
| 808 | * connection and we need to bind only to that pipe |
| 809 | * - start this pipeline |
| 810 | */ |
| 811 | static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w, |
| 812 | struct skl *skl) |
| 813 | { |
| 814 | int ret = 0; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 815 | struct snd_soc_dapm_widget *source, *sink; |
| 816 | struct skl_module_cfg *src_mconfig, *sink_mconfig; |
| 817 | struct skl_sst *ctx = skl->skl_sst; |
| 818 | int src_pipe_started = 0; |
| 819 | |
| 820 | sink = w; |
| 821 | sink_mconfig = sink->priv; |
| 822 | |
| 823 | /* |
| 824 | * If source pipe is already started, that means source is driving |
| 825 | * one more sink before this sink got connected, Since source is |
| 826 | * started, bind this sink to source and start this pipe. |
| 827 | */ |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 828 | source = skl_get_src_dsp_widget(w, skl); |
| 829 | if (source != NULL) { |
| 830 | src_mconfig = source->priv; |
| 831 | sink_mconfig = sink->priv; |
| 832 | src_pipe_started = 1; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 833 | |
| 834 | /* |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 835 | * check pipe state, then no need to bind or start the |
| 836 | * pipe |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 837 | */ |
Jeeja KP | 8724ff1 | 2015-10-27 09:22:52 +0900 | [diff] [blame] | 838 | if (src_mconfig->pipe->state != SKL_PIPE_STARTED) |
| 839 | src_pipe_started = 0; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 840 | } |
| 841 | |
| 842 | if (src_pipe_started) { |
| 843 | ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig); |
| 844 | if (ret) |
| 845 | return ret; |
| 846 | |
Jeeja KP | cc6a404 | 2016-02-05 12:19:08 +0530 | [diff] [blame] | 847 | /* set module params after bind */ |
| 848 | skl_tplg_set_module_bind_params(source, src_mconfig, ctx); |
| 849 | skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx); |
| 850 | |
Jeeja KP | d1730c3 | 2015-10-27 09:22:53 +0900 | [diff] [blame] | 851 | if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE) |
| 852 | ret = skl_run_pipe(ctx, sink_mconfig->pipe); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 853 | } |
| 854 | |
| 855 | return ret; |
| 856 | } |
| 857 | |
| 858 | /* |
| 859 | * in the Pre-PMD event of mixer we need to do following: |
| 860 | * - Stop the pipe |
| 861 | * - find the source connections and remove that from dapm_path_list |
| 862 | * - unbind with source pipelines if still connected |
| 863 | */ |
| 864 | static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w, |
| 865 | struct skl *skl) |
| 866 | { |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 867 | struct skl_module_cfg *src_mconfig, *sink_mconfig; |
Jeeja KP | ce1b555 | 2015-10-27 09:22:51 +0900 | [diff] [blame] | 868 | int ret = 0, i; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 869 | struct skl_sst *ctx = skl->skl_sst; |
| 870 | |
Jeeja KP | ce1b555 | 2015-10-27 09:22:51 +0900 | [diff] [blame] | 871 | sink_mconfig = w->priv; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 872 | |
| 873 | /* Stop the pipe */ |
| 874 | ret = skl_stop_pipe(ctx, sink_mconfig->pipe); |
| 875 | if (ret) |
| 876 | return ret; |
| 877 | |
Jeeja KP | ce1b555 | 2015-10-27 09:22:51 +0900 | [diff] [blame] | 878 | for (i = 0; i < sink_mconfig->max_in_queue; i++) { |
| 879 | if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) { |
| 880 | src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg; |
| 881 | if (!src_mconfig) |
| 882 | continue; |
| 883 | /* |
| 884 | * If path_found == 1, that means pmd for source |
| 885 | * pipe has not occurred, source is connected to |
| 886 | * some other sink. so its responsibility of sink |
| 887 | * to unbind itself from source. |
| 888 | */ |
| 889 | ret = skl_stop_pipe(ctx, src_mconfig->pipe); |
| 890 | if (ret < 0) |
| 891 | return ret; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 892 | |
Jeeja KP | ce1b555 | 2015-10-27 09:22:51 +0900 | [diff] [blame] | 893 | ret = skl_unbind_modules(ctx, |
| 894 | src_mconfig, sink_mconfig); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 895 | } |
| 896 | } |
| 897 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 898 | return ret; |
| 899 | } |
| 900 | |
| 901 | /* |
| 902 | * in the Post-PMD event of mixer we need to do following: |
| 903 | * - Free the mcps used |
| 904 | * - Free the mem used |
| 905 | * - Unbind the modules within the pipeline |
| 906 | * - Delete the pipeline (modules are not required to be explicitly |
| 907 | * deleted, pipeline delete is enough here |
| 908 | */ |
| 909 | static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w, |
| 910 | struct skl *skl) |
| 911 | { |
| 912 | struct skl_module_cfg *mconfig = w->priv; |
| 913 | struct skl_pipe_module *w_module; |
| 914 | struct skl_module_cfg *src_module = NULL, *dst_module; |
| 915 | struct skl_sst *ctx = skl->skl_sst; |
| 916 | struct skl_pipe *s_pipe = mconfig->pipe; |
| 917 | int ret = 0; |
| 918 | |
| 919 | skl_tplg_free_pipe_mcps(skl, mconfig); |
Vinod Koul | 6597687 | 2015-11-23 22:26:29 +0530 | [diff] [blame] | 920 | skl_tplg_free_pipe_mem(skl, mconfig); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 921 | |
| 922 | list_for_each_entry(w_module, &s_pipe->w_list, node) { |
| 923 | dst_module = w_module->w->priv; |
| 924 | |
Vinod Koul | 7ae3cb1 | 2015-11-05 21:34:10 +0530 | [diff] [blame] | 925 | skl_tplg_free_pipe_mcps(skl, dst_module); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 926 | if (src_module == NULL) { |
| 927 | src_module = dst_module; |
| 928 | continue; |
| 929 | } |
| 930 | |
Guneshwor Singh | 7ca42f5 | 2016-02-03 17:59:46 +0530 | [diff] [blame] | 931 | skl_unbind_modules(ctx, src_module, dst_module); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 932 | src_module = dst_module; |
| 933 | } |
| 934 | |
| 935 | ret = skl_delete_pipe(ctx, mconfig->pipe); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 936 | |
Dharageswari R | 6c5768b | 2015-12-03 23:29:50 +0530 | [diff] [blame] | 937 | return skl_tplg_unload_pipe_modules(ctx, s_pipe); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 938 | } |
| 939 | |
| 940 | /* |
| 941 | * in the Post-PMD event of PGA we need to do following: |
| 942 | * - Free the mcps used |
| 943 | * - Stop the pipeline |
| 944 | * - In source pipe is connected, unbind with source pipelines |
| 945 | */ |
| 946 | static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w, |
| 947 | struct skl *skl) |
| 948 | { |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 949 | struct skl_module_cfg *src_mconfig, *sink_mconfig; |
Jeeja KP | ce1b555 | 2015-10-27 09:22:51 +0900 | [diff] [blame] | 950 | int ret = 0, i; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 951 | struct skl_sst *ctx = skl->skl_sst; |
| 952 | |
Jeeja KP | ce1b555 | 2015-10-27 09:22:51 +0900 | [diff] [blame] | 953 | src_mconfig = w->priv; |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 954 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 955 | /* Stop the pipe since this is a mixin module */ |
| 956 | ret = skl_stop_pipe(ctx, src_mconfig->pipe); |
| 957 | if (ret) |
| 958 | return ret; |
| 959 | |
Jeeja KP | ce1b555 | 2015-10-27 09:22:51 +0900 | [diff] [blame] | 960 | for (i = 0; i < src_mconfig->max_out_queue; i++) { |
| 961 | if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) { |
| 962 | sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg; |
| 963 | if (!sink_mconfig) |
| 964 | continue; |
| 965 | /* |
| 966 | * This is a connecter and if path is found that means |
| 967 | * unbind between source and sink has not happened yet |
| 968 | */ |
Jeeja KP | ce1b555 | 2015-10-27 09:22:51 +0900 | [diff] [blame] | 969 | ret = skl_unbind_modules(ctx, src_mconfig, |
| 970 | sink_mconfig); |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 971 | } |
| 972 | } |
| 973 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 974 | return ret; |
| 975 | } |
| 976 | |
| 977 | /* |
| 978 | * In modelling, we assume there will be ONLY one mixer in a pipeline. If |
| 979 | * mixer is not required then it is treated as static mixer aka vmixer with |
| 980 | * a hard path to source module |
| 981 | * So we don't need to check if source is started or not as hard path puts |
| 982 | * dependency on each other |
| 983 | */ |
| 984 | static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w, |
| 985 | struct snd_kcontrol *k, int event) |
| 986 | { |
| 987 | struct snd_soc_dapm_context *dapm = w->dapm; |
| 988 | struct skl *skl = get_skl_ctx(dapm->dev); |
| 989 | |
| 990 | switch (event) { |
| 991 | case SND_SOC_DAPM_PRE_PMU: |
| 992 | return skl_tplg_mixer_dapm_pre_pmu_event(w, skl); |
| 993 | |
Jeeja KP | de1fedf | 2016-02-03 17:59:52 +0530 | [diff] [blame] | 994 | case SND_SOC_DAPM_POST_PMU: |
| 995 | return skl_tplg_mixer_dapm_post_pmu_event(w, skl); |
| 996 | |
| 997 | case SND_SOC_DAPM_PRE_PMD: |
| 998 | return skl_tplg_mixer_dapm_pre_pmd_event(w, skl); |
| 999 | |
Vinod Koul | d93f8e5 | 2015-10-07 11:31:54 +0100 | [diff] [blame] | 1000 | case SND_SOC_DAPM_POST_PMD: |
| 1001 | return skl_tplg_mixer_dapm_post_pmd_event(w, skl); |
| 1002 | } |
| 1003 | |
| 1004 | return 0; |
| 1005 | } |
| 1006 | |
| 1007 | /* |
| 1008 | * In modelling, we assume there will be ONLY one mixer in a pipeline. If a |
| 1009 | * second one is required that is created as another pipe entity. |
| 1010 | * The mixer is responsible for pipe management and represent a pipeline |
| 1011 | * instance |
| 1012 | */ |
| 1013 | static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w, |
| 1014 | struct snd_kcontrol *k, int event) |
| 1015 | { |
| 1016 | struct snd_soc_dapm_context *dapm = w->dapm; |
| 1017 | struct skl *skl = get_skl_ctx(dapm->dev); |
| 1018 | |
| 1019 | switch (event) { |
| 1020 | case SND_SOC_DAPM_PRE_PMU: |
| 1021 | return skl_tplg_mixer_dapm_pre_pmu_event(w, skl); |
| 1022 | |
| 1023 | case SND_SOC_DAPM_POST_PMU: |
| 1024 | return skl_tplg_mixer_dapm_post_pmu_event(w, skl); |
| 1025 | |
| 1026 | case SND_SOC_DAPM_PRE_PMD: |
| 1027 | return skl_tplg_mixer_dapm_pre_pmd_event(w, skl); |
| 1028 | |
| 1029 | case SND_SOC_DAPM_POST_PMD: |
| 1030 | return skl_tplg_mixer_dapm_post_pmd_event(w, skl); |
| 1031 | } |
| 1032 | |
| 1033 | return 0; |
| 1034 | } |
| 1035 | |
| 1036 | /* |
| 1037 | * In modelling, we assumed rest of the modules in pipeline are PGA. But we |
| 1038 | * are interested in last PGA (leaf PGA) in a pipeline to disconnect with |
| 1039 | * the sink when it is running (two FE to one BE or one FE to two BE) |
| 1040 | * scenarios |
| 1041 | */ |
| 1042 | static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w, |
| 1043 | struct snd_kcontrol *k, int event) |
| 1044 | |
| 1045 | { |
| 1046 | struct snd_soc_dapm_context *dapm = w->dapm; |
| 1047 | struct skl *skl = get_skl_ctx(dapm->dev); |
| 1048 | |
| 1049 | switch (event) { |
| 1050 | case SND_SOC_DAPM_PRE_PMU: |
| 1051 | return skl_tplg_pga_dapm_pre_pmu_event(w, skl); |
| 1052 | |
| 1053 | case SND_SOC_DAPM_POST_PMD: |
| 1054 | return skl_tplg_pga_dapm_post_pmd_event(w, skl); |
| 1055 | } |
| 1056 | |
| 1057 | return 0; |
| 1058 | } |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1059 | |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 1060 | static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol, |
| 1061 | unsigned int __user *data, unsigned int size) |
| 1062 | { |
| 1063 | struct soc_bytes_ext *sb = |
| 1064 | (struct soc_bytes_ext *)kcontrol->private_value; |
| 1065 | struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private; |
Omair M Abdullah | 7d9f291 | 2015-12-03 23:29:56 +0530 | [diff] [blame] | 1066 | struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol); |
| 1067 | struct skl_module_cfg *mconfig = w->priv; |
| 1068 | struct skl *skl = get_skl_ctx(w->dapm->dev); |
| 1069 | |
| 1070 | if (w->power) |
| 1071 | skl_get_module_params(skl->skl_sst, (u32 *)bc->params, |
| 1072 | bc->max, bc->param_id, mconfig); |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 1073 | |
Vinod Koul | 41556f6 | 2016-02-03 17:59:44 +0530 | [diff] [blame] | 1074 | /* decrement size for TLV header */ |
| 1075 | size -= 2 * sizeof(u32); |
| 1076 | |
| 1077 | /* check size as we don't want to send kernel data */ |
| 1078 | if (size > bc->max) |
| 1079 | size = bc->max; |
| 1080 | |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 1081 | if (bc->params) { |
| 1082 | if (copy_to_user(data, &bc->param_id, sizeof(u32))) |
| 1083 | return -EFAULT; |
Dan Carpenter | e8bc3c9 | 2015-12-08 08:53:22 +0300 | [diff] [blame] | 1084 | if (copy_to_user(data + 1, &size, sizeof(u32))) |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 1085 | return -EFAULT; |
Dan Carpenter | e8bc3c9 | 2015-12-08 08:53:22 +0300 | [diff] [blame] | 1086 | if (copy_to_user(data + 2, bc->params, size)) |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 1087 | return -EFAULT; |
| 1088 | } |
| 1089 | |
| 1090 | return 0; |
| 1091 | } |
| 1092 | |
| 1093 | #define SKL_PARAM_VENDOR_ID 0xff |
| 1094 | |
| 1095 | static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol, |
| 1096 | const unsigned int __user *data, unsigned int size) |
| 1097 | { |
| 1098 | struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol); |
| 1099 | struct skl_module_cfg *mconfig = w->priv; |
| 1100 | struct soc_bytes_ext *sb = |
| 1101 | (struct soc_bytes_ext *)kcontrol->private_value; |
| 1102 | struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private; |
| 1103 | struct skl *skl = get_skl_ctx(w->dapm->dev); |
| 1104 | |
| 1105 | if (ac->params) { |
| 1106 | /* |
| 1107 | * if the param_is is of type Vendor, firmware expects actual |
| 1108 | * parameter id and size from the control. |
| 1109 | */ |
| 1110 | if (ac->param_id == SKL_PARAM_VENDOR_ID) { |
| 1111 | if (copy_from_user(ac->params, data, size)) |
| 1112 | return -EFAULT; |
| 1113 | } else { |
| 1114 | if (copy_from_user(ac->params, |
Alan | 65b4bcb | 2016-02-19 11:42:32 +0530 | [diff] [blame] | 1115 | data + 2, size)) |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 1116 | return -EFAULT; |
| 1117 | } |
| 1118 | |
| 1119 | if (w->power) |
| 1120 | return skl_set_module_params(skl->skl_sst, |
| 1121 | (u32 *)ac->params, ac->max, |
| 1122 | ac->param_id, mconfig); |
| 1123 | } |
| 1124 | |
| 1125 | return 0; |
| 1126 | } |
| 1127 | |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1128 | /* |
| 1129 | * The FE params are passed by hw_params of the DAI. |
| 1130 | * On hw_params, the params are stored in Gateway module of the FE and we |
| 1131 | * need to calculate the format in DSP module configuration, that |
| 1132 | * conversion is done here |
| 1133 | */ |
| 1134 | int skl_tplg_update_pipe_params(struct device *dev, |
| 1135 | struct skl_module_cfg *mconfig, |
| 1136 | struct skl_pipe_params *params) |
| 1137 | { |
| 1138 | struct skl_pipe *pipe = mconfig->pipe; |
| 1139 | struct skl_module_fmt *format = NULL; |
| 1140 | |
| 1141 | memcpy(pipe->p_params, params, sizeof(*params)); |
| 1142 | |
| 1143 | if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 1144 | format = &mconfig->in_fmt[0]; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1145 | else |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 1146 | format = &mconfig->out_fmt[0]; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1147 | |
| 1148 | /* set the hw_params */ |
| 1149 | format->s_freq = params->s_freq; |
| 1150 | format->channels = params->ch; |
| 1151 | format->valid_bit_depth = skl_get_bit_depth(params->s_fmt); |
| 1152 | |
| 1153 | /* |
| 1154 | * 16 bit is 16 bit container whereas 24 bit is in 32 bit |
| 1155 | * container so update bit depth accordingly |
| 1156 | */ |
| 1157 | switch (format->valid_bit_depth) { |
| 1158 | case SKL_DEPTH_16BIT: |
| 1159 | format->bit_depth = format->valid_bit_depth; |
| 1160 | break; |
| 1161 | |
| 1162 | case SKL_DEPTH_24BIT: |
Jeeja KP | 6654f39 | 2015-10-27 09:22:46 +0900 | [diff] [blame] | 1163 | case SKL_DEPTH_32BIT: |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1164 | format->bit_depth = SKL_DEPTH_32BIT; |
| 1165 | break; |
| 1166 | |
| 1167 | default: |
| 1168 | dev_err(dev, "Invalid bit depth %x for pipe\n", |
| 1169 | format->valid_bit_depth); |
| 1170 | return -EINVAL; |
| 1171 | } |
| 1172 | |
| 1173 | if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 1174 | mconfig->ibs = (format->s_freq / 1000) * |
| 1175 | (format->channels) * |
| 1176 | (format->bit_depth >> 3); |
| 1177 | } else { |
| 1178 | mconfig->obs = (format->s_freq / 1000) * |
| 1179 | (format->channels) * |
| 1180 | (format->bit_depth >> 3); |
| 1181 | } |
| 1182 | |
| 1183 | return 0; |
| 1184 | } |
| 1185 | |
| 1186 | /* |
| 1187 | * Query the module config for the FE DAI |
| 1188 | * This is used to find the hw_params set for that DAI and apply to FE |
| 1189 | * pipeline |
| 1190 | */ |
| 1191 | struct skl_module_cfg * |
| 1192 | skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream) |
| 1193 | { |
| 1194 | struct snd_soc_dapm_widget *w; |
| 1195 | struct snd_soc_dapm_path *p = NULL; |
| 1196 | |
| 1197 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 1198 | w = dai->playback_widget; |
Subhransu S. Prusty | f0900eb | 2015-10-22 23:22:36 +0530 | [diff] [blame] | 1199 | snd_soc_dapm_widget_for_each_sink_path(w, p) { |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1200 | if (p->connect && p->sink->power && |
Jeeja KP | a28f51d | 2015-10-27 09:22:44 +0900 | [diff] [blame] | 1201 | !is_skl_dsp_widget_type(p->sink)) |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1202 | continue; |
| 1203 | |
| 1204 | if (p->sink->priv) { |
| 1205 | dev_dbg(dai->dev, "set params for %s\n", |
| 1206 | p->sink->name); |
| 1207 | return p->sink->priv; |
| 1208 | } |
| 1209 | } |
| 1210 | } else { |
| 1211 | w = dai->capture_widget; |
Subhransu S. Prusty | f0900eb | 2015-10-22 23:22:36 +0530 | [diff] [blame] | 1212 | snd_soc_dapm_widget_for_each_source_path(w, p) { |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1213 | if (p->connect && p->source->power && |
Jeeja KP | a28f51d | 2015-10-27 09:22:44 +0900 | [diff] [blame] | 1214 | !is_skl_dsp_widget_type(p->source)) |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1215 | continue; |
| 1216 | |
| 1217 | if (p->source->priv) { |
| 1218 | dev_dbg(dai->dev, "set params for %s\n", |
| 1219 | p->source->name); |
| 1220 | return p->source->priv; |
| 1221 | } |
| 1222 | } |
| 1223 | } |
| 1224 | |
| 1225 | return NULL; |
| 1226 | } |
| 1227 | |
Dharageswari.R | 718a42b | 2016-02-05 12:19:06 +0530 | [diff] [blame] | 1228 | static struct skl_module_cfg *skl_get_mconfig_pb_cpr( |
| 1229 | struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w) |
| 1230 | { |
| 1231 | struct snd_soc_dapm_path *p; |
| 1232 | struct skl_module_cfg *mconfig = NULL; |
| 1233 | |
| 1234 | snd_soc_dapm_widget_for_each_source_path(w, p) { |
| 1235 | if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) { |
| 1236 | if (p->connect && |
| 1237 | (p->sink->id == snd_soc_dapm_aif_out) && |
| 1238 | p->source->priv) { |
| 1239 | mconfig = p->source->priv; |
| 1240 | return mconfig; |
| 1241 | } |
| 1242 | mconfig = skl_get_mconfig_pb_cpr(dai, p->source); |
| 1243 | if (mconfig) |
| 1244 | return mconfig; |
| 1245 | } |
| 1246 | } |
| 1247 | return mconfig; |
| 1248 | } |
| 1249 | |
| 1250 | static struct skl_module_cfg *skl_get_mconfig_cap_cpr( |
| 1251 | struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w) |
| 1252 | { |
| 1253 | struct snd_soc_dapm_path *p; |
| 1254 | struct skl_module_cfg *mconfig = NULL; |
| 1255 | |
| 1256 | snd_soc_dapm_widget_for_each_sink_path(w, p) { |
| 1257 | if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) { |
| 1258 | if (p->connect && |
| 1259 | (p->source->id == snd_soc_dapm_aif_in) && |
| 1260 | p->sink->priv) { |
| 1261 | mconfig = p->sink->priv; |
| 1262 | return mconfig; |
| 1263 | } |
| 1264 | mconfig = skl_get_mconfig_cap_cpr(dai, p->sink); |
| 1265 | if (mconfig) |
| 1266 | return mconfig; |
| 1267 | } |
| 1268 | } |
| 1269 | return mconfig; |
| 1270 | } |
| 1271 | |
| 1272 | struct skl_module_cfg * |
| 1273 | skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream) |
| 1274 | { |
| 1275 | struct snd_soc_dapm_widget *w; |
| 1276 | struct skl_module_cfg *mconfig; |
| 1277 | |
| 1278 | if (stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 1279 | w = dai->playback_widget; |
| 1280 | mconfig = skl_get_mconfig_pb_cpr(dai, w); |
| 1281 | } else { |
| 1282 | w = dai->capture_widget; |
| 1283 | mconfig = skl_get_mconfig_cap_cpr(dai, w); |
| 1284 | } |
| 1285 | return mconfig; |
| 1286 | } |
| 1287 | |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1288 | static u8 skl_tplg_be_link_type(int dev_type) |
| 1289 | { |
| 1290 | int ret; |
| 1291 | |
| 1292 | switch (dev_type) { |
| 1293 | case SKL_DEVICE_BT: |
| 1294 | ret = NHLT_LINK_SSP; |
| 1295 | break; |
| 1296 | |
| 1297 | case SKL_DEVICE_DMIC: |
| 1298 | ret = NHLT_LINK_DMIC; |
| 1299 | break; |
| 1300 | |
| 1301 | case SKL_DEVICE_I2S: |
| 1302 | ret = NHLT_LINK_SSP; |
| 1303 | break; |
| 1304 | |
| 1305 | case SKL_DEVICE_HDALINK: |
| 1306 | ret = NHLT_LINK_HDA; |
| 1307 | break; |
| 1308 | |
| 1309 | default: |
| 1310 | ret = NHLT_LINK_INVALID; |
| 1311 | break; |
| 1312 | } |
| 1313 | |
| 1314 | return ret; |
| 1315 | } |
| 1316 | |
| 1317 | /* |
| 1318 | * Fill the BE gateway parameters |
| 1319 | * The BE gateway expects a blob of parameters which are kept in the ACPI |
| 1320 | * NHLT blob, so query the blob for interface type (i2s/pdm) and instance. |
| 1321 | * The port can have multiple settings so pick based on the PCM |
| 1322 | * parameters |
| 1323 | */ |
| 1324 | static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai, |
| 1325 | struct skl_module_cfg *mconfig, |
| 1326 | struct skl_pipe_params *params) |
| 1327 | { |
| 1328 | struct skl_pipe *pipe = mconfig->pipe; |
| 1329 | struct nhlt_specific_cfg *cfg; |
| 1330 | struct skl *skl = get_skl_ctx(dai->dev); |
| 1331 | int link_type = skl_tplg_be_link_type(mconfig->dev_type); |
| 1332 | |
| 1333 | memcpy(pipe->p_params, params, sizeof(*params)); |
| 1334 | |
Jeeja KP | b30c275 | 2015-10-27 09:22:48 +0900 | [diff] [blame] | 1335 | if (link_type == NHLT_LINK_HDA) |
| 1336 | return 0; |
| 1337 | |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1338 | /* update the blob based on virtual bus_id*/ |
| 1339 | cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type, |
| 1340 | params->s_fmt, params->ch, |
| 1341 | params->s_freq, params->stream); |
| 1342 | if (cfg) { |
| 1343 | mconfig->formats_config.caps_size = cfg->size; |
Jeeja KP | bc03281 | 2015-10-22 23:22:35 +0530 | [diff] [blame] | 1344 | mconfig->formats_config.caps = (u32 *) &cfg->caps; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1345 | } else { |
| 1346 | dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n", |
| 1347 | mconfig->vbus_id, link_type, |
| 1348 | params->stream); |
| 1349 | dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n", |
| 1350 | params->ch, params->s_freq, params->s_fmt); |
| 1351 | return -EINVAL; |
| 1352 | } |
| 1353 | |
| 1354 | return 0; |
| 1355 | } |
| 1356 | |
| 1357 | static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai, |
| 1358 | struct snd_soc_dapm_widget *w, |
| 1359 | struct skl_pipe_params *params) |
| 1360 | { |
| 1361 | struct snd_soc_dapm_path *p; |
Subhransu S. Prusty | 4d8adccb | 2015-10-22 23:22:37 +0530 | [diff] [blame] | 1362 | int ret = -EIO; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1363 | |
Subhransu S. Prusty | f0900eb | 2015-10-22 23:22:36 +0530 | [diff] [blame] | 1364 | snd_soc_dapm_widget_for_each_source_path(w, p) { |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1365 | if (p->connect && is_skl_dsp_widget_type(p->source) && |
| 1366 | p->source->priv) { |
| 1367 | |
Jeeja KP | 9a03cb4 | 2015-10-27 09:22:54 +0900 | [diff] [blame] | 1368 | ret = skl_tplg_be_fill_pipe_params(dai, |
| 1369 | p->source->priv, params); |
| 1370 | if (ret < 0) |
| 1371 | return ret; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1372 | } else { |
Jeeja KP | 9a03cb4 | 2015-10-27 09:22:54 +0900 | [diff] [blame] | 1373 | ret = skl_tplg_be_set_src_pipe_params(dai, |
| 1374 | p->source, params); |
Subhransu S. Prusty | 4d8adccb | 2015-10-22 23:22:37 +0530 | [diff] [blame] | 1375 | if (ret < 0) |
| 1376 | return ret; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1377 | } |
| 1378 | } |
| 1379 | |
Subhransu S. Prusty | 4d8adccb | 2015-10-22 23:22:37 +0530 | [diff] [blame] | 1380 | return ret; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1381 | } |
| 1382 | |
| 1383 | static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai, |
| 1384 | struct snd_soc_dapm_widget *w, struct skl_pipe_params *params) |
| 1385 | { |
| 1386 | struct snd_soc_dapm_path *p = NULL; |
Subhransu S. Prusty | 4d8adccb | 2015-10-22 23:22:37 +0530 | [diff] [blame] | 1387 | int ret = -EIO; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1388 | |
Subhransu S. Prusty | f0900eb | 2015-10-22 23:22:36 +0530 | [diff] [blame] | 1389 | snd_soc_dapm_widget_for_each_sink_path(w, p) { |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1390 | if (p->connect && is_skl_dsp_widget_type(p->sink) && |
| 1391 | p->sink->priv) { |
| 1392 | |
Jeeja KP | 9a03cb4 | 2015-10-27 09:22:54 +0900 | [diff] [blame] | 1393 | ret = skl_tplg_be_fill_pipe_params(dai, |
| 1394 | p->sink->priv, params); |
| 1395 | if (ret < 0) |
| 1396 | return ret; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1397 | } else { |
Subhransu S. Prusty | 4d8adccb | 2015-10-22 23:22:37 +0530 | [diff] [blame] | 1398 | ret = skl_tplg_be_set_sink_pipe_params( |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1399 | dai, p->sink, params); |
Subhransu S. Prusty | 4d8adccb | 2015-10-22 23:22:37 +0530 | [diff] [blame] | 1400 | if (ret < 0) |
| 1401 | return ret; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1402 | } |
| 1403 | } |
| 1404 | |
Subhransu S. Prusty | 4d8adccb | 2015-10-22 23:22:37 +0530 | [diff] [blame] | 1405 | return ret; |
Vinod Koul | cfb0a87 | 2015-10-07 11:31:55 +0100 | [diff] [blame] | 1406 | } |
| 1407 | |
| 1408 | /* |
| 1409 | * BE hw_params can be a source parameters (capture) or sink parameters |
| 1410 | * (playback). Based on sink and source we need to either find the source |
| 1411 | * list or the sink list and set the pipeline parameters |
| 1412 | */ |
| 1413 | int skl_tplg_be_update_params(struct snd_soc_dai *dai, |
| 1414 | struct skl_pipe_params *params) |
| 1415 | { |
| 1416 | struct snd_soc_dapm_widget *w; |
| 1417 | |
| 1418 | if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) { |
| 1419 | w = dai->playback_widget; |
| 1420 | |
| 1421 | return skl_tplg_be_set_src_pipe_params(dai, w, params); |
| 1422 | |
| 1423 | } else { |
| 1424 | w = dai->capture_widget; |
| 1425 | |
| 1426 | return skl_tplg_be_set_sink_pipe_params(dai, w, params); |
| 1427 | } |
| 1428 | |
| 1429 | return 0; |
| 1430 | } |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1431 | |
| 1432 | static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = { |
| 1433 | {SKL_MIXER_EVENT, skl_tplg_mixer_event}, |
| 1434 | {SKL_VMIXER_EVENT, skl_tplg_vmixer_event}, |
| 1435 | {SKL_PGA_EVENT, skl_tplg_pga_event}, |
| 1436 | }; |
| 1437 | |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 1438 | static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = { |
| 1439 | {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get, |
| 1440 | skl_tplg_tlv_control_set}, |
| 1441 | }; |
| 1442 | |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1443 | /* |
| 1444 | * The topology binary passes the pin info for a module so initialize the pin |
| 1445 | * info passed into module instance |
| 1446 | */ |
Jeeja KP | 6abca1d | 2015-10-22 23:22:42 +0530 | [diff] [blame] | 1447 | static void skl_fill_module_pin_info(struct skl_dfw_module_pin *dfw_pin, |
| 1448 | struct skl_module_pin *m_pin, |
| 1449 | bool is_dynamic, int max_pin) |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1450 | { |
| 1451 | int i; |
| 1452 | |
| 1453 | for (i = 0; i < max_pin; i++) { |
Jeeja KP | 6abca1d | 2015-10-22 23:22:42 +0530 | [diff] [blame] | 1454 | m_pin[i].id.module_id = dfw_pin[i].module_id; |
| 1455 | m_pin[i].id.instance_id = dfw_pin[i].instance_id; |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1456 | m_pin[i].in_use = false; |
Jeeja KP | 6abca1d | 2015-10-22 23:22:42 +0530 | [diff] [blame] | 1457 | m_pin[i].is_dynamic = is_dynamic; |
Jeeja KP | 4f74570 | 2015-10-27 09:22:49 +0900 | [diff] [blame] | 1458 | m_pin[i].pin_state = SKL_PIN_UNBIND; |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1459 | } |
| 1460 | } |
| 1461 | |
| 1462 | /* |
| 1463 | * Add pipeline from topology binary into driver pipeline list |
| 1464 | * |
| 1465 | * If already added we return that instance |
| 1466 | * Otherwise we create a new instance and add into driver list |
| 1467 | */ |
| 1468 | static struct skl_pipe *skl_tplg_add_pipe(struct device *dev, |
| 1469 | struct skl *skl, struct skl_dfw_pipe *dfw_pipe) |
| 1470 | { |
| 1471 | struct skl_pipeline *ppl; |
| 1472 | struct skl_pipe *pipe; |
| 1473 | struct skl_pipe_params *params; |
| 1474 | |
| 1475 | list_for_each_entry(ppl, &skl->ppl_list, node) { |
| 1476 | if (ppl->pipe->ppl_id == dfw_pipe->pipe_id) |
| 1477 | return ppl->pipe; |
| 1478 | } |
| 1479 | |
| 1480 | ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL); |
| 1481 | if (!ppl) |
| 1482 | return NULL; |
| 1483 | |
| 1484 | pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL); |
| 1485 | if (!pipe) |
| 1486 | return NULL; |
| 1487 | |
| 1488 | params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL); |
| 1489 | if (!params) |
| 1490 | return NULL; |
| 1491 | |
| 1492 | pipe->ppl_id = dfw_pipe->pipe_id; |
| 1493 | pipe->memory_pages = dfw_pipe->memory_pages; |
| 1494 | pipe->pipe_priority = dfw_pipe->pipe_priority; |
| 1495 | pipe->conn_type = dfw_pipe->conn_type; |
| 1496 | pipe->state = SKL_PIPE_INVALID; |
| 1497 | pipe->p_params = params; |
| 1498 | INIT_LIST_HEAD(&pipe->w_list); |
| 1499 | |
| 1500 | ppl->pipe = pipe; |
| 1501 | list_add(&ppl->node, &skl->ppl_list); |
| 1502 | |
| 1503 | return ppl->pipe; |
| 1504 | } |
| 1505 | |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 1506 | static void skl_tplg_fill_fmt(struct skl_module_fmt *dst_fmt, |
| 1507 | struct skl_dfw_module_fmt *src_fmt, |
| 1508 | int pins) |
| 1509 | { |
| 1510 | int i; |
| 1511 | |
| 1512 | for (i = 0; i < pins; i++) { |
| 1513 | dst_fmt[i].channels = src_fmt[i].channels; |
| 1514 | dst_fmt[i].s_freq = src_fmt[i].freq; |
| 1515 | dst_fmt[i].bit_depth = src_fmt[i].bit_depth; |
| 1516 | dst_fmt[i].valid_bit_depth = src_fmt[i].valid_bit_depth; |
| 1517 | dst_fmt[i].ch_cfg = src_fmt[i].ch_cfg; |
| 1518 | dst_fmt[i].ch_map = src_fmt[i].ch_map; |
| 1519 | dst_fmt[i].interleaving_style = src_fmt[i].interleaving_style; |
| 1520 | dst_fmt[i].sample_type = src_fmt[i].sample_type; |
| 1521 | } |
| 1522 | } |
| 1523 | |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1524 | /* |
| 1525 | * Topology core widget load callback |
| 1526 | * |
| 1527 | * This is used to save the private data for each widget which gives |
| 1528 | * information to the driver about module and pipeline parameters which DSP |
| 1529 | * FW expects like ids, resource values, formats etc |
| 1530 | */ |
| 1531 | static int skl_tplg_widget_load(struct snd_soc_component *cmpnt, |
Jeeja KP | b663a8c | 2015-10-07 11:31:57 +0100 | [diff] [blame] | 1532 | struct snd_soc_dapm_widget *w, |
| 1533 | struct snd_soc_tplg_dapm_widget *tplg_w) |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1534 | { |
| 1535 | int ret; |
| 1536 | struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt); |
| 1537 | struct skl *skl = ebus_to_skl(ebus); |
| 1538 | struct hdac_bus *bus = ebus_to_hbus(ebus); |
| 1539 | struct skl_module_cfg *mconfig; |
| 1540 | struct skl_pipe *pipe; |
Jeeja KP | b663a8c | 2015-10-07 11:31:57 +0100 | [diff] [blame] | 1541 | struct skl_dfw_module *dfw_config = |
| 1542 | (struct skl_dfw_module *)tplg_w->priv.data; |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1543 | |
| 1544 | if (!tplg_w->priv.size) |
| 1545 | goto bind_event; |
| 1546 | |
| 1547 | mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL); |
| 1548 | |
| 1549 | if (!mconfig) |
| 1550 | return -ENOMEM; |
| 1551 | |
| 1552 | w->priv = mconfig; |
| 1553 | mconfig->id.module_id = dfw_config->module_id; |
| 1554 | mconfig->id.instance_id = dfw_config->instance_id; |
| 1555 | mconfig->mcps = dfw_config->max_mcps; |
| 1556 | mconfig->ibs = dfw_config->ibs; |
| 1557 | mconfig->obs = dfw_config->obs; |
| 1558 | mconfig->core_id = dfw_config->core_id; |
| 1559 | mconfig->max_in_queue = dfw_config->max_in_queue; |
| 1560 | mconfig->max_out_queue = dfw_config->max_out_queue; |
| 1561 | mconfig->is_loadable = dfw_config->is_loadable; |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 1562 | skl_tplg_fill_fmt(mconfig->in_fmt, dfw_config->in_fmt, |
| 1563 | MODULE_MAX_IN_PINS); |
| 1564 | skl_tplg_fill_fmt(mconfig->out_fmt, dfw_config->out_fmt, |
| 1565 | MODULE_MAX_OUT_PINS); |
| 1566 | |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1567 | mconfig->params_fixup = dfw_config->params_fixup; |
| 1568 | mconfig->converter = dfw_config->converter; |
| 1569 | mconfig->m_type = dfw_config->module_type; |
| 1570 | mconfig->vbus_id = dfw_config->vbus_id; |
Jeeja KP | b18c458 | 2015-12-03 23:29:51 +0530 | [diff] [blame] | 1571 | mconfig->mem_pages = dfw_config->mem_pages; |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1572 | |
| 1573 | pipe = skl_tplg_add_pipe(bus->dev, skl, &dfw_config->pipe); |
| 1574 | if (pipe) |
| 1575 | mconfig->pipe = pipe; |
| 1576 | |
| 1577 | mconfig->dev_type = dfw_config->dev_type; |
| 1578 | mconfig->hw_conn_type = dfw_config->hw_conn_type; |
| 1579 | mconfig->time_slot = dfw_config->time_slot; |
| 1580 | mconfig->formats_config.caps_size = dfw_config->caps.caps_size; |
| 1581 | |
Hardik T Shah | 65aecfa | 2015-10-27 09:22:57 +0900 | [diff] [blame] | 1582 | if (dfw_config->is_loadable) |
| 1583 | memcpy(mconfig->guid, dfw_config->uuid, |
| 1584 | ARRAY_SIZE(dfw_config->uuid)); |
| 1585 | |
Hardik T Shah | 4cd9899 | 2015-10-27 09:22:55 +0900 | [diff] [blame] | 1586 | mconfig->m_in_pin = devm_kzalloc(bus->dev, (mconfig->max_in_queue) * |
| 1587 | sizeof(*mconfig->m_in_pin), |
| 1588 | GFP_KERNEL); |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1589 | if (!mconfig->m_in_pin) |
| 1590 | return -ENOMEM; |
| 1591 | |
Jeeja KP | 6abca1d | 2015-10-22 23:22:42 +0530 | [diff] [blame] | 1592 | mconfig->m_out_pin = devm_kzalloc(bus->dev, (mconfig->max_out_queue) * |
| 1593 | sizeof(*mconfig->m_out_pin), |
| 1594 | GFP_KERNEL); |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1595 | if (!mconfig->m_out_pin) |
| 1596 | return -ENOMEM; |
| 1597 | |
Jeeja KP | 6abca1d | 2015-10-22 23:22:42 +0530 | [diff] [blame] | 1598 | skl_fill_module_pin_info(dfw_config->in_pin, mconfig->m_in_pin, |
| 1599 | dfw_config->is_dynamic_in_pin, |
| 1600 | mconfig->max_in_queue); |
| 1601 | |
| 1602 | skl_fill_module_pin_info(dfw_config->out_pin, mconfig->m_out_pin, |
| 1603 | dfw_config->is_dynamic_out_pin, |
| 1604 | mconfig->max_out_queue); |
| 1605 | |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1606 | |
| 1607 | if (mconfig->formats_config.caps_size == 0) |
| 1608 | goto bind_event; |
| 1609 | |
| 1610 | mconfig->formats_config.caps = (u32 *)devm_kzalloc(bus->dev, |
Jeeja KP | b663a8c | 2015-10-07 11:31:57 +0100 | [diff] [blame] | 1611 | mconfig->formats_config.caps_size, GFP_KERNEL); |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1612 | |
| 1613 | if (mconfig->formats_config.caps == NULL) |
| 1614 | return -ENOMEM; |
| 1615 | |
| 1616 | memcpy(mconfig->formats_config.caps, dfw_config->caps.caps, |
Jeeja KP | abb7400 | 2015-11-28 15:01:49 +0530 | [diff] [blame] | 1617 | dfw_config->caps.caps_size); |
| 1618 | mconfig->formats_config.param_id = dfw_config->caps.param_id; |
| 1619 | mconfig->formats_config.set_params = dfw_config->caps.set_params; |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1620 | |
| 1621 | bind_event: |
| 1622 | if (tplg_w->event_type == 0) { |
Vinod Koul | 3373f71 | 2015-10-07 16:39:38 +0100 | [diff] [blame] | 1623 | dev_dbg(bus->dev, "ASoC: No event handler required\n"); |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1624 | return 0; |
| 1625 | } |
| 1626 | |
| 1627 | ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops, |
Jeeja KP | b663a8c | 2015-10-07 11:31:57 +0100 | [diff] [blame] | 1628 | ARRAY_SIZE(skl_tplg_widget_ops), |
| 1629 | tplg_w->event_type); |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1630 | |
| 1631 | if (ret) { |
| 1632 | dev_err(bus->dev, "%s: No matching event handlers found for %d\n", |
| 1633 | __func__, tplg_w->event_type); |
| 1634 | return -EINVAL; |
| 1635 | } |
| 1636 | |
| 1637 | return 0; |
| 1638 | } |
| 1639 | |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 1640 | static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be, |
| 1641 | struct snd_soc_tplg_bytes_control *bc) |
| 1642 | { |
| 1643 | struct skl_algo_data *ac; |
| 1644 | struct skl_dfw_algo_data *dfw_ac = |
| 1645 | (struct skl_dfw_algo_data *)bc->priv.data; |
| 1646 | |
| 1647 | ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL); |
| 1648 | if (!ac) |
| 1649 | return -ENOMEM; |
| 1650 | |
| 1651 | /* Fill private data */ |
| 1652 | ac->max = dfw_ac->max; |
| 1653 | ac->param_id = dfw_ac->param_id; |
| 1654 | ac->set_params = dfw_ac->set_params; |
| 1655 | |
| 1656 | if (ac->max) { |
| 1657 | ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL); |
| 1658 | if (!ac->params) |
| 1659 | return -ENOMEM; |
| 1660 | |
Alan Cox | edd7ea2 | 2016-02-22 09:37:27 +0530 | [diff] [blame] | 1661 | memcpy(ac->params, dfw_ac->params, ac->max); |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 1662 | } |
| 1663 | |
| 1664 | be->dobj.private = ac; |
| 1665 | return 0; |
| 1666 | } |
| 1667 | |
| 1668 | static int skl_tplg_control_load(struct snd_soc_component *cmpnt, |
| 1669 | struct snd_kcontrol_new *kctl, |
| 1670 | struct snd_soc_tplg_ctl_hdr *hdr) |
| 1671 | { |
| 1672 | struct soc_bytes_ext *sb; |
| 1673 | struct snd_soc_tplg_bytes_control *tplg_bc; |
| 1674 | struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt); |
| 1675 | struct hdac_bus *bus = ebus_to_hbus(ebus); |
| 1676 | |
| 1677 | switch (hdr->ops.info) { |
| 1678 | case SND_SOC_TPLG_CTL_BYTES: |
| 1679 | tplg_bc = container_of(hdr, |
| 1680 | struct snd_soc_tplg_bytes_control, hdr); |
| 1681 | if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) { |
| 1682 | sb = (struct soc_bytes_ext *)kctl->private_value; |
| 1683 | if (tplg_bc->priv.size) |
| 1684 | return skl_init_algo_data( |
| 1685 | bus->dev, sb, tplg_bc); |
| 1686 | } |
| 1687 | break; |
| 1688 | |
| 1689 | default: |
| 1690 | dev_warn(bus->dev, "Control load not supported %d:%d:%d\n", |
| 1691 | hdr->ops.get, hdr->ops.put, hdr->ops.info); |
| 1692 | break; |
| 1693 | } |
| 1694 | |
| 1695 | return 0; |
| 1696 | } |
| 1697 | |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1698 | static struct snd_soc_tplg_ops skl_tplg_ops = { |
| 1699 | .widget_load = skl_tplg_widget_load, |
Jeeja KP | 140adfb | 2015-11-28 15:01:50 +0530 | [diff] [blame] | 1700 | .control_load = skl_tplg_control_load, |
| 1701 | .bytes_ext_ops = skl_tlv_ops, |
| 1702 | .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops), |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1703 | }; |
| 1704 | |
| 1705 | /* This will be read from topology manifest, currently defined here */ |
| 1706 | #define SKL_MAX_MCPS 30000000 |
| 1707 | #define SKL_FW_MAX_MEM 1000000 |
| 1708 | |
| 1709 | /* |
| 1710 | * SKL topology init routine |
| 1711 | */ |
| 1712 | int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus) |
| 1713 | { |
| 1714 | int ret; |
| 1715 | const struct firmware *fw; |
| 1716 | struct hdac_bus *bus = ebus_to_hbus(ebus); |
| 1717 | struct skl *skl = ebus_to_skl(ebus); |
| 1718 | |
Vinod Koul | 4b235c4 | 2016-02-19 11:42:34 +0530 | [diff] [blame] | 1719 | ret = request_firmware(&fw, skl->tplg_name, bus->dev); |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1720 | if (ret < 0) { |
Jeeja KP | b663a8c | 2015-10-07 11:31:57 +0100 | [diff] [blame] | 1721 | dev_err(bus->dev, "tplg fw %s load failed with %d\n", |
Vinod Koul | 4b235c4 | 2016-02-19 11:42:34 +0530 | [diff] [blame] | 1722 | skl->tplg_name, ret); |
| 1723 | ret = request_firmware(&fw, "dfw_sst.bin", bus->dev); |
| 1724 | if (ret < 0) { |
| 1725 | dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n", |
| 1726 | "dfw_sst.bin", ret); |
| 1727 | return ret; |
| 1728 | } |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1729 | } |
| 1730 | |
| 1731 | /* |
| 1732 | * The complete tplg for SKL is loaded as index 0, we don't use |
| 1733 | * any other index |
| 1734 | */ |
Jeeja KP | b663a8c | 2015-10-07 11:31:57 +0100 | [diff] [blame] | 1735 | ret = snd_soc_tplg_component_load(&platform->component, |
| 1736 | &skl_tplg_ops, fw, 0); |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1737 | if (ret < 0) { |
| 1738 | dev_err(bus->dev, "tplg component load failed%d\n", ret); |
Sudip Mukherjee | c14a82c | 2016-01-21 17:27:59 +0530 | [diff] [blame] | 1739 | release_firmware(fw); |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1740 | return -EINVAL; |
| 1741 | } |
| 1742 | |
| 1743 | skl->resource.max_mcps = SKL_MAX_MCPS; |
| 1744 | skl->resource.max_mem = SKL_FW_MAX_MEM; |
| 1745 | |
Vinod Koul | d801836 | 2016-01-05 17:16:04 +0530 | [diff] [blame] | 1746 | skl->tplg = fw; |
| 1747 | |
Vinod Koul | 3af3670 | 2015-10-07 11:31:56 +0100 | [diff] [blame] | 1748 | return 0; |
| 1749 | } |