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Tomi Valkeinen80c39712009-11-12 11:41:42 +02001/*
2 * linux/drivers/video/omap2/dss/dispc.c
3 *
4 * Copyright (C) 2009 Nokia Corporation
5 * Author: Tomi Valkeinen <tomi.valkeinen@nokia.com>
6 *
7 * Some code and ideas taken from drivers/video/omap/ driver
8 * by Imre Deak.
9 *
10 * This program is free software; you can redistribute it and/or modify it
11 * under the terms of the GNU General Public License version 2 as published by
12 * the Free Software Foundation.
13 *
14 * This program is distributed in the hope that it will be useful, but WITHOUT
15 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
16 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
17 * more details.
18 *
19 * You should have received a copy of the GNU General Public License along with
20 * this program. If not, see <http://www.gnu.org/licenses/>.
21 */
22
23#define DSS_SUBSYS_NAME "DISPC"
24
25#include <linux/kernel.h>
26#include <linux/dma-mapping.h>
27#include <linux/vmalloc.h>
Paul Gortmakera8a35932011-07-10 13:20:26 -040028#include <linux/export.h>
Tomi Valkeinen80c39712009-11-12 11:41:42 +020029#include <linux/clk.h>
30#include <linux/io.h>
31#include <linux/jiffies.h>
32#include <linux/seq_file.h>
33#include <linux/delay.h>
34#include <linux/workqueue.h>
Tomi Valkeinenab83b142010-06-09 15:31:01 +030035#include <linux/hardirq.h>
archit tanejaaffe3602011-02-23 08:41:03 +000036#include <linux/interrupt.h>
Tomi Valkeinen24e62892011-05-23 11:51:18 +030037#include <linux/platform_device.h>
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +030038#include <linux/pm_runtime.h>
Tomi Valkeinen80c39712009-11-12 11:41:42 +020039
Tomi Valkeinen80c39712009-11-12 11:41:42 +020040#include <plat/clock.h>
41
Tomi Valkeinena0b38cc2011-05-11 14:05:07 +030042#include <video/omapdss.h>
Tomi Valkeinen80c39712009-11-12 11:41:42 +020043
44#include "dss.h"
Archit Tanejaa0acb552010-09-15 19:20:00 +053045#include "dss_features.h"
Archit Taneja9b372c22011-05-06 11:45:49 +053046#include "dispc.h"
Tomi Valkeinen80c39712009-11-12 11:41:42 +020047
48/* DISPC */
Sumit Semwal8613b002010-12-02 11:27:09 +000049#define DISPC_SZ_REGS SZ_4K
Tomi Valkeinen80c39712009-11-12 11:41:42 +020050
Tomi Valkeinen80c39712009-11-12 11:41:42 +020051#define DISPC_IRQ_MASK_ERROR (DISPC_IRQ_GFX_FIFO_UNDERFLOW | \
52 DISPC_IRQ_OCP_ERR | \
53 DISPC_IRQ_VID1_FIFO_UNDERFLOW | \
54 DISPC_IRQ_VID2_FIFO_UNDERFLOW | \
55 DISPC_IRQ_SYNC_LOST | \
56 DISPC_IRQ_SYNC_LOST_DIGIT)
57
58#define DISPC_MAX_NR_ISRS 8
59
60struct omap_dispc_isr_data {
61 omap_dispc_isr_t isr;
62 void *arg;
63 u32 mask;
64};
65
Tomi Valkeinen5ed8cf52011-06-21 09:35:36 +030066enum omap_burst_size {
67 BURST_SIZE_X2 = 0,
68 BURST_SIZE_X4 = 1,
69 BURST_SIZE_X8 = 2,
70};
71
Tomi Valkeinen80c39712009-11-12 11:41:42 +020072#define REG_GET(idx, start, end) \
73 FLD_GET(dispc_read_reg(idx), start, end)
74
75#define REG_FLD_MOD(idx, val, start, end) \
76 dispc_write_reg(idx, FLD_MOD(dispc_read_reg(idx), val, start, end))
77
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +020078struct dispc_irq_stats {
79 unsigned long last_reset;
80 unsigned irq_count;
81 unsigned irqs[32];
82};
83
Tomi Valkeinen80c39712009-11-12 11:41:42 +020084static struct {
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +000085 struct platform_device *pdev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +020086 void __iomem *base;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +030087
88 int ctx_loss_cnt;
89
archit tanejaaffe3602011-02-23 08:41:03 +000090 int irq;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +030091 struct clk *dss_clk;
Tomi Valkeinen80c39712009-11-12 11:41:42 +020092
Archit Tanejae13a1382011-08-05 19:06:04 +053093 u32 fifo_size[MAX_DSS_OVERLAYS];
Tomi Valkeinen80c39712009-11-12 11:41:42 +020094
95 spinlock_t irq_lock;
96 u32 irq_error_mask;
97 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
98 u32 error_irqs;
99 struct work_struct error_work;
100
Tomi Valkeinen49ea86f2011-06-01 15:54:06 +0300101 bool ctx_valid;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200102 u32 ctx[DISPC_SZ_REGS / sizeof(u32)];
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +0200103
104#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
105 spinlock_t irq_stats_lock;
106 struct dispc_irq_stats irq_stats;
107#endif
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200108} dispc;
109
Amber Jain0d66cbb2011-05-19 19:47:54 +0530110enum omap_color_component {
111 /* used for all color formats for OMAP3 and earlier
112 * and for RGB and Y color component on OMAP4
113 */
114 DISPC_COLOR_COMPONENT_RGB_Y = 1 << 0,
115 /* used for UV component for
116 * OMAP_DSS_COLOR_YUV2, OMAP_DSS_COLOR_UYVY, OMAP_DSS_COLOR_NV12
117 * color formats on OMAP4
118 */
119 DISPC_COLOR_COMPONENT_UV = 1 << 1,
120};
121
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200122static void _omap_dispc_set_irqs(void);
123
Archit Taneja55978cc2011-05-06 11:45:51 +0530124static inline void dispc_write_reg(const u16 idx, u32 val)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200125{
Archit Taneja55978cc2011-05-06 11:45:51 +0530126 __raw_writel(val, dispc.base + idx);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200127}
128
Archit Taneja55978cc2011-05-06 11:45:51 +0530129static inline u32 dispc_read_reg(const u16 idx)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200130{
Archit Taneja55978cc2011-05-06 11:45:51 +0530131 return __raw_readl(dispc.base + idx);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200132}
133
134#define SR(reg) \
Archit Taneja55978cc2011-05-06 11:45:51 +0530135 dispc.ctx[DISPC_##reg / sizeof(u32)] = dispc_read_reg(DISPC_##reg)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200136#define RR(reg) \
Archit Taneja55978cc2011-05-06 11:45:51 +0530137 dispc_write_reg(DISPC_##reg, dispc.ctx[DISPC_##reg / sizeof(u32)])
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200138
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300139static void dispc_save_context(void)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200140{
Archit Tanejac6104b82011-08-05 19:06:02 +0530141 int i, j;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200142
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300143 DSSDBG("dispc_save_context\n");
144
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200145 SR(IRQENABLE);
146 SR(CONTROL);
147 SR(CONFIG);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200148 SR(LINE_NUMBER);
Archit Taneja11354dd2011-09-26 11:47:29 +0530149 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
150 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
Tomi Valkeinen332e9d72011-05-27 14:22:16 +0300151 SR(GLOBAL_ALPHA);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000152 if (dss_has_feature(FEAT_MGR_LCD2)) {
153 SR(CONTROL2);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000154 SR(CONFIG2);
155 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200156
Archit Tanejac6104b82011-08-05 19:06:02 +0530157 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
158 SR(DEFAULT_COLOR(i));
159 SR(TRANS_COLOR(i));
160 SR(SIZE_MGR(i));
161 if (i == OMAP_DSS_CHANNEL_DIGIT)
162 continue;
163 SR(TIMING_H(i));
164 SR(TIMING_V(i));
165 SR(POL_FREQ(i));
166 SR(DIVISORo(i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200167
Archit Tanejac6104b82011-08-05 19:06:02 +0530168 SR(DATA_CYCLE1(i));
169 SR(DATA_CYCLE2(i));
170 SR(DATA_CYCLE3(i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200171
Tomi Valkeinen332e9d72011-05-27 14:22:16 +0300172 if (dss_has_feature(FEAT_CPR)) {
Archit Tanejac6104b82011-08-05 19:06:02 +0530173 SR(CPR_COEF_R(i));
174 SR(CPR_COEF_G(i));
175 SR(CPR_COEF_B(i));
176 }
177 }
178
179 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
180 SR(OVL_BA0(i));
181 SR(OVL_BA1(i));
182 SR(OVL_POSITION(i));
183 SR(OVL_SIZE(i));
184 SR(OVL_ATTRIBUTES(i));
185 SR(OVL_FIFO_THRESHOLD(i));
186 SR(OVL_ROW_INC(i));
187 SR(OVL_PIXEL_INC(i));
188 if (dss_has_feature(FEAT_PRELOAD))
189 SR(OVL_PRELOAD(i));
190 if (i == OMAP_DSS_GFX) {
191 SR(OVL_WINDOW_SKIP(i));
192 SR(OVL_TABLE_BA(i));
193 continue;
194 }
195 SR(OVL_FIR(i));
196 SR(OVL_PICTURE_SIZE(i));
197 SR(OVL_ACCU0(i));
198 SR(OVL_ACCU1(i));
199
200 for (j = 0; j < 8; j++)
201 SR(OVL_FIR_COEF_H(i, j));
202
203 for (j = 0; j < 8; j++)
204 SR(OVL_FIR_COEF_HV(i, j));
205
206 for (j = 0; j < 5; j++)
207 SR(OVL_CONV_COEF(i, j));
208
209 if (dss_has_feature(FEAT_FIR_COEF_V)) {
210 for (j = 0; j < 8; j++)
211 SR(OVL_FIR_COEF_V(i, j));
Tomi Valkeinen332e9d72011-05-27 14:22:16 +0300212 }
Sumit Semwal2a205f32010-12-02 11:27:12 +0000213
Archit Tanejac6104b82011-08-05 19:06:02 +0530214 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
215 SR(OVL_BA0_UV(i));
216 SR(OVL_BA1_UV(i));
217 SR(OVL_FIR2(i));
218 SR(OVL_ACCU2_0(i));
219 SR(OVL_ACCU2_1(i));
220
221 for (j = 0; j < 8; j++)
222 SR(OVL_FIR_COEF_H2(i, j));
223
224 for (j = 0; j < 8; j++)
225 SR(OVL_FIR_COEF_HV2(i, j));
226
227 for (j = 0; j < 8; j++)
228 SR(OVL_FIR_COEF_V2(i, j));
229 }
230 if (dss_has_feature(FEAT_ATTR2))
231 SR(OVL_ATTRIBUTES2(i));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000232 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200233
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600234 if (dss_has_feature(FEAT_CORE_CLK_DIV))
235 SR(DIVISOR);
Tomi Valkeinen49ea86f2011-06-01 15:54:06 +0300236
Tomi Valkeinen00928ea2012-02-20 11:50:06 +0200237 dispc.ctx_loss_cnt = dss_get_ctx_loss_count(&dispc.pdev->dev);
Tomi Valkeinen49ea86f2011-06-01 15:54:06 +0300238 dispc.ctx_valid = true;
239
240 DSSDBG("context saved, ctx_loss_count %d\n", dispc.ctx_loss_cnt);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200241}
242
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300243static void dispc_restore_context(void)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200244{
Archit Tanejac6104b82011-08-05 19:06:02 +0530245 int i, j, ctx;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300246
247 DSSDBG("dispc_restore_context\n");
248
Tomi Valkeinen49ea86f2011-06-01 15:54:06 +0300249 if (!dispc.ctx_valid)
250 return;
251
Tomi Valkeinen00928ea2012-02-20 11:50:06 +0200252 ctx = dss_get_ctx_loss_count(&dispc.pdev->dev);
Tomi Valkeinen49ea86f2011-06-01 15:54:06 +0300253
254 if (ctx >= 0 && ctx == dispc.ctx_loss_cnt)
255 return;
256
257 DSSDBG("ctx_loss_count: saved %d, current %d\n",
258 dispc.ctx_loss_cnt, ctx);
259
Ville Syrjälä75c7d592010-03-05 01:13:11 +0200260 /*RR(IRQENABLE);*/
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200261 /*RR(CONTROL);*/
262 RR(CONFIG);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200263 RR(LINE_NUMBER);
Archit Taneja11354dd2011-09-26 11:47:29 +0530264 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
265 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
Tomi Valkeinen332e9d72011-05-27 14:22:16 +0300266 RR(GLOBAL_ALPHA);
Archit Tanejac6104b82011-08-05 19:06:02 +0530267 if (dss_has_feature(FEAT_MGR_LCD2))
Sumit Semwal2a205f32010-12-02 11:27:12 +0000268 RR(CONFIG2);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200269
Archit Tanejac6104b82011-08-05 19:06:02 +0530270 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
271 RR(DEFAULT_COLOR(i));
272 RR(TRANS_COLOR(i));
273 RR(SIZE_MGR(i));
274 if (i == OMAP_DSS_CHANNEL_DIGIT)
275 continue;
276 RR(TIMING_H(i));
277 RR(TIMING_V(i));
278 RR(POL_FREQ(i));
279 RR(DIVISORo(i));
Archit Taneja9b372c22011-05-06 11:45:49 +0530280
Archit Tanejac6104b82011-08-05 19:06:02 +0530281 RR(DATA_CYCLE1(i));
282 RR(DATA_CYCLE2(i));
283 RR(DATA_CYCLE3(i));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000284
Tomi Valkeinen332e9d72011-05-27 14:22:16 +0300285 if (dss_has_feature(FEAT_CPR)) {
Archit Tanejac6104b82011-08-05 19:06:02 +0530286 RR(CPR_COEF_R(i));
287 RR(CPR_COEF_G(i));
288 RR(CPR_COEF_B(i));
Tomi Valkeinen332e9d72011-05-27 14:22:16 +0300289 }
Sumit Semwal2a205f32010-12-02 11:27:12 +0000290 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200291
Archit Tanejac6104b82011-08-05 19:06:02 +0530292 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
293 RR(OVL_BA0(i));
294 RR(OVL_BA1(i));
295 RR(OVL_POSITION(i));
296 RR(OVL_SIZE(i));
297 RR(OVL_ATTRIBUTES(i));
298 RR(OVL_FIFO_THRESHOLD(i));
299 RR(OVL_ROW_INC(i));
300 RR(OVL_PIXEL_INC(i));
301 if (dss_has_feature(FEAT_PRELOAD))
302 RR(OVL_PRELOAD(i));
303 if (i == OMAP_DSS_GFX) {
304 RR(OVL_WINDOW_SKIP(i));
305 RR(OVL_TABLE_BA(i));
306 continue;
307 }
308 RR(OVL_FIR(i));
309 RR(OVL_PICTURE_SIZE(i));
310 RR(OVL_ACCU0(i));
311 RR(OVL_ACCU1(i));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200312
Archit Tanejac6104b82011-08-05 19:06:02 +0530313 for (j = 0; j < 8; j++)
314 RR(OVL_FIR_COEF_H(i, j));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200315
Archit Tanejac6104b82011-08-05 19:06:02 +0530316 for (j = 0; j < 8; j++)
317 RR(OVL_FIR_COEF_HV(i, j));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200318
Archit Tanejac6104b82011-08-05 19:06:02 +0530319 for (j = 0; j < 5; j++)
320 RR(OVL_CONV_COEF(i, j));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200321
Archit Tanejac6104b82011-08-05 19:06:02 +0530322 if (dss_has_feature(FEAT_FIR_COEF_V)) {
323 for (j = 0; j < 8; j++)
324 RR(OVL_FIR_COEF_V(i, j));
325 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200326
Archit Tanejac6104b82011-08-05 19:06:02 +0530327 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
328 RR(OVL_BA0_UV(i));
329 RR(OVL_BA1_UV(i));
330 RR(OVL_FIR2(i));
331 RR(OVL_ACCU2_0(i));
332 RR(OVL_ACCU2_1(i));
333
334 for (j = 0; j < 8; j++)
335 RR(OVL_FIR_COEF_H2(i, j));
336
337 for (j = 0; j < 8; j++)
338 RR(OVL_FIR_COEF_HV2(i, j));
339
340 for (j = 0; j < 8; j++)
341 RR(OVL_FIR_COEF_V2(i, j));
342 }
343 if (dss_has_feature(FEAT_ATTR2))
344 RR(OVL_ATTRIBUTES2(i));
Tomi Valkeinen332e9d72011-05-27 14:22:16 +0300345 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200346
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -0600347 if (dss_has_feature(FEAT_CORE_CLK_DIV))
348 RR(DIVISOR);
349
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200350 /* enable last, because LCD & DIGIT enable are here */
351 RR(CONTROL);
Sumit Semwal2a205f32010-12-02 11:27:12 +0000352 if (dss_has_feature(FEAT_MGR_LCD2))
353 RR(CONTROL2);
Ville Syrjälä75c7d592010-03-05 01:13:11 +0200354 /* clear spurious SYNC_LOST_DIGIT interrupts */
355 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
356
357 /*
358 * enable last so IRQs won't trigger before
359 * the context is fully restored
360 */
361 RR(IRQENABLE);
Tomi Valkeinen49ea86f2011-06-01 15:54:06 +0300362
363 DSSDBG("context restored\n");
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200364}
365
366#undef SR
367#undef RR
368
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300369int dispc_runtime_get(void)
370{
371 int r;
372
373 DSSDBG("dispc_runtime_get\n");
374
375 r = pm_runtime_get_sync(&dispc.pdev->dev);
376 WARN_ON(r < 0);
377 return r < 0 ? r : 0;
378}
379
380void dispc_runtime_put(void)
381{
382 int r;
383
384 DSSDBG("dispc_runtime_put\n");
385
Tomi Valkeinen0eaf9f52012-01-23 13:23:08 +0200386 r = pm_runtime_put_sync(&dispc.pdev->dev);
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300387 WARN_ON(r < 0);
388}
389
Archit Tanejadac57a02011-09-08 12:30:19 +0530390static inline bool dispc_mgr_is_lcd(enum omap_channel channel)
391{
392 if (channel == OMAP_DSS_CHANNEL_LCD ||
393 channel == OMAP_DSS_CHANNEL_LCD2)
394 return true;
395 else
396 return false;
397}
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +0300398
Tomi Valkeinen3dcec4d2011-11-07 15:50:09 +0200399u32 dispc_mgr_get_vsync_irq(enum omap_channel channel)
400{
401 switch (channel) {
402 case OMAP_DSS_CHANNEL_LCD:
403 return DISPC_IRQ_VSYNC;
404 case OMAP_DSS_CHANNEL_LCD2:
405 return DISPC_IRQ_VSYNC2;
406 case OMAP_DSS_CHANNEL_DIGIT:
407 return DISPC_IRQ_EVSYNC_ODD | DISPC_IRQ_EVSYNC_EVEN;
408 default:
409 BUG();
410 }
411}
412
Tomi Valkeinen7d1365c2011-11-18 15:39:52 +0200413u32 dispc_mgr_get_framedone_irq(enum omap_channel channel)
414{
415 switch (channel) {
416 case OMAP_DSS_CHANNEL_LCD:
417 return DISPC_IRQ_FRAMEDONE;
418 case OMAP_DSS_CHANNEL_LCD2:
419 return DISPC_IRQ_FRAMEDONE2;
420 case OMAP_DSS_CHANNEL_DIGIT:
421 return 0;
422 default:
423 BUG();
424 }
425}
426
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +0300427bool dispc_mgr_go_busy(enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200428{
429 int bit;
430
Archit Tanejadac57a02011-09-08 12:30:19 +0530431 if (dispc_mgr_is_lcd(channel))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200432 bit = 5; /* GOLCD */
433 else
434 bit = 6; /* GODIGIT */
435
Sumit Semwal2a205f32010-12-02 11:27:12 +0000436 if (channel == OMAP_DSS_CHANNEL_LCD2)
437 return REG_GET(DISPC_CONTROL2, bit, bit) == 1;
438 else
439 return REG_GET(DISPC_CONTROL, bit, bit) == 1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200440}
441
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +0300442void dispc_mgr_go(enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200443{
444 int bit;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000445 bool enable_bit, go_bit;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200446
Archit Tanejadac57a02011-09-08 12:30:19 +0530447 if (dispc_mgr_is_lcd(channel))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200448 bit = 0; /* LCDENABLE */
449 else
450 bit = 1; /* DIGITALENABLE */
451
452 /* if the channel is not enabled, we don't need GO */
Sumit Semwal2a205f32010-12-02 11:27:12 +0000453 if (channel == OMAP_DSS_CHANNEL_LCD2)
454 enable_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
455 else
456 enable_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
457
458 if (!enable_bit)
Tomi Valkeinene6d80f92011-05-19 14:12:26 +0300459 return;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200460
Archit Tanejadac57a02011-09-08 12:30:19 +0530461 if (dispc_mgr_is_lcd(channel))
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200462 bit = 5; /* GOLCD */
463 else
464 bit = 6; /* GODIGIT */
465
Sumit Semwal2a205f32010-12-02 11:27:12 +0000466 if (channel == OMAP_DSS_CHANNEL_LCD2)
467 go_bit = REG_GET(DISPC_CONTROL2, bit, bit) == 1;
468 else
469 go_bit = REG_GET(DISPC_CONTROL, bit, bit) == 1;
470
471 if (go_bit) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200472 DSSERR("GO bit not down for channel %d\n", channel);
Tomi Valkeinene6d80f92011-05-19 14:12:26 +0300473 return;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200474 }
475
Sumit Semwal2a205f32010-12-02 11:27:12 +0000476 DSSDBG("GO %s\n", channel == OMAP_DSS_CHANNEL_LCD ? "LCD" :
477 (channel == OMAP_DSS_CHANNEL_LCD2 ? "LCD2" : "DIGIT"));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200478
Sumit Semwal2a205f32010-12-02 11:27:12 +0000479 if (channel == OMAP_DSS_CHANNEL_LCD2)
480 REG_FLD_MOD(DISPC_CONTROL2, 1, bit, bit);
481 else
482 REG_FLD_MOD(DISPC_CONTROL, 1, bit, bit);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200483}
484
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300485static void dispc_ovl_write_firh_reg(enum omap_plane plane, int reg, u32 value)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200486{
Archit Taneja9b372c22011-05-06 11:45:49 +0530487 dispc_write_reg(DISPC_OVL_FIR_COEF_H(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200488}
489
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300490static void dispc_ovl_write_firhv_reg(enum omap_plane plane, int reg, u32 value)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200491{
Archit Taneja9b372c22011-05-06 11:45:49 +0530492 dispc_write_reg(DISPC_OVL_FIR_COEF_HV(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200493}
494
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300495static void dispc_ovl_write_firv_reg(enum omap_plane plane, int reg, u32 value)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200496{
Archit Taneja9b372c22011-05-06 11:45:49 +0530497 dispc_write_reg(DISPC_OVL_FIR_COEF_V(plane, reg), value);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200498}
499
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300500static void dispc_ovl_write_firh2_reg(enum omap_plane plane, int reg, u32 value)
Amber Jainab5ca072011-05-19 19:47:53 +0530501{
502 BUG_ON(plane == OMAP_DSS_GFX);
503
504 dispc_write_reg(DISPC_OVL_FIR_COEF_H2(plane, reg), value);
505}
506
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300507static void dispc_ovl_write_firhv2_reg(enum omap_plane plane, int reg,
508 u32 value)
Amber Jainab5ca072011-05-19 19:47:53 +0530509{
510 BUG_ON(plane == OMAP_DSS_GFX);
511
512 dispc_write_reg(DISPC_OVL_FIR_COEF_HV2(plane, reg), value);
513}
514
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300515static void dispc_ovl_write_firv2_reg(enum omap_plane plane, int reg, u32 value)
Amber Jainab5ca072011-05-19 19:47:53 +0530516{
517 BUG_ON(plane == OMAP_DSS_GFX);
518
519 dispc_write_reg(DISPC_OVL_FIR_COEF_V2(plane, reg), value);
520}
521
Chandrabhanu Mahapatradebd9072011-12-19 14:03:44 +0530522static void dispc_ovl_set_scale_coef(enum omap_plane plane, int fir_hinc,
523 int fir_vinc, int five_taps,
524 enum omap_color_component color_comp)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200525{
Chandrabhanu Mahapatradebd9072011-12-19 14:03:44 +0530526 const struct dispc_coef *h_coef, *v_coef;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200527 int i;
528
Chandrabhanu Mahapatradebd9072011-12-19 14:03:44 +0530529 h_coef = dispc_ovl_get_scale_coef(fir_hinc, true);
530 v_coef = dispc_ovl_get_scale_coef(fir_vinc, five_taps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200531
532 for (i = 0; i < 8; i++) {
533 u32 h, hv;
534
Chandrabhanu Mahapatradebd9072011-12-19 14:03:44 +0530535 h = FLD_VAL(h_coef[i].hc0_vc00, 7, 0)
536 | FLD_VAL(h_coef[i].hc1_vc0, 15, 8)
537 | FLD_VAL(h_coef[i].hc2_vc1, 23, 16)
538 | FLD_VAL(h_coef[i].hc3_vc2, 31, 24);
539 hv = FLD_VAL(h_coef[i].hc4_vc22, 7, 0)
540 | FLD_VAL(v_coef[i].hc1_vc0, 15, 8)
541 | FLD_VAL(v_coef[i].hc2_vc1, 23, 16)
542 | FLD_VAL(v_coef[i].hc3_vc2, 31, 24);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200543
Amber Jain0d66cbb2011-05-19 19:47:54 +0530544 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300545 dispc_ovl_write_firh_reg(plane, i, h);
546 dispc_ovl_write_firhv_reg(plane, i, hv);
Amber Jain0d66cbb2011-05-19 19:47:54 +0530547 } else {
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300548 dispc_ovl_write_firh2_reg(plane, i, h);
549 dispc_ovl_write_firhv2_reg(plane, i, hv);
Amber Jain0d66cbb2011-05-19 19:47:54 +0530550 }
551
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200552 }
553
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200554 if (five_taps) {
555 for (i = 0; i < 8; i++) {
556 u32 v;
Chandrabhanu Mahapatradebd9072011-12-19 14:03:44 +0530557 v = FLD_VAL(v_coef[i].hc0_vc00, 7, 0)
558 | FLD_VAL(v_coef[i].hc4_vc22, 15, 8);
Amber Jain0d66cbb2011-05-19 19:47:54 +0530559 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y)
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300560 dispc_ovl_write_firv_reg(plane, i, v);
Amber Jain0d66cbb2011-05-19 19:47:54 +0530561 else
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300562 dispc_ovl_write_firv2_reg(plane, i, v);
Grazvydas Ignotas66be8f62010-08-24 15:18:43 +0200563 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200564 }
565}
566
567static void _dispc_setup_color_conv_coef(void)
568{
Archit Tanejaac01c292011-08-05 19:06:03 +0530569 int i;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200570 const struct color_conv_coef {
571 int ry, rcr, rcb, gy, gcr, gcb, by, bcr, bcb;
572 int full_range;
573 } ctbl_bt601_5 = {
574 298, 409, 0, 298, -208, -100, 298, 0, 517, 0,
575 };
576
577 const struct color_conv_coef *ct;
578
579#define CVAL(x, y) (FLD_VAL(x, 26, 16) | FLD_VAL(y, 10, 0))
580
581 ct = &ctbl_bt601_5;
582
Archit Tanejaac01c292011-08-05 19:06:03 +0530583 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
584 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 0),
585 CVAL(ct->rcr, ct->ry));
586 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 1),
587 CVAL(ct->gy, ct->rcb));
588 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 2),
589 CVAL(ct->gcb, ct->gcr));
590 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 3),
591 CVAL(ct->bcr, ct->by));
592 dispc_write_reg(DISPC_OVL_CONV_COEF(i, 4),
593 CVAL(0, ct->bcb));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200594
Archit Tanejaac01c292011-08-05 19:06:03 +0530595 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), ct->full_range,
596 11, 11);
597 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200598
599#undef CVAL
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200600}
601
602
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300603static void dispc_ovl_set_ba0(enum omap_plane plane, u32 paddr)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200604{
Archit Taneja9b372c22011-05-06 11:45:49 +0530605 dispc_write_reg(DISPC_OVL_BA0(plane), paddr);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200606}
607
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300608static void dispc_ovl_set_ba1(enum omap_plane plane, u32 paddr)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200609{
Archit Taneja9b372c22011-05-06 11:45:49 +0530610 dispc_write_reg(DISPC_OVL_BA1(plane), paddr);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200611}
612
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300613static void dispc_ovl_set_ba0_uv(enum omap_plane plane, u32 paddr)
Amber Jainab5ca072011-05-19 19:47:53 +0530614{
615 dispc_write_reg(DISPC_OVL_BA0_UV(plane), paddr);
616}
617
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300618static void dispc_ovl_set_ba1_uv(enum omap_plane plane, u32 paddr)
Amber Jainab5ca072011-05-19 19:47:53 +0530619{
620 dispc_write_reg(DISPC_OVL_BA1_UV(plane), paddr);
621}
622
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300623static void dispc_ovl_set_pos(enum omap_plane plane, int x, int y)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200624{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200625 u32 val = FLD_VAL(y, 26, 16) | FLD_VAL(x, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530626
627 dispc_write_reg(DISPC_OVL_POSITION(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200628}
629
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300630static void dispc_ovl_set_pic_size(enum omap_plane plane, int width, int height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200631{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200632 u32 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530633
634 if (plane == OMAP_DSS_GFX)
635 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
636 else
637 dispc_write_reg(DISPC_OVL_PICTURE_SIZE(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200638}
639
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300640static void dispc_ovl_set_vid_size(enum omap_plane plane, int width, int height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200641{
642 u32 val;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200643
644 BUG_ON(plane == OMAP_DSS_GFX);
645
646 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
Archit Taneja9b372c22011-05-06 11:45:49 +0530647
648 dispc_write_reg(DISPC_OVL_SIZE(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200649}
650
Archit Taneja54128702011-09-08 11:29:17 +0530651static void dispc_ovl_set_zorder(enum omap_plane plane, u8 zorder)
652{
653 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
654
655 if ((ovl->caps & OMAP_DSS_OVL_CAP_ZORDER) == 0)
656 return;
657
658 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), zorder, 27, 26);
659}
660
661static void dispc_ovl_enable_zorder_planes(void)
662{
663 int i;
664
665 if (!dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
666 return;
667
668 for (i = 0; i < dss_feat_get_num_ovls(); i++)
669 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(i), 1, 25, 25);
670}
671
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300672static void dispc_ovl_set_pre_mult_alpha(enum omap_plane plane, bool enable)
Rajkumar Nfd28a392010-11-04 12:28:42 +0100673{
Tomi Valkeinenf6dc8152011-08-15 15:18:20 +0300674 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
Rajkumar Nfd28a392010-11-04 12:28:42 +0100675
Tomi Valkeinenf6dc8152011-08-15 15:18:20 +0300676 if ((ovl->caps & OMAP_DSS_OVL_CAP_PRE_MULT_ALPHA) == 0)
Rajkumar Nfd28a392010-11-04 12:28:42 +0100677 return;
678
Archit Taneja9b372c22011-05-06 11:45:49 +0530679 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 28, 28);
Rajkumar Nfd28a392010-11-04 12:28:42 +0100680}
681
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300682static void dispc_ovl_setup_global_alpha(enum omap_plane plane, u8 global_alpha)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200683{
Archit Tanejab8c095b2011-09-13 18:20:33 +0530684 static const unsigned shifts[] = { 0, 8, 16, 24, };
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +0300685 int shift;
Tomi Valkeinenf6dc8152011-08-15 15:18:20 +0300686 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +0300687
Tomi Valkeinenf6dc8152011-08-15 15:18:20 +0300688 if ((ovl->caps & OMAP_DSS_OVL_CAP_GLOBAL_ALPHA) == 0)
Rajkumar Nfd28a392010-11-04 12:28:42 +0100689 return;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530690
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +0300691 shift = shifts[plane];
692 REG_FLD_MOD(DISPC_GLOBAL_ALPHA, global_alpha, shift + 7, shift);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200693}
694
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300695static void dispc_ovl_set_pix_inc(enum omap_plane plane, s32 inc)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200696{
Archit Taneja9b372c22011-05-06 11:45:49 +0530697 dispc_write_reg(DISPC_OVL_PIXEL_INC(plane), inc);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200698}
699
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300700static void dispc_ovl_set_row_inc(enum omap_plane plane, s32 inc)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200701{
Archit Taneja9b372c22011-05-06 11:45:49 +0530702 dispc_write_reg(DISPC_OVL_ROW_INC(plane), inc);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200703}
704
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300705static void dispc_ovl_set_color_mode(enum omap_plane plane,
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200706 enum omap_color_mode color_mode)
707{
708 u32 m = 0;
Amber Jainf20e4222011-05-19 19:47:50 +0530709 if (plane != OMAP_DSS_GFX) {
710 switch (color_mode) {
711 case OMAP_DSS_COLOR_NV12:
712 m = 0x0; break;
Lajos Molnar08f32672012-02-21 19:36:30 +0530713 case OMAP_DSS_COLOR_RGBX16:
Amber Jainf20e4222011-05-19 19:47:50 +0530714 m = 0x1; break;
715 case OMAP_DSS_COLOR_RGBA16:
716 m = 0x2; break;
Lajos Molnar08f32672012-02-21 19:36:30 +0530717 case OMAP_DSS_COLOR_RGB12U:
Amber Jainf20e4222011-05-19 19:47:50 +0530718 m = 0x4; break;
719 case OMAP_DSS_COLOR_ARGB16:
720 m = 0x5; break;
721 case OMAP_DSS_COLOR_RGB16:
722 m = 0x6; break;
723 case OMAP_DSS_COLOR_ARGB16_1555:
724 m = 0x7; break;
725 case OMAP_DSS_COLOR_RGB24U:
726 m = 0x8; break;
727 case OMAP_DSS_COLOR_RGB24P:
728 m = 0x9; break;
729 case OMAP_DSS_COLOR_YUV2:
730 m = 0xa; break;
731 case OMAP_DSS_COLOR_UYVY:
732 m = 0xb; break;
733 case OMAP_DSS_COLOR_ARGB32:
734 m = 0xc; break;
735 case OMAP_DSS_COLOR_RGBA32:
736 m = 0xd; break;
737 case OMAP_DSS_COLOR_RGBX32:
738 m = 0xe; break;
739 case OMAP_DSS_COLOR_XRGB16_1555:
740 m = 0xf; break;
741 default:
742 BUG(); break;
743 }
744 } else {
745 switch (color_mode) {
746 case OMAP_DSS_COLOR_CLUT1:
747 m = 0x0; break;
748 case OMAP_DSS_COLOR_CLUT2:
749 m = 0x1; break;
750 case OMAP_DSS_COLOR_CLUT4:
751 m = 0x2; break;
752 case OMAP_DSS_COLOR_CLUT8:
753 m = 0x3; break;
754 case OMAP_DSS_COLOR_RGB12U:
755 m = 0x4; break;
756 case OMAP_DSS_COLOR_ARGB16:
757 m = 0x5; break;
758 case OMAP_DSS_COLOR_RGB16:
759 m = 0x6; break;
760 case OMAP_DSS_COLOR_ARGB16_1555:
761 m = 0x7; break;
762 case OMAP_DSS_COLOR_RGB24U:
763 m = 0x8; break;
764 case OMAP_DSS_COLOR_RGB24P:
765 m = 0x9; break;
Lajos Molnar08f32672012-02-21 19:36:30 +0530766 case OMAP_DSS_COLOR_RGBX16:
Amber Jainf20e4222011-05-19 19:47:50 +0530767 m = 0xa; break;
Lajos Molnar08f32672012-02-21 19:36:30 +0530768 case OMAP_DSS_COLOR_RGBA16:
Amber Jainf20e4222011-05-19 19:47:50 +0530769 m = 0xb; break;
770 case OMAP_DSS_COLOR_ARGB32:
771 m = 0xc; break;
772 case OMAP_DSS_COLOR_RGBA32:
773 m = 0xd; break;
774 case OMAP_DSS_COLOR_RGBX32:
775 m = 0xe; break;
776 case OMAP_DSS_COLOR_XRGB16_1555:
777 m = 0xf; break;
778 default:
779 BUG(); break;
780 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200781 }
782
Archit Taneja9b372c22011-05-06 11:45:49 +0530783 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), m, 4, 1);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200784}
785
Tomi Valkeinenf4279842011-10-28 15:26:26 +0300786void dispc_ovl_set_channel_out(enum omap_plane plane, enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200787{
788 int shift;
789 u32 val;
Sumit Semwal2a205f32010-12-02 11:27:12 +0000790 int chan = 0, chan2 = 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200791
792 switch (plane) {
793 case OMAP_DSS_GFX:
794 shift = 8;
795 break;
796 case OMAP_DSS_VIDEO1:
797 case OMAP_DSS_VIDEO2:
Archit Tanejab8c095b2011-09-13 18:20:33 +0530798 case OMAP_DSS_VIDEO3:
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200799 shift = 16;
800 break;
801 default:
802 BUG();
803 return;
804 }
805
Archit Taneja9b372c22011-05-06 11:45:49 +0530806 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Sumit Semwal2a205f32010-12-02 11:27:12 +0000807 if (dss_has_feature(FEAT_MGR_LCD2)) {
808 switch (channel) {
809 case OMAP_DSS_CHANNEL_LCD:
810 chan = 0;
811 chan2 = 0;
812 break;
813 case OMAP_DSS_CHANNEL_DIGIT:
814 chan = 1;
815 chan2 = 0;
816 break;
817 case OMAP_DSS_CHANNEL_LCD2:
818 chan = 0;
819 chan2 = 1;
820 break;
821 default:
822 BUG();
823 }
824
825 val = FLD_MOD(val, chan, shift, shift);
826 val = FLD_MOD(val, chan2, 31, 30);
827 } else {
828 val = FLD_MOD(val, channel, shift, shift);
829 }
Archit Taneja9b372c22011-05-06 11:45:49 +0530830 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200831}
832
Tomi Valkeinen2cc5d1a2011-11-03 17:03:44 +0200833static enum omap_channel dispc_ovl_get_channel_out(enum omap_plane plane)
834{
835 int shift;
836 u32 val;
837 enum omap_channel channel;
838
839 switch (plane) {
840 case OMAP_DSS_GFX:
841 shift = 8;
842 break;
843 case OMAP_DSS_VIDEO1:
844 case OMAP_DSS_VIDEO2:
845 case OMAP_DSS_VIDEO3:
846 shift = 16;
847 break;
848 default:
849 BUG();
850 }
851
852 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
853
854 if (dss_has_feature(FEAT_MGR_LCD2)) {
855 if (FLD_GET(val, 31, 30) == 0)
856 channel = FLD_GET(val, shift, shift);
857 else
858 channel = OMAP_DSS_CHANNEL_LCD2;
859 } else {
860 channel = FLD_GET(val, shift, shift);
861 }
862
863 return channel;
864}
865
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300866static void dispc_ovl_set_burst_size(enum omap_plane plane,
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200867 enum omap_burst_size burst_size)
868{
Archit Tanejab8c095b2011-09-13 18:20:33 +0530869 static const unsigned shifts[] = { 6, 14, 14, 14, };
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200870 int shift;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200871
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +0300872 shift = shifts[plane];
Tomi Valkeinen5ed8cf52011-06-21 09:35:36 +0300873 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), burst_size, shift + 1, shift);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200874}
875
Tomi Valkeinen5ed8cf52011-06-21 09:35:36 +0300876static void dispc_configure_burst_sizes(void)
877{
878 int i;
879 const int burst_size = BURST_SIZE_X8;
880
881 /* Configure burst size always to maximum size */
882 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300883 dispc_ovl_set_burst_size(i, burst_size);
Tomi Valkeinen5ed8cf52011-06-21 09:35:36 +0300884}
885
Tomi Valkeinen83fa2f22012-01-13 13:17:01 +0200886static u32 dispc_ovl_get_burst_size(enum omap_plane plane)
Tomi Valkeinen5ed8cf52011-06-21 09:35:36 +0300887{
888 unsigned unit = dss_feat_get_burst_size_unit();
889 /* burst multiplier is always x8 (see dispc_configure_burst_sizes()) */
890 return unit * 8;
891}
892
Mythri P Kd3862612011-03-11 18:02:49 +0530893void dispc_enable_gamma_table(bool enable)
894{
895 /*
896 * This is partially implemented to support only disabling of
897 * the gamma table.
898 */
899 if (enable) {
900 DSSWARN("Gamma table enabling for TV not yet supported");
901 return;
902 }
903
904 REG_FLD_MOD(DISPC_CONFIG, enable, 9, 9);
905}
906
Tomi Valkeinenc64dca42011-11-04 18:14:20 +0200907static void dispc_mgr_enable_cpr(enum omap_channel channel, bool enable)
Tomi Valkeinen3c07cae2011-06-21 09:34:30 +0300908{
909 u16 reg;
910
911 if (channel == OMAP_DSS_CHANNEL_LCD)
912 reg = DISPC_CONFIG;
913 else if (channel == OMAP_DSS_CHANNEL_LCD2)
914 reg = DISPC_CONFIG2;
915 else
916 return;
917
918 REG_FLD_MOD(reg, enable, 15, 15);
919}
920
Tomi Valkeinenc64dca42011-11-04 18:14:20 +0200921static void dispc_mgr_set_cpr_coef(enum omap_channel channel,
Tomi Valkeinen3c07cae2011-06-21 09:34:30 +0300922 struct omap_dss_cpr_coefs *coefs)
923{
924 u32 coef_r, coef_g, coef_b;
925
Archit Tanejadac57a02011-09-08 12:30:19 +0530926 if (!dispc_mgr_is_lcd(channel))
Tomi Valkeinen3c07cae2011-06-21 09:34:30 +0300927 return;
928
929 coef_r = FLD_VAL(coefs->rr, 31, 22) | FLD_VAL(coefs->rg, 20, 11) |
930 FLD_VAL(coefs->rb, 9, 0);
931 coef_g = FLD_VAL(coefs->gr, 31, 22) | FLD_VAL(coefs->gg, 20, 11) |
932 FLD_VAL(coefs->gb, 9, 0);
933 coef_b = FLD_VAL(coefs->br, 31, 22) | FLD_VAL(coefs->bg, 20, 11) |
934 FLD_VAL(coefs->bb, 9, 0);
935
936 dispc_write_reg(DISPC_CPR_COEF_R(channel), coef_r);
937 dispc_write_reg(DISPC_CPR_COEF_G(channel), coef_g);
938 dispc_write_reg(DISPC_CPR_COEF_B(channel), coef_b);
939}
940
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +0300941static void dispc_ovl_set_vid_color_conv(enum omap_plane plane, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200942{
943 u32 val;
944
945 BUG_ON(plane == OMAP_DSS_GFX);
946
Archit Taneja9b372c22011-05-06 11:45:49 +0530947 val = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200948 val = FLD_MOD(val, enable, 9, 9);
Archit Taneja9b372c22011-05-06 11:45:49 +0530949 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200950}
951
Archit Tanejac3d925292011-09-14 11:52:54 +0530952static void dispc_ovl_enable_replication(enum omap_plane plane, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200953{
Archit Tanejab8c095b2011-09-13 18:20:33 +0530954 static const unsigned shifts[] = { 5, 10, 10, 10 };
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +0300955 int shift;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200956
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +0300957 shift = shifts[plane];
958 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable, shift, shift);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200959}
960
Archit Taneja8f366162012-04-16 12:53:44 +0530961static void dispc_mgr_set_size(enum omap_channel channel, u16 width,
Archit Tanejae5c09e02012-04-16 12:53:42 +0530962 u16 height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200963{
964 u32 val;
Archit Taneja8f366162012-04-16 12:53:44 +0530965
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200966 val = FLD_VAL(height - 1, 26, 16) | FLD_VAL(width - 1, 10, 0);
Archit Taneja702d1442011-05-06 11:45:50 +0530967 dispc_write_reg(DISPC_SIZE_MGR(channel), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200968}
969
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200970static void dispc_read_plane_fifo_sizes(void)
971{
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200972 u32 size;
973 int plane;
Archit Tanejaa0acb552010-09-15 19:20:00 +0530974 u8 start, end;
Tomi Valkeinen5ed8cf52011-06-21 09:35:36 +0300975 u32 unit;
976
977 unit = dss_feat_get_buffer_size_unit();
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200978
Archit Tanejaa0acb552010-09-15 19:20:00 +0530979 dss_feat_get_reg_field(FEAT_REG_FIFOSIZE, &start, &end);
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200980
Archit Tanejae13a1382011-08-05 19:06:04 +0530981 for (plane = 0; plane < dss_feat_get_num_ovls(); ++plane) {
Tomi Valkeinen5ed8cf52011-06-21 09:35:36 +0300982 size = REG_GET(DISPC_OVL_FIFO_SIZE_STATUS(plane), start, end);
983 size *= unit;
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200984 dispc.fifo_size[plane] = size;
985 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200986}
987
Tomi Valkeinen83fa2f22012-01-13 13:17:01 +0200988static u32 dispc_ovl_get_fifo_size(enum omap_plane plane)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200989{
990 return dispc.fifo_size[plane];
991}
992
Tomi Valkeinen6f04e1b2011-10-31 08:58:52 +0200993void dispc_ovl_set_fifo_threshold(enum omap_plane plane, u32 low, u32 high)
Tomi Valkeinen80c39712009-11-12 11:41:42 +0200994{
Archit Tanejaa0acb552010-09-15 19:20:00 +0530995 u8 hi_start, hi_end, lo_start, lo_end;
Tomi Valkeinen5ed8cf52011-06-21 09:35:36 +0300996 u32 unit;
997
998 unit = dss_feat_get_buffer_size_unit();
999
1000 WARN_ON(low % unit != 0);
1001 WARN_ON(high % unit != 0);
1002
1003 low /= unit;
1004 high /= unit;
Archit Tanejaa0acb552010-09-15 19:20:00 +05301005
Archit Taneja9b372c22011-05-06 11:45:49 +05301006 dss_feat_get_reg_field(FEAT_REG_FIFOHIGHTHRESHOLD, &hi_start, &hi_end);
1007 dss_feat_get_reg_field(FEAT_REG_FIFOLOWTHRESHOLD, &lo_start, &lo_end);
1008
Tomi Valkeinen3cb5d962012-01-13 13:14:57 +02001009 DSSDBG("fifo(%d) threshold (bytes), old %u/%u, new %u/%u\n",
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001010 plane,
Archit Taneja9b372c22011-05-06 11:45:49 +05301011 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
Tomi Valkeinen3cb5d962012-01-13 13:14:57 +02001012 lo_start, lo_end) * unit,
Archit Taneja9b372c22011-05-06 11:45:49 +05301013 REG_GET(DISPC_OVL_FIFO_THRESHOLD(plane),
Tomi Valkeinen3cb5d962012-01-13 13:14:57 +02001014 hi_start, hi_end) * unit,
1015 low * unit, high * unit);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001016
Archit Taneja9b372c22011-05-06 11:45:49 +05301017 dispc_write_reg(DISPC_OVL_FIFO_THRESHOLD(plane),
Archit Tanejaa0acb552010-09-15 19:20:00 +05301018 FLD_VAL(high, hi_start, hi_end) |
1019 FLD_VAL(low, lo_start, lo_end));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001020}
1021
1022void dispc_enable_fifomerge(bool enable)
1023{
Tomi Valkeinene6b0f882012-01-13 13:24:04 +02001024 if (!dss_has_feature(FEAT_FIFO_MERGE)) {
1025 WARN_ON(enable);
1026 return;
1027 }
1028
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001029 DSSDBG("FIFO merge %s\n", enable ? "enabled" : "disabled");
1030 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 14, 14);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001031}
1032
Tomi Valkeinen83fa2f22012-01-13 13:17:01 +02001033void dispc_ovl_compute_fifo_thresholds(enum omap_plane plane,
Tomi Valkeinen3568f2a2012-05-15 15:31:01 +03001034 u32 *fifo_low, u32 *fifo_high, bool use_fifomerge,
1035 bool manual_update)
Tomi Valkeinen83fa2f22012-01-13 13:17:01 +02001036{
1037 /*
1038 * All sizes are in bytes. Both the buffer and burst are made of
1039 * buffer_units, and the fifo thresholds must be buffer_unit aligned.
1040 */
1041
1042 unsigned buf_unit = dss_feat_get_buffer_size_unit();
Tomi Valkeinene0e405b2012-01-13 13:18:11 +02001043 unsigned ovl_fifo_size, total_fifo_size, burst_size;
1044 int i;
Tomi Valkeinen83fa2f22012-01-13 13:17:01 +02001045
1046 burst_size = dispc_ovl_get_burst_size(plane);
Tomi Valkeinene0e405b2012-01-13 13:18:11 +02001047 ovl_fifo_size = dispc_ovl_get_fifo_size(plane);
Tomi Valkeinen83fa2f22012-01-13 13:17:01 +02001048
Tomi Valkeinene0e405b2012-01-13 13:18:11 +02001049 if (use_fifomerge) {
1050 total_fifo_size = 0;
1051 for (i = 0; i < omap_dss_get_num_overlays(); ++i)
1052 total_fifo_size += dispc_ovl_get_fifo_size(i);
1053 } else {
1054 total_fifo_size = ovl_fifo_size;
1055 }
1056
1057 /*
1058 * We use the same low threshold for both fifomerge and non-fifomerge
1059 * cases, but for fifomerge we calculate the high threshold using the
1060 * combined fifo size
1061 */
1062
Tomi Valkeinen3568f2a2012-05-15 15:31:01 +03001063 if (manual_update && dss_has_feature(FEAT_OMAP3_DSI_FIFO_BUG)) {
Tomi Valkeinene0e405b2012-01-13 13:18:11 +02001064 *fifo_low = ovl_fifo_size - burst_size * 2;
1065 *fifo_high = total_fifo_size - burst_size;
1066 } else {
1067 *fifo_low = ovl_fifo_size - burst_size;
1068 *fifo_high = total_fifo_size - buf_unit;
1069 }
Tomi Valkeinen83fa2f22012-01-13 13:17:01 +02001070}
1071
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001072static void dispc_ovl_set_fir(enum omap_plane plane,
Amber Jain0d66cbb2011-05-19 19:47:54 +05301073 int hinc, int vinc,
1074 enum omap_color_component color_comp)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001075{
1076 u32 val;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001077
Amber Jain0d66cbb2011-05-19 19:47:54 +05301078 if (color_comp == DISPC_COLOR_COMPONENT_RGB_Y) {
1079 u8 hinc_start, hinc_end, vinc_start, vinc_end;
Archit Tanejaa0acb552010-09-15 19:20:00 +05301080
Amber Jain0d66cbb2011-05-19 19:47:54 +05301081 dss_feat_get_reg_field(FEAT_REG_FIRHINC,
1082 &hinc_start, &hinc_end);
1083 dss_feat_get_reg_field(FEAT_REG_FIRVINC,
1084 &vinc_start, &vinc_end);
1085 val = FLD_VAL(vinc, vinc_start, vinc_end) |
1086 FLD_VAL(hinc, hinc_start, hinc_end);
Archit Tanejaa0acb552010-09-15 19:20:00 +05301087
Amber Jain0d66cbb2011-05-19 19:47:54 +05301088 dispc_write_reg(DISPC_OVL_FIR(plane), val);
1089 } else {
1090 val = FLD_VAL(vinc, 28, 16) | FLD_VAL(hinc, 12, 0);
1091 dispc_write_reg(DISPC_OVL_FIR2(plane), val);
1092 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001093}
1094
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001095static void dispc_ovl_set_vid_accu0(enum omap_plane plane, int haccu, int vaccu)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001096{
1097 u32 val;
Archit Taneja87a74842011-03-02 11:19:50 +05301098 u8 hor_start, hor_end, vert_start, vert_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001099
Archit Taneja87a74842011-03-02 11:19:50 +05301100 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1101 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1102
1103 val = FLD_VAL(vaccu, vert_start, vert_end) |
1104 FLD_VAL(haccu, hor_start, hor_end);
1105
Archit Taneja9b372c22011-05-06 11:45:49 +05301106 dispc_write_reg(DISPC_OVL_ACCU0(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001107}
1108
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001109static void dispc_ovl_set_vid_accu1(enum omap_plane plane, int haccu, int vaccu)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001110{
1111 u32 val;
Archit Taneja87a74842011-03-02 11:19:50 +05301112 u8 hor_start, hor_end, vert_start, vert_end;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001113
Archit Taneja87a74842011-03-02 11:19:50 +05301114 dss_feat_get_reg_field(FEAT_REG_HORIZONTALACCU, &hor_start, &hor_end);
1115 dss_feat_get_reg_field(FEAT_REG_VERTICALACCU, &vert_start, &vert_end);
1116
1117 val = FLD_VAL(vaccu, vert_start, vert_end) |
1118 FLD_VAL(haccu, hor_start, hor_end);
1119
Archit Taneja9b372c22011-05-06 11:45:49 +05301120 dispc_write_reg(DISPC_OVL_ACCU1(plane), val);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001121}
1122
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001123static void dispc_ovl_set_vid_accu2_0(enum omap_plane plane, int haccu,
1124 int vaccu)
Amber Jainab5ca072011-05-19 19:47:53 +05301125{
1126 u32 val;
1127
1128 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1129 dispc_write_reg(DISPC_OVL_ACCU2_0(plane), val);
1130}
1131
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001132static void dispc_ovl_set_vid_accu2_1(enum omap_plane plane, int haccu,
1133 int vaccu)
Amber Jainab5ca072011-05-19 19:47:53 +05301134{
1135 u32 val;
1136
1137 val = FLD_VAL(vaccu, 26, 16) | FLD_VAL(haccu, 10, 0);
1138 dispc_write_reg(DISPC_OVL_ACCU2_1(plane), val);
1139}
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001140
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001141static void dispc_ovl_set_scale_param(enum omap_plane plane,
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001142 u16 orig_width, u16 orig_height,
1143 u16 out_width, u16 out_height,
Amber Jain0d66cbb2011-05-19 19:47:54 +05301144 bool five_taps, u8 rotation,
1145 enum omap_color_component color_comp)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001146{
Amber Jain0d66cbb2011-05-19 19:47:54 +05301147 int fir_hinc, fir_vinc;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001148
Amber Jained14a3c2011-05-19 19:47:51 +05301149 fir_hinc = 1024 * orig_width / out_width;
1150 fir_vinc = 1024 * orig_height / out_height;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001151
Chandrabhanu Mahapatradebd9072011-12-19 14:03:44 +05301152 dispc_ovl_set_scale_coef(plane, fir_hinc, fir_vinc, five_taps,
1153 color_comp);
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001154 dispc_ovl_set_fir(plane, fir_hinc, fir_vinc, color_comp);
Amber Jain0d66cbb2011-05-19 19:47:54 +05301155}
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001156
Chandrabhanu Mahapatra05dd0f52012-05-15 12:22:34 +05301157static void dispc_ovl_set_accu_uv(enum omap_plane plane,
1158 u16 orig_width, u16 orig_height, u16 out_width, u16 out_height,
1159 bool ilace, enum omap_color_mode color_mode, u8 rotation)
1160{
1161 int h_accu2_0, h_accu2_1;
1162 int v_accu2_0, v_accu2_1;
1163 int chroma_hinc, chroma_vinc;
1164 int idx;
1165
1166 struct accu {
1167 s8 h0_m, h0_n;
1168 s8 h1_m, h1_n;
1169 s8 v0_m, v0_n;
1170 s8 v1_m, v1_n;
1171 };
1172
1173 const struct accu *accu_table;
1174 const struct accu *accu_val;
1175
1176 static const struct accu accu_nv12[4] = {
1177 { 0, 1, 0, 1 , -1, 2, 0, 1 },
1178 { 1, 2, -3, 4 , 0, 1, 0, 1 },
1179 { -1, 1, 0, 1 , -1, 2, 0, 1 },
1180 { -1, 2, -1, 2 , -1, 1, 0, 1 },
1181 };
1182
1183 static const struct accu accu_nv12_ilace[4] = {
1184 { 0, 1, 0, 1 , -3, 4, -1, 4 },
1185 { -1, 4, -3, 4 , 0, 1, 0, 1 },
1186 { -1, 1, 0, 1 , -1, 4, -3, 4 },
1187 { -3, 4, -3, 4 , -1, 1, 0, 1 },
1188 };
1189
1190 static const struct accu accu_yuv[4] = {
1191 { 0, 1, 0, 1, 0, 1, 0, 1 },
1192 { 0, 1, 0, 1, 0, 1, 0, 1 },
1193 { -1, 1, 0, 1, 0, 1, 0, 1 },
1194 { 0, 1, 0, 1, -1, 1, 0, 1 },
1195 };
1196
1197 switch (rotation) {
1198 case OMAP_DSS_ROT_0:
1199 idx = 0;
1200 break;
1201 case OMAP_DSS_ROT_90:
1202 idx = 1;
1203 break;
1204 case OMAP_DSS_ROT_180:
1205 idx = 2;
1206 break;
1207 case OMAP_DSS_ROT_270:
1208 idx = 3;
1209 break;
1210 default:
1211 BUG();
1212 }
1213
1214 switch (color_mode) {
1215 case OMAP_DSS_COLOR_NV12:
1216 if (ilace)
1217 accu_table = accu_nv12_ilace;
1218 else
1219 accu_table = accu_nv12;
1220 break;
1221 case OMAP_DSS_COLOR_YUV2:
1222 case OMAP_DSS_COLOR_UYVY:
1223 accu_table = accu_yuv;
1224 break;
1225 default:
1226 BUG();
1227 }
1228
1229 accu_val = &accu_table[idx];
1230
1231 chroma_hinc = 1024 * orig_width / out_width;
1232 chroma_vinc = 1024 * orig_height / out_height;
1233
1234 h_accu2_0 = (accu_val->h0_m * chroma_hinc / accu_val->h0_n) % 1024;
1235 h_accu2_1 = (accu_val->h1_m * chroma_hinc / accu_val->h1_n) % 1024;
1236 v_accu2_0 = (accu_val->v0_m * chroma_vinc / accu_val->v0_n) % 1024;
1237 v_accu2_1 = (accu_val->v1_m * chroma_vinc / accu_val->v1_n) % 1024;
1238
1239 dispc_ovl_set_vid_accu2_0(plane, h_accu2_0, v_accu2_0);
1240 dispc_ovl_set_vid_accu2_1(plane, h_accu2_1, v_accu2_1);
1241}
1242
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001243static void dispc_ovl_set_scaling_common(enum omap_plane plane,
Amber Jain0d66cbb2011-05-19 19:47:54 +05301244 u16 orig_width, u16 orig_height,
1245 u16 out_width, u16 out_height,
1246 bool ilace, bool five_taps,
1247 bool fieldmode, enum omap_color_mode color_mode,
1248 u8 rotation)
1249{
1250 int accu0 = 0;
1251 int accu1 = 0;
1252 u32 l;
1253
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001254 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
Amber Jain0d66cbb2011-05-19 19:47:54 +05301255 out_width, out_height, five_taps,
1256 rotation, DISPC_COLOR_COMPONENT_RGB_Y);
Archit Taneja9b372c22011-05-06 11:45:49 +05301257 l = dispc_read_reg(DISPC_OVL_ATTRIBUTES(plane));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001258
Archit Taneja87a74842011-03-02 11:19:50 +05301259 /* RESIZEENABLE and VERTICALTAPS */
1260 l &= ~((0x3 << 5) | (0x1 << 21));
Amber Jained14a3c2011-05-19 19:47:51 +05301261 l |= (orig_width != out_width) ? (1 << 5) : 0;
1262 l |= (orig_height != out_height) ? (1 << 6) : 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001263 l |= five_taps ? (1 << 21) : 0;
Archit Taneja87a74842011-03-02 11:19:50 +05301264
1265 /* VRESIZECONF and HRESIZECONF */
1266 if (dss_has_feature(FEAT_RESIZECONF)) {
1267 l &= ~(0x3 << 7);
Amber Jain0d66cbb2011-05-19 19:47:54 +05301268 l |= (orig_width <= out_width) ? 0 : (1 << 7);
1269 l |= (orig_height <= out_height) ? 0 : (1 << 8);
Archit Taneja87a74842011-03-02 11:19:50 +05301270 }
1271
1272 /* LINEBUFFERSPLIT */
1273 if (dss_has_feature(FEAT_LINEBUFFERSPLIT)) {
1274 l &= ~(0x1 << 22);
1275 l |= five_taps ? (1 << 22) : 0;
1276 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001277
Archit Taneja9b372c22011-05-06 11:45:49 +05301278 dispc_write_reg(DISPC_OVL_ATTRIBUTES(plane), l);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001279
1280 /*
1281 * field 0 = even field = bottom field
1282 * field 1 = odd field = top field
1283 */
1284 if (ilace && !fieldmode) {
1285 accu1 = 0;
Amber Jain0d66cbb2011-05-19 19:47:54 +05301286 accu0 = ((1024 * orig_height / out_height) / 2) & 0x3ff;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001287 if (accu0 >= 1024/2) {
1288 accu1 = 1024/2;
1289 accu0 -= accu1;
1290 }
1291 }
1292
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001293 dispc_ovl_set_vid_accu0(plane, 0, accu0);
1294 dispc_ovl_set_vid_accu1(plane, 0, accu1);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001295}
1296
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001297static void dispc_ovl_set_scaling_uv(enum omap_plane plane,
Amber Jain0d66cbb2011-05-19 19:47:54 +05301298 u16 orig_width, u16 orig_height,
1299 u16 out_width, u16 out_height,
1300 bool ilace, bool five_taps,
1301 bool fieldmode, enum omap_color_mode color_mode,
1302 u8 rotation)
1303{
1304 int scale_x = out_width != orig_width;
1305 int scale_y = out_height != orig_height;
1306
1307 if (!dss_has_feature(FEAT_HANDLE_UV_SEPARATE))
1308 return;
1309 if ((color_mode != OMAP_DSS_COLOR_YUV2 &&
1310 color_mode != OMAP_DSS_COLOR_UYVY &&
1311 color_mode != OMAP_DSS_COLOR_NV12)) {
1312 /* reset chroma resampling for RGB formats */
1313 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane), 0, 8, 8);
1314 return;
1315 }
Tomi Valkeinen36377352012-05-15 15:54:15 +03001316
1317 dispc_ovl_set_accu_uv(plane, orig_width, orig_height, out_width,
1318 out_height, ilace, color_mode, rotation);
1319
Amber Jain0d66cbb2011-05-19 19:47:54 +05301320 switch (color_mode) {
1321 case OMAP_DSS_COLOR_NV12:
1322 /* UV is subsampled by 2 vertically*/
1323 orig_height >>= 1;
1324 /* UV is subsampled by 2 horz.*/
1325 orig_width >>= 1;
1326 break;
1327 case OMAP_DSS_COLOR_YUV2:
1328 case OMAP_DSS_COLOR_UYVY:
1329 /*For YUV422 with 90/270 rotation,
1330 *we don't upsample chroma
1331 */
1332 if (rotation == OMAP_DSS_ROT_0 ||
1333 rotation == OMAP_DSS_ROT_180)
1334 /* UV is subsampled by 2 hrz*/
1335 orig_width >>= 1;
1336 /* must use FIR for YUV422 if rotated */
1337 if (rotation != OMAP_DSS_ROT_0)
1338 scale_x = scale_y = true;
1339 break;
1340 default:
1341 BUG();
1342 }
1343
1344 if (out_width != orig_width)
1345 scale_x = true;
1346 if (out_height != orig_height)
1347 scale_y = true;
1348
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001349 dispc_ovl_set_scale_param(plane, orig_width, orig_height,
Amber Jain0d66cbb2011-05-19 19:47:54 +05301350 out_width, out_height, five_taps,
1351 rotation, DISPC_COLOR_COMPONENT_UV);
1352
1353 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES2(plane),
1354 (scale_x || scale_y) ? 1 : 0, 8, 8);
1355 /* set H scaling */
1356 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_x ? 1 : 0, 5, 5);
1357 /* set V scaling */
1358 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), scale_y ? 1 : 0, 6, 6);
Amber Jain0d66cbb2011-05-19 19:47:54 +05301359}
1360
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001361static void dispc_ovl_set_scaling(enum omap_plane plane,
Amber Jain0d66cbb2011-05-19 19:47:54 +05301362 u16 orig_width, u16 orig_height,
1363 u16 out_width, u16 out_height,
1364 bool ilace, bool five_taps,
1365 bool fieldmode, enum omap_color_mode color_mode,
1366 u8 rotation)
1367{
1368 BUG_ON(plane == OMAP_DSS_GFX);
1369
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001370 dispc_ovl_set_scaling_common(plane,
Amber Jain0d66cbb2011-05-19 19:47:54 +05301371 orig_width, orig_height,
1372 out_width, out_height,
1373 ilace, five_taps,
1374 fieldmode, color_mode,
1375 rotation);
1376
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001377 dispc_ovl_set_scaling_uv(plane,
Amber Jain0d66cbb2011-05-19 19:47:54 +05301378 orig_width, orig_height,
1379 out_width, out_height,
1380 ilace, five_taps,
1381 fieldmode, color_mode,
1382 rotation);
1383}
1384
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03001385static void dispc_ovl_set_rotation_attrs(enum omap_plane plane, u8 rotation,
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001386 bool mirroring, enum omap_color_mode color_mode)
1387{
Archit Taneja87a74842011-03-02 11:19:50 +05301388 bool row_repeat = false;
1389 int vidrot = 0;
1390
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001391 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1392 color_mode == OMAP_DSS_COLOR_UYVY) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001393
1394 if (mirroring) {
1395 switch (rotation) {
1396 case OMAP_DSS_ROT_0:
1397 vidrot = 2;
1398 break;
1399 case OMAP_DSS_ROT_90:
1400 vidrot = 1;
1401 break;
1402 case OMAP_DSS_ROT_180:
1403 vidrot = 0;
1404 break;
1405 case OMAP_DSS_ROT_270:
1406 vidrot = 3;
1407 break;
1408 }
1409 } else {
1410 switch (rotation) {
1411 case OMAP_DSS_ROT_0:
1412 vidrot = 0;
1413 break;
1414 case OMAP_DSS_ROT_90:
1415 vidrot = 1;
1416 break;
1417 case OMAP_DSS_ROT_180:
1418 vidrot = 2;
1419 break;
1420 case OMAP_DSS_ROT_270:
1421 vidrot = 3;
1422 break;
1423 }
1424 }
1425
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001426 if (rotation == OMAP_DSS_ROT_90 || rotation == OMAP_DSS_ROT_270)
Archit Taneja87a74842011-03-02 11:19:50 +05301427 row_repeat = true;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001428 else
Archit Taneja87a74842011-03-02 11:19:50 +05301429 row_repeat = false;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001430 }
Archit Taneja87a74842011-03-02 11:19:50 +05301431
Archit Taneja9b372c22011-05-06 11:45:49 +05301432 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), vidrot, 13, 12);
Archit Taneja87a74842011-03-02 11:19:50 +05301433 if (dss_has_feature(FEAT_ROWREPEATENABLE))
Archit Taneja9b372c22011-05-06 11:45:49 +05301434 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane),
1435 row_repeat ? 1 : 0, 18, 18);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001436}
1437
1438static int color_mode_to_bpp(enum omap_color_mode color_mode)
1439{
1440 switch (color_mode) {
1441 case OMAP_DSS_COLOR_CLUT1:
1442 return 1;
1443 case OMAP_DSS_COLOR_CLUT2:
1444 return 2;
1445 case OMAP_DSS_COLOR_CLUT4:
1446 return 4;
1447 case OMAP_DSS_COLOR_CLUT8:
Amber Jainf20e4222011-05-19 19:47:50 +05301448 case OMAP_DSS_COLOR_NV12:
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001449 return 8;
1450 case OMAP_DSS_COLOR_RGB12U:
1451 case OMAP_DSS_COLOR_RGB16:
1452 case OMAP_DSS_COLOR_ARGB16:
1453 case OMAP_DSS_COLOR_YUV2:
1454 case OMAP_DSS_COLOR_UYVY:
Amber Jainf20e4222011-05-19 19:47:50 +05301455 case OMAP_DSS_COLOR_RGBA16:
1456 case OMAP_DSS_COLOR_RGBX16:
1457 case OMAP_DSS_COLOR_ARGB16_1555:
1458 case OMAP_DSS_COLOR_XRGB16_1555:
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001459 return 16;
1460 case OMAP_DSS_COLOR_RGB24P:
1461 return 24;
1462 case OMAP_DSS_COLOR_RGB24U:
1463 case OMAP_DSS_COLOR_ARGB32:
1464 case OMAP_DSS_COLOR_RGBA32:
1465 case OMAP_DSS_COLOR_RGBX32:
1466 return 32;
1467 default:
1468 BUG();
1469 }
1470}
1471
1472static s32 pixinc(int pixels, u8 ps)
1473{
1474 if (pixels == 1)
1475 return 1;
1476 else if (pixels > 1)
1477 return 1 + (pixels - 1) * ps;
1478 else if (pixels < 0)
1479 return 1 - (-pixels + 1) * ps;
1480 else
1481 BUG();
1482}
1483
1484static void calc_vrfb_rotation_offset(u8 rotation, bool mirror,
1485 u16 screen_width,
1486 u16 width, u16 height,
1487 enum omap_color_mode color_mode, bool fieldmode,
1488 unsigned int field_offset,
1489 unsigned *offset0, unsigned *offset1,
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301490 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001491{
1492 u8 ps;
1493
1494 /* FIXME CLUT formats */
1495 switch (color_mode) {
1496 case OMAP_DSS_COLOR_CLUT1:
1497 case OMAP_DSS_COLOR_CLUT2:
1498 case OMAP_DSS_COLOR_CLUT4:
1499 case OMAP_DSS_COLOR_CLUT8:
1500 BUG();
1501 return;
1502 case OMAP_DSS_COLOR_YUV2:
1503 case OMAP_DSS_COLOR_UYVY:
1504 ps = 4;
1505 break;
1506 default:
1507 ps = color_mode_to_bpp(color_mode) / 8;
1508 break;
1509 }
1510
1511 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1512 width, height);
1513
1514 /*
1515 * field 0 = even field = bottom field
1516 * field 1 = odd field = top field
1517 */
1518 switch (rotation + mirror * 4) {
1519 case OMAP_DSS_ROT_0:
1520 case OMAP_DSS_ROT_180:
1521 /*
1522 * If the pixel format is YUV or UYVY divide the width
1523 * of the image by 2 for 0 and 180 degree rotation.
1524 */
1525 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1526 color_mode == OMAP_DSS_COLOR_UYVY)
1527 width = width >> 1;
1528 case OMAP_DSS_ROT_90:
1529 case OMAP_DSS_ROT_270:
1530 *offset1 = 0;
1531 if (field_offset)
1532 *offset0 = field_offset * screen_width * ps;
1533 else
1534 *offset0 = 0;
1535
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301536 *row_inc = pixinc(1 +
1537 (y_predecim * screen_width - x_predecim * width) +
1538 (fieldmode ? screen_width : 0), ps);
1539 *pix_inc = pixinc(x_predecim, ps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001540 break;
1541
1542 case OMAP_DSS_ROT_0 + 4:
1543 case OMAP_DSS_ROT_180 + 4:
1544 /* If the pixel format is YUV or UYVY divide the width
1545 * of the image by 2 for 0 degree and 180 degree
1546 */
1547 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1548 color_mode == OMAP_DSS_COLOR_UYVY)
1549 width = width >> 1;
1550 case OMAP_DSS_ROT_90 + 4:
1551 case OMAP_DSS_ROT_270 + 4:
1552 *offset1 = 0;
1553 if (field_offset)
1554 *offset0 = field_offset * screen_width * ps;
1555 else
1556 *offset0 = 0;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301557 *row_inc = pixinc(1 -
1558 (y_predecim * screen_width + x_predecim * width) -
1559 (fieldmode ? screen_width : 0), ps);
1560 *pix_inc = pixinc(x_predecim, ps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001561 break;
1562
1563 default:
1564 BUG();
1565 }
1566}
1567
1568static void calc_dma_rotation_offset(u8 rotation, bool mirror,
1569 u16 screen_width,
1570 u16 width, u16 height,
1571 enum omap_color_mode color_mode, bool fieldmode,
1572 unsigned int field_offset,
1573 unsigned *offset0, unsigned *offset1,
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301574 s32 *row_inc, s32 *pix_inc, int x_predecim, int y_predecim)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001575{
1576 u8 ps;
1577 u16 fbw, fbh;
1578
1579 /* FIXME CLUT formats */
1580 switch (color_mode) {
1581 case OMAP_DSS_COLOR_CLUT1:
1582 case OMAP_DSS_COLOR_CLUT2:
1583 case OMAP_DSS_COLOR_CLUT4:
1584 case OMAP_DSS_COLOR_CLUT8:
1585 BUG();
1586 return;
1587 default:
1588 ps = color_mode_to_bpp(color_mode) / 8;
1589 break;
1590 }
1591
1592 DSSDBG("calc_rot(%d): scrw %d, %dx%d\n", rotation, screen_width,
1593 width, height);
1594
1595 /* width & height are overlay sizes, convert to fb sizes */
1596
1597 if (rotation == OMAP_DSS_ROT_0 || rotation == OMAP_DSS_ROT_180) {
1598 fbw = width;
1599 fbh = height;
1600 } else {
1601 fbw = height;
1602 fbh = width;
1603 }
1604
1605 /*
1606 * field 0 = even field = bottom field
1607 * field 1 = odd field = top field
1608 */
1609 switch (rotation + mirror * 4) {
1610 case OMAP_DSS_ROT_0:
1611 *offset1 = 0;
1612 if (field_offset)
1613 *offset0 = *offset1 + field_offset * screen_width * ps;
1614 else
1615 *offset0 = *offset1;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301616 *row_inc = pixinc(1 +
1617 (y_predecim * screen_width - fbw * x_predecim) +
1618 (fieldmode ? screen_width : 0), ps);
1619 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1620 color_mode == OMAP_DSS_COLOR_UYVY)
1621 *pix_inc = pixinc(x_predecim, 2 * ps);
1622 else
1623 *pix_inc = pixinc(x_predecim, ps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001624 break;
1625 case OMAP_DSS_ROT_90:
1626 *offset1 = screen_width * (fbh - 1) * ps;
1627 if (field_offset)
1628 *offset0 = *offset1 + field_offset * ps;
1629 else
1630 *offset0 = *offset1;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301631 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) +
1632 y_predecim + (fieldmode ? 1 : 0), ps);
1633 *pix_inc = pixinc(-x_predecim * screen_width, ps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001634 break;
1635 case OMAP_DSS_ROT_180:
1636 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1637 if (field_offset)
1638 *offset0 = *offset1 - field_offset * screen_width * ps;
1639 else
1640 *offset0 = *offset1;
1641 *row_inc = pixinc(-1 -
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301642 (y_predecim * screen_width - fbw * x_predecim) -
1643 (fieldmode ? screen_width : 0), ps);
1644 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1645 color_mode == OMAP_DSS_COLOR_UYVY)
1646 *pix_inc = pixinc(-x_predecim, 2 * ps);
1647 else
1648 *pix_inc = pixinc(-x_predecim, ps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001649 break;
1650 case OMAP_DSS_ROT_270:
1651 *offset1 = (fbw - 1) * ps;
1652 if (field_offset)
1653 *offset0 = *offset1 - field_offset * ps;
1654 else
1655 *offset0 = *offset1;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301656 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) -
1657 y_predecim - (fieldmode ? 1 : 0), ps);
1658 *pix_inc = pixinc(x_predecim * screen_width, ps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001659 break;
1660
1661 /* mirroring */
1662 case OMAP_DSS_ROT_0 + 4:
1663 *offset1 = (fbw - 1) * ps;
1664 if (field_offset)
1665 *offset0 = *offset1 + field_offset * screen_width * ps;
1666 else
1667 *offset0 = *offset1;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301668 *row_inc = pixinc(y_predecim * screen_width * 2 - 1 +
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001669 (fieldmode ? screen_width : 0),
1670 ps);
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301671 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1672 color_mode == OMAP_DSS_COLOR_UYVY)
1673 *pix_inc = pixinc(-x_predecim, 2 * ps);
1674 else
1675 *pix_inc = pixinc(-x_predecim, ps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001676 break;
1677
1678 case OMAP_DSS_ROT_90 + 4:
1679 *offset1 = 0;
1680 if (field_offset)
1681 *offset0 = *offset1 + field_offset * ps;
1682 else
1683 *offset0 = *offset1;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301684 *row_inc = pixinc(-screen_width * (fbh * x_predecim - 1) +
1685 y_predecim + (fieldmode ? 1 : 0),
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001686 ps);
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301687 *pix_inc = pixinc(x_predecim * screen_width, ps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001688 break;
1689
1690 case OMAP_DSS_ROT_180 + 4:
1691 *offset1 = screen_width * (fbh - 1) * ps;
1692 if (field_offset)
1693 *offset0 = *offset1 - field_offset * screen_width * ps;
1694 else
1695 *offset0 = *offset1;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301696 *row_inc = pixinc(1 - y_predecim * screen_width * 2 -
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001697 (fieldmode ? screen_width : 0),
1698 ps);
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301699 if (color_mode == OMAP_DSS_COLOR_YUV2 ||
1700 color_mode == OMAP_DSS_COLOR_UYVY)
1701 *pix_inc = pixinc(x_predecim, 2 * ps);
1702 else
1703 *pix_inc = pixinc(x_predecim, ps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001704 break;
1705
1706 case OMAP_DSS_ROT_270 + 4:
1707 *offset1 = (screen_width * (fbh - 1) + fbw - 1) * ps;
1708 if (field_offset)
1709 *offset0 = *offset1 - field_offset * ps;
1710 else
1711 *offset0 = *offset1;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301712 *row_inc = pixinc(screen_width * (fbh * x_predecim - 1) -
1713 y_predecim - (fieldmode ? 1 : 0),
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001714 ps);
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301715 *pix_inc = pixinc(-x_predecim * screen_width, ps);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001716 break;
1717
1718 default:
1719 BUG();
1720 }
1721}
1722
Chandrabhanu Mahapatra7faa9232012-04-02 20:43:17 +05301723/*
1724 * This function is used to avoid synclosts in OMAP3, because of some
1725 * undocumented horizontal position and timing related limitations.
1726 */
Archit Taneja81ab95b2012-05-08 15:53:20 +05301727static int check_horiz_timing_omap3(enum omap_channel channel,
1728 const struct omap_video_timings *t, u16 pos_x,
Chandrabhanu Mahapatra7faa9232012-04-02 20:43:17 +05301729 u16 width, u16 height, u16 out_width, u16 out_height)
1730{
1731 int DS = DIV_ROUND_UP(height, out_height);
Chandrabhanu Mahapatra7faa9232012-04-02 20:43:17 +05301732 unsigned long nonactive, lclk, pclk;
1733 static const u8 limits[3] = { 8, 10, 20 };
1734 u64 val, blank;
1735 int i;
1736
Archit Taneja81ab95b2012-05-08 15:53:20 +05301737 nonactive = t->x_res + t->hfp + t->hsw + t->hbp - out_width;
Chandrabhanu Mahapatra7faa9232012-04-02 20:43:17 +05301738 pclk = dispc_mgr_pclk_rate(channel);
1739 if (dispc_mgr_is_lcd(channel))
1740 lclk = dispc_mgr_lclk_rate(channel);
1741 else
1742 lclk = dispc_fclk_rate();
1743
1744 i = 0;
1745 if (out_height < height)
1746 i++;
1747 if (out_width < width)
1748 i++;
Archit Taneja81ab95b2012-05-08 15:53:20 +05301749 blank = div_u64((u64)(t->hbp + t->hsw + t->hfp) * lclk, pclk);
Chandrabhanu Mahapatra7faa9232012-04-02 20:43:17 +05301750 DSSDBG("blanking period + ppl = %llu (limit = %u)\n", blank, limits[i]);
1751 if (blank <= limits[i])
1752 return -EINVAL;
1753
1754 /*
1755 * Pixel data should be prepared before visible display point starts.
1756 * So, atleast DS-2 lines must have already been fetched by DISPC
1757 * during nonactive - pos_x period.
1758 */
1759 val = div_u64((u64)(nonactive - pos_x) * lclk, pclk);
1760 DSSDBG("(nonactive - pos_x) * pcd = %llu max(0, DS - 2) * width = %d\n",
1761 val, max(0, DS - 2) * width);
1762 if (val < max(0, DS - 2) * width)
1763 return -EINVAL;
1764
1765 /*
1766 * All lines need to be refilled during the nonactive period of which
1767 * only one line can be loaded during the active period. So, atleast
1768 * DS - 1 lines should be loaded during nonactive period.
1769 */
1770 val = div_u64((u64)nonactive * lclk, pclk);
1771 DSSDBG("nonactive * pcd = %llu, max(0, DS - 1) * width = %d\n",
1772 val, max(0, DS - 1) * width);
1773 if (val < max(0, DS - 1) * width)
1774 return -EINVAL;
1775
1776 return 0;
1777}
1778
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301779static unsigned long calc_core_clk_five_taps(enum omap_channel channel,
Archit Taneja81ab95b2012-05-08 15:53:20 +05301780 const struct omap_video_timings *mgr_timings, u16 width,
1781 u16 height, u16 out_width, u16 out_height,
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00001782 enum omap_color_mode color_mode)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001783{
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301784 u32 core_clk = 0;
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03001785 u64 tmp, pclk = dispc_mgr_pclk_rate(channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001786
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301787 if (height <= out_height && width <= out_width)
1788 return (unsigned long) pclk;
1789
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001790 if (height > out_height) {
Archit Taneja81ab95b2012-05-08 15:53:20 +05301791 unsigned int ppl = mgr_timings->x_res;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001792
1793 tmp = pclk * height * out_width;
1794 do_div(tmp, 2 * out_height * ppl);
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301795 core_clk = tmp;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001796
Ville Syrjälä2d9c5592010-01-08 11:56:41 +02001797 if (height > 2 * out_height) {
1798 if (ppl == out_width)
1799 return 0;
1800
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001801 tmp = pclk * (height - 2 * out_height) * out_width;
1802 do_div(tmp, 2 * out_height * (ppl - out_width));
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301803 core_clk = max_t(u32, core_clk, tmp);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001804 }
1805 }
1806
1807 if (width > out_width) {
1808 tmp = pclk * width;
1809 do_div(tmp, out_width);
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301810 core_clk = max_t(u32, core_clk, tmp);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001811
1812 if (color_mode == OMAP_DSS_COLOR_RGB24U)
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301813 core_clk <<= 1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001814 }
1815
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301816 return core_clk;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001817}
1818
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301819static unsigned long calc_core_clk(enum omap_channel channel, u16 width,
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00001820 u16 height, u16 out_width, u16 out_height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001821{
1822 unsigned int hf, vf;
Archit Taneja79ee89c2012-01-30 10:54:17 +05301823 unsigned long pclk = dispc_mgr_pclk_rate(channel);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001824
1825 /*
1826 * FIXME how to determine the 'A' factor
1827 * for the no downscaling case ?
1828 */
1829
1830 if (width > 3 * out_width)
1831 hf = 4;
1832 else if (width > 2 * out_width)
1833 hf = 3;
1834 else if (width > out_width)
1835 hf = 2;
1836 else
1837 hf = 1;
1838
1839 if (height > out_height)
1840 vf = 2;
1841 else
1842 vf = 1;
1843
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301844 if (cpu_is_omap24xx()) {
1845 if (vf > 1 && hf > 1)
Archit Taneja79ee89c2012-01-30 10:54:17 +05301846 return pclk * 4;
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301847 else
Archit Taneja79ee89c2012-01-30 10:54:17 +05301848 return pclk * 2;
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301849 } else if (cpu_is_omap34xx()) {
Archit Taneja79ee89c2012-01-30 10:54:17 +05301850 return pclk * vf * hf;
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301851 } else {
Archit Taneja79ee89c2012-01-30 10:54:17 +05301852 if (hf > 1)
1853 return DIV_ROUND_UP(pclk, out_width) * width;
1854 else
1855 return pclk;
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301856 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02001857}
1858
Archit Taneja79ad75f2011-09-08 13:15:11 +05301859static int dispc_ovl_calc_scaling(enum omap_plane plane,
Archit Taneja81ab95b2012-05-08 15:53:20 +05301860 enum omap_channel channel,
1861 const struct omap_video_timings *mgr_timings,
1862 u16 width, u16 height, u16 out_width, u16 out_height,
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301863 enum omap_color_mode color_mode, bool *five_taps,
Chandrabhanu Mahapatra7faa9232012-04-02 20:43:17 +05301864 int *x_predecim, int *y_predecim, u16 pos_x)
Archit Taneja79ad75f2011-09-08 13:15:11 +05301865{
1866 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
Archit Taneja0373cac2011-09-08 13:25:17 +05301867 const int maxdownscale = dss_feat_get_param_max(FEAT_PARAM_DOWNSCALE);
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301868 const int maxsinglelinewidth =
1869 dss_feat_get_param_max(FEAT_PARAM_LINEWIDTH);
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301870 const int max_decim_limit = 16;
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301871 unsigned long core_clk = 0;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301872 int decim_x, decim_y, error, min_factor;
1873 u16 in_width, in_height, in_width_max = 0;
Archit Taneja79ad75f2011-09-08 13:15:11 +05301874
Tomi Valkeinenf95cb5e2011-11-01 10:50:45 +02001875 if (width == out_width && height == out_height)
1876 return 0;
1877
1878 if ((ovl->caps & OMAP_DSS_OVL_CAP_SCALE) == 0)
1879 return -EINVAL;
Archit Taneja79ad75f2011-09-08 13:15:11 +05301880
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301881 *x_predecim = max_decim_limit;
1882 *y_predecim = max_decim_limit;
1883
1884 if (color_mode == OMAP_DSS_COLOR_CLUT1 ||
1885 color_mode == OMAP_DSS_COLOR_CLUT2 ||
1886 color_mode == OMAP_DSS_COLOR_CLUT4 ||
1887 color_mode == OMAP_DSS_COLOR_CLUT8) {
1888 *x_predecim = 1;
1889 *y_predecim = 1;
1890 *five_taps = false;
1891 return 0;
1892 }
1893
1894 decim_x = DIV_ROUND_UP(DIV_ROUND_UP(width, out_width), maxdownscale);
1895 decim_y = DIV_ROUND_UP(DIV_ROUND_UP(height, out_height), maxdownscale);
1896
1897 min_factor = min(decim_x, decim_y);
1898
1899 if (decim_x > *x_predecim || out_width > width * 8)
Archit Taneja79ad75f2011-09-08 13:15:11 +05301900 return -EINVAL;
1901
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301902 if (decim_y > *y_predecim || out_height > height * 8)
Archit Taneja79ad75f2011-09-08 13:15:11 +05301903 return -EINVAL;
1904
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301905 if (cpu_is_omap24xx()) {
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301906 *five_taps = false;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301907
1908 do {
1909 in_height = DIV_ROUND_UP(height, decim_y);
1910 in_width = DIV_ROUND_UP(width, decim_x);
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301911 core_clk = calc_core_clk(channel, in_width, in_height,
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301912 out_width, out_height);
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301913 error = (in_width > maxsinglelinewidth || !core_clk ||
1914 core_clk > dispc_core_clk_rate());
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301915 if (error) {
1916 if (decim_x == decim_y) {
1917 decim_x = min_factor;
1918 decim_y++;
1919 } else {
1920 swap(decim_x, decim_y);
1921 if (decim_x < decim_y)
1922 decim_x++;
1923 }
1924 }
1925 } while (decim_x <= *x_predecim && decim_y <= *y_predecim &&
1926 error);
1927
1928 if (in_width > maxsinglelinewidth) {
1929 DSSERR("Cannot scale max input width exceeded");
1930 return -EINVAL;
1931 }
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301932 } else if (cpu_is_omap34xx()) {
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301933
1934 do {
1935 in_height = DIV_ROUND_UP(height, decim_y);
1936 in_width = DIV_ROUND_UP(width, decim_x);
Archit Taneja81ab95b2012-05-08 15:53:20 +05301937 core_clk = calc_core_clk_five_taps(channel, mgr_timings,
1938 in_width, in_height, out_width, out_height,
1939 color_mode);
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301940
Archit Taneja81ab95b2012-05-08 15:53:20 +05301941 error = check_horiz_timing_omap3(channel, mgr_timings,
1942 pos_x, in_width, in_height, out_width,
1943 out_height);
Chandrabhanu Mahapatra7faa9232012-04-02 20:43:17 +05301944
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301945 if (in_width > maxsinglelinewidth)
1946 if (in_height > out_height &&
1947 in_height < out_height * 2)
1948 *five_taps = false;
1949 if (!*five_taps)
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301950 core_clk = calc_core_clk(channel, in_width,
1951 in_height, out_width, out_height);
Chandrabhanu Mahapatra7faa9232012-04-02 20:43:17 +05301952 error = (error || in_width > maxsinglelinewidth * 2 ||
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301953 (in_width > maxsinglelinewidth && *five_taps) ||
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301954 !core_clk || core_clk > dispc_core_clk_rate());
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301955 if (error) {
1956 if (decim_x == decim_y) {
1957 decim_x = min_factor;
1958 decim_y++;
1959 } else {
1960 swap(decim_x, decim_y);
1961 if (decim_x < decim_y)
1962 decim_x++;
1963 }
1964 }
1965 } while (decim_x <= *x_predecim && decim_y <= *y_predecim
1966 && error);
1967
Archit Taneja81ab95b2012-05-08 15:53:20 +05301968 if (check_horiz_timing_omap3(channel, mgr_timings, pos_x, width,
1969 height, out_width, out_height)){
Chandrabhanu Mahapatra7faa9232012-04-02 20:43:17 +05301970 DSSERR("horizontal timing too tight\n");
1971 return -EINVAL;
1972 }
1973
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301974 if (in_width > (maxsinglelinewidth * 2)) {
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301975 DSSERR("Cannot setup scaling");
1976 DSSERR("width exceeds maximum width possible");
1977 return -EINVAL;
1978 }
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301979
1980 if (in_width > maxsinglelinewidth && *five_taps) {
1981 DSSERR("cannot setup scaling with five taps");
1982 return -EINVAL;
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301983 }
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05301984 } else {
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301985 int decim_x_min = decim_x;
1986 in_height = DIV_ROUND_UP(height, decim_y);
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05301987 in_width_max = dispc_core_clk_rate() /
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05301988 DIV_ROUND_UP(dispc_mgr_pclk_rate(channel),
1989 out_width);
1990 decim_x = DIV_ROUND_UP(width, in_width_max);
1991
1992 decim_x = decim_x > decim_x_min ? decim_x : decim_x_min;
1993 if (decim_x > *x_predecim)
1994 return -EINVAL;
1995
1996 do {
1997 in_width = DIV_ROUND_UP(width, decim_x);
1998 } while (decim_x <= *x_predecim &&
1999 in_width > maxsinglelinewidth && decim_x++);
2000
2001 if (in_width > maxsinglelinewidth) {
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05302002 DSSERR("Cannot scale width exceeds max line width");
2003 return -EINVAL;
2004 }
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302005
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05302006 core_clk = calc_core_clk(channel, in_width, in_height,
2007 out_width, out_height);
Archit Taneja79ad75f2011-09-08 13:15:11 +05302008 }
2009
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05302010 DSSDBG("required core clk rate = %lu Hz\n", core_clk);
2011 DSSDBG("current core clk rate = %lu Hz\n", dispc_core_clk_rate());
Archit Taneja79ad75f2011-09-08 13:15:11 +05302012
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05302013 if (!core_clk || core_clk > dispc_core_clk_rate()) {
Archit Taneja79ad75f2011-09-08 13:15:11 +05302014 DSSERR("failed to set up scaling, "
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05302015 "required core clk rate = %lu Hz, "
2016 "current core clk rate = %lu Hz\n",
2017 core_clk, dispc_core_clk_rate());
Archit Taneja79ad75f2011-09-08 13:15:11 +05302018 return -EINVAL;
2019 }
2020
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302021 *x_predecim = decim_x;
2022 *y_predecim = decim_y;
Archit Taneja79ad75f2011-09-08 13:15:11 +05302023 return 0;
2024}
2025
Archit Tanejaa4273b72011-09-14 11:10:10 +05302026int dispc_ovl_setup(enum omap_plane plane, struct omap_overlay_info *oi,
Archit Taneja81ab95b2012-05-08 15:53:20 +05302027 bool ilace, bool replication,
2028 const struct omap_video_timings *mgr_timings)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002029{
Archit Taneja79ad75f2011-09-08 13:15:11 +05302030 struct omap_overlay *ovl = omap_dss_get_overlay(plane);
Chandrabhanu Mahapatra7282f1b2011-12-19 14:03:56 +05302031 bool five_taps = true;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002032 bool fieldmode = 0;
Archit Taneja79ad75f2011-09-08 13:15:11 +05302033 int r, cconv = 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002034 unsigned offset0, offset1;
2035 s32 row_inc;
2036 s32 pix_inc;
Archit Tanejaa4273b72011-09-14 11:10:10 +05302037 u16 frame_height = oi->height;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002038 unsigned int field_offset = 0;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302039 u16 in_height = oi->height;
2040 u16 in_width = oi->width;
2041 u16 out_width, out_height;
Tomi Valkeinen2cc5d1a2011-11-03 17:03:44 +02002042 enum omap_channel channel;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302043 int x_predecim = 1, y_predecim = 1;
Tomi Valkeinen2cc5d1a2011-11-03 17:03:44 +02002044
2045 channel = dispc_ovl_get_channel_out(plane);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002046
Archit Tanejaa4273b72011-09-14 11:10:10 +05302047 DSSDBG("dispc_ovl_setup %d, pa %x, pa_uv %x, sw %d, %d,%d, %dx%d -> "
Tomi Valkeinenf38545d2011-11-03 17:00:07 +02002048 "%dx%d, cmode %x, rot %d, mir %d, ilace %d chan %d repl %d\n",
2049 plane, oi->paddr, oi->p_uv_addr,
Archit Tanejac3d925292011-09-14 11:52:54 +05302050 oi->screen_width, oi->pos_x, oi->pos_y, oi->width, oi->height,
2051 oi->out_width, oi->out_height, oi->color_mode, oi->rotation,
Tomi Valkeinenf38545d2011-11-03 17:00:07 +02002052 oi->mirror, ilace, channel, replication);
Tomi Valkeinene6d80f92011-05-19 14:12:26 +03002053
Archit Tanejaa4273b72011-09-14 11:10:10 +05302054 if (oi->paddr == 0)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002055 return -EINVAL;
2056
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302057 out_width = oi->out_width == 0 ? oi->width : oi->out_width;
2058 out_height = oi->out_height == 0 ? oi->height : oi->out_height;
Tomi Valkeinencf073662011-11-03 16:08:27 +02002059
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302060 if (ilace && oi->height == out_height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002061 fieldmode = 1;
2062
2063 if (ilace) {
2064 if (fieldmode)
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302065 in_height /= 2;
Archit Tanejaa4273b72011-09-14 11:10:10 +05302066 oi->pos_y /= 2;
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302067 out_height /= 2;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002068
2069 DSSDBG("adjusting for ilace: height %d, pos_y %d, "
2070 "out_height %d\n",
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302071 in_height, oi->pos_y, out_height);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002072 }
2073
Archit Tanejaa4273b72011-09-14 11:10:10 +05302074 if (!dss_feat_color_mode_supported(plane, oi->color_mode))
Archit Taneja8dad2ab2010-11-25 17:58:10 +05302075 return -EINVAL;
2076
Archit Taneja81ab95b2012-05-08 15:53:20 +05302077 r = dispc_ovl_calc_scaling(plane, channel, mgr_timings, in_width,
2078 in_height, out_width, out_height, oi->color_mode,
2079 &five_taps, &x_predecim, &y_predecim, oi->pos_x);
Archit Taneja79ad75f2011-09-08 13:15:11 +05302080 if (r)
2081 return r;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002082
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302083 in_width = DIV_ROUND_UP(in_width, x_predecim);
2084 in_height = DIV_ROUND_UP(in_height, y_predecim);
2085
Archit Taneja79ad75f2011-09-08 13:15:11 +05302086 if (oi->color_mode == OMAP_DSS_COLOR_YUV2 ||
2087 oi->color_mode == OMAP_DSS_COLOR_UYVY ||
2088 oi->color_mode == OMAP_DSS_COLOR_NV12)
2089 cconv = 1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002090
2091 if (ilace && !fieldmode) {
2092 /*
2093 * when downscaling the bottom field may have to start several
2094 * source lines below the top field. Unfortunately ACCUI
2095 * registers will only hold the fractional part of the offset
2096 * so the integer part must be added to the base address of the
2097 * bottom field.
2098 */
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302099 if (!in_height || in_height == out_height)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002100 field_offset = 0;
2101 else
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302102 field_offset = in_height / out_height / 2;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002103 }
2104
2105 /* Fields are independent but interleaved in memory. */
2106 if (fieldmode)
2107 field_offset = 1;
2108
Archit Tanejaa4273b72011-09-14 11:10:10 +05302109 if (oi->rotation_type == OMAP_DSS_ROT_DMA)
2110 calc_dma_rotation_offset(oi->rotation, oi->mirror,
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302111 oi->screen_width, in_width, frame_height,
Archit Tanejaa4273b72011-09-14 11:10:10 +05302112 oi->color_mode, fieldmode, field_offset,
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302113 &offset0, &offset1, &row_inc, &pix_inc,
2114 x_predecim, y_predecim);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002115 else
Archit Tanejaa4273b72011-09-14 11:10:10 +05302116 calc_vrfb_rotation_offset(oi->rotation, oi->mirror,
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302117 oi->screen_width, in_width, frame_height,
Archit Tanejaa4273b72011-09-14 11:10:10 +05302118 oi->color_mode, fieldmode, field_offset,
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302119 &offset0, &offset1, &row_inc, &pix_inc,
2120 x_predecim, y_predecim);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002121
2122 DSSDBG("offset0 %u, offset1 %u, row_inc %d, pix_inc %d\n",
2123 offset0, offset1, row_inc, pix_inc);
2124
Archit Tanejaa4273b72011-09-14 11:10:10 +05302125 dispc_ovl_set_color_mode(plane, oi->color_mode);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002126
Archit Tanejaa4273b72011-09-14 11:10:10 +05302127 dispc_ovl_set_ba0(plane, oi->paddr + offset0);
2128 dispc_ovl_set_ba1(plane, oi->paddr + offset1);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002129
Archit Tanejaa4273b72011-09-14 11:10:10 +05302130 if (OMAP_DSS_COLOR_NV12 == oi->color_mode) {
2131 dispc_ovl_set_ba0_uv(plane, oi->p_uv_addr + offset0);
2132 dispc_ovl_set_ba1_uv(plane, oi->p_uv_addr + offset1);
Amber Jain0d66cbb2011-05-19 19:47:54 +05302133 }
2134
2135
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03002136 dispc_ovl_set_row_inc(plane, row_inc);
2137 dispc_ovl_set_pix_inc(plane, pix_inc);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002138
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302139 DSSDBG("%d,%d %dx%d -> %dx%d\n", oi->pos_x, oi->pos_y, in_width,
2140 in_height, out_width, out_height);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002141
Archit Tanejaa4273b72011-09-14 11:10:10 +05302142 dispc_ovl_set_pos(plane, oi->pos_x, oi->pos_y);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002143
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302144 dispc_ovl_set_pic_size(plane, in_width, in_height);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002145
Archit Taneja79ad75f2011-09-08 13:15:11 +05302146 if (ovl->caps & OMAP_DSS_OVL_CAP_SCALE) {
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302147 dispc_ovl_set_scaling(plane, in_width, in_height, out_width,
2148 out_height, ilace, five_taps, fieldmode,
Archit Tanejaa4273b72011-09-14 11:10:10 +05302149 oi->color_mode, oi->rotation);
Chandrabhanu Mahapatraaed74b552012-04-02 20:43:16 +05302150 dispc_ovl_set_vid_size(plane, out_width, out_height);
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03002151 dispc_ovl_set_vid_color_conv(plane, cconv);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002152 }
2153
Archit Tanejaa4273b72011-09-14 11:10:10 +05302154 dispc_ovl_set_rotation_attrs(plane, oi->rotation, oi->mirror,
2155 oi->color_mode);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002156
Archit Taneja54128702011-09-08 11:29:17 +05302157 dispc_ovl_set_zorder(plane, oi->zorder);
Archit Tanejaa4273b72011-09-14 11:10:10 +05302158 dispc_ovl_set_pre_mult_alpha(plane, oi->pre_mult_alpha);
2159 dispc_ovl_setup_global_alpha(plane, oi->global_alpha);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002160
Archit Tanejac3d925292011-09-14 11:52:54 +05302161 dispc_ovl_enable_replication(plane, replication);
Archit Tanejac3d925292011-09-14 11:52:54 +05302162
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002163 return 0;
2164}
2165
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03002166int dispc_ovl_enable(enum omap_plane plane, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002167{
Tomi Valkeinene6d80f92011-05-19 14:12:26 +03002168 DSSDBG("dispc_enable_plane %d, %d\n", plane, enable);
2169
Archit Taneja9b372c22011-05-06 11:45:49 +05302170 REG_FLD_MOD(DISPC_OVL_ATTRIBUTES(plane), enable ? 1 : 0, 0, 0);
Tomi Valkeinene6d80f92011-05-19 14:12:26 +03002171
2172 return 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002173}
2174
2175static void dispc_disable_isr(void *data, u32 mask)
2176{
2177 struct completion *compl = data;
2178 complete(compl);
2179}
2180
Sumit Semwal2a205f32010-12-02 11:27:12 +00002181static void _enable_lcd_out(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002182{
Tomi Valkeinenb6a44e72011-10-12 10:17:02 +03002183 if (channel == OMAP_DSS_CHANNEL_LCD2) {
Sumit Semwal2a205f32010-12-02 11:27:12 +00002184 REG_FLD_MOD(DISPC_CONTROL2, enable ? 1 : 0, 0, 0);
Tomi Valkeinenb6a44e72011-10-12 10:17:02 +03002185 /* flush posted write */
2186 dispc_read_reg(DISPC_CONTROL2);
2187 } else {
Sumit Semwal2a205f32010-12-02 11:27:12 +00002188 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 0, 0);
Tomi Valkeinenb6a44e72011-10-12 10:17:02 +03002189 dispc_read_reg(DISPC_CONTROL);
2190 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002191}
2192
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002193static void dispc_mgr_enable_lcd_out(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002194{
2195 struct completion frame_done_completion;
2196 bool is_on;
2197 int r;
Sumit Semwal2a205f32010-12-02 11:27:12 +00002198 u32 irq;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002199
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002200 /* When we disable LCD output, we need to wait until frame is done.
2201 * Otherwise the DSS is still working, and turning off the clocks
2202 * prevents DSS from going to OFF mode */
Sumit Semwal2a205f32010-12-02 11:27:12 +00002203 is_on = channel == OMAP_DSS_CHANNEL_LCD2 ?
2204 REG_GET(DISPC_CONTROL2, 0, 0) :
2205 REG_GET(DISPC_CONTROL, 0, 0);
2206
2207 irq = channel == OMAP_DSS_CHANNEL_LCD2 ? DISPC_IRQ_FRAMEDONE2 :
2208 DISPC_IRQ_FRAMEDONE;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002209
2210 if (!enable && is_on) {
2211 init_completion(&frame_done_completion);
2212
2213 r = omap_dispc_register_isr(dispc_disable_isr,
Sumit Semwal2a205f32010-12-02 11:27:12 +00002214 &frame_done_completion, irq);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002215
2216 if (r)
2217 DSSERR("failed to register FRAMEDONE isr\n");
2218 }
2219
Sumit Semwal2a205f32010-12-02 11:27:12 +00002220 _enable_lcd_out(channel, enable);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002221
2222 if (!enable && is_on) {
2223 if (!wait_for_completion_timeout(&frame_done_completion,
2224 msecs_to_jiffies(100)))
2225 DSSERR("timeout waiting for FRAME DONE\n");
2226
2227 r = omap_dispc_unregister_isr(dispc_disable_isr,
Sumit Semwal2a205f32010-12-02 11:27:12 +00002228 &frame_done_completion, irq);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002229
2230 if (r)
2231 DSSERR("failed to unregister FRAMEDONE isr\n");
2232 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002233}
2234
2235static void _enable_digit_out(bool enable)
2236{
2237 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 1, 1);
Tomi Valkeinenb6a44e72011-10-12 10:17:02 +03002238 /* flush posted write */
2239 dispc_read_reg(DISPC_CONTROL);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002240}
2241
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002242static void dispc_mgr_enable_digit_out(bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002243{
2244 struct completion frame_done_completion;
Tomi Valkeinene82b0902011-08-31 14:42:49 +03002245 enum dss_hdmi_venc_clk_source_select src;
2246 int r, i;
2247 u32 irq_mask;
2248 int num_irqs;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002249
Tomi Valkeinene6d80f92011-05-19 14:12:26 +03002250 if (REG_GET(DISPC_CONTROL, 1, 1) == enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002251 return;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002252
Tomi Valkeinene82b0902011-08-31 14:42:49 +03002253 src = dss_get_hdmi_venc_clk_source();
2254
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002255 if (enable) {
2256 unsigned long flags;
2257 /* When we enable digit output, we'll get an extra digit
2258 * sync lost interrupt, that we need to ignore */
2259 spin_lock_irqsave(&dispc.irq_lock, flags);
2260 dispc.irq_error_mask &= ~DISPC_IRQ_SYNC_LOST_DIGIT;
2261 _omap_dispc_set_irqs();
2262 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2263 }
2264
2265 /* When we disable digit output, we need to wait until fields are done.
2266 * Otherwise the DSS is still working, and turning off the clocks
2267 * prevents DSS from going to OFF mode. And when enabling, we need to
2268 * wait for the extra sync losts */
2269 init_completion(&frame_done_completion);
2270
Tomi Valkeinene82b0902011-08-31 14:42:49 +03002271 if (src == DSS_HDMI_M_PCLK && enable == false) {
2272 irq_mask = DISPC_IRQ_FRAMEDONETV;
2273 num_irqs = 1;
2274 } else {
2275 irq_mask = DISPC_IRQ_EVSYNC_EVEN | DISPC_IRQ_EVSYNC_ODD;
2276 /* XXX I understand from TRM that we should only wait for the
2277 * current field to complete. But it seems we have to wait for
2278 * both fields */
2279 num_irqs = 2;
2280 }
2281
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002282 r = omap_dispc_register_isr(dispc_disable_isr, &frame_done_completion,
Tomi Valkeinene82b0902011-08-31 14:42:49 +03002283 irq_mask);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002284 if (r)
Tomi Valkeinene82b0902011-08-31 14:42:49 +03002285 DSSERR("failed to register %x isr\n", irq_mask);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002286
2287 _enable_digit_out(enable);
2288
Tomi Valkeinene82b0902011-08-31 14:42:49 +03002289 for (i = 0; i < num_irqs; ++i) {
2290 if (!wait_for_completion_timeout(&frame_done_completion,
2291 msecs_to_jiffies(100)))
2292 DSSERR("timeout waiting for digit out to %s\n",
2293 enable ? "start" : "stop");
2294 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002295
Tomi Valkeinene82b0902011-08-31 14:42:49 +03002296 r = omap_dispc_unregister_isr(dispc_disable_isr, &frame_done_completion,
2297 irq_mask);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002298 if (r)
Tomi Valkeinene82b0902011-08-31 14:42:49 +03002299 DSSERR("failed to unregister %x isr\n", irq_mask);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002300
2301 if (enable) {
2302 unsigned long flags;
2303 spin_lock_irqsave(&dispc.irq_lock, flags);
Tomi Valkeinene82b0902011-08-31 14:42:49 +03002304 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST_DIGIT;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002305 dispc_write_reg(DISPC_IRQSTATUS, DISPC_IRQ_SYNC_LOST_DIGIT);
2306 _omap_dispc_set_irqs();
2307 spin_unlock_irqrestore(&dispc.irq_lock, flags);
2308 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002309}
2310
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002311bool dispc_mgr_is_enabled(enum omap_channel channel)
Tomi Valkeinena2faee82010-01-08 17:14:53 +02002312{
2313 if (channel == OMAP_DSS_CHANNEL_LCD)
2314 return !!REG_GET(DISPC_CONTROL, 0, 0);
2315 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
2316 return !!REG_GET(DISPC_CONTROL, 1, 1);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002317 else if (channel == OMAP_DSS_CHANNEL_LCD2)
2318 return !!REG_GET(DISPC_CONTROL2, 0, 0);
Tomi Valkeinena2faee82010-01-08 17:14:53 +02002319 else
2320 BUG();
2321}
2322
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002323void dispc_mgr_enable(enum omap_channel channel, bool enable)
Tomi Valkeinena2faee82010-01-08 17:14:53 +02002324{
Archit Tanejadac57a02011-09-08 12:30:19 +05302325 if (dispc_mgr_is_lcd(channel))
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002326 dispc_mgr_enable_lcd_out(channel, enable);
Tomi Valkeinena2faee82010-01-08 17:14:53 +02002327 else if (channel == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002328 dispc_mgr_enable_digit_out(enable);
Tomi Valkeinena2faee82010-01-08 17:14:53 +02002329 else
2330 BUG();
2331}
2332
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002333void dispc_lcd_enable_signal_polarity(bool act_high)
2334{
Archit Taneja6ced40b2010-12-02 11:27:13 +00002335 if (!dss_has_feature(FEAT_LCDENABLEPOL))
2336 return;
2337
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002338 REG_FLD_MOD(DISPC_CONTROL, act_high ? 1 : 0, 29, 29);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002339}
2340
2341void dispc_lcd_enable_signal(bool enable)
2342{
Archit Taneja6ced40b2010-12-02 11:27:13 +00002343 if (!dss_has_feature(FEAT_LCDENABLESIGNAL))
2344 return;
2345
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002346 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 28, 28);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002347}
2348
2349void dispc_pck_free_enable(bool enable)
2350{
Archit Taneja6ced40b2010-12-02 11:27:13 +00002351 if (!dss_has_feature(FEAT_PCKFREEENABLE))
2352 return;
2353
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002354 REG_FLD_MOD(DISPC_CONTROL, enable ? 1 : 0, 27, 27);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002355}
2356
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002357void dispc_mgr_enable_fifohandcheck(enum omap_channel channel, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002358{
Sumit Semwal2a205f32010-12-02 11:27:12 +00002359 if (channel == OMAP_DSS_CHANNEL_LCD2)
2360 REG_FLD_MOD(DISPC_CONFIG2, enable ? 1 : 0, 16, 16);
2361 else
2362 REG_FLD_MOD(DISPC_CONFIG, enable ? 1 : 0, 16, 16);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002363}
2364
2365
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002366void dispc_mgr_set_lcd_display_type(enum omap_channel channel,
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002367 enum omap_lcd_display_type type)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002368{
2369 int mode;
2370
2371 switch (type) {
2372 case OMAP_DSS_LCD_DISPLAY_STN:
2373 mode = 0;
2374 break;
2375
2376 case OMAP_DSS_LCD_DISPLAY_TFT:
2377 mode = 1;
2378 break;
2379
2380 default:
2381 BUG();
2382 return;
2383 }
2384
Sumit Semwal2a205f32010-12-02 11:27:12 +00002385 if (channel == OMAP_DSS_CHANNEL_LCD2)
2386 REG_FLD_MOD(DISPC_CONTROL2, mode, 3, 3);
2387 else
2388 REG_FLD_MOD(DISPC_CONTROL, mode, 3, 3);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002389}
2390
2391void dispc_set_loadmode(enum omap_dss_load_mode mode)
2392{
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002393 REG_FLD_MOD(DISPC_CONFIG, mode, 2, 1);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002394}
2395
2396
Tomi Valkeinenc64dca42011-11-04 18:14:20 +02002397static void dispc_mgr_set_default_color(enum omap_channel channel, u32 color)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002398{
Sumit Semwal8613b002010-12-02 11:27:09 +00002399 dispc_write_reg(DISPC_DEFAULT_COLOR(channel), color);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002400}
2401
Tomi Valkeinenc64dca42011-11-04 18:14:20 +02002402static void dispc_mgr_set_trans_key(enum omap_channel ch,
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002403 enum omap_dss_trans_key_type type,
2404 u32 trans_key)
2405{
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002406 if (ch == OMAP_DSS_CHANNEL_LCD)
2407 REG_FLD_MOD(DISPC_CONFIG, type, 11, 11);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002408 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002409 REG_FLD_MOD(DISPC_CONFIG, type, 13, 13);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002410 else /* OMAP_DSS_CHANNEL_LCD2 */
2411 REG_FLD_MOD(DISPC_CONFIG2, type, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002412
Sumit Semwal8613b002010-12-02 11:27:09 +00002413 dispc_write_reg(DISPC_TRANS_COLOR(ch), trans_key);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002414}
2415
Tomi Valkeinenc64dca42011-11-04 18:14:20 +02002416static void dispc_mgr_enable_trans_key(enum omap_channel ch, bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002417{
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002418 if (ch == OMAP_DSS_CHANNEL_LCD)
2419 REG_FLD_MOD(DISPC_CONFIG, enable, 10, 10);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002420 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002421 REG_FLD_MOD(DISPC_CONFIG, enable, 12, 12);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002422 else /* OMAP_DSS_CHANNEL_LCD2 */
2423 REG_FLD_MOD(DISPC_CONFIG2, enable, 10, 10);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002424}
Archit Taneja11354dd2011-09-26 11:47:29 +05302425
Tomi Valkeinenc64dca42011-11-04 18:14:20 +02002426static void dispc_mgr_enable_alpha_fixed_zorder(enum omap_channel ch,
2427 bool enable)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002428{
Archit Taneja11354dd2011-09-26 11:47:29 +05302429 if (!dss_has_feature(FEAT_ALPHA_FIXED_ZORDER))
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002430 return;
2431
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002432 if (ch == OMAP_DSS_CHANNEL_LCD)
2433 REG_FLD_MOD(DISPC_CONFIG, enable, 18, 18);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002434 else if (ch == OMAP_DSS_CHANNEL_DIGIT)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002435 REG_FLD_MOD(DISPC_CONFIG, enable, 19, 19);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002436}
Archit Taneja11354dd2011-09-26 11:47:29 +05302437
Tomi Valkeinenc64dca42011-11-04 18:14:20 +02002438void dispc_mgr_setup(enum omap_channel channel,
2439 struct omap_overlay_manager_info *info)
2440{
2441 dispc_mgr_set_default_color(channel, info->default_color);
2442 dispc_mgr_set_trans_key(channel, info->trans_key_type, info->trans_key);
2443 dispc_mgr_enable_trans_key(channel, info->trans_enabled);
2444 dispc_mgr_enable_alpha_fixed_zorder(channel,
2445 info->partial_alpha_enabled);
2446 if (dss_has_feature(FEAT_CPR)) {
2447 dispc_mgr_enable_cpr(channel, info->cpr_enable);
2448 dispc_mgr_set_cpr_coef(channel, &info->cpr_coefs);
2449 }
2450}
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002451
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002452void dispc_mgr_set_tft_data_lines(enum omap_channel channel, u8 data_lines)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002453{
2454 int code;
2455
2456 switch (data_lines) {
2457 case 12:
2458 code = 0;
2459 break;
2460 case 16:
2461 code = 1;
2462 break;
2463 case 18:
2464 code = 2;
2465 break;
2466 case 24:
2467 code = 3;
2468 break;
2469 default:
2470 BUG();
2471 return;
2472 }
2473
Sumit Semwal2a205f32010-12-02 11:27:12 +00002474 if (channel == OMAP_DSS_CHANNEL_LCD2)
2475 REG_FLD_MOD(DISPC_CONTROL2, code, 9, 8);
2476 else
2477 REG_FLD_MOD(DISPC_CONTROL, code, 9, 8);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002478}
2479
Archit Taneja569969d2011-08-22 17:41:57 +05302480void dispc_mgr_set_io_pad_mode(enum dss_io_pad_mode mode)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002481{
2482 u32 l;
Archit Taneja569969d2011-08-22 17:41:57 +05302483 int gpout0, gpout1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002484
2485 switch (mode) {
Archit Taneja569969d2011-08-22 17:41:57 +05302486 case DSS_IO_PAD_MODE_RESET:
2487 gpout0 = 0;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002488 gpout1 = 0;
2489 break;
Archit Taneja569969d2011-08-22 17:41:57 +05302490 case DSS_IO_PAD_MODE_RFBI:
2491 gpout0 = 1;
2492 gpout1 = 0;
2493 break;
2494 case DSS_IO_PAD_MODE_BYPASS:
2495 gpout0 = 1;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002496 gpout1 = 1;
2497 break;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002498 default:
2499 BUG();
2500 return;
2501 }
2502
Archit Taneja569969d2011-08-22 17:41:57 +05302503 l = dispc_read_reg(DISPC_CONTROL);
2504 l = FLD_MOD(l, gpout0, 15, 15);
2505 l = FLD_MOD(l, gpout1, 16, 16);
2506 dispc_write_reg(DISPC_CONTROL, l);
2507}
2508
2509void dispc_mgr_enable_stallmode(enum omap_channel channel, bool enable)
2510{
2511 if (channel == OMAP_DSS_CHANNEL_LCD2)
2512 REG_FLD_MOD(DISPC_CONTROL2, enable, 11, 11);
2513 else
2514 REG_FLD_MOD(DISPC_CONTROL, enable, 11, 11);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002515}
2516
Archit Taneja8f366162012-04-16 12:53:44 +05302517static bool _dispc_mgr_size_ok(u16 width, u16 height)
2518{
2519 return width <= dss_feat_get_param_max(FEAT_PARAM_MGR_WIDTH) &&
2520 height <= dss_feat_get_param_max(FEAT_PARAM_MGR_HEIGHT);
2521}
2522
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002523static bool _dispc_lcd_timings_ok(int hsw, int hfp, int hbp,
2524 int vsw, int vfp, int vbp)
2525{
2526 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2527 if (hsw < 1 || hsw > 64 ||
2528 hfp < 1 || hfp > 256 ||
2529 hbp < 1 || hbp > 256 ||
2530 vsw < 1 || vsw > 64 ||
2531 vfp < 0 || vfp > 255 ||
2532 vbp < 0 || vbp > 255)
2533 return false;
2534 } else {
2535 if (hsw < 1 || hsw > 256 ||
2536 hfp < 1 || hfp > 4096 ||
2537 hbp < 1 || hbp > 4096 ||
2538 vsw < 1 || vsw > 256 ||
2539 vfp < 0 || vfp > 4095 ||
2540 vbp < 0 || vbp > 4095)
2541 return false;
2542 }
2543
2544 return true;
2545}
2546
Archit Taneja8f366162012-04-16 12:53:44 +05302547bool dispc_mgr_timings_ok(enum omap_channel channel,
Archit Tanejab917fa32012-04-27 01:07:28 +05302548 const struct omap_video_timings *timings)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002549{
Archit Taneja8f366162012-04-16 12:53:44 +05302550 bool timings_ok;
2551
2552 timings_ok = _dispc_mgr_size_ok(timings->x_res, timings->y_res);
2553
2554 if (dispc_mgr_is_lcd(channel))
2555 timings_ok = timings_ok && _dispc_lcd_timings_ok(timings->hsw,
2556 timings->hfp, timings->hbp,
2557 timings->vsw, timings->vfp,
2558 timings->vbp);
2559
2560 return timings_ok;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002561}
2562
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002563static void _dispc_mgr_set_lcd_timings(enum omap_channel channel, int hsw,
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002564 int hfp, int hbp, int vsw, int vfp, int vbp)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002565{
2566 u32 timing_h, timing_v;
2567
2568 if (cpu_is_omap24xx() || omap_rev() < OMAP3430_REV_ES3_0) {
2569 timing_h = FLD_VAL(hsw-1, 5, 0) | FLD_VAL(hfp-1, 15, 8) |
2570 FLD_VAL(hbp-1, 27, 20);
2571
2572 timing_v = FLD_VAL(vsw-1, 5, 0) | FLD_VAL(vfp, 15, 8) |
2573 FLD_VAL(vbp, 27, 20);
2574 } else {
2575 timing_h = FLD_VAL(hsw-1, 7, 0) | FLD_VAL(hfp-1, 19, 8) |
2576 FLD_VAL(hbp-1, 31, 20);
2577
2578 timing_v = FLD_VAL(vsw-1, 7, 0) | FLD_VAL(vfp, 19, 8) |
2579 FLD_VAL(vbp, 31, 20);
2580 }
2581
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002582 dispc_write_reg(DISPC_TIMING_H(channel), timing_h);
2583 dispc_write_reg(DISPC_TIMING_V(channel), timing_v);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002584}
2585
2586/* change name to mode? */
Archit Tanejac51d9212012-04-16 12:53:43 +05302587void dispc_mgr_set_timings(enum omap_channel channel,
Sumit Semwal64ba4f72010-12-02 11:27:10 +00002588 struct omap_video_timings *timings)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002589{
2590 unsigned xtot, ytot;
2591 unsigned long ht, vt;
2592
Sumit Semwal2a205f32010-12-02 11:27:12 +00002593 DSSDBG("channel %d xres %u yres %u\n", channel, timings->x_res,
2594 timings->y_res);
Archit Tanejac51d9212012-04-16 12:53:43 +05302595
Archit Taneja8f366162012-04-16 12:53:44 +05302596 if (!dispc_mgr_timings_ok(channel, timings))
2597 BUG();
Archit Tanejac51d9212012-04-16 12:53:43 +05302598
Archit Taneja8f366162012-04-16 12:53:44 +05302599 if (dispc_mgr_is_lcd(channel)) {
Archit Tanejac51d9212012-04-16 12:53:43 +05302600 _dispc_mgr_set_lcd_timings(channel, timings->hsw, timings->hfp,
2601 timings->hbp, timings->vsw, timings->vfp,
2602 timings->vbp);
2603
Archit Tanejac51d9212012-04-16 12:53:43 +05302604 xtot = timings->x_res + timings->hfp + timings->hsw +
2605 timings->hbp;
2606 ytot = timings->y_res + timings->vfp + timings->vsw +
2607 timings->vbp;
2608
2609 ht = (timings->pixel_clock * 1000) / xtot;
2610 vt = (timings->pixel_clock * 1000) / xtot / ytot;
2611
2612 DSSDBG("pck %u\n", timings->pixel_clock);
2613 DSSDBG("hsw %d hfp %d hbp %d vsw %d vfp %d vbp %d\n",
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002614 timings->hsw, timings->hfp, timings->hbp,
2615 timings->vsw, timings->vfp, timings->vbp);
2616
Archit Tanejac51d9212012-04-16 12:53:43 +05302617 DSSDBG("hsync %luHz, vsync %luHz\n", ht, vt);
Archit Tanejac51d9212012-04-16 12:53:43 +05302618 }
Archit Taneja8f366162012-04-16 12:53:44 +05302619
2620 dispc_mgr_set_size(channel, timings->x_res, timings->y_res);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002621}
2622
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002623static void dispc_mgr_set_lcd_divisor(enum omap_channel channel, u16 lck_div,
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002624 u16 pck_div)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002625{
2626 BUG_ON(lck_div < 1);
Tomi Valkeinen9eaaf202011-08-29 15:56:04 +03002627 BUG_ON(pck_div < 1);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002628
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -06002629 dispc_write_reg(DISPC_DIVISORo(channel),
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002630 FLD_VAL(lck_div, 23, 16) | FLD_VAL(pck_div, 7, 0));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002631}
2632
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002633static void dispc_mgr_get_lcd_divisor(enum omap_channel channel, int *lck_div,
Sumit Semwal2a205f32010-12-02 11:27:12 +00002634 int *pck_div)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002635{
2636 u32 l;
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -06002637 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002638 *lck_div = FLD_GET(l, 23, 16);
2639 *pck_div = FLD_GET(l, 7, 0);
2640}
2641
2642unsigned long dispc_fclk_rate(void)
2643{
Archit Tanejaa72b64b2011-05-12 17:26:26 +05302644 struct platform_device *dsidev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002645 unsigned long r = 0;
2646
Taneja, Archit66534e82011-03-08 05:50:34 -06002647 switch (dss_get_dispc_clk_source()) {
Archit Taneja89a35e52011-04-12 13:52:23 +05302648 case OMAP_DSS_CLK_SRC_FCK:
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03002649 r = clk_get_rate(dispc.dss_clk);
Taneja, Archit66534e82011-03-08 05:50:34 -06002650 break;
Archit Taneja89a35e52011-04-12 13:52:23 +05302651 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
Archit Tanejaa72b64b2011-05-12 17:26:26 +05302652 dsidev = dsi_get_dsidev_from_id(0);
2653 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
Taneja, Archit66534e82011-03-08 05:50:34 -06002654 break;
Archit Taneja5a8b5722011-05-12 17:26:29 +05302655 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2656 dsidev = dsi_get_dsidev_from_id(1);
2657 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2658 break;
Taneja, Archit66534e82011-03-08 05:50:34 -06002659 default:
2660 BUG();
2661 }
2662
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002663 return r;
2664}
2665
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002666unsigned long dispc_mgr_lclk_rate(enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002667{
Archit Tanejaa72b64b2011-05-12 17:26:26 +05302668 struct platform_device *dsidev;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002669 int lcd;
2670 unsigned long r;
2671 u32 l;
2672
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -06002673 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002674
2675 lcd = FLD_GET(l, 23, 16);
2676
Taneja, Architea751592011-03-08 05:50:35 -06002677 switch (dss_get_lcd_clk_source(channel)) {
Archit Taneja89a35e52011-04-12 13:52:23 +05302678 case OMAP_DSS_CLK_SRC_FCK:
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03002679 r = clk_get_rate(dispc.dss_clk);
Taneja, Architea751592011-03-08 05:50:35 -06002680 break;
Archit Taneja89a35e52011-04-12 13:52:23 +05302681 case OMAP_DSS_CLK_SRC_DSI_PLL_HSDIV_DISPC:
Archit Tanejaa72b64b2011-05-12 17:26:26 +05302682 dsidev = dsi_get_dsidev_from_id(0);
2683 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
Taneja, Architea751592011-03-08 05:50:35 -06002684 break;
Archit Taneja5a8b5722011-05-12 17:26:29 +05302685 case OMAP_DSS_CLK_SRC_DSI2_PLL_HSDIV_DISPC:
2686 dsidev = dsi_get_dsidev_from_id(1);
2687 r = dsi_get_pll_hsdiv_dispc_rate(dsidev);
2688 break;
Taneja, Architea751592011-03-08 05:50:35 -06002689 default:
2690 BUG();
2691 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002692
2693 return r / lcd;
2694}
2695
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002696unsigned long dispc_mgr_pclk_rate(enum omap_channel channel)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002697{
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002698 unsigned long r;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002699
Archit Tanejac3dc6a72011-09-13 18:28:41 +05302700 if (dispc_mgr_is_lcd(channel)) {
2701 int pcd;
2702 u32 l;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002703
Archit Tanejac3dc6a72011-09-13 18:28:41 +05302704 l = dispc_read_reg(DISPC_DIVISORo(channel));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002705
Archit Tanejac3dc6a72011-09-13 18:28:41 +05302706 pcd = FLD_GET(l, 7, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002707
Archit Tanejac3dc6a72011-09-13 18:28:41 +05302708 r = dispc_mgr_lclk_rate(channel);
2709
2710 return r / pcd;
2711 } else {
Archit Taneja3fa03ba2012-04-09 15:06:41 +05302712 enum dss_hdmi_venc_clk_source_select source;
Archit Tanejac3dc6a72011-09-13 18:28:41 +05302713
Archit Taneja3fa03ba2012-04-09 15:06:41 +05302714 source = dss_get_hdmi_venc_clk_source();
2715
2716 switch (source) {
2717 case DSS_VENC_TV_CLK:
Archit Tanejac3dc6a72011-09-13 18:28:41 +05302718 return venc_get_pixel_clock();
Archit Taneja3fa03ba2012-04-09 15:06:41 +05302719 case DSS_HDMI_M_PCLK:
Archit Tanejac3dc6a72011-09-13 18:28:41 +05302720 return hdmi_get_pixel_clock();
2721 default:
2722 BUG();
2723 }
2724 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002725}
2726
Chandrabhanu Mahapatra8b53d992012-04-23 12:16:50 +05302727unsigned long dispc_core_clk_rate(void)
2728{
2729 int lcd;
2730 unsigned long fclk = dispc_fclk_rate();
2731
2732 if (dss_has_feature(FEAT_CORE_CLK_DIV))
2733 lcd = REG_GET(DISPC_DIVISOR, 23, 16);
2734 else
2735 lcd = REG_GET(DISPC_DIVISORo(OMAP_DSS_CHANNEL_LCD), 23, 16);
2736
2737 return fclk / lcd;
2738}
2739
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002740void dispc_dump_clocks(struct seq_file *s)
2741{
2742 int lcd, pcd;
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -06002743 u32 l;
Archit Taneja89a35e52011-04-12 13:52:23 +05302744 enum omap_dss_clk_source dispc_clk_src = dss_get_dispc_clk_source();
2745 enum omap_dss_clk_source lcd_clk_src;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002746
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03002747 if (dispc_runtime_get())
2748 return;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002749
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002750 seq_printf(s, "- DISPC -\n");
2751
Archit Taneja067a57e2011-03-02 11:57:25 +05302752 seq_printf(s, "dispc fclk source = %s (%s)\n",
2753 dss_get_generic_clk_source_name(dispc_clk_src),
2754 dss_feat_get_clk_source_name(dispc_clk_src));
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002755
2756 seq_printf(s, "fck\t\t%-16lu\n", dispc_fclk_rate());
Sumit Semwal2a205f32010-12-02 11:27:12 +00002757
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -06002758 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
2759 seq_printf(s, "- DISPC-CORE-CLK -\n");
2760 l = dispc_read_reg(DISPC_DIVISOR);
2761 lcd = FLD_GET(l, 23, 16);
2762
2763 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
2764 (dispc_fclk_rate()/lcd), lcd);
2765 }
Sumit Semwal2a205f32010-12-02 11:27:12 +00002766 seq_printf(s, "- LCD1 -\n");
2767
Taneja, Architea751592011-03-08 05:50:35 -06002768 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD);
2769
2770 seq_printf(s, "lcd1_clk source = %s (%s)\n",
2771 dss_get_generic_clk_source_name(lcd_clk_src),
2772 dss_feat_get_clk_source_name(lcd_clk_src));
2773
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002774 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD, &lcd, &pcd);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002775
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002776 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002777 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD), lcd);
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00002778 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002779 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD), pcd);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002780 if (dss_has_feature(FEAT_MGR_LCD2)) {
2781 seq_printf(s, "- LCD2 -\n");
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002782
Taneja, Architea751592011-03-08 05:50:35 -06002783 lcd_clk_src = dss_get_lcd_clk_source(OMAP_DSS_CHANNEL_LCD2);
2784
2785 seq_printf(s, "lcd2_clk source = %s (%s)\n",
2786 dss_get_generic_clk_source_name(lcd_clk_src),
2787 dss_feat_get_clk_source_name(lcd_clk_src));
2788
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002789 dispc_mgr_get_lcd_divisor(OMAP_DSS_CHANNEL_LCD2, &lcd, &pcd);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002790
2791 seq_printf(s, "lck\t\t%-16lulck div\t%u\n",
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002792 dispc_mgr_lclk_rate(OMAP_DSS_CHANNEL_LCD2), lcd);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002793 seq_printf(s, "pck\t\t%-16lupck div\t%u\n",
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03002794 dispc_mgr_pclk_rate(OMAP_DSS_CHANNEL_LCD2), pcd);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002795 }
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03002796
2797 dispc_runtime_put();
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002798}
2799
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02002800#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
2801void dispc_dump_irqs(struct seq_file *s)
2802{
2803 unsigned long flags;
2804 struct dispc_irq_stats stats;
2805
2806 spin_lock_irqsave(&dispc.irq_stats_lock, flags);
2807
2808 stats = dispc.irq_stats;
2809 memset(&dispc.irq_stats, 0, sizeof(dispc.irq_stats));
2810 dispc.irq_stats.last_reset = jiffies;
2811
2812 spin_unlock_irqrestore(&dispc.irq_stats_lock, flags);
2813
2814 seq_printf(s, "period %u ms\n",
2815 jiffies_to_msecs(jiffies - stats.last_reset));
2816
2817 seq_printf(s, "irqs %d\n", stats.irq_count);
2818#define PIS(x) \
2819 seq_printf(s, "%-20s %10d\n", #x, stats.irqs[ffs(DISPC_IRQ_##x)-1]);
2820
2821 PIS(FRAMEDONE);
2822 PIS(VSYNC);
2823 PIS(EVSYNC_EVEN);
2824 PIS(EVSYNC_ODD);
2825 PIS(ACBIAS_COUNT_STAT);
2826 PIS(PROG_LINE_NUM);
2827 PIS(GFX_FIFO_UNDERFLOW);
2828 PIS(GFX_END_WIN);
2829 PIS(PAL_GAMMA_MASK);
2830 PIS(OCP_ERR);
2831 PIS(VID1_FIFO_UNDERFLOW);
2832 PIS(VID1_END_WIN);
2833 PIS(VID2_FIFO_UNDERFLOW);
2834 PIS(VID2_END_WIN);
Archit Tanejab8c095b2011-09-13 18:20:33 +05302835 if (dss_feat_get_num_ovls() > 3) {
2836 PIS(VID3_FIFO_UNDERFLOW);
2837 PIS(VID3_END_WIN);
2838 }
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02002839 PIS(SYNC_LOST);
2840 PIS(SYNC_LOST_DIGIT);
2841 PIS(WAKEUP);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002842 if (dss_has_feature(FEAT_MGR_LCD2)) {
2843 PIS(FRAMEDONE2);
2844 PIS(VSYNC2);
2845 PIS(ACBIAS_COUNT_STAT2);
2846 PIS(SYNC_LOST2);
2847 }
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02002848#undef PIS
2849}
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02002850#endif
2851
Tomi Valkeinene40402c2012-03-02 18:01:07 +02002852static void dispc_dump_regs(struct seq_file *s)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002853{
Archit Taneja4dd2da12011-08-05 19:06:01 +05302854 int i, j;
2855 const char *mgr_names[] = {
2856 [OMAP_DSS_CHANNEL_LCD] = "LCD",
2857 [OMAP_DSS_CHANNEL_DIGIT] = "TV",
2858 [OMAP_DSS_CHANNEL_LCD2] = "LCD2",
2859 };
2860 const char *ovl_names[] = {
2861 [OMAP_DSS_GFX] = "GFX",
2862 [OMAP_DSS_VIDEO1] = "VID1",
2863 [OMAP_DSS_VIDEO2] = "VID2",
Archit Tanejab8c095b2011-09-13 18:20:33 +05302864 [OMAP_DSS_VIDEO3] = "VID3",
Archit Taneja4dd2da12011-08-05 19:06:01 +05302865 };
2866 const char **p_names;
2867
Archit Taneja9b372c22011-05-06 11:45:49 +05302868#define DUMPREG(r) seq_printf(s, "%-50s %08x\n", #r, dispc_read_reg(r))
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002869
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03002870 if (dispc_runtime_get())
2871 return;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002872
Archit Taneja5010be82011-08-05 19:06:00 +05302873 /* DISPC common registers */
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002874 DUMPREG(DISPC_REVISION);
2875 DUMPREG(DISPC_SYSCONFIG);
2876 DUMPREG(DISPC_SYSSTATUS);
2877 DUMPREG(DISPC_IRQSTATUS);
2878 DUMPREG(DISPC_IRQENABLE);
2879 DUMPREG(DISPC_CONTROL);
2880 DUMPREG(DISPC_CONFIG);
2881 DUMPREG(DISPC_CAPABLE);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002882 DUMPREG(DISPC_LINE_STATUS);
2883 DUMPREG(DISPC_LINE_NUMBER);
Archit Taneja11354dd2011-09-26 11:47:29 +05302884 if (dss_has_feature(FEAT_ALPHA_FIXED_ZORDER) ||
2885 dss_has_feature(FEAT_ALPHA_FREE_ZORDER))
Tomi Valkeinen332e9d72011-05-27 14:22:16 +03002886 DUMPREG(DISPC_GLOBAL_ALPHA);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002887 if (dss_has_feature(FEAT_MGR_LCD2)) {
2888 DUMPREG(DISPC_CONTROL2);
2889 DUMPREG(DISPC_CONFIG2);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002890 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002891
Archit Taneja5010be82011-08-05 19:06:00 +05302892#undef DUMPREG
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002893
Archit Taneja5010be82011-08-05 19:06:00 +05302894#define DISPC_REG(i, name) name(i)
Archit Taneja4dd2da12011-08-05 19:06:01 +05302895#define DUMPREG(i, r) seq_printf(s, "%s(%s)%*s %08x\n", #r, p_names[i], \
2896 48 - strlen(#r) - strlen(p_names[i]), " ", \
Archit Taneja5010be82011-08-05 19:06:00 +05302897 dispc_read_reg(DISPC_REG(i, r)))
2898
Archit Taneja4dd2da12011-08-05 19:06:01 +05302899 p_names = mgr_names;
Archit Taneja5010be82011-08-05 19:06:00 +05302900
Archit Taneja4dd2da12011-08-05 19:06:01 +05302901 /* DISPC channel specific registers */
2902 for (i = 0; i < dss_feat_get_num_mgrs(); i++) {
2903 DUMPREG(i, DISPC_DEFAULT_COLOR);
2904 DUMPREG(i, DISPC_TRANS_COLOR);
2905 DUMPREG(i, DISPC_SIZE_MGR);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002906
Archit Taneja4dd2da12011-08-05 19:06:01 +05302907 if (i == OMAP_DSS_CHANNEL_DIGIT)
2908 continue;
Archit Taneja5010be82011-08-05 19:06:00 +05302909
Archit Taneja4dd2da12011-08-05 19:06:01 +05302910 DUMPREG(i, DISPC_DEFAULT_COLOR);
2911 DUMPREG(i, DISPC_TRANS_COLOR);
2912 DUMPREG(i, DISPC_TIMING_H);
2913 DUMPREG(i, DISPC_TIMING_V);
2914 DUMPREG(i, DISPC_POL_FREQ);
2915 DUMPREG(i, DISPC_DIVISORo);
2916 DUMPREG(i, DISPC_SIZE_MGR);
Archit Taneja5010be82011-08-05 19:06:00 +05302917
Archit Taneja4dd2da12011-08-05 19:06:01 +05302918 DUMPREG(i, DISPC_DATA_CYCLE1);
2919 DUMPREG(i, DISPC_DATA_CYCLE2);
2920 DUMPREG(i, DISPC_DATA_CYCLE3);
Sumit Semwal2a205f32010-12-02 11:27:12 +00002921
Tomi Valkeinen332e9d72011-05-27 14:22:16 +03002922 if (dss_has_feature(FEAT_CPR)) {
Archit Taneja4dd2da12011-08-05 19:06:01 +05302923 DUMPREG(i, DISPC_CPR_COEF_R);
2924 DUMPREG(i, DISPC_CPR_COEF_G);
2925 DUMPREG(i, DISPC_CPR_COEF_B);
Tomi Valkeinen332e9d72011-05-27 14:22:16 +03002926 }
Sumit Semwal2a205f32010-12-02 11:27:12 +00002927 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002928
Archit Taneja4dd2da12011-08-05 19:06:01 +05302929 p_names = ovl_names;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002930
Archit Taneja4dd2da12011-08-05 19:06:01 +05302931 for (i = 0; i < dss_feat_get_num_ovls(); i++) {
2932 DUMPREG(i, DISPC_OVL_BA0);
2933 DUMPREG(i, DISPC_OVL_BA1);
2934 DUMPREG(i, DISPC_OVL_POSITION);
2935 DUMPREG(i, DISPC_OVL_SIZE);
2936 DUMPREG(i, DISPC_OVL_ATTRIBUTES);
2937 DUMPREG(i, DISPC_OVL_FIFO_THRESHOLD);
2938 DUMPREG(i, DISPC_OVL_FIFO_SIZE_STATUS);
2939 DUMPREG(i, DISPC_OVL_ROW_INC);
2940 DUMPREG(i, DISPC_OVL_PIXEL_INC);
2941 if (dss_has_feature(FEAT_PRELOAD))
2942 DUMPREG(i, DISPC_OVL_PRELOAD);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002943
Archit Taneja4dd2da12011-08-05 19:06:01 +05302944 if (i == OMAP_DSS_GFX) {
2945 DUMPREG(i, DISPC_OVL_WINDOW_SKIP);
2946 DUMPREG(i, DISPC_OVL_TABLE_BA);
2947 continue;
2948 }
2949
2950 DUMPREG(i, DISPC_OVL_FIR);
2951 DUMPREG(i, DISPC_OVL_PICTURE_SIZE);
2952 DUMPREG(i, DISPC_OVL_ACCU0);
2953 DUMPREG(i, DISPC_OVL_ACCU1);
2954 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2955 DUMPREG(i, DISPC_OVL_BA0_UV);
2956 DUMPREG(i, DISPC_OVL_BA1_UV);
2957 DUMPREG(i, DISPC_OVL_FIR2);
2958 DUMPREG(i, DISPC_OVL_ACCU2_0);
2959 DUMPREG(i, DISPC_OVL_ACCU2_1);
2960 }
2961 if (dss_has_feature(FEAT_ATTR2))
2962 DUMPREG(i, DISPC_OVL_ATTRIBUTES2);
2963 if (dss_has_feature(FEAT_PRELOAD))
2964 DUMPREG(i, DISPC_OVL_PRELOAD);
Archit Taneja5010be82011-08-05 19:06:00 +05302965 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002966
Archit Taneja5010be82011-08-05 19:06:00 +05302967#undef DISPC_REG
2968#undef DUMPREG
2969
2970#define DISPC_REG(plane, name, i) name(plane, i)
2971#define DUMPREG(plane, name, i) \
Archit Taneja4dd2da12011-08-05 19:06:01 +05302972 seq_printf(s, "%s_%d(%s)%*s %08x\n", #name, i, p_names[plane], \
2973 46 - strlen(#name) - strlen(p_names[plane]), " ", \
Archit Taneja5010be82011-08-05 19:06:00 +05302974 dispc_read_reg(DISPC_REG(plane, name, i)))
2975
Archit Taneja4dd2da12011-08-05 19:06:01 +05302976 /* Video pipeline coefficient registers */
Archit Taneja5010be82011-08-05 19:06:00 +05302977
Archit Taneja4dd2da12011-08-05 19:06:01 +05302978 /* start from OMAP_DSS_VIDEO1 */
2979 for (i = 1; i < dss_feat_get_num_ovls(); i++) {
2980 for (j = 0; j < 8; j++)
2981 DUMPREG(i, DISPC_OVL_FIR_COEF_H, j);
Archit Taneja5010be82011-08-05 19:06:00 +05302982
Archit Taneja4dd2da12011-08-05 19:06:01 +05302983 for (j = 0; j < 8; j++)
2984 DUMPREG(i, DISPC_OVL_FIR_COEF_HV, j);
Archit Taneja5010be82011-08-05 19:06:00 +05302985
Archit Taneja4dd2da12011-08-05 19:06:01 +05302986 for (j = 0; j < 5; j++)
2987 DUMPREG(i, DISPC_OVL_CONV_COEF, j);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02002988
Archit Taneja4dd2da12011-08-05 19:06:01 +05302989 if (dss_has_feature(FEAT_FIR_COEF_V)) {
2990 for (j = 0; j < 8; j++)
2991 DUMPREG(i, DISPC_OVL_FIR_COEF_V, j);
2992 }
Amber Jainab5ca072011-05-19 19:47:53 +05302993
Archit Taneja4dd2da12011-08-05 19:06:01 +05302994 if (dss_has_feature(FEAT_HANDLE_UV_SEPARATE)) {
2995 for (j = 0; j < 8; j++)
2996 DUMPREG(i, DISPC_OVL_FIR_COEF_H2, j);
Amber Jainab5ca072011-05-19 19:47:53 +05302997
Archit Taneja4dd2da12011-08-05 19:06:01 +05302998 for (j = 0; j < 8; j++)
2999 DUMPREG(i, DISPC_OVL_FIR_COEF_HV2, j);
Amber Jainab5ca072011-05-19 19:47:53 +05303000
Archit Taneja4dd2da12011-08-05 19:06:01 +05303001 for (j = 0; j < 8; j++)
3002 DUMPREG(i, DISPC_OVL_FIR_COEF_V2, j);
3003 }
Tomi Valkeinen332e9d72011-05-27 14:22:16 +03003004 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003005
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003006 dispc_runtime_put();
Archit Taneja5010be82011-08-05 19:06:00 +05303007
3008#undef DISPC_REG
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003009#undef DUMPREG
3010}
3011
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03003012static void _dispc_mgr_set_pol_freq(enum omap_channel channel, bool onoff,
3013 bool rf, bool ieo, bool ipc, bool ihs, bool ivs, u8 acbi,
3014 u8 acb)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003015{
3016 u32 l = 0;
3017
3018 DSSDBG("onoff %d rf %d ieo %d ipc %d ihs %d ivs %d acbi %d acb %d\n",
3019 onoff, rf, ieo, ipc, ihs, ivs, acbi, acb);
3020
3021 l |= FLD_VAL(onoff, 17, 17);
3022 l |= FLD_VAL(rf, 16, 16);
3023 l |= FLD_VAL(ieo, 15, 15);
3024 l |= FLD_VAL(ipc, 14, 14);
3025 l |= FLD_VAL(ihs, 13, 13);
3026 l |= FLD_VAL(ivs, 12, 12);
3027 l |= FLD_VAL(acbi, 11, 8);
3028 l |= FLD_VAL(acb, 7, 0);
3029
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00003030 dispc_write_reg(DISPC_POL_FREQ(channel), l);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003031}
3032
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03003033void dispc_mgr_set_pol_freq(enum omap_channel channel,
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00003034 enum omap_panel_config config, u8 acbi, u8 acb)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003035{
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03003036 _dispc_mgr_set_pol_freq(channel, (config & OMAP_DSS_LCD_ONOFF) != 0,
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003037 (config & OMAP_DSS_LCD_RF) != 0,
3038 (config & OMAP_DSS_LCD_IEO) != 0,
3039 (config & OMAP_DSS_LCD_IPC) != 0,
3040 (config & OMAP_DSS_LCD_IHS) != 0,
3041 (config & OMAP_DSS_LCD_IVS) != 0,
3042 acbi, acb);
3043}
3044
3045/* with fck as input clock rate, find dispc dividers that produce req_pck */
3046void dispc_find_clk_divs(bool is_tft, unsigned long req_pck, unsigned long fck,
3047 struct dispc_clock_info *cinfo)
3048{
Tomi Valkeinen9eaaf202011-08-29 15:56:04 +03003049 u16 pcd_min, pcd_max;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003050 unsigned long best_pck;
3051 u16 best_ld, cur_ld;
3052 u16 best_pd, cur_pd;
3053
Tomi Valkeinen9eaaf202011-08-29 15:56:04 +03003054 pcd_min = dss_feat_get_param_min(FEAT_PARAM_DSS_PCD);
3055 pcd_max = dss_feat_get_param_max(FEAT_PARAM_DSS_PCD);
3056
3057 if (!is_tft)
3058 pcd_min = 3;
3059
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003060 best_pck = 0;
3061 best_ld = 0;
3062 best_pd = 0;
3063
3064 for (cur_ld = 1; cur_ld <= 255; ++cur_ld) {
3065 unsigned long lck = fck / cur_ld;
3066
Tomi Valkeinen9eaaf202011-08-29 15:56:04 +03003067 for (cur_pd = pcd_min; cur_pd <= pcd_max; ++cur_pd) {
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003068 unsigned long pck = lck / cur_pd;
3069 long old_delta = abs(best_pck - req_pck);
3070 long new_delta = abs(pck - req_pck);
3071
3072 if (best_pck == 0 || new_delta < old_delta) {
3073 best_pck = pck;
3074 best_ld = cur_ld;
3075 best_pd = cur_pd;
3076
3077 if (pck == req_pck)
3078 goto found;
3079 }
3080
3081 if (pck < req_pck)
3082 break;
3083 }
3084
3085 if (lck / pcd_min < req_pck)
3086 break;
3087 }
3088
3089found:
3090 cinfo->lck_div = best_ld;
3091 cinfo->pck_div = best_pd;
3092 cinfo->lck = fck / cinfo->lck_div;
3093 cinfo->pck = cinfo->lck / cinfo->pck_div;
3094}
3095
3096/* calculate clock rates using dividers in cinfo */
3097int dispc_calc_clock_rates(unsigned long dispc_fclk_rate,
3098 struct dispc_clock_info *cinfo)
3099{
3100 if (cinfo->lck_div > 255 || cinfo->lck_div == 0)
3101 return -EINVAL;
Tomi Valkeinen9eaaf202011-08-29 15:56:04 +03003102 if (cinfo->pck_div < 1 || cinfo->pck_div > 255)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003103 return -EINVAL;
3104
3105 cinfo->lck = dispc_fclk_rate / cinfo->lck_div;
3106 cinfo->pck = cinfo->lck / cinfo->pck_div;
3107
3108 return 0;
3109}
3110
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03003111int dispc_mgr_set_clock_div(enum omap_channel channel,
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00003112 struct dispc_clock_info *cinfo)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003113{
3114 DSSDBG("lck = %lu (%u)\n", cinfo->lck, cinfo->lck_div);
3115 DSSDBG("pck = %lu (%u)\n", cinfo->pck, cinfo->pck_div);
3116
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03003117 dispc_mgr_set_lcd_divisor(channel, cinfo->lck_div, cinfo->pck_div);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003118
3119 return 0;
3120}
3121
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03003122int dispc_mgr_get_clock_div(enum omap_channel channel,
Sumit Semwalff1b2cd2010-12-02 11:27:11 +00003123 struct dispc_clock_info *cinfo)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003124{
3125 unsigned long fck;
3126
3127 fck = dispc_fclk_rate();
3128
Murthy, Raghuveerce7fa5e2011-03-03 09:27:59 -06003129 cinfo->lck_div = REG_GET(DISPC_DIVISORo(channel), 23, 16);
3130 cinfo->pck_div = REG_GET(DISPC_DIVISORo(channel), 7, 0);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003131
3132 cinfo->lck = fck / cinfo->lck_div;
3133 cinfo->pck = cinfo->lck / cinfo->pck_div;
3134
3135 return 0;
3136}
3137
3138/* dispc.irq_lock has to be locked by the caller */
3139static void _omap_dispc_set_irqs(void)
3140{
3141 u32 mask;
3142 u32 old_mask;
3143 int i;
3144 struct omap_dispc_isr_data *isr_data;
3145
3146 mask = dispc.irq_error_mask;
3147
3148 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3149 isr_data = &dispc.registered_isr[i];
3150
3151 if (isr_data->isr == NULL)
3152 continue;
3153
3154 mask |= isr_data->mask;
3155 }
3156
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003157 old_mask = dispc_read_reg(DISPC_IRQENABLE);
3158 /* clear the irqstatus for newly enabled irqs */
3159 dispc_write_reg(DISPC_IRQSTATUS, (mask ^ old_mask) & mask);
3160
3161 dispc_write_reg(DISPC_IRQENABLE, mask);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003162}
3163
3164int omap_dispc_register_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3165{
3166 int i;
3167 int ret;
3168 unsigned long flags;
3169 struct omap_dispc_isr_data *isr_data;
3170
3171 if (isr == NULL)
3172 return -EINVAL;
3173
3174 spin_lock_irqsave(&dispc.irq_lock, flags);
3175
3176 /* check for duplicate entry */
3177 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3178 isr_data = &dispc.registered_isr[i];
3179 if (isr_data->isr == isr && isr_data->arg == arg &&
3180 isr_data->mask == mask) {
3181 ret = -EINVAL;
3182 goto err;
3183 }
3184 }
3185
3186 isr_data = NULL;
3187 ret = -EBUSY;
3188
3189 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3190 isr_data = &dispc.registered_isr[i];
3191
3192 if (isr_data->isr != NULL)
3193 continue;
3194
3195 isr_data->isr = isr;
3196 isr_data->arg = arg;
3197 isr_data->mask = mask;
3198 ret = 0;
3199
3200 break;
3201 }
3202
Tomi Valkeinenb9cb0982011-03-04 18:19:54 +02003203 if (ret)
3204 goto err;
3205
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003206 _omap_dispc_set_irqs();
3207
3208 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3209
3210 return 0;
3211err:
3212 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3213
3214 return ret;
3215}
3216EXPORT_SYMBOL(omap_dispc_register_isr);
3217
3218int omap_dispc_unregister_isr(omap_dispc_isr_t isr, void *arg, u32 mask)
3219{
3220 int i;
3221 unsigned long flags;
3222 int ret = -EINVAL;
3223 struct omap_dispc_isr_data *isr_data;
3224
3225 spin_lock_irqsave(&dispc.irq_lock, flags);
3226
3227 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3228 isr_data = &dispc.registered_isr[i];
3229 if (isr_data->isr != isr || isr_data->arg != arg ||
3230 isr_data->mask != mask)
3231 continue;
3232
3233 /* found the correct isr */
3234
3235 isr_data->isr = NULL;
3236 isr_data->arg = NULL;
3237 isr_data->mask = 0;
3238
3239 ret = 0;
3240 break;
3241 }
3242
3243 if (ret == 0)
3244 _omap_dispc_set_irqs();
3245
3246 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3247
3248 return ret;
3249}
3250EXPORT_SYMBOL(omap_dispc_unregister_isr);
3251
3252#ifdef DEBUG
3253static void print_irq_status(u32 status)
3254{
3255 if ((status & dispc.irq_error_mask) == 0)
3256 return;
3257
3258 printk(KERN_DEBUG "DISPC IRQ: 0x%x: ", status);
3259
3260#define PIS(x) \
3261 if (status & DISPC_IRQ_##x) \
3262 printk(#x " ");
3263 PIS(GFX_FIFO_UNDERFLOW);
3264 PIS(OCP_ERR);
3265 PIS(VID1_FIFO_UNDERFLOW);
3266 PIS(VID2_FIFO_UNDERFLOW);
Archit Tanejab8c095b2011-09-13 18:20:33 +05303267 if (dss_feat_get_num_ovls() > 3)
3268 PIS(VID3_FIFO_UNDERFLOW);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003269 PIS(SYNC_LOST);
3270 PIS(SYNC_LOST_DIGIT);
Sumit Semwal2a205f32010-12-02 11:27:12 +00003271 if (dss_has_feature(FEAT_MGR_LCD2))
3272 PIS(SYNC_LOST2);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003273#undef PIS
3274
3275 printk("\n");
3276}
3277#endif
3278
3279/* Called from dss.c. Note that we don't touch clocks here,
3280 * but we presume they are on because we got an IRQ. However,
3281 * an irq handler may turn the clocks off, so we may not have
3282 * clock later in the function. */
archit tanejaaffe3602011-02-23 08:41:03 +00003283static irqreturn_t omap_dispc_irq_handler(int irq, void *arg)
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003284{
3285 int i;
archit tanejaaffe3602011-02-23 08:41:03 +00003286 u32 irqstatus, irqenable;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003287 u32 handledirqs = 0;
3288 u32 unhandled_errors;
3289 struct omap_dispc_isr_data *isr_data;
3290 struct omap_dispc_isr_data registered_isr[DISPC_MAX_NR_ISRS];
3291
3292 spin_lock(&dispc.irq_lock);
3293
3294 irqstatus = dispc_read_reg(DISPC_IRQSTATUS);
archit tanejaaffe3602011-02-23 08:41:03 +00003295 irqenable = dispc_read_reg(DISPC_IRQENABLE);
3296
3297 /* IRQ is not for us */
3298 if (!(irqstatus & irqenable)) {
3299 spin_unlock(&dispc.irq_lock);
3300 return IRQ_NONE;
3301 }
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003302
Tomi Valkeinendfc0fd82009-12-17 14:35:21 +02003303#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3304 spin_lock(&dispc.irq_stats_lock);
3305 dispc.irq_stats.irq_count++;
3306 dss_collect_irq_stats(irqstatus, dispc.irq_stats.irqs);
3307 spin_unlock(&dispc.irq_stats_lock);
3308#endif
3309
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003310#ifdef DEBUG
3311 if (dss_debug)
3312 print_irq_status(irqstatus);
3313#endif
3314 /* Ack the interrupt. Do it here before clocks are possibly turned
3315 * off */
3316 dispc_write_reg(DISPC_IRQSTATUS, irqstatus);
3317 /* flush posted write */
3318 dispc_read_reg(DISPC_IRQSTATUS);
3319
3320 /* make a copy and unlock, so that isrs can unregister
3321 * themselves */
3322 memcpy(registered_isr, dispc.registered_isr,
3323 sizeof(registered_isr));
3324
3325 spin_unlock(&dispc.irq_lock);
3326
3327 for (i = 0; i < DISPC_MAX_NR_ISRS; i++) {
3328 isr_data = &registered_isr[i];
3329
3330 if (!isr_data->isr)
3331 continue;
3332
3333 if (isr_data->mask & irqstatus) {
3334 isr_data->isr(isr_data->arg, irqstatus);
3335 handledirqs |= isr_data->mask;
3336 }
3337 }
3338
3339 spin_lock(&dispc.irq_lock);
3340
3341 unhandled_errors = irqstatus & ~handledirqs & dispc.irq_error_mask;
3342
3343 if (unhandled_errors) {
3344 dispc.error_irqs |= unhandled_errors;
3345
3346 dispc.irq_error_mask &= ~unhandled_errors;
3347 _omap_dispc_set_irqs();
3348
3349 schedule_work(&dispc.error_work);
3350 }
3351
3352 spin_unlock(&dispc.irq_lock);
archit tanejaaffe3602011-02-23 08:41:03 +00003353
3354 return IRQ_HANDLED;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003355}
3356
3357static void dispc_error_worker(struct work_struct *work)
3358{
3359 int i;
3360 u32 errors;
3361 unsigned long flags;
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003362 static const unsigned fifo_underflow_bits[] = {
3363 DISPC_IRQ_GFX_FIFO_UNDERFLOW,
3364 DISPC_IRQ_VID1_FIFO_UNDERFLOW,
3365 DISPC_IRQ_VID2_FIFO_UNDERFLOW,
Archit Tanejab8c095b2011-09-13 18:20:33 +05303366 DISPC_IRQ_VID3_FIFO_UNDERFLOW,
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003367 };
3368
3369 static const unsigned sync_lost_bits[] = {
3370 DISPC_IRQ_SYNC_LOST,
3371 DISPC_IRQ_SYNC_LOST_DIGIT,
3372 DISPC_IRQ_SYNC_LOST2,
3373 };
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003374
3375 spin_lock_irqsave(&dispc.irq_lock, flags);
3376 errors = dispc.error_irqs;
3377 dispc.error_irqs = 0;
3378 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3379
Dima Zavin13eae1f2011-06-27 10:31:05 -07003380 dispc_runtime_get();
3381
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003382 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3383 struct omap_overlay *ovl;
3384 unsigned bit;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003385
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003386 ovl = omap_dss_get_overlay(i);
3387 bit = fifo_underflow_bits[i];
3388
3389 if (bit & errors) {
3390 DSSERR("FIFO UNDERFLOW on %s, disabling the overlay\n",
3391 ovl->name);
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03003392 dispc_ovl_enable(ovl->id, false);
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03003393 dispc_mgr_go(ovl->manager->id);
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003394 mdelay(50);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003395 }
3396 }
3397
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003398 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3399 struct omap_overlay_manager *mgr;
3400 unsigned bit;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003401
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003402 mgr = omap_dss_get_overlay_manager(i);
3403 bit = sync_lost_bits[i];
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003404
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003405 if (bit & errors) {
3406 struct omap_dss_device *dssdev = mgr->device;
3407 bool enable;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003408
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003409 DSSERR("SYNC_LOST on channel %s, restarting the output "
3410 "with video overlays disabled\n",
3411 mgr->name);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003412
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003413 enable = dssdev->state == OMAP_DSS_DISPLAY_ACTIVE;
3414 dssdev->driver->disable(dssdev);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003415
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003416 for (i = 0; i < omap_dss_get_num_overlays(); ++i) {
3417 struct omap_overlay *ovl;
3418 ovl = omap_dss_get_overlay(i);
3419
Tomi Valkeinenfe3cc9d2011-08-15 11:51:50 +03003420 if (ovl->id != OMAP_DSS_GFX &&
3421 ovl->manager == mgr)
Tomi Valkeinenf0e5caa2011-08-16 13:25:00 +03003422 dispc_ovl_enable(ovl->id, false);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003423 }
3424
Tomi Valkeinen26d9dd02011-08-16 13:45:15 +03003425 dispc_mgr_go(mgr->id);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003426 mdelay(50);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003427
Sumit Semwal2a205f32010-12-02 11:27:12 +00003428 if (enable)
3429 dssdev->driver->enable(dssdev);
3430 }
3431 }
3432
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003433 if (errors & DISPC_IRQ_OCP_ERR) {
3434 DSSERR("OCP_ERR\n");
3435 for (i = 0; i < omap_dss_get_num_overlay_managers(); ++i) {
3436 struct omap_overlay_manager *mgr;
3437 mgr = omap_dss_get_overlay_manager(i);
Rob Clark00f17e42011-12-11 14:02:27 -06003438 if (mgr->device && mgr->device->driver)
3439 mgr->device->driver->disable(mgr->device);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003440 }
3441 }
3442
3443 spin_lock_irqsave(&dispc.irq_lock, flags);
3444 dispc.irq_error_mask |= errors;
3445 _omap_dispc_set_irqs();
3446 spin_unlock_irqrestore(&dispc.irq_lock, flags);
Dima Zavin13eae1f2011-06-27 10:31:05 -07003447
3448 dispc_runtime_put();
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003449}
3450
3451int omap_dispc_wait_for_irq_timeout(u32 irqmask, unsigned long timeout)
3452{
3453 void dispc_irq_wait_handler(void *data, u32 mask)
3454 {
3455 complete((struct completion *)data);
3456 }
3457
3458 int r;
3459 DECLARE_COMPLETION_ONSTACK(completion);
3460
3461 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3462 irqmask);
3463
3464 if (r)
3465 return r;
3466
3467 timeout = wait_for_completion_timeout(&completion, timeout);
3468
3469 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3470
3471 if (timeout == 0)
3472 return -ETIMEDOUT;
3473
3474 if (timeout == -ERESTARTSYS)
3475 return -ERESTARTSYS;
3476
3477 return 0;
3478}
3479
3480int omap_dispc_wait_for_irq_interruptible_timeout(u32 irqmask,
3481 unsigned long timeout)
3482{
3483 void dispc_irq_wait_handler(void *data, u32 mask)
3484 {
3485 complete((struct completion *)data);
3486 }
3487
3488 int r;
3489 DECLARE_COMPLETION_ONSTACK(completion);
3490
3491 r = omap_dispc_register_isr(dispc_irq_wait_handler, &completion,
3492 irqmask);
3493
3494 if (r)
3495 return r;
3496
3497 timeout = wait_for_completion_interruptible_timeout(&completion,
3498 timeout);
3499
3500 omap_dispc_unregister_isr(dispc_irq_wait_handler, &completion, irqmask);
3501
3502 if (timeout == 0)
3503 return -ETIMEDOUT;
3504
3505 if (timeout == -ERESTARTSYS)
3506 return -ERESTARTSYS;
3507
3508 return 0;
3509}
3510
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003511static void _omap_dispc_initialize_irq(void)
3512{
3513 unsigned long flags;
3514
3515 spin_lock_irqsave(&dispc.irq_lock, flags);
3516
3517 memset(dispc.registered_isr, 0, sizeof(dispc.registered_isr));
3518
3519 dispc.irq_error_mask = DISPC_IRQ_MASK_ERROR;
Sumit Semwal2a205f32010-12-02 11:27:12 +00003520 if (dss_has_feature(FEAT_MGR_LCD2))
3521 dispc.irq_error_mask |= DISPC_IRQ_SYNC_LOST2;
Archit Tanejab8c095b2011-09-13 18:20:33 +05303522 if (dss_feat_get_num_ovls() > 3)
3523 dispc.irq_error_mask |= DISPC_IRQ_VID3_FIFO_UNDERFLOW;
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003524
3525 /* there's SYNC_LOST_DIGIT waiting after enabling the DSS,
3526 * so clear it */
3527 dispc_write_reg(DISPC_IRQSTATUS, dispc_read_reg(DISPC_IRQSTATUS));
3528
3529 _omap_dispc_set_irqs();
3530
3531 spin_unlock_irqrestore(&dispc.irq_lock, flags);
3532}
3533
3534void dispc_enable_sidle(void)
3535{
3536 REG_FLD_MOD(DISPC_SYSCONFIG, 2, 4, 3); /* SIDLEMODE: smart idle */
3537}
3538
3539void dispc_disable_sidle(void)
3540{
3541 REG_FLD_MOD(DISPC_SYSCONFIG, 1, 4, 3); /* SIDLEMODE: no idle */
3542}
3543
3544static void _omap_dispc_initial_config(void)
3545{
3546 u32 l;
3547
Murthy, Raghuveer0cf35df2011-03-03 09:28:00 -06003548 /* Exclusively enable DISPC_CORE_CLK and set divider to 1 */
3549 if (dss_has_feature(FEAT_CORE_CLK_DIV)) {
3550 l = dispc_read_reg(DISPC_DIVISOR);
3551 /* Use DISPC_DIVISOR.LCD, instead of DISPC_DIVISOR1.LCD */
3552 l = FLD_MOD(l, 1, 0, 0);
3553 l = FLD_MOD(l, 1, 23, 16);
3554 dispc_write_reg(DISPC_DIVISOR, l);
3555 }
3556
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003557 /* FUNCGATED */
Archit Taneja6ced40b2010-12-02 11:27:13 +00003558 if (dss_has_feature(FEAT_FUNCGATED))
3559 REG_FLD_MOD(DISPC_CONFIG, 1, 9, 9);
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003560
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003561 _dispc_setup_color_conv_coef();
3562
3563 dispc_set_loadmode(OMAP_DSS_LOAD_FRAME_ONLY);
3564
3565 dispc_read_plane_fifo_sizes();
Tomi Valkeinen5ed8cf52011-06-21 09:35:36 +03003566
3567 dispc_configure_burst_sizes();
Archit Taneja54128702011-09-08 11:29:17 +05303568
3569 dispc_ovl_enable_zorder_planes();
Tomi Valkeinen80c39712009-11-12 11:41:42 +02003570}
3571
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003572/* DISPC HW IP initialisation */
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +02003573static int __init omap_dispchw_probe(struct platform_device *pdev)
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003574{
3575 u32 rev;
archit tanejaaffe3602011-02-23 08:41:03 +00003576 int r = 0;
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +00003577 struct resource *dispc_mem;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003578 struct clk *clk;
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +00003579
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003580 dispc.pdev = pdev;
3581
3582 spin_lock_init(&dispc.irq_lock);
3583
3584#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3585 spin_lock_init(&dispc.irq_stats_lock);
3586 dispc.irq_stats.last_reset = jiffies;
3587#endif
3588
3589 INIT_WORK(&dispc.error_work, dispc_error_worker);
3590
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +00003591 dispc_mem = platform_get_resource(dispc.pdev, IORESOURCE_MEM, 0);
3592 if (!dispc_mem) {
3593 DSSERR("can't get IORESOURCE_MEM DISPC\n");
Tomi Valkeinencd3b3442012-01-25 13:31:04 +02003594 return -EINVAL;
Senthilvadivu Guruswamyea9da362011-01-24 06:22:04 +00003595 }
Tomi Valkeinencd3b3442012-01-25 13:31:04 +02003596
Julia Lawall6e2a14d2012-01-24 14:00:45 +01003597 dispc.base = devm_ioremap(&pdev->dev, dispc_mem->start,
3598 resource_size(dispc_mem));
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003599 if (!dispc.base) {
3600 DSSERR("can't ioremap DISPC\n");
Tomi Valkeinencd3b3442012-01-25 13:31:04 +02003601 return -ENOMEM;
archit tanejaaffe3602011-02-23 08:41:03 +00003602 }
Tomi Valkeinencd3b3442012-01-25 13:31:04 +02003603
archit tanejaaffe3602011-02-23 08:41:03 +00003604 dispc.irq = platform_get_irq(dispc.pdev, 0);
3605 if (dispc.irq < 0) {
3606 DSSERR("platform_get_irq failed\n");
Tomi Valkeinencd3b3442012-01-25 13:31:04 +02003607 return -ENODEV;
archit tanejaaffe3602011-02-23 08:41:03 +00003608 }
3609
Julia Lawall6e2a14d2012-01-24 14:00:45 +01003610 r = devm_request_irq(&pdev->dev, dispc.irq, omap_dispc_irq_handler,
3611 IRQF_SHARED, "OMAP DISPC", dispc.pdev);
archit tanejaaffe3602011-02-23 08:41:03 +00003612 if (r < 0) {
3613 DSSERR("request_irq failed\n");
Tomi Valkeinencd3b3442012-01-25 13:31:04 +02003614 return r;
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003615 }
3616
Tomi Valkeinencd3b3442012-01-25 13:31:04 +02003617 clk = clk_get(&pdev->dev, "fck");
3618 if (IS_ERR(clk)) {
3619 DSSERR("can't get fck\n");
3620 r = PTR_ERR(clk);
3621 return r;
3622 }
3623
3624 dispc.dss_clk = clk;
3625
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003626 pm_runtime_enable(&pdev->dev);
3627
3628 r = dispc_runtime_get();
3629 if (r)
3630 goto err_runtime_get;
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003631
3632 _omap_dispc_initial_config();
3633
3634 _omap_dispc_initialize_irq();
3635
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003636 rev = dispc_read_reg(DISPC_REVISION);
Sumit Semwala06b62f2011-01-24 06:22:03 +00003637 dev_dbg(&pdev->dev, "OMAP DISPC rev %d.%d\n",
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003638 FLD_GET(rev, 7, 4), FLD_GET(rev, 3, 0));
3639
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003640 dispc_runtime_put();
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003641
Tomi Valkeinene40402c2012-03-02 18:01:07 +02003642 dss_debugfs_create_file("dispc", dispc_dump_regs);
3643
3644#ifdef CONFIG_OMAP2_DSS_COLLECT_IRQ_STATS
3645 dss_debugfs_create_file("dispc_irq", dispc_dump_irqs);
3646#endif
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003647 return 0;
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003648
3649err_runtime_get:
3650 pm_runtime_disable(&pdev->dev);
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003651 clk_put(dispc.dss_clk);
archit tanejaaffe3602011-02-23 08:41:03 +00003652 return r;
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003653}
3654
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +02003655static int __exit omap_dispchw_remove(struct platform_device *pdev)
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003656{
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003657 pm_runtime_disable(&pdev->dev);
3658
3659 clk_put(dispc.dss_clk);
3660
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003661 return 0;
3662}
3663
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003664static int dispc_runtime_suspend(struct device *dev)
3665{
3666 dispc_save_context();
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003667
3668 return 0;
3669}
3670
3671static int dispc_runtime_resume(struct device *dev)
3672{
Tomi Valkeinen49ea86f2011-06-01 15:54:06 +03003673 dispc_restore_context();
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003674
3675 return 0;
3676}
3677
3678static const struct dev_pm_ops dispc_pm_ops = {
3679 .runtime_suspend = dispc_runtime_suspend,
3680 .runtime_resume = dispc_runtime_resume,
3681};
3682
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003683static struct platform_driver omap_dispchw_driver = {
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +02003684 .remove = __exit_p(omap_dispchw_remove),
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003685 .driver = {
3686 .name = "omapdss_dispc",
3687 .owner = THIS_MODULE,
Tomi Valkeinen4fbafaf2011-05-27 10:52:19 +03003688 .pm = &dispc_pm_ops,
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003689 },
3690};
3691
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +02003692int __init dispc_init_platform_driver(void)
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003693{
Tomi Valkeinen11436e12012-03-07 12:53:18 +02003694 return platform_driver_probe(&omap_dispchw_driver, omap_dispchw_probe);
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003695}
3696
Tomi Valkeinen6e7e8f02012-02-17 17:41:13 +02003697void __exit dispc_uninit_platform_driver(void)
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003698{
Tomi Valkeinen04c742c2012-02-23 15:32:37 +02003699 platform_driver_unregister(&omap_dispchw_driver);
Senthilvadivu Guruswamy060b6d92011-01-24 06:22:00 +00003700}