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Jerome Glisse771fe6b2009-06-05 14:42:42 +02001/*
2 * Copyright 2009 Jerome Glisse.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the
7 * "Software"), to deal in the Software without restriction, including
8 * without limitation the rights to use, copy, modify, merge, publish,
9 * distribute, sub license, and/or sell copies of the Software, and to
10 * permit persons to whom the Software is furnished to do so, subject to
11 * the following conditions:
12 *
13 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
14 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
15 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
16 * THE COPYRIGHT HOLDERS, AUTHORS AND/OR ITS SUPPLIERS BE LIABLE FOR ANY CLAIM,
17 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
18 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
19 * USE OR OTHER DEALINGS IN THE SOFTWARE.
20 *
21 * The above copyright notice and this permission notice (including the
22 * next paragraph) shall be included in all copies or substantial portions
23 * of the Software.
24 *
25 */
26/*
27 * Authors:
28 * Jerome Glisse <glisse@freedesktop.org>
29 * Thomas Hellstrom <thomas-at-tungstengraphics-dot-com>
30 * Dave Airlie
31 */
32#include <linux/list.h>
Tejun Heo5a0e3ad2010-03-24 17:04:11 +090033#include <linux/slab.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020034#include <drm/drmP.h>
David Howells760285e2012-10-02 18:01:07 +010035#include <drm/radeon_drm.h>
Jerome Glisse771fe6b2009-06-05 14:42:42 +020036#include "radeon.h"
Dave Airlie99ee7fa2010-11-23 11:47:49 +100037#include "radeon_trace.h"
Jerome Glisse771fe6b2009-06-05 14:42:42 +020038
Jerome Glisse771fe6b2009-06-05 14:42:42 +020039
40int radeon_ttm_init(struct radeon_device *rdev);
41void radeon_ttm_fini(struct radeon_device *rdev);
Jerome Glisse4c788672009-11-20 14:29:23 +010042static void radeon_bo_clear_surface_reg(struct radeon_bo *bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020043
44/*
45 * To exclude mutual BO access we rely on bo_reserve exclusion, as all
46 * function are calling it.
47 */
48
Marek Olšák67e8e3f2014-03-02 00:56:18 +010049static void radeon_update_memory_usage(struct radeon_bo *bo,
50 unsigned mem_type, int sign)
51{
52 struct radeon_device *rdev = bo->rdev;
53 u64 size = (u64)bo->tbo.num_pages << PAGE_SHIFT;
54
55 switch (mem_type) {
56 case TTM_PL_TT:
57 if (sign > 0)
58 atomic64_add(size, &rdev->gtt_usage);
59 else
60 atomic64_sub(size, &rdev->gtt_usage);
61 break;
62 case TTM_PL_VRAM:
63 if (sign > 0)
64 atomic64_add(size, &rdev->vram_usage);
65 else
66 atomic64_sub(size, &rdev->vram_usage);
67 break;
68 }
69}
70
Jerome Glisse4c788672009-11-20 14:29:23 +010071static void radeon_ttm_bo_destroy(struct ttm_buffer_object *tbo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +020072{
Jerome Glisse4c788672009-11-20 14:29:23 +010073 struct radeon_bo *bo;
74
75 bo = container_of(tbo, struct radeon_bo, tbo);
Marek Olšák67e8e3f2014-03-02 00:56:18 +010076
77 radeon_update_memory_usage(bo, bo->tbo.mem.mem_type, -1);
Christian König341cb9e2014-08-07 09:36:03 +020078 radeon_mn_unregister(bo);
Marek Olšák67e8e3f2014-03-02 00:56:18 +010079
Jerome Glisse4c788672009-11-20 14:29:23 +010080 mutex_lock(&bo->rdev->gem.mutex);
81 list_del_init(&bo->list);
82 mutex_unlock(&bo->rdev->gem.mutex);
83 radeon_bo_clear_surface_reg(bo);
Christian Königc265f242014-07-18 09:24:54 +020084 WARN_ON(!list_empty(&bo->va));
Daniel Vetter441921d2011-02-18 17:59:16 +010085 drm_gem_object_release(&bo->gem_base);
Jerome Glisse4c788672009-11-20 14:29:23 +010086 kfree(bo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +020087}
88
Jerome Glissed03d8582009-12-14 21:02:09 +010089bool radeon_ttm_bo_is_radeon_bo(struct ttm_buffer_object *bo)
90{
91 if (bo->destroy == &radeon_ttm_bo_destroy)
92 return true;
93 return false;
94}
95
Jerome Glisse312ea8d2009-12-07 15:52:58 +010096void radeon_ttm_placement_from_domain(struct radeon_bo *rbo, u32 domain)
97{
Lauri Kasanendeadcb32014-04-02 20:33:42 +030098 u32 c = 0, i;
Jerome Glisse312ea8d2009-12-07 15:52:58 +010099
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100100 rbo->placement.placement = rbo->placements;
Alex Deucher20707872013-01-17 13:10:50 -0500101 rbo->placement.busy_placement = rbo->placements;
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900102 if (domain & RADEON_GEM_DOMAIN_VRAM) {
103 /* Try placing BOs which don't need CPU access outside of the
104 * CPU accessible part of VRAM
105 */
106 if ((rbo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
107 rbo->rdev->mc.visible_vram_size < rbo->rdev->mc.real_vram_size) {
108 rbo->placements[c].fpfn =
109 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
110 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
111 TTM_PL_FLAG_UNCACHED |
112 TTM_PL_FLAG_VRAM;
113 }
114
115 rbo->placements[c].fpfn = 0;
Christian Königf1217ed2014-08-27 13:16:04 +0200116 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
117 TTM_PL_FLAG_UNCACHED |
118 TTM_PL_FLAG_VRAM;
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900119 }
Christian Königf1217ed2014-08-27 13:16:04 +0200120
Jerome Glisse0d0b3e72012-11-28 13:47:55 -0500121 if (domain & RADEON_GEM_DOMAIN_GTT) {
Michel Dänzer02376d82014-07-17 19:01:08 +0900122 if (rbo->flags & RADEON_GEM_GTT_UC) {
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900123 rbo->placements[c].fpfn = 0;
Christian Königf1217ed2014-08-27 13:16:04 +0200124 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
125 TTM_PL_FLAG_TT;
126
Michel Dänzer02376d82014-07-17 19:01:08 +0900127 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
128 (rbo->rdev->flags & RADEON_IS_AGP)) {
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900129 rbo->placements[c].fpfn = 0;
Christian Königf1217ed2014-08-27 13:16:04 +0200130 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
131 TTM_PL_FLAG_UNCACHED |
Michel Dänzer02376d82014-07-17 19:01:08 +0900132 TTM_PL_FLAG_TT;
Jerome Glisse0d0b3e72012-11-28 13:47:55 -0500133 } else {
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900134 rbo->placements[c].fpfn = 0;
Christian Königf1217ed2014-08-27 13:16:04 +0200135 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
136 TTM_PL_FLAG_TT;
Jerome Glisse0d0b3e72012-11-28 13:47:55 -0500137 }
138 }
Christian Königf1217ed2014-08-27 13:16:04 +0200139
Jerome Glisse0d0b3e72012-11-28 13:47:55 -0500140 if (domain & RADEON_GEM_DOMAIN_CPU) {
Michel Dänzer02376d82014-07-17 19:01:08 +0900141 if (rbo->flags & RADEON_GEM_GTT_UC) {
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900142 rbo->placements[c].fpfn = 0;
Christian Königf1217ed2014-08-27 13:16:04 +0200143 rbo->placements[c++].flags = TTM_PL_FLAG_UNCACHED |
144 TTM_PL_FLAG_SYSTEM;
145
Michel Dänzer02376d82014-07-17 19:01:08 +0900146 } else if ((rbo->flags & RADEON_GEM_GTT_WC) ||
147 rbo->rdev->flags & RADEON_IS_AGP) {
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900148 rbo->placements[c].fpfn = 0;
Christian Königf1217ed2014-08-27 13:16:04 +0200149 rbo->placements[c++].flags = TTM_PL_FLAG_WC |
150 TTM_PL_FLAG_UNCACHED |
Michel Dänzer02376d82014-07-17 19:01:08 +0900151 TTM_PL_FLAG_SYSTEM;
Jerome Glisse0d0b3e72012-11-28 13:47:55 -0500152 } else {
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900153 rbo->placements[c].fpfn = 0;
Christian Königf1217ed2014-08-27 13:16:04 +0200154 rbo->placements[c++].flags = TTM_PL_FLAG_CACHED |
155 TTM_PL_FLAG_SYSTEM;
Jerome Glisse0d0b3e72012-11-28 13:47:55 -0500156 }
157 }
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900158 if (!c) {
159 rbo->placements[c].fpfn = 0;
Christian Königf1217ed2014-08-27 13:16:04 +0200160 rbo->placements[c++].flags = TTM_PL_MASK_CACHING |
161 TTM_PL_FLAG_SYSTEM;
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900162 }
Christian Königf1217ed2014-08-27 13:16:04 +0200163
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100164 rbo->placement.num_placement = c;
165 rbo->placement.num_busy_placement = c;
Lauri Kasanendeadcb32014-04-02 20:33:42 +0300166
Christian Königf1217ed2014-08-27 13:16:04 +0200167 for (i = 0; i < c; ++i) {
Michel Dänzerc8584032014-08-28 15:56:00 +0900168 if ((rbo->flags & RADEON_GEM_CPU_ACCESS) &&
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900169 (rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
170 !rbo->placements[i].fpfn)
Michel Dänzerc8584032014-08-28 15:56:00 +0900171 rbo->placements[i].lpfn =
172 rbo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
173 else
174 rbo->placements[i].lpfn = 0;
Christian Königf1217ed2014-08-27 13:16:04 +0200175 }
176
Lauri Kasanendeadcb32014-04-02 20:33:42 +0300177 /*
178 * Use two-ended allocation depending on the buffer size to
179 * improve fragmentation quality.
180 * 512kb was measured as the most optimal number.
181 */
Michel Dänzera8b5ebe2014-10-28 18:35:02 +0900182 if (rbo->tbo.mem.size > 512 * 1024) {
Lauri Kasanendeadcb32014-04-02 20:33:42 +0300183 for (i = 0; i < c; i++) {
Christian Königf1217ed2014-08-27 13:16:04 +0200184 rbo->placements[i].flags |= TTM_PL_FLAG_TOPDOWN;
Lauri Kasanendeadcb32014-04-02 20:33:42 +0300185 }
186 }
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100187}
188
Daniel Vetter441921d2011-02-18 17:59:16 +0100189int radeon_bo_create(struct radeon_device *rdev,
Maarten Lankhorst831b6962014-09-18 14:11:56 +0200190 unsigned long size, int byte_align, bool kernel,
191 u32 domain, u32 flags, struct sg_table *sg,
192 struct reservation_object *resv,
193 struct radeon_bo **bo_ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200194{
Jerome Glisse4c788672009-11-20 14:29:23 +0100195 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200196 enum ttm_bo_type type;
Jerome Glisse93225b02010-12-03 16:38:19 -0500197 unsigned long page_align = roundup(byte_align, PAGE_SIZE) >> PAGE_SHIFT;
Jerome Glisse57de4ba2011-11-11 15:42:57 -0500198 size_t acc_size;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200199 int r;
200
Daniel Vetter441921d2011-02-18 17:59:16 +0100201 size = ALIGN(size, PAGE_SIZE);
202
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200203 if (kernel) {
204 type = ttm_bo_type_kernel;
Alex Deucher40f5cf92012-05-10 18:33:13 -0400205 } else if (sg) {
206 type = ttm_bo_type_sg;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200207 } else {
208 type = ttm_bo_type_device;
209 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100210 *bo_ptr = NULL;
Michel Dänzer2b66b502010-11-09 11:50:05 +0100211
Jerome Glisse57de4ba2011-11-11 15:42:57 -0500212 acc_size = ttm_bo_dma_acc_size(&rdev->mman.bdev, size,
213 sizeof(struct radeon_bo));
214
Jerome Glisse4c788672009-11-20 14:29:23 +0100215 bo = kzalloc(sizeof(struct radeon_bo), GFP_KERNEL);
216 if (bo == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200217 return -ENOMEM;
Daniel Vetter441921d2011-02-18 17:59:16 +0100218 r = drm_gem_object_init(rdev->ddev, &bo->gem_base, size);
219 if (unlikely(r)) {
220 kfree(bo);
221 return r;
222 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100223 bo->rdev = rdev;
Jerome Glisse4c788672009-11-20 14:29:23 +0100224 bo->surface_reg = -1;
225 INIT_LIST_HEAD(&bo->list);
Jerome Glisse721604a2012-01-05 22:11:05 -0500226 INIT_LIST_HEAD(&bo->va);
Marek Olšákbda72d52014-03-02 00:56:17 +0100227 bo->initial_domain = domain & (RADEON_GEM_DOMAIN_VRAM |
228 RADEON_GEM_DOMAIN_GTT |
229 RADEON_GEM_DOMAIN_CPU);
Michel Dänzer02376d82014-07-17 19:01:08 +0900230
231 bo->flags = flags;
232 /* PCI GART is always snooped */
233 if (!(rdev->flags & RADEON_IS_PCIE))
234 bo->flags &= ~(RADEON_GEM_GTT_WC | RADEON_GEM_GTT_UC);
235
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100236 radeon_ttm_placement_from_domain(bo, domain);
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100237 /* Kernel allocation are uninterruptible */
Christian Königdb7fce32012-05-11 14:57:18 +0200238 down_read(&rdev->pm.mclk_lock);
Jerome Glisse1fb107f2009-12-10 17:16:28 +0100239 r = ttm_bo_init(&rdev->mman.bdev, &bo->tbo, size, type,
Marcin Slusarz0b91c4a2012-11-06 21:49:51 +0000240 &bo->placement, page_align, !kernel, NULL,
Maarten Lankhorst831b6962014-09-18 14:11:56 +0200241 acc_size, sg, resv, &radeon_ttm_bo_destroy);
Christian Königdb7fce32012-05-11 14:57:18 +0200242 up_read(&rdev->pm.mclk_lock);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200243 if (unlikely(r != 0)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200244 return r;
245 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100246 *bo_ptr = bo;
Daniel Vetter441921d2011-02-18 17:59:16 +0100247
Dave Airlie99ee7fa2010-11-23 11:47:49 +1000248 trace_radeon_bo_create(bo);
Daniel Vetter441921d2011-02-18 17:59:16 +0100249
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200250 return 0;
251}
252
Jerome Glisse4c788672009-11-20 14:29:23 +0100253int radeon_bo_kmap(struct radeon_bo *bo, void **ptr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200254{
Jerome Glisse4c788672009-11-20 14:29:23 +0100255 bool is_iomem;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200256 int r;
257
Jerome Glisse4c788672009-11-20 14:29:23 +0100258 if (bo->kptr) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200259 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100260 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200261 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200262 return 0;
263 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100264 r = ttm_bo_kmap(&bo->tbo, 0, bo->tbo.num_pages, &bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200265 if (r) {
266 return r;
267 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100268 bo->kptr = ttm_kmap_obj_virtual(&bo->kmap, &is_iomem);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200269 if (ptr) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100270 *ptr = bo->kptr;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200271 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100272 radeon_bo_check_tiling(bo, 0, 0);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200273 return 0;
274}
275
Jerome Glisse4c788672009-11-20 14:29:23 +0100276void radeon_bo_kunmap(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200277{
Jerome Glisse4c788672009-11-20 14:29:23 +0100278 if (bo->kptr == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200279 return;
Jerome Glisse4c788672009-11-20 14:29:23 +0100280 bo->kptr = NULL;
281 radeon_bo_check_tiling(bo, 0, 0);
282 ttm_bo_kunmap(&bo->kmap);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200283}
284
Christian König512d8af2014-07-30 21:04:56 +0200285struct radeon_bo *radeon_bo_ref(struct radeon_bo *bo)
286{
287 if (bo == NULL)
288 return NULL;
289
290 ttm_bo_reference(&bo->tbo);
291 return bo;
292}
293
Jerome Glisse4c788672009-11-20 14:29:23 +0100294void radeon_bo_unref(struct radeon_bo **bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200295{
Jerome Glisse4c788672009-11-20 14:29:23 +0100296 struct ttm_buffer_object *tbo;
Dave Airlief4b7fb92010-04-29 18:37:59 +1000297 struct radeon_device *rdev;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200298
Jerome Glisse4c788672009-11-20 14:29:23 +0100299 if ((*bo) == NULL)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200300 return;
Dave Airlief4b7fb92010-04-29 18:37:59 +1000301 rdev = (*bo)->rdev;
Jerome Glisse4c788672009-11-20 14:29:23 +0100302 tbo = &((*bo)->tbo);
303 ttm_bo_unref(&tbo);
304 if (tbo == NULL)
305 *bo = NULL;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200306}
307
Michel Dänzerc4353012012-03-14 17:12:41 +0100308int radeon_bo_pin_restricted(struct radeon_bo *bo, u32 domain, u64 max_offset,
309 u64 *gpu_addr)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200310{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100311 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200312
Christian Königf72a113a2014-08-07 09:36:00 +0200313 if (radeon_ttm_tt_has_userptr(bo->tbo.ttm))
314 return -EPERM;
315
Jerome Glisse4c788672009-11-20 14:29:23 +0100316 if (bo->pin_count) {
317 bo->pin_count++;
318 if (gpu_addr)
319 *gpu_addr = radeon_bo_gpu_offset(bo);
Michel Dänzerd9366222012-03-28 08:52:32 +0200320
321 if (max_offset != 0) {
322 u64 domain_start;
323
324 if (domain == RADEON_GEM_DOMAIN_VRAM)
325 domain_start = bo->rdev->mc.vram_start;
326 else
327 domain_start = bo->rdev->mc.gtt_start;
Michel Dänzere199fd42012-03-29 16:47:43 +0200328 WARN_ON_ONCE(max_offset <
329 (radeon_bo_gpu_offset(bo) - domain_start));
Michel Dänzerd9366222012-03-28 08:52:32 +0200330 }
331
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200332 return 0;
333 }
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100334 radeon_ttm_placement_from_domain(bo, domain);
Christian Königf1217ed2014-08-27 13:16:04 +0200335 for (i = 0; i < bo->placement.num_placement; i++) {
Michel Dänzer3ca82da2010-03-26 19:18:55 +0000336 /* force to pin into visible video ram */
Michel Dänzerb76ee672014-09-09 10:09:23 +0900337 if ((bo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
Alex Deucherf266f042014-08-28 10:59:05 -0400338 !(bo->flags & RADEON_GEM_NO_CPU_ACCESS) &&
Michel Dänzerb76ee672014-09-09 10:09:23 +0900339 (!max_offset || max_offset > bo->rdev->mc.visible_vram_size))
340 bo->placements[i].lpfn =
341 bo->rdev->mc.visible_vram_size >> PAGE_SHIFT;
Christian Königf1217ed2014-08-27 13:16:04 +0200342 else
Michel Dänzerb76ee672014-09-09 10:09:23 +0900343 bo->placements[i].lpfn = max_offset >> PAGE_SHIFT;
Michel Dänzerc4353012012-03-14 17:12:41 +0100344
Christian Königf1217ed2014-08-27 13:16:04 +0200345 bo->placements[i].flags |= TTM_PL_FLAG_NO_EVICT;
Michel Dänzerc4353012012-03-14 17:12:41 +0100346 }
Christian Königf1217ed2014-08-27 13:16:04 +0200347
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000348 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
Jerome Glisse4c788672009-11-20 14:29:23 +0100349 if (likely(r == 0)) {
350 bo->pin_count = 1;
351 if (gpu_addr != NULL)
352 *gpu_addr = radeon_bo_gpu_offset(bo);
Alex Deucher71ecc972014-07-17 12:09:25 -0400353 if (domain == RADEON_GEM_DOMAIN_VRAM)
354 bo->rdev->vram_pin_size += radeon_bo_size(bo);
355 else
356 bo->rdev->gart_pin_size += radeon_bo_size(bo);
357 } else {
Jerome Glisse4c788672009-11-20 14:29:23 +0100358 dev_err(bo->rdev->dev, "%p pin failed\n", bo);
Alex Deucher71ecc972014-07-17 12:09:25 -0400359 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200360 return r;
361}
362
Michel Dänzerc4353012012-03-14 17:12:41 +0100363int radeon_bo_pin(struct radeon_bo *bo, u32 domain, u64 *gpu_addr)
364{
365 return radeon_bo_pin_restricted(bo, domain, 0, gpu_addr);
366}
367
Jerome Glisse4c788672009-11-20 14:29:23 +0100368int radeon_bo_unpin(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200369{
Jerome Glisse312ea8d2009-12-07 15:52:58 +0100370 int r, i;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200371
Jerome Glisse4c788672009-11-20 14:29:23 +0100372 if (!bo->pin_count) {
373 dev_warn(bo->rdev->dev, "%p unpin not necessary\n", bo);
374 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200375 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100376 bo->pin_count--;
377 if (bo->pin_count)
378 return 0;
Christian Königf1217ed2014-08-27 13:16:04 +0200379 for (i = 0; i < bo->placement.num_placement; i++) {
380 bo->placements[i].lpfn = 0;
381 bo->placements[i].flags &= ~TTM_PL_FLAG_NO_EVICT;
382 }
Maarten Lankhorst97a875c2012-11-28 11:25:44 +0000383 r = ttm_bo_validate(&bo->tbo, &bo->placement, false, false);
Alex Deucher71ecc972014-07-17 12:09:25 -0400384 if (likely(r == 0)) {
385 if (bo->tbo.mem.mem_type == TTM_PL_VRAM)
386 bo->rdev->vram_pin_size -= radeon_bo_size(bo);
387 else
388 bo->rdev->gart_pin_size -= radeon_bo_size(bo);
389 } else {
Jerome Glisse4c788672009-11-20 14:29:23 +0100390 dev_err(bo->rdev->dev, "%p validate failed for unpin\n", bo);
Alex Deucher71ecc972014-07-17 12:09:25 -0400391 }
Thomas Hellstrom5cc6fba2009-12-07 18:36:19 +0100392 return r;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200393}
394
Jerome Glisse4c788672009-11-20 14:29:23 +0100395int radeon_bo_evict_vram(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200396{
Dave Airlied796d842010-01-25 13:08:08 +1000397 /* late 2.6.33 fix IGP hibernate - we need pm ops to do this correct */
398 if (0 && (rdev->flags & RADEON_IS_IGP)) {
Alex Deucher06b64762010-01-05 11:27:29 -0500399 if (rdev->mc.igp_sideport_enabled == false)
400 /* Useless to evict on IGP chips */
401 return 0;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200402 }
403 return ttm_bo_evict_mm(&rdev->mman.bdev, TTM_PL_VRAM);
404}
405
Jerome Glisse4c788672009-11-20 14:29:23 +0100406void radeon_bo_force_delete(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200407{
Jerome Glisse4c788672009-11-20 14:29:23 +0100408 struct radeon_bo *bo, *n;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200409
410 if (list_empty(&rdev->gem.objects)) {
411 return;
412 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100413 dev_err(rdev->dev, "Userspace still has active objects !\n");
414 list_for_each_entry_safe(bo, n, &rdev->gem.objects, list) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200415 mutex_lock(&rdev->ddev->struct_mutex);
Jerome Glisse4c788672009-11-20 14:29:23 +0100416 dev_err(rdev->dev, "%p %p %lu %lu force free\n",
Daniel Vetter31c36032011-02-18 17:59:18 +0100417 &bo->gem_base, bo, (unsigned long)bo->gem_base.size,
418 *((unsigned long *)&bo->gem_base.refcount));
Jerome Glisse4c788672009-11-20 14:29:23 +0100419 mutex_lock(&bo->rdev->gem.mutex);
420 list_del_init(&bo->list);
421 mutex_unlock(&bo->rdev->gem.mutex);
Dave Airlie91132d62011-03-01 13:40:06 +1000422 /* this should unref the ttm bo */
Daniel Vetter31c36032011-02-18 17:59:18 +0100423 drm_gem_object_unreference(&bo->gem_base);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200424 mutex_unlock(&rdev->ddev->struct_mutex);
425 }
426}
427
Jerome Glisse4c788672009-11-20 14:29:23 +0100428int radeon_bo_init(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200429{
Jerome Glissea4d68272009-09-11 13:00:43 +0200430 /* Add an MTRR for the VRAM */
Samuel Lia0a53aa2013-04-08 17:25:47 -0400431 if (!rdev->fastfb_working) {
Andy Lutomirski07ebea22013-05-13 23:58:45 +0000432 rdev->mc.vram_mtrr = arch_phys_wc_add(rdev->mc.aper_base,
433 rdev->mc.aper_size);
Samuel Lia0a53aa2013-04-08 17:25:47 -0400434 }
Jerome Glissea4d68272009-09-11 13:00:43 +0200435 DRM_INFO("Detected VRAM RAM=%lluM, BAR=%lluM\n",
436 rdev->mc.mc_vram_size >> 20,
437 (unsigned long long)rdev->mc.aper_size >> 20);
438 DRM_INFO("RAM width %dbits %cDR\n",
439 rdev->mc.vram_width, rdev->mc.vram_is_ddr ? 'D' : 'S');
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200440 return radeon_ttm_init(rdev);
441}
442
Jerome Glisse4c788672009-11-20 14:29:23 +0100443void radeon_bo_fini(struct radeon_device *rdev)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200444{
445 radeon_ttm_fini(rdev);
Andy Lutomirski07ebea22013-05-13 23:58:45 +0000446 arch_phys_wc_del(rdev->mc.vram_mtrr);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200447}
448
Marek Olšák19dff562014-03-02 00:56:22 +0100449/* Returns how many bytes TTM can move per IB.
450 */
451static u64 radeon_bo_get_threshold_for_moves(struct radeon_device *rdev)
452{
453 u64 real_vram_size = rdev->mc.real_vram_size;
454 u64 vram_usage = atomic64_read(&rdev->vram_usage);
455
456 /* This function is based on the current VRAM usage.
457 *
458 * - If all of VRAM is free, allow relocating the number of bytes that
459 * is equal to 1/4 of the size of VRAM for this IB.
460
461 * - If more than one half of VRAM is occupied, only allow relocating
462 * 1 MB of data for this IB.
463 *
464 * - From 0 to one half of used VRAM, the threshold decreases
465 * linearly.
466 * __________________
467 * 1/4 of -|\ |
468 * VRAM | \ |
469 * | \ |
470 * | \ |
471 * | \ |
472 * | \ |
473 * | \ |
474 * | \________|1 MB
475 * |----------------|
476 * VRAM 0 % 100 %
477 * used used
478 *
479 * Note: It's a threshold, not a limit. The threshold must be crossed
480 * for buffer relocations to stop, so any buffer of an arbitrary size
481 * can be moved as long as the threshold isn't crossed before
482 * the relocation takes place. We don't want to disable buffer
483 * relocations completely.
484 *
485 * The idea is that buffers should be placed in VRAM at creation time
486 * and TTM should only do a minimum number of relocations during
487 * command submission. In practice, you need to submit at least
488 * a dozen IBs to move all buffers to VRAM if they are in GTT.
489 *
490 * Also, things can get pretty crazy under memory pressure and actual
491 * VRAM usage can change a lot, so playing safe even at 50% does
492 * consistently increase performance.
493 */
494
495 u64 half_vram = real_vram_size >> 1;
496 u64 half_free_vram = vram_usage >= half_vram ? 0 : half_vram - vram_usage;
497 u64 bytes_moved_threshold = half_free_vram >> 1;
498 return max(bytes_moved_threshold, 1024*1024ull);
499}
500
501int radeon_bo_list_validate(struct radeon_device *rdev,
502 struct ww_acquire_ctx *ticket,
Maarten Lankhorstecff6652013-06-27 13:48:17 +0200503 struct list_head *head, int ring)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200504{
Christian König1d0c0942014-11-27 14:48:42 +0100505 struct radeon_bo_list *lobj;
Jerome Glisse4c788672009-11-20 14:29:23 +0100506 struct radeon_bo *bo;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200507 int r;
Marek Olšák19dff562014-03-02 00:56:22 +0100508 u64 bytes_moved = 0, initial_bytes_moved;
509 u64 bytes_moved_threshold = radeon_bo_get_threshold_for_moves(rdev);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200510
Christian Königaa350712014-12-03 15:46:48 +0100511 r = ttm_eu_reserve_buffers(ticket, head, true, NULL);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200512 if (unlikely(r != 0)) {
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200513 return r;
514 }
Marek Olšák19dff562014-03-02 00:56:22 +0100515
Thomas Hellstrom147666f2010-11-17 12:38:32 +0000516 list_for_each_entry(lobj, head, tv.head) {
Christian Königdf0af442014-03-03 12:38:08 +0100517 bo = lobj->robj;
Jerome Glisse4c788672009-11-20 14:29:23 +0100518 if (!bo->pin_count) {
Christian Königce6758c2014-06-02 17:33:07 +0200519 u32 domain = lobj->prefered_domains;
Christian König38527522014-08-21 12:18:12 +0200520 u32 allowed = lobj->allowed_domains;
Marek Olšák19dff562014-03-02 00:56:22 +0100521 u32 current_domain =
522 radeon_mem_type_to_domain(bo->tbo.mem.mem_type);
523
Thomas Hellstrom355a7012014-11-20 09:56:25 +0100524 WARN_ONCE(bo->gem_base.dumb,
525 "GPU use of dumb buffer is illegal.\n");
526
Marek Olšák19dff562014-03-02 00:56:22 +0100527 /* Check if this buffer will be moved and don't move it
528 * if we have moved too many buffers for this IB already.
529 *
530 * Note that this allows moving at least one buffer of
531 * any size, because it doesn't take the current "bo"
532 * into account. We don't want to disallow buffer moves
533 * completely.
534 */
Christian König38527522014-08-21 12:18:12 +0200535 if ((allowed & current_domain) != 0 &&
Marek Olšák19dff562014-03-02 00:56:22 +0100536 (domain & current_domain) == 0 && /* will be moved */
537 bytes_moved > bytes_moved_threshold) {
538 /* don't move it */
539 domain = current_domain;
540 }
541
Alex Deucher20707872013-01-17 13:10:50 -0500542 retry:
543 radeon_ttm_placement_from_domain(bo, domain);
Christian Königf2ba57b2013-04-08 12:41:29 +0200544 if (ring == R600_RING_TYPE_UVD_INDEX)
Christian König38527522014-08-21 12:18:12 +0200545 radeon_uvd_force_into_uvd_segment(bo, allowed);
Marek Olšák19dff562014-03-02 00:56:22 +0100546
547 initial_bytes_moved = atomic64_read(&rdev->num_bytes_moved);
548 r = ttm_bo_validate(&bo->tbo, &bo->placement, true, false);
549 bytes_moved += atomic64_read(&rdev->num_bytes_moved) -
550 initial_bytes_moved;
551
Michel Dänzere376573f2010-07-08 12:43:28 +1000552 if (unlikely(r)) {
Christian Königce6758c2014-06-02 17:33:07 +0200553 if (r != -ERESTARTSYS &&
554 domain != lobj->allowed_domains) {
555 domain = lobj->allowed_domains;
Alex Deucher20707872013-01-17 13:10:50 -0500556 goto retry;
557 }
Maarten Lankhorst1b6e5fd2013-07-10 12:26:56 +0200558 ttm_eu_backoff_reservation(ticket, head);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200559 return r;
Michel Dänzere376573f2010-07-08 12:43:28 +1000560 }
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200561 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100562 lobj->gpu_offset = radeon_bo_gpu_offset(bo);
563 lobj->tiling_flags = bo->tiling_flags;
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200564 }
565 return 0;
566}
567
Jerome Glisse4c788672009-11-20 14:29:23 +0100568int radeon_bo_fbdev_mmap(struct radeon_bo *bo,
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200569 struct vm_area_struct *vma)
570{
Jerome Glisse4c788672009-11-20 14:29:23 +0100571 return ttm_fbdev_mmap(vma, &bo->tbo);
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200572}
573
Dave Airlie550e2d92009-12-09 14:15:38 +1000574int radeon_bo_get_surface_reg(struct radeon_bo *bo)
Jerome Glisse771fe6b2009-06-05 14:42:42 +0200575{
Jerome Glisse4c788672009-11-20 14:29:23 +0100576 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000577 struct radeon_surface_reg *reg;
Jerome Glisse4c788672009-11-20 14:29:23 +0100578 struct radeon_bo *old_object;
Dave Airliee024e112009-06-24 09:48:08 +1000579 int steal;
580 int i;
581
Maarten Lankhorst977c38d2013-06-27 13:48:26 +0200582 lockdep_assert_held(&bo->tbo.resv->lock.base);
Jerome Glisse4c788672009-11-20 14:29:23 +0100583
584 if (!bo->tiling_flags)
Dave Airliee024e112009-06-24 09:48:08 +1000585 return 0;
586
Jerome Glisse4c788672009-11-20 14:29:23 +0100587 if (bo->surface_reg >= 0) {
588 reg = &rdev->surface_regs[bo->surface_reg];
589 i = bo->surface_reg;
Dave Airliee024e112009-06-24 09:48:08 +1000590 goto out;
591 }
592
593 steal = -1;
594 for (i = 0; i < RADEON_GEM_MAX_SURFACES; i++) {
595
596 reg = &rdev->surface_regs[i];
Jerome Glisse4c788672009-11-20 14:29:23 +0100597 if (!reg->bo)
Dave Airliee024e112009-06-24 09:48:08 +1000598 break;
599
Jerome Glisse4c788672009-11-20 14:29:23 +0100600 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000601 if (old_object->pin_count == 0)
602 steal = i;
603 }
604
605 /* if we are all out */
606 if (i == RADEON_GEM_MAX_SURFACES) {
607 if (steal == -1)
608 return -ENOMEM;
609 /* find someone with a surface reg and nuke their BO */
610 reg = &rdev->surface_regs[steal];
Jerome Glisse4c788672009-11-20 14:29:23 +0100611 old_object = reg->bo;
Dave Airliee024e112009-06-24 09:48:08 +1000612 /* blow away the mapping */
613 DRM_DEBUG("stealing surface reg %d from %p\n", steal, old_object);
Jerome Glisse4c788672009-11-20 14:29:23 +0100614 ttm_bo_unmap_virtual(&old_object->tbo);
Dave Airliee024e112009-06-24 09:48:08 +1000615 old_object->surface_reg = -1;
616 i = steal;
617 }
618
Jerome Glisse4c788672009-11-20 14:29:23 +0100619 bo->surface_reg = i;
620 reg->bo = bo;
Dave Airliee024e112009-06-24 09:48:08 +1000621
622out:
Jerome Glisse4c788672009-11-20 14:29:23 +0100623 radeon_set_surface_reg(rdev, i, bo->tiling_flags, bo->pitch,
Ben Skeggsd961db72010-08-05 10:48:18 +1000624 bo->tbo.mem.start << PAGE_SHIFT,
Jerome Glisse4c788672009-11-20 14:29:23 +0100625 bo->tbo.num_pages << PAGE_SHIFT);
Dave Airliee024e112009-06-24 09:48:08 +1000626 return 0;
627}
628
Jerome Glisse4c788672009-11-20 14:29:23 +0100629static void radeon_bo_clear_surface_reg(struct radeon_bo *bo)
Dave Airliee024e112009-06-24 09:48:08 +1000630{
Jerome Glisse4c788672009-11-20 14:29:23 +0100631 struct radeon_device *rdev = bo->rdev;
Dave Airliee024e112009-06-24 09:48:08 +1000632 struct radeon_surface_reg *reg;
633
Jerome Glisse4c788672009-11-20 14:29:23 +0100634 if (bo->surface_reg == -1)
Dave Airliee024e112009-06-24 09:48:08 +1000635 return;
636
Jerome Glisse4c788672009-11-20 14:29:23 +0100637 reg = &rdev->surface_regs[bo->surface_reg];
638 radeon_clear_surface_reg(rdev, bo->surface_reg);
Dave Airliee024e112009-06-24 09:48:08 +1000639
Jerome Glisse4c788672009-11-20 14:29:23 +0100640 reg->bo = NULL;
641 bo->surface_reg = -1;
Dave Airliee024e112009-06-24 09:48:08 +1000642}
643
Jerome Glisse4c788672009-11-20 14:29:23 +0100644int radeon_bo_set_tiling_flags(struct radeon_bo *bo,
645 uint32_t tiling_flags, uint32_t pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000646{
Jerome Glisse285484e2011-12-16 17:03:42 -0500647 struct radeon_device *rdev = bo->rdev;
Jerome Glisse4c788672009-11-20 14:29:23 +0100648 int r;
649
Jerome Glisse285484e2011-12-16 17:03:42 -0500650 if (rdev->family >= CHIP_CEDAR) {
651 unsigned bankw, bankh, mtaspect, tilesplit, stilesplit;
652
653 bankw = (tiling_flags >> RADEON_TILING_EG_BANKW_SHIFT) & RADEON_TILING_EG_BANKW_MASK;
654 bankh = (tiling_flags >> RADEON_TILING_EG_BANKH_SHIFT) & RADEON_TILING_EG_BANKH_MASK;
655 mtaspect = (tiling_flags >> RADEON_TILING_EG_MACRO_TILE_ASPECT_SHIFT) & RADEON_TILING_EG_MACRO_TILE_ASPECT_MASK;
656 tilesplit = (tiling_flags >> RADEON_TILING_EG_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_TILE_SPLIT_MASK;
657 stilesplit = (tiling_flags >> RADEON_TILING_EG_STENCIL_TILE_SPLIT_SHIFT) & RADEON_TILING_EG_STENCIL_TILE_SPLIT_MASK;
658 switch (bankw) {
659 case 0:
660 case 1:
661 case 2:
662 case 4:
663 case 8:
664 break;
665 default:
666 return -EINVAL;
667 }
668 switch (bankh) {
669 case 0:
670 case 1:
671 case 2:
672 case 4:
673 case 8:
674 break;
675 default:
676 return -EINVAL;
677 }
678 switch (mtaspect) {
679 case 0:
680 case 1:
681 case 2:
682 case 4:
683 case 8:
684 break;
685 default:
686 return -EINVAL;
687 }
688 if (tilesplit > 6) {
689 return -EINVAL;
690 }
691 if (stilesplit > 6) {
692 return -EINVAL;
693 }
694 }
Jerome Glisse4c788672009-11-20 14:29:23 +0100695 r = radeon_bo_reserve(bo, false);
696 if (unlikely(r != 0))
697 return r;
698 bo->tiling_flags = tiling_flags;
699 bo->pitch = pitch;
700 radeon_bo_unreserve(bo);
701 return 0;
Dave Airliee024e112009-06-24 09:48:08 +1000702}
703
Jerome Glisse4c788672009-11-20 14:29:23 +0100704void radeon_bo_get_tiling_flags(struct radeon_bo *bo,
705 uint32_t *tiling_flags,
706 uint32_t *pitch)
Dave Airliee024e112009-06-24 09:48:08 +1000707{
Maarten Lankhorst977c38d2013-06-27 13:48:26 +0200708 lockdep_assert_held(&bo->tbo.resv->lock.base);
709
Dave Airliee024e112009-06-24 09:48:08 +1000710 if (tiling_flags)
Jerome Glisse4c788672009-11-20 14:29:23 +0100711 *tiling_flags = bo->tiling_flags;
Dave Airliee024e112009-06-24 09:48:08 +1000712 if (pitch)
Jerome Glisse4c788672009-11-20 14:29:23 +0100713 *pitch = bo->pitch;
Dave Airliee024e112009-06-24 09:48:08 +1000714}
715
Jerome Glisse4c788672009-11-20 14:29:23 +0100716int radeon_bo_check_tiling(struct radeon_bo *bo, bool has_moved,
717 bool force_drop)
Dave Airliee024e112009-06-24 09:48:08 +1000718{
Maarten Lankhorst977c38d2013-06-27 13:48:26 +0200719 if (!force_drop)
720 lockdep_assert_held(&bo->tbo.resv->lock.base);
Jerome Glisse4c788672009-11-20 14:29:23 +0100721
722 if (!(bo->tiling_flags & RADEON_TILING_SURFACE))
Dave Airliee024e112009-06-24 09:48:08 +1000723 return 0;
724
725 if (force_drop) {
Jerome Glisse4c788672009-11-20 14:29:23 +0100726 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000727 return 0;
728 }
729
Jerome Glisse4c788672009-11-20 14:29:23 +0100730 if (bo->tbo.mem.mem_type != TTM_PL_VRAM) {
Dave Airliee024e112009-06-24 09:48:08 +1000731 if (!has_moved)
732 return 0;
733
Jerome Glisse4c788672009-11-20 14:29:23 +0100734 if (bo->surface_reg >= 0)
735 radeon_bo_clear_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000736 return 0;
737 }
738
Jerome Glisse4c788672009-11-20 14:29:23 +0100739 if ((bo->surface_reg >= 0) && !has_moved)
Dave Airliee024e112009-06-24 09:48:08 +1000740 return 0;
741
Jerome Glisse4c788672009-11-20 14:29:23 +0100742 return radeon_bo_get_surface_reg(bo);
Dave Airliee024e112009-06-24 09:48:08 +1000743}
744
745void radeon_bo_move_notify(struct ttm_buffer_object *bo,
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100746 struct ttm_mem_reg *new_mem)
Dave Airliee024e112009-06-24 09:48:08 +1000747{
Jerome Glissed03d8582009-12-14 21:02:09 +0100748 struct radeon_bo *rbo;
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100749
Jerome Glissed03d8582009-12-14 21:02:09 +0100750 if (!radeon_ttm_bo_is_radeon_bo(bo))
751 return;
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100752
Jerome Glissed03d8582009-12-14 21:02:09 +0100753 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100754 radeon_bo_check_tiling(rbo, 0, 1);
Jerome Glisse721604a2012-01-05 22:11:05 -0500755 radeon_vm_bo_invalidate(rbo->rdev, rbo);
Marek Olšák67e8e3f2014-03-02 00:56:18 +0100756
757 /* update statistics */
758 if (!new_mem)
759 return;
760
761 radeon_update_memory_usage(rbo, bo->mem.mem_type, -1);
762 radeon_update_memory_usage(rbo, new_mem->mem_type, 1);
Dave Airliee024e112009-06-24 09:48:08 +1000763}
764
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200765int radeon_bo_fault_reserve_notify(struct ttm_buffer_object *bo)
Dave Airliee024e112009-06-24 09:48:08 +1000766{
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200767 struct radeon_device *rdev;
Jerome Glissed03d8582009-12-14 21:02:09 +0100768 struct radeon_bo *rbo;
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900769 unsigned long offset, size, lpfn;
770 int i, r;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200771
Jerome Glissed03d8582009-12-14 21:02:09 +0100772 if (!radeon_ttm_bo_is_radeon_bo(bo))
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200773 return 0;
Jerome Glissed03d8582009-12-14 21:02:09 +0100774 rbo = container_of(bo, struct radeon_bo, tbo);
Jerome Glisse4c788672009-11-20 14:29:23 +0100775 radeon_bo_check_tiling(rbo, 0, 0);
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200776 rdev = rbo->rdev;
Christian König54409252014-05-05 18:40:12 +0200777 if (bo->mem.mem_type != TTM_PL_VRAM)
778 return 0;
779
780 size = bo->mem.num_pages << PAGE_SHIFT;
781 offset = bo->mem.start << PAGE_SHIFT;
782 if ((offset + size) <= rdev->mc.visible_vram_size)
783 return 0;
784
785 /* hurrah the memory is not visible ! */
786 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_VRAM);
Michel Dänzerc9da4a42014-10-10 12:28:36 +0900787 lpfn = rdev->mc.visible_vram_size >> PAGE_SHIFT;
788 for (i = 0; i < rbo->placement.num_placement; i++) {
789 /* Force into visible VRAM */
790 if ((rbo->placements[i].flags & TTM_PL_FLAG_VRAM) &&
791 (!rbo->placements[i].lpfn || rbo->placements[i].lpfn > lpfn))
792 rbo->placements[i].lpfn = lpfn;
793 }
Christian König54409252014-05-05 18:40:12 +0200794 r = ttm_bo_validate(bo, &rbo->placement, false, false);
795 if (unlikely(r == -ENOMEM)) {
796 radeon_ttm_placement_from_domain(rbo, RADEON_GEM_DOMAIN_GTT);
797 return ttm_bo_validate(bo, &rbo->placement, false, false);
798 } else if (unlikely(r != 0)) {
799 return r;
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200800 }
Christian König54409252014-05-05 18:40:12 +0200801
802 offset = bo->mem.start << PAGE_SHIFT;
803 /* this should never happen */
804 if ((offset + size) > rdev->mc.visible_vram_size)
805 return -EINVAL;
806
Jerome Glisse0a2d50e2010-04-09 14:39:24 +0200807 return 0;
Dave Airliee024e112009-06-24 09:48:08 +1000808}
Andi Kleence580fa2011-10-13 16:08:47 -0700809
Dave Airlie83f30d02011-10-27 18:15:10 +0200810int radeon_bo_wait(struct radeon_bo *bo, u32 *mem_type, bool no_wait)
Andi Kleence580fa2011-10-13 16:08:47 -0700811{
812 int r;
813
Michele CURTI12432352014-05-19 11:18:52 -0400814 r = ttm_bo_reserve(&bo->tbo, true, no_wait, false, NULL);
Andi Kleence580fa2011-10-13 16:08:47 -0700815 if (unlikely(r != 0))
816 return r;
Andi Kleence580fa2011-10-13 16:08:47 -0700817 if (mem_type)
818 *mem_type = bo->tbo.mem.mem_type;
Maarten Lankhorstf2c24b82014-04-02 17:14:48 +0200819
820 r = ttm_bo_wait(&bo->tbo, true, true, no_wait);
Andi Kleence580fa2011-10-13 16:08:47 -0700821 ttm_bo_unreserve(&bo->tbo);
822 return r;
823}
Christian König587cdda2014-11-19 14:01:23 +0100824
825/**
826 * radeon_bo_fence - add fence to buffer object
827 *
828 * @bo: buffer object in question
829 * @fence: fence to add
830 * @shared: true if fence should be added shared
831 *
832 */
833void radeon_bo_fence(struct radeon_bo *bo, struct radeon_fence *fence,
834 bool shared)
835{
836 struct reservation_object *resv = bo->tbo.resv;
837
838 if (shared)
839 reservation_object_add_shared_fence(resv, &fence->base);
840 else
841 reservation_object_add_excl_fence(resv, &fence->base);
842}