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Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001/*
2 * Copyright (C) 2015 Microchip Technology
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17#include <linux/version.h>
18#include <linux/module.h>
19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
21#include <linux/ethtool.h>
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000022#include <linux/usb.h>
23#include <linux/crc32.h>
24#include <linux/signal.h>
25#include <linux/slab.h>
26#include <linux/if_vlan.h>
27#include <linux/uaccess.h>
28#include <linux/list.h>
29#include <linux/ip.h>
30#include <linux/ipv6.h>
31#include <linux/mdio.h>
Andrew Lunnc6e970a2017-03-28 23:45:06 +020032#include <linux/phy.h>
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000033#include <net/ip6_checksum.h>
Woojung Huhcc89c322016-11-01 20:02:00 +000034#include <linux/interrupt.h>
35#include <linux/irqdomain.h>
36#include <linux/irq.h>
37#include <linux/irqchip/chained_irq.h>
Woojung.Huh@microchip.combdfba55e2015-09-16 23:41:07 +000038#include <linux/microchipphy.h>
Raghuram Chary J89b36fb2018-04-28 11:33:14 +053039#include <linux/phy_fixed.h>
Phil Elwell1827b062018-04-19 17:59:39 +010040#include <linux/of_mdio.h>
Phil Elwell760db292018-04-19 17:59:38 +010041#include <linux/of_net.h>
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000042#include "lan78xx.h"
43
44#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
45#define DRIVER_DESC "LAN78XX USB 3.0 Gigabit Ethernet Devices"
46#define DRIVER_NAME "lan78xx"
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000047
48#define TX_TIMEOUT_JIFFIES (5 * HZ)
49#define THROTTLE_JIFFIES (HZ / 8)
50#define UNLINK_TIMEOUT_MS 3
51
52#define RX_MAX_QUEUE_MEMORY (60 * 1518)
53
54#define SS_USB_PKT_SIZE (1024)
55#define HS_USB_PKT_SIZE (512)
56#define FS_USB_PKT_SIZE (64)
57
58#define MAX_RX_FIFO_SIZE (12 * 1024)
59#define MAX_TX_FIFO_SIZE (12 * 1024)
60#define DEFAULT_BURST_CAP_SIZE (MAX_TX_FIFO_SIZE)
61#define DEFAULT_BULK_IN_DELAY (0x0800)
62#define MAX_SINGLE_PACKET_SIZE (9000)
63#define DEFAULT_TX_CSUM_ENABLE (true)
64#define DEFAULT_RX_CSUM_ENABLE (true)
65#define DEFAULT_TSO_CSUM_ENABLE (true)
66#define DEFAULT_VLAN_FILTER_ENABLE (true)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000067#define TX_OVERHEAD (8)
68#define RXW_PADDING 2
69
70#define LAN78XX_USB_VENDOR_ID (0x0424)
71#define LAN7800_USB_PRODUCT_ID (0x7800)
72#define LAN7850_USB_PRODUCT_ID (0x7850)
Woojung Huh02dc1f32016-12-07 20:26:25 +000073#define LAN7801_USB_PRODUCT_ID (0x7801)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000074#define LAN78XX_EEPROM_MAGIC (0x78A5)
75#define LAN78XX_OTP_MAGIC (0x78F3)
76
77#define MII_READ 1
78#define MII_WRITE 0
79
80#define EEPROM_INDICATOR (0xA5)
81#define EEPROM_MAC_OFFSET (0x01)
82#define MAX_EEPROM_SIZE 512
83#define OTP_INDICATOR_1 (0xF3)
84#define OTP_INDICATOR_2 (0xF7)
85
86#define WAKE_ALL (WAKE_PHY | WAKE_UCAST | \
87 WAKE_MCAST | WAKE_BCAST | \
88 WAKE_ARP | WAKE_MAGIC)
89
90/* USB related defines */
91#define BULK_IN_PIPE 1
92#define BULK_OUT_PIPE 2
93
94/* default autosuspend delay (mSec)*/
95#define DEFAULT_AUTOSUSPEND_DELAY (10 * 1000)
96
Woojung Huh20ff5562016-03-16 22:10:40 +000097/* statistic update interval (mSec) */
98#define STAT_UPDATE_TIMER (1 * 1000)
99
Woojung Huhcc89c322016-11-01 20:02:00 +0000100/* defines interrupts from interrupt EP */
101#define MAX_INT_EP (32)
102#define INT_EP_INTEP (31)
103#define INT_EP_OTP_WR_DONE (28)
104#define INT_EP_EEE_TX_LPI_START (26)
105#define INT_EP_EEE_TX_LPI_STOP (25)
106#define INT_EP_EEE_RX_LPI (24)
107#define INT_EP_MAC_RESET_TIMEOUT (23)
108#define INT_EP_RDFO (22)
109#define INT_EP_TXE (21)
110#define INT_EP_USB_STATUS (20)
111#define INT_EP_TX_DIS (19)
112#define INT_EP_RX_DIS (18)
113#define INT_EP_PHY (17)
114#define INT_EP_DP (16)
115#define INT_EP_MAC_ERR (15)
116#define INT_EP_TDFU (14)
117#define INT_EP_TDFO (13)
118#define INT_EP_UTX (12)
119#define INT_EP_GPIO_11 (11)
120#define INT_EP_GPIO_10 (10)
121#define INT_EP_GPIO_9 (9)
122#define INT_EP_GPIO_8 (8)
123#define INT_EP_GPIO_7 (7)
124#define INT_EP_GPIO_6 (6)
125#define INT_EP_GPIO_5 (5)
126#define INT_EP_GPIO_4 (4)
127#define INT_EP_GPIO_3 (3)
128#define INT_EP_GPIO_2 (2)
129#define INT_EP_GPIO_1 (1)
130#define INT_EP_GPIO_0 (0)
131
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000132static const char lan78xx_gstrings[][ETH_GSTRING_LEN] = {
133 "RX FCS Errors",
134 "RX Alignment Errors",
135 "Rx Fragment Errors",
136 "RX Jabber Errors",
137 "RX Undersize Frame Errors",
138 "RX Oversize Frame Errors",
139 "RX Dropped Frames",
140 "RX Unicast Byte Count",
141 "RX Broadcast Byte Count",
142 "RX Multicast Byte Count",
143 "RX Unicast Frames",
144 "RX Broadcast Frames",
145 "RX Multicast Frames",
146 "RX Pause Frames",
147 "RX 64 Byte Frames",
148 "RX 65 - 127 Byte Frames",
149 "RX 128 - 255 Byte Frames",
150 "RX 256 - 511 Bytes Frames",
151 "RX 512 - 1023 Byte Frames",
152 "RX 1024 - 1518 Byte Frames",
153 "RX Greater 1518 Byte Frames",
154 "EEE RX LPI Transitions",
155 "EEE RX LPI Time",
156 "TX FCS Errors",
157 "TX Excess Deferral Errors",
158 "TX Carrier Errors",
159 "TX Bad Byte Count",
160 "TX Single Collisions",
161 "TX Multiple Collisions",
162 "TX Excessive Collision",
163 "TX Late Collisions",
164 "TX Unicast Byte Count",
165 "TX Broadcast Byte Count",
166 "TX Multicast Byte Count",
167 "TX Unicast Frames",
168 "TX Broadcast Frames",
169 "TX Multicast Frames",
170 "TX Pause Frames",
171 "TX 64 Byte Frames",
172 "TX 65 - 127 Byte Frames",
173 "TX 128 - 255 Byte Frames",
174 "TX 256 - 511 Bytes Frames",
175 "TX 512 - 1023 Byte Frames",
176 "TX 1024 - 1518 Byte Frames",
177 "TX Greater 1518 Byte Frames",
178 "EEE TX LPI Transitions",
179 "EEE TX LPI Time",
180};
181
182struct lan78xx_statstage {
183 u32 rx_fcs_errors;
184 u32 rx_alignment_errors;
185 u32 rx_fragment_errors;
186 u32 rx_jabber_errors;
187 u32 rx_undersize_frame_errors;
188 u32 rx_oversize_frame_errors;
189 u32 rx_dropped_frames;
190 u32 rx_unicast_byte_count;
191 u32 rx_broadcast_byte_count;
192 u32 rx_multicast_byte_count;
193 u32 rx_unicast_frames;
194 u32 rx_broadcast_frames;
195 u32 rx_multicast_frames;
196 u32 rx_pause_frames;
197 u32 rx_64_byte_frames;
198 u32 rx_65_127_byte_frames;
199 u32 rx_128_255_byte_frames;
200 u32 rx_256_511_bytes_frames;
201 u32 rx_512_1023_byte_frames;
202 u32 rx_1024_1518_byte_frames;
203 u32 rx_greater_1518_byte_frames;
204 u32 eee_rx_lpi_transitions;
205 u32 eee_rx_lpi_time;
206 u32 tx_fcs_errors;
207 u32 tx_excess_deferral_errors;
208 u32 tx_carrier_errors;
209 u32 tx_bad_byte_count;
210 u32 tx_single_collisions;
211 u32 tx_multiple_collisions;
212 u32 tx_excessive_collision;
213 u32 tx_late_collisions;
214 u32 tx_unicast_byte_count;
215 u32 tx_broadcast_byte_count;
216 u32 tx_multicast_byte_count;
217 u32 tx_unicast_frames;
218 u32 tx_broadcast_frames;
219 u32 tx_multicast_frames;
220 u32 tx_pause_frames;
221 u32 tx_64_byte_frames;
222 u32 tx_65_127_byte_frames;
223 u32 tx_128_255_byte_frames;
224 u32 tx_256_511_bytes_frames;
225 u32 tx_512_1023_byte_frames;
226 u32 tx_1024_1518_byte_frames;
227 u32 tx_greater_1518_byte_frames;
228 u32 eee_tx_lpi_transitions;
229 u32 eee_tx_lpi_time;
230};
231
Woojung Huh20ff5562016-03-16 22:10:40 +0000232struct lan78xx_statstage64 {
233 u64 rx_fcs_errors;
234 u64 rx_alignment_errors;
235 u64 rx_fragment_errors;
236 u64 rx_jabber_errors;
237 u64 rx_undersize_frame_errors;
238 u64 rx_oversize_frame_errors;
239 u64 rx_dropped_frames;
240 u64 rx_unicast_byte_count;
241 u64 rx_broadcast_byte_count;
242 u64 rx_multicast_byte_count;
243 u64 rx_unicast_frames;
244 u64 rx_broadcast_frames;
245 u64 rx_multicast_frames;
246 u64 rx_pause_frames;
247 u64 rx_64_byte_frames;
248 u64 rx_65_127_byte_frames;
249 u64 rx_128_255_byte_frames;
250 u64 rx_256_511_bytes_frames;
251 u64 rx_512_1023_byte_frames;
252 u64 rx_1024_1518_byte_frames;
253 u64 rx_greater_1518_byte_frames;
254 u64 eee_rx_lpi_transitions;
255 u64 eee_rx_lpi_time;
256 u64 tx_fcs_errors;
257 u64 tx_excess_deferral_errors;
258 u64 tx_carrier_errors;
259 u64 tx_bad_byte_count;
260 u64 tx_single_collisions;
261 u64 tx_multiple_collisions;
262 u64 tx_excessive_collision;
263 u64 tx_late_collisions;
264 u64 tx_unicast_byte_count;
265 u64 tx_broadcast_byte_count;
266 u64 tx_multicast_byte_count;
267 u64 tx_unicast_frames;
268 u64 tx_broadcast_frames;
269 u64 tx_multicast_frames;
270 u64 tx_pause_frames;
271 u64 tx_64_byte_frames;
272 u64 tx_65_127_byte_frames;
273 u64 tx_128_255_byte_frames;
274 u64 tx_256_511_bytes_frames;
275 u64 tx_512_1023_byte_frames;
276 u64 tx_1024_1518_byte_frames;
277 u64 tx_greater_1518_byte_frames;
278 u64 eee_tx_lpi_transitions;
279 u64 eee_tx_lpi_time;
280};
281
Raghuram Chary J49621862018-04-20 11:43:50 +0530282static u32 lan78xx_regs[] = {
283 ID_REV,
284 INT_STS,
285 HW_CFG,
286 PMT_CTL,
287 E2P_CMD,
288 E2P_DATA,
289 USB_STATUS,
290 VLAN_TYPE,
291 MAC_CR,
292 MAC_RX,
293 MAC_TX,
294 FLOW,
295 ERR_STS,
296 MII_ACC,
297 MII_DATA,
298 EEE_TX_LPI_REQ_DLY,
299 EEE_TW_TX_SYS,
300 EEE_TX_LPI_REM_DLY,
301 WUCSR
302};
303
304#define PHY_REG_SIZE (32 * sizeof(u32))
305
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000306struct lan78xx_net;
307
308struct lan78xx_priv {
309 struct lan78xx_net *dev;
310 u32 rfe_ctl;
311 u32 mchash_table[DP_SEL_VHF_HASH_LEN]; /* multicat hash table */
312 u32 pfilter_table[NUM_OF_MAF][2]; /* perfect filter table */
313 u32 vlan_table[DP_SEL_VHF_VLAN_LEN];
314 struct mutex dataport_mutex; /* for dataport access */
315 spinlock_t rfe_ctl_lock; /* for rfe register access */
316 struct work_struct set_multicast;
317 struct work_struct set_vlan;
318 u32 wol;
319};
320
321enum skb_state {
322 illegal = 0,
323 tx_start,
324 tx_done,
325 rx_start,
326 rx_done,
327 rx_cleanup,
328 unlink_start
329};
330
331struct skb_data { /* skb->cb is one of these */
332 struct urb *urb;
333 struct lan78xx_net *dev;
334 enum skb_state state;
335 size_t length;
Woojung Huh74d79a22016-04-25 22:22:32 +0000336 int num_of_packet;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000337};
338
339struct usb_context {
340 struct usb_ctrlrequest req;
341 struct lan78xx_net *dev;
342};
343
344#define EVENT_TX_HALT 0
345#define EVENT_RX_HALT 1
346#define EVENT_RX_MEMORY 2
347#define EVENT_STS_SPLIT 3
348#define EVENT_LINK_RESET 4
349#define EVENT_RX_PAUSED 5
350#define EVENT_DEV_WAKING 6
351#define EVENT_DEV_ASLEEP 7
352#define EVENT_DEV_OPEN 8
Woojung Huh20ff5562016-03-16 22:10:40 +0000353#define EVENT_STAT_UPDATE 9
354
355struct statstage {
356 struct mutex access_lock; /* for stats access */
357 struct lan78xx_statstage saved;
358 struct lan78xx_statstage rollover_count;
359 struct lan78xx_statstage rollover_max;
360 struct lan78xx_statstage64 curr_stat;
361};
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000362
Woojung Huhcc89c322016-11-01 20:02:00 +0000363struct irq_domain_data {
364 struct irq_domain *irqdomain;
365 unsigned int phyirq;
366 struct irq_chip *irqchip;
367 irq_flow_handler_t irq_handler;
368 u32 irqenable;
369 struct mutex irq_lock; /* for irq bus access */
370};
371
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000372struct lan78xx_net {
373 struct net_device *net;
374 struct usb_device *udev;
375 struct usb_interface *intf;
376 void *driver_priv;
377
378 int rx_qlen;
379 int tx_qlen;
380 struct sk_buff_head rxq;
381 struct sk_buff_head txq;
382 struct sk_buff_head done;
383 struct sk_buff_head rxq_pause;
384 struct sk_buff_head txq_pend;
385
386 struct tasklet_struct bh;
387 struct delayed_work wq;
388
389 struct usb_host_endpoint *ep_blkin;
390 struct usb_host_endpoint *ep_blkout;
391 struct usb_host_endpoint *ep_intr;
392
393 int msg_enable;
394
395 struct urb *urb_intr;
396 struct usb_anchor deferred;
397
398 struct mutex phy_mutex; /* for phy access */
399 unsigned pipe_in, pipe_out, pipe_intr;
400
401 u32 hard_mtu; /* count any extra framing */
402 size_t rx_urb_size; /* size for rx urbs */
403
404 unsigned long flags;
405
406 wait_queue_head_t *wait;
407 unsigned char suspend_count;
408
409 unsigned maxpacket;
410 struct timer_list delay;
Woojung Huh20ff5562016-03-16 22:10:40 +0000411 struct timer_list stat_monitor;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000412
413 unsigned long data[5];
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000414
415 int link_on;
416 u8 mdix_ctrl;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +0000417
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000418 u32 chipid;
419 u32 chiprev;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +0000420 struct mii_bus *mdiobus;
Woojung Huh02dc1f32016-12-07 20:26:25 +0000421 phy_interface_t interface;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +0000422
423 int fc_autoneg;
424 u8 fc_request_control;
Woojung Huh20ff5562016-03-16 22:10:40 +0000425
426 int delta;
427 struct statstage stats;
Woojung Huhcc89c322016-11-01 20:02:00 +0000428
429 struct irq_domain_data domain_data;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000430};
431
Woojung Huh02dc1f32016-12-07 20:26:25 +0000432/* define external phy id */
433#define PHY_LAN8835 (0x0007C130)
434#define PHY_KSZ9031RNX (0x00221620)
435
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000436/* use ethtool to change the level for any given device */
437static int msg_level = -1;
438module_param(msg_level, int, 0);
439MODULE_PARM_DESC(msg_level, "Override default message level");
440
441static int lan78xx_read_reg(struct lan78xx_net *dev, u32 index, u32 *data)
442{
443 u32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);
444 int ret;
445
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000446 if (!buf)
447 return -ENOMEM;
448
449 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
450 USB_VENDOR_REQUEST_READ_REGISTER,
451 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
452 0, index, buf, 4, USB_CTRL_GET_TIMEOUT);
453 if (likely(ret >= 0)) {
454 le32_to_cpus(buf);
455 *data = *buf;
456 } else {
457 netdev_warn(dev->net,
458 "Failed to read register index 0x%08x. ret = %d",
459 index, ret);
460 }
461
462 kfree(buf);
463
464 return ret;
465}
466
467static int lan78xx_write_reg(struct lan78xx_net *dev, u32 index, u32 data)
468{
469 u32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);
470 int ret;
471
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000472 if (!buf)
473 return -ENOMEM;
474
475 *buf = data;
476 cpu_to_le32s(buf);
477
478 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
479 USB_VENDOR_REQUEST_WRITE_REGISTER,
480 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
481 0, index, buf, 4, USB_CTRL_SET_TIMEOUT);
482 if (unlikely(ret < 0)) {
483 netdev_warn(dev->net,
484 "Failed to write register index 0x%08x. ret = %d",
485 index, ret);
486 }
487
488 kfree(buf);
489
490 return ret;
491}
492
493static int lan78xx_read_stats(struct lan78xx_net *dev,
494 struct lan78xx_statstage *data)
495{
496 int ret = 0;
497 int i;
498 struct lan78xx_statstage *stats;
499 u32 *src;
500 u32 *dst;
501
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000502 stats = kmalloc(sizeof(*stats), GFP_KERNEL);
503 if (!stats)
504 return -ENOMEM;
505
506 ret = usb_control_msg(dev->udev,
507 usb_rcvctrlpipe(dev->udev, 0),
508 USB_VENDOR_REQUEST_GET_STATS,
509 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
510 0,
511 0,
512 (void *)stats,
513 sizeof(*stats),
514 USB_CTRL_SET_TIMEOUT);
515 if (likely(ret >= 0)) {
516 src = (u32 *)stats;
517 dst = (u32 *)data;
518 for (i = 0; i < sizeof(*stats)/sizeof(u32); i++) {
519 le32_to_cpus(&src[i]);
520 dst[i] = src[i];
521 }
522 } else {
523 netdev_warn(dev->net,
524 "Failed to read stat ret = 0x%x", ret);
525 }
526
527 kfree(stats);
528
529 return ret;
530}
531
Woojung Huh20ff5562016-03-16 22:10:40 +0000532#define check_counter_rollover(struct1, dev_stats, member) { \
533 if (struct1->member < dev_stats.saved.member) \
534 dev_stats.rollover_count.member++; \
535 }
536
537static void lan78xx_check_stat_rollover(struct lan78xx_net *dev,
538 struct lan78xx_statstage *stats)
539{
540 check_counter_rollover(stats, dev->stats, rx_fcs_errors);
541 check_counter_rollover(stats, dev->stats, rx_alignment_errors);
542 check_counter_rollover(stats, dev->stats, rx_fragment_errors);
543 check_counter_rollover(stats, dev->stats, rx_jabber_errors);
544 check_counter_rollover(stats, dev->stats, rx_undersize_frame_errors);
545 check_counter_rollover(stats, dev->stats, rx_oversize_frame_errors);
546 check_counter_rollover(stats, dev->stats, rx_dropped_frames);
547 check_counter_rollover(stats, dev->stats, rx_unicast_byte_count);
548 check_counter_rollover(stats, dev->stats, rx_broadcast_byte_count);
549 check_counter_rollover(stats, dev->stats, rx_multicast_byte_count);
550 check_counter_rollover(stats, dev->stats, rx_unicast_frames);
551 check_counter_rollover(stats, dev->stats, rx_broadcast_frames);
552 check_counter_rollover(stats, dev->stats, rx_multicast_frames);
553 check_counter_rollover(stats, dev->stats, rx_pause_frames);
554 check_counter_rollover(stats, dev->stats, rx_64_byte_frames);
555 check_counter_rollover(stats, dev->stats, rx_65_127_byte_frames);
556 check_counter_rollover(stats, dev->stats, rx_128_255_byte_frames);
557 check_counter_rollover(stats, dev->stats, rx_256_511_bytes_frames);
558 check_counter_rollover(stats, dev->stats, rx_512_1023_byte_frames);
559 check_counter_rollover(stats, dev->stats, rx_1024_1518_byte_frames);
560 check_counter_rollover(stats, dev->stats, rx_greater_1518_byte_frames);
561 check_counter_rollover(stats, dev->stats, eee_rx_lpi_transitions);
562 check_counter_rollover(stats, dev->stats, eee_rx_lpi_time);
563 check_counter_rollover(stats, dev->stats, tx_fcs_errors);
564 check_counter_rollover(stats, dev->stats, tx_excess_deferral_errors);
565 check_counter_rollover(stats, dev->stats, tx_carrier_errors);
566 check_counter_rollover(stats, dev->stats, tx_bad_byte_count);
567 check_counter_rollover(stats, dev->stats, tx_single_collisions);
568 check_counter_rollover(stats, dev->stats, tx_multiple_collisions);
569 check_counter_rollover(stats, dev->stats, tx_excessive_collision);
570 check_counter_rollover(stats, dev->stats, tx_late_collisions);
571 check_counter_rollover(stats, dev->stats, tx_unicast_byte_count);
572 check_counter_rollover(stats, dev->stats, tx_broadcast_byte_count);
573 check_counter_rollover(stats, dev->stats, tx_multicast_byte_count);
574 check_counter_rollover(stats, dev->stats, tx_unicast_frames);
575 check_counter_rollover(stats, dev->stats, tx_broadcast_frames);
576 check_counter_rollover(stats, dev->stats, tx_multicast_frames);
577 check_counter_rollover(stats, dev->stats, tx_pause_frames);
578 check_counter_rollover(stats, dev->stats, tx_64_byte_frames);
579 check_counter_rollover(stats, dev->stats, tx_65_127_byte_frames);
580 check_counter_rollover(stats, dev->stats, tx_128_255_byte_frames);
581 check_counter_rollover(stats, dev->stats, tx_256_511_bytes_frames);
582 check_counter_rollover(stats, dev->stats, tx_512_1023_byte_frames);
583 check_counter_rollover(stats, dev->stats, tx_1024_1518_byte_frames);
584 check_counter_rollover(stats, dev->stats, tx_greater_1518_byte_frames);
585 check_counter_rollover(stats, dev->stats, eee_tx_lpi_transitions);
586 check_counter_rollover(stats, dev->stats, eee_tx_lpi_time);
587
588 memcpy(&dev->stats.saved, stats, sizeof(struct lan78xx_statstage));
589}
590
591static void lan78xx_update_stats(struct lan78xx_net *dev)
592{
593 u32 *p, *count, *max;
594 u64 *data;
595 int i;
596 struct lan78xx_statstage lan78xx_stats;
597
598 if (usb_autopm_get_interface(dev->intf) < 0)
599 return;
600
601 p = (u32 *)&lan78xx_stats;
602 count = (u32 *)&dev->stats.rollover_count;
603 max = (u32 *)&dev->stats.rollover_max;
604 data = (u64 *)&dev->stats.curr_stat;
605
606 mutex_lock(&dev->stats.access_lock);
607
608 if (lan78xx_read_stats(dev, &lan78xx_stats) > 0)
609 lan78xx_check_stat_rollover(dev, &lan78xx_stats);
610
611 for (i = 0; i < (sizeof(lan78xx_stats) / (sizeof(u32))); i++)
612 data[i] = (u64)p[i] + ((u64)count[i] * ((u64)max[i] + 1));
613
614 mutex_unlock(&dev->stats.access_lock);
615
616 usb_autopm_put_interface(dev->intf);
617}
618
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000619/* Loop until the read is completed with timeout called with phy_mutex held */
620static int lan78xx_phy_wait_not_busy(struct lan78xx_net *dev)
621{
622 unsigned long start_time = jiffies;
623 u32 val;
624 int ret;
625
626 do {
627 ret = lan78xx_read_reg(dev, MII_ACC, &val);
628 if (unlikely(ret < 0))
629 return -EIO;
630
631 if (!(val & MII_ACC_MII_BUSY_))
632 return 0;
633 } while (!time_after(jiffies, start_time + HZ));
634
635 return -EIO;
636}
637
638static inline u32 mii_access(int id, int index, int read)
639{
640 u32 ret;
641
642 ret = ((u32)id << MII_ACC_PHY_ADDR_SHIFT_) & MII_ACC_PHY_ADDR_MASK_;
643 ret |= ((u32)index << MII_ACC_MIIRINDA_SHIFT_) & MII_ACC_MIIRINDA_MASK_;
644 if (read)
645 ret |= MII_ACC_MII_READ_;
646 else
647 ret |= MII_ACC_MII_WRITE_;
648 ret |= MII_ACC_MII_BUSY_;
649
650 return ret;
651}
652
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000653static int lan78xx_wait_eeprom(struct lan78xx_net *dev)
654{
655 unsigned long start_time = jiffies;
656 u32 val;
657 int ret;
658
659 do {
660 ret = lan78xx_read_reg(dev, E2P_CMD, &val);
661 if (unlikely(ret < 0))
662 return -EIO;
663
664 if (!(val & E2P_CMD_EPC_BUSY_) ||
665 (val & E2P_CMD_EPC_TIMEOUT_))
666 break;
667 usleep_range(40, 100);
668 } while (!time_after(jiffies, start_time + HZ));
669
670 if (val & (E2P_CMD_EPC_TIMEOUT_ | E2P_CMD_EPC_BUSY_)) {
671 netdev_warn(dev->net, "EEPROM read operation timeout");
672 return -EIO;
673 }
674
675 return 0;
676}
677
678static int lan78xx_eeprom_confirm_not_busy(struct lan78xx_net *dev)
679{
680 unsigned long start_time = jiffies;
681 u32 val;
682 int ret;
683
684 do {
685 ret = lan78xx_read_reg(dev, E2P_CMD, &val);
686 if (unlikely(ret < 0))
687 return -EIO;
688
689 if (!(val & E2P_CMD_EPC_BUSY_))
690 return 0;
691
692 usleep_range(40, 100);
693 } while (!time_after(jiffies, start_time + HZ));
694
695 netdev_warn(dev->net, "EEPROM is busy");
696 return -EIO;
697}
698
699static int lan78xx_read_raw_eeprom(struct lan78xx_net *dev, u32 offset,
700 u32 length, u8 *data)
701{
702 u32 val;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000703 u32 saved;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000704 int i, ret;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000705 int retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000706
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000707 /* depends on chip, some EEPROM pins are muxed with LED function.
708 * disable & restore LED function to access EEPROM.
709 */
710 ret = lan78xx_read_reg(dev, HW_CFG, &val);
711 saved = val;
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000712 if (dev->chipid == ID_REV_CHIP_ID_7800_) {
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000713 val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
714 ret = lan78xx_write_reg(dev, HW_CFG, val);
715 }
716
717 retval = lan78xx_eeprom_confirm_not_busy(dev);
718 if (retval)
719 return retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000720
721 for (i = 0; i < length; i++) {
722 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_;
723 val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
724 ret = lan78xx_write_reg(dev, E2P_CMD, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000725 if (unlikely(ret < 0)) {
726 retval = -EIO;
727 goto exit;
728 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000729
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000730 retval = lan78xx_wait_eeprom(dev);
731 if (retval < 0)
732 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000733
734 ret = lan78xx_read_reg(dev, E2P_DATA, &val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000735 if (unlikely(ret < 0)) {
736 retval = -EIO;
737 goto exit;
738 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000739
740 data[i] = val & 0xFF;
741 offset++;
742 }
743
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000744 retval = 0;
745exit:
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000746 if (dev->chipid == ID_REV_CHIP_ID_7800_)
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000747 ret = lan78xx_write_reg(dev, HW_CFG, saved);
748
749 return retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000750}
751
752static int lan78xx_read_eeprom(struct lan78xx_net *dev, u32 offset,
753 u32 length, u8 *data)
754{
755 u8 sig;
756 int ret;
757
758 ret = lan78xx_read_raw_eeprom(dev, 0, 1, &sig);
759 if ((ret == 0) && (sig == EEPROM_INDICATOR))
760 ret = lan78xx_read_raw_eeprom(dev, offset, length, data);
761 else
762 ret = -EINVAL;
763
764 return ret;
765}
766
767static int lan78xx_write_raw_eeprom(struct lan78xx_net *dev, u32 offset,
768 u32 length, u8 *data)
769{
770 u32 val;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000771 u32 saved;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000772 int i, ret;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000773 int retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000774
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000775 /* depends on chip, some EEPROM pins are muxed with LED function.
776 * disable & restore LED function to access EEPROM.
777 */
778 ret = lan78xx_read_reg(dev, HW_CFG, &val);
779 saved = val;
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000780 if (dev->chipid == ID_REV_CHIP_ID_7800_) {
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000781 val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
782 ret = lan78xx_write_reg(dev, HW_CFG, val);
783 }
784
785 retval = lan78xx_eeprom_confirm_not_busy(dev);
786 if (retval)
787 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000788
789 /* Issue write/erase enable command */
790 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_;
791 ret = lan78xx_write_reg(dev, E2P_CMD, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000792 if (unlikely(ret < 0)) {
793 retval = -EIO;
794 goto exit;
795 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000796
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000797 retval = lan78xx_wait_eeprom(dev);
798 if (retval < 0)
799 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000800
801 for (i = 0; i < length; i++) {
802 /* Fill data register */
803 val = data[i];
804 ret = lan78xx_write_reg(dev, E2P_DATA, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000805 if (ret < 0) {
806 retval = -EIO;
807 goto exit;
808 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000809
810 /* Send "write" command */
811 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_;
812 val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
813 ret = lan78xx_write_reg(dev, E2P_CMD, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000814 if (ret < 0) {
815 retval = -EIO;
816 goto exit;
817 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000818
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000819 retval = lan78xx_wait_eeprom(dev);
820 if (retval < 0)
821 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000822
823 offset++;
824 }
825
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000826 retval = 0;
827exit:
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000828 if (dev->chipid == ID_REV_CHIP_ID_7800_)
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000829 ret = lan78xx_write_reg(dev, HW_CFG, saved);
830
831 return retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000832}
833
834static int lan78xx_read_raw_otp(struct lan78xx_net *dev, u32 offset,
835 u32 length, u8 *data)
836{
837 int i;
838 int ret;
839 u32 buf;
840 unsigned long timeout;
841
842 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
843
844 if (buf & OTP_PWR_DN_PWRDN_N_) {
845 /* clear it and wait to be cleared */
846 ret = lan78xx_write_reg(dev, OTP_PWR_DN, 0);
847
848 timeout = jiffies + HZ;
849 do {
850 usleep_range(1, 10);
851 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
852 if (time_after(jiffies, timeout)) {
853 netdev_warn(dev->net,
854 "timeout on OTP_PWR_DN");
855 return -EIO;
856 }
857 } while (buf & OTP_PWR_DN_PWRDN_N_);
858 }
859
860 for (i = 0; i < length; i++) {
861 ret = lan78xx_write_reg(dev, OTP_ADDR1,
862 ((offset + i) >> 8) & OTP_ADDR1_15_11);
863 ret = lan78xx_write_reg(dev, OTP_ADDR2,
864 ((offset + i) & OTP_ADDR2_10_3));
865
866 ret = lan78xx_write_reg(dev, OTP_FUNC_CMD, OTP_FUNC_CMD_READ_);
867 ret = lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
868
869 timeout = jiffies + HZ;
870 do {
871 udelay(1);
872 ret = lan78xx_read_reg(dev, OTP_STATUS, &buf);
873 if (time_after(jiffies, timeout)) {
874 netdev_warn(dev->net,
875 "timeout on OTP_STATUS");
876 return -EIO;
877 }
878 } while (buf & OTP_STATUS_BUSY_);
879
880 ret = lan78xx_read_reg(dev, OTP_RD_DATA, &buf);
881
882 data[i] = (u8)(buf & 0xFF);
883 }
884
885 return 0;
886}
887
Woojung.Huh@microchip.com9fb60662016-01-05 17:29:59 +0000888static int lan78xx_write_raw_otp(struct lan78xx_net *dev, u32 offset,
889 u32 length, u8 *data)
890{
891 int i;
892 int ret;
893 u32 buf;
894 unsigned long timeout;
895
896 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
897
898 if (buf & OTP_PWR_DN_PWRDN_N_) {
899 /* clear it and wait to be cleared */
900 ret = lan78xx_write_reg(dev, OTP_PWR_DN, 0);
901
902 timeout = jiffies + HZ;
903 do {
904 udelay(1);
905 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
906 if (time_after(jiffies, timeout)) {
907 netdev_warn(dev->net,
908 "timeout on OTP_PWR_DN completion");
909 return -EIO;
910 }
911 } while (buf & OTP_PWR_DN_PWRDN_N_);
912 }
913
914 /* set to BYTE program mode */
915 ret = lan78xx_write_reg(dev, OTP_PRGM_MODE, OTP_PRGM_MODE_BYTE_);
916
917 for (i = 0; i < length; i++) {
918 ret = lan78xx_write_reg(dev, OTP_ADDR1,
919 ((offset + i) >> 8) & OTP_ADDR1_15_11);
920 ret = lan78xx_write_reg(dev, OTP_ADDR2,
921 ((offset + i) & OTP_ADDR2_10_3));
922 ret = lan78xx_write_reg(dev, OTP_PRGM_DATA, data[i]);
923 ret = lan78xx_write_reg(dev, OTP_TST_CMD, OTP_TST_CMD_PRGVRFY_);
924 ret = lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
925
926 timeout = jiffies + HZ;
927 do {
928 udelay(1);
929 ret = lan78xx_read_reg(dev, OTP_STATUS, &buf);
930 if (time_after(jiffies, timeout)) {
931 netdev_warn(dev->net,
932 "Timeout on OTP_STATUS completion");
933 return -EIO;
934 }
935 } while (buf & OTP_STATUS_BUSY_);
936 }
937
938 return 0;
939}
940
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000941static int lan78xx_read_otp(struct lan78xx_net *dev, u32 offset,
942 u32 length, u8 *data)
943{
944 u8 sig;
945 int ret;
946
947 ret = lan78xx_read_raw_otp(dev, 0, 1, &sig);
948
949 if (ret == 0) {
950 if (sig == OTP_INDICATOR_1)
951 offset = offset;
952 else if (sig == OTP_INDICATOR_2)
953 offset += 0x100;
954 else
955 ret = -EINVAL;
Phil Elwell4bfc3382018-04-11 10:59:17 +0100956 if (!ret)
957 ret = lan78xx_read_raw_otp(dev, offset, length, data);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000958 }
959
960 return ret;
961}
962
963static int lan78xx_dataport_wait_not_busy(struct lan78xx_net *dev)
964{
965 int i, ret;
966
967 for (i = 0; i < 100; i++) {
968 u32 dp_sel;
969
970 ret = lan78xx_read_reg(dev, DP_SEL, &dp_sel);
971 if (unlikely(ret < 0))
972 return -EIO;
973
974 if (dp_sel & DP_SEL_DPRDY_)
975 return 0;
976
977 usleep_range(40, 100);
978 }
979
980 netdev_warn(dev->net, "lan78xx_dataport_wait_not_busy timed out");
981
982 return -EIO;
983}
984
985static int lan78xx_dataport_write(struct lan78xx_net *dev, u32 ram_select,
986 u32 addr, u32 length, u32 *buf)
987{
988 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
989 u32 dp_sel;
990 int i, ret;
991
992 if (usb_autopm_get_interface(dev->intf) < 0)
993 return 0;
994
995 mutex_lock(&pdata->dataport_mutex);
996
997 ret = lan78xx_dataport_wait_not_busy(dev);
998 if (ret < 0)
999 goto done;
1000
1001 ret = lan78xx_read_reg(dev, DP_SEL, &dp_sel);
1002
1003 dp_sel &= ~DP_SEL_RSEL_MASK_;
1004 dp_sel |= ram_select;
1005 ret = lan78xx_write_reg(dev, DP_SEL, dp_sel);
1006
1007 for (i = 0; i < length; i++) {
1008 ret = lan78xx_write_reg(dev, DP_ADDR, addr + i);
1009
1010 ret = lan78xx_write_reg(dev, DP_DATA, buf[i]);
1011
1012 ret = lan78xx_write_reg(dev, DP_CMD, DP_CMD_WRITE_);
1013
1014 ret = lan78xx_dataport_wait_not_busy(dev);
1015 if (ret < 0)
1016 goto done;
1017 }
1018
1019done:
1020 mutex_unlock(&pdata->dataport_mutex);
1021 usb_autopm_put_interface(dev->intf);
1022
1023 return ret;
1024}
1025
1026static void lan78xx_set_addr_filter(struct lan78xx_priv *pdata,
1027 int index, u8 addr[ETH_ALEN])
1028{
1029 u32 temp;
1030
1031 if ((pdata) && (index > 0) && (index < NUM_OF_MAF)) {
1032 temp = addr[3];
1033 temp = addr[2] | (temp << 8);
1034 temp = addr[1] | (temp << 8);
1035 temp = addr[0] | (temp << 8);
1036 pdata->pfilter_table[index][1] = temp;
1037 temp = addr[5];
1038 temp = addr[4] | (temp << 8);
1039 temp |= MAF_HI_VALID_ | MAF_HI_TYPE_DST_;
1040 pdata->pfilter_table[index][0] = temp;
1041 }
1042}
1043
1044/* returns hash bit number for given MAC address */
1045static inline u32 lan78xx_hash(char addr[ETH_ALEN])
1046{
1047 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
1048}
1049
1050static void lan78xx_deferred_multicast_write(struct work_struct *param)
1051{
1052 struct lan78xx_priv *pdata =
1053 container_of(param, struct lan78xx_priv, set_multicast);
1054 struct lan78xx_net *dev = pdata->dev;
1055 int i;
1056 int ret;
1057
1058 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
1059 pdata->rfe_ctl);
1060
1061 lan78xx_dataport_write(dev, DP_SEL_RSEL_VLAN_DA_, DP_SEL_VHF_VLAN_LEN,
1062 DP_SEL_VHF_HASH_LEN, pdata->mchash_table);
1063
1064 for (i = 1; i < NUM_OF_MAF; i++) {
1065 ret = lan78xx_write_reg(dev, MAF_HI(i), 0);
1066 ret = lan78xx_write_reg(dev, MAF_LO(i),
1067 pdata->pfilter_table[i][1]);
1068 ret = lan78xx_write_reg(dev, MAF_HI(i),
1069 pdata->pfilter_table[i][0]);
1070 }
1071
1072 ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1073}
1074
1075static void lan78xx_set_multicast(struct net_device *netdev)
1076{
1077 struct lan78xx_net *dev = netdev_priv(netdev);
1078 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
1079 unsigned long flags;
1080 int i;
1081
1082 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
1083
1084 pdata->rfe_ctl &= ~(RFE_CTL_UCAST_EN_ | RFE_CTL_MCAST_EN_ |
1085 RFE_CTL_DA_PERFECT_ | RFE_CTL_MCAST_HASH_);
1086
1087 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
1088 pdata->mchash_table[i] = 0;
1089 /* pfilter_table[0] has own HW address */
1090 for (i = 1; i < NUM_OF_MAF; i++) {
1091 pdata->pfilter_table[i][0] =
1092 pdata->pfilter_table[i][1] = 0;
1093 }
1094
1095 pdata->rfe_ctl |= RFE_CTL_BCAST_EN_;
1096
1097 if (dev->net->flags & IFF_PROMISC) {
1098 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled");
1099 pdata->rfe_ctl |= RFE_CTL_MCAST_EN_ | RFE_CTL_UCAST_EN_;
1100 } else {
1101 if (dev->net->flags & IFF_ALLMULTI) {
1102 netif_dbg(dev, drv, dev->net,
1103 "receive all multicast enabled");
1104 pdata->rfe_ctl |= RFE_CTL_MCAST_EN_;
1105 }
1106 }
1107
1108 if (netdev_mc_count(dev->net)) {
1109 struct netdev_hw_addr *ha;
1110 int i;
1111
1112 netif_dbg(dev, drv, dev->net, "receive multicast hash filter");
1113
1114 pdata->rfe_ctl |= RFE_CTL_DA_PERFECT_;
1115
1116 i = 1;
1117 netdev_for_each_mc_addr(ha, netdev) {
1118 /* set first 32 into Perfect Filter */
1119 if (i < 33) {
1120 lan78xx_set_addr_filter(pdata, i, ha->addr);
1121 } else {
1122 u32 bitnum = lan78xx_hash(ha->addr);
1123
1124 pdata->mchash_table[bitnum / 32] |=
1125 (1 << (bitnum % 32));
1126 pdata->rfe_ctl |= RFE_CTL_MCAST_HASH_;
1127 }
1128 i++;
1129 }
1130 }
1131
1132 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
1133
1134 /* defer register writes to a sleepable context */
1135 schedule_work(&pdata->set_multicast);
1136}
1137
1138static int lan78xx_update_flowcontrol(struct lan78xx_net *dev, u8 duplex,
1139 u16 lcladv, u16 rmtadv)
1140{
1141 u32 flow = 0, fct_flow = 0;
1142 int ret;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001143 u8 cap;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001144
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001145 if (dev->fc_autoneg)
1146 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1147 else
1148 cap = dev->fc_request_control;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001149
1150 if (cap & FLOW_CTRL_TX)
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001151 flow |= (FLOW_CR_TX_FCEN_ | 0xFFFF);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001152
1153 if (cap & FLOW_CTRL_RX)
1154 flow |= FLOW_CR_RX_FCEN_;
1155
1156 if (dev->udev->speed == USB_SPEED_SUPER)
1157 fct_flow = 0x817;
1158 else if (dev->udev->speed == USB_SPEED_HIGH)
1159 fct_flow = 0x211;
1160
1161 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s",
1162 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1163 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1164
1165 ret = lan78xx_write_reg(dev, FCT_FLOW, fct_flow);
1166
1167 /* threshold value should be set before enabling flow */
1168 ret = lan78xx_write_reg(dev, FLOW, flow);
1169
1170 return 0;
1171}
1172
1173static int lan78xx_link_reset(struct lan78xx_net *dev)
1174{
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001175 struct phy_device *phydev = dev->net->phydev;
Philippe Reynes6e765102016-10-09 12:07:04 +02001176 struct ethtool_link_ksettings ecmd;
Geert Uytterhoeven99c79ec2015-09-04 12:47:28 +02001177 int ladv, radv, ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001178 u32 buf;
1179
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001180 /* clear LAN78xx interrupt status */
1181 ret = lan78xx_write_reg(dev, INT_STS, INT_STS_PHY_INT_);
1182 if (unlikely(ret < 0))
1183 return -EIO;
1184
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001185 phy_read_status(phydev);
1186
1187 if (!phydev->link && dev->link_on) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001188 dev->link_on = false;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001189
1190 /* reset MAC */
1191 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1192 if (unlikely(ret < 0))
1193 return -EIO;
1194 buf |= MAC_CR_RST_;
1195 ret = lan78xx_write_reg(dev, MAC_CR, buf);
1196 if (unlikely(ret < 0))
1197 return -EIO;
Woojung.Huh@microchip.come4953912016-01-27 22:57:52 +00001198
Woojung Huh20ff5562016-03-16 22:10:40 +00001199 del_timer(&dev->stat_monitor);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001200 } else if (phydev->link && !dev->link_on) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001201 dev->link_on = true;
1202
Philippe Reynes6e765102016-10-09 12:07:04 +02001203 phy_ethtool_ksettings_get(phydev, &ecmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001204
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001205 if (dev->udev->speed == USB_SPEED_SUPER) {
Philippe Reynes6e765102016-10-09 12:07:04 +02001206 if (ecmd.base.speed == 1000) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001207 /* disable U2 */
1208 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
1209 buf &= ~USB_CFG1_DEV_U2_INIT_EN_;
1210 ret = lan78xx_write_reg(dev, USB_CFG1, buf);
1211 /* enable U1 */
1212 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
1213 buf |= USB_CFG1_DEV_U1_INIT_EN_;
1214 ret = lan78xx_write_reg(dev, USB_CFG1, buf);
1215 } else {
1216 /* enable U1 & U2 */
1217 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
1218 buf |= USB_CFG1_DEV_U2_INIT_EN_;
1219 buf |= USB_CFG1_DEV_U1_INIT_EN_;
1220 ret = lan78xx_write_reg(dev, USB_CFG1, buf);
1221 }
1222 }
1223
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001224 ladv = phy_read(phydev, MII_ADVERTISE);
Geert Uytterhoeven99c79ec2015-09-04 12:47:28 +02001225 if (ladv < 0)
1226 return ladv;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001227
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001228 radv = phy_read(phydev, MII_LPA);
Geert Uytterhoeven99c79ec2015-09-04 12:47:28 +02001229 if (radv < 0)
1230 return radv;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001231
1232 netif_dbg(dev, link, dev->net,
1233 "speed: %u duplex: %d anadv: 0x%04x anlpa: 0x%04x",
Philippe Reynes6e765102016-10-09 12:07:04 +02001234 ecmd.base.speed, ecmd.base.duplex, ladv, radv);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001235
Philippe Reynes6e765102016-10-09 12:07:04 +02001236 ret = lan78xx_update_flowcontrol(dev, ecmd.base.duplex, ladv,
1237 radv);
Woojung Huh20ff5562016-03-16 22:10:40 +00001238
1239 if (!timer_pending(&dev->stat_monitor)) {
1240 dev->delta = 1;
1241 mod_timer(&dev->stat_monitor,
1242 jiffies + STAT_UPDATE_TIMER);
1243 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001244 }
1245
1246 return ret;
1247}
1248
1249/* some work can't be done in tasklets, so we use keventd
1250 *
1251 * NOTE: annoying asymmetry: if it's active, schedule_work() fails,
1252 * but tasklet_schedule() doesn't. hope the failure is rare.
1253 */
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08001254static void lan78xx_defer_kevent(struct lan78xx_net *dev, int work)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001255{
1256 set_bit(work, &dev->flags);
1257 if (!schedule_delayed_work(&dev->wq, 0))
1258 netdev_err(dev->net, "kevent %d may have been dropped\n", work);
1259}
1260
1261static void lan78xx_status(struct lan78xx_net *dev, struct urb *urb)
1262{
1263 u32 intdata;
1264
1265 if (urb->actual_length != 4) {
1266 netdev_warn(dev->net,
1267 "unexpected urb length %d", urb->actual_length);
1268 return;
1269 }
1270
1271 memcpy(&intdata, urb->transfer_buffer, 4);
1272 le32_to_cpus(&intdata);
1273
1274 if (intdata & INT_ENP_PHY_INT) {
1275 netif_dbg(dev, link, dev->net, "PHY INTR: 0x%08x\n", intdata);
Woojung Huhcc89c322016-11-01 20:02:00 +00001276 lan78xx_defer_kevent(dev, EVENT_LINK_RESET);
1277
1278 if (dev->domain_data.phyirq > 0)
1279 generic_handle_irq(dev->domain_data.phyirq);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001280 } else
1281 netdev_warn(dev->net,
1282 "unexpected interrupt: 0x%08x\n", intdata);
1283}
1284
1285static int lan78xx_ethtool_get_eeprom_len(struct net_device *netdev)
1286{
1287 return MAX_EEPROM_SIZE;
1288}
1289
1290static int lan78xx_ethtool_get_eeprom(struct net_device *netdev,
1291 struct ethtool_eeprom *ee, u8 *data)
1292{
1293 struct lan78xx_net *dev = netdev_priv(netdev);
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301294 int ret;
1295
1296 ret = usb_autopm_get_interface(dev->intf);
1297 if (ret)
1298 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001299
1300 ee->magic = LAN78XX_EEPROM_MAGIC;
1301
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301302 ret = lan78xx_read_raw_eeprom(dev, ee->offset, ee->len, data);
1303
1304 usb_autopm_put_interface(dev->intf);
1305
1306 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001307}
1308
1309static int lan78xx_ethtool_set_eeprom(struct net_device *netdev,
1310 struct ethtool_eeprom *ee, u8 *data)
1311{
1312 struct lan78xx_net *dev = netdev_priv(netdev);
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301313 int ret;
1314
1315 ret = usb_autopm_get_interface(dev->intf);
1316 if (ret)
1317 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001318
Nisar Sayedc0776822017-09-21 02:36:37 +05301319 /* Invalid EEPROM_INDICATOR at offset zero will result in a failure
1320 * to load data from EEPROM
1321 */
1322 if (ee->magic == LAN78XX_EEPROM_MAGIC)
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301323 ret = lan78xx_write_raw_eeprom(dev, ee->offset, ee->len, data);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001324 else if ((ee->magic == LAN78XX_OTP_MAGIC) &&
1325 (ee->offset == 0) &&
1326 (ee->len == 512) &&
1327 (data[0] == OTP_INDICATOR_1))
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301328 ret = lan78xx_write_raw_otp(dev, ee->offset, ee->len, data);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001329
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301330 usb_autopm_put_interface(dev->intf);
1331
1332 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001333}
1334
1335static void lan78xx_get_strings(struct net_device *netdev, u32 stringset,
1336 u8 *data)
1337{
1338 if (stringset == ETH_SS_STATS)
1339 memcpy(data, lan78xx_gstrings, sizeof(lan78xx_gstrings));
1340}
1341
1342static int lan78xx_get_sset_count(struct net_device *netdev, int sset)
1343{
1344 if (sset == ETH_SS_STATS)
1345 return ARRAY_SIZE(lan78xx_gstrings);
1346 else
1347 return -EOPNOTSUPP;
1348}
1349
1350static void lan78xx_get_stats(struct net_device *netdev,
1351 struct ethtool_stats *stats, u64 *data)
1352{
1353 struct lan78xx_net *dev = netdev_priv(netdev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001354
Woojung Huh20ff5562016-03-16 22:10:40 +00001355 lan78xx_update_stats(dev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001356
Woojung Huh20ff5562016-03-16 22:10:40 +00001357 mutex_lock(&dev->stats.access_lock);
1358 memcpy(data, &dev->stats.curr_stat, sizeof(dev->stats.curr_stat));
1359 mutex_unlock(&dev->stats.access_lock);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001360}
1361
1362static void lan78xx_get_wol(struct net_device *netdev,
1363 struct ethtool_wolinfo *wol)
1364{
1365 struct lan78xx_net *dev = netdev_priv(netdev);
1366 int ret;
1367 u32 buf;
1368 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
1369
1370 if (usb_autopm_get_interface(dev->intf) < 0)
1371 return;
1372
1373 ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
1374 if (unlikely(ret < 0)) {
1375 wol->supported = 0;
1376 wol->wolopts = 0;
1377 } else {
1378 if (buf & USB_CFG_RMT_WKP_) {
1379 wol->supported = WAKE_ALL;
1380 wol->wolopts = pdata->wol;
1381 } else {
1382 wol->supported = 0;
1383 wol->wolopts = 0;
1384 }
1385 }
1386
1387 usb_autopm_put_interface(dev->intf);
1388}
1389
1390static int lan78xx_set_wol(struct net_device *netdev,
1391 struct ethtool_wolinfo *wol)
1392{
1393 struct lan78xx_net *dev = netdev_priv(netdev);
1394 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
1395 int ret;
1396
1397 ret = usb_autopm_get_interface(dev->intf);
1398 if (ret < 0)
1399 return ret;
1400
1401 pdata->wol = 0;
1402 if (wol->wolopts & WAKE_UCAST)
1403 pdata->wol |= WAKE_UCAST;
1404 if (wol->wolopts & WAKE_MCAST)
1405 pdata->wol |= WAKE_MCAST;
1406 if (wol->wolopts & WAKE_BCAST)
1407 pdata->wol |= WAKE_BCAST;
1408 if (wol->wolopts & WAKE_MAGIC)
1409 pdata->wol |= WAKE_MAGIC;
1410 if (wol->wolopts & WAKE_PHY)
1411 pdata->wol |= WAKE_PHY;
1412 if (wol->wolopts & WAKE_ARP)
1413 pdata->wol |= WAKE_ARP;
1414
1415 device_set_wakeup_enable(&dev->udev->dev, (bool)wol->wolopts);
1416
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001417 phy_ethtool_set_wol(netdev->phydev, wol);
1418
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001419 usb_autopm_put_interface(dev->intf);
1420
1421 return ret;
1422}
1423
1424static int lan78xx_get_eee(struct net_device *net, struct ethtool_eee *edata)
1425{
1426 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001427 struct phy_device *phydev = net->phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001428 int ret;
1429 u32 buf;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001430
1431 ret = usb_autopm_get_interface(dev->intf);
1432 if (ret < 0)
1433 return ret;
1434
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001435 ret = phy_ethtool_get_eee(phydev, edata);
1436 if (ret < 0)
1437 goto exit;
1438
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001439 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1440 if (buf & MAC_CR_EEE_EN_) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001441 edata->eee_enabled = true;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001442 edata->eee_active = !!(edata->advertised &
1443 edata->lp_advertised);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001444 edata->tx_lpi_enabled = true;
1445 /* EEE_TX_LPI_REQ_DLY & tx_lpi_timer are same uSec unit */
1446 ret = lan78xx_read_reg(dev, EEE_TX_LPI_REQ_DLY, &buf);
1447 edata->tx_lpi_timer = buf;
1448 } else {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001449 edata->eee_enabled = false;
1450 edata->eee_active = false;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001451 edata->tx_lpi_enabled = false;
1452 edata->tx_lpi_timer = 0;
1453 }
1454
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001455 ret = 0;
1456exit:
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001457 usb_autopm_put_interface(dev->intf);
1458
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001459 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001460}
1461
1462static int lan78xx_set_eee(struct net_device *net, struct ethtool_eee *edata)
1463{
1464 struct lan78xx_net *dev = netdev_priv(net);
1465 int ret;
1466 u32 buf;
1467
1468 ret = usb_autopm_get_interface(dev->intf);
1469 if (ret < 0)
1470 return ret;
1471
1472 if (edata->eee_enabled) {
1473 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1474 buf |= MAC_CR_EEE_EN_;
1475 ret = lan78xx_write_reg(dev, MAC_CR, buf);
1476
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001477 phy_ethtool_set_eee(net->phydev, edata);
1478
1479 buf = (u32)edata->tx_lpi_timer;
1480 ret = lan78xx_write_reg(dev, EEE_TX_LPI_REQ_DLY, buf);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001481 } else {
1482 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1483 buf &= ~MAC_CR_EEE_EN_;
1484 ret = lan78xx_write_reg(dev, MAC_CR, buf);
1485 }
1486
1487 usb_autopm_put_interface(dev->intf);
1488
1489 return 0;
1490}
1491
1492static u32 lan78xx_get_link(struct net_device *net)
1493{
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001494 phy_read_status(net->phydev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001495
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001496 return net->phydev->link;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001497}
1498
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001499static void lan78xx_get_drvinfo(struct net_device *net,
1500 struct ethtool_drvinfo *info)
1501{
1502 struct lan78xx_net *dev = netdev_priv(net);
1503
1504 strncpy(info->driver, DRIVER_NAME, sizeof(info->driver));
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001505 usb_make_path(dev->udev, info->bus_info, sizeof(info->bus_info));
1506}
1507
1508static u32 lan78xx_get_msglevel(struct net_device *net)
1509{
1510 struct lan78xx_net *dev = netdev_priv(net);
1511
1512 return dev->msg_enable;
1513}
1514
1515static void lan78xx_set_msglevel(struct net_device *net, u32 level)
1516{
1517 struct lan78xx_net *dev = netdev_priv(net);
1518
1519 dev->msg_enable = level;
1520}
1521
Philippe Reynes6e765102016-10-09 12:07:04 +02001522static int lan78xx_get_link_ksettings(struct net_device *net,
1523 struct ethtool_link_ksettings *cmd)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001524{
1525 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001526 struct phy_device *phydev = net->phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001527 int ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001528
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001529 ret = usb_autopm_get_interface(dev->intf);
1530 if (ret < 0)
1531 return ret;
1532
yuval.shaia@oracle.com55141742017-06-13 10:09:46 +03001533 phy_ethtool_ksettings_get(phydev, cmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001534
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001535 usb_autopm_put_interface(dev->intf);
1536
1537 return ret;
1538}
1539
Philippe Reynes6e765102016-10-09 12:07:04 +02001540static int lan78xx_set_link_ksettings(struct net_device *net,
1541 const struct ethtool_link_ksettings *cmd)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001542{
1543 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001544 struct phy_device *phydev = net->phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001545 int ret = 0;
1546 int temp;
1547
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001548 ret = usb_autopm_get_interface(dev->intf);
1549 if (ret < 0)
1550 return ret;
1551
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001552 /* change speed & duplex */
Philippe Reynes6e765102016-10-09 12:07:04 +02001553 ret = phy_ethtool_ksettings_set(phydev, cmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001554
Philippe Reynes6e765102016-10-09 12:07:04 +02001555 if (!cmd->base.autoneg) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001556 /* force link down */
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001557 temp = phy_read(phydev, MII_BMCR);
1558 phy_write(phydev, MII_BMCR, temp | BMCR_LOOPBACK);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001559 mdelay(1);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001560 phy_write(phydev, MII_BMCR, temp);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001561 }
1562
1563 usb_autopm_put_interface(dev->intf);
1564
1565 return ret;
1566}
1567
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001568static void lan78xx_get_pause(struct net_device *net,
1569 struct ethtool_pauseparam *pause)
1570{
1571 struct lan78xx_net *dev = netdev_priv(net);
1572 struct phy_device *phydev = net->phydev;
Philippe Reynes6e765102016-10-09 12:07:04 +02001573 struct ethtool_link_ksettings ecmd;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001574
Philippe Reynes6e765102016-10-09 12:07:04 +02001575 phy_ethtool_ksettings_get(phydev, &ecmd);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001576
1577 pause->autoneg = dev->fc_autoneg;
1578
1579 if (dev->fc_request_control & FLOW_CTRL_TX)
1580 pause->tx_pause = 1;
1581
1582 if (dev->fc_request_control & FLOW_CTRL_RX)
1583 pause->rx_pause = 1;
1584}
1585
1586static int lan78xx_set_pause(struct net_device *net,
1587 struct ethtool_pauseparam *pause)
1588{
1589 struct lan78xx_net *dev = netdev_priv(net);
1590 struct phy_device *phydev = net->phydev;
Philippe Reynes6e765102016-10-09 12:07:04 +02001591 struct ethtool_link_ksettings ecmd;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001592 int ret;
1593
Philippe Reynes6e765102016-10-09 12:07:04 +02001594 phy_ethtool_ksettings_get(phydev, &ecmd);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001595
Philippe Reynes6e765102016-10-09 12:07:04 +02001596 if (pause->autoneg && !ecmd.base.autoneg) {
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001597 ret = -EINVAL;
1598 goto exit;
1599 }
1600
1601 dev->fc_request_control = 0;
1602 if (pause->rx_pause)
1603 dev->fc_request_control |= FLOW_CTRL_RX;
1604
1605 if (pause->tx_pause)
1606 dev->fc_request_control |= FLOW_CTRL_TX;
1607
Philippe Reynes6e765102016-10-09 12:07:04 +02001608 if (ecmd.base.autoneg) {
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001609 u32 mii_adv;
Philippe Reynes6e765102016-10-09 12:07:04 +02001610 u32 advertising;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001611
Philippe Reynes6e765102016-10-09 12:07:04 +02001612 ethtool_convert_link_mode_to_legacy_u32(
1613 &advertising, ecmd.link_modes.advertising);
1614
1615 advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001616 mii_adv = (u32)mii_advertise_flowctrl(dev->fc_request_control);
Philippe Reynes6e765102016-10-09 12:07:04 +02001617 advertising |= mii_adv_to_ethtool_adv_t(mii_adv);
1618
1619 ethtool_convert_legacy_u32_to_link_mode(
1620 ecmd.link_modes.advertising, advertising);
1621
1622 phy_ethtool_ksettings_set(phydev, &ecmd);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001623 }
1624
1625 dev->fc_autoneg = pause->autoneg;
1626
1627 ret = 0;
1628exit:
1629 return ret;
1630}
1631
Raghuram Chary J49621862018-04-20 11:43:50 +05301632static int lan78xx_get_regs_len(struct net_device *netdev)
1633{
1634 if (!netdev->phydev)
1635 return (sizeof(lan78xx_regs));
1636 else
1637 return (sizeof(lan78xx_regs) + PHY_REG_SIZE);
1638}
1639
1640static void
1641lan78xx_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
1642 void *buf)
1643{
1644 u32 *data = buf;
1645 int i, j;
1646 struct lan78xx_net *dev = netdev_priv(netdev);
1647
1648 /* Read Device/MAC registers */
1649 for (i = 0; i < (sizeof(lan78xx_regs) / sizeof(u32)); i++)
1650 lan78xx_read_reg(dev, lan78xx_regs[i], &data[i]);
1651
1652 if (!netdev->phydev)
1653 return;
1654
1655 /* Read PHY registers */
1656 for (j = 0; j < 32; i++, j++)
1657 data[i] = phy_read(netdev->phydev, j);
1658}
1659
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001660static const struct ethtool_ops lan78xx_ethtool_ops = {
1661 .get_link = lan78xx_get_link,
Florian Fainelli860ce4b2016-11-15 10:06:44 -08001662 .nway_reset = phy_ethtool_nway_reset,
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001663 .get_drvinfo = lan78xx_get_drvinfo,
1664 .get_msglevel = lan78xx_get_msglevel,
1665 .set_msglevel = lan78xx_set_msglevel,
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001666 .get_eeprom_len = lan78xx_ethtool_get_eeprom_len,
1667 .get_eeprom = lan78xx_ethtool_get_eeprom,
1668 .set_eeprom = lan78xx_ethtool_set_eeprom,
1669 .get_ethtool_stats = lan78xx_get_stats,
1670 .get_sset_count = lan78xx_get_sset_count,
1671 .get_strings = lan78xx_get_strings,
1672 .get_wol = lan78xx_get_wol,
1673 .set_wol = lan78xx_set_wol,
1674 .get_eee = lan78xx_get_eee,
1675 .set_eee = lan78xx_set_eee,
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001676 .get_pauseparam = lan78xx_get_pause,
1677 .set_pauseparam = lan78xx_set_pause,
Philippe Reynes6e765102016-10-09 12:07:04 +02001678 .get_link_ksettings = lan78xx_get_link_ksettings,
1679 .set_link_ksettings = lan78xx_set_link_ksettings,
Raghuram Chary J49621862018-04-20 11:43:50 +05301680 .get_regs_len = lan78xx_get_regs_len,
1681 .get_regs = lan78xx_get_regs,
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001682};
1683
1684static int lan78xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
1685{
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001686 if (!netif_running(netdev))
1687 return -EINVAL;
1688
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001689 return phy_mii_ioctl(netdev->phydev, rq, cmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001690}
1691
1692static void lan78xx_init_mac_address(struct lan78xx_net *dev)
1693{
1694 u32 addr_lo, addr_hi;
1695 int ret;
1696 u8 addr[6];
1697
1698 ret = lan78xx_read_reg(dev, RX_ADDRL, &addr_lo);
1699 ret = lan78xx_read_reg(dev, RX_ADDRH, &addr_hi);
1700
1701 addr[0] = addr_lo & 0xFF;
1702 addr[1] = (addr_lo >> 8) & 0xFF;
1703 addr[2] = (addr_lo >> 16) & 0xFF;
1704 addr[3] = (addr_lo >> 24) & 0xFF;
1705 addr[4] = addr_hi & 0xFF;
1706 addr[5] = (addr_hi >> 8) & 0xFF;
1707
1708 if (!is_valid_ether_addr(addr)) {
Phil Elwell760db292018-04-19 17:59:38 +01001709 if (!eth_platform_get_mac_address(&dev->udev->dev, addr)) {
1710 /* valid address present in Device Tree */
1711 netif_dbg(dev, ifup, dev->net,
1712 "MAC address read from Device Tree");
1713 } else if (((lan78xx_read_eeprom(dev, EEPROM_MAC_OFFSET,
1714 ETH_ALEN, addr) == 0) ||
1715 (lan78xx_read_otp(dev, EEPROM_MAC_OFFSET,
1716 ETH_ALEN, addr) == 0)) &&
1717 is_valid_ether_addr(addr)) {
1718 /* eeprom values are valid so use them */
1719 netif_dbg(dev, ifup, dev->net,
1720 "MAC address read from EEPROM");
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001721 } else {
1722 /* generate random MAC */
1723 random_ether_addr(addr);
1724 netif_dbg(dev, ifup, dev->net,
1725 "MAC address set to random addr");
1726 }
Phil Elwell760db292018-04-19 17:59:38 +01001727
1728 addr_lo = addr[0] | (addr[1] << 8) |
1729 (addr[2] << 16) | (addr[3] << 24);
1730 addr_hi = addr[4] | (addr[5] << 8);
1731
1732 ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
1733 ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001734 }
1735
1736 ret = lan78xx_write_reg(dev, MAF_LO(0), addr_lo);
1737 ret = lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_);
1738
1739 ether_addr_copy(dev->net->dev_addr, addr);
1740}
1741
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001742/* MDIO read and write wrappers for phylib */
1743static int lan78xx_mdiobus_read(struct mii_bus *bus, int phy_id, int idx)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001744{
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001745 struct lan78xx_net *dev = bus->priv;
1746 u32 val, addr;
1747 int ret;
1748
1749 ret = usb_autopm_get_interface(dev->intf);
1750 if (ret < 0)
1751 return ret;
1752
1753 mutex_lock(&dev->phy_mutex);
1754
1755 /* confirm MII not busy */
1756 ret = lan78xx_phy_wait_not_busy(dev);
1757 if (ret < 0)
1758 goto done;
1759
1760 /* set the address, index & direction (read from PHY) */
1761 addr = mii_access(phy_id, idx, MII_READ);
1762 ret = lan78xx_write_reg(dev, MII_ACC, addr);
1763
1764 ret = lan78xx_phy_wait_not_busy(dev);
1765 if (ret < 0)
1766 goto done;
1767
1768 ret = lan78xx_read_reg(dev, MII_DATA, &val);
1769
1770 ret = (int)(val & 0xFFFF);
1771
1772done:
1773 mutex_unlock(&dev->phy_mutex);
1774 usb_autopm_put_interface(dev->intf);
Woojung Huh02dc1f32016-12-07 20:26:25 +00001775
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001776 return ret;
1777}
1778
1779static int lan78xx_mdiobus_write(struct mii_bus *bus, int phy_id, int idx,
1780 u16 regval)
1781{
1782 struct lan78xx_net *dev = bus->priv;
1783 u32 val, addr;
1784 int ret;
1785
1786 ret = usb_autopm_get_interface(dev->intf);
1787 if (ret < 0)
1788 return ret;
1789
1790 mutex_lock(&dev->phy_mutex);
1791
1792 /* confirm MII not busy */
1793 ret = lan78xx_phy_wait_not_busy(dev);
1794 if (ret < 0)
1795 goto done;
1796
1797 val = (u32)regval;
1798 ret = lan78xx_write_reg(dev, MII_DATA, val);
1799
1800 /* set the address, index & direction (write to PHY) */
1801 addr = mii_access(phy_id, idx, MII_WRITE);
1802 ret = lan78xx_write_reg(dev, MII_ACC, addr);
1803
1804 ret = lan78xx_phy_wait_not_busy(dev);
1805 if (ret < 0)
1806 goto done;
1807
1808done:
1809 mutex_unlock(&dev->phy_mutex);
1810 usb_autopm_put_interface(dev->intf);
1811 return 0;
1812}
1813
1814static int lan78xx_mdio_init(struct lan78xx_net *dev)
1815{
Phil Elwell1827b062018-04-19 17:59:39 +01001816 struct device_node *node;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001817 int ret;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001818
1819 dev->mdiobus = mdiobus_alloc();
1820 if (!dev->mdiobus) {
1821 netdev_err(dev->net, "can't allocate MDIO bus\n");
1822 return -ENOMEM;
1823 }
1824
1825 dev->mdiobus->priv = (void *)dev;
1826 dev->mdiobus->read = lan78xx_mdiobus_read;
1827 dev->mdiobus->write = lan78xx_mdiobus_write;
1828 dev->mdiobus->name = "lan78xx-mdiobus";
1829
1830 snprintf(dev->mdiobus->id, MII_BUS_ID_SIZE, "usb-%03d:%03d",
1831 dev->udev->bus->busnum, dev->udev->devnum);
1832
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +00001833 switch (dev->chipid) {
1834 case ID_REV_CHIP_ID_7800_:
1835 case ID_REV_CHIP_ID_7850_:
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001836 /* set to internal PHY id */
1837 dev->mdiobus->phy_mask = ~(1 << 1);
1838 break;
Woojung Huh02dc1f32016-12-07 20:26:25 +00001839 case ID_REV_CHIP_ID_7801_:
1840 /* scan thru PHYAD[2..0] */
1841 dev->mdiobus->phy_mask = ~(0xFF);
1842 break;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001843 }
1844
Phil Elwell1827b062018-04-19 17:59:39 +01001845 node = of_get_child_by_name(dev->udev->dev.of_node, "mdio");
Florian Fainelli00e798c2018-05-15 16:56:19 -07001846 ret = of_mdiobus_register(dev->mdiobus, node);
1847 if (node)
Phil Elwell1827b062018-04-19 17:59:39 +01001848 of_node_put(node);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001849 if (ret) {
1850 netdev_err(dev->net, "can't register MDIO bus\n");
Andrew Lunne7f4dc32016-01-06 20:11:15 +01001851 goto exit1;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001852 }
1853
1854 netdev_dbg(dev->net, "registered mdiobus bus %s\n", dev->mdiobus->id);
1855 return 0;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001856exit1:
1857 mdiobus_free(dev->mdiobus);
1858 return ret;
1859}
1860
1861static void lan78xx_remove_mdio(struct lan78xx_net *dev)
1862{
1863 mdiobus_unregister(dev->mdiobus);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001864 mdiobus_free(dev->mdiobus);
1865}
1866
1867static void lan78xx_link_status_change(struct net_device *net)
1868{
Woojung Huh14437e32016-04-25 22:22:36 +00001869 struct phy_device *phydev = net->phydev;
1870 int ret, temp;
1871
1872 /* At forced 100 F/H mode, chip may fail to set mode correctly
1873 * when cable is switched between long(~50+m) and short one.
1874 * As workaround, set to 10 before setting to 100
1875 * at forced 100 F/H mode.
1876 */
1877 if (!phydev->autoneg && (phydev->speed == 100)) {
1878 /* disable phy interrupt */
1879 temp = phy_read(phydev, LAN88XX_INT_MASK);
1880 temp &= ~LAN88XX_INT_MASK_MDINTPIN_EN_;
1881 ret = phy_write(phydev, LAN88XX_INT_MASK, temp);
1882
1883 temp = phy_read(phydev, MII_BMCR);
1884 temp &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
1885 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
1886 temp |= BMCR_SPEED100;
1887 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */
1888
1889 /* clear pending interrupt generated while workaround */
1890 temp = phy_read(phydev, LAN88XX_INT_STS);
1891
1892 /* enable phy interrupt back */
1893 temp = phy_read(phydev, LAN88XX_INT_MASK);
1894 temp |= LAN88XX_INT_MASK_MDINTPIN_EN_;
1895 ret = phy_write(phydev, LAN88XX_INT_MASK, temp);
1896 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001897}
1898
Woojung Huhcc89c322016-11-01 20:02:00 +00001899static int irq_map(struct irq_domain *d, unsigned int irq,
1900 irq_hw_number_t hwirq)
1901{
1902 struct irq_domain_data *data = d->host_data;
1903
1904 irq_set_chip_data(irq, data);
1905 irq_set_chip_and_handler(irq, data->irqchip, data->irq_handler);
1906 irq_set_noprobe(irq);
1907
1908 return 0;
1909}
1910
1911static void irq_unmap(struct irq_domain *d, unsigned int irq)
1912{
1913 irq_set_chip_and_handler(irq, NULL, NULL);
1914 irq_set_chip_data(irq, NULL);
1915}
1916
1917static const struct irq_domain_ops chip_domain_ops = {
1918 .map = irq_map,
1919 .unmap = irq_unmap,
1920};
1921
1922static void lan78xx_irq_mask(struct irq_data *irqd)
1923{
1924 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1925
1926 data->irqenable &= ~BIT(irqd_to_hwirq(irqd));
1927}
1928
1929static void lan78xx_irq_unmask(struct irq_data *irqd)
1930{
1931 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1932
1933 data->irqenable |= BIT(irqd_to_hwirq(irqd));
1934}
1935
1936static void lan78xx_irq_bus_lock(struct irq_data *irqd)
1937{
1938 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1939
1940 mutex_lock(&data->irq_lock);
1941}
1942
1943static void lan78xx_irq_bus_sync_unlock(struct irq_data *irqd)
1944{
1945 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1946 struct lan78xx_net *dev =
1947 container_of(data, struct lan78xx_net, domain_data);
1948 u32 buf;
1949 int ret;
1950
1951 /* call register access here because irq_bus_lock & irq_bus_sync_unlock
1952 * are only two callbacks executed in non-atomic contex.
1953 */
1954 ret = lan78xx_read_reg(dev, INT_EP_CTL, &buf);
1955 if (buf != data->irqenable)
1956 ret = lan78xx_write_reg(dev, INT_EP_CTL, data->irqenable);
1957
1958 mutex_unlock(&data->irq_lock);
1959}
1960
1961static struct irq_chip lan78xx_irqchip = {
1962 .name = "lan78xx-irqs",
1963 .irq_mask = lan78xx_irq_mask,
1964 .irq_unmask = lan78xx_irq_unmask,
1965 .irq_bus_lock = lan78xx_irq_bus_lock,
1966 .irq_bus_sync_unlock = lan78xx_irq_bus_sync_unlock,
1967};
1968
1969static int lan78xx_setup_irq_domain(struct lan78xx_net *dev)
1970{
1971 struct device_node *of_node;
1972 struct irq_domain *irqdomain;
1973 unsigned int irqmap = 0;
1974 u32 buf;
1975 int ret = 0;
1976
1977 of_node = dev->udev->dev.parent->of_node;
1978
1979 mutex_init(&dev->domain_data.irq_lock);
1980
1981 lan78xx_read_reg(dev, INT_EP_CTL, &buf);
1982 dev->domain_data.irqenable = buf;
1983
1984 dev->domain_data.irqchip = &lan78xx_irqchip;
1985 dev->domain_data.irq_handler = handle_simple_irq;
1986
1987 irqdomain = irq_domain_add_simple(of_node, MAX_INT_EP, 0,
1988 &chip_domain_ops, &dev->domain_data);
1989 if (irqdomain) {
1990 /* create mapping for PHY interrupt */
1991 irqmap = irq_create_mapping(irqdomain, INT_EP_PHY);
1992 if (!irqmap) {
1993 irq_domain_remove(irqdomain);
1994
1995 irqdomain = NULL;
1996 ret = -EINVAL;
1997 }
1998 } else {
1999 ret = -EINVAL;
2000 }
2001
2002 dev->domain_data.irqdomain = irqdomain;
2003 dev->domain_data.phyirq = irqmap;
2004
2005 return ret;
2006}
2007
2008static void lan78xx_remove_irq_domain(struct lan78xx_net *dev)
2009{
2010 if (dev->domain_data.phyirq > 0) {
2011 irq_dispose_mapping(dev->domain_data.phyirq);
2012
2013 if (dev->domain_data.irqdomain)
2014 irq_domain_remove(dev->domain_data.irqdomain);
2015 }
2016 dev->domain_data.phyirq = 0;
2017 dev->domain_data.irqdomain = NULL;
2018}
2019
Woojung Huh02dc1f32016-12-07 20:26:25 +00002020static int lan8835_fixup(struct phy_device *phydev)
2021{
2022 int buf;
2023 int ret;
2024 struct lan78xx_net *dev = netdev_priv(phydev->attached_dev);
2025
2026 /* LED2/PME_N/IRQ_N/RGMII_ID pin to IRQ_N mode */
Russell King5f613672017-03-21 16:36:48 +00002027 buf = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x8010);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002028 buf &= ~0x1800;
2029 buf |= 0x0800;
Russell King5f613672017-03-21 16:36:48 +00002030 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8010, buf);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002031
2032 /* RGMII MAC TXC Delay Enable */
2033 ret = lan78xx_write_reg(dev, MAC_RGMII_ID,
2034 MAC_RGMII_ID_TXC_DELAY_EN_);
2035
2036 /* RGMII TX DLL Tune Adjust */
2037 ret = lan78xx_write_reg(dev, RGMII_TX_BYP_DLL, 0x3D00);
2038
2039 dev->interface = PHY_INTERFACE_MODE_RGMII_TXID;
2040
2041 return 1;
2042}
2043
2044static int ksz9031rnx_fixup(struct phy_device *phydev)
2045{
2046 struct lan78xx_net *dev = netdev_priv(phydev->attached_dev);
2047
2048 /* Micrel9301RNX PHY configuration */
2049 /* RGMII Control Signal Pad Skew */
Russell King5f613672017-03-21 16:36:48 +00002050 phy_write_mmd(phydev, MDIO_MMD_WIS, 4, 0x0077);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002051 /* RGMII RX Data Pad Skew */
Russell King5f613672017-03-21 16:36:48 +00002052 phy_write_mmd(phydev, MDIO_MMD_WIS, 5, 0x7777);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002053 /* RGMII RX Clock Pad Skew */
Russell King5f613672017-03-21 16:36:48 +00002054 phy_write_mmd(phydev, MDIO_MMD_WIS, 8, 0x1FF);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002055
2056 dev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
2057
2058 return 1;
2059}
2060
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302061static struct phy_device *lan7801_phy_init(struct lan78xx_net *dev)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002062{
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302063 u32 buf;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002064 int ret;
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302065 struct fixed_phy_status fphy_status = {
2066 .link = 1,
2067 .speed = SPEED_1000,
2068 .duplex = DUPLEX_FULL,
2069 };
Colin Ian King3b51cc72018-02-01 17:10:18 +00002070 struct phy_device *phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002071
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002072 phydev = phy_find_first(dev->mdiobus);
2073 if (!phydev) {
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302074 netdev_dbg(dev->net, "PHY Not Found!! Registering Fixed PHY\n");
2075 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1,
2076 NULL);
2077 if (IS_ERR(phydev)) {
2078 netdev_err(dev->net, "No PHY/fixed_PHY found\n");
2079 return NULL;
2080 }
2081 netdev_dbg(dev->net, "Registered FIXED PHY\n");
2082 dev->interface = PHY_INTERFACE_MODE_RGMII;
2083 ret = lan78xx_write_reg(dev, MAC_RGMII_ID,
2084 MAC_RGMII_ID_TXC_DELAY_EN_);
2085 ret = lan78xx_write_reg(dev, RGMII_TX_BYP_DLL, 0x3D00);
2086 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2087 buf |= HW_CFG_CLK125_EN_;
2088 buf |= HW_CFG_REFCLK25_EN_;
2089 ret = lan78xx_write_reg(dev, HW_CFG, buf);
2090 } else {
Woojung Huh02dc1f32016-12-07 20:26:25 +00002091 if (!phydev->drv) {
2092 netdev_err(dev->net, "no PHY driver found\n");
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302093 return NULL;
Woojung Huh02dc1f32016-12-07 20:26:25 +00002094 }
Woojung Huh02dc1f32016-12-07 20:26:25 +00002095 dev->interface = PHY_INTERFACE_MODE_RGMII;
Woojung Huh02dc1f32016-12-07 20:26:25 +00002096 /* external PHY fixup for KSZ9031RNX */
2097 ret = phy_register_fixup_for_uid(PHY_KSZ9031RNX, 0xfffffff0,
2098 ksz9031rnx_fixup);
2099 if (ret < 0) {
Raghuram Chary J7670ed72018-04-28 11:33:16 +05302100 netdev_err(dev->net, "Failed to register fixup for PHY_KSZ9031RNX\n");
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302101 return NULL;
Woojung Huh02dc1f32016-12-07 20:26:25 +00002102 }
2103 /* external PHY fixup for LAN8835 */
2104 ret = phy_register_fixup_for_uid(PHY_LAN8835, 0xfffffff0,
2105 lan8835_fixup);
2106 if (ret < 0) {
Raghuram Chary J7670ed72018-04-28 11:33:16 +05302107 netdev_err(dev->net, "Failed to register fixup for PHY_LAN8835\n");
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302108 return NULL;
Woojung Huh02dc1f32016-12-07 20:26:25 +00002109 }
2110 /* add more external PHY fixup here if needed */
2111
2112 phydev->is_internal = false;
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302113 }
2114 return phydev;
2115}
2116
2117static int lan78xx_phy_init(struct lan78xx_net *dev)
2118{
2119 int ret;
2120 u32 mii_adv;
2121 struct phy_device *phydev;
2122
2123 switch (dev->chipid) {
2124 case ID_REV_CHIP_ID_7801_:
2125 phydev = lan7801_phy_init(dev);
2126 if (!phydev) {
2127 netdev_err(dev->net, "lan7801: PHY Init Failed");
2128 return -EIO;
2129 }
2130 break;
2131
2132 case ID_REV_CHIP_ID_7800_:
2133 case ID_REV_CHIP_ID_7850_:
2134 phydev = phy_find_first(dev->mdiobus);
2135 if (!phydev) {
2136 netdev_err(dev->net, "no PHY found\n");
2137 return -EIO;
2138 }
2139 phydev->is_internal = true;
2140 dev->interface = PHY_INTERFACE_MODE_GMII;
2141 break;
2142
2143 default:
2144 netdev_err(dev->net, "Unknown CHIP ID found\n");
2145 return -EIO;
Woojung Huh02dc1f32016-12-07 20:26:25 +00002146 }
2147
Woojung Huhcc89c322016-11-01 20:02:00 +00002148 /* if phyirq is not set, use polling mode in phylib */
2149 if (dev->domain_data.phyirq > 0)
2150 phydev->irq = dev->domain_data.phyirq;
2151 else
2152 phydev->irq = 0;
2153 netdev_dbg(dev->net, "phydev->irq = %d\n", phydev->irq);
Woojung.Huh@microchip.come4953912016-01-27 22:57:52 +00002154
Woojung Huhf6e3ef32016-11-17 22:10:02 +00002155 /* set to AUTOMDIX */
2156 phydev->mdix = ETH_TP_MDI_AUTO;
2157
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002158 ret = phy_connect_direct(dev->net, phydev,
2159 lan78xx_link_status_change,
Woojung Huh02dc1f32016-12-07 20:26:25 +00002160 dev->interface);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002161 if (ret) {
2162 netdev_err(dev->net, "can't attach PHY to %s\n",
2163 dev->mdiobus->id);
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302164 if (dev->chipid == ID_REV_CHIP_ID_7801_) {
2165 if (phy_is_pseudo_fixed_link(phydev)) {
2166 fixed_phy_unregister(phydev);
2167 } else {
2168 phy_unregister_fixup_for_uid(PHY_KSZ9031RNX,
2169 0xfffffff0);
2170 phy_unregister_fixup_for_uid(PHY_LAN8835,
2171 0xfffffff0);
2172 }
2173 }
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002174 return -EIO;
2175 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002176
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002177 /* MAC doesn't support 1000T Half */
2178 phydev->supported &= ~SUPPORTED_1000baseT_Half;
Woojung.Huh@microchip.come270b2d2016-02-25 23:33:09 +00002179
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00002180 /* support both flow controls */
2181 dev->fc_request_control = (FLOW_CTRL_RX | FLOW_CTRL_TX);
2182 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
2183 mii_adv = (u32)mii_advertise_flowctrl(dev->fc_request_control);
2184 phydev->advertising |= mii_adv_to_ethtool_adv_t(mii_adv);
2185
Phil Elwell1827b062018-04-19 17:59:39 +01002186 if (phydev->mdio.dev.of_node) {
2187 u32 reg;
2188 int len;
2189
2190 len = of_property_count_elems_of_size(phydev->mdio.dev.of_node,
2191 "microchip,led-modes",
2192 sizeof(u32));
2193 if (len >= 0) {
2194 /* Ensure the appropriate LEDs are enabled */
2195 lan78xx_read_reg(dev, HW_CFG, &reg);
2196 reg &= ~(HW_CFG_LED0_EN_ |
2197 HW_CFG_LED1_EN_ |
2198 HW_CFG_LED2_EN_ |
2199 HW_CFG_LED3_EN_);
2200 reg |= (len > 0) * HW_CFG_LED0_EN_ |
2201 (len > 1) * HW_CFG_LED1_EN_ |
2202 (len > 2) * HW_CFG_LED2_EN_ |
2203 (len > 3) * HW_CFG_LED3_EN_;
2204 lan78xx_write_reg(dev, HW_CFG, reg);
2205 }
2206 }
2207
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002208 genphy_config_aneg(phydev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002209
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00002210 dev->fc_autoneg = phydev->autoneg;
2211
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002212 return 0;
2213}
2214
2215static int lan78xx_set_rx_max_frame_length(struct lan78xx_net *dev, int size)
2216{
2217 int ret = 0;
2218 u32 buf;
2219 bool rxenabled;
2220
2221 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
2222
2223 rxenabled = ((buf & MAC_RX_RXEN_) != 0);
2224
2225 if (rxenabled) {
2226 buf &= ~MAC_RX_RXEN_;
2227 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2228 }
2229
2230 /* add 4 to size for FCS */
2231 buf &= ~MAC_RX_MAX_SIZE_MASK_;
2232 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT_) & MAC_RX_MAX_SIZE_MASK_);
2233
2234 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2235
2236 if (rxenabled) {
2237 buf |= MAC_RX_RXEN_;
2238 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2239 }
2240
2241 return 0;
2242}
2243
2244static int unlink_urbs(struct lan78xx_net *dev, struct sk_buff_head *q)
2245{
2246 struct sk_buff *skb;
2247 unsigned long flags;
2248 int count = 0;
2249
2250 spin_lock_irqsave(&q->lock, flags);
2251 while (!skb_queue_empty(q)) {
2252 struct skb_data *entry;
2253 struct urb *urb;
2254 int ret;
2255
2256 skb_queue_walk(q, skb) {
2257 entry = (struct skb_data *)skb->cb;
2258 if (entry->state != unlink_start)
2259 goto found;
2260 }
2261 break;
2262found:
2263 entry->state = unlink_start;
2264 urb = entry->urb;
2265
2266 /* Get reference count of the URB to avoid it to be
2267 * freed during usb_unlink_urb, which may trigger
2268 * use-after-free problem inside usb_unlink_urb since
2269 * usb_unlink_urb is always racing with .complete
2270 * handler(include defer_bh).
2271 */
2272 usb_get_urb(urb);
2273 spin_unlock_irqrestore(&q->lock, flags);
2274 /* during some PM-driven resume scenarios,
2275 * these (async) unlinks complete immediately
2276 */
2277 ret = usb_unlink_urb(urb);
2278 if (ret != -EINPROGRESS && ret != 0)
2279 netdev_dbg(dev->net, "unlink urb err, %d\n", ret);
2280 else
2281 count++;
2282 usb_put_urb(urb);
2283 spin_lock_irqsave(&q->lock, flags);
2284 }
2285 spin_unlock_irqrestore(&q->lock, flags);
2286 return count;
2287}
2288
2289static int lan78xx_change_mtu(struct net_device *netdev, int new_mtu)
2290{
2291 struct lan78xx_net *dev = netdev_priv(netdev);
2292 int ll_mtu = new_mtu + netdev->hard_header_len;
2293 int old_hard_mtu = dev->hard_mtu;
2294 int old_rx_urb_size = dev->rx_urb_size;
2295 int ret;
2296
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002297 /* no second zero-length packet read wanted after mtu-sized packets */
2298 if ((ll_mtu % dev->maxpacket) == 0)
2299 return -EDOM;
2300
Dave Stevenson2259b7a2018-06-25 15:07:12 +01002301 ret = lan78xx_set_rx_max_frame_length(dev, new_mtu + VLAN_ETH_HLEN);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002302
2303 netdev->mtu = new_mtu;
2304
2305 dev->hard_mtu = netdev->mtu + netdev->hard_header_len;
2306 if (dev->rx_urb_size == old_hard_mtu) {
2307 dev->rx_urb_size = dev->hard_mtu;
2308 if (dev->rx_urb_size > old_rx_urb_size) {
2309 if (netif_running(dev->net)) {
2310 unlink_urbs(dev, &dev->rxq);
2311 tasklet_schedule(&dev->bh);
2312 }
2313 }
2314 }
2315
2316 return 0;
2317}
2318
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002319static int lan78xx_set_mac_addr(struct net_device *netdev, void *p)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002320{
2321 struct lan78xx_net *dev = netdev_priv(netdev);
2322 struct sockaddr *addr = p;
2323 u32 addr_lo, addr_hi;
2324 int ret;
2325
2326 if (netif_running(netdev))
2327 return -EBUSY;
2328
2329 if (!is_valid_ether_addr(addr->sa_data))
2330 return -EADDRNOTAVAIL;
2331
2332 ether_addr_copy(netdev->dev_addr, addr->sa_data);
2333
2334 addr_lo = netdev->dev_addr[0] |
2335 netdev->dev_addr[1] << 8 |
2336 netdev->dev_addr[2] << 16 |
2337 netdev->dev_addr[3] << 24;
2338 addr_hi = netdev->dev_addr[4] |
2339 netdev->dev_addr[5] << 8;
2340
2341 ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
2342 ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
2343
2344 return 0;
2345}
2346
2347/* Enable or disable Rx checksum offload engine */
2348static int lan78xx_set_features(struct net_device *netdev,
2349 netdev_features_t features)
2350{
2351 struct lan78xx_net *dev = netdev_priv(netdev);
2352 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2353 unsigned long flags;
2354 int ret;
2355
2356 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
2357
2358 if (features & NETIF_F_RXCSUM) {
2359 pdata->rfe_ctl |= RFE_CTL_TCPUDP_COE_ | RFE_CTL_IP_COE_;
2360 pdata->rfe_ctl |= RFE_CTL_ICMP_COE_ | RFE_CTL_IGMP_COE_;
2361 } else {
2362 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_COE_ | RFE_CTL_IP_COE_);
2363 pdata->rfe_ctl &= ~(RFE_CTL_ICMP_COE_ | RFE_CTL_IGMP_COE_);
2364 }
2365
2366 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2367 pdata->rfe_ctl |= RFE_CTL_VLAN_FILTER_;
2368 else
2369 pdata->rfe_ctl &= ~RFE_CTL_VLAN_FILTER_;
2370
2371 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
2372
2373 ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
2374
2375 return 0;
2376}
2377
2378static void lan78xx_deferred_vlan_write(struct work_struct *param)
2379{
2380 struct lan78xx_priv *pdata =
2381 container_of(param, struct lan78xx_priv, set_vlan);
2382 struct lan78xx_net *dev = pdata->dev;
2383
2384 lan78xx_dataport_write(dev, DP_SEL_RSEL_VLAN_DA_, 0,
2385 DP_SEL_VHF_VLAN_LEN, pdata->vlan_table);
2386}
2387
2388static int lan78xx_vlan_rx_add_vid(struct net_device *netdev,
2389 __be16 proto, u16 vid)
2390{
2391 struct lan78xx_net *dev = netdev_priv(netdev);
2392 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2393 u16 vid_bit_index;
2394 u16 vid_dword_index;
2395
2396 vid_dword_index = (vid >> 5) & 0x7F;
2397 vid_bit_index = vid & 0x1F;
2398
2399 pdata->vlan_table[vid_dword_index] |= (1 << vid_bit_index);
2400
2401 /* defer register writes to a sleepable context */
2402 schedule_work(&pdata->set_vlan);
2403
2404 return 0;
2405}
2406
2407static int lan78xx_vlan_rx_kill_vid(struct net_device *netdev,
2408 __be16 proto, u16 vid)
2409{
2410 struct lan78xx_net *dev = netdev_priv(netdev);
2411 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2412 u16 vid_bit_index;
2413 u16 vid_dword_index;
2414
2415 vid_dword_index = (vid >> 5) & 0x7F;
2416 vid_bit_index = vid & 0x1F;
2417
2418 pdata->vlan_table[vid_dword_index] &= ~(1 << vid_bit_index);
2419
2420 /* defer register writes to a sleepable context */
2421 schedule_work(&pdata->set_vlan);
2422
2423 return 0;
2424}
2425
2426static void lan78xx_init_ltm(struct lan78xx_net *dev)
2427{
2428 int ret;
2429 u32 buf;
2430 u32 regs[6] = { 0 };
2431
2432 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
2433 if (buf & USB_CFG1_LTM_ENABLE_) {
2434 u8 temp[2];
2435 /* Get values from EEPROM first */
2436 if (lan78xx_read_eeprom(dev, 0x3F, 2, temp) == 0) {
2437 if (temp[0] == 24) {
2438 ret = lan78xx_read_raw_eeprom(dev,
2439 temp[1] * 2,
2440 24,
2441 (u8 *)regs);
2442 if (ret < 0)
2443 return;
2444 }
2445 } else if (lan78xx_read_otp(dev, 0x3F, 2, temp) == 0) {
2446 if (temp[0] == 24) {
2447 ret = lan78xx_read_raw_otp(dev,
2448 temp[1] * 2,
2449 24,
2450 (u8 *)regs);
2451 if (ret < 0)
2452 return;
2453 }
2454 }
2455 }
2456
2457 lan78xx_write_reg(dev, LTM_BELT_IDLE0, regs[0]);
2458 lan78xx_write_reg(dev, LTM_BELT_IDLE1, regs[1]);
2459 lan78xx_write_reg(dev, LTM_BELT_ACT0, regs[2]);
2460 lan78xx_write_reg(dev, LTM_BELT_ACT1, regs[3]);
2461 lan78xx_write_reg(dev, LTM_INACTIVE0, regs[4]);
2462 lan78xx_write_reg(dev, LTM_INACTIVE1, regs[5]);
2463}
2464
2465static int lan78xx_reset(struct lan78xx_net *dev)
2466{
2467 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2468 u32 buf;
2469 int ret = 0;
2470 unsigned long timeout;
Raghuram Chary Je69647a2018-03-23 15:48:08 +05302471 u8 sig;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002472
2473 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2474 buf |= HW_CFG_LRST_;
2475 ret = lan78xx_write_reg(dev, HW_CFG, buf);
2476
2477 timeout = jiffies + HZ;
2478 do {
2479 mdelay(1);
2480 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2481 if (time_after(jiffies, timeout)) {
2482 netdev_warn(dev->net,
2483 "timeout on completion of LiteReset");
2484 return -EIO;
2485 }
2486 } while (buf & HW_CFG_LRST_);
2487
2488 lan78xx_init_mac_address(dev);
2489
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002490 /* save DEVID for later usage */
2491 ret = lan78xx_read_reg(dev, ID_REV, &buf);
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +00002492 dev->chipid = (buf & ID_REV_CHIP_ID_MASK_) >> 16;
2493 dev->chiprev = buf & ID_REV_CHIP_REV_MASK_;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002494
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002495 /* Respond to the IN token with a NAK */
2496 ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
2497 buf |= USB_CFG_BIR_;
2498 ret = lan78xx_write_reg(dev, USB_CFG0, buf);
2499
2500 /* Init LTM */
2501 lan78xx_init_ltm(dev);
2502
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002503 if (dev->udev->speed == USB_SPEED_SUPER) {
2504 buf = DEFAULT_BURST_CAP_SIZE / SS_USB_PKT_SIZE;
2505 dev->rx_urb_size = DEFAULT_BURST_CAP_SIZE;
2506 dev->rx_qlen = 4;
2507 dev->tx_qlen = 4;
2508 } else if (dev->udev->speed == USB_SPEED_HIGH) {
2509 buf = DEFAULT_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
2510 dev->rx_urb_size = DEFAULT_BURST_CAP_SIZE;
2511 dev->rx_qlen = RX_MAX_QUEUE_MEMORY / dev->rx_urb_size;
2512 dev->tx_qlen = RX_MAX_QUEUE_MEMORY / dev->hard_mtu;
2513 } else {
2514 buf = DEFAULT_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
2515 dev->rx_urb_size = DEFAULT_BURST_CAP_SIZE;
2516 dev->rx_qlen = 4;
Yuiko Oshinoa5b13792018-01-15 13:24:28 -05002517 dev->tx_qlen = 4;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002518 }
2519
2520 ret = lan78xx_write_reg(dev, BURST_CAP, buf);
2521 ret = lan78xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
2522
2523 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2524 buf |= HW_CFG_MEF_;
2525 ret = lan78xx_write_reg(dev, HW_CFG, buf);
2526
2527 ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
2528 buf |= USB_CFG_BCE_;
2529 ret = lan78xx_write_reg(dev, USB_CFG0, buf);
2530
2531 /* set FIFO sizes */
2532 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
2533 ret = lan78xx_write_reg(dev, FCT_RX_FIFO_END, buf);
2534
2535 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
2536 ret = lan78xx_write_reg(dev, FCT_TX_FIFO_END, buf);
2537
2538 ret = lan78xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
2539 ret = lan78xx_write_reg(dev, FLOW, 0);
2540 ret = lan78xx_write_reg(dev, FCT_FLOW, 0);
2541
2542 /* Don't need rfe_ctl_lock during initialisation */
2543 ret = lan78xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
2544 pdata->rfe_ctl |= RFE_CTL_BCAST_EN_ | RFE_CTL_DA_PERFECT_;
2545 ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
2546
2547 /* Enable or disable checksum offload engines */
2548 lan78xx_set_features(dev->net, dev->net->features);
2549
2550 lan78xx_set_multicast(dev->net);
2551
2552 /* reset PHY */
2553 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
2554 buf |= PMT_CTL_PHY_RST_;
2555 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
2556
2557 timeout = jiffies + HZ;
2558 do {
2559 mdelay(1);
2560 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
2561 if (time_after(jiffies, timeout)) {
2562 netdev_warn(dev->net, "timeout waiting for PHY Reset");
2563 return -EIO;
2564 }
Woojung.Huh@microchip.com6c595b02015-09-16 23:40:39 +00002565 } while ((buf & PMT_CTL_PHY_RST_) || !(buf & PMT_CTL_READY_));
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002566
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002567 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002568 /* LAN7801 only has RGMII mode */
2569 if (dev->chipid == ID_REV_CHIP_ID_7801_)
2570 buf &= ~MAC_CR_GMII_EN_;
Raghuram Chary Je69647a2018-03-23 15:48:08 +05302571
2572 if (dev->chipid == ID_REV_CHIP_ID_7800_) {
2573 ret = lan78xx_read_raw_eeprom(dev, 0, 1, &sig);
2574 if (!ret && sig != EEPROM_INDICATOR) {
2575 /* Implies there is no external eeprom. Set mac speed */
2576 netdev_info(dev->net, "No External EEPROM. Setting MAC Speed\n");
2577 buf |= MAC_CR_AUTO_DUPLEX_ | MAC_CR_AUTO_SPEED_;
2578 }
2579 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002580 ret = lan78xx_write_reg(dev, MAC_CR, buf);
2581
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002582 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
2583 buf |= MAC_TX_TXEN_;
2584 ret = lan78xx_write_reg(dev, MAC_TX, buf);
2585
2586 ret = lan78xx_read_reg(dev, FCT_TX_CTL, &buf);
2587 buf |= FCT_TX_CTL_EN_;
2588 ret = lan78xx_write_reg(dev, FCT_TX_CTL, buf);
2589
Dave Stevenson2259b7a2018-06-25 15:07:12 +01002590 ret = lan78xx_set_rx_max_frame_length(dev,
2591 dev->net->mtu + VLAN_ETH_HLEN);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002592
2593 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
2594 buf |= MAC_RX_RXEN_;
2595 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2596
2597 ret = lan78xx_read_reg(dev, FCT_RX_CTL, &buf);
2598 buf |= FCT_RX_CTL_EN_;
2599 ret = lan78xx_write_reg(dev, FCT_RX_CTL, buf);
2600
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002601 return 0;
2602}
2603
Woojung Huh20ff5562016-03-16 22:10:40 +00002604static void lan78xx_init_stats(struct lan78xx_net *dev)
2605{
2606 u32 *p;
2607 int i;
2608
2609 /* initialize for stats update
2610 * some counters are 20bits and some are 32bits
2611 */
2612 p = (u32 *)&dev->stats.rollover_max;
2613 for (i = 0; i < (sizeof(dev->stats.rollover_max) / (sizeof(u32))); i++)
2614 p[i] = 0xFFFFF;
2615
2616 dev->stats.rollover_max.rx_unicast_byte_count = 0xFFFFFFFF;
2617 dev->stats.rollover_max.rx_broadcast_byte_count = 0xFFFFFFFF;
2618 dev->stats.rollover_max.rx_multicast_byte_count = 0xFFFFFFFF;
2619 dev->stats.rollover_max.eee_rx_lpi_transitions = 0xFFFFFFFF;
2620 dev->stats.rollover_max.eee_rx_lpi_time = 0xFFFFFFFF;
2621 dev->stats.rollover_max.tx_unicast_byte_count = 0xFFFFFFFF;
2622 dev->stats.rollover_max.tx_broadcast_byte_count = 0xFFFFFFFF;
2623 dev->stats.rollover_max.tx_multicast_byte_count = 0xFFFFFFFF;
2624 dev->stats.rollover_max.eee_tx_lpi_transitions = 0xFFFFFFFF;
2625 dev->stats.rollover_max.eee_tx_lpi_time = 0xFFFFFFFF;
2626
Phil Elwellfed56072018-04-11 12:02:47 +01002627 set_bit(EVENT_STAT_UPDATE, &dev->flags);
Woojung Huh20ff5562016-03-16 22:10:40 +00002628}
2629
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002630static int lan78xx_open(struct net_device *net)
2631{
2632 struct lan78xx_net *dev = netdev_priv(net);
2633 int ret;
2634
2635 ret = usb_autopm_get_interface(dev->intf);
2636 if (ret < 0)
2637 goto out;
2638
Alexander Graf92571a12018-04-04 00:19:35 +02002639 phy_start(net->phydev);
2640
2641 netif_dbg(dev, ifup, dev->net, "phy initialised successfully");
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002642
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002643 /* for Link Check */
2644 if (dev->urb_intr) {
2645 ret = usb_submit_urb(dev->urb_intr, GFP_KERNEL);
2646 if (ret < 0) {
2647 netif_err(dev, ifup, dev->net,
2648 "intr submit %d\n", ret);
2649 goto done;
2650 }
2651 }
2652
Woojung Huh20ff5562016-03-16 22:10:40 +00002653 lan78xx_init_stats(dev);
2654
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002655 set_bit(EVENT_DEV_OPEN, &dev->flags);
2656
2657 netif_start_queue(net);
2658
2659 dev->link_on = false;
2660
2661 lan78xx_defer_kevent(dev, EVENT_LINK_RESET);
2662done:
2663 usb_autopm_put_interface(dev->intf);
2664
2665out:
2666 return ret;
2667}
2668
2669static void lan78xx_terminate_urbs(struct lan78xx_net *dev)
2670{
2671 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(unlink_wakeup);
2672 DECLARE_WAITQUEUE(wait, current);
2673 int temp;
2674
2675 /* ensure there are no more active urbs */
2676 add_wait_queue(&unlink_wakeup, &wait);
2677 set_current_state(TASK_UNINTERRUPTIBLE);
2678 dev->wait = &unlink_wakeup;
2679 temp = unlink_urbs(dev, &dev->txq) + unlink_urbs(dev, &dev->rxq);
2680
2681 /* maybe wait for deletions to finish. */
2682 while (!skb_queue_empty(&dev->rxq) &&
2683 !skb_queue_empty(&dev->txq) &&
2684 !skb_queue_empty(&dev->done)) {
2685 schedule_timeout(msecs_to_jiffies(UNLINK_TIMEOUT_MS));
2686 set_current_state(TASK_UNINTERRUPTIBLE);
2687 netif_dbg(dev, ifdown, dev->net,
2688 "waited for %d urb completions\n", temp);
2689 }
2690 set_current_state(TASK_RUNNING);
2691 dev->wait = NULL;
2692 remove_wait_queue(&unlink_wakeup, &wait);
2693}
2694
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002695static int lan78xx_stop(struct net_device *net)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002696{
2697 struct lan78xx_net *dev = netdev_priv(net);
2698
Woojung Huh20ff5562016-03-16 22:10:40 +00002699 if (timer_pending(&dev->stat_monitor))
2700 del_timer_sync(&dev->stat_monitor);
2701
Alexander Graf92571a12018-04-04 00:19:35 +02002702 if (net->phydev)
2703 phy_stop(net->phydev);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002704
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002705 clear_bit(EVENT_DEV_OPEN, &dev->flags);
2706 netif_stop_queue(net);
2707
2708 netif_info(dev, ifdown, dev->net,
2709 "stop stats: rx/tx %lu/%lu, errs %lu/%lu\n",
2710 net->stats.rx_packets, net->stats.tx_packets,
2711 net->stats.rx_errors, net->stats.tx_errors);
2712
2713 lan78xx_terminate_urbs(dev);
2714
2715 usb_kill_urb(dev->urb_intr);
2716
2717 skb_queue_purge(&dev->rxq_pause);
2718
2719 /* deferred work (task, timer, softirq) must also stop.
2720 * can't flush_scheduled_work() until we drop rtnl (later),
2721 * else workers could deadlock; so make workers a NOP.
2722 */
2723 dev->flags = 0;
2724 cancel_delayed_work_sync(&dev->wq);
2725 tasklet_kill(&dev->bh);
2726
2727 usb_autopm_put_interface(dev->intf);
2728
2729 return 0;
2730}
2731
2732static int lan78xx_linearize(struct sk_buff *skb)
2733{
2734 return skb_linearize(skb);
2735}
2736
2737static struct sk_buff *lan78xx_tx_prep(struct lan78xx_net *dev,
2738 struct sk_buff *skb, gfp_t flags)
2739{
2740 u32 tx_cmd_a, tx_cmd_b;
2741
Eric Dumazetd4ca7352017-04-19 09:59:24 -07002742 if (skb_cow_head(skb, TX_OVERHEAD)) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002743 dev_kfree_skb_any(skb);
Eric Dumazetd4ca7352017-04-19 09:59:24 -07002744 return NULL;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002745 }
2746
2747 if (lan78xx_linearize(skb) < 0)
2748 return NULL;
2749
2750 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN_MASK_) | TX_CMD_A_FCS_;
2751
2752 if (skb->ip_summed == CHECKSUM_PARTIAL)
2753 tx_cmd_a |= TX_CMD_A_IPE_ | TX_CMD_A_TPE_;
2754
2755 tx_cmd_b = 0;
2756 if (skb_is_gso(skb)) {
2757 u16 mss = max(skb_shinfo(skb)->gso_size, TX_CMD_B_MSS_MIN_);
2758
2759 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT_) & TX_CMD_B_MSS_MASK_;
2760
2761 tx_cmd_a |= TX_CMD_A_LSO_;
2762 }
2763
2764 if (skb_vlan_tag_present(skb)) {
2765 tx_cmd_a |= TX_CMD_A_IVTG_;
2766 tx_cmd_b |= skb_vlan_tag_get(skb) & TX_CMD_B_VTAG_MASK_;
2767 }
2768
2769 skb_push(skb, 4);
2770 cpu_to_le32s(&tx_cmd_b);
2771 memcpy(skb->data, &tx_cmd_b, 4);
2772
2773 skb_push(skb, 4);
2774 cpu_to_le32s(&tx_cmd_a);
2775 memcpy(skb->data, &tx_cmd_a, 4);
2776
2777 return skb;
2778}
2779
2780static enum skb_state defer_bh(struct lan78xx_net *dev, struct sk_buff *skb,
2781 struct sk_buff_head *list, enum skb_state state)
2782{
2783 unsigned long flags;
2784 enum skb_state old_state;
2785 struct skb_data *entry = (struct skb_data *)skb->cb;
2786
2787 spin_lock_irqsave(&list->lock, flags);
2788 old_state = entry->state;
2789 entry->state = state;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002790
2791 __skb_unlink(skb, list);
2792 spin_unlock(&list->lock);
2793 spin_lock(&dev->done.lock);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002794
2795 __skb_queue_tail(&dev->done, skb);
2796 if (skb_queue_len(&dev->done) == 1)
2797 tasklet_schedule(&dev->bh);
2798 spin_unlock_irqrestore(&dev->done.lock, flags);
2799
2800 return old_state;
2801}
2802
2803static void tx_complete(struct urb *urb)
2804{
2805 struct sk_buff *skb = (struct sk_buff *)urb->context;
2806 struct skb_data *entry = (struct skb_data *)skb->cb;
2807 struct lan78xx_net *dev = entry->dev;
2808
2809 if (urb->status == 0) {
Woojung Huh74d79a22016-04-25 22:22:32 +00002810 dev->net->stats.tx_packets += entry->num_of_packet;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002811 dev->net->stats.tx_bytes += entry->length;
2812 } else {
2813 dev->net->stats.tx_errors++;
2814
2815 switch (urb->status) {
2816 case -EPIPE:
2817 lan78xx_defer_kevent(dev, EVENT_TX_HALT);
2818 break;
2819
2820 /* software-driven interface shutdown */
2821 case -ECONNRESET:
2822 case -ESHUTDOWN:
2823 break;
2824
2825 case -EPROTO:
2826 case -ETIME:
2827 case -EILSEQ:
2828 netif_stop_queue(dev->net);
2829 break;
2830 default:
2831 netif_dbg(dev, tx_err, dev->net,
2832 "tx err %d\n", entry->urb->status);
2833 break;
2834 }
2835 }
2836
2837 usb_autopm_put_interface_async(dev->intf);
2838
Woojung.Huh@microchip.com81c38e82015-08-11 15:21:41 +00002839 defer_bh(dev, skb, &dev->txq, tx_done);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002840}
2841
2842static void lan78xx_queue_skb(struct sk_buff_head *list,
2843 struct sk_buff *newsk, enum skb_state state)
2844{
2845 struct skb_data *entry = (struct skb_data *)newsk->cb;
2846
2847 __skb_queue_tail(list, newsk);
2848 entry->state = state;
2849}
2850
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002851static netdev_tx_t
2852lan78xx_start_xmit(struct sk_buff *skb, struct net_device *net)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002853{
2854 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.com81c38e82015-08-11 15:21:41 +00002855 struct sk_buff *skb2 = NULL;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002856
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002857 if (skb) {
Woojung.Huh@microchip.com81c38e82015-08-11 15:21:41 +00002858 skb_tx_timestamp(skb);
2859 skb2 = lan78xx_tx_prep(dev, skb, GFP_ATOMIC);
2860 }
2861
2862 if (skb2) {
2863 skb_queue_tail(&dev->txq_pend, skb2);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002864
Woojung.Huh@microchip.com4b2a4a92016-01-27 22:57:54 +00002865 /* throttle TX patch at slower than SUPER SPEED USB */
2866 if ((dev->udev->speed < USB_SPEED_SUPER) &&
2867 (skb_queue_len(&dev->txq_pend) > 10))
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002868 netif_stop_queue(net);
2869 } else {
2870 netif_dbg(dev, tx_err, dev->net,
2871 "lan78xx_tx_prep return NULL\n");
2872 dev->net->stats.tx_errors++;
2873 dev->net->stats.tx_dropped++;
2874 }
2875
2876 tasklet_schedule(&dev->bh);
2877
2878 return NETDEV_TX_OK;
2879}
2880
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002881static int
2882lan78xx_get_endpoints(struct lan78xx_net *dev, struct usb_interface *intf)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002883{
2884 int tmp;
2885 struct usb_host_interface *alt = NULL;
2886 struct usb_host_endpoint *in = NULL, *out = NULL;
2887 struct usb_host_endpoint *status = NULL;
2888
2889 for (tmp = 0; tmp < intf->num_altsetting; tmp++) {
2890 unsigned ep;
2891
2892 in = NULL;
2893 out = NULL;
2894 status = NULL;
2895 alt = intf->altsetting + tmp;
2896
2897 for (ep = 0; ep < alt->desc.bNumEndpoints; ep++) {
2898 struct usb_host_endpoint *e;
2899 int intr = 0;
2900
2901 e = alt->endpoint + ep;
2902 switch (e->desc.bmAttributes) {
2903 case USB_ENDPOINT_XFER_INT:
2904 if (!usb_endpoint_dir_in(&e->desc))
2905 continue;
2906 intr = 1;
2907 /* FALLTHROUGH */
2908 case USB_ENDPOINT_XFER_BULK:
2909 break;
2910 default:
2911 continue;
2912 }
2913 if (usb_endpoint_dir_in(&e->desc)) {
2914 if (!intr && !in)
2915 in = e;
2916 else if (intr && !status)
2917 status = e;
2918 } else {
2919 if (!out)
2920 out = e;
2921 }
2922 }
2923 if (in && out)
2924 break;
2925 }
2926 if (!alt || !in || !out)
2927 return -EINVAL;
2928
2929 dev->pipe_in = usb_rcvbulkpipe(dev->udev,
2930 in->desc.bEndpointAddress &
2931 USB_ENDPOINT_NUMBER_MASK);
2932 dev->pipe_out = usb_sndbulkpipe(dev->udev,
2933 out->desc.bEndpointAddress &
2934 USB_ENDPOINT_NUMBER_MASK);
2935 dev->ep_intr = status;
2936
2937 return 0;
2938}
2939
2940static int lan78xx_bind(struct lan78xx_net *dev, struct usb_interface *intf)
2941{
2942 struct lan78xx_priv *pdata = NULL;
2943 int ret;
2944 int i;
2945
2946 ret = lan78xx_get_endpoints(dev, intf);
2947
2948 dev->data[0] = (unsigned long)kzalloc(sizeof(*pdata), GFP_KERNEL);
2949
2950 pdata = (struct lan78xx_priv *)(dev->data[0]);
2951 if (!pdata) {
2952 netdev_warn(dev->net, "Unable to allocate lan78xx_priv");
2953 return -ENOMEM;
2954 }
2955
2956 pdata->dev = dev;
2957
2958 spin_lock_init(&pdata->rfe_ctl_lock);
2959 mutex_init(&pdata->dataport_mutex);
2960
2961 INIT_WORK(&pdata->set_multicast, lan78xx_deferred_multicast_write);
2962
2963 for (i = 0; i < DP_SEL_VHF_VLAN_LEN; i++)
2964 pdata->vlan_table[i] = 0;
2965
2966 INIT_WORK(&pdata->set_vlan, lan78xx_deferred_vlan_write);
2967
2968 dev->net->features = 0;
2969
2970 if (DEFAULT_TX_CSUM_ENABLE)
2971 dev->net->features |= NETIF_F_HW_CSUM;
2972
2973 if (DEFAULT_RX_CSUM_ENABLE)
2974 dev->net->features |= NETIF_F_RXCSUM;
2975
2976 if (DEFAULT_TSO_CSUM_ENABLE)
2977 dev->net->features |= NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_SG;
2978
2979 dev->net->hw_features = dev->net->features;
2980
Woojung Huhcc89c322016-11-01 20:02:00 +00002981 ret = lan78xx_setup_irq_domain(dev);
2982 if (ret < 0) {
2983 netdev_warn(dev->net,
2984 "lan78xx_setup_irq_domain() failed : %d", ret);
Raghuram Chary J2d2d99e2018-03-27 14:51:16 +05302985 goto out1;
Woojung Huhcc89c322016-11-01 20:02:00 +00002986 }
2987
Nisar Sayed0573f942017-08-01 10:24:33 +00002988 dev->net->hard_header_len += TX_OVERHEAD;
2989 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
2990
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002991 /* Init all registers */
2992 ret = lan78xx_reset(dev);
Raghuram Chary J2d2d99e2018-03-27 14:51:16 +05302993 if (ret) {
2994 netdev_warn(dev->net, "Registers INIT FAILED....");
2995 goto out2;
2996 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002997
Nisar Sayedfb52c3b2017-08-01 10:24:17 +00002998 ret = lan78xx_mdio_init(dev);
Raghuram Chary J2d2d99e2018-03-27 14:51:16 +05302999 if (ret) {
3000 netdev_warn(dev->net, "MDIO INIT FAILED.....");
3001 goto out2;
3002 }
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00003003
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003004 dev->net->flags |= IFF_MULTICAST;
3005
3006 pdata->wol = WAKE_MAGIC;
3007
Nisar Sayedfb52c3b2017-08-01 10:24:17 +00003008 return ret;
Raghuram Chary J2d2d99e2018-03-27 14:51:16 +05303009
3010out2:
3011 lan78xx_remove_irq_domain(dev);
3012
3013out1:
3014 netdev_warn(dev->net, "Bind routine FAILED");
3015 cancel_work_sync(&pdata->set_multicast);
3016 cancel_work_sync(&pdata->set_vlan);
3017 kfree(pdata);
3018 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003019}
3020
3021static void lan78xx_unbind(struct lan78xx_net *dev, struct usb_interface *intf)
3022{
3023 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
3024
Woojung Huhcc89c322016-11-01 20:02:00 +00003025 lan78xx_remove_irq_domain(dev);
3026
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00003027 lan78xx_remove_mdio(dev);
3028
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003029 if (pdata) {
Raghuram Chary J2d2d99e2018-03-27 14:51:16 +05303030 cancel_work_sync(&pdata->set_multicast);
3031 cancel_work_sync(&pdata->set_vlan);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003032 netif_dbg(dev, ifdown, dev->net, "free pdata");
3033 kfree(pdata);
3034 pdata = NULL;
3035 dev->data[0] = 0;
3036 }
3037}
3038
3039static void lan78xx_rx_csum_offload(struct lan78xx_net *dev,
3040 struct sk_buff *skb,
3041 u32 rx_cmd_a, u32 rx_cmd_b)
3042{
3043 if (!(dev->net->features & NETIF_F_RXCSUM) ||
3044 unlikely(rx_cmd_a & RX_CMD_A_ICSM_)) {
3045 skb->ip_summed = CHECKSUM_NONE;
3046 } else {
3047 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT_));
3048 skb->ip_summed = CHECKSUM_COMPLETE;
3049 }
3050}
3051
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08003052static void lan78xx_skb_return(struct lan78xx_net *dev, struct sk_buff *skb)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003053{
3054 int status;
3055
3056 if (test_bit(EVENT_RX_PAUSED, &dev->flags)) {
3057 skb_queue_tail(&dev->rxq_pause, skb);
3058 return;
3059 }
3060
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003061 dev->net->stats.rx_packets++;
3062 dev->net->stats.rx_bytes += skb->len;
3063
Woojung Huh74d79a22016-04-25 22:22:32 +00003064 skb->protocol = eth_type_trans(skb, dev->net);
3065
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003066 netif_dbg(dev, rx_status, dev->net, "< rx, len %zu, type 0x%x\n",
3067 skb->len + sizeof(struct ethhdr), skb->protocol);
3068 memset(skb->cb, 0, sizeof(struct skb_data));
3069
3070 if (skb_defer_rx_timestamp(skb))
3071 return;
3072
3073 status = netif_rx(skb);
3074 if (status != NET_RX_SUCCESS)
3075 netif_dbg(dev, rx_err, dev->net,
3076 "netif_rx status %d\n", status);
3077}
3078
3079static int lan78xx_rx(struct lan78xx_net *dev, struct sk_buff *skb)
3080{
3081 if (skb->len < dev->net->hard_header_len)
3082 return 0;
3083
3084 while (skb->len > 0) {
3085 u32 rx_cmd_a, rx_cmd_b, align_count, size;
3086 u16 rx_cmd_c;
3087 struct sk_buff *skb2;
3088 unsigned char *packet;
3089
3090 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
3091 le32_to_cpus(&rx_cmd_a);
3092 skb_pull(skb, sizeof(rx_cmd_a));
3093
3094 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
3095 le32_to_cpus(&rx_cmd_b);
3096 skb_pull(skb, sizeof(rx_cmd_b));
3097
3098 memcpy(&rx_cmd_c, skb->data, sizeof(rx_cmd_c));
3099 le16_to_cpus(&rx_cmd_c);
3100 skb_pull(skb, sizeof(rx_cmd_c));
3101
3102 packet = skb->data;
3103
3104 /* get the packet length */
3105 size = (rx_cmd_a & RX_CMD_A_LEN_MASK_);
3106 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
3107
3108 if (unlikely(rx_cmd_a & RX_CMD_A_RED_)) {
3109 netif_dbg(dev, rx_err, dev->net,
3110 "Error rx_cmd_a=0x%08x", rx_cmd_a);
3111 } else {
3112 /* last frame in this batch */
3113 if (skb->len == size) {
3114 lan78xx_rx_csum_offload(dev, skb,
3115 rx_cmd_a, rx_cmd_b);
3116
3117 skb_trim(skb, skb->len - 4); /* remove fcs */
3118 skb->truesize = size + sizeof(struct sk_buff);
3119
3120 return 1;
3121 }
3122
3123 skb2 = skb_clone(skb, GFP_ATOMIC);
3124 if (unlikely(!skb2)) {
3125 netdev_warn(dev->net, "Error allocating skb");
3126 return 0;
3127 }
3128
3129 skb2->len = size;
3130 skb2->data = packet;
3131 skb_set_tail_pointer(skb2, size);
3132
3133 lan78xx_rx_csum_offload(dev, skb2, rx_cmd_a, rx_cmd_b);
3134
3135 skb_trim(skb2, skb2->len - 4); /* remove fcs */
3136 skb2->truesize = size + sizeof(struct sk_buff);
3137
3138 lan78xx_skb_return(dev, skb2);
3139 }
3140
3141 skb_pull(skb, size);
3142
3143 /* padding bytes before the next frame starts */
3144 if (skb->len)
3145 skb_pull(skb, align_count);
3146 }
3147
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003148 return 1;
3149}
3150
3151static inline void rx_process(struct lan78xx_net *dev, struct sk_buff *skb)
3152{
3153 if (!lan78xx_rx(dev, skb)) {
3154 dev->net->stats.rx_errors++;
3155 goto done;
3156 }
3157
3158 if (skb->len) {
3159 lan78xx_skb_return(dev, skb);
3160 return;
3161 }
3162
3163 netif_dbg(dev, rx_err, dev->net, "drop\n");
3164 dev->net->stats.rx_errors++;
3165done:
3166 skb_queue_tail(&dev->done, skb);
3167}
3168
3169static void rx_complete(struct urb *urb);
3170
3171static int rx_submit(struct lan78xx_net *dev, struct urb *urb, gfp_t flags)
3172{
3173 struct sk_buff *skb;
3174 struct skb_data *entry;
3175 unsigned long lockflags;
3176 size_t size = dev->rx_urb_size;
3177 int ret = 0;
3178
3179 skb = netdev_alloc_skb_ip_align(dev->net, size);
3180 if (!skb) {
3181 usb_free_urb(urb);
3182 return -ENOMEM;
3183 }
3184
3185 entry = (struct skb_data *)skb->cb;
3186 entry->urb = urb;
3187 entry->dev = dev;
3188 entry->length = 0;
3189
3190 usb_fill_bulk_urb(urb, dev->udev, dev->pipe_in,
3191 skb->data, size, rx_complete, skb);
3192
3193 spin_lock_irqsave(&dev->rxq.lock, lockflags);
3194
3195 if (netif_device_present(dev->net) &&
3196 netif_running(dev->net) &&
3197 !test_bit(EVENT_RX_HALT, &dev->flags) &&
3198 !test_bit(EVENT_DEV_ASLEEP, &dev->flags)) {
3199 ret = usb_submit_urb(urb, GFP_ATOMIC);
3200 switch (ret) {
3201 case 0:
3202 lan78xx_queue_skb(&dev->rxq, skb, rx_start);
3203 break;
3204 case -EPIPE:
3205 lan78xx_defer_kevent(dev, EVENT_RX_HALT);
3206 break;
3207 case -ENODEV:
3208 netif_dbg(dev, ifdown, dev->net, "device gone\n");
3209 netif_device_detach(dev->net);
3210 break;
3211 case -EHOSTUNREACH:
3212 ret = -ENOLINK;
3213 break;
3214 default:
3215 netif_dbg(dev, rx_err, dev->net,
3216 "rx submit, %d\n", ret);
3217 tasklet_schedule(&dev->bh);
3218 }
3219 } else {
3220 netif_dbg(dev, ifdown, dev->net, "rx: stopped\n");
3221 ret = -ENOLINK;
3222 }
3223 spin_unlock_irqrestore(&dev->rxq.lock, lockflags);
3224 if (ret) {
3225 dev_kfree_skb_any(skb);
3226 usb_free_urb(urb);
3227 }
3228 return ret;
3229}
3230
3231static void rx_complete(struct urb *urb)
3232{
3233 struct sk_buff *skb = (struct sk_buff *)urb->context;
3234 struct skb_data *entry = (struct skb_data *)skb->cb;
3235 struct lan78xx_net *dev = entry->dev;
3236 int urb_status = urb->status;
3237 enum skb_state state;
3238
3239 skb_put(skb, urb->actual_length);
3240 state = rx_done;
3241 entry->urb = NULL;
3242
3243 switch (urb_status) {
3244 case 0:
3245 if (skb->len < dev->net->hard_header_len) {
3246 state = rx_cleanup;
3247 dev->net->stats.rx_errors++;
3248 dev->net->stats.rx_length_errors++;
3249 netif_dbg(dev, rx_err, dev->net,
3250 "rx length %d\n", skb->len);
3251 }
3252 usb_mark_last_busy(dev->udev);
3253 break;
3254 case -EPIPE:
3255 dev->net->stats.rx_errors++;
3256 lan78xx_defer_kevent(dev, EVENT_RX_HALT);
3257 /* FALLTHROUGH */
3258 case -ECONNRESET: /* async unlink */
3259 case -ESHUTDOWN: /* hardware gone */
3260 netif_dbg(dev, ifdown, dev->net,
3261 "rx shutdown, code %d\n", urb_status);
3262 state = rx_cleanup;
3263 entry->urb = urb;
3264 urb = NULL;
3265 break;
3266 case -EPROTO:
3267 case -ETIME:
3268 case -EILSEQ:
3269 dev->net->stats.rx_errors++;
3270 state = rx_cleanup;
3271 entry->urb = urb;
3272 urb = NULL;
3273 break;
3274
3275 /* data overrun ... flush fifo? */
3276 case -EOVERFLOW:
3277 dev->net->stats.rx_over_errors++;
3278 /* FALLTHROUGH */
3279
3280 default:
3281 state = rx_cleanup;
3282 dev->net->stats.rx_errors++;
3283 netif_dbg(dev, rx_err, dev->net, "rx status %d\n", urb_status);
3284 break;
3285 }
3286
3287 state = defer_bh(dev, skb, &dev->rxq, state);
3288
3289 if (urb) {
3290 if (netif_running(dev->net) &&
3291 !test_bit(EVENT_RX_HALT, &dev->flags) &&
3292 state != unlink_start) {
3293 rx_submit(dev, urb, GFP_ATOMIC);
3294 return;
3295 }
3296 usb_free_urb(urb);
3297 }
3298 netif_dbg(dev, rx_err, dev->net, "no read resubmitted\n");
3299}
3300
3301static void lan78xx_tx_bh(struct lan78xx_net *dev)
3302{
3303 int length;
3304 struct urb *urb = NULL;
3305 struct skb_data *entry;
3306 unsigned long flags;
3307 struct sk_buff_head *tqp = &dev->txq_pend;
3308 struct sk_buff *skb, *skb2;
3309 int ret;
3310 int count, pos;
3311 int skb_totallen, pkt_cnt;
3312
3313 skb_totallen = 0;
3314 pkt_cnt = 0;
Woojung Huh74d79a22016-04-25 22:22:32 +00003315 count = 0;
3316 length = 0;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003317 for (skb = tqp->next; pkt_cnt < tqp->qlen; skb = skb->next) {
3318 if (skb_is_gso(skb)) {
3319 if (pkt_cnt) {
3320 /* handle previous packets first */
3321 break;
3322 }
Woojung Huh74d79a22016-04-25 22:22:32 +00003323 count = 1;
3324 length = skb->len - TX_OVERHEAD;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003325 skb2 = skb_dequeue(tqp);
3326 goto gso_skb;
3327 }
3328
3329 if ((skb_totallen + skb->len) > MAX_SINGLE_PACKET_SIZE)
3330 break;
3331 skb_totallen = skb->len + roundup(skb_totallen, sizeof(u32));
3332 pkt_cnt++;
3333 }
3334
3335 /* copy to a single skb */
3336 skb = alloc_skb(skb_totallen, GFP_ATOMIC);
3337 if (!skb)
3338 goto drop;
3339
3340 skb_put(skb, skb_totallen);
3341
3342 for (count = pos = 0; count < pkt_cnt; count++) {
3343 skb2 = skb_dequeue(tqp);
3344 if (skb2) {
Woojung Huh74d79a22016-04-25 22:22:32 +00003345 length += (skb2->len - TX_OVERHEAD);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003346 memcpy(skb->data + pos, skb2->data, skb2->len);
3347 pos += roundup(skb2->len, sizeof(u32));
3348 dev_kfree_skb(skb2);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003349 }
3350 }
3351
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003352gso_skb:
3353 urb = usb_alloc_urb(0, GFP_ATOMIC);
Wolfram Sangd7c4e842016-08-11 23:05:27 +02003354 if (!urb)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003355 goto drop;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003356
3357 entry = (struct skb_data *)skb->cb;
3358 entry->urb = urb;
3359 entry->dev = dev;
3360 entry->length = length;
Woojung Huh74d79a22016-04-25 22:22:32 +00003361 entry->num_of_packet = count;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003362
3363 spin_lock_irqsave(&dev->txq.lock, flags);
3364 ret = usb_autopm_get_interface_async(dev->intf);
3365 if (ret < 0) {
3366 spin_unlock_irqrestore(&dev->txq.lock, flags);
3367 goto drop;
3368 }
3369
3370 usb_fill_bulk_urb(urb, dev->udev, dev->pipe_out,
3371 skb->data, skb->len, tx_complete, skb);
3372
3373 if (length % dev->maxpacket == 0) {
3374 /* send USB_ZERO_PACKET */
3375 urb->transfer_flags |= URB_ZERO_PACKET;
3376 }
3377
3378#ifdef CONFIG_PM
3379 /* if this triggers the device is still a sleep */
3380 if (test_bit(EVENT_DEV_ASLEEP, &dev->flags)) {
3381 /* transmission will be done in resume */
3382 usb_anchor_urb(urb, &dev->deferred);
3383 /* no use to process more packets */
3384 netif_stop_queue(dev->net);
3385 usb_put_urb(urb);
3386 spin_unlock_irqrestore(&dev->txq.lock, flags);
3387 netdev_dbg(dev->net, "Delaying transmission for resumption\n");
3388 return;
3389 }
3390#endif
3391
3392 ret = usb_submit_urb(urb, GFP_ATOMIC);
3393 switch (ret) {
3394 case 0:
Florian Westphal860e9532016-05-03 16:33:13 +02003395 netif_trans_update(dev->net);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003396 lan78xx_queue_skb(&dev->txq, skb, tx_start);
3397 if (skb_queue_len(&dev->txq) >= dev->tx_qlen)
3398 netif_stop_queue(dev->net);
3399 break;
3400 case -EPIPE:
3401 netif_stop_queue(dev->net);
3402 lan78xx_defer_kevent(dev, EVENT_TX_HALT);
3403 usb_autopm_put_interface_async(dev->intf);
3404 break;
3405 default:
3406 usb_autopm_put_interface_async(dev->intf);
3407 netif_dbg(dev, tx_err, dev->net,
3408 "tx: submit urb err %d\n", ret);
3409 break;
3410 }
3411
3412 spin_unlock_irqrestore(&dev->txq.lock, flags);
3413
3414 if (ret) {
3415 netif_dbg(dev, tx_err, dev->net, "drop, code %d\n", ret);
3416drop:
3417 dev->net->stats.tx_dropped++;
3418 if (skb)
3419 dev_kfree_skb_any(skb);
3420 usb_free_urb(urb);
3421 } else
3422 netif_dbg(dev, tx_queued, dev->net,
3423 "> tx, len %d, type 0x%x\n", length, skb->protocol);
3424}
3425
3426static void lan78xx_rx_bh(struct lan78xx_net *dev)
3427{
3428 struct urb *urb;
3429 int i;
3430
3431 if (skb_queue_len(&dev->rxq) < dev->rx_qlen) {
3432 for (i = 0; i < 10; i++) {
3433 if (skb_queue_len(&dev->rxq) >= dev->rx_qlen)
3434 break;
3435 urb = usb_alloc_urb(0, GFP_ATOMIC);
3436 if (urb)
3437 if (rx_submit(dev, urb, GFP_ATOMIC) == -ENOLINK)
3438 return;
3439 }
3440
3441 if (skb_queue_len(&dev->rxq) < dev->rx_qlen)
3442 tasklet_schedule(&dev->bh);
3443 }
3444 if (skb_queue_len(&dev->txq) < dev->tx_qlen)
3445 netif_wake_queue(dev->net);
3446}
3447
3448static void lan78xx_bh(unsigned long param)
3449{
3450 struct lan78xx_net *dev = (struct lan78xx_net *)param;
3451 struct sk_buff *skb;
3452 struct skb_data *entry;
3453
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003454 while ((skb = skb_dequeue(&dev->done))) {
3455 entry = (struct skb_data *)(skb->cb);
3456 switch (entry->state) {
3457 case rx_done:
3458 entry->state = rx_cleanup;
3459 rx_process(dev, skb);
3460 continue;
3461 case tx_done:
3462 usb_free_urb(entry->urb);
3463 dev_kfree_skb(skb);
3464 continue;
3465 case rx_cleanup:
3466 usb_free_urb(entry->urb);
3467 dev_kfree_skb(skb);
3468 continue;
3469 default:
3470 netdev_dbg(dev->net, "skb state %d\n", entry->state);
3471 return;
3472 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003473 }
3474
3475 if (netif_device_present(dev->net) && netif_running(dev->net)) {
Woojung Huh20ff5562016-03-16 22:10:40 +00003476 /* reset update timer delta */
3477 if (timer_pending(&dev->stat_monitor) && (dev->delta != 1)) {
3478 dev->delta = 1;
3479 mod_timer(&dev->stat_monitor,
3480 jiffies + STAT_UPDATE_TIMER);
3481 }
3482
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003483 if (!skb_queue_empty(&dev->txq_pend))
3484 lan78xx_tx_bh(dev);
3485
3486 if (!timer_pending(&dev->delay) &&
3487 !test_bit(EVENT_RX_HALT, &dev->flags))
3488 lan78xx_rx_bh(dev);
3489 }
3490}
3491
3492static void lan78xx_delayedwork(struct work_struct *work)
3493{
3494 int status;
3495 struct lan78xx_net *dev;
3496
3497 dev = container_of(work, struct lan78xx_net, wq.work);
3498
3499 if (test_bit(EVENT_TX_HALT, &dev->flags)) {
3500 unlink_urbs(dev, &dev->txq);
3501 status = usb_autopm_get_interface(dev->intf);
3502 if (status < 0)
3503 goto fail_pipe;
3504 status = usb_clear_halt(dev->udev, dev->pipe_out);
3505 usb_autopm_put_interface(dev->intf);
3506 if (status < 0 &&
3507 status != -EPIPE &&
3508 status != -ESHUTDOWN) {
3509 if (netif_msg_tx_err(dev))
3510fail_pipe:
3511 netdev_err(dev->net,
3512 "can't clear tx halt, status %d\n",
3513 status);
3514 } else {
3515 clear_bit(EVENT_TX_HALT, &dev->flags);
3516 if (status != -ESHUTDOWN)
3517 netif_wake_queue(dev->net);
3518 }
3519 }
3520 if (test_bit(EVENT_RX_HALT, &dev->flags)) {
3521 unlink_urbs(dev, &dev->rxq);
3522 status = usb_autopm_get_interface(dev->intf);
3523 if (status < 0)
3524 goto fail_halt;
3525 status = usb_clear_halt(dev->udev, dev->pipe_in);
3526 usb_autopm_put_interface(dev->intf);
3527 if (status < 0 &&
3528 status != -EPIPE &&
3529 status != -ESHUTDOWN) {
3530 if (netif_msg_rx_err(dev))
3531fail_halt:
3532 netdev_err(dev->net,
3533 "can't clear rx halt, status %d\n",
3534 status);
3535 } else {
3536 clear_bit(EVENT_RX_HALT, &dev->flags);
3537 tasklet_schedule(&dev->bh);
3538 }
3539 }
3540
3541 if (test_bit(EVENT_LINK_RESET, &dev->flags)) {
3542 int ret = 0;
3543
3544 clear_bit(EVENT_LINK_RESET, &dev->flags);
3545 status = usb_autopm_get_interface(dev->intf);
3546 if (status < 0)
3547 goto skip_reset;
3548 if (lan78xx_link_reset(dev) < 0) {
3549 usb_autopm_put_interface(dev->intf);
3550skip_reset:
3551 netdev_info(dev->net, "link reset failed (%d)\n",
3552 ret);
3553 } else {
3554 usb_autopm_put_interface(dev->intf);
3555 }
3556 }
Woojung Huh20ff5562016-03-16 22:10:40 +00003557
3558 if (test_bit(EVENT_STAT_UPDATE, &dev->flags)) {
3559 lan78xx_update_stats(dev);
3560
3561 clear_bit(EVENT_STAT_UPDATE, &dev->flags);
3562
3563 mod_timer(&dev->stat_monitor,
3564 jiffies + (STAT_UPDATE_TIMER * dev->delta));
3565
3566 dev->delta = min((dev->delta * 2), 50);
3567 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003568}
3569
3570static void intr_complete(struct urb *urb)
3571{
3572 struct lan78xx_net *dev = urb->context;
3573 int status = urb->status;
3574
3575 switch (status) {
3576 /* success */
3577 case 0:
3578 lan78xx_status(dev, urb);
3579 break;
3580
3581 /* software-driven interface shutdown */
3582 case -ENOENT: /* urb killed */
3583 case -ESHUTDOWN: /* hardware gone */
3584 netif_dbg(dev, ifdown, dev->net,
3585 "intr shutdown, code %d\n", status);
3586 return;
3587
3588 /* NOTE: not throttling like RX/TX, since this endpoint
3589 * already polls infrequently
3590 */
3591 default:
3592 netdev_dbg(dev->net, "intr status %d\n", status);
3593 break;
3594 }
3595
3596 if (!netif_running(dev->net))
3597 return;
3598
3599 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length);
3600 status = usb_submit_urb(urb, GFP_ATOMIC);
3601 if (status != 0)
3602 netif_err(dev, timer, dev->net,
3603 "intr resubmit --> %d\n", status);
3604}
3605
3606static void lan78xx_disconnect(struct usb_interface *intf)
3607{
3608 struct lan78xx_net *dev;
3609 struct usb_device *udev;
3610 struct net_device *net;
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05303611 struct phy_device *phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003612
3613 dev = usb_get_intfdata(intf);
3614 usb_set_intfdata(intf, NULL);
3615 if (!dev)
3616 return;
3617
3618 udev = interface_to_usbdev(intf);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003619 net = dev->net;
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05303620 phydev = net->phydev;
Alexander Graf92571a12018-04-04 00:19:35 +02003621
3622 phy_unregister_fixup_for_uid(PHY_KSZ9031RNX, 0xfffffff0);
3623 phy_unregister_fixup_for_uid(PHY_LAN8835, 0xfffffff0);
3624
3625 phy_disconnect(net->phydev);
3626
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05303627 if (phy_is_pseudo_fixed_link(phydev))
3628 fixed_phy_unregister(phydev);
3629
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003630 unregister_netdev(net);
3631
3632 cancel_delayed_work_sync(&dev->wq);
3633
3634 usb_scuttle_anchored_urbs(&dev->deferred);
3635
3636 lan78xx_unbind(dev, intf);
3637
3638 usb_kill_urb(dev->urb_intr);
3639 usb_free_urb(dev->urb_intr);
3640
3641 free_netdev(net);
3642 usb_put_dev(udev);
3643}
3644
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08003645static void lan78xx_tx_timeout(struct net_device *net)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003646{
3647 struct lan78xx_net *dev = netdev_priv(net);
3648
3649 unlink_urbs(dev, &dev->txq);
3650 tasklet_schedule(&dev->bh);
3651}
3652
3653static const struct net_device_ops lan78xx_netdev_ops = {
3654 .ndo_open = lan78xx_open,
3655 .ndo_stop = lan78xx_stop,
3656 .ndo_start_xmit = lan78xx_start_xmit,
3657 .ndo_tx_timeout = lan78xx_tx_timeout,
3658 .ndo_change_mtu = lan78xx_change_mtu,
3659 .ndo_set_mac_address = lan78xx_set_mac_addr,
3660 .ndo_validate_addr = eth_validate_addr,
3661 .ndo_do_ioctl = lan78xx_ioctl,
3662 .ndo_set_rx_mode = lan78xx_set_multicast,
3663 .ndo_set_features = lan78xx_set_features,
3664 .ndo_vlan_rx_add_vid = lan78xx_vlan_rx_add_vid,
3665 .ndo_vlan_rx_kill_vid = lan78xx_vlan_rx_kill_vid,
3666};
3667
Kees Cookd28bb962017-10-16 17:29:32 -07003668static void lan78xx_stat_monitor(struct timer_list *t)
Woojung Huh20ff5562016-03-16 22:10:40 +00003669{
Kees Cookd28bb962017-10-16 17:29:32 -07003670 struct lan78xx_net *dev = from_timer(dev, t, stat_monitor);
Woojung Huh20ff5562016-03-16 22:10:40 +00003671
3672 lan78xx_defer_kevent(dev, EVENT_STAT_UPDATE);
3673}
3674
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003675static int lan78xx_probe(struct usb_interface *intf,
3676 const struct usb_device_id *id)
3677{
3678 struct lan78xx_net *dev;
3679 struct net_device *netdev;
3680 struct usb_device *udev;
3681 int ret;
3682 unsigned maxp;
3683 unsigned period;
3684 u8 *buf = NULL;
3685
3686 udev = interface_to_usbdev(intf);
3687 udev = usb_get_dev(udev);
3688
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003689 netdev = alloc_etherdev(sizeof(struct lan78xx_net));
3690 if (!netdev) {
Nisar Sayedfb52c3b2017-08-01 10:24:17 +00003691 dev_err(&intf->dev, "Error: OOM\n");
3692 ret = -ENOMEM;
3693 goto out1;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003694 }
3695
3696 /* netdev_printk() needs this */
3697 SET_NETDEV_DEV(netdev, &intf->dev);
3698
3699 dev = netdev_priv(netdev);
3700 dev->udev = udev;
3701 dev->intf = intf;
3702 dev->net = netdev;
3703 dev->msg_enable = netif_msg_init(msg_level, NETIF_MSG_DRV
3704 | NETIF_MSG_PROBE | NETIF_MSG_LINK);
3705
3706 skb_queue_head_init(&dev->rxq);
3707 skb_queue_head_init(&dev->txq);
3708 skb_queue_head_init(&dev->done);
3709 skb_queue_head_init(&dev->rxq_pause);
3710 skb_queue_head_init(&dev->txq_pend);
3711 mutex_init(&dev->phy_mutex);
3712
3713 tasklet_init(&dev->bh, lan78xx_bh, (unsigned long)dev);
3714 INIT_DELAYED_WORK(&dev->wq, lan78xx_delayedwork);
3715 init_usb_anchor(&dev->deferred);
3716
3717 netdev->netdev_ops = &lan78xx_netdev_ops;
3718 netdev->watchdog_timeo = TX_TIMEOUT_JIFFIES;
3719 netdev->ethtool_ops = &lan78xx_ethtool_ops;
3720
Woojung Huh20ff5562016-03-16 22:10:40 +00003721 dev->delta = 1;
Kees Cookd28bb962017-10-16 17:29:32 -07003722 timer_setup(&dev->stat_monitor, lan78xx_stat_monitor, 0);
Woojung Huh20ff5562016-03-16 22:10:40 +00003723
3724 mutex_init(&dev->stats.access_lock);
3725
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003726 ret = lan78xx_bind(dev, intf);
3727 if (ret < 0)
3728 goto out2;
3729 strcpy(netdev->name, "eth%d");
3730
3731 if (netdev->mtu > (dev->hard_mtu - netdev->hard_header_len))
3732 netdev->mtu = dev->hard_mtu - netdev->hard_header_len;
3733
Jarod Wilsonf77f0ae2016-10-20 13:55:17 -04003734 /* MTU range: 68 - 9000 */
3735 netdev->max_mtu = MAX_SINGLE_PACKET_SIZE;
3736
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003737 dev->ep_blkin = (intf->cur_altsetting)->endpoint + 0;
3738 dev->ep_blkout = (intf->cur_altsetting)->endpoint + 1;
3739 dev->ep_intr = (intf->cur_altsetting)->endpoint + 2;
3740
3741 dev->pipe_in = usb_rcvbulkpipe(udev, BULK_IN_PIPE);
3742 dev->pipe_out = usb_sndbulkpipe(udev, BULK_OUT_PIPE);
3743
3744 dev->pipe_intr = usb_rcvintpipe(dev->udev,
3745 dev->ep_intr->desc.bEndpointAddress &
3746 USB_ENDPOINT_NUMBER_MASK);
3747 period = dev->ep_intr->desc.bInterval;
3748
3749 maxp = usb_maxpacket(dev->udev, dev->pipe_intr, 0);
3750 buf = kmalloc(maxp, GFP_KERNEL);
3751 if (buf) {
3752 dev->urb_intr = usb_alloc_urb(0, GFP_KERNEL);
3753 if (!dev->urb_intr) {
Pan Bian51920832016-12-03 19:24:48 +08003754 ret = -ENOMEM;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003755 kfree(buf);
3756 goto out3;
3757 } else {
3758 usb_fill_int_urb(dev->urb_intr, dev->udev,
3759 dev->pipe_intr, buf, maxp,
3760 intr_complete, dev, period);
3761 }
3762 }
3763
3764 dev->maxpacket = usb_maxpacket(dev->udev, dev->pipe_out, 1);
3765
3766 /* driver requires remote-wakeup capability during autosuspend. */
3767 intf->needs_remote_wakeup = 1;
3768
3769 ret = register_netdev(netdev);
3770 if (ret != 0) {
3771 netif_err(dev, probe, netdev, "couldn't register the device\n");
Nisar Sayedfb52c3b2017-08-01 10:24:17 +00003772 goto out3;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003773 }
3774
3775 usb_set_intfdata(intf, dev);
3776
3777 ret = device_set_wakeup_enable(&udev->dev, true);
3778
3779 /* Default delay of 2sec has more overhead than advantage.
3780 * Set to 10sec as default.
3781 */
3782 pm_runtime_set_autosuspend_delay(&udev->dev,
3783 DEFAULT_AUTOSUSPEND_DELAY);
3784
Alexander Graf92571a12018-04-04 00:19:35 +02003785 ret = lan78xx_phy_init(dev);
3786 if (ret < 0)
3787 goto out4;
3788
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003789 return 0;
3790
Alexander Graf92571a12018-04-04 00:19:35 +02003791out4:
3792 unregister_netdev(netdev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003793out3:
3794 lan78xx_unbind(dev, intf);
3795out2:
3796 free_netdev(netdev);
3797out1:
3798 usb_put_dev(udev);
3799
3800 return ret;
3801}
3802
3803static u16 lan78xx_wakeframe_crc16(const u8 *buf, int len)
3804{
3805 const u16 crc16poly = 0x8005;
3806 int i;
3807 u16 bit, crc, msb;
3808 u8 data;
3809
3810 crc = 0xFFFF;
3811 for (i = 0; i < len; i++) {
3812 data = *buf++;
3813 for (bit = 0; bit < 8; bit++) {
3814 msb = crc >> 15;
3815 crc <<= 1;
3816
3817 if (msb ^ (u16)(data & 1)) {
3818 crc ^= crc16poly;
3819 crc |= (u16)0x0001U;
3820 }
3821 data >>= 1;
3822 }
3823 }
3824
3825 return crc;
3826}
3827
3828static int lan78xx_set_suspend(struct lan78xx_net *dev, u32 wol)
3829{
3830 u32 buf;
3831 int ret;
3832 int mask_index;
3833 u16 crc;
3834 u32 temp_wucsr;
3835 u32 temp_pmt_ctl;
3836 const u8 ipv4_multicast[3] = { 0x01, 0x00, 0x5E };
3837 const u8 ipv6_multicast[3] = { 0x33, 0x33 };
3838 const u8 arp_type[2] = { 0x08, 0x06 };
3839
3840 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
3841 buf &= ~MAC_TX_TXEN_;
3842 ret = lan78xx_write_reg(dev, MAC_TX, buf);
3843 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3844 buf &= ~MAC_RX_RXEN_;
3845 ret = lan78xx_write_reg(dev, MAC_RX, buf);
3846
3847 ret = lan78xx_write_reg(dev, WUCSR, 0);
3848 ret = lan78xx_write_reg(dev, WUCSR2, 0);
3849 ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
3850
3851 temp_wucsr = 0;
3852
3853 temp_pmt_ctl = 0;
3854 ret = lan78xx_read_reg(dev, PMT_CTL, &temp_pmt_ctl);
3855 temp_pmt_ctl &= ~PMT_CTL_RES_CLR_WKP_EN_;
3856 temp_pmt_ctl |= PMT_CTL_RES_CLR_WKP_STS_;
3857
3858 for (mask_index = 0; mask_index < NUM_OF_WUF_CFG; mask_index++)
3859 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index), 0);
3860
3861 mask_index = 0;
3862 if (wol & WAKE_PHY) {
3863 temp_pmt_ctl |= PMT_CTL_PHY_WAKE_EN_;
3864
3865 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3866 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3867 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3868 }
3869 if (wol & WAKE_MAGIC) {
3870 temp_wucsr |= WUCSR_MPEN_;
3871
3872 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3873 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3874 temp_pmt_ctl |= PMT_CTL_SUS_MODE_3_;
3875 }
3876 if (wol & WAKE_BCAST) {
3877 temp_wucsr |= WUCSR_BCST_EN_;
3878
3879 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3880 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3881 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3882 }
3883 if (wol & WAKE_MCAST) {
3884 temp_wucsr |= WUCSR_WAKE_EN_;
3885
3886 /* set WUF_CFG & WUF_MASK for IPv4 Multicast */
3887 crc = lan78xx_wakeframe_crc16(ipv4_multicast, 3);
3888 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3889 WUF_CFGX_EN_ |
3890 WUF_CFGX_TYPE_MCAST_ |
3891 (0 << WUF_CFGX_OFFSET_SHIFT_) |
3892 (crc & WUF_CFGX_CRC16_MASK_));
3893
3894 ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 7);
3895 ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3896 ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3897 ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3898 mask_index++;
3899
3900 /* for IPv6 Multicast */
3901 crc = lan78xx_wakeframe_crc16(ipv6_multicast, 2);
3902 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3903 WUF_CFGX_EN_ |
3904 WUF_CFGX_TYPE_MCAST_ |
3905 (0 << WUF_CFGX_OFFSET_SHIFT_) |
3906 (crc & WUF_CFGX_CRC16_MASK_));
3907
3908 ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 3);
3909 ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3910 ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3911 ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3912 mask_index++;
3913
3914 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3915 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3916 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3917 }
3918 if (wol & WAKE_UCAST) {
3919 temp_wucsr |= WUCSR_PFDA_EN_;
3920
3921 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3922 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3923 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3924 }
3925 if (wol & WAKE_ARP) {
3926 temp_wucsr |= WUCSR_WAKE_EN_;
3927
3928 /* set WUF_CFG & WUF_MASK
3929 * for packettype (offset 12,13) = ARP (0x0806)
3930 */
3931 crc = lan78xx_wakeframe_crc16(arp_type, 2);
3932 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3933 WUF_CFGX_EN_ |
3934 WUF_CFGX_TYPE_ALL_ |
3935 (0 << WUF_CFGX_OFFSET_SHIFT_) |
3936 (crc & WUF_CFGX_CRC16_MASK_));
3937
3938 ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 0x3000);
3939 ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3940 ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3941 ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3942 mask_index++;
3943
3944 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3945 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3946 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3947 }
3948
3949 ret = lan78xx_write_reg(dev, WUCSR, temp_wucsr);
3950
3951 /* when multiple WOL bits are set */
3952 if (hweight_long((unsigned long)wol) > 1) {
3953 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3954 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3955 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3956 }
3957 ret = lan78xx_write_reg(dev, PMT_CTL, temp_pmt_ctl);
3958
3959 /* clear WUPS */
3960 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
3961 buf |= PMT_CTL_WUPS_MASK_;
3962 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
3963
3964 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3965 buf |= MAC_RX_RXEN_;
3966 ret = lan78xx_write_reg(dev, MAC_RX, buf);
3967
3968 return 0;
3969}
3970
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08003971static int lan78xx_suspend(struct usb_interface *intf, pm_message_t message)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003972{
3973 struct lan78xx_net *dev = usb_get_intfdata(intf);
3974 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
3975 u32 buf;
3976 int ret;
3977 int event;
3978
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003979 event = message.event;
3980
3981 if (!dev->suspend_count++) {
3982 spin_lock_irq(&dev->txq.lock);
3983 /* don't autosuspend while transmitting */
3984 if ((skb_queue_len(&dev->txq) ||
3985 skb_queue_len(&dev->txq_pend)) &&
3986 PMSG_IS_AUTO(message)) {
3987 spin_unlock_irq(&dev->txq.lock);
3988 ret = -EBUSY;
3989 goto out;
3990 } else {
3991 set_bit(EVENT_DEV_ASLEEP, &dev->flags);
3992 spin_unlock_irq(&dev->txq.lock);
3993 }
3994
3995 /* stop TX & RX */
3996 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
3997 buf &= ~MAC_TX_TXEN_;
3998 ret = lan78xx_write_reg(dev, MAC_TX, buf);
3999 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
4000 buf &= ~MAC_RX_RXEN_;
4001 ret = lan78xx_write_reg(dev, MAC_RX, buf);
4002
4003 /* empty out the rx and queues */
4004 netif_device_detach(dev->net);
4005 lan78xx_terminate_urbs(dev);
4006 usb_kill_urb(dev->urb_intr);
4007
4008 /* reattach */
4009 netif_device_attach(dev->net);
4010 }
4011
4012 if (test_bit(EVENT_DEV_ASLEEP, &dev->flags)) {
Woojung Huh20ff5562016-03-16 22:10:40 +00004013 del_timer(&dev->stat_monitor);
4014
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004015 if (PMSG_IS_AUTO(message)) {
4016 /* auto suspend (selective suspend) */
4017 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
4018 buf &= ~MAC_TX_TXEN_;
4019 ret = lan78xx_write_reg(dev, MAC_TX, buf);
4020 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
4021 buf &= ~MAC_RX_RXEN_;
4022 ret = lan78xx_write_reg(dev, MAC_RX, buf);
4023
4024 ret = lan78xx_write_reg(dev, WUCSR, 0);
4025 ret = lan78xx_write_reg(dev, WUCSR2, 0);
4026 ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
4027
4028 /* set goodframe wakeup */
4029 ret = lan78xx_read_reg(dev, WUCSR, &buf);
4030
4031 buf |= WUCSR_RFE_WAKE_EN_;
4032 buf |= WUCSR_STORE_WAKE_;
4033
4034 ret = lan78xx_write_reg(dev, WUCSR, buf);
4035
4036 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
4037
4038 buf &= ~PMT_CTL_RES_CLR_WKP_EN_;
4039 buf |= PMT_CTL_RES_CLR_WKP_STS_;
4040
4041 buf |= PMT_CTL_PHY_WAKE_EN_;
4042 buf |= PMT_CTL_WOL_EN_;
4043 buf &= ~PMT_CTL_SUS_MODE_MASK_;
4044 buf |= PMT_CTL_SUS_MODE_3_;
4045
4046 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
4047
4048 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
4049
4050 buf |= PMT_CTL_WUPS_MASK_;
4051
4052 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
4053
4054 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
4055 buf |= MAC_RX_RXEN_;
4056 ret = lan78xx_write_reg(dev, MAC_RX, buf);
4057 } else {
4058 lan78xx_set_suspend(dev, pdata->wol);
4059 }
4060 }
4061
Woojung.Huh@microchip.com49d28b562015-09-25 21:13:48 +00004062 ret = 0;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004063out:
4064 return ret;
4065}
4066
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08004067static int lan78xx_resume(struct usb_interface *intf)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004068{
4069 struct lan78xx_net *dev = usb_get_intfdata(intf);
4070 struct sk_buff *skb;
4071 struct urb *res;
4072 int ret;
4073 u32 buf;
4074
Woojung Huh20ff5562016-03-16 22:10:40 +00004075 if (!timer_pending(&dev->stat_monitor)) {
4076 dev->delta = 1;
4077 mod_timer(&dev->stat_monitor,
4078 jiffies + STAT_UPDATE_TIMER);
4079 }
4080
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004081 if (!--dev->suspend_count) {
4082 /* resume interrupt URBs */
4083 if (dev->urb_intr && test_bit(EVENT_DEV_OPEN, &dev->flags))
4084 usb_submit_urb(dev->urb_intr, GFP_NOIO);
4085
4086 spin_lock_irq(&dev->txq.lock);
4087 while ((res = usb_get_from_anchor(&dev->deferred))) {
4088 skb = (struct sk_buff *)res->context;
4089 ret = usb_submit_urb(res, GFP_ATOMIC);
4090 if (ret < 0) {
4091 dev_kfree_skb_any(skb);
4092 usb_free_urb(res);
4093 usb_autopm_put_interface_async(dev->intf);
4094 } else {
Florian Westphal860e9532016-05-03 16:33:13 +02004095 netif_trans_update(dev->net);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004096 lan78xx_queue_skb(&dev->txq, skb, tx_start);
4097 }
4098 }
4099
4100 clear_bit(EVENT_DEV_ASLEEP, &dev->flags);
4101 spin_unlock_irq(&dev->txq.lock);
4102
4103 if (test_bit(EVENT_DEV_OPEN, &dev->flags)) {
4104 if (!(skb_queue_len(&dev->txq) >= dev->tx_qlen))
4105 netif_start_queue(dev->net);
4106 tasklet_schedule(&dev->bh);
4107 }
4108 }
4109
4110 ret = lan78xx_write_reg(dev, WUCSR2, 0);
4111 ret = lan78xx_write_reg(dev, WUCSR, 0);
4112 ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
4113
4114 ret = lan78xx_write_reg(dev, WUCSR2, WUCSR2_NS_RCD_ |
4115 WUCSR2_ARP_RCD_ |
4116 WUCSR2_IPV6_TCPSYN_RCD_ |
4117 WUCSR2_IPV4_TCPSYN_RCD_);
4118
4119 ret = lan78xx_write_reg(dev, WUCSR, WUCSR_EEE_TX_WAKE_ |
4120 WUCSR_EEE_RX_WAKE_ |
4121 WUCSR_PFDA_FR_ |
4122 WUCSR_RFE_WAKE_FR_ |
4123 WUCSR_WUFR_ |
4124 WUCSR_MPR_ |
4125 WUCSR_BCST_FR_);
4126
4127 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
4128 buf |= MAC_TX_TXEN_;
4129 ret = lan78xx_write_reg(dev, MAC_TX, buf);
4130
4131 return 0;
4132}
4133
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08004134static int lan78xx_reset_resume(struct usb_interface *intf)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004135{
4136 struct lan78xx_net *dev = usb_get_intfdata(intf);
4137
4138 lan78xx_reset(dev);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00004139
Alexander Graf92571a12018-04-04 00:19:35 +02004140 phy_start(dev->net->phydev);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00004141
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004142 return lan78xx_resume(intf);
4143}
4144
4145static const struct usb_device_id products[] = {
4146 {
4147 /* LAN7800 USB Gigabit Ethernet Device */
4148 USB_DEVICE(LAN78XX_USB_VENDOR_ID, LAN7800_USB_PRODUCT_ID),
4149 },
4150 {
4151 /* LAN7850 USB Gigabit Ethernet Device */
4152 USB_DEVICE(LAN78XX_USB_VENDOR_ID, LAN7850_USB_PRODUCT_ID),
4153 },
Woojung Huh02dc1f32016-12-07 20:26:25 +00004154 {
4155 /* LAN7801 USB Gigabit Ethernet Device */
4156 USB_DEVICE(LAN78XX_USB_VENDOR_ID, LAN7801_USB_PRODUCT_ID),
4157 },
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004158 {},
4159};
4160MODULE_DEVICE_TABLE(usb, products);
4161
4162static struct usb_driver lan78xx_driver = {
4163 .name = DRIVER_NAME,
4164 .id_table = products,
4165 .probe = lan78xx_probe,
4166 .disconnect = lan78xx_disconnect,
4167 .suspend = lan78xx_suspend,
4168 .resume = lan78xx_resume,
4169 .reset_resume = lan78xx_reset_resume,
4170 .supports_autosuspend = 1,
4171 .disable_hub_initiated_lpm = 1,
4172};
4173
4174module_usb_driver(lan78xx_driver);
4175
4176MODULE_AUTHOR(DRIVER_AUTHOR);
4177MODULE_DESCRIPTION(DRIVER_DESC);
4178MODULE_LICENSE("GPL");