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Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001/*
2 * Copyright (C) 2015 Microchip Technology
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version 2
7 * of the License, or (at your option) any later version.
8 *
9 * This program is distributed in the hope that it will be useful,
10 * but WITHOUT ANY WARRANTY; without even the implied warranty of
11 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 * GNU General Public License for more details.
13 *
14 * You should have received a copy of the GNU General Public License
15 * along with this program; if not, see <http://www.gnu.org/licenses/>.
16 */
17#include <linux/version.h>
18#include <linux/module.h>
19#include <linux/netdevice.h>
20#include <linux/etherdevice.h>
21#include <linux/ethtool.h>
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000022#include <linux/usb.h>
23#include <linux/crc32.h>
24#include <linux/signal.h>
25#include <linux/slab.h>
26#include <linux/if_vlan.h>
27#include <linux/uaccess.h>
28#include <linux/list.h>
29#include <linux/ip.h>
30#include <linux/ipv6.h>
31#include <linux/mdio.h>
Andrew Lunnc6e970a2017-03-28 23:45:06 +020032#include <linux/phy.h>
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000033#include <net/ip6_checksum.h>
Woojung Huhcc89c322016-11-01 20:02:00 +000034#include <linux/interrupt.h>
35#include <linux/irqdomain.h>
36#include <linux/irq.h>
37#include <linux/irqchip/chained_irq.h>
Woojung.Huh@microchip.combdfba55e2015-09-16 23:41:07 +000038#include <linux/microchipphy.h>
Raghuram Chary J89b36fb2018-04-28 11:33:14 +053039#include <linux/phy_fixed.h>
Phil Elwell1827b062018-04-19 17:59:39 +010040#include <linux/of_mdio.h>
Phil Elwell760db292018-04-19 17:59:38 +010041#include <linux/of_net.h>
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000042#include "lan78xx.h"
43
44#define DRIVER_AUTHOR "WOOJUNG HUH <woojung.huh@microchip.com>"
45#define DRIVER_DESC "LAN78XX USB 3.0 Gigabit Ethernet Devices"
46#define DRIVER_NAME "lan78xx"
Woojung Huh02dc1f32016-12-07 20:26:25 +000047#define DRIVER_VERSION "1.0.6"
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000048
49#define TX_TIMEOUT_JIFFIES (5 * HZ)
50#define THROTTLE_JIFFIES (HZ / 8)
51#define UNLINK_TIMEOUT_MS 3
52
53#define RX_MAX_QUEUE_MEMORY (60 * 1518)
54
55#define SS_USB_PKT_SIZE (1024)
56#define HS_USB_PKT_SIZE (512)
57#define FS_USB_PKT_SIZE (64)
58
59#define MAX_RX_FIFO_SIZE (12 * 1024)
60#define MAX_TX_FIFO_SIZE (12 * 1024)
61#define DEFAULT_BURST_CAP_SIZE (MAX_TX_FIFO_SIZE)
62#define DEFAULT_BULK_IN_DELAY (0x0800)
63#define MAX_SINGLE_PACKET_SIZE (9000)
64#define DEFAULT_TX_CSUM_ENABLE (true)
65#define DEFAULT_RX_CSUM_ENABLE (true)
66#define DEFAULT_TSO_CSUM_ENABLE (true)
67#define DEFAULT_VLAN_FILTER_ENABLE (true)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000068#define TX_OVERHEAD (8)
69#define RXW_PADDING 2
70
71#define LAN78XX_USB_VENDOR_ID (0x0424)
72#define LAN7800_USB_PRODUCT_ID (0x7800)
73#define LAN7850_USB_PRODUCT_ID (0x7850)
Woojung Huh02dc1f32016-12-07 20:26:25 +000074#define LAN7801_USB_PRODUCT_ID (0x7801)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +000075#define LAN78XX_EEPROM_MAGIC (0x78A5)
76#define LAN78XX_OTP_MAGIC (0x78F3)
77
78#define MII_READ 1
79#define MII_WRITE 0
80
81#define EEPROM_INDICATOR (0xA5)
82#define EEPROM_MAC_OFFSET (0x01)
83#define MAX_EEPROM_SIZE 512
84#define OTP_INDICATOR_1 (0xF3)
85#define OTP_INDICATOR_2 (0xF7)
86
87#define WAKE_ALL (WAKE_PHY | WAKE_UCAST | \
88 WAKE_MCAST | WAKE_BCAST | \
89 WAKE_ARP | WAKE_MAGIC)
90
91/* USB related defines */
92#define BULK_IN_PIPE 1
93#define BULK_OUT_PIPE 2
94
95/* default autosuspend delay (mSec)*/
96#define DEFAULT_AUTOSUSPEND_DELAY (10 * 1000)
97
Woojung Huh20ff5562016-03-16 22:10:40 +000098/* statistic update interval (mSec) */
99#define STAT_UPDATE_TIMER (1 * 1000)
100
Woojung Huhcc89c322016-11-01 20:02:00 +0000101/* defines interrupts from interrupt EP */
102#define MAX_INT_EP (32)
103#define INT_EP_INTEP (31)
104#define INT_EP_OTP_WR_DONE (28)
105#define INT_EP_EEE_TX_LPI_START (26)
106#define INT_EP_EEE_TX_LPI_STOP (25)
107#define INT_EP_EEE_RX_LPI (24)
108#define INT_EP_MAC_RESET_TIMEOUT (23)
109#define INT_EP_RDFO (22)
110#define INT_EP_TXE (21)
111#define INT_EP_USB_STATUS (20)
112#define INT_EP_TX_DIS (19)
113#define INT_EP_RX_DIS (18)
114#define INT_EP_PHY (17)
115#define INT_EP_DP (16)
116#define INT_EP_MAC_ERR (15)
117#define INT_EP_TDFU (14)
118#define INT_EP_TDFO (13)
119#define INT_EP_UTX (12)
120#define INT_EP_GPIO_11 (11)
121#define INT_EP_GPIO_10 (10)
122#define INT_EP_GPIO_9 (9)
123#define INT_EP_GPIO_8 (8)
124#define INT_EP_GPIO_7 (7)
125#define INT_EP_GPIO_6 (6)
126#define INT_EP_GPIO_5 (5)
127#define INT_EP_GPIO_4 (4)
128#define INT_EP_GPIO_3 (3)
129#define INT_EP_GPIO_2 (2)
130#define INT_EP_GPIO_1 (1)
131#define INT_EP_GPIO_0 (0)
132
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000133static const char lan78xx_gstrings[][ETH_GSTRING_LEN] = {
134 "RX FCS Errors",
135 "RX Alignment Errors",
136 "Rx Fragment Errors",
137 "RX Jabber Errors",
138 "RX Undersize Frame Errors",
139 "RX Oversize Frame Errors",
140 "RX Dropped Frames",
141 "RX Unicast Byte Count",
142 "RX Broadcast Byte Count",
143 "RX Multicast Byte Count",
144 "RX Unicast Frames",
145 "RX Broadcast Frames",
146 "RX Multicast Frames",
147 "RX Pause Frames",
148 "RX 64 Byte Frames",
149 "RX 65 - 127 Byte Frames",
150 "RX 128 - 255 Byte Frames",
151 "RX 256 - 511 Bytes Frames",
152 "RX 512 - 1023 Byte Frames",
153 "RX 1024 - 1518 Byte Frames",
154 "RX Greater 1518 Byte Frames",
155 "EEE RX LPI Transitions",
156 "EEE RX LPI Time",
157 "TX FCS Errors",
158 "TX Excess Deferral Errors",
159 "TX Carrier Errors",
160 "TX Bad Byte Count",
161 "TX Single Collisions",
162 "TX Multiple Collisions",
163 "TX Excessive Collision",
164 "TX Late Collisions",
165 "TX Unicast Byte Count",
166 "TX Broadcast Byte Count",
167 "TX Multicast Byte Count",
168 "TX Unicast Frames",
169 "TX Broadcast Frames",
170 "TX Multicast Frames",
171 "TX Pause Frames",
172 "TX 64 Byte Frames",
173 "TX 65 - 127 Byte Frames",
174 "TX 128 - 255 Byte Frames",
175 "TX 256 - 511 Bytes Frames",
176 "TX 512 - 1023 Byte Frames",
177 "TX 1024 - 1518 Byte Frames",
178 "TX Greater 1518 Byte Frames",
179 "EEE TX LPI Transitions",
180 "EEE TX LPI Time",
181};
182
183struct lan78xx_statstage {
184 u32 rx_fcs_errors;
185 u32 rx_alignment_errors;
186 u32 rx_fragment_errors;
187 u32 rx_jabber_errors;
188 u32 rx_undersize_frame_errors;
189 u32 rx_oversize_frame_errors;
190 u32 rx_dropped_frames;
191 u32 rx_unicast_byte_count;
192 u32 rx_broadcast_byte_count;
193 u32 rx_multicast_byte_count;
194 u32 rx_unicast_frames;
195 u32 rx_broadcast_frames;
196 u32 rx_multicast_frames;
197 u32 rx_pause_frames;
198 u32 rx_64_byte_frames;
199 u32 rx_65_127_byte_frames;
200 u32 rx_128_255_byte_frames;
201 u32 rx_256_511_bytes_frames;
202 u32 rx_512_1023_byte_frames;
203 u32 rx_1024_1518_byte_frames;
204 u32 rx_greater_1518_byte_frames;
205 u32 eee_rx_lpi_transitions;
206 u32 eee_rx_lpi_time;
207 u32 tx_fcs_errors;
208 u32 tx_excess_deferral_errors;
209 u32 tx_carrier_errors;
210 u32 tx_bad_byte_count;
211 u32 tx_single_collisions;
212 u32 tx_multiple_collisions;
213 u32 tx_excessive_collision;
214 u32 tx_late_collisions;
215 u32 tx_unicast_byte_count;
216 u32 tx_broadcast_byte_count;
217 u32 tx_multicast_byte_count;
218 u32 tx_unicast_frames;
219 u32 tx_broadcast_frames;
220 u32 tx_multicast_frames;
221 u32 tx_pause_frames;
222 u32 tx_64_byte_frames;
223 u32 tx_65_127_byte_frames;
224 u32 tx_128_255_byte_frames;
225 u32 tx_256_511_bytes_frames;
226 u32 tx_512_1023_byte_frames;
227 u32 tx_1024_1518_byte_frames;
228 u32 tx_greater_1518_byte_frames;
229 u32 eee_tx_lpi_transitions;
230 u32 eee_tx_lpi_time;
231};
232
Woojung Huh20ff5562016-03-16 22:10:40 +0000233struct lan78xx_statstage64 {
234 u64 rx_fcs_errors;
235 u64 rx_alignment_errors;
236 u64 rx_fragment_errors;
237 u64 rx_jabber_errors;
238 u64 rx_undersize_frame_errors;
239 u64 rx_oversize_frame_errors;
240 u64 rx_dropped_frames;
241 u64 rx_unicast_byte_count;
242 u64 rx_broadcast_byte_count;
243 u64 rx_multicast_byte_count;
244 u64 rx_unicast_frames;
245 u64 rx_broadcast_frames;
246 u64 rx_multicast_frames;
247 u64 rx_pause_frames;
248 u64 rx_64_byte_frames;
249 u64 rx_65_127_byte_frames;
250 u64 rx_128_255_byte_frames;
251 u64 rx_256_511_bytes_frames;
252 u64 rx_512_1023_byte_frames;
253 u64 rx_1024_1518_byte_frames;
254 u64 rx_greater_1518_byte_frames;
255 u64 eee_rx_lpi_transitions;
256 u64 eee_rx_lpi_time;
257 u64 tx_fcs_errors;
258 u64 tx_excess_deferral_errors;
259 u64 tx_carrier_errors;
260 u64 tx_bad_byte_count;
261 u64 tx_single_collisions;
262 u64 tx_multiple_collisions;
263 u64 tx_excessive_collision;
264 u64 tx_late_collisions;
265 u64 tx_unicast_byte_count;
266 u64 tx_broadcast_byte_count;
267 u64 tx_multicast_byte_count;
268 u64 tx_unicast_frames;
269 u64 tx_broadcast_frames;
270 u64 tx_multicast_frames;
271 u64 tx_pause_frames;
272 u64 tx_64_byte_frames;
273 u64 tx_65_127_byte_frames;
274 u64 tx_128_255_byte_frames;
275 u64 tx_256_511_bytes_frames;
276 u64 tx_512_1023_byte_frames;
277 u64 tx_1024_1518_byte_frames;
278 u64 tx_greater_1518_byte_frames;
279 u64 eee_tx_lpi_transitions;
280 u64 eee_tx_lpi_time;
281};
282
Raghuram Chary J49621862018-04-20 11:43:50 +0530283static u32 lan78xx_regs[] = {
284 ID_REV,
285 INT_STS,
286 HW_CFG,
287 PMT_CTL,
288 E2P_CMD,
289 E2P_DATA,
290 USB_STATUS,
291 VLAN_TYPE,
292 MAC_CR,
293 MAC_RX,
294 MAC_TX,
295 FLOW,
296 ERR_STS,
297 MII_ACC,
298 MII_DATA,
299 EEE_TX_LPI_REQ_DLY,
300 EEE_TW_TX_SYS,
301 EEE_TX_LPI_REM_DLY,
302 WUCSR
303};
304
305#define PHY_REG_SIZE (32 * sizeof(u32))
306
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000307struct lan78xx_net;
308
309struct lan78xx_priv {
310 struct lan78xx_net *dev;
311 u32 rfe_ctl;
312 u32 mchash_table[DP_SEL_VHF_HASH_LEN]; /* multicat hash table */
313 u32 pfilter_table[NUM_OF_MAF][2]; /* perfect filter table */
314 u32 vlan_table[DP_SEL_VHF_VLAN_LEN];
315 struct mutex dataport_mutex; /* for dataport access */
316 spinlock_t rfe_ctl_lock; /* for rfe register access */
317 struct work_struct set_multicast;
318 struct work_struct set_vlan;
319 u32 wol;
320};
321
322enum skb_state {
323 illegal = 0,
324 tx_start,
325 tx_done,
326 rx_start,
327 rx_done,
328 rx_cleanup,
329 unlink_start
330};
331
332struct skb_data { /* skb->cb is one of these */
333 struct urb *urb;
334 struct lan78xx_net *dev;
335 enum skb_state state;
336 size_t length;
Woojung Huh74d79a22016-04-25 22:22:32 +0000337 int num_of_packet;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000338};
339
340struct usb_context {
341 struct usb_ctrlrequest req;
342 struct lan78xx_net *dev;
343};
344
345#define EVENT_TX_HALT 0
346#define EVENT_RX_HALT 1
347#define EVENT_RX_MEMORY 2
348#define EVENT_STS_SPLIT 3
349#define EVENT_LINK_RESET 4
350#define EVENT_RX_PAUSED 5
351#define EVENT_DEV_WAKING 6
352#define EVENT_DEV_ASLEEP 7
353#define EVENT_DEV_OPEN 8
Woojung Huh20ff5562016-03-16 22:10:40 +0000354#define EVENT_STAT_UPDATE 9
355
356struct statstage {
357 struct mutex access_lock; /* for stats access */
358 struct lan78xx_statstage saved;
359 struct lan78xx_statstage rollover_count;
360 struct lan78xx_statstage rollover_max;
361 struct lan78xx_statstage64 curr_stat;
362};
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000363
Woojung Huhcc89c322016-11-01 20:02:00 +0000364struct irq_domain_data {
365 struct irq_domain *irqdomain;
366 unsigned int phyirq;
367 struct irq_chip *irqchip;
368 irq_flow_handler_t irq_handler;
369 u32 irqenable;
370 struct mutex irq_lock; /* for irq bus access */
371};
372
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000373struct lan78xx_net {
374 struct net_device *net;
375 struct usb_device *udev;
376 struct usb_interface *intf;
377 void *driver_priv;
378
379 int rx_qlen;
380 int tx_qlen;
381 struct sk_buff_head rxq;
382 struct sk_buff_head txq;
383 struct sk_buff_head done;
384 struct sk_buff_head rxq_pause;
385 struct sk_buff_head txq_pend;
386
387 struct tasklet_struct bh;
388 struct delayed_work wq;
389
390 struct usb_host_endpoint *ep_blkin;
391 struct usb_host_endpoint *ep_blkout;
392 struct usb_host_endpoint *ep_intr;
393
394 int msg_enable;
395
396 struct urb *urb_intr;
397 struct usb_anchor deferred;
398
399 struct mutex phy_mutex; /* for phy access */
400 unsigned pipe_in, pipe_out, pipe_intr;
401
402 u32 hard_mtu; /* count any extra framing */
403 size_t rx_urb_size; /* size for rx urbs */
404
405 unsigned long flags;
406
407 wait_queue_head_t *wait;
408 unsigned char suspend_count;
409
410 unsigned maxpacket;
411 struct timer_list delay;
Woojung Huh20ff5562016-03-16 22:10:40 +0000412 struct timer_list stat_monitor;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000413
414 unsigned long data[5];
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000415
416 int link_on;
417 u8 mdix_ctrl;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +0000418
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000419 u32 chipid;
420 u32 chiprev;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +0000421 struct mii_bus *mdiobus;
Woojung Huh02dc1f32016-12-07 20:26:25 +0000422 phy_interface_t interface;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +0000423
424 int fc_autoneg;
425 u8 fc_request_control;
Woojung Huh20ff5562016-03-16 22:10:40 +0000426
427 int delta;
428 struct statstage stats;
Woojung Huhcc89c322016-11-01 20:02:00 +0000429
430 struct irq_domain_data domain_data;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000431};
432
Woojung Huh02dc1f32016-12-07 20:26:25 +0000433/* define external phy id */
434#define PHY_LAN8835 (0x0007C130)
435#define PHY_KSZ9031RNX (0x00221620)
436
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000437/* use ethtool to change the level for any given device */
438static int msg_level = -1;
439module_param(msg_level, int, 0);
440MODULE_PARM_DESC(msg_level, "Override default message level");
441
442static int lan78xx_read_reg(struct lan78xx_net *dev, u32 index, u32 *data)
443{
444 u32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);
445 int ret;
446
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000447 if (!buf)
448 return -ENOMEM;
449
450 ret = usb_control_msg(dev->udev, usb_rcvctrlpipe(dev->udev, 0),
451 USB_VENDOR_REQUEST_READ_REGISTER,
452 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
453 0, index, buf, 4, USB_CTRL_GET_TIMEOUT);
454 if (likely(ret >= 0)) {
455 le32_to_cpus(buf);
456 *data = *buf;
457 } else {
458 netdev_warn(dev->net,
459 "Failed to read register index 0x%08x. ret = %d",
460 index, ret);
461 }
462
463 kfree(buf);
464
465 return ret;
466}
467
468static int lan78xx_write_reg(struct lan78xx_net *dev, u32 index, u32 data)
469{
470 u32 *buf = kmalloc(sizeof(u32), GFP_KERNEL);
471 int ret;
472
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000473 if (!buf)
474 return -ENOMEM;
475
476 *buf = data;
477 cpu_to_le32s(buf);
478
479 ret = usb_control_msg(dev->udev, usb_sndctrlpipe(dev->udev, 0),
480 USB_VENDOR_REQUEST_WRITE_REGISTER,
481 USB_DIR_OUT | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
482 0, index, buf, 4, USB_CTRL_SET_TIMEOUT);
483 if (unlikely(ret < 0)) {
484 netdev_warn(dev->net,
485 "Failed to write register index 0x%08x. ret = %d",
486 index, ret);
487 }
488
489 kfree(buf);
490
491 return ret;
492}
493
494static int lan78xx_read_stats(struct lan78xx_net *dev,
495 struct lan78xx_statstage *data)
496{
497 int ret = 0;
498 int i;
499 struct lan78xx_statstage *stats;
500 u32 *src;
501 u32 *dst;
502
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000503 stats = kmalloc(sizeof(*stats), GFP_KERNEL);
504 if (!stats)
505 return -ENOMEM;
506
507 ret = usb_control_msg(dev->udev,
508 usb_rcvctrlpipe(dev->udev, 0),
509 USB_VENDOR_REQUEST_GET_STATS,
510 USB_DIR_IN | USB_TYPE_VENDOR | USB_RECIP_DEVICE,
511 0,
512 0,
513 (void *)stats,
514 sizeof(*stats),
515 USB_CTRL_SET_TIMEOUT);
516 if (likely(ret >= 0)) {
517 src = (u32 *)stats;
518 dst = (u32 *)data;
519 for (i = 0; i < sizeof(*stats)/sizeof(u32); i++) {
520 le32_to_cpus(&src[i]);
521 dst[i] = src[i];
522 }
523 } else {
524 netdev_warn(dev->net,
525 "Failed to read stat ret = 0x%x", ret);
526 }
527
528 kfree(stats);
529
530 return ret;
531}
532
Woojung Huh20ff5562016-03-16 22:10:40 +0000533#define check_counter_rollover(struct1, dev_stats, member) { \
534 if (struct1->member < dev_stats.saved.member) \
535 dev_stats.rollover_count.member++; \
536 }
537
538static void lan78xx_check_stat_rollover(struct lan78xx_net *dev,
539 struct lan78xx_statstage *stats)
540{
541 check_counter_rollover(stats, dev->stats, rx_fcs_errors);
542 check_counter_rollover(stats, dev->stats, rx_alignment_errors);
543 check_counter_rollover(stats, dev->stats, rx_fragment_errors);
544 check_counter_rollover(stats, dev->stats, rx_jabber_errors);
545 check_counter_rollover(stats, dev->stats, rx_undersize_frame_errors);
546 check_counter_rollover(stats, dev->stats, rx_oversize_frame_errors);
547 check_counter_rollover(stats, dev->stats, rx_dropped_frames);
548 check_counter_rollover(stats, dev->stats, rx_unicast_byte_count);
549 check_counter_rollover(stats, dev->stats, rx_broadcast_byte_count);
550 check_counter_rollover(stats, dev->stats, rx_multicast_byte_count);
551 check_counter_rollover(stats, dev->stats, rx_unicast_frames);
552 check_counter_rollover(stats, dev->stats, rx_broadcast_frames);
553 check_counter_rollover(stats, dev->stats, rx_multicast_frames);
554 check_counter_rollover(stats, dev->stats, rx_pause_frames);
555 check_counter_rollover(stats, dev->stats, rx_64_byte_frames);
556 check_counter_rollover(stats, dev->stats, rx_65_127_byte_frames);
557 check_counter_rollover(stats, dev->stats, rx_128_255_byte_frames);
558 check_counter_rollover(stats, dev->stats, rx_256_511_bytes_frames);
559 check_counter_rollover(stats, dev->stats, rx_512_1023_byte_frames);
560 check_counter_rollover(stats, dev->stats, rx_1024_1518_byte_frames);
561 check_counter_rollover(stats, dev->stats, rx_greater_1518_byte_frames);
562 check_counter_rollover(stats, dev->stats, eee_rx_lpi_transitions);
563 check_counter_rollover(stats, dev->stats, eee_rx_lpi_time);
564 check_counter_rollover(stats, dev->stats, tx_fcs_errors);
565 check_counter_rollover(stats, dev->stats, tx_excess_deferral_errors);
566 check_counter_rollover(stats, dev->stats, tx_carrier_errors);
567 check_counter_rollover(stats, dev->stats, tx_bad_byte_count);
568 check_counter_rollover(stats, dev->stats, tx_single_collisions);
569 check_counter_rollover(stats, dev->stats, tx_multiple_collisions);
570 check_counter_rollover(stats, dev->stats, tx_excessive_collision);
571 check_counter_rollover(stats, dev->stats, tx_late_collisions);
572 check_counter_rollover(stats, dev->stats, tx_unicast_byte_count);
573 check_counter_rollover(stats, dev->stats, tx_broadcast_byte_count);
574 check_counter_rollover(stats, dev->stats, tx_multicast_byte_count);
575 check_counter_rollover(stats, dev->stats, tx_unicast_frames);
576 check_counter_rollover(stats, dev->stats, tx_broadcast_frames);
577 check_counter_rollover(stats, dev->stats, tx_multicast_frames);
578 check_counter_rollover(stats, dev->stats, tx_pause_frames);
579 check_counter_rollover(stats, dev->stats, tx_64_byte_frames);
580 check_counter_rollover(stats, dev->stats, tx_65_127_byte_frames);
581 check_counter_rollover(stats, dev->stats, tx_128_255_byte_frames);
582 check_counter_rollover(stats, dev->stats, tx_256_511_bytes_frames);
583 check_counter_rollover(stats, dev->stats, tx_512_1023_byte_frames);
584 check_counter_rollover(stats, dev->stats, tx_1024_1518_byte_frames);
585 check_counter_rollover(stats, dev->stats, tx_greater_1518_byte_frames);
586 check_counter_rollover(stats, dev->stats, eee_tx_lpi_transitions);
587 check_counter_rollover(stats, dev->stats, eee_tx_lpi_time);
588
589 memcpy(&dev->stats.saved, stats, sizeof(struct lan78xx_statstage));
590}
591
592static void lan78xx_update_stats(struct lan78xx_net *dev)
593{
594 u32 *p, *count, *max;
595 u64 *data;
596 int i;
597 struct lan78xx_statstage lan78xx_stats;
598
599 if (usb_autopm_get_interface(dev->intf) < 0)
600 return;
601
602 p = (u32 *)&lan78xx_stats;
603 count = (u32 *)&dev->stats.rollover_count;
604 max = (u32 *)&dev->stats.rollover_max;
605 data = (u64 *)&dev->stats.curr_stat;
606
607 mutex_lock(&dev->stats.access_lock);
608
609 if (lan78xx_read_stats(dev, &lan78xx_stats) > 0)
610 lan78xx_check_stat_rollover(dev, &lan78xx_stats);
611
612 for (i = 0; i < (sizeof(lan78xx_stats) / (sizeof(u32))); i++)
613 data[i] = (u64)p[i] + ((u64)count[i] * ((u64)max[i] + 1));
614
615 mutex_unlock(&dev->stats.access_lock);
616
617 usb_autopm_put_interface(dev->intf);
618}
619
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000620/* Loop until the read is completed with timeout called with phy_mutex held */
621static int lan78xx_phy_wait_not_busy(struct lan78xx_net *dev)
622{
623 unsigned long start_time = jiffies;
624 u32 val;
625 int ret;
626
627 do {
628 ret = lan78xx_read_reg(dev, MII_ACC, &val);
629 if (unlikely(ret < 0))
630 return -EIO;
631
632 if (!(val & MII_ACC_MII_BUSY_))
633 return 0;
634 } while (!time_after(jiffies, start_time + HZ));
635
636 return -EIO;
637}
638
639static inline u32 mii_access(int id, int index, int read)
640{
641 u32 ret;
642
643 ret = ((u32)id << MII_ACC_PHY_ADDR_SHIFT_) & MII_ACC_PHY_ADDR_MASK_;
644 ret |= ((u32)index << MII_ACC_MIIRINDA_SHIFT_) & MII_ACC_MIIRINDA_MASK_;
645 if (read)
646 ret |= MII_ACC_MII_READ_;
647 else
648 ret |= MII_ACC_MII_WRITE_;
649 ret |= MII_ACC_MII_BUSY_;
650
651 return ret;
652}
653
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000654static int lan78xx_wait_eeprom(struct lan78xx_net *dev)
655{
656 unsigned long start_time = jiffies;
657 u32 val;
658 int ret;
659
660 do {
661 ret = lan78xx_read_reg(dev, E2P_CMD, &val);
662 if (unlikely(ret < 0))
663 return -EIO;
664
665 if (!(val & E2P_CMD_EPC_BUSY_) ||
666 (val & E2P_CMD_EPC_TIMEOUT_))
667 break;
668 usleep_range(40, 100);
669 } while (!time_after(jiffies, start_time + HZ));
670
671 if (val & (E2P_CMD_EPC_TIMEOUT_ | E2P_CMD_EPC_BUSY_)) {
672 netdev_warn(dev->net, "EEPROM read operation timeout");
673 return -EIO;
674 }
675
676 return 0;
677}
678
679static int lan78xx_eeprom_confirm_not_busy(struct lan78xx_net *dev)
680{
681 unsigned long start_time = jiffies;
682 u32 val;
683 int ret;
684
685 do {
686 ret = lan78xx_read_reg(dev, E2P_CMD, &val);
687 if (unlikely(ret < 0))
688 return -EIO;
689
690 if (!(val & E2P_CMD_EPC_BUSY_))
691 return 0;
692
693 usleep_range(40, 100);
694 } while (!time_after(jiffies, start_time + HZ));
695
696 netdev_warn(dev->net, "EEPROM is busy");
697 return -EIO;
698}
699
700static int lan78xx_read_raw_eeprom(struct lan78xx_net *dev, u32 offset,
701 u32 length, u8 *data)
702{
703 u32 val;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000704 u32 saved;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000705 int i, ret;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000706 int retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000707
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000708 /* depends on chip, some EEPROM pins are muxed with LED function.
709 * disable & restore LED function to access EEPROM.
710 */
711 ret = lan78xx_read_reg(dev, HW_CFG, &val);
712 saved = val;
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000713 if (dev->chipid == ID_REV_CHIP_ID_7800_) {
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000714 val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
715 ret = lan78xx_write_reg(dev, HW_CFG, val);
716 }
717
718 retval = lan78xx_eeprom_confirm_not_busy(dev);
719 if (retval)
720 return retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000721
722 for (i = 0; i < length; i++) {
723 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_READ_;
724 val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
725 ret = lan78xx_write_reg(dev, E2P_CMD, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000726 if (unlikely(ret < 0)) {
727 retval = -EIO;
728 goto exit;
729 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000730
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000731 retval = lan78xx_wait_eeprom(dev);
732 if (retval < 0)
733 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000734
735 ret = lan78xx_read_reg(dev, E2P_DATA, &val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000736 if (unlikely(ret < 0)) {
737 retval = -EIO;
738 goto exit;
739 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000740
741 data[i] = val & 0xFF;
742 offset++;
743 }
744
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000745 retval = 0;
746exit:
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000747 if (dev->chipid == ID_REV_CHIP_ID_7800_)
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000748 ret = lan78xx_write_reg(dev, HW_CFG, saved);
749
750 return retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000751}
752
753static int lan78xx_read_eeprom(struct lan78xx_net *dev, u32 offset,
754 u32 length, u8 *data)
755{
756 u8 sig;
757 int ret;
758
759 ret = lan78xx_read_raw_eeprom(dev, 0, 1, &sig);
760 if ((ret == 0) && (sig == EEPROM_INDICATOR))
761 ret = lan78xx_read_raw_eeprom(dev, offset, length, data);
762 else
763 ret = -EINVAL;
764
765 return ret;
766}
767
768static int lan78xx_write_raw_eeprom(struct lan78xx_net *dev, u32 offset,
769 u32 length, u8 *data)
770{
771 u32 val;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000772 u32 saved;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000773 int i, ret;
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000774 int retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000775
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000776 /* depends on chip, some EEPROM pins are muxed with LED function.
777 * disable & restore LED function to access EEPROM.
778 */
779 ret = lan78xx_read_reg(dev, HW_CFG, &val);
780 saved = val;
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000781 if (dev->chipid == ID_REV_CHIP_ID_7800_) {
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000782 val &= ~(HW_CFG_LED1_EN_ | HW_CFG_LED0_EN_);
783 ret = lan78xx_write_reg(dev, HW_CFG, val);
784 }
785
786 retval = lan78xx_eeprom_confirm_not_busy(dev);
787 if (retval)
788 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000789
790 /* Issue write/erase enable command */
791 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_EWEN_;
792 ret = lan78xx_write_reg(dev, E2P_CMD, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000793 if (unlikely(ret < 0)) {
794 retval = -EIO;
795 goto exit;
796 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000797
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000798 retval = lan78xx_wait_eeprom(dev);
799 if (retval < 0)
800 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000801
802 for (i = 0; i < length; i++) {
803 /* Fill data register */
804 val = data[i];
805 ret = lan78xx_write_reg(dev, E2P_DATA, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000806 if (ret < 0) {
807 retval = -EIO;
808 goto exit;
809 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000810
811 /* Send "write" command */
812 val = E2P_CMD_EPC_BUSY_ | E2P_CMD_EPC_CMD_WRITE_;
813 val |= (offset & E2P_CMD_EPC_ADDR_MASK_);
814 ret = lan78xx_write_reg(dev, E2P_CMD, val);
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000815 if (ret < 0) {
816 retval = -EIO;
817 goto exit;
818 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000819
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000820 retval = lan78xx_wait_eeprom(dev);
821 if (retval < 0)
822 goto exit;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000823
824 offset++;
825 }
826
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000827 retval = 0;
828exit:
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +0000829 if (dev->chipid == ID_REV_CHIP_ID_7800_)
Woojung.Huh@microchip.coma0db7d12016-01-27 22:57:53 +0000830 ret = lan78xx_write_reg(dev, HW_CFG, saved);
831
832 return retval;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000833}
834
835static int lan78xx_read_raw_otp(struct lan78xx_net *dev, u32 offset,
836 u32 length, u8 *data)
837{
838 int i;
839 int ret;
840 u32 buf;
841 unsigned long timeout;
842
843 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
844
845 if (buf & OTP_PWR_DN_PWRDN_N_) {
846 /* clear it and wait to be cleared */
847 ret = lan78xx_write_reg(dev, OTP_PWR_DN, 0);
848
849 timeout = jiffies + HZ;
850 do {
851 usleep_range(1, 10);
852 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
853 if (time_after(jiffies, timeout)) {
854 netdev_warn(dev->net,
855 "timeout on OTP_PWR_DN");
856 return -EIO;
857 }
858 } while (buf & OTP_PWR_DN_PWRDN_N_);
859 }
860
861 for (i = 0; i < length; i++) {
862 ret = lan78xx_write_reg(dev, OTP_ADDR1,
863 ((offset + i) >> 8) & OTP_ADDR1_15_11);
864 ret = lan78xx_write_reg(dev, OTP_ADDR2,
865 ((offset + i) & OTP_ADDR2_10_3));
866
867 ret = lan78xx_write_reg(dev, OTP_FUNC_CMD, OTP_FUNC_CMD_READ_);
868 ret = lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
869
870 timeout = jiffies + HZ;
871 do {
872 udelay(1);
873 ret = lan78xx_read_reg(dev, OTP_STATUS, &buf);
874 if (time_after(jiffies, timeout)) {
875 netdev_warn(dev->net,
876 "timeout on OTP_STATUS");
877 return -EIO;
878 }
879 } while (buf & OTP_STATUS_BUSY_);
880
881 ret = lan78xx_read_reg(dev, OTP_RD_DATA, &buf);
882
883 data[i] = (u8)(buf & 0xFF);
884 }
885
886 return 0;
887}
888
Woojung.Huh@microchip.com9fb60662016-01-05 17:29:59 +0000889static int lan78xx_write_raw_otp(struct lan78xx_net *dev, u32 offset,
890 u32 length, u8 *data)
891{
892 int i;
893 int ret;
894 u32 buf;
895 unsigned long timeout;
896
897 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
898
899 if (buf & OTP_PWR_DN_PWRDN_N_) {
900 /* clear it and wait to be cleared */
901 ret = lan78xx_write_reg(dev, OTP_PWR_DN, 0);
902
903 timeout = jiffies + HZ;
904 do {
905 udelay(1);
906 ret = lan78xx_read_reg(dev, OTP_PWR_DN, &buf);
907 if (time_after(jiffies, timeout)) {
908 netdev_warn(dev->net,
909 "timeout on OTP_PWR_DN completion");
910 return -EIO;
911 }
912 } while (buf & OTP_PWR_DN_PWRDN_N_);
913 }
914
915 /* set to BYTE program mode */
916 ret = lan78xx_write_reg(dev, OTP_PRGM_MODE, OTP_PRGM_MODE_BYTE_);
917
918 for (i = 0; i < length; i++) {
919 ret = lan78xx_write_reg(dev, OTP_ADDR1,
920 ((offset + i) >> 8) & OTP_ADDR1_15_11);
921 ret = lan78xx_write_reg(dev, OTP_ADDR2,
922 ((offset + i) & OTP_ADDR2_10_3));
923 ret = lan78xx_write_reg(dev, OTP_PRGM_DATA, data[i]);
924 ret = lan78xx_write_reg(dev, OTP_TST_CMD, OTP_TST_CMD_PRGVRFY_);
925 ret = lan78xx_write_reg(dev, OTP_CMD_GO, OTP_CMD_GO_GO_);
926
927 timeout = jiffies + HZ;
928 do {
929 udelay(1);
930 ret = lan78xx_read_reg(dev, OTP_STATUS, &buf);
931 if (time_after(jiffies, timeout)) {
932 netdev_warn(dev->net,
933 "Timeout on OTP_STATUS completion");
934 return -EIO;
935 }
936 } while (buf & OTP_STATUS_BUSY_);
937 }
938
939 return 0;
940}
941
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000942static int lan78xx_read_otp(struct lan78xx_net *dev, u32 offset,
943 u32 length, u8 *data)
944{
945 u8 sig;
946 int ret;
947
948 ret = lan78xx_read_raw_otp(dev, 0, 1, &sig);
949
950 if (ret == 0) {
951 if (sig == OTP_INDICATOR_1)
952 offset = offset;
953 else if (sig == OTP_INDICATOR_2)
954 offset += 0x100;
955 else
956 ret = -EINVAL;
Phil Elwell4bfc3382018-04-11 10:59:17 +0100957 if (!ret)
958 ret = lan78xx_read_raw_otp(dev, offset, length, data);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +0000959 }
960
961 return ret;
962}
963
964static int lan78xx_dataport_wait_not_busy(struct lan78xx_net *dev)
965{
966 int i, ret;
967
968 for (i = 0; i < 100; i++) {
969 u32 dp_sel;
970
971 ret = lan78xx_read_reg(dev, DP_SEL, &dp_sel);
972 if (unlikely(ret < 0))
973 return -EIO;
974
975 if (dp_sel & DP_SEL_DPRDY_)
976 return 0;
977
978 usleep_range(40, 100);
979 }
980
981 netdev_warn(dev->net, "lan78xx_dataport_wait_not_busy timed out");
982
983 return -EIO;
984}
985
986static int lan78xx_dataport_write(struct lan78xx_net *dev, u32 ram_select,
987 u32 addr, u32 length, u32 *buf)
988{
989 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
990 u32 dp_sel;
991 int i, ret;
992
993 if (usb_autopm_get_interface(dev->intf) < 0)
994 return 0;
995
996 mutex_lock(&pdata->dataport_mutex);
997
998 ret = lan78xx_dataport_wait_not_busy(dev);
999 if (ret < 0)
1000 goto done;
1001
1002 ret = lan78xx_read_reg(dev, DP_SEL, &dp_sel);
1003
1004 dp_sel &= ~DP_SEL_RSEL_MASK_;
1005 dp_sel |= ram_select;
1006 ret = lan78xx_write_reg(dev, DP_SEL, dp_sel);
1007
1008 for (i = 0; i < length; i++) {
1009 ret = lan78xx_write_reg(dev, DP_ADDR, addr + i);
1010
1011 ret = lan78xx_write_reg(dev, DP_DATA, buf[i]);
1012
1013 ret = lan78xx_write_reg(dev, DP_CMD, DP_CMD_WRITE_);
1014
1015 ret = lan78xx_dataport_wait_not_busy(dev);
1016 if (ret < 0)
1017 goto done;
1018 }
1019
1020done:
1021 mutex_unlock(&pdata->dataport_mutex);
1022 usb_autopm_put_interface(dev->intf);
1023
1024 return ret;
1025}
1026
1027static void lan78xx_set_addr_filter(struct lan78xx_priv *pdata,
1028 int index, u8 addr[ETH_ALEN])
1029{
1030 u32 temp;
1031
1032 if ((pdata) && (index > 0) && (index < NUM_OF_MAF)) {
1033 temp = addr[3];
1034 temp = addr[2] | (temp << 8);
1035 temp = addr[1] | (temp << 8);
1036 temp = addr[0] | (temp << 8);
1037 pdata->pfilter_table[index][1] = temp;
1038 temp = addr[5];
1039 temp = addr[4] | (temp << 8);
1040 temp |= MAF_HI_VALID_ | MAF_HI_TYPE_DST_;
1041 pdata->pfilter_table[index][0] = temp;
1042 }
1043}
1044
1045/* returns hash bit number for given MAC address */
1046static inline u32 lan78xx_hash(char addr[ETH_ALEN])
1047{
1048 return (ether_crc(ETH_ALEN, addr) >> 23) & 0x1ff;
1049}
1050
1051static void lan78xx_deferred_multicast_write(struct work_struct *param)
1052{
1053 struct lan78xx_priv *pdata =
1054 container_of(param, struct lan78xx_priv, set_multicast);
1055 struct lan78xx_net *dev = pdata->dev;
1056 int i;
1057 int ret;
1058
1059 netif_dbg(dev, drv, dev->net, "deferred multicast write 0x%08x\n",
1060 pdata->rfe_ctl);
1061
1062 lan78xx_dataport_write(dev, DP_SEL_RSEL_VLAN_DA_, DP_SEL_VHF_VLAN_LEN,
1063 DP_SEL_VHF_HASH_LEN, pdata->mchash_table);
1064
1065 for (i = 1; i < NUM_OF_MAF; i++) {
1066 ret = lan78xx_write_reg(dev, MAF_HI(i), 0);
1067 ret = lan78xx_write_reg(dev, MAF_LO(i),
1068 pdata->pfilter_table[i][1]);
1069 ret = lan78xx_write_reg(dev, MAF_HI(i),
1070 pdata->pfilter_table[i][0]);
1071 }
1072
1073 ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
1074}
1075
1076static void lan78xx_set_multicast(struct net_device *netdev)
1077{
1078 struct lan78xx_net *dev = netdev_priv(netdev);
1079 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
1080 unsigned long flags;
1081 int i;
1082
1083 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
1084
1085 pdata->rfe_ctl &= ~(RFE_CTL_UCAST_EN_ | RFE_CTL_MCAST_EN_ |
1086 RFE_CTL_DA_PERFECT_ | RFE_CTL_MCAST_HASH_);
1087
1088 for (i = 0; i < DP_SEL_VHF_HASH_LEN; i++)
1089 pdata->mchash_table[i] = 0;
1090 /* pfilter_table[0] has own HW address */
1091 for (i = 1; i < NUM_OF_MAF; i++) {
1092 pdata->pfilter_table[i][0] =
1093 pdata->pfilter_table[i][1] = 0;
1094 }
1095
1096 pdata->rfe_ctl |= RFE_CTL_BCAST_EN_;
1097
1098 if (dev->net->flags & IFF_PROMISC) {
1099 netif_dbg(dev, drv, dev->net, "promiscuous mode enabled");
1100 pdata->rfe_ctl |= RFE_CTL_MCAST_EN_ | RFE_CTL_UCAST_EN_;
1101 } else {
1102 if (dev->net->flags & IFF_ALLMULTI) {
1103 netif_dbg(dev, drv, dev->net,
1104 "receive all multicast enabled");
1105 pdata->rfe_ctl |= RFE_CTL_MCAST_EN_;
1106 }
1107 }
1108
1109 if (netdev_mc_count(dev->net)) {
1110 struct netdev_hw_addr *ha;
1111 int i;
1112
1113 netif_dbg(dev, drv, dev->net, "receive multicast hash filter");
1114
1115 pdata->rfe_ctl |= RFE_CTL_DA_PERFECT_;
1116
1117 i = 1;
1118 netdev_for_each_mc_addr(ha, netdev) {
1119 /* set first 32 into Perfect Filter */
1120 if (i < 33) {
1121 lan78xx_set_addr_filter(pdata, i, ha->addr);
1122 } else {
1123 u32 bitnum = lan78xx_hash(ha->addr);
1124
1125 pdata->mchash_table[bitnum / 32] |=
1126 (1 << (bitnum % 32));
1127 pdata->rfe_ctl |= RFE_CTL_MCAST_HASH_;
1128 }
1129 i++;
1130 }
1131 }
1132
1133 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
1134
1135 /* defer register writes to a sleepable context */
1136 schedule_work(&pdata->set_multicast);
1137}
1138
1139static int lan78xx_update_flowcontrol(struct lan78xx_net *dev, u8 duplex,
1140 u16 lcladv, u16 rmtadv)
1141{
1142 u32 flow = 0, fct_flow = 0;
1143 int ret;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001144 u8 cap;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001145
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001146 if (dev->fc_autoneg)
1147 cap = mii_resolve_flowctrl_fdx(lcladv, rmtadv);
1148 else
1149 cap = dev->fc_request_control;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001150
1151 if (cap & FLOW_CTRL_TX)
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001152 flow |= (FLOW_CR_TX_FCEN_ | 0xFFFF);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001153
1154 if (cap & FLOW_CTRL_RX)
1155 flow |= FLOW_CR_RX_FCEN_;
1156
1157 if (dev->udev->speed == USB_SPEED_SUPER)
1158 fct_flow = 0x817;
1159 else if (dev->udev->speed == USB_SPEED_HIGH)
1160 fct_flow = 0x211;
1161
1162 netif_dbg(dev, link, dev->net, "rx pause %s, tx pause %s",
1163 (cap & FLOW_CTRL_RX ? "enabled" : "disabled"),
1164 (cap & FLOW_CTRL_TX ? "enabled" : "disabled"));
1165
1166 ret = lan78xx_write_reg(dev, FCT_FLOW, fct_flow);
1167
1168 /* threshold value should be set before enabling flow */
1169 ret = lan78xx_write_reg(dev, FLOW, flow);
1170
1171 return 0;
1172}
1173
1174static int lan78xx_link_reset(struct lan78xx_net *dev)
1175{
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001176 struct phy_device *phydev = dev->net->phydev;
Philippe Reynes6e765102016-10-09 12:07:04 +02001177 struct ethtool_link_ksettings ecmd;
Geert Uytterhoeven99c79ec2015-09-04 12:47:28 +02001178 int ladv, radv, ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001179 u32 buf;
1180
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001181 /* clear LAN78xx interrupt status */
1182 ret = lan78xx_write_reg(dev, INT_STS, INT_STS_PHY_INT_);
1183 if (unlikely(ret < 0))
1184 return -EIO;
1185
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001186 phy_read_status(phydev);
1187
1188 if (!phydev->link && dev->link_on) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001189 dev->link_on = false;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001190
1191 /* reset MAC */
1192 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1193 if (unlikely(ret < 0))
1194 return -EIO;
1195 buf |= MAC_CR_RST_;
1196 ret = lan78xx_write_reg(dev, MAC_CR, buf);
1197 if (unlikely(ret < 0))
1198 return -EIO;
Woojung.Huh@microchip.come4953912016-01-27 22:57:52 +00001199
Woojung Huh20ff5562016-03-16 22:10:40 +00001200 del_timer(&dev->stat_monitor);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001201 } else if (phydev->link && !dev->link_on) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001202 dev->link_on = true;
1203
Philippe Reynes6e765102016-10-09 12:07:04 +02001204 phy_ethtool_ksettings_get(phydev, &ecmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001205
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001206 if (dev->udev->speed == USB_SPEED_SUPER) {
Philippe Reynes6e765102016-10-09 12:07:04 +02001207 if (ecmd.base.speed == 1000) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001208 /* disable U2 */
1209 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
1210 buf &= ~USB_CFG1_DEV_U2_INIT_EN_;
1211 ret = lan78xx_write_reg(dev, USB_CFG1, buf);
1212 /* enable U1 */
1213 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
1214 buf |= USB_CFG1_DEV_U1_INIT_EN_;
1215 ret = lan78xx_write_reg(dev, USB_CFG1, buf);
1216 } else {
1217 /* enable U1 & U2 */
1218 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
1219 buf |= USB_CFG1_DEV_U2_INIT_EN_;
1220 buf |= USB_CFG1_DEV_U1_INIT_EN_;
1221 ret = lan78xx_write_reg(dev, USB_CFG1, buf);
1222 }
1223 }
1224
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001225 ladv = phy_read(phydev, MII_ADVERTISE);
Geert Uytterhoeven99c79ec2015-09-04 12:47:28 +02001226 if (ladv < 0)
1227 return ladv;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001228
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001229 radv = phy_read(phydev, MII_LPA);
Geert Uytterhoeven99c79ec2015-09-04 12:47:28 +02001230 if (radv < 0)
1231 return radv;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001232
1233 netif_dbg(dev, link, dev->net,
1234 "speed: %u duplex: %d anadv: 0x%04x anlpa: 0x%04x",
Philippe Reynes6e765102016-10-09 12:07:04 +02001235 ecmd.base.speed, ecmd.base.duplex, ladv, radv);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001236
Philippe Reynes6e765102016-10-09 12:07:04 +02001237 ret = lan78xx_update_flowcontrol(dev, ecmd.base.duplex, ladv,
1238 radv);
Woojung Huh20ff5562016-03-16 22:10:40 +00001239
1240 if (!timer_pending(&dev->stat_monitor)) {
1241 dev->delta = 1;
1242 mod_timer(&dev->stat_monitor,
1243 jiffies + STAT_UPDATE_TIMER);
1244 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001245 }
1246
1247 return ret;
1248}
1249
1250/* some work can't be done in tasklets, so we use keventd
1251 *
1252 * NOTE: annoying asymmetry: if it's active, schedule_work() fails,
1253 * but tasklet_schedule() doesn't. hope the failure is rare.
1254 */
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08001255static void lan78xx_defer_kevent(struct lan78xx_net *dev, int work)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001256{
1257 set_bit(work, &dev->flags);
1258 if (!schedule_delayed_work(&dev->wq, 0))
1259 netdev_err(dev->net, "kevent %d may have been dropped\n", work);
1260}
1261
1262static void lan78xx_status(struct lan78xx_net *dev, struct urb *urb)
1263{
1264 u32 intdata;
1265
1266 if (urb->actual_length != 4) {
1267 netdev_warn(dev->net,
1268 "unexpected urb length %d", urb->actual_length);
1269 return;
1270 }
1271
1272 memcpy(&intdata, urb->transfer_buffer, 4);
1273 le32_to_cpus(&intdata);
1274
1275 if (intdata & INT_ENP_PHY_INT) {
1276 netif_dbg(dev, link, dev->net, "PHY INTR: 0x%08x\n", intdata);
Woojung Huhcc89c322016-11-01 20:02:00 +00001277 lan78xx_defer_kevent(dev, EVENT_LINK_RESET);
1278
1279 if (dev->domain_data.phyirq > 0)
1280 generic_handle_irq(dev->domain_data.phyirq);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001281 } else
1282 netdev_warn(dev->net,
1283 "unexpected interrupt: 0x%08x\n", intdata);
1284}
1285
1286static int lan78xx_ethtool_get_eeprom_len(struct net_device *netdev)
1287{
1288 return MAX_EEPROM_SIZE;
1289}
1290
1291static int lan78xx_ethtool_get_eeprom(struct net_device *netdev,
1292 struct ethtool_eeprom *ee, u8 *data)
1293{
1294 struct lan78xx_net *dev = netdev_priv(netdev);
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301295 int ret;
1296
1297 ret = usb_autopm_get_interface(dev->intf);
1298 if (ret)
1299 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001300
1301 ee->magic = LAN78XX_EEPROM_MAGIC;
1302
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301303 ret = lan78xx_read_raw_eeprom(dev, ee->offset, ee->len, data);
1304
1305 usb_autopm_put_interface(dev->intf);
1306
1307 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001308}
1309
1310static int lan78xx_ethtool_set_eeprom(struct net_device *netdev,
1311 struct ethtool_eeprom *ee, u8 *data)
1312{
1313 struct lan78xx_net *dev = netdev_priv(netdev);
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301314 int ret;
1315
1316 ret = usb_autopm_get_interface(dev->intf);
1317 if (ret)
1318 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001319
Nisar Sayedc0776822017-09-21 02:36:37 +05301320 /* Invalid EEPROM_INDICATOR at offset zero will result in a failure
1321 * to load data from EEPROM
1322 */
1323 if (ee->magic == LAN78XX_EEPROM_MAGIC)
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301324 ret = lan78xx_write_raw_eeprom(dev, ee->offset, ee->len, data);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001325 else if ((ee->magic == LAN78XX_OTP_MAGIC) &&
1326 (ee->offset == 0) &&
1327 (ee->len == 512) &&
1328 (data[0] == OTP_INDICATOR_1))
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301329 ret = lan78xx_write_raw_otp(dev, ee->offset, ee->len, data);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001330
Nisar Sayed8a7ffeb2017-09-21 02:36:36 +05301331 usb_autopm_put_interface(dev->intf);
1332
1333 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001334}
1335
1336static void lan78xx_get_strings(struct net_device *netdev, u32 stringset,
1337 u8 *data)
1338{
1339 if (stringset == ETH_SS_STATS)
1340 memcpy(data, lan78xx_gstrings, sizeof(lan78xx_gstrings));
1341}
1342
1343static int lan78xx_get_sset_count(struct net_device *netdev, int sset)
1344{
1345 if (sset == ETH_SS_STATS)
1346 return ARRAY_SIZE(lan78xx_gstrings);
1347 else
1348 return -EOPNOTSUPP;
1349}
1350
1351static void lan78xx_get_stats(struct net_device *netdev,
1352 struct ethtool_stats *stats, u64 *data)
1353{
1354 struct lan78xx_net *dev = netdev_priv(netdev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001355
Woojung Huh20ff5562016-03-16 22:10:40 +00001356 lan78xx_update_stats(dev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001357
Woojung Huh20ff5562016-03-16 22:10:40 +00001358 mutex_lock(&dev->stats.access_lock);
1359 memcpy(data, &dev->stats.curr_stat, sizeof(dev->stats.curr_stat));
1360 mutex_unlock(&dev->stats.access_lock);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001361}
1362
1363static void lan78xx_get_wol(struct net_device *netdev,
1364 struct ethtool_wolinfo *wol)
1365{
1366 struct lan78xx_net *dev = netdev_priv(netdev);
1367 int ret;
1368 u32 buf;
1369 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
1370
1371 if (usb_autopm_get_interface(dev->intf) < 0)
1372 return;
1373
1374 ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
1375 if (unlikely(ret < 0)) {
1376 wol->supported = 0;
1377 wol->wolopts = 0;
1378 } else {
1379 if (buf & USB_CFG_RMT_WKP_) {
1380 wol->supported = WAKE_ALL;
1381 wol->wolopts = pdata->wol;
1382 } else {
1383 wol->supported = 0;
1384 wol->wolopts = 0;
1385 }
1386 }
1387
1388 usb_autopm_put_interface(dev->intf);
1389}
1390
1391static int lan78xx_set_wol(struct net_device *netdev,
1392 struct ethtool_wolinfo *wol)
1393{
1394 struct lan78xx_net *dev = netdev_priv(netdev);
1395 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
1396 int ret;
1397
1398 ret = usb_autopm_get_interface(dev->intf);
1399 if (ret < 0)
1400 return ret;
1401
1402 pdata->wol = 0;
1403 if (wol->wolopts & WAKE_UCAST)
1404 pdata->wol |= WAKE_UCAST;
1405 if (wol->wolopts & WAKE_MCAST)
1406 pdata->wol |= WAKE_MCAST;
1407 if (wol->wolopts & WAKE_BCAST)
1408 pdata->wol |= WAKE_BCAST;
1409 if (wol->wolopts & WAKE_MAGIC)
1410 pdata->wol |= WAKE_MAGIC;
1411 if (wol->wolopts & WAKE_PHY)
1412 pdata->wol |= WAKE_PHY;
1413 if (wol->wolopts & WAKE_ARP)
1414 pdata->wol |= WAKE_ARP;
1415
1416 device_set_wakeup_enable(&dev->udev->dev, (bool)wol->wolopts);
1417
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001418 phy_ethtool_set_wol(netdev->phydev, wol);
1419
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001420 usb_autopm_put_interface(dev->intf);
1421
1422 return ret;
1423}
1424
1425static int lan78xx_get_eee(struct net_device *net, struct ethtool_eee *edata)
1426{
1427 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001428 struct phy_device *phydev = net->phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001429 int ret;
1430 u32 buf;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001431
1432 ret = usb_autopm_get_interface(dev->intf);
1433 if (ret < 0)
1434 return ret;
1435
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001436 ret = phy_ethtool_get_eee(phydev, edata);
1437 if (ret < 0)
1438 goto exit;
1439
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001440 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1441 if (buf & MAC_CR_EEE_EN_) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001442 edata->eee_enabled = true;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001443 edata->eee_active = !!(edata->advertised &
1444 edata->lp_advertised);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001445 edata->tx_lpi_enabled = true;
1446 /* EEE_TX_LPI_REQ_DLY & tx_lpi_timer are same uSec unit */
1447 ret = lan78xx_read_reg(dev, EEE_TX_LPI_REQ_DLY, &buf);
1448 edata->tx_lpi_timer = buf;
1449 } else {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001450 edata->eee_enabled = false;
1451 edata->eee_active = false;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001452 edata->tx_lpi_enabled = false;
1453 edata->tx_lpi_timer = 0;
1454 }
1455
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001456 ret = 0;
1457exit:
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001458 usb_autopm_put_interface(dev->intf);
1459
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001460 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001461}
1462
1463static int lan78xx_set_eee(struct net_device *net, struct ethtool_eee *edata)
1464{
1465 struct lan78xx_net *dev = netdev_priv(net);
1466 int ret;
1467 u32 buf;
1468
1469 ret = usb_autopm_get_interface(dev->intf);
1470 if (ret < 0)
1471 return ret;
1472
1473 if (edata->eee_enabled) {
1474 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1475 buf |= MAC_CR_EEE_EN_;
1476 ret = lan78xx_write_reg(dev, MAC_CR, buf);
1477
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001478 phy_ethtool_set_eee(net->phydev, edata);
1479
1480 buf = (u32)edata->tx_lpi_timer;
1481 ret = lan78xx_write_reg(dev, EEE_TX_LPI_REQ_DLY, buf);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001482 } else {
1483 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
1484 buf &= ~MAC_CR_EEE_EN_;
1485 ret = lan78xx_write_reg(dev, MAC_CR, buf);
1486 }
1487
1488 usb_autopm_put_interface(dev->intf);
1489
1490 return 0;
1491}
1492
1493static u32 lan78xx_get_link(struct net_device *net)
1494{
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001495 phy_read_status(net->phydev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001496
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001497 return net->phydev->link;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001498}
1499
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001500static void lan78xx_get_drvinfo(struct net_device *net,
1501 struct ethtool_drvinfo *info)
1502{
1503 struct lan78xx_net *dev = netdev_priv(net);
1504
1505 strncpy(info->driver, DRIVER_NAME, sizeof(info->driver));
1506 strncpy(info->version, DRIVER_VERSION, sizeof(info->version));
1507 usb_make_path(dev->udev, info->bus_info, sizeof(info->bus_info));
1508}
1509
1510static u32 lan78xx_get_msglevel(struct net_device *net)
1511{
1512 struct lan78xx_net *dev = netdev_priv(net);
1513
1514 return dev->msg_enable;
1515}
1516
1517static void lan78xx_set_msglevel(struct net_device *net, u32 level)
1518{
1519 struct lan78xx_net *dev = netdev_priv(net);
1520
1521 dev->msg_enable = level;
1522}
1523
Philippe Reynes6e765102016-10-09 12:07:04 +02001524static int lan78xx_get_link_ksettings(struct net_device *net,
1525 struct ethtool_link_ksettings *cmd)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001526{
1527 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001528 struct phy_device *phydev = net->phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001529 int ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001530
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001531 ret = usb_autopm_get_interface(dev->intf);
1532 if (ret < 0)
1533 return ret;
1534
yuval.shaia@oracle.com55141742017-06-13 10:09:46 +03001535 phy_ethtool_ksettings_get(phydev, cmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001536
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001537 usb_autopm_put_interface(dev->intf);
1538
1539 return ret;
1540}
1541
Philippe Reynes6e765102016-10-09 12:07:04 +02001542static int lan78xx_set_link_ksettings(struct net_device *net,
1543 const struct ethtool_link_ksettings *cmd)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001544{
1545 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001546 struct phy_device *phydev = net->phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001547 int ret = 0;
1548 int temp;
1549
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001550 ret = usb_autopm_get_interface(dev->intf);
1551 if (ret < 0)
1552 return ret;
1553
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001554 /* change speed & duplex */
Philippe Reynes6e765102016-10-09 12:07:04 +02001555 ret = phy_ethtool_ksettings_set(phydev, cmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001556
Philippe Reynes6e765102016-10-09 12:07:04 +02001557 if (!cmd->base.autoneg) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001558 /* force link down */
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001559 temp = phy_read(phydev, MII_BMCR);
1560 phy_write(phydev, MII_BMCR, temp | BMCR_LOOPBACK);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001561 mdelay(1);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001562 phy_write(phydev, MII_BMCR, temp);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001563 }
1564
1565 usb_autopm_put_interface(dev->intf);
1566
1567 return ret;
1568}
1569
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001570static void lan78xx_get_pause(struct net_device *net,
1571 struct ethtool_pauseparam *pause)
1572{
1573 struct lan78xx_net *dev = netdev_priv(net);
1574 struct phy_device *phydev = net->phydev;
Philippe Reynes6e765102016-10-09 12:07:04 +02001575 struct ethtool_link_ksettings ecmd;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001576
Philippe Reynes6e765102016-10-09 12:07:04 +02001577 phy_ethtool_ksettings_get(phydev, &ecmd);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001578
1579 pause->autoneg = dev->fc_autoneg;
1580
1581 if (dev->fc_request_control & FLOW_CTRL_TX)
1582 pause->tx_pause = 1;
1583
1584 if (dev->fc_request_control & FLOW_CTRL_RX)
1585 pause->rx_pause = 1;
1586}
1587
1588static int lan78xx_set_pause(struct net_device *net,
1589 struct ethtool_pauseparam *pause)
1590{
1591 struct lan78xx_net *dev = netdev_priv(net);
1592 struct phy_device *phydev = net->phydev;
Philippe Reynes6e765102016-10-09 12:07:04 +02001593 struct ethtool_link_ksettings ecmd;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001594 int ret;
1595
Philippe Reynes6e765102016-10-09 12:07:04 +02001596 phy_ethtool_ksettings_get(phydev, &ecmd);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001597
Philippe Reynes6e765102016-10-09 12:07:04 +02001598 if (pause->autoneg && !ecmd.base.autoneg) {
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001599 ret = -EINVAL;
1600 goto exit;
1601 }
1602
1603 dev->fc_request_control = 0;
1604 if (pause->rx_pause)
1605 dev->fc_request_control |= FLOW_CTRL_RX;
1606
1607 if (pause->tx_pause)
1608 dev->fc_request_control |= FLOW_CTRL_TX;
1609
Philippe Reynes6e765102016-10-09 12:07:04 +02001610 if (ecmd.base.autoneg) {
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001611 u32 mii_adv;
Philippe Reynes6e765102016-10-09 12:07:04 +02001612 u32 advertising;
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001613
Philippe Reynes6e765102016-10-09 12:07:04 +02001614 ethtool_convert_link_mode_to_legacy_u32(
1615 &advertising, ecmd.link_modes.advertising);
1616
1617 advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001618 mii_adv = (u32)mii_advertise_flowctrl(dev->fc_request_control);
Philippe Reynes6e765102016-10-09 12:07:04 +02001619 advertising |= mii_adv_to_ethtool_adv_t(mii_adv);
1620
1621 ethtool_convert_legacy_u32_to_link_mode(
1622 ecmd.link_modes.advertising, advertising);
1623
1624 phy_ethtool_ksettings_set(phydev, &ecmd);
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001625 }
1626
1627 dev->fc_autoneg = pause->autoneg;
1628
1629 ret = 0;
1630exit:
1631 return ret;
1632}
1633
Raghuram Chary J49621862018-04-20 11:43:50 +05301634static int lan78xx_get_regs_len(struct net_device *netdev)
1635{
1636 if (!netdev->phydev)
1637 return (sizeof(lan78xx_regs));
1638 else
1639 return (sizeof(lan78xx_regs) + PHY_REG_SIZE);
1640}
1641
1642static void
1643lan78xx_get_regs(struct net_device *netdev, struct ethtool_regs *regs,
1644 void *buf)
1645{
1646 u32 *data = buf;
1647 int i, j;
1648 struct lan78xx_net *dev = netdev_priv(netdev);
1649
1650 /* Read Device/MAC registers */
1651 for (i = 0; i < (sizeof(lan78xx_regs) / sizeof(u32)); i++)
1652 lan78xx_read_reg(dev, lan78xx_regs[i], &data[i]);
1653
1654 if (!netdev->phydev)
1655 return;
1656
1657 /* Read PHY registers */
1658 for (j = 0; j < 32; i++, j++)
1659 data[i] = phy_read(netdev->phydev, j);
1660}
1661
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001662static const struct ethtool_ops lan78xx_ethtool_ops = {
1663 .get_link = lan78xx_get_link,
Florian Fainelli860ce4b2016-11-15 10:06:44 -08001664 .nway_reset = phy_ethtool_nway_reset,
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001665 .get_drvinfo = lan78xx_get_drvinfo,
1666 .get_msglevel = lan78xx_get_msglevel,
1667 .set_msglevel = lan78xx_set_msglevel,
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001668 .get_eeprom_len = lan78xx_ethtool_get_eeprom_len,
1669 .get_eeprom = lan78xx_ethtool_get_eeprom,
1670 .set_eeprom = lan78xx_ethtool_set_eeprom,
1671 .get_ethtool_stats = lan78xx_get_stats,
1672 .get_sset_count = lan78xx_get_sset_count,
1673 .get_strings = lan78xx_get_strings,
1674 .get_wol = lan78xx_get_wol,
1675 .set_wol = lan78xx_set_wol,
1676 .get_eee = lan78xx_get_eee,
1677 .set_eee = lan78xx_set_eee,
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00001678 .get_pauseparam = lan78xx_get_pause,
1679 .set_pauseparam = lan78xx_set_pause,
Philippe Reynes6e765102016-10-09 12:07:04 +02001680 .get_link_ksettings = lan78xx_get_link_ksettings,
1681 .set_link_ksettings = lan78xx_set_link_ksettings,
Raghuram Chary J49621862018-04-20 11:43:50 +05301682 .get_regs_len = lan78xx_get_regs_len,
1683 .get_regs = lan78xx_get_regs,
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001684};
1685
1686static int lan78xx_ioctl(struct net_device *netdev, struct ifreq *rq, int cmd)
1687{
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001688 if (!netif_running(netdev))
1689 return -EINVAL;
1690
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001691 return phy_mii_ioctl(netdev->phydev, rq, cmd);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001692}
1693
1694static void lan78xx_init_mac_address(struct lan78xx_net *dev)
1695{
1696 u32 addr_lo, addr_hi;
1697 int ret;
1698 u8 addr[6];
1699
1700 ret = lan78xx_read_reg(dev, RX_ADDRL, &addr_lo);
1701 ret = lan78xx_read_reg(dev, RX_ADDRH, &addr_hi);
1702
1703 addr[0] = addr_lo & 0xFF;
1704 addr[1] = (addr_lo >> 8) & 0xFF;
1705 addr[2] = (addr_lo >> 16) & 0xFF;
1706 addr[3] = (addr_lo >> 24) & 0xFF;
1707 addr[4] = addr_hi & 0xFF;
1708 addr[5] = (addr_hi >> 8) & 0xFF;
1709
1710 if (!is_valid_ether_addr(addr)) {
Phil Elwell760db292018-04-19 17:59:38 +01001711 if (!eth_platform_get_mac_address(&dev->udev->dev, addr)) {
1712 /* valid address present in Device Tree */
1713 netif_dbg(dev, ifup, dev->net,
1714 "MAC address read from Device Tree");
1715 } else if (((lan78xx_read_eeprom(dev, EEPROM_MAC_OFFSET,
1716 ETH_ALEN, addr) == 0) ||
1717 (lan78xx_read_otp(dev, EEPROM_MAC_OFFSET,
1718 ETH_ALEN, addr) == 0)) &&
1719 is_valid_ether_addr(addr)) {
1720 /* eeprom values are valid so use them */
1721 netif_dbg(dev, ifup, dev->net,
1722 "MAC address read from EEPROM");
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001723 } else {
1724 /* generate random MAC */
1725 random_ether_addr(addr);
1726 netif_dbg(dev, ifup, dev->net,
1727 "MAC address set to random addr");
1728 }
Phil Elwell760db292018-04-19 17:59:38 +01001729
1730 addr_lo = addr[0] | (addr[1] << 8) |
1731 (addr[2] << 16) | (addr[3] << 24);
1732 addr_hi = addr[4] | (addr[5] << 8);
1733
1734 ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
1735 ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001736 }
1737
1738 ret = lan78xx_write_reg(dev, MAF_LO(0), addr_lo);
1739 ret = lan78xx_write_reg(dev, MAF_HI(0), addr_hi | MAF_HI_VALID_);
1740
1741 ether_addr_copy(dev->net->dev_addr, addr);
1742}
1743
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001744/* MDIO read and write wrappers for phylib */
1745static int lan78xx_mdiobus_read(struct mii_bus *bus, int phy_id, int idx)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001746{
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001747 struct lan78xx_net *dev = bus->priv;
1748 u32 val, addr;
1749 int ret;
1750
1751 ret = usb_autopm_get_interface(dev->intf);
1752 if (ret < 0)
1753 return ret;
1754
1755 mutex_lock(&dev->phy_mutex);
1756
1757 /* confirm MII not busy */
1758 ret = lan78xx_phy_wait_not_busy(dev);
1759 if (ret < 0)
1760 goto done;
1761
1762 /* set the address, index & direction (read from PHY) */
1763 addr = mii_access(phy_id, idx, MII_READ);
1764 ret = lan78xx_write_reg(dev, MII_ACC, addr);
1765
1766 ret = lan78xx_phy_wait_not_busy(dev);
1767 if (ret < 0)
1768 goto done;
1769
1770 ret = lan78xx_read_reg(dev, MII_DATA, &val);
1771
1772 ret = (int)(val & 0xFFFF);
1773
1774done:
1775 mutex_unlock(&dev->phy_mutex);
1776 usb_autopm_put_interface(dev->intf);
Woojung Huh02dc1f32016-12-07 20:26:25 +00001777
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001778 return ret;
1779}
1780
1781static int lan78xx_mdiobus_write(struct mii_bus *bus, int phy_id, int idx,
1782 u16 regval)
1783{
1784 struct lan78xx_net *dev = bus->priv;
1785 u32 val, addr;
1786 int ret;
1787
1788 ret = usb_autopm_get_interface(dev->intf);
1789 if (ret < 0)
1790 return ret;
1791
1792 mutex_lock(&dev->phy_mutex);
1793
1794 /* confirm MII not busy */
1795 ret = lan78xx_phy_wait_not_busy(dev);
1796 if (ret < 0)
1797 goto done;
1798
1799 val = (u32)regval;
1800 ret = lan78xx_write_reg(dev, MII_DATA, val);
1801
1802 /* set the address, index & direction (write to PHY) */
1803 addr = mii_access(phy_id, idx, MII_WRITE);
1804 ret = lan78xx_write_reg(dev, MII_ACC, addr);
1805
1806 ret = lan78xx_phy_wait_not_busy(dev);
1807 if (ret < 0)
1808 goto done;
1809
1810done:
1811 mutex_unlock(&dev->phy_mutex);
1812 usb_autopm_put_interface(dev->intf);
1813 return 0;
1814}
1815
1816static int lan78xx_mdio_init(struct lan78xx_net *dev)
1817{
Phil Elwell1827b062018-04-19 17:59:39 +01001818 struct device_node *node;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001819 int ret;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001820
1821 dev->mdiobus = mdiobus_alloc();
1822 if (!dev->mdiobus) {
1823 netdev_err(dev->net, "can't allocate MDIO bus\n");
1824 return -ENOMEM;
1825 }
1826
1827 dev->mdiobus->priv = (void *)dev;
1828 dev->mdiobus->read = lan78xx_mdiobus_read;
1829 dev->mdiobus->write = lan78xx_mdiobus_write;
1830 dev->mdiobus->name = "lan78xx-mdiobus";
1831
1832 snprintf(dev->mdiobus->id, MII_BUS_ID_SIZE, "usb-%03d:%03d",
1833 dev->udev->bus->busnum, dev->udev->devnum);
1834
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +00001835 switch (dev->chipid) {
1836 case ID_REV_CHIP_ID_7800_:
1837 case ID_REV_CHIP_ID_7850_:
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001838 /* set to internal PHY id */
1839 dev->mdiobus->phy_mask = ~(1 << 1);
1840 break;
Woojung Huh02dc1f32016-12-07 20:26:25 +00001841 case ID_REV_CHIP_ID_7801_:
1842 /* scan thru PHYAD[2..0] */
1843 dev->mdiobus->phy_mask = ~(0xFF);
1844 break;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001845 }
1846
Phil Elwell1827b062018-04-19 17:59:39 +01001847 node = of_get_child_by_name(dev->udev->dev.of_node, "mdio");
1848 if (node) {
1849 ret = of_mdiobus_register(dev->mdiobus, node);
1850 of_node_put(node);
1851 } else {
1852 ret = mdiobus_register(dev->mdiobus);
1853 }
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001854 if (ret) {
1855 netdev_err(dev->net, "can't register MDIO bus\n");
Andrew Lunne7f4dc32016-01-06 20:11:15 +01001856 goto exit1;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001857 }
1858
1859 netdev_dbg(dev->net, "registered mdiobus bus %s\n", dev->mdiobus->id);
1860 return 0;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001861exit1:
1862 mdiobus_free(dev->mdiobus);
1863 return ret;
1864}
1865
1866static void lan78xx_remove_mdio(struct lan78xx_net *dev)
1867{
1868 mdiobus_unregister(dev->mdiobus);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00001869 mdiobus_free(dev->mdiobus);
1870}
1871
1872static void lan78xx_link_status_change(struct net_device *net)
1873{
Woojung Huh14437e32016-04-25 22:22:36 +00001874 struct phy_device *phydev = net->phydev;
1875 int ret, temp;
1876
1877 /* At forced 100 F/H mode, chip may fail to set mode correctly
1878 * when cable is switched between long(~50+m) and short one.
1879 * As workaround, set to 10 before setting to 100
1880 * at forced 100 F/H mode.
1881 */
1882 if (!phydev->autoneg && (phydev->speed == 100)) {
1883 /* disable phy interrupt */
1884 temp = phy_read(phydev, LAN88XX_INT_MASK);
1885 temp &= ~LAN88XX_INT_MASK_MDINTPIN_EN_;
1886 ret = phy_write(phydev, LAN88XX_INT_MASK, temp);
1887
1888 temp = phy_read(phydev, MII_BMCR);
1889 temp &= ~(BMCR_SPEED100 | BMCR_SPEED1000);
1890 phy_write(phydev, MII_BMCR, temp); /* set to 10 first */
1891 temp |= BMCR_SPEED100;
1892 phy_write(phydev, MII_BMCR, temp); /* set to 100 later */
1893
1894 /* clear pending interrupt generated while workaround */
1895 temp = phy_read(phydev, LAN88XX_INT_STS);
1896
1897 /* enable phy interrupt back */
1898 temp = phy_read(phydev, LAN88XX_INT_MASK);
1899 temp |= LAN88XX_INT_MASK_MDINTPIN_EN_;
1900 ret = phy_write(phydev, LAN88XX_INT_MASK, temp);
1901 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00001902}
1903
Woojung Huhcc89c322016-11-01 20:02:00 +00001904static int irq_map(struct irq_domain *d, unsigned int irq,
1905 irq_hw_number_t hwirq)
1906{
1907 struct irq_domain_data *data = d->host_data;
1908
1909 irq_set_chip_data(irq, data);
1910 irq_set_chip_and_handler(irq, data->irqchip, data->irq_handler);
1911 irq_set_noprobe(irq);
1912
1913 return 0;
1914}
1915
1916static void irq_unmap(struct irq_domain *d, unsigned int irq)
1917{
1918 irq_set_chip_and_handler(irq, NULL, NULL);
1919 irq_set_chip_data(irq, NULL);
1920}
1921
1922static const struct irq_domain_ops chip_domain_ops = {
1923 .map = irq_map,
1924 .unmap = irq_unmap,
1925};
1926
1927static void lan78xx_irq_mask(struct irq_data *irqd)
1928{
1929 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1930
1931 data->irqenable &= ~BIT(irqd_to_hwirq(irqd));
1932}
1933
1934static void lan78xx_irq_unmask(struct irq_data *irqd)
1935{
1936 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1937
1938 data->irqenable |= BIT(irqd_to_hwirq(irqd));
1939}
1940
1941static void lan78xx_irq_bus_lock(struct irq_data *irqd)
1942{
1943 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1944
1945 mutex_lock(&data->irq_lock);
1946}
1947
1948static void lan78xx_irq_bus_sync_unlock(struct irq_data *irqd)
1949{
1950 struct irq_domain_data *data = irq_data_get_irq_chip_data(irqd);
1951 struct lan78xx_net *dev =
1952 container_of(data, struct lan78xx_net, domain_data);
1953 u32 buf;
1954 int ret;
1955
1956 /* call register access here because irq_bus_lock & irq_bus_sync_unlock
1957 * are only two callbacks executed in non-atomic contex.
1958 */
1959 ret = lan78xx_read_reg(dev, INT_EP_CTL, &buf);
1960 if (buf != data->irqenable)
1961 ret = lan78xx_write_reg(dev, INT_EP_CTL, data->irqenable);
1962
1963 mutex_unlock(&data->irq_lock);
1964}
1965
1966static struct irq_chip lan78xx_irqchip = {
1967 .name = "lan78xx-irqs",
1968 .irq_mask = lan78xx_irq_mask,
1969 .irq_unmask = lan78xx_irq_unmask,
1970 .irq_bus_lock = lan78xx_irq_bus_lock,
1971 .irq_bus_sync_unlock = lan78xx_irq_bus_sync_unlock,
1972};
1973
1974static int lan78xx_setup_irq_domain(struct lan78xx_net *dev)
1975{
1976 struct device_node *of_node;
1977 struct irq_domain *irqdomain;
1978 unsigned int irqmap = 0;
1979 u32 buf;
1980 int ret = 0;
1981
1982 of_node = dev->udev->dev.parent->of_node;
1983
1984 mutex_init(&dev->domain_data.irq_lock);
1985
1986 lan78xx_read_reg(dev, INT_EP_CTL, &buf);
1987 dev->domain_data.irqenable = buf;
1988
1989 dev->domain_data.irqchip = &lan78xx_irqchip;
1990 dev->domain_data.irq_handler = handle_simple_irq;
1991
1992 irqdomain = irq_domain_add_simple(of_node, MAX_INT_EP, 0,
1993 &chip_domain_ops, &dev->domain_data);
1994 if (irqdomain) {
1995 /* create mapping for PHY interrupt */
1996 irqmap = irq_create_mapping(irqdomain, INT_EP_PHY);
1997 if (!irqmap) {
1998 irq_domain_remove(irqdomain);
1999
2000 irqdomain = NULL;
2001 ret = -EINVAL;
2002 }
2003 } else {
2004 ret = -EINVAL;
2005 }
2006
2007 dev->domain_data.irqdomain = irqdomain;
2008 dev->domain_data.phyirq = irqmap;
2009
2010 return ret;
2011}
2012
2013static void lan78xx_remove_irq_domain(struct lan78xx_net *dev)
2014{
2015 if (dev->domain_data.phyirq > 0) {
2016 irq_dispose_mapping(dev->domain_data.phyirq);
2017
2018 if (dev->domain_data.irqdomain)
2019 irq_domain_remove(dev->domain_data.irqdomain);
2020 }
2021 dev->domain_data.phyirq = 0;
2022 dev->domain_data.irqdomain = NULL;
2023}
2024
Woojung Huh02dc1f32016-12-07 20:26:25 +00002025static int lan8835_fixup(struct phy_device *phydev)
2026{
2027 int buf;
2028 int ret;
2029 struct lan78xx_net *dev = netdev_priv(phydev->attached_dev);
2030
2031 /* LED2/PME_N/IRQ_N/RGMII_ID pin to IRQ_N mode */
Russell King5f613672017-03-21 16:36:48 +00002032 buf = phy_read_mmd(phydev, MDIO_MMD_PCS, 0x8010);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002033 buf &= ~0x1800;
2034 buf |= 0x0800;
Russell King5f613672017-03-21 16:36:48 +00002035 phy_write_mmd(phydev, MDIO_MMD_PCS, 0x8010, buf);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002036
2037 /* RGMII MAC TXC Delay Enable */
2038 ret = lan78xx_write_reg(dev, MAC_RGMII_ID,
2039 MAC_RGMII_ID_TXC_DELAY_EN_);
2040
2041 /* RGMII TX DLL Tune Adjust */
2042 ret = lan78xx_write_reg(dev, RGMII_TX_BYP_DLL, 0x3D00);
2043
2044 dev->interface = PHY_INTERFACE_MODE_RGMII_TXID;
2045
2046 return 1;
2047}
2048
2049static int ksz9031rnx_fixup(struct phy_device *phydev)
2050{
2051 struct lan78xx_net *dev = netdev_priv(phydev->attached_dev);
2052
2053 /* Micrel9301RNX PHY configuration */
2054 /* RGMII Control Signal Pad Skew */
Russell King5f613672017-03-21 16:36:48 +00002055 phy_write_mmd(phydev, MDIO_MMD_WIS, 4, 0x0077);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002056 /* RGMII RX Data Pad Skew */
Russell King5f613672017-03-21 16:36:48 +00002057 phy_write_mmd(phydev, MDIO_MMD_WIS, 5, 0x7777);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002058 /* RGMII RX Clock Pad Skew */
Russell King5f613672017-03-21 16:36:48 +00002059 phy_write_mmd(phydev, MDIO_MMD_WIS, 8, 0x1FF);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002060
2061 dev->interface = PHY_INTERFACE_MODE_RGMII_RXID;
2062
2063 return 1;
2064}
2065
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302066static struct phy_device *lan7801_phy_init(struct lan78xx_net *dev)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002067{
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302068 u32 buf;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002069 int ret;
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302070 struct fixed_phy_status fphy_status = {
2071 .link = 1,
2072 .speed = SPEED_1000,
2073 .duplex = DUPLEX_FULL,
2074 };
Colin Ian King3b51cc72018-02-01 17:10:18 +00002075 struct phy_device *phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002076
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002077 phydev = phy_find_first(dev->mdiobus);
2078 if (!phydev) {
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302079 netdev_dbg(dev->net, "PHY Not Found!! Registering Fixed PHY\n");
2080 phydev = fixed_phy_register(PHY_POLL, &fphy_status, -1,
2081 NULL);
2082 if (IS_ERR(phydev)) {
2083 netdev_err(dev->net, "No PHY/fixed_PHY found\n");
2084 return NULL;
2085 }
2086 netdev_dbg(dev->net, "Registered FIXED PHY\n");
2087 dev->interface = PHY_INTERFACE_MODE_RGMII;
2088 ret = lan78xx_write_reg(dev, MAC_RGMII_ID,
2089 MAC_RGMII_ID_TXC_DELAY_EN_);
2090 ret = lan78xx_write_reg(dev, RGMII_TX_BYP_DLL, 0x3D00);
2091 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2092 buf |= HW_CFG_CLK125_EN_;
2093 buf |= HW_CFG_REFCLK25_EN_;
2094 ret = lan78xx_write_reg(dev, HW_CFG, buf);
2095 } else {
Woojung Huh02dc1f32016-12-07 20:26:25 +00002096 if (!phydev->drv) {
2097 netdev_err(dev->net, "no PHY driver found\n");
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302098 return NULL;
Woojung Huh02dc1f32016-12-07 20:26:25 +00002099 }
Woojung Huh02dc1f32016-12-07 20:26:25 +00002100 dev->interface = PHY_INTERFACE_MODE_RGMII;
Woojung Huh02dc1f32016-12-07 20:26:25 +00002101 /* external PHY fixup for KSZ9031RNX */
2102 ret = phy_register_fixup_for_uid(PHY_KSZ9031RNX, 0xfffffff0,
2103 ksz9031rnx_fixup);
2104 if (ret < 0) {
2105 netdev_err(dev->net, "fail to register fixup\n");
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302106 return NULL;
Woojung Huh02dc1f32016-12-07 20:26:25 +00002107 }
2108 /* external PHY fixup for LAN8835 */
2109 ret = phy_register_fixup_for_uid(PHY_LAN8835, 0xfffffff0,
2110 lan8835_fixup);
2111 if (ret < 0) {
2112 netdev_err(dev->net, "fail to register fixup\n");
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302113 return NULL;
Woojung Huh02dc1f32016-12-07 20:26:25 +00002114 }
2115 /* add more external PHY fixup here if needed */
2116
2117 phydev->is_internal = false;
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302118 }
2119 return phydev;
2120}
2121
2122static int lan78xx_phy_init(struct lan78xx_net *dev)
2123{
2124 int ret;
2125 u32 mii_adv;
2126 struct phy_device *phydev;
2127
2128 switch (dev->chipid) {
2129 case ID_REV_CHIP_ID_7801_:
2130 phydev = lan7801_phy_init(dev);
2131 if (!phydev) {
2132 netdev_err(dev->net, "lan7801: PHY Init Failed");
2133 return -EIO;
2134 }
2135 break;
2136
2137 case ID_REV_CHIP_ID_7800_:
2138 case ID_REV_CHIP_ID_7850_:
2139 phydev = phy_find_first(dev->mdiobus);
2140 if (!phydev) {
2141 netdev_err(dev->net, "no PHY found\n");
2142 return -EIO;
2143 }
2144 phydev->is_internal = true;
2145 dev->interface = PHY_INTERFACE_MODE_GMII;
2146 break;
2147
2148 default:
2149 netdev_err(dev->net, "Unknown CHIP ID found\n");
2150 return -EIO;
Woojung Huh02dc1f32016-12-07 20:26:25 +00002151 }
2152
Woojung Huhcc89c322016-11-01 20:02:00 +00002153 /* if phyirq is not set, use polling mode in phylib */
2154 if (dev->domain_data.phyirq > 0)
2155 phydev->irq = dev->domain_data.phyirq;
2156 else
2157 phydev->irq = 0;
2158 netdev_dbg(dev->net, "phydev->irq = %d\n", phydev->irq);
Woojung.Huh@microchip.come4953912016-01-27 22:57:52 +00002159
Woojung Huhf6e3ef32016-11-17 22:10:02 +00002160 /* set to AUTOMDIX */
2161 phydev->mdix = ETH_TP_MDI_AUTO;
2162
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002163 ret = phy_connect_direct(dev->net, phydev,
2164 lan78xx_link_status_change,
Woojung Huh02dc1f32016-12-07 20:26:25 +00002165 dev->interface);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002166 if (ret) {
2167 netdev_err(dev->net, "can't attach PHY to %s\n",
2168 dev->mdiobus->id);
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05302169 if (dev->chipid == ID_REV_CHIP_ID_7801_) {
2170 if (phy_is_pseudo_fixed_link(phydev)) {
2171 fixed_phy_unregister(phydev);
2172 } else {
2173 phy_unregister_fixup_for_uid(PHY_KSZ9031RNX,
2174 0xfffffff0);
2175 phy_unregister_fixup_for_uid(PHY_LAN8835,
2176 0xfffffff0);
2177 }
2178 }
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002179 return -EIO;
2180 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002181
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002182 /* MAC doesn't support 1000T Half */
2183 phydev->supported &= ~SUPPORTED_1000baseT_Half;
Woojung.Huh@microchip.come270b2d2016-02-25 23:33:09 +00002184
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00002185 /* support both flow controls */
2186 dev->fc_request_control = (FLOW_CTRL_RX | FLOW_CTRL_TX);
2187 phydev->advertising &= ~(ADVERTISED_Pause | ADVERTISED_Asym_Pause);
2188 mii_adv = (u32)mii_advertise_flowctrl(dev->fc_request_control);
2189 phydev->advertising |= mii_adv_to_ethtool_adv_t(mii_adv);
2190
Phil Elwell1827b062018-04-19 17:59:39 +01002191 if (phydev->mdio.dev.of_node) {
2192 u32 reg;
2193 int len;
2194
2195 len = of_property_count_elems_of_size(phydev->mdio.dev.of_node,
2196 "microchip,led-modes",
2197 sizeof(u32));
2198 if (len >= 0) {
2199 /* Ensure the appropriate LEDs are enabled */
2200 lan78xx_read_reg(dev, HW_CFG, &reg);
2201 reg &= ~(HW_CFG_LED0_EN_ |
2202 HW_CFG_LED1_EN_ |
2203 HW_CFG_LED2_EN_ |
2204 HW_CFG_LED3_EN_);
2205 reg |= (len > 0) * HW_CFG_LED0_EN_ |
2206 (len > 1) * HW_CFG_LED1_EN_ |
2207 (len > 2) * HW_CFG_LED2_EN_ |
2208 (len > 3) * HW_CFG_LED3_EN_;
2209 lan78xx_write_reg(dev, HW_CFG, reg);
2210 }
2211 }
2212
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002213 genphy_config_aneg(phydev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002214
Woojung.Huh@microchip.com349e0c52016-02-25 23:33:14 +00002215 dev->fc_autoneg = phydev->autoneg;
2216
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002217 return 0;
2218}
2219
2220static int lan78xx_set_rx_max_frame_length(struct lan78xx_net *dev, int size)
2221{
2222 int ret = 0;
2223 u32 buf;
2224 bool rxenabled;
2225
2226 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
2227
2228 rxenabled = ((buf & MAC_RX_RXEN_) != 0);
2229
2230 if (rxenabled) {
2231 buf &= ~MAC_RX_RXEN_;
2232 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2233 }
2234
2235 /* add 4 to size for FCS */
2236 buf &= ~MAC_RX_MAX_SIZE_MASK_;
2237 buf |= (((size + 4) << MAC_RX_MAX_SIZE_SHIFT_) & MAC_RX_MAX_SIZE_MASK_);
2238
2239 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2240
2241 if (rxenabled) {
2242 buf |= MAC_RX_RXEN_;
2243 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2244 }
2245
2246 return 0;
2247}
2248
2249static int unlink_urbs(struct lan78xx_net *dev, struct sk_buff_head *q)
2250{
2251 struct sk_buff *skb;
2252 unsigned long flags;
2253 int count = 0;
2254
2255 spin_lock_irqsave(&q->lock, flags);
2256 while (!skb_queue_empty(q)) {
2257 struct skb_data *entry;
2258 struct urb *urb;
2259 int ret;
2260
2261 skb_queue_walk(q, skb) {
2262 entry = (struct skb_data *)skb->cb;
2263 if (entry->state != unlink_start)
2264 goto found;
2265 }
2266 break;
2267found:
2268 entry->state = unlink_start;
2269 urb = entry->urb;
2270
2271 /* Get reference count of the URB to avoid it to be
2272 * freed during usb_unlink_urb, which may trigger
2273 * use-after-free problem inside usb_unlink_urb since
2274 * usb_unlink_urb is always racing with .complete
2275 * handler(include defer_bh).
2276 */
2277 usb_get_urb(urb);
2278 spin_unlock_irqrestore(&q->lock, flags);
2279 /* during some PM-driven resume scenarios,
2280 * these (async) unlinks complete immediately
2281 */
2282 ret = usb_unlink_urb(urb);
2283 if (ret != -EINPROGRESS && ret != 0)
2284 netdev_dbg(dev->net, "unlink urb err, %d\n", ret);
2285 else
2286 count++;
2287 usb_put_urb(urb);
2288 spin_lock_irqsave(&q->lock, flags);
2289 }
2290 spin_unlock_irqrestore(&q->lock, flags);
2291 return count;
2292}
2293
2294static int lan78xx_change_mtu(struct net_device *netdev, int new_mtu)
2295{
2296 struct lan78xx_net *dev = netdev_priv(netdev);
2297 int ll_mtu = new_mtu + netdev->hard_header_len;
2298 int old_hard_mtu = dev->hard_mtu;
2299 int old_rx_urb_size = dev->rx_urb_size;
2300 int ret;
2301
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002302 /* no second zero-length packet read wanted after mtu-sized packets */
2303 if ((ll_mtu % dev->maxpacket) == 0)
2304 return -EDOM;
2305
2306 ret = lan78xx_set_rx_max_frame_length(dev, new_mtu + ETH_HLEN);
2307
2308 netdev->mtu = new_mtu;
2309
2310 dev->hard_mtu = netdev->mtu + netdev->hard_header_len;
2311 if (dev->rx_urb_size == old_hard_mtu) {
2312 dev->rx_urb_size = dev->hard_mtu;
2313 if (dev->rx_urb_size > old_rx_urb_size) {
2314 if (netif_running(dev->net)) {
2315 unlink_urbs(dev, &dev->rxq);
2316 tasklet_schedule(&dev->bh);
2317 }
2318 }
2319 }
2320
2321 return 0;
2322}
2323
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002324static int lan78xx_set_mac_addr(struct net_device *netdev, void *p)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002325{
2326 struct lan78xx_net *dev = netdev_priv(netdev);
2327 struct sockaddr *addr = p;
2328 u32 addr_lo, addr_hi;
2329 int ret;
2330
2331 if (netif_running(netdev))
2332 return -EBUSY;
2333
2334 if (!is_valid_ether_addr(addr->sa_data))
2335 return -EADDRNOTAVAIL;
2336
2337 ether_addr_copy(netdev->dev_addr, addr->sa_data);
2338
2339 addr_lo = netdev->dev_addr[0] |
2340 netdev->dev_addr[1] << 8 |
2341 netdev->dev_addr[2] << 16 |
2342 netdev->dev_addr[3] << 24;
2343 addr_hi = netdev->dev_addr[4] |
2344 netdev->dev_addr[5] << 8;
2345
2346 ret = lan78xx_write_reg(dev, RX_ADDRL, addr_lo);
2347 ret = lan78xx_write_reg(dev, RX_ADDRH, addr_hi);
2348
2349 return 0;
2350}
2351
2352/* Enable or disable Rx checksum offload engine */
2353static int lan78xx_set_features(struct net_device *netdev,
2354 netdev_features_t features)
2355{
2356 struct lan78xx_net *dev = netdev_priv(netdev);
2357 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2358 unsigned long flags;
2359 int ret;
2360
2361 spin_lock_irqsave(&pdata->rfe_ctl_lock, flags);
2362
2363 if (features & NETIF_F_RXCSUM) {
2364 pdata->rfe_ctl |= RFE_CTL_TCPUDP_COE_ | RFE_CTL_IP_COE_;
2365 pdata->rfe_ctl |= RFE_CTL_ICMP_COE_ | RFE_CTL_IGMP_COE_;
2366 } else {
2367 pdata->rfe_ctl &= ~(RFE_CTL_TCPUDP_COE_ | RFE_CTL_IP_COE_);
2368 pdata->rfe_ctl &= ~(RFE_CTL_ICMP_COE_ | RFE_CTL_IGMP_COE_);
2369 }
2370
2371 if (features & NETIF_F_HW_VLAN_CTAG_RX)
2372 pdata->rfe_ctl |= RFE_CTL_VLAN_FILTER_;
2373 else
2374 pdata->rfe_ctl &= ~RFE_CTL_VLAN_FILTER_;
2375
2376 spin_unlock_irqrestore(&pdata->rfe_ctl_lock, flags);
2377
2378 ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
2379
2380 return 0;
2381}
2382
2383static void lan78xx_deferred_vlan_write(struct work_struct *param)
2384{
2385 struct lan78xx_priv *pdata =
2386 container_of(param, struct lan78xx_priv, set_vlan);
2387 struct lan78xx_net *dev = pdata->dev;
2388
2389 lan78xx_dataport_write(dev, DP_SEL_RSEL_VLAN_DA_, 0,
2390 DP_SEL_VHF_VLAN_LEN, pdata->vlan_table);
2391}
2392
2393static int lan78xx_vlan_rx_add_vid(struct net_device *netdev,
2394 __be16 proto, u16 vid)
2395{
2396 struct lan78xx_net *dev = netdev_priv(netdev);
2397 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2398 u16 vid_bit_index;
2399 u16 vid_dword_index;
2400
2401 vid_dword_index = (vid >> 5) & 0x7F;
2402 vid_bit_index = vid & 0x1F;
2403
2404 pdata->vlan_table[vid_dword_index] |= (1 << vid_bit_index);
2405
2406 /* defer register writes to a sleepable context */
2407 schedule_work(&pdata->set_vlan);
2408
2409 return 0;
2410}
2411
2412static int lan78xx_vlan_rx_kill_vid(struct net_device *netdev,
2413 __be16 proto, u16 vid)
2414{
2415 struct lan78xx_net *dev = netdev_priv(netdev);
2416 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2417 u16 vid_bit_index;
2418 u16 vid_dword_index;
2419
2420 vid_dword_index = (vid >> 5) & 0x7F;
2421 vid_bit_index = vid & 0x1F;
2422
2423 pdata->vlan_table[vid_dword_index] &= ~(1 << vid_bit_index);
2424
2425 /* defer register writes to a sleepable context */
2426 schedule_work(&pdata->set_vlan);
2427
2428 return 0;
2429}
2430
2431static void lan78xx_init_ltm(struct lan78xx_net *dev)
2432{
2433 int ret;
2434 u32 buf;
2435 u32 regs[6] = { 0 };
2436
2437 ret = lan78xx_read_reg(dev, USB_CFG1, &buf);
2438 if (buf & USB_CFG1_LTM_ENABLE_) {
2439 u8 temp[2];
2440 /* Get values from EEPROM first */
2441 if (lan78xx_read_eeprom(dev, 0x3F, 2, temp) == 0) {
2442 if (temp[0] == 24) {
2443 ret = lan78xx_read_raw_eeprom(dev,
2444 temp[1] * 2,
2445 24,
2446 (u8 *)regs);
2447 if (ret < 0)
2448 return;
2449 }
2450 } else if (lan78xx_read_otp(dev, 0x3F, 2, temp) == 0) {
2451 if (temp[0] == 24) {
2452 ret = lan78xx_read_raw_otp(dev,
2453 temp[1] * 2,
2454 24,
2455 (u8 *)regs);
2456 if (ret < 0)
2457 return;
2458 }
2459 }
2460 }
2461
2462 lan78xx_write_reg(dev, LTM_BELT_IDLE0, regs[0]);
2463 lan78xx_write_reg(dev, LTM_BELT_IDLE1, regs[1]);
2464 lan78xx_write_reg(dev, LTM_BELT_ACT0, regs[2]);
2465 lan78xx_write_reg(dev, LTM_BELT_ACT1, regs[3]);
2466 lan78xx_write_reg(dev, LTM_INACTIVE0, regs[4]);
2467 lan78xx_write_reg(dev, LTM_INACTIVE1, regs[5]);
2468}
2469
2470static int lan78xx_reset(struct lan78xx_net *dev)
2471{
2472 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
2473 u32 buf;
2474 int ret = 0;
2475 unsigned long timeout;
Raghuram Chary Je69647a2018-03-23 15:48:08 +05302476 u8 sig;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002477
2478 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2479 buf |= HW_CFG_LRST_;
2480 ret = lan78xx_write_reg(dev, HW_CFG, buf);
2481
2482 timeout = jiffies + HZ;
2483 do {
2484 mdelay(1);
2485 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2486 if (time_after(jiffies, timeout)) {
2487 netdev_warn(dev->net,
2488 "timeout on completion of LiteReset");
2489 return -EIO;
2490 }
2491 } while (buf & HW_CFG_LRST_);
2492
2493 lan78xx_init_mac_address(dev);
2494
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002495 /* save DEVID for later usage */
2496 ret = lan78xx_read_reg(dev, ID_REV, &buf);
Woojung.Huh@microchip.com87177ba2016-02-25 23:33:07 +00002497 dev->chipid = (buf & ID_REV_CHIP_ID_MASK_) >> 16;
2498 dev->chiprev = buf & ID_REV_CHIP_REV_MASK_;
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002499
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002500 /* Respond to the IN token with a NAK */
2501 ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
2502 buf |= USB_CFG_BIR_;
2503 ret = lan78xx_write_reg(dev, USB_CFG0, buf);
2504
2505 /* Init LTM */
2506 lan78xx_init_ltm(dev);
2507
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002508 if (dev->udev->speed == USB_SPEED_SUPER) {
2509 buf = DEFAULT_BURST_CAP_SIZE / SS_USB_PKT_SIZE;
2510 dev->rx_urb_size = DEFAULT_BURST_CAP_SIZE;
2511 dev->rx_qlen = 4;
2512 dev->tx_qlen = 4;
2513 } else if (dev->udev->speed == USB_SPEED_HIGH) {
2514 buf = DEFAULT_BURST_CAP_SIZE / HS_USB_PKT_SIZE;
2515 dev->rx_urb_size = DEFAULT_BURST_CAP_SIZE;
2516 dev->rx_qlen = RX_MAX_QUEUE_MEMORY / dev->rx_urb_size;
2517 dev->tx_qlen = RX_MAX_QUEUE_MEMORY / dev->hard_mtu;
2518 } else {
2519 buf = DEFAULT_BURST_CAP_SIZE / FS_USB_PKT_SIZE;
2520 dev->rx_urb_size = DEFAULT_BURST_CAP_SIZE;
2521 dev->rx_qlen = 4;
Yuiko Oshinoa5b13792018-01-15 13:24:28 -05002522 dev->tx_qlen = 4;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002523 }
2524
2525 ret = lan78xx_write_reg(dev, BURST_CAP, buf);
2526 ret = lan78xx_write_reg(dev, BULK_IN_DLY, DEFAULT_BULK_IN_DELAY);
2527
2528 ret = lan78xx_read_reg(dev, HW_CFG, &buf);
2529 buf |= HW_CFG_MEF_;
2530 ret = lan78xx_write_reg(dev, HW_CFG, buf);
2531
2532 ret = lan78xx_read_reg(dev, USB_CFG0, &buf);
2533 buf |= USB_CFG_BCE_;
2534 ret = lan78xx_write_reg(dev, USB_CFG0, buf);
2535
2536 /* set FIFO sizes */
2537 buf = (MAX_RX_FIFO_SIZE - 512) / 512;
2538 ret = lan78xx_write_reg(dev, FCT_RX_FIFO_END, buf);
2539
2540 buf = (MAX_TX_FIFO_SIZE - 512) / 512;
2541 ret = lan78xx_write_reg(dev, FCT_TX_FIFO_END, buf);
2542
2543 ret = lan78xx_write_reg(dev, INT_STS, INT_STS_CLEAR_ALL_);
2544 ret = lan78xx_write_reg(dev, FLOW, 0);
2545 ret = lan78xx_write_reg(dev, FCT_FLOW, 0);
2546
2547 /* Don't need rfe_ctl_lock during initialisation */
2548 ret = lan78xx_read_reg(dev, RFE_CTL, &pdata->rfe_ctl);
2549 pdata->rfe_ctl |= RFE_CTL_BCAST_EN_ | RFE_CTL_DA_PERFECT_;
2550 ret = lan78xx_write_reg(dev, RFE_CTL, pdata->rfe_ctl);
2551
2552 /* Enable or disable checksum offload engines */
2553 lan78xx_set_features(dev->net, dev->net->features);
2554
2555 lan78xx_set_multicast(dev->net);
2556
2557 /* reset PHY */
2558 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
2559 buf |= PMT_CTL_PHY_RST_;
2560 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
2561
2562 timeout = jiffies + HZ;
2563 do {
2564 mdelay(1);
2565 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
2566 if (time_after(jiffies, timeout)) {
2567 netdev_warn(dev->net, "timeout waiting for PHY Reset");
2568 return -EIO;
2569 }
Woojung.Huh@microchip.com6c595b02015-09-16 23:40:39 +00002570 } while ((buf & PMT_CTL_PHY_RST_) || !(buf & PMT_CTL_READY_));
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002571
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002572 ret = lan78xx_read_reg(dev, MAC_CR, &buf);
Woojung Huh02dc1f32016-12-07 20:26:25 +00002573 /* LAN7801 only has RGMII mode */
2574 if (dev->chipid == ID_REV_CHIP_ID_7801_)
2575 buf &= ~MAC_CR_GMII_EN_;
Raghuram Chary Je69647a2018-03-23 15:48:08 +05302576
2577 if (dev->chipid == ID_REV_CHIP_ID_7800_) {
2578 ret = lan78xx_read_raw_eeprom(dev, 0, 1, &sig);
2579 if (!ret && sig != EEPROM_INDICATOR) {
2580 /* Implies there is no external eeprom. Set mac speed */
2581 netdev_info(dev->net, "No External EEPROM. Setting MAC Speed\n");
2582 buf |= MAC_CR_AUTO_DUPLEX_ | MAC_CR_AUTO_SPEED_;
2583 }
2584 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002585 ret = lan78xx_write_reg(dev, MAC_CR, buf);
2586
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002587 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
2588 buf |= MAC_TX_TXEN_;
2589 ret = lan78xx_write_reg(dev, MAC_TX, buf);
2590
2591 ret = lan78xx_read_reg(dev, FCT_TX_CTL, &buf);
2592 buf |= FCT_TX_CTL_EN_;
2593 ret = lan78xx_write_reg(dev, FCT_TX_CTL, buf);
2594
2595 ret = lan78xx_set_rx_max_frame_length(dev, dev->net->mtu + ETH_HLEN);
2596
2597 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
2598 buf |= MAC_RX_RXEN_;
2599 ret = lan78xx_write_reg(dev, MAC_RX, buf);
2600
2601 ret = lan78xx_read_reg(dev, FCT_RX_CTL, &buf);
2602 buf |= FCT_RX_CTL_EN_;
2603 ret = lan78xx_write_reg(dev, FCT_RX_CTL, buf);
2604
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002605 return 0;
2606}
2607
Woojung Huh20ff5562016-03-16 22:10:40 +00002608static void lan78xx_init_stats(struct lan78xx_net *dev)
2609{
2610 u32 *p;
2611 int i;
2612
2613 /* initialize for stats update
2614 * some counters are 20bits and some are 32bits
2615 */
2616 p = (u32 *)&dev->stats.rollover_max;
2617 for (i = 0; i < (sizeof(dev->stats.rollover_max) / (sizeof(u32))); i++)
2618 p[i] = 0xFFFFF;
2619
2620 dev->stats.rollover_max.rx_unicast_byte_count = 0xFFFFFFFF;
2621 dev->stats.rollover_max.rx_broadcast_byte_count = 0xFFFFFFFF;
2622 dev->stats.rollover_max.rx_multicast_byte_count = 0xFFFFFFFF;
2623 dev->stats.rollover_max.eee_rx_lpi_transitions = 0xFFFFFFFF;
2624 dev->stats.rollover_max.eee_rx_lpi_time = 0xFFFFFFFF;
2625 dev->stats.rollover_max.tx_unicast_byte_count = 0xFFFFFFFF;
2626 dev->stats.rollover_max.tx_broadcast_byte_count = 0xFFFFFFFF;
2627 dev->stats.rollover_max.tx_multicast_byte_count = 0xFFFFFFFF;
2628 dev->stats.rollover_max.eee_tx_lpi_transitions = 0xFFFFFFFF;
2629 dev->stats.rollover_max.eee_tx_lpi_time = 0xFFFFFFFF;
2630
Phil Elwellfed56072018-04-11 12:02:47 +01002631 set_bit(EVENT_STAT_UPDATE, &dev->flags);
Woojung Huh20ff5562016-03-16 22:10:40 +00002632}
2633
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002634static int lan78xx_open(struct net_device *net)
2635{
2636 struct lan78xx_net *dev = netdev_priv(net);
2637 int ret;
2638
2639 ret = usb_autopm_get_interface(dev->intf);
2640 if (ret < 0)
2641 goto out;
2642
Alexander Graf92571a12018-04-04 00:19:35 +02002643 phy_start(net->phydev);
2644
2645 netif_dbg(dev, ifup, dev->net, "phy initialised successfully");
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002646
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002647 /* for Link Check */
2648 if (dev->urb_intr) {
2649 ret = usb_submit_urb(dev->urb_intr, GFP_KERNEL);
2650 if (ret < 0) {
2651 netif_err(dev, ifup, dev->net,
2652 "intr submit %d\n", ret);
2653 goto done;
2654 }
2655 }
2656
Woojung Huh20ff5562016-03-16 22:10:40 +00002657 lan78xx_init_stats(dev);
2658
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002659 set_bit(EVENT_DEV_OPEN, &dev->flags);
2660
2661 netif_start_queue(net);
2662
2663 dev->link_on = false;
2664
2665 lan78xx_defer_kevent(dev, EVENT_LINK_RESET);
2666done:
2667 usb_autopm_put_interface(dev->intf);
2668
2669out:
2670 return ret;
2671}
2672
2673static void lan78xx_terminate_urbs(struct lan78xx_net *dev)
2674{
2675 DECLARE_WAIT_QUEUE_HEAD_ONSTACK(unlink_wakeup);
2676 DECLARE_WAITQUEUE(wait, current);
2677 int temp;
2678
2679 /* ensure there are no more active urbs */
2680 add_wait_queue(&unlink_wakeup, &wait);
2681 set_current_state(TASK_UNINTERRUPTIBLE);
2682 dev->wait = &unlink_wakeup;
2683 temp = unlink_urbs(dev, &dev->txq) + unlink_urbs(dev, &dev->rxq);
2684
2685 /* maybe wait for deletions to finish. */
2686 while (!skb_queue_empty(&dev->rxq) &&
2687 !skb_queue_empty(&dev->txq) &&
2688 !skb_queue_empty(&dev->done)) {
2689 schedule_timeout(msecs_to_jiffies(UNLINK_TIMEOUT_MS));
2690 set_current_state(TASK_UNINTERRUPTIBLE);
2691 netif_dbg(dev, ifdown, dev->net,
2692 "waited for %d urb completions\n", temp);
2693 }
2694 set_current_state(TASK_RUNNING);
2695 dev->wait = NULL;
2696 remove_wait_queue(&unlink_wakeup, &wait);
2697}
2698
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002699static int lan78xx_stop(struct net_device *net)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002700{
2701 struct lan78xx_net *dev = netdev_priv(net);
2702
Woojung Huh20ff5562016-03-16 22:10:40 +00002703 if (timer_pending(&dev->stat_monitor))
2704 del_timer_sync(&dev->stat_monitor);
2705
Alexander Graf92571a12018-04-04 00:19:35 +02002706 if (net->phydev)
2707 phy_stop(net->phydev);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00002708
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002709 clear_bit(EVENT_DEV_OPEN, &dev->flags);
2710 netif_stop_queue(net);
2711
2712 netif_info(dev, ifdown, dev->net,
2713 "stop stats: rx/tx %lu/%lu, errs %lu/%lu\n",
2714 net->stats.rx_packets, net->stats.tx_packets,
2715 net->stats.rx_errors, net->stats.tx_errors);
2716
2717 lan78xx_terminate_urbs(dev);
2718
2719 usb_kill_urb(dev->urb_intr);
2720
2721 skb_queue_purge(&dev->rxq_pause);
2722
2723 /* deferred work (task, timer, softirq) must also stop.
2724 * can't flush_scheduled_work() until we drop rtnl (later),
2725 * else workers could deadlock; so make workers a NOP.
2726 */
2727 dev->flags = 0;
2728 cancel_delayed_work_sync(&dev->wq);
2729 tasklet_kill(&dev->bh);
2730
2731 usb_autopm_put_interface(dev->intf);
2732
2733 return 0;
2734}
2735
2736static int lan78xx_linearize(struct sk_buff *skb)
2737{
2738 return skb_linearize(skb);
2739}
2740
2741static struct sk_buff *lan78xx_tx_prep(struct lan78xx_net *dev,
2742 struct sk_buff *skb, gfp_t flags)
2743{
2744 u32 tx_cmd_a, tx_cmd_b;
2745
Eric Dumazetd4ca7352017-04-19 09:59:24 -07002746 if (skb_cow_head(skb, TX_OVERHEAD)) {
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002747 dev_kfree_skb_any(skb);
Eric Dumazetd4ca7352017-04-19 09:59:24 -07002748 return NULL;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002749 }
2750
2751 if (lan78xx_linearize(skb) < 0)
2752 return NULL;
2753
2754 tx_cmd_a = (u32)(skb->len & TX_CMD_A_LEN_MASK_) | TX_CMD_A_FCS_;
2755
2756 if (skb->ip_summed == CHECKSUM_PARTIAL)
2757 tx_cmd_a |= TX_CMD_A_IPE_ | TX_CMD_A_TPE_;
2758
2759 tx_cmd_b = 0;
2760 if (skb_is_gso(skb)) {
2761 u16 mss = max(skb_shinfo(skb)->gso_size, TX_CMD_B_MSS_MIN_);
2762
2763 tx_cmd_b = (mss << TX_CMD_B_MSS_SHIFT_) & TX_CMD_B_MSS_MASK_;
2764
2765 tx_cmd_a |= TX_CMD_A_LSO_;
2766 }
2767
2768 if (skb_vlan_tag_present(skb)) {
2769 tx_cmd_a |= TX_CMD_A_IVTG_;
2770 tx_cmd_b |= skb_vlan_tag_get(skb) & TX_CMD_B_VTAG_MASK_;
2771 }
2772
2773 skb_push(skb, 4);
2774 cpu_to_le32s(&tx_cmd_b);
2775 memcpy(skb->data, &tx_cmd_b, 4);
2776
2777 skb_push(skb, 4);
2778 cpu_to_le32s(&tx_cmd_a);
2779 memcpy(skb->data, &tx_cmd_a, 4);
2780
2781 return skb;
2782}
2783
2784static enum skb_state defer_bh(struct lan78xx_net *dev, struct sk_buff *skb,
2785 struct sk_buff_head *list, enum skb_state state)
2786{
2787 unsigned long flags;
2788 enum skb_state old_state;
2789 struct skb_data *entry = (struct skb_data *)skb->cb;
2790
2791 spin_lock_irqsave(&list->lock, flags);
2792 old_state = entry->state;
2793 entry->state = state;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002794
2795 __skb_unlink(skb, list);
2796 spin_unlock(&list->lock);
2797 spin_lock(&dev->done.lock);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002798
2799 __skb_queue_tail(&dev->done, skb);
2800 if (skb_queue_len(&dev->done) == 1)
2801 tasklet_schedule(&dev->bh);
2802 spin_unlock_irqrestore(&dev->done.lock, flags);
2803
2804 return old_state;
2805}
2806
2807static void tx_complete(struct urb *urb)
2808{
2809 struct sk_buff *skb = (struct sk_buff *)urb->context;
2810 struct skb_data *entry = (struct skb_data *)skb->cb;
2811 struct lan78xx_net *dev = entry->dev;
2812
2813 if (urb->status == 0) {
Woojung Huh74d79a22016-04-25 22:22:32 +00002814 dev->net->stats.tx_packets += entry->num_of_packet;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002815 dev->net->stats.tx_bytes += entry->length;
2816 } else {
2817 dev->net->stats.tx_errors++;
2818
2819 switch (urb->status) {
2820 case -EPIPE:
2821 lan78xx_defer_kevent(dev, EVENT_TX_HALT);
2822 break;
2823
2824 /* software-driven interface shutdown */
2825 case -ECONNRESET:
2826 case -ESHUTDOWN:
2827 break;
2828
2829 case -EPROTO:
2830 case -ETIME:
2831 case -EILSEQ:
2832 netif_stop_queue(dev->net);
2833 break;
2834 default:
2835 netif_dbg(dev, tx_err, dev->net,
2836 "tx err %d\n", entry->urb->status);
2837 break;
2838 }
2839 }
2840
2841 usb_autopm_put_interface_async(dev->intf);
2842
Woojung.Huh@microchip.com81c38e82015-08-11 15:21:41 +00002843 defer_bh(dev, skb, &dev->txq, tx_done);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002844}
2845
2846static void lan78xx_queue_skb(struct sk_buff_head *list,
2847 struct sk_buff *newsk, enum skb_state state)
2848{
2849 struct skb_data *entry = (struct skb_data *)newsk->cb;
2850
2851 __skb_queue_tail(list, newsk);
2852 entry->state = state;
2853}
2854
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002855static netdev_tx_t
2856lan78xx_start_xmit(struct sk_buff *skb, struct net_device *net)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002857{
2858 struct lan78xx_net *dev = netdev_priv(net);
Woojung.Huh@microchip.com81c38e82015-08-11 15:21:41 +00002859 struct sk_buff *skb2 = NULL;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002860
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002861 if (skb) {
Woojung.Huh@microchip.com81c38e82015-08-11 15:21:41 +00002862 skb_tx_timestamp(skb);
2863 skb2 = lan78xx_tx_prep(dev, skb, GFP_ATOMIC);
2864 }
2865
2866 if (skb2) {
2867 skb_queue_tail(&dev->txq_pend, skb2);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002868
Woojung.Huh@microchip.com4b2a4a92016-01-27 22:57:54 +00002869 /* throttle TX patch at slower than SUPER SPEED USB */
2870 if ((dev->udev->speed < USB_SPEED_SUPER) &&
2871 (skb_queue_len(&dev->txq_pend) > 10))
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002872 netif_stop_queue(net);
2873 } else {
2874 netif_dbg(dev, tx_err, dev->net,
2875 "lan78xx_tx_prep return NULL\n");
2876 dev->net->stats.tx_errors++;
2877 dev->net->stats.tx_dropped++;
2878 }
2879
2880 tasklet_schedule(&dev->bh);
2881
2882 return NETDEV_TX_OK;
2883}
2884
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08002885static int
2886lan78xx_get_endpoints(struct lan78xx_net *dev, struct usb_interface *intf)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002887{
2888 int tmp;
2889 struct usb_host_interface *alt = NULL;
2890 struct usb_host_endpoint *in = NULL, *out = NULL;
2891 struct usb_host_endpoint *status = NULL;
2892
2893 for (tmp = 0; tmp < intf->num_altsetting; tmp++) {
2894 unsigned ep;
2895
2896 in = NULL;
2897 out = NULL;
2898 status = NULL;
2899 alt = intf->altsetting + tmp;
2900
2901 for (ep = 0; ep < alt->desc.bNumEndpoints; ep++) {
2902 struct usb_host_endpoint *e;
2903 int intr = 0;
2904
2905 e = alt->endpoint + ep;
2906 switch (e->desc.bmAttributes) {
2907 case USB_ENDPOINT_XFER_INT:
2908 if (!usb_endpoint_dir_in(&e->desc))
2909 continue;
2910 intr = 1;
2911 /* FALLTHROUGH */
2912 case USB_ENDPOINT_XFER_BULK:
2913 break;
2914 default:
2915 continue;
2916 }
2917 if (usb_endpoint_dir_in(&e->desc)) {
2918 if (!intr && !in)
2919 in = e;
2920 else if (intr && !status)
2921 status = e;
2922 } else {
2923 if (!out)
2924 out = e;
2925 }
2926 }
2927 if (in && out)
2928 break;
2929 }
2930 if (!alt || !in || !out)
2931 return -EINVAL;
2932
2933 dev->pipe_in = usb_rcvbulkpipe(dev->udev,
2934 in->desc.bEndpointAddress &
2935 USB_ENDPOINT_NUMBER_MASK);
2936 dev->pipe_out = usb_sndbulkpipe(dev->udev,
2937 out->desc.bEndpointAddress &
2938 USB_ENDPOINT_NUMBER_MASK);
2939 dev->ep_intr = status;
2940
2941 return 0;
2942}
2943
2944static int lan78xx_bind(struct lan78xx_net *dev, struct usb_interface *intf)
2945{
2946 struct lan78xx_priv *pdata = NULL;
2947 int ret;
2948 int i;
2949
2950 ret = lan78xx_get_endpoints(dev, intf);
2951
2952 dev->data[0] = (unsigned long)kzalloc(sizeof(*pdata), GFP_KERNEL);
2953
2954 pdata = (struct lan78xx_priv *)(dev->data[0]);
2955 if (!pdata) {
2956 netdev_warn(dev->net, "Unable to allocate lan78xx_priv");
2957 return -ENOMEM;
2958 }
2959
2960 pdata->dev = dev;
2961
2962 spin_lock_init(&pdata->rfe_ctl_lock);
2963 mutex_init(&pdata->dataport_mutex);
2964
2965 INIT_WORK(&pdata->set_multicast, lan78xx_deferred_multicast_write);
2966
2967 for (i = 0; i < DP_SEL_VHF_VLAN_LEN; i++)
2968 pdata->vlan_table[i] = 0;
2969
2970 INIT_WORK(&pdata->set_vlan, lan78xx_deferred_vlan_write);
2971
2972 dev->net->features = 0;
2973
2974 if (DEFAULT_TX_CSUM_ENABLE)
2975 dev->net->features |= NETIF_F_HW_CSUM;
2976
2977 if (DEFAULT_RX_CSUM_ENABLE)
2978 dev->net->features |= NETIF_F_RXCSUM;
2979
2980 if (DEFAULT_TSO_CSUM_ENABLE)
2981 dev->net->features |= NETIF_F_TSO | NETIF_F_TSO6 | NETIF_F_SG;
2982
2983 dev->net->hw_features = dev->net->features;
2984
Woojung Huhcc89c322016-11-01 20:02:00 +00002985 ret = lan78xx_setup_irq_domain(dev);
2986 if (ret < 0) {
2987 netdev_warn(dev->net,
2988 "lan78xx_setup_irq_domain() failed : %d", ret);
Raghuram Chary J2d2d99e2018-03-27 14:51:16 +05302989 goto out1;
Woojung Huhcc89c322016-11-01 20:02:00 +00002990 }
2991
Nisar Sayed0573f942017-08-01 10:24:33 +00002992 dev->net->hard_header_len += TX_OVERHEAD;
2993 dev->hard_mtu = dev->net->mtu + dev->net->hard_header_len;
2994
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00002995 /* Init all registers */
2996 ret = lan78xx_reset(dev);
Raghuram Chary J2d2d99e2018-03-27 14:51:16 +05302997 if (ret) {
2998 netdev_warn(dev->net, "Registers INIT FAILED....");
2999 goto out2;
3000 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003001
Nisar Sayedfb52c3b2017-08-01 10:24:17 +00003002 ret = lan78xx_mdio_init(dev);
Raghuram Chary J2d2d99e2018-03-27 14:51:16 +05303003 if (ret) {
3004 netdev_warn(dev->net, "MDIO INIT FAILED.....");
3005 goto out2;
3006 }
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00003007
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003008 dev->net->flags |= IFF_MULTICAST;
3009
3010 pdata->wol = WAKE_MAGIC;
3011
Nisar Sayedfb52c3b2017-08-01 10:24:17 +00003012 return ret;
Raghuram Chary J2d2d99e2018-03-27 14:51:16 +05303013
3014out2:
3015 lan78xx_remove_irq_domain(dev);
3016
3017out1:
3018 netdev_warn(dev->net, "Bind routine FAILED");
3019 cancel_work_sync(&pdata->set_multicast);
3020 cancel_work_sync(&pdata->set_vlan);
3021 kfree(pdata);
3022 return ret;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003023}
3024
3025static void lan78xx_unbind(struct lan78xx_net *dev, struct usb_interface *intf)
3026{
3027 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
3028
Woojung Huhcc89c322016-11-01 20:02:00 +00003029 lan78xx_remove_irq_domain(dev);
3030
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00003031 lan78xx_remove_mdio(dev);
3032
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003033 if (pdata) {
Raghuram Chary J2d2d99e2018-03-27 14:51:16 +05303034 cancel_work_sync(&pdata->set_multicast);
3035 cancel_work_sync(&pdata->set_vlan);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003036 netif_dbg(dev, ifdown, dev->net, "free pdata");
3037 kfree(pdata);
3038 pdata = NULL;
3039 dev->data[0] = 0;
3040 }
3041}
3042
3043static void lan78xx_rx_csum_offload(struct lan78xx_net *dev,
3044 struct sk_buff *skb,
3045 u32 rx_cmd_a, u32 rx_cmd_b)
3046{
3047 if (!(dev->net->features & NETIF_F_RXCSUM) ||
3048 unlikely(rx_cmd_a & RX_CMD_A_ICSM_)) {
3049 skb->ip_summed = CHECKSUM_NONE;
3050 } else {
3051 skb->csum = ntohs((u16)(rx_cmd_b >> RX_CMD_B_CSUM_SHIFT_));
3052 skb->ip_summed = CHECKSUM_COMPLETE;
3053 }
3054}
3055
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08003056static void lan78xx_skb_return(struct lan78xx_net *dev, struct sk_buff *skb)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003057{
3058 int status;
3059
3060 if (test_bit(EVENT_RX_PAUSED, &dev->flags)) {
3061 skb_queue_tail(&dev->rxq_pause, skb);
3062 return;
3063 }
3064
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003065 dev->net->stats.rx_packets++;
3066 dev->net->stats.rx_bytes += skb->len;
3067
Woojung Huh74d79a22016-04-25 22:22:32 +00003068 skb->protocol = eth_type_trans(skb, dev->net);
3069
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003070 netif_dbg(dev, rx_status, dev->net, "< rx, len %zu, type 0x%x\n",
3071 skb->len + sizeof(struct ethhdr), skb->protocol);
3072 memset(skb->cb, 0, sizeof(struct skb_data));
3073
3074 if (skb_defer_rx_timestamp(skb))
3075 return;
3076
3077 status = netif_rx(skb);
3078 if (status != NET_RX_SUCCESS)
3079 netif_dbg(dev, rx_err, dev->net,
3080 "netif_rx status %d\n", status);
3081}
3082
3083static int lan78xx_rx(struct lan78xx_net *dev, struct sk_buff *skb)
3084{
3085 if (skb->len < dev->net->hard_header_len)
3086 return 0;
3087
3088 while (skb->len > 0) {
3089 u32 rx_cmd_a, rx_cmd_b, align_count, size;
3090 u16 rx_cmd_c;
3091 struct sk_buff *skb2;
3092 unsigned char *packet;
3093
3094 memcpy(&rx_cmd_a, skb->data, sizeof(rx_cmd_a));
3095 le32_to_cpus(&rx_cmd_a);
3096 skb_pull(skb, sizeof(rx_cmd_a));
3097
3098 memcpy(&rx_cmd_b, skb->data, sizeof(rx_cmd_b));
3099 le32_to_cpus(&rx_cmd_b);
3100 skb_pull(skb, sizeof(rx_cmd_b));
3101
3102 memcpy(&rx_cmd_c, skb->data, sizeof(rx_cmd_c));
3103 le16_to_cpus(&rx_cmd_c);
3104 skb_pull(skb, sizeof(rx_cmd_c));
3105
3106 packet = skb->data;
3107
3108 /* get the packet length */
3109 size = (rx_cmd_a & RX_CMD_A_LEN_MASK_);
3110 align_count = (4 - ((size + RXW_PADDING) % 4)) % 4;
3111
3112 if (unlikely(rx_cmd_a & RX_CMD_A_RED_)) {
3113 netif_dbg(dev, rx_err, dev->net,
3114 "Error rx_cmd_a=0x%08x", rx_cmd_a);
3115 } else {
3116 /* last frame in this batch */
3117 if (skb->len == size) {
3118 lan78xx_rx_csum_offload(dev, skb,
3119 rx_cmd_a, rx_cmd_b);
3120
3121 skb_trim(skb, skb->len - 4); /* remove fcs */
3122 skb->truesize = size + sizeof(struct sk_buff);
3123
3124 return 1;
3125 }
3126
3127 skb2 = skb_clone(skb, GFP_ATOMIC);
3128 if (unlikely(!skb2)) {
3129 netdev_warn(dev->net, "Error allocating skb");
3130 return 0;
3131 }
3132
3133 skb2->len = size;
3134 skb2->data = packet;
3135 skb_set_tail_pointer(skb2, size);
3136
3137 lan78xx_rx_csum_offload(dev, skb2, rx_cmd_a, rx_cmd_b);
3138
3139 skb_trim(skb2, skb2->len - 4); /* remove fcs */
3140 skb2->truesize = size + sizeof(struct sk_buff);
3141
3142 lan78xx_skb_return(dev, skb2);
3143 }
3144
3145 skb_pull(skb, size);
3146
3147 /* padding bytes before the next frame starts */
3148 if (skb->len)
3149 skb_pull(skb, align_count);
3150 }
3151
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003152 return 1;
3153}
3154
3155static inline void rx_process(struct lan78xx_net *dev, struct sk_buff *skb)
3156{
3157 if (!lan78xx_rx(dev, skb)) {
3158 dev->net->stats.rx_errors++;
3159 goto done;
3160 }
3161
3162 if (skb->len) {
3163 lan78xx_skb_return(dev, skb);
3164 return;
3165 }
3166
3167 netif_dbg(dev, rx_err, dev->net, "drop\n");
3168 dev->net->stats.rx_errors++;
3169done:
3170 skb_queue_tail(&dev->done, skb);
3171}
3172
3173static void rx_complete(struct urb *urb);
3174
3175static int rx_submit(struct lan78xx_net *dev, struct urb *urb, gfp_t flags)
3176{
3177 struct sk_buff *skb;
3178 struct skb_data *entry;
3179 unsigned long lockflags;
3180 size_t size = dev->rx_urb_size;
3181 int ret = 0;
3182
3183 skb = netdev_alloc_skb_ip_align(dev->net, size);
3184 if (!skb) {
3185 usb_free_urb(urb);
3186 return -ENOMEM;
3187 }
3188
3189 entry = (struct skb_data *)skb->cb;
3190 entry->urb = urb;
3191 entry->dev = dev;
3192 entry->length = 0;
3193
3194 usb_fill_bulk_urb(urb, dev->udev, dev->pipe_in,
3195 skb->data, size, rx_complete, skb);
3196
3197 spin_lock_irqsave(&dev->rxq.lock, lockflags);
3198
3199 if (netif_device_present(dev->net) &&
3200 netif_running(dev->net) &&
3201 !test_bit(EVENT_RX_HALT, &dev->flags) &&
3202 !test_bit(EVENT_DEV_ASLEEP, &dev->flags)) {
3203 ret = usb_submit_urb(urb, GFP_ATOMIC);
3204 switch (ret) {
3205 case 0:
3206 lan78xx_queue_skb(&dev->rxq, skb, rx_start);
3207 break;
3208 case -EPIPE:
3209 lan78xx_defer_kevent(dev, EVENT_RX_HALT);
3210 break;
3211 case -ENODEV:
3212 netif_dbg(dev, ifdown, dev->net, "device gone\n");
3213 netif_device_detach(dev->net);
3214 break;
3215 case -EHOSTUNREACH:
3216 ret = -ENOLINK;
3217 break;
3218 default:
3219 netif_dbg(dev, rx_err, dev->net,
3220 "rx submit, %d\n", ret);
3221 tasklet_schedule(&dev->bh);
3222 }
3223 } else {
3224 netif_dbg(dev, ifdown, dev->net, "rx: stopped\n");
3225 ret = -ENOLINK;
3226 }
3227 spin_unlock_irqrestore(&dev->rxq.lock, lockflags);
3228 if (ret) {
3229 dev_kfree_skb_any(skb);
3230 usb_free_urb(urb);
3231 }
3232 return ret;
3233}
3234
3235static void rx_complete(struct urb *urb)
3236{
3237 struct sk_buff *skb = (struct sk_buff *)urb->context;
3238 struct skb_data *entry = (struct skb_data *)skb->cb;
3239 struct lan78xx_net *dev = entry->dev;
3240 int urb_status = urb->status;
3241 enum skb_state state;
3242
3243 skb_put(skb, urb->actual_length);
3244 state = rx_done;
3245 entry->urb = NULL;
3246
3247 switch (urb_status) {
3248 case 0:
3249 if (skb->len < dev->net->hard_header_len) {
3250 state = rx_cleanup;
3251 dev->net->stats.rx_errors++;
3252 dev->net->stats.rx_length_errors++;
3253 netif_dbg(dev, rx_err, dev->net,
3254 "rx length %d\n", skb->len);
3255 }
3256 usb_mark_last_busy(dev->udev);
3257 break;
3258 case -EPIPE:
3259 dev->net->stats.rx_errors++;
3260 lan78xx_defer_kevent(dev, EVENT_RX_HALT);
3261 /* FALLTHROUGH */
3262 case -ECONNRESET: /* async unlink */
3263 case -ESHUTDOWN: /* hardware gone */
3264 netif_dbg(dev, ifdown, dev->net,
3265 "rx shutdown, code %d\n", urb_status);
3266 state = rx_cleanup;
3267 entry->urb = urb;
3268 urb = NULL;
3269 break;
3270 case -EPROTO:
3271 case -ETIME:
3272 case -EILSEQ:
3273 dev->net->stats.rx_errors++;
3274 state = rx_cleanup;
3275 entry->urb = urb;
3276 urb = NULL;
3277 break;
3278
3279 /* data overrun ... flush fifo? */
3280 case -EOVERFLOW:
3281 dev->net->stats.rx_over_errors++;
3282 /* FALLTHROUGH */
3283
3284 default:
3285 state = rx_cleanup;
3286 dev->net->stats.rx_errors++;
3287 netif_dbg(dev, rx_err, dev->net, "rx status %d\n", urb_status);
3288 break;
3289 }
3290
3291 state = defer_bh(dev, skb, &dev->rxq, state);
3292
3293 if (urb) {
3294 if (netif_running(dev->net) &&
3295 !test_bit(EVENT_RX_HALT, &dev->flags) &&
3296 state != unlink_start) {
3297 rx_submit(dev, urb, GFP_ATOMIC);
3298 return;
3299 }
3300 usb_free_urb(urb);
3301 }
3302 netif_dbg(dev, rx_err, dev->net, "no read resubmitted\n");
3303}
3304
3305static void lan78xx_tx_bh(struct lan78xx_net *dev)
3306{
3307 int length;
3308 struct urb *urb = NULL;
3309 struct skb_data *entry;
3310 unsigned long flags;
3311 struct sk_buff_head *tqp = &dev->txq_pend;
3312 struct sk_buff *skb, *skb2;
3313 int ret;
3314 int count, pos;
3315 int skb_totallen, pkt_cnt;
3316
3317 skb_totallen = 0;
3318 pkt_cnt = 0;
Woojung Huh74d79a22016-04-25 22:22:32 +00003319 count = 0;
3320 length = 0;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003321 for (skb = tqp->next; pkt_cnt < tqp->qlen; skb = skb->next) {
3322 if (skb_is_gso(skb)) {
3323 if (pkt_cnt) {
3324 /* handle previous packets first */
3325 break;
3326 }
Woojung Huh74d79a22016-04-25 22:22:32 +00003327 count = 1;
3328 length = skb->len - TX_OVERHEAD;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003329 skb2 = skb_dequeue(tqp);
3330 goto gso_skb;
3331 }
3332
3333 if ((skb_totallen + skb->len) > MAX_SINGLE_PACKET_SIZE)
3334 break;
3335 skb_totallen = skb->len + roundup(skb_totallen, sizeof(u32));
3336 pkt_cnt++;
3337 }
3338
3339 /* copy to a single skb */
3340 skb = alloc_skb(skb_totallen, GFP_ATOMIC);
3341 if (!skb)
3342 goto drop;
3343
3344 skb_put(skb, skb_totallen);
3345
3346 for (count = pos = 0; count < pkt_cnt; count++) {
3347 skb2 = skb_dequeue(tqp);
3348 if (skb2) {
Woojung Huh74d79a22016-04-25 22:22:32 +00003349 length += (skb2->len - TX_OVERHEAD);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003350 memcpy(skb->data + pos, skb2->data, skb2->len);
3351 pos += roundup(skb2->len, sizeof(u32));
3352 dev_kfree_skb(skb2);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003353 }
3354 }
3355
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003356gso_skb:
3357 urb = usb_alloc_urb(0, GFP_ATOMIC);
Wolfram Sangd7c4e842016-08-11 23:05:27 +02003358 if (!urb)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003359 goto drop;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003360
3361 entry = (struct skb_data *)skb->cb;
3362 entry->urb = urb;
3363 entry->dev = dev;
3364 entry->length = length;
Woojung Huh74d79a22016-04-25 22:22:32 +00003365 entry->num_of_packet = count;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003366
3367 spin_lock_irqsave(&dev->txq.lock, flags);
3368 ret = usb_autopm_get_interface_async(dev->intf);
3369 if (ret < 0) {
3370 spin_unlock_irqrestore(&dev->txq.lock, flags);
3371 goto drop;
3372 }
3373
3374 usb_fill_bulk_urb(urb, dev->udev, dev->pipe_out,
3375 skb->data, skb->len, tx_complete, skb);
3376
3377 if (length % dev->maxpacket == 0) {
3378 /* send USB_ZERO_PACKET */
3379 urb->transfer_flags |= URB_ZERO_PACKET;
3380 }
3381
3382#ifdef CONFIG_PM
3383 /* if this triggers the device is still a sleep */
3384 if (test_bit(EVENT_DEV_ASLEEP, &dev->flags)) {
3385 /* transmission will be done in resume */
3386 usb_anchor_urb(urb, &dev->deferred);
3387 /* no use to process more packets */
3388 netif_stop_queue(dev->net);
3389 usb_put_urb(urb);
3390 spin_unlock_irqrestore(&dev->txq.lock, flags);
3391 netdev_dbg(dev->net, "Delaying transmission for resumption\n");
3392 return;
3393 }
3394#endif
3395
3396 ret = usb_submit_urb(urb, GFP_ATOMIC);
3397 switch (ret) {
3398 case 0:
Florian Westphal860e9532016-05-03 16:33:13 +02003399 netif_trans_update(dev->net);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003400 lan78xx_queue_skb(&dev->txq, skb, tx_start);
3401 if (skb_queue_len(&dev->txq) >= dev->tx_qlen)
3402 netif_stop_queue(dev->net);
3403 break;
3404 case -EPIPE:
3405 netif_stop_queue(dev->net);
3406 lan78xx_defer_kevent(dev, EVENT_TX_HALT);
3407 usb_autopm_put_interface_async(dev->intf);
3408 break;
3409 default:
3410 usb_autopm_put_interface_async(dev->intf);
3411 netif_dbg(dev, tx_err, dev->net,
3412 "tx: submit urb err %d\n", ret);
3413 break;
3414 }
3415
3416 spin_unlock_irqrestore(&dev->txq.lock, flags);
3417
3418 if (ret) {
3419 netif_dbg(dev, tx_err, dev->net, "drop, code %d\n", ret);
3420drop:
3421 dev->net->stats.tx_dropped++;
3422 if (skb)
3423 dev_kfree_skb_any(skb);
3424 usb_free_urb(urb);
3425 } else
3426 netif_dbg(dev, tx_queued, dev->net,
3427 "> tx, len %d, type 0x%x\n", length, skb->protocol);
3428}
3429
3430static void lan78xx_rx_bh(struct lan78xx_net *dev)
3431{
3432 struct urb *urb;
3433 int i;
3434
3435 if (skb_queue_len(&dev->rxq) < dev->rx_qlen) {
3436 for (i = 0; i < 10; i++) {
3437 if (skb_queue_len(&dev->rxq) >= dev->rx_qlen)
3438 break;
3439 urb = usb_alloc_urb(0, GFP_ATOMIC);
3440 if (urb)
3441 if (rx_submit(dev, urb, GFP_ATOMIC) == -ENOLINK)
3442 return;
3443 }
3444
3445 if (skb_queue_len(&dev->rxq) < dev->rx_qlen)
3446 tasklet_schedule(&dev->bh);
3447 }
3448 if (skb_queue_len(&dev->txq) < dev->tx_qlen)
3449 netif_wake_queue(dev->net);
3450}
3451
3452static void lan78xx_bh(unsigned long param)
3453{
3454 struct lan78xx_net *dev = (struct lan78xx_net *)param;
3455 struct sk_buff *skb;
3456 struct skb_data *entry;
3457
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003458 while ((skb = skb_dequeue(&dev->done))) {
3459 entry = (struct skb_data *)(skb->cb);
3460 switch (entry->state) {
3461 case rx_done:
3462 entry->state = rx_cleanup;
3463 rx_process(dev, skb);
3464 continue;
3465 case tx_done:
3466 usb_free_urb(entry->urb);
3467 dev_kfree_skb(skb);
3468 continue;
3469 case rx_cleanup:
3470 usb_free_urb(entry->urb);
3471 dev_kfree_skb(skb);
3472 continue;
3473 default:
3474 netdev_dbg(dev->net, "skb state %d\n", entry->state);
3475 return;
3476 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003477 }
3478
3479 if (netif_device_present(dev->net) && netif_running(dev->net)) {
Woojung Huh20ff5562016-03-16 22:10:40 +00003480 /* reset update timer delta */
3481 if (timer_pending(&dev->stat_monitor) && (dev->delta != 1)) {
3482 dev->delta = 1;
3483 mod_timer(&dev->stat_monitor,
3484 jiffies + STAT_UPDATE_TIMER);
3485 }
3486
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003487 if (!skb_queue_empty(&dev->txq_pend))
3488 lan78xx_tx_bh(dev);
3489
3490 if (!timer_pending(&dev->delay) &&
3491 !test_bit(EVENT_RX_HALT, &dev->flags))
3492 lan78xx_rx_bh(dev);
3493 }
3494}
3495
3496static void lan78xx_delayedwork(struct work_struct *work)
3497{
3498 int status;
3499 struct lan78xx_net *dev;
3500
3501 dev = container_of(work, struct lan78xx_net, wq.work);
3502
3503 if (test_bit(EVENT_TX_HALT, &dev->flags)) {
3504 unlink_urbs(dev, &dev->txq);
3505 status = usb_autopm_get_interface(dev->intf);
3506 if (status < 0)
3507 goto fail_pipe;
3508 status = usb_clear_halt(dev->udev, dev->pipe_out);
3509 usb_autopm_put_interface(dev->intf);
3510 if (status < 0 &&
3511 status != -EPIPE &&
3512 status != -ESHUTDOWN) {
3513 if (netif_msg_tx_err(dev))
3514fail_pipe:
3515 netdev_err(dev->net,
3516 "can't clear tx halt, status %d\n",
3517 status);
3518 } else {
3519 clear_bit(EVENT_TX_HALT, &dev->flags);
3520 if (status != -ESHUTDOWN)
3521 netif_wake_queue(dev->net);
3522 }
3523 }
3524 if (test_bit(EVENT_RX_HALT, &dev->flags)) {
3525 unlink_urbs(dev, &dev->rxq);
3526 status = usb_autopm_get_interface(dev->intf);
3527 if (status < 0)
3528 goto fail_halt;
3529 status = usb_clear_halt(dev->udev, dev->pipe_in);
3530 usb_autopm_put_interface(dev->intf);
3531 if (status < 0 &&
3532 status != -EPIPE &&
3533 status != -ESHUTDOWN) {
3534 if (netif_msg_rx_err(dev))
3535fail_halt:
3536 netdev_err(dev->net,
3537 "can't clear rx halt, status %d\n",
3538 status);
3539 } else {
3540 clear_bit(EVENT_RX_HALT, &dev->flags);
3541 tasklet_schedule(&dev->bh);
3542 }
3543 }
3544
3545 if (test_bit(EVENT_LINK_RESET, &dev->flags)) {
3546 int ret = 0;
3547
3548 clear_bit(EVENT_LINK_RESET, &dev->flags);
3549 status = usb_autopm_get_interface(dev->intf);
3550 if (status < 0)
3551 goto skip_reset;
3552 if (lan78xx_link_reset(dev) < 0) {
3553 usb_autopm_put_interface(dev->intf);
3554skip_reset:
3555 netdev_info(dev->net, "link reset failed (%d)\n",
3556 ret);
3557 } else {
3558 usb_autopm_put_interface(dev->intf);
3559 }
3560 }
Woojung Huh20ff5562016-03-16 22:10:40 +00003561
3562 if (test_bit(EVENT_STAT_UPDATE, &dev->flags)) {
3563 lan78xx_update_stats(dev);
3564
3565 clear_bit(EVENT_STAT_UPDATE, &dev->flags);
3566
3567 mod_timer(&dev->stat_monitor,
3568 jiffies + (STAT_UPDATE_TIMER * dev->delta));
3569
3570 dev->delta = min((dev->delta * 2), 50);
3571 }
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003572}
3573
3574static void intr_complete(struct urb *urb)
3575{
3576 struct lan78xx_net *dev = urb->context;
3577 int status = urb->status;
3578
3579 switch (status) {
3580 /* success */
3581 case 0:
3582 lan78xx_status(dev, urb);
3583 break;
3584
3585 /* software-driven interface shutdown */
3586 case -ENOENT: /* urb killed */
3587 case -ESHUTDOWN: /* hardware gone */
3588 netif_dbg(dev, ifdown, dev->net,
3589 "intr shutdown, code %d\n", status);
3590 return;
3591
3592 /* NOTE: not throttling like RX/TX, since this endpoint
3593 * already polls infrequently
3594 */
3595 default:
3596 netdev_dbg(dev->net, "intr status %d\n", status);
3597 break;
3598 }
3599
3600 if (!netif_running(dev->net))
3601 return;
3602
3603 memset(urb->transfer_buffer, 0, urb->transfer_buffer_length);
3604 status = usb_submit_urb(urb, GFP_ATOMIC);
3605 if (status != 0)
3606 netif_err(dev, timer, dev->net,
3607 "intr resubmit --> %d\n", status);
3608}
3609
3610static void lan78xx_disconnect(struct usb_interface *intf)
3611{
3612 struct lan78xx_net *dev;
3613 struct usb_device *udev;
3614 struct net_device *net;
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05303615 struct phy_device *phydev;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003616
3617 dev = usb_get_intfdata(intf);
3618 usb_set_intfdata(intf, NULL);
3619 if (!dev)
3620 return;
3621
3622 udev = interface_to_usbdev(intf);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003623 net = dev->net;
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05303624 phydev = net->phydev;
Alexander Graf92571a12018-04-04 00:19:35 +02003625
3626 phy_unregister_fixup_for_uid(PHY_KSZ9031RNX, 0xfffffff0);
3627 phy_unregister_fixup_for_uid(PHY_LAN8835, 0xfffffff0);
3628
3629 phy_disconnect(net->phydev);
3630
Raghuram Chary J89b36fb2018-04-28 11:33:14 +05303631 if (phy_is_pseudo_fixed_link(phydev))
3632 fixed_phy_unregister(phydev);
3633
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003634 unregister_netdev(net);
3635
3636 cancel_delayed_work_sync(&dev->wq);
3637
3638 usb_scuttle_anchored_urbs(&dev->deferred);
3639
3640 lan78xx_unbind(dev, intf);
3641
3642 usb_kill_urb(dev->urb_intr);
3643 usb_free_urb(dev->urb_intr);
3644
3645 free_netdev(net);
3646 usb_put_dev(udev);
3647}
3648
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08003649static void lan78xx_tx_timeout(struct net_device *net)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003650{
3651 struct lan78xx_net *dev = netdev_priv(net);
3652
3653 unlink_urbs(dev, &dev->txq);
3654 tasklet_schedule(&dev->bh);
3655}
3656
3657static const struct net_device_ops lan78xx_netdev_ops = {
3658 .ndo_open = lan78xx_open,
3659 .ndo_stop = lan78xx_stop,
3660 .ndo_start_xmit = lan78xx_start_xmit,
3661 .ndo_tx_timeout = lan78xx_tx_timeout,
3662 .ndo_change_mtu = lan78xx_change_mtu,
3663 .ndo_set_mac_address = lan78xx_set_mac_addr,
3664 .ndo_validate_addr = eth_validate_addr,
3665 .ndo_do_ioctl = lan78xx_ioctl,
3666 .ndo_set_rx_mode = lan78xx_set_multicast,
3667 .ndo_set_features = lan78xx_set_features,
3668 .ndo_vlan_rx_add_vid = lan78xx_vlan_rx_add_vid,
3669 .ndo_vlan_rx_kill_vid = lan78xx_vlan_rx_kill_vid,
3670};
3671
Kees Cookd28bb962017-10-16 17:29:32 -07003672static void lan78xx_stat_monitor(struct timer_list *t)
Woojung Huh20ff5562016-03-16 22:10:40 +00003673{
Kees Cookd28bb962017-10-16 17:29:32 -07003674 struct lan78xx_net *dev = from_timer(dev, t, stat_monitor);
Woojung Huh20ff5562016-03-16 22:10:40 +00003675
3676 lan78xx_defer_kevent(dev, EVENT_STAT_UPDATE);
3677}
3678
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003679static int lan78xx_probe(struct usb_interface *intf,
3680 const struct usb_device_id *id)
3681{
3682 struct lan78xx_net *dev;
3683 struct net_device *netdev;
3684 struct usb_device *udev;
3685 int ret;
3686 unsigned maxp;
3687 unsigned period;
3688 u8 *buf = NULL;
3689
3690 udev = interface_to_usbdev(intf);
3691 udev = usb_get_dev(udev);
3692
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003693 netdev = alloc_etherdev(sizeof(struct lan78xx_net));
3694 if (!netdev) {
Nisar Sayedfb52c3b2017-08-01 10:24:17 +00003695 dev_err(&intf->dev, "Error: OOM\n");
3696 ret = -ENOMEM;
3697 goto out1;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003698 }
3699
3700 /* netdev_printk() needs this */
3701 SET_NETDEV_DEV(netdev, &intf->dev);
3702
3703 dev = netdev_priv(netdev);
3704 dev->udev = udev;
3705 dev->intf = intf;
3706 dev->net = netdev;
3707 dev->msg_enable = netif_msg_init(msg_level, NETIF_MSG_DRV
3708 | NETIF_MSG_PROBE | NETIF_MSG_LINK);
3709
3710 skb_queue_head_init(&dev->rxq);
3711 skb_queue_head_init(&dev->txq);
3712 skb_queue_head_init(&dev->done);
3713 skb_queue_head_init(&dev->rxq_pause);
3714 skb_queue_head_init(&dev->txq_pend);
3715 mutex_init(&dev->phy_mutex);
3716
3717 tasklet_init(&dev->bh, lan78xx_bh, (unsigned long)dev);
3718 INIT_DELAYED_WORK(&dev->wq, lan78xx_delayedwork);
3719 init_usb_anchor(&dev->deferred);
3720
3721 netdev->netdev_ops = &lan78xx_netdev_ops;
3722 netdev->watchdog_timeo = TX_TIMEOUT_JIFFIES;
3723 netdev->ethtool_ops = &lan78xx_ethtool_ops;
3724
Woojung Huh20ff5562016-03-16 22:10:40 +00003725 dev->delta = 1;
Kees Cookd28bb962017-10-16 17:29:32 -07003726 timer_setup(&dev->stat_monitor, lan78xx_stat_monitor, 0);
Woojung Huh20ff5562016-03-16 22:10:40 +00003727
3728 mutex_init(&dev->stats.access_lock);
3729
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003730 ret = lan78xx_bind(dev, intf);
3731 if (ret < 0)
3732 goto out2;
3733 strcpy(netdev->name, "eth%d");
3734
3735 if (netdev->mtu > (dev->hard_mtu - netdev->hard_header_len))
3736 netdev->mtu = dev->hard_mtu - netdev->hard_header_len;
3737
Jarod Wilsonf77f0ae2016-10-20 13:55:17 -04003738 /* MTU range: 68 - 9000 */
3739 netdev->max_mtu = MAX_SINGLE_PACKET_SIZE;
3740
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003741 dev->ep_blkin = (intf->cur_altsetting)->endpoint + 0;
3742 dev->ep_blkout = (intf->cur_altsetting)->endpoint + 1;
3743 dev->ep_intr = (intf->cur_altsetting)->endpoint + 2;
3744
3745 dev->pipe_in = usb_rcvbulkpipe(udev, BULK_IN_PIPE);
3746 dev->pipe_out = usb_sndbulkpipe(udev, BULK_OUT_PIPE);
3747
3748 dev->pipe_intr = usb_rcvintpipe(dev->udev,
3749 dev->ep_intr->desc.bEndpointAddress &
3750 USB_ENDPOINT_NUMBER_MASK);
3751 period = dev->ep_intr->desc.bInterval;
3752
3753 maxp = usb_maxpacket(dev->udev, dev->pipe_intr, 0);
3754 buf = kmalloc(maxp, GFP_KERNEL);
3755 if (buf) {
3756 dev->urb_intr = usb_alloc_urb(0, GFP_KERNEL);
3757 if (!dev->urb_intr) {
Pan Bian51920832016-12-03 19:24:48 +08003758 ret = -ENOMEM;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003759 kfree(buf);
3760 goto out3;
3761 } else {
3762 usb_fill_int_urb(dev->urb_intr, dev->udev,
3763 dev->pipe_intr, buf, maxp,
3764 intr_complete, dev, period);
3765 }
3766 }
3767
3768 dev->maxpacket = usb_maxpacket(dev->udev, dev->pipe_out, 1);
3769
3770 /* driver requires remote-wakeup capability during autosuspend. */
3771 intf->needs_remote_wakeup = 1;
3772
3773 ret = register_netdev(netdev);
3774 if (ret != 0) {
3775 netif_err(dev, probe, netdev, "couldn't register the device\n");
Nisar Sayedfb52c3b2017-08-01 10:24:17 +00003776 goto out3;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003777 }
3778
3779 usb_set_intfdata(intf, dev);
3780
3781 ret = device_set_wakeup_enable(&udev->dev, true);
3782
3783 /* Default delay of 2sec has more overhead than advantage.
3784 * Set to 10sec as default.
3785 */
3786 pm_runtime_set_autosuspend_delay(&udev->dev,
3787 DEFAULT_AUTOSUSPEND_DELAY);
3788
Alexander Graf92571a12018-04-04 00:19:35 +02003789 ret = lan78xx_phy_init(dev);
3790 if (ret < 0)
3791 goto out4;
3792
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003793 return 0;
3794
Alexander Graf92571a12018-04-04 00:19:35 +02003795out4:
3796 unregister_netdev(netdev);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003797out3:
3798 lan78xx_unbind(dev, intf);
3799out2:
3800 free_netdev(netdev);
3801out1:
3802 usb_put_dev(udev);
3803
3804 return ret;
3805}
3806
3807static u16 lan78xx_wakeframe_crc16(const u8 *buf, int len)
3808{
3809 const u16 crc16poly = 0x8005;
3810 int i;
3811 u16 bit, crc, msb;
3812 u8 data;
3813
3814 crc = 0xFFFF;
3815 for (i = 0; i < len; i++) {
3816 data = *buf++;
3817 for (bit = 0; bit < 8; bit++) {
3818 msb = crc >> 15;
3819 crc <<= 1;
3820
3821 if (msb ^ (u16)(data & 1)) {
3822 crc ^= crc16poly;
3823 crc |= (u16)0x0001U;
3824 }
3825 data >>= 1;
3826 }
3827 }
3828
3829 return crc;
3830}
3831
3832static int lan78xx_set_suspend(struct lan78xx_net *dev, u32 wol)
3833{
3834 u32 buf;
3835 int ret;
3836 int mask_index;
3837 u16 crc;
3838 u32 temp_wucsr;
3839 u32 temp_pmt_ctl;
3840 const u8 ipv4_multicast[3] = { 0x01, 0x00, 0x5E };
3841 const u8 ipv6_multicast[3] = { 0x33, 0x33 };
3842 const u8 arp_type[2] = { 0x08, 0x06 };
3843
3844 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
3845 buf &= ~MAC_TX_TXEN_;
3846 ret = lan78xx_write_reg(dev, MAC_TX, buf);
3847 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3848 buf &= ~MAC_RX_RXEN_;
3849 ret = lan78xx_write_reg(dev, MAC_RX, buf);
3850
3851 ret = lan78xx_write_reg(dev, WUCSR, 0);
3852 ret = lan78xx_write_reg(dev, WUCSR2, 0);
3853 ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
3854
3855 temp_wucsr = 0;
3856
3857 temp_pmt_ctl = 0;
3858 ret = lan78xx_read_reg(dev, PMT_CTL, &temp_pmt_ctl);
3859 temp_pmt_ctl &= ~PMT_CTL_RES_CLR_WKP_EN_;
3860 temp_pmt_ctl |= PMT_CTL_RES_CLR_WKP_STS_;
3861
3862 for (mask_index = 0; mask_index < NUM_OF_WUF_CFG; mask_index++)
3863 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index), 0);
3864
3865 mask_index = 0;
3866 if (wol & WAKE_PHY) {
3867 temp_pmt_ctl |= PMT_CTL_PHY_WAKE_EN_;
3868
3869 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3870 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3871 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3872 }
3873 if (wol & WAKE_MAGIC) {
3874 temp_wucsr |= WUCSR_MPEN_;
3875
3876 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3877 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3878 temp_pmt_ctl |= PMT_CTL_SUS_MODE_3_;
3879 }
3880 if (wol & WAKE_BCAST) {
3881 temp_wucsr |= WUCSR_BCST_EN_;
3882
3883 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3884 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3885 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3886 }
3887 if (wol & WAKE_MCAST) {
3888 temp_wucsr |= WUCSR_WAKE_EN_;
3889
3890 /* set WUF_CFG & WUF_MASK for IPv4 Multicast */
3891 crc = lan78xx_wakeframe_crc16(ipv4_multicast, 3);
3892 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3893 WUF_CFGX_EN_ |
3894 WUF_CFGX_TYPE_MCAST_ |
3895 (0 << WUF_CFGX_OFFSET_SHIFT_) |
3896 (crc & WUF_CFGX_CRC16_MASK_));
3897
3898 ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 7);
3899 ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3900 ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3901 ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3902 mask_index++;
3903
3904 /* for IPv6 Multicast */
3905 crc = lan78xx_wakeframe_crc16(ipv6_multicast, 2);
3906 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3907 WUF_CFGX_EN_ |
3908 WUF_CFGX_TYPE_MCAST_ |
3909 (0 << WUF_CFGX_OFFSET_SHIFT_) |
3910 (crc & WUF_CFGX_CRC16_MASK_));
3911
3912 ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 3);
3913 ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3914 ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3915 ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3916 mask_index++;
3917
3918 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3919 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3920 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3921 }
3922 if (wol & WAKE_UCAST) {
3923 temp_wucsr |= WUCSR_PFDA_EN_;
3924
3925 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3926 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3927 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3928 }
3929 if (wol & WAKE_ARP) {
3930 temp_wucsr |= WUCSR_WAKE_EN_;
3931
3932 /* set WUF_CFG & WUF_MASK
3933 * for packettype (offset 12,13) = ARP (0x0806)
3934 */
3935 crc = lan78xx_wakeframe_crc16(arp_type, 2);
3936 ret = lan78xx_write_reg(dev, WUF_CFG(mask_index),
3937 WUF_CFGX_EN_ |
3938 WUF_CFGX_TYPE_ALL_ |
3939 (0 << WUF_CFGX_OFFSET_SHIFT_) |
3940 (crc & WUF_CFGX_CRC16_MASK_));
3941
3942 ret = lan78xx_write_reg(dev, WUF_MASK0(mask_index), 0x3000);
3943 ret = lan78xx_write_reg(dev, WUF_MASK1(mask_index), 0);
3944 ret = lan78xx_write_reg(dev, WUF_MASK2(mask_index), 0);
3945 ret = lan78xx_write_reg(dev, WUF_MASK3(mask_index), 0);
3946 mask_index++;
3947
3948 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3949 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3950 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3951 }
3952
3953 ret = lan78xx_write_reg(dev, WUCSR, temp_wucsr);
3954
3955 /* when multiple WOL bits are set */
3956 if (hweight_long((unsigned long)wol) > 1) {
3957 temp_pmt_ctl |= PMT_CTL_WOL_EN_;
3958 temp_pmt_ctl &= ~PMT_CTL_SUS_MODE_MASK_;
3959 temp_pmt_ctl |= PMT_CTL_SUS_MODE_0_;
3960 }
3961 ret = lan78xx_write_reg(dev, PMT_CTL, temp_pmt_ctl);
3962
3963 /* clear WUPS */
3964 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
3965 buf |= PMT_CTL_WUPS_MASK_;
3966 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
3967
3968 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
3969 buf |= MAC_RX_RXEN_;
3970 ret = lan78xx_write_reg(dev, MAC_RX, buf);
3971
3972 return 0;
3973}
3974
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08003975static int lan78xx_suspend(struct usb_interface *intf, pm_message_t message)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003976{
3977 struct lan78xx_net *dev = usb_get_intfdata(intf);
3978 struct lan78xx_priv *pdata = (struct lan78xx_priv *)(dev->data[0]);
3979 u32 buf;
3980 int ret;
3981 int event;
3982
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00003983 event = message.event;
3984
3985 if (!dev->suspend_count++) {
3986 spin_lock_irq(&dev->txq.lock);
3987 /* don't autosuspend while transmitting */
3988 if ((skb_queue_len(&dev->txq) ||
3989 skb_queue_len(&dev->txq_pend)) &&
3990 PMSG_IS_AUTO(message)) {
3991 spin_unlock_irq(&dev->txq.lock);
3992 ret = -EBUSY;
3993 goto out;
3994 } else {
3995 set_bit(EVENT_DEV_ASLEEP, &dev->flags);
3996 spin_unlock_irq(&dev->txq.lock);
3997 }
3998
3999 /* stop TX & RX */
4000 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
4001 buf &= ~MAC_TX_TXEN_;
4002 ret = lan78xx_write_reg(dev, MAC_TX, buf);
4003 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
4004 buf &= ~MAC_RX_RXEN_;
4005 ret = lan78xx_write_reg(dev, MAC_RX, buf);
4006
4007 /* empty out the rx and queues */
4008 netif_device_detach(dev->net);
4009 lan78xx_terminate_urbs(dev);
4010 usb_kill_urb(dev->urb_intr);
4011
4012 /* reattach */
4013 netif_device_attach(dev->net);
4014 }
4015
4016 if (test_bit(EVENT_DEV_ASLEEP, &dev->flags)) {
Woojung Huh20ff5562016-03-16 22:10:40 +00004017 del_timer(&dev->stat_monitor);
4018
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004019 if (PMSG_IS_AUTO(message)) {
4020 /* auto suspend (selective suspend) */
4021 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
4022 buf &= ~MAC_TX_TXEN_;
4023 ret = lan78xx_write_reg(dev, MAC_TX, buf);
4024 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
4025 buf &= ~MAC_RX_RXEN_;
4026 ret = lan78xx_write_reg(dev, MAC_RX, buf);
4027
4028 ret = lan78xx_write_reg(dev, WUCSR, 0);
4029 ret = lan78xx_write_reg(dev, WUCSR2, 0);
4030 ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
4031
4032 /* set goodframe wakeup */
4033 ret = lan78xx_read_reg(dev, WUCSR, &buf);
4034
4035 buf |= WUCSR_RFE_WAKE_EN_;
4036 buf |= WUCSR_STORE_WAKE_;
4037
4038 ret = lan78xx_write_reg(dev, WUCSR, buf);
4039
4040 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
4041
4042 buf &= ~PMT_CTL_RES_CLR_WKP_EN_;
4043 buf |= PMT_CTL_RES_CLR_WKP_STS_;
4044
4045 buf |= PMT_CTL_PHY_WAKE_EN_;
4046 buf |= PMT_CTL_WOL_EN_;
4047 buf &= ~PMT_CTL_SUS_MODE_MASK_;
4048 buf |= PMT_CTL_SUS_MODE_3_;
4049
4050 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
4051
4052 ret = lan78xx_read_reg(dev, PMT_CTL, &buf);
4053
4054 buf |= PMT_CTL_WUPS_MASK_;
4055
4056 ret = lan78xx_write_reg(dev, PMT_CTL, buf);
4057
4058 ret = lan78xx_read_reg(dev, MAC_RX, &buf);
4059 buf |= MAC_RX_RXEN_;
4060 ret = lan78xx_write_reg(dev, MAC_RX, buf);
4061 } else {
4062 lan78xx_set_suspend(dev, pdata->wol);
4063 }
4064 }
4065
Woojung.Huh@microchip.com49d28b562015-09-25 21:13:48 +00004066 ret = 0;
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004067out:
4068 return ret;
4069}
4070
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08004071static int lan78xx_resume(struct usb_interface *intf)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004072{
4073 struct lan78xx_net *dev = usb_get_intfdata(intf);
4074 struct sk_buff *skb;
4075 struct urb *res;
4076 int ret;
4077 u32 buf;
4078
Woojung Huh20ff5562016-03-16 22:10:40 +00004079 if (!timer_pending(&dev->stat_monitor)) {
4080 dev->delta = 1;
4081 mod_timer(&dev->stat_monitor,
4082 jiffies + STAT_UPDATE_TIMER);
4083 }
4084
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004085 if (!--dev->suspend_count) {
4086 /* resume interrupt URBs */
4087 if (dev->urb_intr && test_bit(EVENT_DEV_OPEN, &dev->flags))
4088 usb_submit_urb(dev->urb_intr, GFP_NOIO);
4089
4090 spin_lock_irq(&dev->txq.lock);
4091 while ((res = usb_get_from_anchor(&dev->deferred))) {
4092 skb = (struct sk_buff *)res->context;
4093 ret = usb_submit_urb(res, GFP_ATOMIC);
4094 if (ret < 0) {
4095 dev_kfree_skb_any(skb);
4096 usb_free_urb(res);
4097 usb_autopm_put_interface_async(dev->intf);
4098 } else {
Florian Westphal860e9532016-05-03 16:33:13 +02004099 netif_trans_update(dev->net);
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004100 lan78xx_queue_skb(&dev->txq, skb, tx_start);
4101 }
4102 }
4103
4104 clear_bit(EVENT_DEV_ASLEEP, &dev->flags);
4105 spin_unlock_irq(&dev->txq.lock);
4106
4107 if (test_bit(EVENT_DEV_OPEN, &dev->flags)) {
4108 if (!(skb_queue_len(&dev->txq) >= dev->tx_qlen))
4109 netif_start_queue(dev->net);
4110 tasklet_schedule(&dev->bh);
4111 }
4112 }
4113
4114 ret = lan78xx_write_reg(dev, WUCSR2, 0);
4115 ret = lan78xx_write_reg(dev, WUCSR, 0);
4116 ret = lan78xx_write_reg(dev, WK_SRC, 0xFFF1FF1FUL);
4117
4118 ret = lan78xx_write_reg(dev, WUCSR2, WUCSR2_NS_RCD_ |
4119 WUCSR2_ARP_RCD_ |
4120 WUCSR2_IPV6_TCPSYN_RCD_ |
4121 WUCSR2_IPV4_TCPSYN_RCD_);
4122
4123 ret = lan78xx_write_reg(dev, WUCSR, WUCSR_EEE_TX_WAKE_ |
4124 WUCSR_EEE_RX_WAKE_ |
4125 WUCSR_PFDA_FR_ |
4126 WUCSR_RFE_WAKE_FR_ |
4127 WUCSR_WUFR_ |
4128 WUCSR_MPR_ |
4129 WUCSR_BCST_FR_);
4130
4131 ret = lan78xx_read_reg(dev, MAC_TX, &buf);
4132 buf |= MAC_TX_TXEN_;
4133 ret = lan78xx_write_reg(dev, MAC_TX, buf);
4134
4135 return 0;
4136}
4137
Baoyou Xiee0c79ff2016-09-06 16:19:02 +08004138static int lan78xx_reset_resume(struct usb_interface *intf)
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004139{
4140 struct lan78xx_net *dev = usb_get_intfdata(intf);
4141
4142 lan78xx_reset(dev);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00004143
Alexander Graf92571a12018-04-04 00:19:35 +02004144 phy_start(dev->net->phydev);
Woojung.Huh@microchip.comce85e132015-09-16 23:40:54 +00004145
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004146 return lan78xx_resume(intf);
4147}
4148
4149static const struct usb_device_id products[] = {
4150 {
4151 /* LAN7800 USB Gigabit Ethernet Device */
4152 USB_DEVICE(LAN78XX_USB_VENDOR_ID, LAN7800_USB_PRODUCT_ID),
4153 },
4154 {
4155 /* LAN7850 USB Gigabit Ethernet Device */
4156 USB_DEVICE(LAN78XX_USB_VENDOR_ID, LAN7850_USB_PRODUCT_ID),
4157 },
Woojung Huh02dc1f32016-12-07 20:26:25 +00004158 {
4159 /* LAN7801 USB Gigabit Ethernet Device */
4160 USB_DEVICE(LAN78XX_USB_VENDOR_ID, LAN7801_USB_PRODUCT_ID),
4161 },
Woojung.Huh@microchip.com55d7de92015-07-30 19:45:21 +00004162 {},
4163};
4164MODULE_DEVICE_TABLE(usb, products);
4165
4166static struct usb_driver lan78xx_driver = {
4167 .name = DRIVER_NAME,
4168 .id_table = products,
4169 .probe = lan78xx_probe,
4170 .disconnect = lan78xx_disconnect,
4171 .suspend = lan78xx_suspend,
4172 .resume = lan78xx_resume,
4173 .reset_resume = lan78xx_reset_resume,
4174 .supports_autosuspend = 1,
4175 .disable_hub_initiated_lpm = 1,
4176};
4177
4178module_usb_driver(lan78xx_driver);
4179
4180MODULE_AUTHOR(DRIVER_AUTHOR);
4181MODULE_DESCRIPTION(DRIVER_DESC);
4182MODULE_LICENSE("GPL");