blob: b6fc374f38b57e33c1d6e997889c284ca9063099 [file] [log] [blame]
Jeeja KPe4e2d2f2015-10-07 11:31:52 +01001/*
2 * skl-topology.c - Implements Platform component ALSA controls/widget
3 * handlers.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/firmware.h>
22#include <sound/soc.h>
23#include <sound/soc-topology.h>
Shreyas NC6277e832016-08-12 12:29:51 +053024#include <uapi/sound/snd_sst_tokens.h>
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010025#include "skl-sst-dsp.h"
26#include "skl-sst-ipc.h"
27#include "skl-topology.h"
28#include "skl.h"
29#include "skl-tplg-interface.h"
Dharageswari R6c5768b2015-12-03 23:29:50 +053030#include "../common/sst-dsp.h"
31#include "../common/sst-dsp-priv.h"
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010032
Jeeja KPf7590d42015-10-07 11:31:53 +010033#define SKL_CH_FIXUP_MASK (1 << 0)
34#define SKL_RATE_FIXUP_MASK (1 << 1)
35#define SKL_FMT_FIXUP_MASK (1 << 2)
Shreyas NC6277e832016-08-12 12:29:51 +053036#define SKL_IN_DIR_BIT_MASK BIT(0)
37#define SKL_PIN_COUNT_MASK GENMASK(7, 4)
Jeeja KPf7590d42015-10-07 11:31:53 +010038
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010039/*
40 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
41 * ignore. This helpers checks if the SKL driver handles this widget type
42 */
43static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w)
44{
45 switch (w->id) {
46 case snd_soc_dapm_dai_link:
47 case snd_soc_dapm_dai_in:
48 case snd_soc_dapm_aif_in:
49 case snd_soc_dapm_aif_out:
50 case snd_soc_dapm_dai_out:
51 case snd_soc_dapm_switch:
52 return false;
53 default:
54 return true;
55 }
56}
57
58/*
59 * Each pipelines needs memory to be allocated. Check if we have free memory
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053060 * from available pool.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010061 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053062static bool skl_is_pipe_mem_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010063 struct skl_module_cfg *mconfig)
64{
65 struct skl_sst *ctx = skl->skl_sst;
66
67 if (skl->resource.mem + mconfig->pipe->memory_pages >
68 skl->resource.max_mem) {
69 dev_err(ctx->dev,
70 "%s: module_id %d instance %d\n", __func__,
71 mconfig->id.module_id,
72 mconfig->id.instance_id);
73 dev_err(ctx->dev,
74 "exceeds ppl memory available %d mem %d\n",
75 skl->resource.max_mem, skl->resource.mem);
76 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053077 } else {
78 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010079 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053080}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010081
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053082/*
83 * Add the mem to the mem pool. This is freed when pipe is deleted.
84 * Note: DSP does actual memory management we only keep track for complete
85 * pool
86 */
87static void skl_tplg_alloc_pipe_mem(struct skl *skl,
88 struct skl_module_cfg *mconfig)
89{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010090 skl->resource.mem += mconfig->pipe->memory_pages;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010091}
92
93/*
94 * Pipeline needs needs DSP CPU resources for computation, this is
95 * quantified in MCPS (Million Clocks Per Second) required for module/pipe
96 *
97 * Each pipelines needs mcps to be allocated. Check if we have mcps for this
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053098 * pipe.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010099 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530100
101static bool skl_is_pipe_mcps_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100102 struct skl_module_cfg *mconfig)
103{
104 struct skl_sst *ctx = skl->skl_sst;
105
106 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) {
107 dev_err(ctx->dev,
108 "%s: module_id %d instance %d\n", __func__,
109 mconfig->id.module_id, mconfig->id.instance_id);
110 dev_err(ctx->dev,
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530111 "exceeds ppl mcps available %d > mem %d\n",
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100112 skl->resource.max_mcps, skl->resource.mcps);
113 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530114 } else {
115 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100116 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530117}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100118
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530119static void skl_tplg_alloc_pipe_mcps(struct skl *skl,
120 struct skl_module_cfg *mconfig)
121{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100122 skl->resource.mcps += mconfig->mcps;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100123}
124
125/*
126 * Free the mcps when tearing down
127 */
128static void
129skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig)
130{
131 skl->resource.mcps -= mconfig->mcps;
132}
133
134/*
135 * Free the memory when tearing down
136 */
137static void
138skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig)
139{
140 skl->resource.mem -= mconfig->pipe->memory_pages;
141}
142
Jeeja KPf7590d42015-10-07 11:31:53 +0100143
144static void skl_dump_mconfig(struct skl_sst *ctx,
145 struct skl_module_cfg *mcfg)
146{
147 dev_dbg(ctx->dev, "Dumping config\n");
148 dev_dbg(ctx->dev, "Input Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900149 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels);
150 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq);
151 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg);
152 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth);
Jeeja KPf7590d42015-10-07 11:31:53 +0100153 dev_dbg(ctx->dev, "Output Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900154 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels);
155 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq);
156 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth);
157 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg);
Jeeja KPf7590d42015-10-07 11:31:53 +0100158}
159
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530160static void skl_tplg_update_chmap(struct skl_module_fmt *fmt, int chs)
161{
162 int slot_map = 0xFFFFFFFF;
163 int start_slot = 0;
164 int i;
165
166 for (i = 0; i < chs; i++) {
167 /*
168 * For 2 channels with starting slot as 0, slot map will
169 * look like 0xFFFFFF10.
170 */
171 slot_map &= (~(0xF << (4 * i)) | (start_slot << (4 * i)));
172 start_slot++;
173 }
174 fmt->ch_map = slot_map;
175}
176
Jeeja KPf7590d42015-10-07 11:31:53 +0100177static void skl_tplg_update_params(struct skl_module_fmt *fmt,
178 struct skl_pipe_params *params, int fixup)
179{
180 if (fixup & SKL_RATE_FIXUP_MASK)
181 fmt->s_freq = params->s_freq;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530182 if (fixup & SKL_CH_FIXUP_MASK) {
Jeeja KPf7590d42015-10-07 11:31:53 +0100183 fmt->channels = params->ch;
Subhransu S. Prustyea5a1372016-04-14 10:07:36 +0530184 skl_tplg_update_chmap(fmt, fmt->channels);
185 }
Jeeja KP98256f82015-11-23 22:26:25 +0530186 if (fixup & SKL_FMT_FIXUP_MASK) {
187 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
188
189 /*
190 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
191 * container so update bit depth accordingly
192 */
193 switch (fmt->valid_bit_depth) {
194 case SKL_DEPTH_16BIT:
195 fmt->bit_depth = fmt->valid_bit_depth;
196 break;
197
198 default:
199 fmt->bit_depth = SKL_DEPTH_32BIT;
200 break;
201 }
202 }
203
Jeeja KPf7590d42015-10-07 11:31:53 +0100204}
205
206/*
207 * A pipeline may have modules which impact the pcm parameters, like SRC,
208 * channel converter, format converter.
209 * We need to calculate the output params by applying the 'fixup'
210 * Topology will tell driver which type of fixup is to be applied by
211 * supplying the fixup mask, so based on that we calculate the output
212 *
213 * Now In FE the pcm hw_params is source/target format. Same is applicable
214 * for BE with its hw_params invoked.
215 * here based on FE, BE pipeline and direction we calculate the input and
216 * outfix and then apply that for a module
217 */
218static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
219 struct skl_pipe_params *params, bool is_fe)
220{
221 int in_fixup, out_fixup;
222 struct skl_module_fmt *in_fmt, *out_fmt;
223
Hardik T Shah4cd98992015-10-27 09:22:55 +0900224 /* Fixups will be applied to pin 0 only */
225 in_fmt = &m_cfg->in_fmt[0];
226 out_fmt = &m_cfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100227
228 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
229 if (is_fe) {
230 in_fixup = m_cfg->params_fixup;
231 out_fixup = (~m_cfg->converter) &
232 m_cfg->params_fixup;
233 } else {
234 out_fixup = m_cfg->params_fixup;
235 in_fixup = (~m_cfg->converter) &
236 m_cfg->params_fixup;
237 }
238 } else {
239 if (is_fe) {
240 out_fixup = m_cfg->params_fixup;
241 in_fixup = (~m_cfg->converter) &
242 m_cfg->params_fixup;
243 } else {
244 in_fixup = m_cfg->params_fixup;
245 out_fixup = (~m_cfg->converter) &
246 m_cfg->params_fixup;
247 }
248 }
249
250 skl_tplg_update_params(in_fmt, params, in_fixup);
251 skl_tplg_update_params(out_fmt, params, out_fixup);
252}
253
254/*
255 * A module needs input and output buffers, which are dependent upon pcm
256 * params, so once we have calculate params, we need buffer calculation as
257 * well.
258 */
259static void skl_tplg_update_buffer_size(struct skl_sst *ctx,
260 struct skl_module_cfg *mcfg)
261{
262 int multiplier = 1;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900263 struct skl_module_fmt *in_fmt, *out_fmt;
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530264 int in_rate, out_rate;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900265
266
267 /* Since fixups is applied to pin 0 only, ibs, obs needs
268 * change for pin 0 only
269 */
270 in_fmt = &mcfg->in_fmt[0];
271 out_fmt = &mcfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100272
273 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
274 multiplier = 5;
Jeeja KPf7590d42015-10-07 11:31:53 +0100275
Subhransu S. Prustyf0c8e1d2016-04-12 10:31:23 +0530276 if (in_fmt->s_freq % 1000)
277 in_rate = (in_fmt->s_freq / 1000) + 1;
278 else
279 in_rate = (in_fmt->s_freq / 1000);
280
281 mcfg->ibs = in_rate * (mcfg->in_fmt->channels) *
282 (mcfg->in_fmt->bit_depth >> 3) *
283 multiplier;
284
285 if (mcfg->out_fmt->s_freq % 1000)
286 out_rate = (mcfg->out_fmt->s_freq / 1000) + 1;
287 else
288 out_rate = (mcfg->out_fmt->s_freq / 1000);
289
290 mcfg->obs = out_rate * (mcfg->out_fmt->channels) *
291 (mcfg->out_fmt->bit_depth >> 3) *
292 multiplier;
Jeeja KPf7590d42015-10-07 11:31:53 +0100293}
294
Jeeja KP2d1419a2016-02-05 12:19:10 +0530295static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w,
296 struct skl_sst *ctx)
297{
298 struct skl_module_cfg *m_cfg = w->priv;
299 int link_type, dir;
300 u32 ch, s_freq, s_fmt;
301 struct nhlt_specific_cfg *cfg;
302 struct skl *skl = get_skl_ctx(ctx->dev);
303
304 /* check if we already have blob */
305 if (m_cfg->formats_config.caps_size > 0)
306 return 0;
307
Jeeja KPc7c6c732016-03-01 07:59:10 +0530308 dev_dbg(ctx->dev, "Applying default cfg blob\n");
Jeeja KP2d1419a2016-02-05 12:19:10 +0530309 switch (m_cfg->dev_type) {
310 case SKL_DEVICE_DMIC:
311 link_type = NHLT_LINK_DMIC;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530312 dir = SNDRV_PCM_STREAM_CAPTURE;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530313 s_freq = m_cfg->in_fmt[0].s_freq;
314 s_fmt = m_cfg->in_fmt[0].bit_depth;
315 ch = m_cfg->in_fmt[0].channels;
316 break;
317
318 case SKL_DEVICE_I2S:
319 link_type = NHLT_LINK_SSP;
320 if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) {
Jeeja KPc7c6c732016-03-01 07:59:10 +0530321 dir = SNDRV_PCM_STREAM_PLAYBACK;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530322 s_freq = m_cfg->out_fmt[0].s_freq;
323 s_fmt = m_cfg->out_fmt[0].bit_depth;
324 ch = m_cfg->out_fmt[0].channels;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530325 } else {
326 dir = SNDRV_PCM_STREAM_CAPTURE;
327 s_freq = m_cfg->in_fmt[0].s_freq;
328 s_fmt = m_cfg->in_fmt[0].bit_depth;
329 ch = m_cfg->in_fmt[0].channels;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530330 }
331 break;
332
333 default:
334 return -EINVAL;
335 }
336
337 /* update the blob based on virtual bus_id and default params */
338 cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type,
339 s_fmt, ch, s_freq, dir);
340 if (cfg) {
341 m_cfg->formats_config.caps_size = cfg->size;
342 m_cfg->formats_config.caps = (u32 *) &cfg->caps;
343 } else {
344 dev_err(ctx->dev, "Blob NULL for id %x type %d dirn %d\n",
345 m_cfg->vbus_id, link_type, dir);
346 dev_err(ctx->dev, "PCM: ch %d, freq %d, fmt %d\n",
347 ch, s_freq, s_fmt);
348 return -EIO;
349 }
350
351 return 0;
352}
353
Jeeja KPf7590d42015-10-07 11:31:53 +0100354static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
355 struct skl_sst *ctx)
356{
357 struct skl_module_cfg *m_cfg = w->priv;
358 struct skl_pipe_params *params = m_cfg->pipe->p_params;
359 int p_conn_type = m_cfg->pipe->conn_type;
360 bool is_fe;
361
362 if (!m_cfg->params_fixup)
363 return;
364
365 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n",
366 w->name);
367
368 skl_dump_mconfig(ctx, m_cfg);
369
370 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
371 is_fe = true;
372 else
373 is_fe = false;
374
375 skl_tplg_update_params_fixup(m_cfg, params, is_fe);
376 skl_tplg_update_buffer_size(ctx, m_cfg);
377
378 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n",
379 w->name);
380
381 skl_dump_mconfig(ctx, m_cfg);
382}
383
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100384/*
Jeeja KPabb74002015-11-28 15:01:49 +0530385 * some modules can have multiple params set from user control and
386 * need to be set after module is initialized. If set_param flag is
387 * set module params will be done after module is initialised.
388 */
389static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
390 struct skl_sst *ctx)
391{
392 int i, ret;
393 struct skl_module_cfg *mconfig = w->priv;
394 const struct snd_kcontrol_new *k;
395 struct soc_bytes_ext *sb;
396 struct skl_algo_data *bc;
397 struct skl_specific_cfg *sp_cfg;
398
399 if (mconfig->formats_config.caps_size > 0 &&
Jeeja KP4ced1822015-12-03 23:29:53 +0530400 mconfig->formats_config.set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530401 sp_cfg = &mconfig->formats_config;
402 ret = skl_set_module_params(ctx, sp_cfg->caps,
403 sp_cfg->caps_size,
404 sp_cfg->param_id, mconfig);
405 if (ret < 0)
406 return ret;
407 }
408
409 for (i = 0; i < w->num_kcontrols; i++) {
410 k = &w->kcontrol_news[i];
411 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
412 sb = (void *) k->private_value;
413 bc = (struct skl_algo_data *)sb->dobj.private;
414
Jeeja KP4ced1822015-12-03 23:29:53 +0530415 if (bc->set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530416 ret = skl_set_module_params(ctx,
Dharageswari R0d682102016-07-08 18:15:03 +0530417 (u32 *)bc->params, bc->size,
Jeeja KPabb74002015-11-28 15:01:49 +0530418 bc->param_id, mconfig);
419 if (ret < 0)
420 return ret;
421 }
422 }
423 }
424
425 return 0;
426}
427
428/*
429 * some module param can set from user control and this is required as
430 * when module is initailzed. if module param is required in init it is
431 * identifed by set_param flag. if set_param flag is not set, then this
432 * parameter needs to set as part of module init.
433 */
434static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
435{
436 const struct snd_kcontrol_new *k;
437 struct soc_bytes_ext *sb;
438 struct skl_algo_data *bc;
439 struct skl_module_cfg *mconfig = w->priv;
440 int i;
441
442 for (i = 0; i < w->num_kcontrols; i++) {
443 k = &w->kcontrol_news[i];
444 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
445 sb = (struct soc_bytes_ext *)k->private_value;
446 bc = (struct skl_algo_data *)sb->dobj.private;
447
Jeeja KP4ced1822015-12-03 23:29:53 +0530448 if (bc->set_params != SKL_PARAM_INIT)
Jeeja KPabb74002015-11-28 15:01:49 +0530449 continue;
450
451 mconfig->formats_config.caps = (u32 *)&bc->params;
Dharageswari R0d682102016-07-08 18:15:03 +0530452 mconfig->formats_config.caps_size = bc->size;
Jeeja KPabb74002015-11-28 15:01:49 +0530453
454 break;
455 }
456 }
457
458 return 0;
459}
460
461/*
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100462 * Inside a pipe instance, we can have various modules. These modules need
463 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
464 * skl_init_module() routine, so invoke that for all modules in a pipeline
465 */
466static int
467skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe)
468{
469 struct skl_pipe_module *w_module;
470 struct snd_soc_dapm_widget *w;
471 struct skl_module_cfg *mconfig;
472 struct skl_sst *ctx = skl->skl_sst;
473 int ret = 0;
474
475 list_for_each_entry(w_module, &pipe->w_list, node) {
476 w = w_module->w;
477 mconfig = w->priv;
478
Vinod Koulb7c50552016-07-26 18:06:40 +0530479 /* check if module ids are populated */
480 if (mconfig->id.module_id < 0) {
Vinod Koula657ae72016-08-10 09:40:50 +0530481 dev_err(skl->skl_sst->dev,
482 "module %pUL id not populated\n",
483 (uuid_le *)mconfig->guid);
484 return -EIO;
Vinod Koulb7c50552016-07-26 18:06:40 +0530485 }
486
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100487 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530488 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100489 return -ENOMEM;
490
Dharageswari R6c5768b2015-12-03 23:29:50 +0530491 if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {
492 ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,
493 mconfig->id.module_id, mconfig->guid);
494 if (ret < 0)
495 return ret;
Jeeja KPd6436782016-03-28 22:11:30 +0530496
497 mconfig->m_state = SKL_MODULE_LOADED;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530498 }
499
Jeeja KP2d1419a2016-02-05 12:19:10 +0530500 /* update blob if blob is null for be with default value */
501 skl_tplg_update_be_blob(w, ctx);
502
Jeeja KPf7590d42015-10-07 11:31:53 +0100503 /*
504 * apply fix/conversion to module params based on
505 * FE/BE params
506 */
507 skl_tplg_update_module_params(w, ctx);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530508 mconfig->id.pvt_id = skl_get_pvt_id(ctx, mconfig);
509 if (mconfig->id.pvt_id < 0)
510 return ret;
Jeeja KPabb74002015-11-28 15:01:49 +0530511 skl_tplg_set_module_init_data(w);
Jeeja KP9939a9c2015-11-28 15:01:47 +0530512 ret = skl_init_module(ctx, mconfig);
Dharageswari Ref2a3522016-09-22 14:00:38 +0530513 if (ret < 0) {
514 skl_put_pvt_id(ctx, mconfig);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100515 return ret;
Dharageswari Ref2a3522016-09-22 14:00:38 +0530516 }
Dharageswari R260eb732016-06-03 18:29:38 +0530517 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Jeeja KPabb74002015-11-28 15:01:49 +0530518 ret = skl_tplg_set_module_params(w, ctx);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100519 if (ret < 0)
520 return ret;
521 }
522
523 return 0;
524}
Vinod Kould93f8e52015-10-07 11:31:54 +0100525
Dharageswari R6c5768b2015-12-03 23:29:50 +0530526static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx,
527 struct skl_pipe *pipe)
528{
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530529 int ret;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530530 struct skl_pipe_module *w_module = NULL;
531 struct skl_module_cfg *mconfig = NULL;
532
533 list_for_each_entry(w_module, &pipe->w_list, node) {
534 mconfig = w_module->w->priv;
535
Jeeja KPd6436782016-03-28 22:11:30 +0530536 if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod &&
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530537 mconfig->m_state > SKL_MODULE_UNINIT) {
538 ret = ctx->dsp->fw_ops.unload_mod(ctx->dsp,
Dharageswari R6c5768b2015-12-03 23:29:50 +0530539 mconfig->id.module_id);
Dharageswari Rb0fab9c2016-08-24 18:03:16 +0530540 if (ret < 0)
541 return -EIO;
542 }
Dharageswari Ref2a3522016-09-22 14:00:38 +0530543 skl_put_pvt_id(ctx, mconfig);
Dharageswari R6c5768b2015-12-03 23:29:50 +0530544 }
545
546 /* no modules to unload in this path, so return */
547 return 0;
548}
549
Vinod Kould93f8e52015-10-07 11:31:54 +0100550/*
551 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
552 * need create the pipeline. So we do following:
553 * - check the resources
554 * - Create the pipeline
555 * - Initialize the modules in pipeline
556 * - finally bind all modules together
557 */
558static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
559 struct skl *skl)
560{
561 int ret;
562 struct skl_module_cfg *mconfig = w->priv;
563 struct skl_pipe_module *w_module;
564 struct skl_pipe *s_pipe = mconfig->pipe;
565 struct skl_module_cfg *src_module = NULL, *dst_module;
566 struct skl_sst *ctx = skl->skl_sst;
567
568 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530569 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100570 return -EBUSY;
571
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530572 if (!skl_is_pipe_mem_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100573 return -ENOMEM;
574
575 /*
576 * Create a list of modules for pipe.
577 * This list contains modules from source to sink
578 */
579 ret = skl_create_pipeline(ctx, mconfig->pipe);
580 if (ret < 0)
581 return ret;
582
Dharageswari R260eb732016-06-03 18:29:38 +0530583 skl_tplg_alloc_pipe_mem(skl, mconfig);
584 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100585
586 /* Init all pipe modules from source to sink */
587 ret = skl_tplg_init_pipe_modules(skl, s_pipe);
588 if (ret < 0)
589 return ret;
590
591 /* Bind modules from source to sink */
592 list_for_each_entry(w_module, &s_pipe->w_list, node) {
593 dst_module = w_module->w->priv;
594
595 if (src_module == NULL) {
596 src_module = dst_module;
597 continue;
598 }
599
600 ret = skl_bind_modules(ctx, src_module, dst_module);
601 if (ret < 0)
602 return ret;
603
604 src_module = dst_module;
605 }
606
607 return 0;
608}
609
Jeeja KPcc6a4042016-02-05 12:19:08 +0530610/*
611 * Some modules require params to be set after the module is bound to
612 * all pins connected.
613 *
614 * The module provider initializes set_param flag for such modules and we
615 * send params after binding
616 */
617static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w,
618 struct skl_module_cfg *mcfg, struct skl_sst *ctx)
619{
620 int i, ret;
621 struct skl_module_cfg *mconfig = w->priv;
622 const struct snd_kcontrol_new *k;
623 struct soc_bytes_ext *sb;
624 struct skl_algo_data *bc;
625 struct skl_specific_cfg *sp_cfg;
626
627 /*
628 * check all out/in pins are in bind state.
629 * if so set the module param
630 */
631 for (i = 0; i < mcfg->max_out_queue; i++) {
632 if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE)
633 return 0;
634 }
635
636 for (i = 0; i < mcfg->max_in_queue; i++) {
637 if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE)
638 return 0;
639 }
640
641 if (mconfig->formats_config.caps_size > 0 &&
642 mconfig->formats_config.set_params == SKL_PARAM_BIND) {
643 sp_cfg = &mconfig->formats_config;
644 ret = skl_set_module_params(ctx, sp_cfg->caps,
645 sp_cfg->caps_size,
646 sp_cfg->param_id, mconfig);
647 if (ret < 0)
648 return ret;
649 }
650
651 for (i = 0; i < w->num_kcontrols; i++) {
652 k = &w->kcontrol_news[i];
653 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
654 sb = (void *) k->private_value;
655 bc = (struct skl_algo_data *)sb->dobj.private;
656
657 if (bc->set_params == SKL_PARAM_BIND) {
658 ret = skl_set_module_params(ctx,
659 (u32 *)bc->params, bc->max,
660 bc->param_id, mconfig);
661 if (ret < 0)
662 return ret;
663 }
664 }
665 }
666
667 return 0;
668}
669
Jeeja KP8724ff12015-10-27 09:22:52 +0900670static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
671 struct skl *skl,
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530672 struct snd_soc_dapm_widget *src_w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900673 struct skl_module_cfg *src_mconfig)
Vinod Kould93f8e52015-10-07 11:31:54 +0100674{
675 struct snd_soc_dapm_path *p;
Jeeja KP0ed95d72015-11-13 19:22:11 +0530676 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
Jeeja KP8724ff12015-10-27 09:22:52 +0900677 struct skl_module_cfg *sink_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100678 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP8724ff12015-10-27 09:22:52 +0900679 int ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100680
Jeeja KP8724ff12015-10-27 09:22:52 +0900681 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Kould93f8e52015-10-07 11:31:54 +0100682 if (!p->connect)
683 continue;
684
685 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name);
686 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name);
687
Jeeja KP0ed95d72015-11-13 19:22:11 +0530688 next_sink = p->sink;
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530689
690 if (!is_skl_dsp_widget_type(p->sink))
691 return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig);
692
Vinod Kould93f8e52015-10-07 11:31:54 +0100693 /*
694 * here we will check widgets in sink pipelines, so that
695 * can be any widgets type and we are only interested if
696 * they are ones used for SKL so check that first
697 */
698 if ((p->sink->priv != NULL) &&
699 is_skl_dsp_widget_type(p->sink)) {
700
701 sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100702 sink_mconfig = sink->priv;
703
Jeeja KPcc6a4042016-02-05 12:19:08 +0530704 if (src_mconfig->m_state == SKL_MODULE_UNINIT ||
705 sink_mconfig->m_state == SKL_MODULE_UNINIT)
706 continue;
707
Vinod Kould93f8e52015-10-07 11:31:54 +0100708 /* Bind source to sink, mixin is always source */
709 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
710 if (ret)
711 return ret;
712
Jeeja KPcc6a4042016-02-05 12:19:08 +0530713 /* set module params after bind */
714 skl_tplg_set_module_bind_params(src_w, src_mconfig, ctx);
715 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
716
Vinod Kould93f8e52015-10-07 11:31:54 +0100717 /* Start sinks pipe first */
718 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
Jeeja KPd1730c32015-10-27 09:22:53 +0900719 if (sink_mconfig->pipe->conn_type !=
720 SKL_PIPE_CONN_TYPE_FE)
721 ret = skl_run_pipe(ctx,
722 sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100723 if (ret)
724 return ret;
725 }
Vinod Kould93f8e52015-10-07 11:31:54 +0100726 }
727 }
728
Jeeja KP8724ff12015-10-27 09:22:52 +0900729 if (!sink)
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530730 return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig);
Jeeja KP8724ff12015-10-27 09:22:52 +0900731
732 return 0;
733}
734
Vinod Kould93f8e52015-10-07 11:31:54 +0100735/*
736 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
737 * we need to do following:
738 * - Bind to sink pipeline
739 * Since the sink pipes can be running and we don't get mixer event on
740 * connect for already running mixer, we need to find the sink pipes
741 * here and bind to them. This way dynamic connect works.
742 * - Start sink pipeline, if not running
743 * - Then run current pipe
744 */
745static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900746 struct skl *skl)
Vinod Kould93f8e52015-10-07 11:31:54 +0100747{
Jeeja KP8724ff12015-10-27 09:22:52 +0900748 struct skl_module_cfg *src_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100749 struct skl_sst *ctx = skl->skl_sst;
750 int ret = 0;
751
Jeeja KP8724ff12015-10-27 09:22:52 +0900752 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100753
754 /*
755 * find which sink it is connected to, bind with the sink,
756 * if sink is not started, start sink pipe first, then start
757 * this pipe
758 */
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530759 ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100760 if (ret)
761 return ret;
762
Vinod Kould93f8e52015-10-07 11:31:54 +0100763 /* Start source pipe last after starting all sinks */
Jeeja KPd1730c32015-10-27 09:22:53 +0900764 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
765 return skl_run_pipe(ctx, src_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100766
767 return 0;
768}
769
Jeeja KP8724ff12015-10-27 09:22:52 +0900770static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
771 struct snd_soc_dapm_widget *w, struct skl *skl)
772{
773 struct snd_soc_dapm_path *p;
774 struct snd_soc_dapm_widget *src_w = NULL;
775 struct skl_sst *ctx = skl->skl_sst;
776
777 snd_soc_dapm_widget_for_each_source_path(w, p) {
778 src_w = p->source;
779 if (!p->connect)
780 continue;
781
782 dev_dbg(ctx->dev, "sink widget=%s\n", w->name);
783 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name);
784
785 /*
786 * here we will check widgets in sink pipelines, so that can
787 * be any widgets type and we are only interested if they are
788 * ones used for SKL so check that first
789 */
790 if ((p->source->priv != NULL) &&
791 is_skl_dsp_widget_type(p->source)) {
792 return p->source;
793 }
794 }
795
796 if (src_w != NULL)
797 return skl_get_src_dsp_widget(src_w, skl);
798
799 return NULL;
800}
801
Vinod Kould93f8e52015-10-07 11:31:54 +0100802/*
803 * in the Post-PMU event of mixer we need to do following:
804 * - Check if this pipe is running
805 * - if not, then
806 * - bind this pipeline to its source pipeline
807 * if source pipe is already running, this means it is a dynamic
808 * connection and we need to bind only to that pipe
809 * - start this pipeline
810 */
811static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
812 struct skl *skl)
813{
814 int ret = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100815 struct snd_soc_dapm_widget *source, *sink;
816 struct skl_module_cfg *src_mconfig, *sink_mconfig;
817 struct skl_sst *ctx = skl->skl_sst;
818 int src_pipe_started = 0;
819
820 sink = w;
821 sink_mconfig = sink->priv;
822
823 /*
824 * If source pipe is already started, that means source is driving
825 * one more sink before this sink got connected, Since source is
826 * started, bind this sink to source and start this pipe.
827 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900828 source = skl_get_src_dsp_widget(w, skl);
829 if (source != NULL) {
830 src_mconfig = source->priv;
831 sink_mconfig = sink->priv;
832 src_pipe_started = 1;
Vinod Kould93f8e52015-10-07 11:31:54 +0100833
834 /*
Jeeja KP8724ff12015-10-27 09:22:52 +0900835 * check pipe state, then no need to bind or start the
836 * pipe
Vinod Kould93f8e52015-10-07 11:31:54 +0100837 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900838 if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
839 src_pipe_started = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100840 }
841
842 if (src_pipe_started) {
843 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
844 if (ret)
845 return ret;
846
Jeeja KPcc6a4042016-02-05 12:19:08 +0530847 /* set module params after bind */
848 skl_tplg_set_module_bind_params(source, src_mconfig, ctx);
849 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
850
Jeeja KPd1730c32015-10-27 09:22:53 +0900851 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
852 ret = skl_run_pipe(ctx, sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100853 }
854
855 return ret;
856}
857
858/*
859 * in the Pre-PMD event of mixer we need to do following:
860 * - Stop the pipe
861 * - find the source connections and remove that from dapm_path_list
862 * - unbind with source pipelines if still connected
863 */
864static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
865 struct skl *skl)
866{
Vinod Kould93f8e52015-10-07 11:31:54 +0100867 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900868 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100869 struct skl_sst *ctx = skl->skl_sst;
870
Jeeja KPce1b5552015-10-27 09:22:51 +0900871 sink_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100872
873 /* Stop the pipe */
874 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
875 if (ret)
876 return ret;
877
Jeeja KPce1b5552015-10-27 09:22:51 +0900878 for (i = 0; i < sink_mconfig->max_in_queue; i++) {
879 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
880 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
881 if (!src_mconfig)
882 continue;
883 /*
884 * If path_found == 1, that means pmd for source
885 * pipe has not occurred, source is connected to
886 * some other sink. so its responsibility of sink
887 * to unbind itself from source.
888 */
889 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
890 if (ret < 0)
891 return ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100892
Jeeja KPce1b5552015-10-27 09:22:51 +0900893 ret = skl_unbind_modules(ctx,
894 src_mconfig, sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100895 }
896 }
897
Vinod Kould93f8e52015-10-07 11:31:54 +0100898 return ret;
899}
900
901/*
902 * in the Post-PMD event of mixer we need to do following:
903 * - Free the mcps used
904 * - Free the mem used
905 * - Unbind the modules within the pipeline
906 * - Delete the pipeline (modules are not required to be explicitly
907 * deleted, pipeline delete is enough here
908 */
909static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
910 struct skl *skl)
911{
912 struct skl_module_cfg *mconfig = w->priv;
913 struct skl_pipe_module *w_module;
914 struct skl_module_cfg *src_module = NULL, *dst_module;
915 struct skl_sst *ctx = skl->skl_sst;
916 struct skl_pipe *s_pipe = mconfig->pipe;
917 int ret = 0;
918
Dharageswari R260eb732016-06-03 18:29:38 +0530919 if (s_pipe->state == SKL_PIPE_INVALID)
920 return -EINVAL;
921
Vinod Kould93f8e52015-10-07 11:31:54 +0100922 skl_tplg_free_pipe_mcps(skl, mconfig);
Vinod Koul65976872015-11-23 22:26:29 +0530923 skl_tplg_free_pipe_mem(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100924
925 list_for_each_entry(w_module, &s_pipe->w_list, node) {
926 dst_module = w_module->w->priv;
927
Dharageswari R260eb732016-06-03 18:29:38 +0530928 if (mconfig->m_state >= SKL_MODULE_INIT_DONE)
929 skl_tplg_free_pipe_mcps(skl, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +0100930 if (src_module == NULL) {
931 src_module = dst_module;
932 continue;
933 }
934
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530935 skl_unbind_modules(ctx, src_module, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +0100936 src_module = dst_module;
937 }
938
939 ret = skl_delete_pipe(ctx, mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100940
Dharageswari R6c5768b2015-12-03 23:29:50 +0530941 return skl_tplg_unload_pipe_modules(ctx, s_pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100942}
943
944/*
945 * in the Post-PMD event of PGA we need to do following:
946 * - Free the mcps used
947 * - Stop the pipeline
948 * - In source pipe is connected, unbind with source pipelines
949 */
950static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
951 struct skl *skl)
952{
Vinod Kould93f8e52015-10-07 11:31:54 +0100953 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900954 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100955 struct skl_sst *ctx = skl->skl_sst;
956
Jeeja KPce1b5552015-10-27 09:22:51 +0900957 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100958
Vinod Kould93f8e52015-10-07 11:31:54 +0100959 /* Stop the pipe since this is a mixin module */
960 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
961 if (ret)
962 return ret;
963
Jeeja KPce1b5552015-10-27 09:22:51 +0900964 for (i = 0; i < src_mconfig->max_out_queue; i++) {
965 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
966 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
967 if (!sink_mconfig)
968 continue;
969 /*
970 * This is a connecter and if path is found that means
971 * unbind between source and sink has not happened yet
972 */
Jeeja KPce1b5552015-10-27 09:22:51 +0900973 ret = skl_unbind_modules(ctx, src_mconfig,
974 sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100975 }
976 }
977
Vinod Kould93f8e52015-10-07 11:31:54 +0100978 return ret;
979}
980
981/*
982 * In modelling, we assume there will be ONLY one mixer in a pipeline. If
983 * mixer is not required then it is treated as static mixer aka vmixer with
984 * a hard path to source module
985 * So we don't need to check if source is started or not as hard path puts
986 * dependency on each other
987 */
988static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w,
989 struct snd_kcontrol *k, int event)
990{
991 struct snd_soc_dapm_context *dapm = w->dapm;
992 struct skl *skl = get_skl_ctx(dapm->dev);
993
994 switch (event) {
995 case SND_SOC_DAPM_PRE_PMU:
996 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
997
Jeeja KPde1fedf2016-02-03 17:59:52 +0530998 case SND_SOC_DAPM_POST_PMU:
999 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1000
1001 case SND_SOC_DAPM_PRE_PMD:
1002 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1003
Vinod Kould93f8e52015-10-07 11:31:54 +01001004 case SND_SOC_DAPM_POST_PMD:
1005 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1006 }
1007
1008 return 0;
1009}
1010
1011/*
1012 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
1013 * second one is required that is created as another pipe entity.
1014 * The mixer is responsible for pipe management and represent a pipeline
1015 * instance
1016 */
1017static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
1018 struct snd_kcontrol *k, int event)
1019{
1020 struct snd_soc_dapm_context *dapm = w->dapm;
1021 struct skl *skl = get_skl_ctx(dapm->dev);
1022
1023 switch (event) {
1024 case SND_SOC_DAPM_PRE_PMU:
1025 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
1026
1027 case SND_SOC_DAPM_POST_PMU:
1028 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1029
1030 case SND_SOC_DAPM_PRE_PMD:
1031 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1032
1033 case SND_SOC_DAPM_POST_PMD:
1034 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1035 }
1036
1037 return 0;
1038}
1039
1040/*
1041 * In modelling, we assumed rest of the modules in pipeline are PGA. But we
1042 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
1043 * the sink when it is running (two FE to one BE or one FE to two BE)
1044 * scenarios
1045 */
1046static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
1047 struct snd_kcontrol *k, int event)
1048
1049{
1050 struct snd_soc_dapm_context *dapm = w->dapm;
1051 struct skl *skl = get_skl_ctx(dapm->dev);
1052
1053 switch (event) {
1054 case SND_SOC_DAPM_PRE_PMU:
1055 return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
1056
1057 case SND_SOC_DAPM_POST_PMD:
1058 return skl_tplg_pga_dapm_post_pmd_event(w, skl);
1059 }
1060
1061 return 0;
1062}
Vinod Koulcfb0a872015-10-07 11:31:55 +01001063
Jeeja KP140adfb2015-11-28 15:01:50 +05301064static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
1065 unsigned int __user *data, unsigned int size)
1066{
1067 struct soc_bytes_ext *sb =
1068 (struct soc_bytes_ext *)kcontrol->private_value;
1069 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
Omair M Abdullah7d9f2912015-12-03 23:29:56 +05301070 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1071 struct skl_module_cfg *mconfig = w->priv;
1072 struct skl *skl = get_skl_ctx(w->dapm->dev);
1073
1074 if (w->power)
1075 skl_get_module_params(skl->skl_sst, (u32 *)bc->params,
Dharageswari R0d682102016-07-08 18:15:03 +05301076 bc->size, bc->param_id, mconfig);
Jeeja KP140adfb2015-11-28 15:01:50 +05301077
Vinod Koul41556f62016-02-03 17:59:44 +05301078 /* decrement size for TLV header */
1079 size -= 2 * sizeof(u32);
1080
1081 /* check size as we don't want to send kernel data */
1082 if (size > bc->max)
1083 size = bc->max;
1084
Jeeja KP140adfb2015-11-28 15:01:50 +05301085 if (bc->params) {
1086 if (copy_to_user(data, &bc->param_id, sizeof(u32)))
1087 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001088 if (copy_to_user(data + 1, &size, sizeof(u32)))
Jeeja KP140adfb2015-11-28 15:01:50 +05301089 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001090 if (copy_to_user(data + 2, bc->params, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301091 return -EFAULT;
1092 }
1093
1094 return 0;
1095}
1096
1097#define SKL_PARAM_VENDOR_ID 0xff
1098
1099static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
1100 const unsigned int __user *data, unsigned int size)
1101{
1102 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1103 struct skl_module_cfg *mconfig = w->priv;
1104 struct soc_bytes_ext *sb =
1105 (struct soc_bytes_ext *)kcontrol->private_value;
1106 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
1107 struct skl *skl = get_skl_ctx(w->dapm->dev);
1108
1109 if (ac->params) {
Dharageswari R0d682102016-07-08 18:15:03 +05301110 if (size > ac->max)
1111 return -EINVAL;
1112
1113 ac->size = size;
Jeeja KP140adfb2015-11-28 15:01:50 +05301114 /*
1115 * if the param_is is of type Vendor, firmware expects actual
1116 * parameter id and size from the control.
1117 */
1118 if (ac->param_id == SKL_PARAM_VENDOR_ID) {
1119 if (copy_from_user(ac->params, data, size))
1120 return -EFAULT;
1121 } else {
1122 if (copy_from_user(ac->params,
Alan65b4bcb2016-02-19 11:42:32 +05301123 data + 2, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301124 return -EFAULT;
1125 }
1126
1127 if (w->power)
1128 return skl_set_module_params(skl->skl_sst,
Dharageswari R0d682102016-07-08 18:15:03 +05301129 (u32 *)ac->params, ac->size,
Jeeja KP140adfb2015-11-28 15:01:50 +05301130 ac->param_id, mconfig);
1131 }
1132
1133 return 0;
1134}
1135
Vinod Koulcfb0a872015-10-07 11:31:55 +01001136/*
Jeeja KP8871dcb2016-06-03 18:29:42 +05301137 * Fill the dma id for host and link. In case of passthrough
1138 * pipeline, this will both host and link in the same
1139 * pipeline, so need to copy the link and host based on dev_type
1140 */
1141static void skl_tplg_fill_dma_id(struct skl_module_cfg *mcfg,
1142 struct skl_pipe_params *params)
1143{
1144 struct skl_pipe *pipe = mcfg->pipe;
1145
1146 if (pipe->passthru) {
1147 switch (mcfg->dev_type) {
1148 case SKL_DEVICE_HDALINK:
1149 pipe->p_params->link_dma_id = params->link_dma_id;
1150 break;
1151
1152 case SKL_DEVICE_HDAHOST:
1153 pipe->p_params->host_dma_id = params->host_dma_id;
1154 break;
1155
1156 default:
1157 break;
1158 }
1159 pipe->p_params->s_fmt = params->s_fmt;
1160 pipe->p_params->ch = params->ch;
1161 pipe->p_params->s_freq = params->s_freq;
1162 pipe->p_params->stream = params->stream;
1163
1164 } else {
1165 memcpy(pipe->p_params, params, sizeof(*params));
1166 }
1167}
1168
1169/*
Vinod Koulcfb0a872015-10-07 11:31:55 +01001170 * The FE params are passed by hw_params of the DAI.
1171 * On hw_params, the params are stored in Gateway module of the FE and we
1172 * need to calculate the format in DSP module configuration, that
1173 * conversion is done here
1174 */
1175int skl_tplg_update_pipe_params(struct device *dev,
1176 struct skl_module_cfg *mconfig,
1177 struct skl_pipe_params *params)
1178{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001179 struct skl_module_fmt *format = NULL;
1180
Jeeja KP8871dcb2016-06-03 18:29:42 +05301181 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001182
1183 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001184 format = &mconfig->in_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001185 else
Hardik T Shah4cd98992015-10-27 09:22:55 +09001186 format = &mconfig->out_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001187
1188 /* set the hw_params */
1189 format->s_freq = params->s_freq;
1190 format->channels = params->ch;
1191 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
1192
1193 /*
1194 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
1195 * container so update bit depth accordingly
1196 */
1197 switch (format->valid_bit_depth) {
1198 case SKL_DEPTH_16BIT:
1199 format->bit_depth = format->valid_bit_depth;
1200 break;
1201
1202 case SKL_DEPTH_24BIT:
Jeeja KP6654f392015-10-27 09:22:46 +09001203 case SKL_DEPTH_32BIT:
Vinod Koulcfb0a872015-10-07 11:31:55 +01001204 format->bit_depth = SKL_DEPTH_32BIT;
1205 break;
1206
1207 default:
1208 dev_err(dev, "Invalid bit depth %x for pipe\n",
1209 format->valid_bit_depth);
1210 return -EINVAL;
1211 }
1212
1213 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1214 mconfig->ibs = (format->s_freq / 1000) *
1215 (format->channels) *
1216 (format->bit_depth >> 3);
1217 } else {
1218 mconfig->obs = (format->s_freq / 1000) *
1219 (format->channels) *
1220 (format->bit_depth >> 3);
1221 }
1222
1223 return 0;
1224}
1225
1226/*
1227 * Query the module config for the FE DAI
1228 * This is used to find the hw_params set for that DAI and apply to FE
1229 * pipeline
1230 */
1231struct skl_module_cfg *
1232skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
1233{
1234 struct snd_soc_dapm_widget *w;
1235 struct snd_soc_dapm_path *p = NULL;
1236
1237 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1238 w = dai->playback_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301239 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001240 if (p->connect && p->sink->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001241 !is_skl_dsp_widget_type(p->sink))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001242 continue;
1243
1244 if (p->sink->priv) {
1245 dev_dbg(dai->dev, "set params for %s\n",
1246 p->sink->name);
1247 return p->sink->priv;
1248 }
1249 }
1250 } else {
1251 w = dai->capture_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301252 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001253 if (p->connect && p->source->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001254 !is_skl_dsp_widget_type(p->source))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001255 continue;
1256
1257 if (p->source->priv) {
1258 dev_dbg(dai->dev, "set params for %s\n",
1259 p->source->name);
1260 return p->source->priv;
1261 }
1262 }
1263 }
1264
1265 return NULL;
1266}
1267
Dharageswari.R718a42b2016-02-05 12:19:06 +05301268static struct skl_module_cfg *skl_get_mconfig_pb_cpr(
1269 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1270{
1271 struct snd_soc_dapm_path *p;
1272 struct skl_module_cfg *mconfig = NULL;
1273
1274 snd_soc_dapm_widget_for_each_source_path(w, p) {
1275 if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) {
1276 if (p->connect &&
1277 (p->sink->id == snd_soc_dapm_aif_out) &&
1278 p->source->priv) {
1279 mconfig = p->source->priv;
1280 return mconfig;
1281 }
1282 mconfig = skl_get_mconfig_pb_cpr(dai, p->source);
1283 if (mconfig)
1284 return mconfig;
1285 }
1286 }
1287 return mconfig;
1288}
1289
1290static struct skl_module_cfg *skl_get_mconfig_cap_cpr(
1291 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1292{
1293 struct snd_soc_dapm_path *p;
1294 struct skl_module_cfg *mconfig = NULL;
1295
1296 snd_soc_dapm_widget_for_each_sink_path(w, p) {
1297 if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) {
1298 if (p->connect &&
1299 (p->source->id == snd_soc_dapm_aif_in) &&
1300 p->sink->priv) {
1301 mconfig = p->sink->priv;
1302 return mconfig;
1303 }
1304 mconfig = skl_get_mconfig_cap_cpr(dai, p->sink);
1305 if (mconfig)
1306 return mconfig;
1307 }
1308 }
1309 return mconfig;
1310}
1311
1312struct skl_module_cfg *
1313skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream)
1314{
1315 struct snd_soc_dapm_widget *w;
1316 struct skl_module_cfg *mconfig;
1317
1318 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1319 w = dai->playback_widget;
1320 mconfig = skl_get_mconfig_pb_cpr(dai, w);
1321 } else {
1322 w = dai->capture_widget;
1323 mconfig = skl_get_mconfig_cap_cpr(dai, w);
1324 }
1325 return mconfig;
1326}
1327
Vinod Koulcfb0a872015-10-07 11:31:55 +01001328static u8 skl_tplg_be_link_type(int dev_type)
1329{
1330 int ret;
1331
1332 switch (dev_type) {
1333 case SKL_DEVICE_BT:
1334 ret = NHLT_LINK_SSP;
1335 break;
1336
1337 case SKL_DEVICE_DMIC:
1338 ret = NHLT_LINK_DMIC;
1339 break;
1340
1341 case SKL_DEVICE_I2S:
1342 ret = NHLT_LINK_SSP;
1343 break;
1344
1345 case SKL_DEVICE_HDALINK:
1346 ret = NHLT_LINK_HDA;
1347 break;
1348
1349 default:
1350 ret = NHLT_LINK_INVALID;
1351 break;
1352 }
1353
1354 return ret;
1355}
1356
1357/*
1358 * Fill the BE gateway parameters
1359 * The BE gateway expects a blob of parameters which are kept in the ACPI
1360 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
1361 * The port can have multiple settings so pick based on the PCM
1362 * parameters
1363 */
1364static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
1365 struct skl_module_cfg *mconfig,
1366 struct skl_pipe_params *params)
1367{
Vinod Koulcfb0a872015-10-07 11:31:55 +01001368 struct nhlt_specific_cfg *cfg;
1369 struct skl *skl = get_skl_ctx(dai->dev);
1370 int link_type = skl_tplg_be_link_type(mconfig->dev_type);
1371
Jeeja KP8871dcb2016-06-03 18:29:42 +05301372 skl_tplg_fill_dma_id(mconfig, params);
Vinod Koulcfb0a872015-10-07 11:31:55 +01001373
Jeeja KPb30c2752015-10-27 09:22:48 +09001374 if (link_type == NHLT_LINK_HDA)
1375 return 0;
1376
Vinod Koulcfb0a872015-10-07 11:31:55 +01001377 /* update the blob based on virtual bus_id*/
1378 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
1379 params->s_fmt, params->ch,
1380 params->s_freq, params->stream);
1381 if (cfg) {
1382 mconfig->formats_config.caps_size = cfg->size;
Jeeja KPbc032812015-10-22 23:22:35 +05301383 mconfig->formats_config.caps = (u32 *) &cfg->caps;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001384 } else {
1385 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
1386 mconfig->vbus_id, link_type,
1387 params->stream);
1388 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
1389 params->ch, params->s_freq, params->s_fmt);
1390 return -EINVAL;
1391 }
1392
1393 return 0;
1394}
1395
1396static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
1397 struct snd_soc_dapm_widget *w,
1398 struct skl_pipe_params *params)
1399{
1400 struct snd_soc_dapm_path *p;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301401 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001402
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301403 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001404 if (p->connect && is_skl_dsp_widget_type(p->source) &&
1405 p->source->priv) {
1406
Jeeja KP9a03cb42015-10-27 09:22:54 +09001407 ret = skl_tplg_be_fill_pipe_params(dai,
1408 p->source->priv, params);
1409 if (ret < 0)
1410 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001411 } else {
Jeeja KP9a03cb42015-10-27 09:22:54 +09001412 ret = skl_tplg_be_set_src_pipe_params(dai,
1413 p->source, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301414 if (ret < 0)
1415 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001416 }
1417 }
1418
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301419 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001420}
1421
1422static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
1423 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
1424{
1425 struct snd_soc_dapm_path *p = NULL;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301426 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001427
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301428 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001429 if (p->connect && is_skl_dsp_widget_type(p->sink) &&
1430 p->sink->priv) {
1431
Jeeja KP9a03cb42015-10-27 09:22:54 +09001432 ret = skl_tplg_be_fill_pipe_params(dai,
1433 p->sink->priv, params);
1434 if (ret < 0)
1435 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001436 } else {
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301437 ret = skl_tplg_be_set_sink_pipe_params(
Vinod Koulcfb0a872015-10-07 11:31:55 +01001438 dai, p->sink, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301439 if (ret < 0)
1440 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001441 }
1442 }
1443
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301444 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001445}
1446
1447/*
1448 * BE hw_params can be a source parameters (capture) or sink parameters
1449 * (playback). Based on sink and source we need to either find the source
1450 * list or the sink list and set the pipeline parameters
1451 */
1452int skl_tplg_be_update_params(struct snd_soc_dai *dai,
1453 struct skl_pipe_params *params)
1454{
1455 struct snd_soc_dapm_widget *w;
1456
1457 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1458 w = dai->playback_widget;
1459
1460 return skl_tplg_be_set_src_pipe_params(dai, w, params);
1461
1462 } else {
1463 w = dai->capture_widget;
1464
1465 return skl_tplg_be_set_sink_pipe_params(dai, w, params);
1466 }
1467
1468 return 0;
1469}
Vinod Koul3af36702015-10-07 11:31:56 +01001470
1471static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
1472 {SKL_MIXER_EVENT, skl_tplg_mixer_event},
1473 {SKL_VMIXER_EVENT, skl_tplg_vmixer_event},
1474 {SKL_PGA_EVENT, skl_tplg_pga_event},
1475};
1476
Jeeja KP140adfb2015-11-28 15:01:50 +05301477static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
1478 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
1479 skl_tplg_tlv_control_set},
1480};
1481
Shreyas NC6277e832016-08-12 12:29:51 +05301482static int skl_tplg_fill_pipe_tkn(struct device *dev,
1483 struct skl_pipe *pipe, u32 tkn,
1484 u32 tkn_val)
Vinod Koul3af36702015-10-07 11:31:56 +01001485{
Vinod Koul3af36702015-10-07 11:31:56 +01001486
Shreyas NC6277e832016-08-12 12:29:51 +05301487 switch (tkn) {
1488 case SKL_TKN_U32_PIPE_CONN_TYPE:
1489 pipe->conn_type = tkn_val;
1490 break;
1491
1492 case SKL_TKN_U32_PIPE_PRIORITY:
1493 pipe->pipe_priority = tkn_val;
1494 break;
1495
1496 case SKL_TKN_U32_PIPE_MEM_PGS:
1497 pipe->memory_pages = tkn_val;
1498 break;
1499
1500 default:
1501 dev_err(dev, "Token not handled %d\n", tkn);
1502 return -EINVAL;
Vinod Koul3af36702015-10-07 11:31:56 +01001503 }
Shreyas NC6277e832016-08-12 12:29:51 +05301504
1505 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001506}
1507
1508/*
Shreyas NC6277e832016-08-12 12:29:51 +05301509 * Add pipeline by parsing the relevant tokens
1510 * Return an existing pipe if the pipe already exists.
Vinod Koul3af36702015-10-07 11:31:56 +01001511 */
Shreyas NC6277e832016-08-12 12:29:51 +05301512static int skl_tplg_add_pipe(struct device *dev,
1513 struct skl_module_cfg *mconfig, struct skl *skl,
1514 struct snd_soc_tplg_vendor_value_elem *tkn_elem)
Vinod Koul3af36702015-10-07 11:31:56 +01001515{
1516 struct skl_pipeline *ppl;
1517 struct skl_pipe *pipe;
1518 struct skl_pipe_params *params;
1519
1520 list_for_each_entry(ppl, &skl->ppl_list, node) {
Shreyas NC6277e832016-08-12 12:29:51 +05301521 if (ppl->pipe->ppl_id == tkn_elem->value) {
1522 mconfig->pipe = ppl->pipe;
1523 return EEXIST;
1524 }
Vinod Koul3af36702015-10-07 11:31:56 +01001525 }
1526
1527 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
1528 if (!ppl)
Shreyas NC6277e832016-08-12 12:29:51 +05301529 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001530
1531 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
1532 if (!pipe)
Shreyas NC6277e832016-08-12 12:29:51 +05301533 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001534
1535 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
1536 if (!params)
Shreyas NC6277e832016-08-12 12:29:51 +05301537 return -ENOMEM;
Vinod Koul3af36702015-10-07 11:31:56 +01001538
Vinod Koul3af36702015-10-07 11:31:56 +01001539 pipe->p_params = params;
Shreyas NC6277e832016-08-12 12:29:51 +05301540 pipe->ppl_id = tkn_elem->value;
Vinod Koul3af36702015-10-07 11:31:56 +01001541 INIT_LIST_HEAD(&pipe->w_list);
1542
1543 ppl->pipe = pipe;
1544 list_add(&ppl->node, &skl->ppl_list);
1545
Shreyas NC6277e832016-08-12 12:29:51 +05301546 mconfig->pipe = pipe;
1547 mconfig->pipe->state = SKL_PIPE_INVALID;
1548
1549 return 0;
Vinod Koul3af36702015-10-07 11:31:56 +01001550}
1551
Shreyas NC6277e832016-08-12 12:29:51 +05301552static int skl_tplg_fill_pin(struct device *dev, u32 tkn,
1553 struct skl_module_pin *m_pin,
1554 int pin_index, u32 value)
1555{
1556 switch (tkn) {
1557 case SKL_TKN_U32_PIN_MOD_ID:
1558 m_pin[pin_index].id.module_id = value;
1559 break;
1560
1561 case SKL_TKN_U32_PIN_INST_ID:
1562 m_pin[pin_index].id.instance_id = value;
1563 break;
1564
1565 default:
1566 dev_err(dev, "%d Not a pin token\n", value);
1567 return -EINVAL;
1568 }
1569
1570 return 0;
1571}
1572
1573/*
1574 * Parse for pin config specific tokens to fill up the
1575 * module private data
1576 */
1577static int skl_tplg_fill_pins_info(struct device *dev,
1578 struct skl_module_cfg *mconfig,
1579 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1580 int dir, int pin_count)
1581{
1582 int ret;
1583 struct skl_module_pin *m_pin;
1584
1585 switch (dir) {
1586 case SKL_DIR_IN:
1587 m_pin = mconfig->m_in_pin;
1588 break;
1589
1590 case SKL_DIR_OUT:
1591 m_pin = mconfig->m_out_pin;
1592 break;
1593
1594 default:
1595 dev_err(dev, "Invalid direction value");
1596 return -EINVAL;
1597 }
1598
1599 ret = skl_tplg_fill_pin(dev, tkn_elem->token,
1600 m_pin, pin_count, tkn_elem->value);
1601
1602 if (ret < 0)
1603 return ret;
1604
1605 m_pin[pin_count].in_use = false;
1606 m_pin[pin_count].pin_state = SKL_PIN_UNBIND;
1607
1608 return 0;
1609}
1610
1611/*
1612 * Fill up input/output module config format based
1613 * on the direction
1614 */
1615static int skl_tplg_fill_fmt(struct device *dev,
1616 struct skl_module_cfg *mconfig, u32 tkn,
1617 u32 value, u32 dir, u32 pin_count)
1618{
1619 struct skl_module_fmt *dst_fmt;
1620
1621 switch (dir) {
1622 case SKL_DIR_IN:
1623 dst_fmt = mconfig->in_fmt;
1624 dst_fmt += pin_count;
1625 break;
1626
1627 case SKL_DIR_OUT:
1628 dst_fmt = mconfig->out_fmt;
1629 dst_fmt += pin_count;
1630 break;
1631
1632 default:
1633 dev_err(dev, "Invalid direction value");
1634 return -EINVAL;
1635 }
1636
1637 switch (tkn) {
1638 case SKL_TKN_U32_FMT_CH:
1639 dst_fmt->channels = value;
1640 break;
1641
1642 case SKL_TKN_U32_FMT_FREQ:
1643 dst_fmt->s_freq = value;
1644 break;
1645
1646 case SKL_TKN_U32_FMT_BIT_DEPTH:
1647 dst_fmt->bit_depth = value;
1648 break;
1649
1650 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1651 dst_fmt->valid_bit_depth = value;
1652 break;
1653
1654 case SKL_TKN_U32_FMT_CH_CONFIG:
1655 dst_fmt->ch_cfg = value;
1656 break;
1657
1658 case SKL_TKN_U32_FMT_INTERLEAVE:
1659 dst_fmt->interleaving_style = value;
1660 break;
1661
1662 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1663 dst_fmt->sample_type = value;
1664 break;
1665
1666 case SKL_TKN_U32_FMT_CH_MAP:
1667 dst_fmt->ch_map = value;
1668 break;
1669
1670 default:
1671 dev_err(dev, "Invalid token %d", tkn);
1672 return -EINVAL;
1673 }
1674
1675 return 0;
1676}
1677
1678static int skl_tplg_get_uuid(struct device *dev, struct skl_module_cfg *mconfig,
1679 struct snd_soc_tplg_vendor_uuid_elem *uuid_tkn)
1680{
1681 if (uuid_tkn->token == SKL_TKN_UUID)
1682 memcpy(&mconfig->guid, &uuid_tkn->uuid, 16);
1683 else {
1684 dev_err(dev, "Not an UUID token tkn %d", uuid_tkn->token);
1685 return -EINVAL;
1686 }
1687
1688 return 0;
1689}
1690
1691static void skl_tplg_fill_pin_dynamic_val(
1692 struct skl_module_pin *mpin, u32 pin_count, u32 value)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001693{
1694 int i;
1695
Shreyas NC6277e832016-08-12 12:29:51 +05301696 for (i = 0; i < pin_count; i++)
1697 mpin[i].is_dynamic = value;
1698}
1699
1700/*
1701 * Parse tokens to fill up the module private data
1702 */
1703static int skl_tplg_get_token(struct device *dev,
1704 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
1705 struct skl *skl, struct skl_module_cfg *mconfig)
1706{
1707 int tkn_count = 0;
1708 int ret;
1709 static int is_pipe_exists;
1710 static int pin_index, dir;
1711
1712 if (tkn_elem->token > SKL_TKN_MAX)
1713 return -EINVAL;
1714
1715 switch (tkn_elem->token) {
1716 case SKL_TKN_U8_IN_QUEUE_COUNT:
1717 mconfig->max_in_queue = tkn_elem->value;
1718 mconfig->m_in_pin = devm_kzalloc(dev, mconfig->max_in_queue *
1719 sizeof(*mconfig->m_in_pin),
1720 GFP_KERNEL);
1721 if (!mconfig->m_in_pin)
1722 return -ENOMEM;
1723
1724 break;
1725
1726 case SKL_TKN_U8_OUT_QUEUE_COUNT:
1727 mconfig->max_out_queue = tkn_elem->value;
1728 mconfig->m_out_pin = devm_kzalloc(dev, mconfig->max_out_queue *
1729 sizeof(*mconfig->m_out_pin),
1730 GFP_KERNEL);
1731
1732 if (!mconfig->m_out_pin)
1733 return -ENOMEM;
1734
1735 break;
1736
1737 case SKL_TKN_U8_DYN_IN_PIN:
1738 if (!mconfig->m_in_pin)
1739 return -ENOMEM;
1740
1741 skl_tplg_fill_pin_dynamic_val(mconfig->m_in_pin,
1742 mconfig->max_in_queue, tkn_elem->value);
1743
1744 break;
1745
1746 case SKL_TKN_U8_DYN_OUT_PIN:
1747 if (!mconfig->m_out_pin)
1748 return -ENOMEM;
1749
1750 skl_tplg_fill_pin_dynamic_val(mconfig->m_out_pin,
1751 mconfig->max_out_queue, tkn_elem->value);
1752
1753 break;
1754
1755 case SKL_TKN_U8_TIME_SLOT:
1756 mconfig->time_slot = tkn_elem->value;
1757 break;
1758
1759 case SKL_TKN_U8_CORE_ID:
1760 mconfig->core_id = tkn_elem->value;
1761
1762 case SKL_TKN_U8_MOD_TYPE:
1763 mconfig->m_type = tkn_elem->value;
1764 break;
1765
1766 case SKL_TKN_U8_DEV_TYPE:
1767 mconfig->dev_type = tkn_elem->value;
1768 break;
1769
1770 case SKL_TKN_U8_HW_CONN_TYPE:
1771 mconfig->hw_conn_type = tkn_elem->value;
1772 break;
1773
1774 case SKL_TKN_U16_MOD_INST_ID:
1775 mconfig->id.instance_id =
1776 tkn_elem->value;
1777 break;
1778
1779 case SKL_TKN_U32_MEM_PAGES:
1780 mconfig->mem_pages = tkn_elem->value;
1781 break;
1782
1783 case SKL_TKN_U32_MAX_MCPS:
1784 mconfig->mcps = tkn_elem->value;
1785 break;
1786
1787 case SKL_TKN_U32_OBS:
1788 mconfig->obs = tkn_elem->value;
1789 break;
1790
1791 case SKL_TKN_U32_IBS:
1792 mconfig->ibs = tkn_elem->value;
1793 break;
1794
1795 case SKL_TKN_U32_VBUS_ID:
1796 mconfig->vbus_id = tkn_elem->value;
1797 break;
1798
1799 case SKL_TKN_U32_PARAMS_FIXUP:
1800 mconfig->params_fixup = tkn_elem->value;
1801 break;
1802
1803 case SKL_TKN_U32_CONVERTER:
1804 mconfig->converter = tkn_elem->value;
1805 break;
1806
1807 case SKL_TKN_U32_PIPE_ID:
1808 ret = skl_tplg_add_pipe(dev,
1809 mconfig, skl, tkn_elem);
1810
1811 if (ret < 0)
1812 return is_pipe_exists;
1813
1814 if (ret == EEXIST)
1815 is_pipe_exists = 1;
1816
1817 break;
1818
1819 case SKL_TKN_U32_PIPE_CONN_TYPE:
1820 case SKL_TKN_U32_PIPE_PRIORITY:
1821 case SKL_TKN_U32_PIPE_MEM_PGS:
1822 if (is_pipe_exists) {
1823 ret = skl_tplg_fill_pipe_tkn(dev, mconfig->pipe,
1824 tkn_elem->token, tkn_elem->value);
1825 if (ret < 0)
1826 return ret;
1827 }
1828
1829 break;
1830
1831 /*
1832 * SKL_TKN_U32_DIR_PIN_COUNT token has the value for both
1833 * direction and the pin count. The first four bits represent
1834 * direction and next four the pin count.
1835 */
1836 case SKL_TKN_U32_DIR_PIN_COUNT:
1837 dir = tkn_elem->value & SKL_IN_DIR_BIT_MASK;
1838 pin_index = (tkn_elem->value &
1839 SKL_PIN_COUNT_MASK) >> 4;
1840
1841 break;
1842
1843 case SKL_TKN_U32_FMT_CH:
1844 case SKL_TKN_U32_FMT_FREQ:
1845 case SKL_TKN_U32_FMT_BIT_DEPTH:
1846 case SKL_TKN_U32_FMT_SAMPLE_SIZE:
1847 case SKL_TKN_U32_FMT_CH_CONFIG:
1848 case SKL_TKN_U32_FMT_INTERLEAVE:
1849 case SKL_TKN_U32_FMT_SAMPLE_TYPE:
1850 case SKL_TKN_U32_FMT_CH_MAP:
1851 ret = skl_tplg_fill_fmt(dev, mconfig, tkn_elem->token,
1852 tkn_elem->value, dir, pin_index);
1853
1854 if (ret < 0)
1855 return ret;
1856
1857 break;
1858
1859 case SKL_TKN_U32_PIN_MOD_ID:
1860 case SKL_TKN_U32_PIN_INST_ID:
1861 ret = skl_tplg_fill_pins_info(dev,
1862 mconfig, tkn_elem, dir,
1863 pin_index);
1864 if (ret < 0)
1865 return ret;
1866
1867 break;
1868
1869 case SKL_TKN_U32_CAPS_SIZE:
1870 mconfig->formats_config.caps_size =
1871 tkn_elem->value;
1872
1873 break;
1874
1875 case SKL_TKN_U32_PROC_DOMAIN:
1876 mconfig->domain =
1877 tkn_elem->value;
1878
1879 break;
1880
1881 case SKL_TKN_U8_IN_PIN_TYPE:
1882 case SKL_TKN_U8_OUT_PIN_TYPE:
1883 case SKL_TKN_U8_CONN_TYPE:
1884 break;
1885
1886 default:
1887 dev_err(dev, "Token %d not handled\n",
1888 tkn_elem->token);
1889 return -EINVAL;
Hardik T Shah4cd98992015-10-27 09:22:55 +09001890 }
Shreyas NC6277e832016-08-12 12:29:51 +05301891
1892 tkn_count++;
1893
1894 return tkn_count;
1895}
1896
1897/*
1898 * Parse the vendor array for specific tokens to construct
1899 * module private data
1900 */
1901static int skl_tplg_get_tokens(struct device *dev,
1902 char *pvt_data, struct skl *skl,
1903 struct skl_module_cfg *mconfig, int block_size)
1904{
1905 struct snd_soc_tplg_vendor_array *array;
1906 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
1907 int tkn_count = 0, ret;
1908 int off = 0, tuple_size = 0;
1909
1910 if (block_size <= 0)
1911 return -EINVAL;
1912
1913 while (tuple_size < block_size) {
1914 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
1915
1916 off += array->size;
1917
1918 switch (array->type) {
1919 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
1920 dev_warn(dev, "no string tokens expected for skl tplg");
1921 continue;
1922
1923 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
1924 ret = skl_tplg_get_uuid(dev, mconfig, array->uuid);
1925 if (ret < 0)
1926 return ret;
1927
1928 tuple_size += sizeof(*array->uuid);
1929
1930 continue;
1931
1932 default:
1933 tkn_elem = array->value;
1934 tkn_count = 0;
1935 break;
1936 }
1937
1938 while (tkn_count <= (array->num_elems - 1)) {
1939 ret = skl_tplg_get_token(dev, tkn_elem,
1940 skl, mconfig);
1941
1942 if (ret < 0)
1943 return ret;
1944
1945 tkn_count = tkn_count + ret;
1946 tkn_elem++;
1947 }
1948
1949 tuple_size += tkn_count * sizeof(*tkn_elem);
1950 }
1951
1952 return 0;
1953}
1954
1955/*
1956 * Every data block is preceded by a descriptor to read the number
1957 * of data blocks, they type of the block and it's size
1958 */
1959static int skl_tplg_get_desc_blocks(struct device *dev,
1960 struct snd_soc_tplg_vendor_array *array)
1961{
1962 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
1963
1964 tkn_elem = array->value;
1965
1966 switch (tkn_elem->token) {
1967 case SKL_TKN_U8_NUM_BLOCKS:
1968 case SKL_TKN_U8_BLOCK_TYPE:
1969 case SKL_TKN_U16_BLOCK_SIZE:
1970 return tkn_elem->value;
1971
1972 default:
1973 dev_err(dev, "Invalid descriptor token %d", tkn_elem->token);
1974 break;
1975 }
1976
1977 return -EINVAL;
1978}
1979
1980/*
1981 * Parse the private data for the token and corresponding value.
1982 * The private data can have multiple data blocks. So, a data block
1983 * is preceded by a descriptor for number of blocks and a descriptor
1984 * for the type and size of the suceeding data block.
1985 */
1986static int skl_tplg_get_pvt_data(struct snd_soc_tplg_dapm_widget *tplg_w,
1987 struct skl *skl, struct device *dev,
1988 struct skl_module_cfg *mconfig)
1989{
1990 struct snd_soc_tplg_vendor_array *array;
1991 int num_blocks, block_size = 0, block_type, off = 0;
1992 char *data;
1993 int ret;
1994
1995 /* Read the NUM_DATA_BLOCKS descriptor */
1996 array = (struct snd_soc_tplg_vendor_array *)tplg_w->priv.data;
1997 ret = skl_tplg_get_desc_blocks(dev, array);
1998 if (ret < 0)
1999 return ret;
2000 num_blocks = ret;
2001
2002 off += array->size;
2003 array = (struct snd_soc_tplg_vendor_array *)(tplg_w->priv.data + off);
2004
2005 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2006 while (num_blocks > 0) {
2007 ret = skl_tplg_get_desc_blocks(dev, array);
2008
2009 if (ret < 0)
2010 return ret;
2011 block_type = ret;
2012 off += array->size;
2013
2014 array = (struct snd_soc_tplg_vendor_array *)
2015 (tplg_w->priv.data + off);
2016
2017 ret = skl_tplg_get_desc_blocks(dev, array);
2018
2019 if (ret < 0)
2020 return ret;
2021 block_size = ret;
2022 off += array->size;
2023
2024 array = (struct snd_soc_tplg_vendor_array *)
2025 (tplg_w->priv.data + off);
2026
2027 data = (tplg_w->priv.data + off);
2028
2029 if (block_type == SKL_TYPE_TUPLE) {
2030 ret = skl_tplg_get_tokens(dev, data,
2031 skl, mconfig, block_size);
2032
2033 if (ret < 0)
2034 return ret;
2035
2036 --num_blocks;
2037 } else {
2038 if (mconfig->formats_config.caps_size > 0)
2039 memcpy(mconfig->formats_config.caps, data,
2040 mconfig->formats_config.caps_size);
2041 --num_blocks;
2042 }
2043 }
2044
2045 return 0;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002046}
2047
Dharageswari Rfe3f4442016-06-03 18:29:39 +05302048static void skl_clear_pin_config(struct snd_soc_platform *platform,
2049 struct snd_soc_dapm_widget *w)
2050{
2051 int i;
2052 struct skl_module_cfg *mconfig;
2053 struct skl_pipe *pipe;
2054
2055 if (!strncmp(w->dapm->component->name, platform->component.name,
2056 strlen(platform->component.name))) {
2057 mconfig = w->priv;
2058 pipe = mconfig->pipe;
2059 for (i = 0; i < mconfig->max_in_queue; i++) {
2060 mconfig->m_in_pin[i].in_use = false;
2061 mconfig->m_in_pin[i].pin_state = SKL_PIN_UNBIND;
2062 }
2063 for (i = 0; i < mconfig->max_out_queue; i++) {
2064 mconfig->m_out_pin[i].in_use = false;
2065 mconfig->m_out_pin[i].pin_state = SKL_PIN_UNBIND;
2066 }
2067 pipe->state = SKL_PIPE_INVALID;
2068 mconfig->m_state = SKL_MODULE_UNINIT;
2069 }
2070}
2071
2072void skl_cleanup_resources(struct skl *skl)
2073{
2074 struct skl_sst *ctx = skl->skl_sst;
2075 struct snd_soc_platform *soc_platform = skl->platform;
2076 struct snd_soc_dapm_widget *w;
2077 struct snd_soc_card *card;
2078
2079 if (soc_platform == NULL)
2080 return;
2081
2082 card = soc_platform->component.card;
2083 if (!card || !card->instantiated)
2084 return;
2085
2086 skl->resource.mem = 0;
2087 skl->resource.mcps = 0;
2088
2089 list_for_each_entry(w, &card->widgets, list) {
2090 if (is_skl_dsp_widget_type(w) && (w->priv != NULL))
2091 skl_clear_pin_config(soc_platform, w);
2092 }
2093
2094 skl_clear_module_cnt(ctx->dsp);
2095}
2096
Vinod Koul3af36702015-10-07 11:31:56 +01002097/*
2098 * Topology core widget load callback
2099 *
2100 * This is used to save the private data for each widget which gives
2101 * information to the driver about module and pipeline parameters which DSP
2102 * FW expects like ids, resource values, formats etc
2103 */
2104static int skl_tplg_widget_load(struct snd_soc_component *cmpnt,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002105 struct snd_soc_dapm_widget *w,
2106 struct snd_soc_tplg_dapm_widget *tplg_w)
Vinod Koul3af36702015-10-07 11:31:56 +01002107{
2108 int ret;
2109 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2110 struct skl *skl = ebus_to_skl(ebus);
2111 struct hdac_bus *bus = ebus_to_hbus(ebus);
2112 struct skl_module_cfg *mconfig;
Vinod Koul3af36702015-10-07 11:31:56 +01002113
2114 if (!tplg_w->priv.size)
2115 goto bind_event;
2116
2117 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
2118
2119 if (!mconfig)
2120 return -ENOMEM;
2121
2122 w->priv = mconfig;
Shreyas NC09305da2016-04-21 11:45:22 +05302123
Vinod Koulb7c50552016-07-26 18:06:40 +05302124 /*
2125 * module binary can be loaded later, so set it to query when
2126 * module is load for a use case
2127 */
2128 mconfig->id.module_id = -1;
Hardik T Shah4cd98992015-10-27 09:22:55 +09002129
Shreyas NC6277e832016-08-12 12:29:51 +05302130 /* Parse private data for tuples */
2131 ret = skl_tplg_get_pvt_data(tplg_w, skl, bus->dev, mconfig);
2132 if (ret < 0)
2133 return ret;
Vinod Koul3af36702015-10-07 11:31:56 +01002134bind_event:
2135 if (tplg_w->event_type == 0) {
Vinod Koul3373f712015-10-07 16:39:38 +01002136 dev_dbg(bus->dev, "ASoC: No event handler required\n");
Vinod Koul3af36702015-10-07 11:31:56 +01002137 return 0;
2138 }
2139
2140 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
Jeeja KPb663a8c2015-10-07 11:31:57 +01002141 ARRAY_SIZE(skl_tplg_widget_ops),
2142 tplg_w->event_type);
Vinod Koul3af36702015-10-07 11:31:56 +01002143
2144 if (ret) {
2145 dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
2146 __func__, tplg_w->event_type);
2147 return -EINVAL;
2148 }
2149
2150 return 0;
2151}
2152
Jeeja KP140adfb2015-11-28 15:01:50 +05302153static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
2154 struct snd_soc_tplg_bytes_control *bc)
2155{
2156 struct skl_algo_data *ac;
2157 struct skl_dfw_algo_data *dfw_ac =
2158 (struct skl_dfw_algo_data *)bc->priv.data;
2159
2160 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
2161 if (!ac)
2162 return -ENOMEM;
2163
2164 /* Fill private data */
2165 ac->max = dfw_ac->max;
2166 ac->param_id = dfw_ac->param_id;
2167 ac->set_params = dfw_ac->set_params;
Dharageswari R0d682102016-07-08 18:15:03 +05302168 ac->size = dfw_ac->max;
Jeeja KP140adfb2015-11-28 15:01:50 +05302169
2170 if (ac->max) {
2171 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL);
2172 if (!ac->params)
2173 return -ENOMEM;
2174
Alan Coxedd7ea22016-02-22 09:37:27 +05302175 memcpy(ac->params, dfw_ac->params, ac->max);
Jeeja KP140adfb2015-11-28 15:01:50 +05302176 }
2177
2178 be->dobj.private = ac;
2179 return 0;
2180}
2181
2182static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
2183 struct snd_kcontrol_new *kctl,
2184 struct snd_soc_tplg_ctl_hdr *hdr)
2185{
2186 struct soc_bytes_ext *sb;
2187 struct snd_soc_tplg_bytes_control *tplg_bc;
2188 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2189 struct hdac_bus *bus = ebus_to_hbus(ebus);
2190
2191 switch (hdr->ops.info) {
2192 case SND_SOC_TPLG_CTL_BYTES:
2193 tplg_bc = container_of(hdr,
2194 struct snd_soc_tplg_bytes_control, hdr);
2195 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
2196 sb = (struct soc_bytes_ext *)kctl->private_value;
2197 if (tplg_bc->priv.size)
2198 return skl_init_algo_data(
2199 bus->dev, sb, tplg_bc);
2200 }
2201 break;
2202
2203 default:
2204 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n",
2205 hdr->ops.get, hdr->ops.put, hdr->ops.info);
2206 break;
2207 }
2208
2209 return 0;
2210}
2211
Shreyas NC541070c2016-08-23 09:31:03 +05302212static int skl_tplg_fill_str_mfest_tkn(struct device *dev,
2213 struct snd_soc_tplg_vendor_string_elem *str_elem,
2214 struct skl_dfw_manifest *minfo)
2215{
2216 int tkn_count = 0;
2217 static int ref_count;
2218
2219 switch (str_elem->token) {
2220 case SKL_TKN_STR_LIB_NAME:
2221 if (ref_count > minfo->lib_count - 1) {
2222 ref_count = 0;
2223 return -EINVAL;
2224 }
2225
2226 strncpy(minfo->lib[ref_count].name, str_elem->string,
2227 ARRAY_SIZE(minfo->lib[ref_count].name));
2228 ref_count++;
2229 tkn_count++;
2230 break;
2231
2232 default:
2233 dev_err(dev, "Not a string token %d", str_elem->token);
2234 break;
2235 }
2236
2237 return tkn_count;
2238}
2239
2240static int skl_tplg_get_str_tkn(struct device *dev,
2241 struct snd_soc_tplg_vendor_array *array,
2242 struct skl_dfw_manifest *minfo)
2243{
2244 int tkn_count = 0, ret;
2245 struct snd_soc_tplg_vendor_string_elem *str_elem;
2246
2247 str_elem = (struct snd_soc_tplg_vendor_string_elem *)array->value;
2248 while (tkn_count < array->num_elems) {
2249 ret = skl_tplg_fill_str_mfest_tkn(dev, str_elem, minfo);
2250 str_elem++;
2251
2252 if (ret < 0)
2253 return ret;
2254
2255 tkn_count = tkn_count + ret;
2256 }
2257
2258 return tkn_count;
2259}
2260
2261static int skl_tplg_get_int_tkn(struct device *dev,
2262 struct snd_soc_tplg_vendor_value_elem *tkn_elem,
2263 struct skl_dfw_manifest *minfo)
2264{
2265 int tkn_count = 0;
2266
2267 switch (tkn_elem->token) {
2268 case SKL_TKN_U32_LIB_COUNT:
2269 minfo->lib_count = tkn_elem->value;
2270 tkn_count++;
2271 break;
2272
2273 default:
2274 dev_err(dev, "Not a manifest token %d", tkn_elem->token);
2275 return -EINVAL;
2276 }
2277
2278 return tkn_count;
2279}
2280
2281/*
2282 * Fill the manifest structure by parsing the tokens based on the
2283 * type.
2284 */
2285static int skl_tplg_get_manifest_tkn(struct device *dev,
2286 char *pvt_data, struct skl_dfw_manifest *minfo,
2287 int block_size)
2288{
2289 int tkn_count = 0, ret;
2290 int off = 0, tuple_size = 0;
2291 struct snd_soc_tplg_vendor_array *array;
2292 struct snd_soc_tplg_vendor_value_elem *tkn_elem;
2293
2294 if (block_size <= 0)
2295 return -EINVAL;
2296
2297 while (tuple_size < block_size) {
2298 array = (struct snd_soc_tplg_vendor_array *)(pvt_data + off);
2299 off += array->size;
2300 switch (array->type) {
2301 case SND_SOC_TPLG_TUPLE_TYPE_STRING:
2302 ret = skl_tplg_get_str_tkn(dev, array, minfo);
2303
2304 if (ret < 0)
2305 return ret;
2306 tkn_count += ret;
2307
2308 tuple_size += tkn_count *
2309 sizeof(struct snd_soc_tplg_vendor_string_elem);
2310 continue;
2311
2312 case SND_SOC_TPLG_TUPLE_TYPE_UUID:
2313 dev_warn(dev, "no uuid tokens for skl tplf manifest");
2314 continue;
2315
2316 default:
2317 tkn_elem = array->value;
2318 tkn_count = 0;
2319 break;
2320 }
2321
2322 while (tkn_count <= array->num_elems - 1) {
2323 ret = skl_tplg_get_int_tkn(dev,
2324 tkn_elem, minfo);
2325 if (ret < 0)
2326 return ret;
2327
2328 tkn_count = tkn_count + ret;
2329 tkn_elem++;
2330 tuple_size += tkn_count *
2331 sizeof(struct snd_soc_tplg_vendor_value_elem);
2332 break;
2333 }
2334 tkn_count = 0;
2335 }
2336
2337 return 0;
2338}
2339
2340/*
2341 * Parse manifest private data for tokens. The private data block is
2342 * preceded by descriptors for type and size of data block.
2343 */
2344static int skl_tplg_get_manifest_data(struct snd_soc_tplg_manifest *manifest,
2345 struct device *dev, struct skl_dfw_manifest *minfo)
2346{
2347 struct snd_soc_tplg_vendor_array *array;
2348 int num_blocks, block_size = 0, block_type, off = 0;
2349 char *data;
2350 int ret;
2351
2352 /* Read the NUM_DATA_BLOCKS descriptor */
2353 array = (struct snd_soc_tplg_vendor_array *)manifest->priv.data;
2354 ret = skl_tplg_get_desc_blocks(dev, array);
2355 if (ret < 0)
2356 return ret;
2357 num_blocks = ret;
2358
2359 off += array->size;
2360 array = (struct snd_soc_tplg_vendor_array *)
2361 (manifest->priv.data + off);
2362
2363 /* Read the BLOCK_TYPE and BLOCK_SIZE descriptor */
2364 while (num_blocks > 0) {
2365 ret = skl_tplg_get_desc_blocks(dev, array);
2366
2367 if (ret < 0)
2368 return ret;
2369 block_type = ret;
2370 off += array->size;
2371
2372 array = (struct snd_soc_tplg_vendor_array *)
2373 (manifest->priv.data + off);
2374
2375 ret = skl_tplg_get_desc_blocks(dev, array);
2376
2377 if (ret < 0)
2378 return ret;
2379 block_size = ret;
2380 off += array->size;
2381
2382 array = (struct snd_soc_tplg_vendor_array *)
2383 (manifest->priv.data + off);
2384
2385 data = (manifest->priv.data + off);
2386
2387 if (block_type == SKL_TYPE_TUPLE) {
2388 ret = skl_tplg_get_manifest_tkn(dev, data, minfo,
2389 block_size);
2390
2391 if (ret < 0)
2392 return ret;
2393
2394 --num_blocks;
2395 } else {
2396 return -EINVAL;
2397 }
2398 }
2399
2400 return 0;
2401}
2402
Kranthi G15ecaba92016-07-26 18:06:43 +05302403static int skl_manifest_load(struct snd_soc_component *cmpnt,
2404 struct snd_soc_tplg_manifest *manifest)
2405{
2406 struct skl_dfw_manifest *minfo;
2407 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
2408 struct hdac_bus *bus = ebus_to_hbus(ebus);
2409 struct skl *skl = ebus_to_skl(ebus);
2410 int ret = 0;
2411
Vinod Koulc15ad602016-08-24 18:03:13 +05302412 /* proceed only if we have private data defined */
2413 if (manifest->priv.size == 0)
2414 return 0;
2415
Kranthi G15ecaba92016-07-26 18:06:43 +05302416 minfo = &skl->skl_sst->manifest;
Shreyas NC541070c2016-08-23 09:31:03 +05302417
2418 skl_tplg_get_manifest_data(manifest, bus->dev, minfo);
Kranthi G15ecaba92016-07-26 18:06:43 +05302419
2420 if (minfo->lib_count > HDA_MAX_LIB) {
2421 dev_err(bus->dev, "Exceeding max Library count. Got:%d\n",
2422 minfo->lib_count);
2423 ret = -EINVAL;
2424 }
2425
2426 return ret;
2427}
2428
Vinod Koul3af36702015-10-07 11:31:56 +01002429static struct snd_soc_tplg_ops skl_tplg_ops = {
2430 .widget_load = skl_tplg_widget_load,
Jeeja KP140adfb2015-11-28 15:01:50 +05302431 .control_load = skl_tplg_control_load,
2432 .bytes_ext_ops = skl_tlv_ops,
2433 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
Kranthi G15ecaba92016-07-26 18:06:43 +05302434 .manifest = skl_manifest_load,
Vinod Koul3af36702015-10-07 11:31:56 +01002435};
2436
Jeeja KP287af4f2016-06-03 18:29:40 +05302437/*
2438 * A pipe can have multiple modules, each of them will be a DAPM widget as
2439 * well. While managing a pipeline we need to get the list of all the
2440 * widgets in a pipelines, so this helper - skl_tplg_create_pipe_widget_list()
2441 * helps to get the SKL type widgets in that pipeline
2442 */
2443static int skl_tplg_create_pipe_widget_list(struct snd_soc_platform *platform)
2444{
2445 struct snd_soc_dapm_widget *w;
2446 struct skl_module_cfg *mcfg = NULL;
2447 struct skl_pipe_module *p_module = NULL;
2448 struct skl_pipe *pipe;
2449
2450 list_for_each_entry(w, &platform->component.card->widgets, list) {
2451 if (is_skl_dsp_widget_type(w) && w->priv != NULL) {
2452 mcfg = w->priv;
2453 pipe = mcfg->pipe;
2454
2455 p_module = devm_kzalloc(platform->dev,
2456 sizeof(*p_module), GFP_KERNEL);
2457 if (!p_module)
2458 return -ENOMEM;
2459
2460 p_module->w = w;
2461 list_add_tail(&p_module->node, &pipe->w_list);
2462 }
2463 }
2464
2465 return 0;
2466}
2467
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302468static void skl_tplg_set_pipe_type(struct skl *skl, struct skl_pipe *pipe)
2469{
2470 struct skl_pipe_module *w_module;
2471 struct snd_soc_dapm_widget *w;
2472 struct skl_module_cfg *mconfig;
2473 bool host_found = false, link_found = false;
2474
2475 list_for_each_entry(w_module, &pipe->w_list, node) {
2476 w = w_module->w;
2477 mconfig = w->priv;
2478
2479 if (mconfig->dev_type == SKL_DEVICE_HDAHOST)
2480 host_found = true;
2481 else if (mconfig->dev_type != SKL_DEVICE_NONE)
2482 link_found = true;
2483 }
2484
2485 if (host_found && link_found)
2486 pipe->passthru = true;
2487 else
2488 pipe->passthru = false;
2489}
2490
Vinod Koul3af36702015-10-07 11:31:56 +01002491/* This will be read from topology manifest, currently defined here */
2492#define SKL_MAX_MCPS 30000000
2493#define SKL_FW_MAX_MEM 1000000
2494
2495/*
2496 * SKL topology init routine
2497 */
2498int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus)
2499{
2500 int ret;
2501 const struct firmware *fw;
2502 struct hdac_bus *bus = ebus_to_hbus(ebus);
2503 struct skl *skl = ebus_to_skl(ebus);
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302504 struct skl_pipeline *ppl;
Vinod Koul3af36702015-10-07 11:31:56 +01002505
Vinod Koul4b235c42016-02-19 11:42:34 +05302506 ret = request_firmware(&fw, skl->tplg_name, bus->dev);
Vinod Koul3af36702015-10-07 11:31:56 +01002507 if (ret < 0) {
Jeeja KPb663a8c2015-10-07 11:31:57 +01002508 dev_err(bus->dev, "tplg fw %s load failed with %d\n",
Vinod Koul4b235c42016-02-19 11:42:34 +05302509 skl->tplg_name, ret);
2510 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
2511 if (ret < 0) {
2512 dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n",
2513 "dfw_sst.bin", ret);
2514 return ret;
2515 }
Vinod Koul3af36702015-10-07 11:31:56 +01002516 }
2517
2518 /*
2519 * The complete tplg for SKL is loaded as index 0, we don't use
2520 * any other index
2521 */
Jeeja KPb663a8c2015-10-07 11:31:57 +01002522 ret = snd_soc_tplg_component_load(&platform->component,
2523 &skl_tplg_ops, fw, 0);
Vinod Koul3af36702015-10-07 11:31:56 +01002524 if (ret < 0) {
2525 dev_err(bus->dev, "tplg component load failed%d\n", ret);
Sudip Mukherjeec14a82c2016-01-21 17:27:59 +05302526 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01002527 return -EINVAL;
2528 }
2529
2530 skl->resource.max_mcps = SKL_MAX_MCPS;
2531 skl->resource.max_mem = SKL_FW_MAX_MEM;
2532
Vinod Kould8018362016-01-05 17:16:04 +05302533 skl->tplg = fw;
Jeeja KP287af4f2016-06-03 18:29:40 +05302534 ret = skl_tplg_create_pipe_widget_list(platform);
2535 if (ret < 0)
2536 return ret;
Vinod Kould8018362016-01-05 17:16:04 +05302537
Jeeja KPf0aa94f2016-06-03 18:29:41 +05302538 list_for_each_entry(ppl, &skl->ppl_list, node)
2539 skl_tplg_set_pipe_type(skl, ppl->pipe);
Vinod Koul3af36702015-10-07 11:31:56 +01002540
2541 return 0;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +01002542}