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Jeeja KPe4e2d2f2015-10-07 11:31:52 +01001/*
2 * skl-topology.c - Implements Platform component ALSA controls/widget
3 * handlers.
4 *
5 * Copyright (C) 2014-2015 Intel Corp
6 * Author: Jeeja KP <jeeja.kp@intel.com>
7 * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
8 *
9 * This program is free software; you can redistribute it and/or modify
10 * it under the terms of the GNU General Public License as version 2, as
11 * published by the Free Software Foundation.
12 *
13 * This program is distributed in the hope that it will be useful, but
14 * WITHOUT ANY WARRANTY; without even the implied warranty of
15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
16 * General Public License for more details.
17 */
18
19#include <linux/slab.h>
20#include <linux/types.h>
21#include <linux/firmware.h>
22#include <sound/soc.h>
23#include <sound/soc-topology.h>
24#include "skl-sst-dsp.h"
25#include "skl-sst-ipc.h"
26#include "skl-topology.h"
27#include "skl.h"
28#include "skl-tplg-interface.h"
Dharageswari R6c5768b2015-12-03 23:29:50 +053029#include "../common/sst-dsp.h"
30#include "../common/sst-dsp-priv.h"
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010031
Jeeja KPf7590d42015-10-07 11:31:53 +010032#define SKL_CH_FIXUP_MASK (1 << 0)
33#define SKL_RATE_FIXUP_MASK (1 << 1)
34#define SKL_FMT_FIXUP_MASK (1 << 2)
35
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010036/*
37 * SKL DSP driver modelling uses only few DAPM widgets so for rest we will
38 * ignore. This helpers checks if the SKL driver handles this widget type
39 */
40static int is_skl_dsp_widget_type(struct snd_soc_dapm_widget *w)
41{
42 switch (w->id) {
43 case snd_soc_dapm_dai_link:
44 case snd_soc_dapm_dai_in:
45 case snd_soc_dapm_aif_in:
46 case snd_soc_dapm_aif_out:
47 case snd_soc_dapm_dai_out:
48 case snd_soc_dapm_switch:
49 return false;
50 default:
51 return true;
52 }
53}
54
55/*
56 * Each pipelines needs memory to be allocated. Check if we have free memory
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053057 * from available pool.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010058 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053059static bool skl_is_pipe_mem_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010060 struct skl_module_cfg *mconfig)
61{
62 struct skl_sst *ctx = skl->skl_sst;
63
64 if (skl->resource.mem + mconfig->pipe->memory_pages >
65 skl->resource.max_mem) {
66 dev_err(ctx->dev,
67 "%s: module_id %d instance %d\n", __func__,
68 mconfig->id.module_id,
69 mconfig->id.instance_id);
70 dev_err(ctx->dev,
71 "exceeds ppl memory available %d mem %d\n",
72 skl->resource.max_mem, skl->resource.mem);
73 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053074 } else {
75 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010076 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053077}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010078
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053079/*
80 * Add the mem to the mem pool. This is freed when pipe is deleted.
81 * Note: DSP does actual memory management we only keep track for complete
82 * pool
83 */
84static void skl_tplg_alloc_pipe_mem(struct skl *skl,
85 struct skl_module_cfg *mconfig)
86{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010087 skl->resource.mem += mconfig->pipe->memory_pages;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010088}
89
90/*
91 * Pipeline needs needs DSP CPU resources for computation, this is
92 * quantified in MCPS (Million Clocks Per Second) required for module/pipe
93 *
94 * Each pipelines needs mcps to be allocated. Check if we have mcps for this
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053095 * pipe.
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010096 */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +053097
98static bool skl_is_pipe_mcps_avail(struct skl *skl,
Jeeja KPe4e2d2f2015-10-07 11:31:52 +010099 struct skl_module_cfg *mconfig)
100{
101 struct skl_sst *ctx = skl->skl_sst;
102
103 if (skl->resource.mcps + mconfig->mcps > skl->resource.max_mcps) {
104 dev_err(ctx->dev,
105 "%s: module_id %d instance %d\n", __func__,
106 mconfig->id.module_id, mconfig->id.instance_id);
107 dev_err(ctx->dev,
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530108 "exceeds ppl mcps available %d > mem %d\n",
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100109 skl->resource.max_mcps, skl->resource.mcps);
110 return false;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530111 } else {
112 return true;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100113 }
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530114}
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100115
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530116static void skl_tplg_alloc_pipe_mcps(struct skl *skl,
117 struct skl_module_cfg *mconfig)
118{
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100119 skl->resource.mcps += mconfig->mcps;
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100120}
121
122/*
123 * Free the mcps when tearing down
124 */
125static void
126skl_tplg_free_pipe_mcps(struct skl *skl, struct skl_module_cfg *mconfig)
127{
128 skl->resource.mcps -= mconfig->mcps;
129}
130
131/*
132 * Free the memory when tearing down
133 */
134static void
135skl_tplg_free_pipe_mem(struct skl *skl, struct skl_module_cfg *mconfig)
136{
137 skl->resource.mem -= mconfig->pipe->memory_pages;
138}
139
Jeeja KPf7590d42015-10-07 11:31:53 +0100140
141static void skl_dump_mconfig(struct skl_sst *ctx,
142 struct skl_module_cfg *mcfg)
143{
144 dev_dbg(ctx->dev, "Dumping config\n");
145 dev_dbg(ctx->dev, "Input Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900146 dev_dbg(ctx->dev, "channels = %d\n", mcfg->in_fmt[0].channels);
147 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->in_fmt[0].s_freq);
148 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->in_fmt[0].ch_cfg);
149 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->in_fmt[0].valid_bit_depth);
Jeeja KPf7590d42015-10-07 11:31:53 +0100150 dev_dbg(ctx->dev, "Output Format:\n");
Hardik T Shah4cd98992015-10-27 09:22:55 +0900151 dev_dbg(ctx->dev, "channels = %d\n", mcfg->out_fmt[0].channels);
152 dev_dbg(ctx->dev, "s_freq = %d\n", mcfg->out_fmt[0].s_freq);
153 dev_dbg(ctx->dev, "valid bit depth = %d\n", mcfg->out_fmt[0].valid_bit_depth);
154 dev_dbg(ctx->dev, "ch_cfg = %d\n", mcfg->out_fmt[0].ch_cfg);
Jeeja KPf7590d42015-10-07 11:31:53 +0100155}
156
157static void skl_tplg_update_params(struct skl_module_fmt *fmt,
158 struct skl_pipe_params *params, int fixup)
159{
160 if (fixup & SKL_RATE_FIXUP_MASK)
161 fmt->s_freq = params->s_freq;
162 if (fixup & SKL_CH_FIXUP_MASK)
163 fmt->channels = params->ch;
Jeeja KP98256f82015-11-23 22:26:25 +0530164 if (fixup & SKL_FMT_FIXUP_MASK) {
165 fmt->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
166
167 /*
168 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
169 * container so update bit depth accordingly
170 */
171 switch (fmt->valid_bit_depth) {
172 case SKL_DEPTH_16BIT:
173 fmt->bit_depth = fmt->valid_bit_depth;
174 break;
175
176 default:
177 fmt->bit_depth = SKL_DEPTH_32BIT;
178 break;
179 }
180 }
181
Jeeja KPf7590d42015-10-07 11:31:53 +0100182}
183
184/*
185 * A pipeline may have modules which impact the pcm parameters, like SRC,
186 * channel converter, format converter.
187 * We need to calculate the output params by applying the 'fixup'
188 * Topology will tell driver which type of fixup is to be applied by
189 * supplying the fixup mask, so based on that we calculate the output
190 *
191 * Now In FE the pcm hw_params is source/target format. Same is applicable
192 * for BE with its hw_params invoked.
193 * here based on FE, BE pipeline and direction we calculate the input and
194 * outfix and then apply that for a module
195 */
196static void skl_tplg_update_params_fixup(struct skl_module_cfg *m_cfg,
197 struct skl_pipe_params *params, bool is_fe)
198{
199 int in_fixup, out_fixup;
200 struct skl_module_fmt *in_fmt, *out_fmt;
201
Hardik T Shah4cd98992015-10-27 09:22:55 +0900202 /* Fixups will be applied to pin 0 only */
203 in_fmt = &m_cfg->in_fmt[0];
204 out_fmt = &m_cfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100205
206 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
207 if (is_fe) {
208 in_fixup = m_cfg->params_fixup;
209 out_fixup = (~m_cfg->converter) &
210 m_cfg->params_fixup;
211 } else {
212 out_fixup = m_cfg->params_fixup;
213 in_fixup = (~m_cfg->converter) &
214 m_cfg->params_fixup;
215 }
216 } else {
217 if (is_fe) {
218 out_fixup = m_cfg->params_fixup;
219 in_fixup = (~m_cfg->converter) &
220 m_cfg->params_fixup;
221 } else {
222 in_fixup = m_cfg->params_fixup;
223 out_fixup = (~m_cfg->converter) &
224 m_cfg->params_fixup;
225 }
226 }
227
228 skl_tplg_update_params(in_fmt, params, in_fixup);
229 skl_tplg_update_params(out_fmt, params, out_fixup);
230}
231
232/*
233 * A module needs input and output buffers, which are dependent upon pcm
234 * params, so once we have calculate params, we need buffer calculation as
235 * well.
236 */
237static void skl_tplg_update_buffer_size(struct skl_sst *ctx,
238 struct skl_module_cfg *mcfg)
239{
240 int multiplier = 1;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900241 struct skl_module_fmt *in_fmt, *out_fmt;
242
243
244 /* Since fixups is applied to pin 0 only, ibs, obs needs
245 * change for pin 0 only
246 */
247 in_fmt = &mcfg->in_fmt[0];
248 out_fmt = &mcfg->out_fmt[0];
Jeeja KPf7590d42015-10-07 11:31:53 +0100249
250 if (mcfg->m_type == SKL_MODULE_TYPE_SRCINT)
251 multiplier = 5;
Hardik T Shah4cd98992015-10-27 09:22:55 +0900252 mcfg->ibs = (in_fmt->s_freq / 1000) *
253 (mcfg->in_fmt->channels) *
254 (mcfg->in_fmt->bit_depth >> 3) *
Jeeja KPf7590d42015-10-07 11:31:53 +0100255 multiplier;
256
Hardik T Shah4cd98992015-10-27 09:22:55 +0900257 mcfg->obs = (mcfg->out_fmt->s_freq / 1000) *
258 (mcfg->out_fmt->channels) *
259 (mcfg->out_fmt->bit_depth >> 3) *
Jeeja KPf7590d42015-10-07 11:31:53 +0100260 multiplier;
261}
262
Jeeja KP2d1419a2016-02-05 12:19:10 +0530263static int skl_tplg_update_be_blob(struct snd_soc_dapm_widget *w,
264 struct skl_sst *ctx)
265{
266 struct skl_module_cfg *m_cfg = w->priv;
267 int link_type, dir;
268 u32 ch, s_freq, s_fmt;
269 struct nhlt_specific_cfg *cfg;
270 struct skl *skl = get_skl_ctx(ctx->dev);
271
272 /* check if we already have blob */
273 if (m_cfg->formats_config.caps_size > 0)
274 return 0;
275
Jeeja KPc7c6c732016-03-01 07:59:10 +0530276 dev_dbg(ctx->dev, "Applying default cfg blob\n");
Jeeja KP2d1419a2016-02-05 12:19:10 +0530277 switch (m_cfg->dev_type) {
278 case SKL_DEVICE_DMIC:
279 link_type = NHLT_LINK_DMIC;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530280 dir = SNDRV_PCM_STREAM_CAPTURE;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530281 s_freq = m_cfg->in_fmt[0].s_freq;
282 s_fmt = m_cfg->in_fmt[0].bit_depth;
283 ch = m_cfg->in_fmt[0].channels;
284 break;
285
286 case SKL_DEVICE_I2S:
287 link_type = NHLT_LINK_SSP;
288 if (m_cfg->hw_conn_type == SKL_CONN_SOURCE) {
Jeeja KPc7c6c732016-03-01 07:59:10 +0530289 dir = SNDRV_PCM_STREAM_PLAYBACK;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530290 s_freq = m_cfg->out_fmt[0].s_freq;
291 s_fmt = m_cfg->out_fmt[0].bit_depth;
292 ch = m_cfg->out_fmt[0].channels;
Jeeja KPc7c6c732016-03-01 07:59:10 +0530293 } else {
294 dir = SNDRV_PCM_STREAM_CAPTURE;
295 s_freq = m_cfg->in_fmt[0].s_freq;
296 s_fmt = m_cfg->in_fmt[0].bit_depth;
297 ch = m_cfg->in_fmt[0].channels;
Jeeja KP2d1419a2016-02-05 12:19:10 +0530298 }
299 break;
300
301 default:
302 return -EINVAL;
303 }
304
305 /* update the blob based on virtual bus_id and default params */
306 cfg = skl_get_ep_blob(skl, m_cfg->vbus_id, link_type,
307 s_fmt, ch, s_freq, dir);
308 if (cfg) {
309 m_cfg->formats_config.caps_size = cfg->size;
310 m_cfg->formats_config.caps = (u32 *) &cfg->caps;
311 } else {
312 dev_err(ctx->dev, "Blob NULL for id %x type %d dirn %d\n",
313 m_cfg->vbus_id, link_type, dir);
314 dev_err(ctx->dev, "PCM: ch %d, freq %d, fmt %d\n",
315 ch, s_freq, s_fmt);
316 return -EIO;
317 }
318
319 return 0;
320}
321
Jeeja KPf7590d42015-10-07 11:31:53 +0100322static void skl_tplg_update_module_params(struct snd_soc_dapm_widget *w,
323 struct skl_sst *ctx)
324{
325 struct skl_module_cfg *m_cfg = w->priv;
326 struct skl_pipe_params *params = m_cfg->pipe->p_params;
327 int p_conn_type = m_cfg->pipe->conn_type;
328 bool is_fe;
329
330 if (!m_cfg->params_fixup)
331 return;
332
333 dev_dbg(ctx->dev, "Mconfig for widget=%s BEFORE updation\n",
334 w->name);
335
336 skl_dump_mconfig(ctx, m_cfg);
337
338 if (p_conn_type == SKL_PIPE_CONN_TYPE_FE)
339 is_fe = true;
340 else
341 is_fe = false;
342
343 skl_tplg_update_params_fixup(m_cfg, params, is_fe);
344 skl_tplg_update_buffer_size(ctx, m_cfg);
345
346 dev_dbg(ctx->dev, "Mconfig for widget=%s AFTER updation\n",
347 w->name);
348
349 skl_dump_mconfig(ctx, m_cfg);
350}
351
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100352/*
353 * A pipe can have multiple modules, each of them will be a DAPM widget as
354 * well. While managing a pipeline we need to get the list of all the
355 * widgets in a pipelines, so this helper - skl_tplg_get_pipe_widget() helps
356 * to get the SKL type widgets in that pipeline
357 */
358static int skl_tplg_alloc_pipe_widget(struct device *dev,
359 struct snd_soc_dapm_widget *w, struct skl_pipe *pipe)
360{
361 struct skl_module_cfg *src_module = NULL;
362 struct snd_soc_dapm_path *p = NULL;
363 struct skl_pipe_module *p_module = NULL;
364
365 p_module = devm_kzalloc(dev, sizeof(*p_module), GFP_KERNEL);
366 if (!p_module)
367 return -ENOMEM;
368
369 p_module->w = w;
370 list_add_tail(&p_module->node, &pipe->w_list);
371
372 snd_soc_dapm_widget_for_each_sink_path(w, p) {
373 if ((p->sink->priv == NULL)
374 && (!is_skl_dsp_widget_type(w)))
375 continue;
376
377 if ((p->sink->priv != NULL) && p->connect
378 && is_skl_dsp_widget_type(p->sink)) {
379
380 src_module = p->sink->priv;
381 if (pipe->ppl_id == src_module->pipe->ppl_id)
382 skl_tplg_alloc_pipe_widget(dev,
383 p->sink, pipe);
384 }
385 }
386 return 0;
387}
388
389/*
Jeeja KPabb74002015-11-28 15:01:49 +0530390 * some modules can have multiple params set from user control and
391 * need to be set after module is initialized. If set_param flag is
392 * set module params will be done after module is initialised.
393 */
394static int skl_tplg_set_module_params(struct snd_soc_dapm_widget *w,
395 struct skl_sst *ctx)
396{
397 int i, ret;
398 struct skl_module_cfg *mconfig = w->priv;
399 const struct snd_kcontrol_new *k;
400 struct soc_bytes_ext *sb;
401 struct skl_algo_data *bc;
402 struct skl_specific_cfg *sp_cfg;
403
404 if (mconfig->formats_config.caps_size > 0 &&
Jeeja KP4ced1822015-12-03 23:29:53 +0530405 mconfig->formats_config.set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530406 sp_cfg = &mconfig->formats_config;
407 ret = skl_set_module_params(ctx, sp_cfg->caps,
408 sp_cfg->caps_size,
409 sp_cfg->param_id, mconfig);
410 if (ret < 0)
411 return ret;
412 }
413
414 for (i = 0; i < w->num_kcontrols; i++) {
415 k = &w->kcontrol_news[i];
416 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
417 sb = (void *) k->private_value;
418 bc = (struct skl_algo_data *)sb->dobj.private;
419
Jeeja KP4ced1822015-12-03 23:29:53 +0530420 if (bc->set_params == SKL_PARAM_SET) {
Jeeja KPabb74002015-11-28 15:01:49 +0530421 ret = skl_set_module_params(ctx,
422 (u32 *)bc->params, bc->max,
423 bc->param_id, mconfig);
424 if (ret < 0)
425 return ret;
426 }
427 }
428 }
429
430 return 0;
431}
432
433/*
434 * some module param can set from user control and this is required as
435 * when module is initailzed. if module param is required in init it is
436 * identifed by set_param flag. if set_param flag is not set, then this
437 * parameter needs to set as part of module init.
438 */
439static int skl_tplg_set_module_init_data(struct snd_soc_dapm_widget *w)
440{
441 const struct snd_kcontrol_new *k;
442 struct soc_bytes_ext *sb;
443 struct skl_algo_data *bc;
444 struct skl_module_cfg *mconfig = w->priv;
445 int i;
446
447 for (i = 0; i < w->num_kcontrols; i++) {
448 k = &w->kcontrol_news[i];
449 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
450 sb = (struct soc_bytes_ext *)k->private_value;
451 bc = (struct skl_algo_data *)sb->dobj.private;
452
Jeeja KP4ced1822015-12-03 23:29:53 +0530453 if (bc->set_params != SKL_PARAM_INIT)
Jeeja KPabb74002015-11-28 15:01:49 +0530454 continue;
455
456 mconfig->formats_config.caps = (u32 *)&bc->params;
457 mconfig->formats_config.caps_size = bc->max;
458
459 break;
460 }
461 }
462
463 return 0;
464}
465
466/*
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100467 * Inside a pipe instance, we can have various modules. These modules need
468 * to instantiated in DSP by invoking INIT_MODULE IPC, which is achieved by
469 * skl_init_module() routine, so invoke that for all modules in a pipeline
470 */
471static int
472skl_tplg_init_pipe_modules(struct skl *skl, struct skl_pipe *pipe)
473{
474 struct skl_pipe_module *w_module;
475 struct snd_soc_dapm_widget *w;
476 struct skl_module_cfg *mconfig;
477 struct skl_sst *ctx = skl->skl_sst;
478 int ret = 0;
479
480 list_for_each_entry(w_module, &pipe->w_list, node) {
481 w = w_module->w;
482 mconfig = w->priv;
483
484 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530485 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100486 return -ENOMEM;
487
Dharageswari R6c5768b2015-12-03 23:29:50 +0530488 if (mconfig->is_loadable && ctx->dsp->fw_ops.load_mod) {
489 ret = ctx->dsp->fw_ops.load_mod(ctx->dsp,
490 mconfig->id.module_id, mconfig->guid);
491 if (ret < 0)
492 return ret;
Jeeja KPd6436782016-03-28 22:11:30 +0530493
494 mconfig->m_state = SKL_MODULE_LOADED;
Dharageswari R6c5768b2015-12-03 23:29:50 +0530495 }
496
Jeeja KP2d1419a2016-02-05 12:19:10 +0530497 /* update blob if blob is null for be with default value */
498 skl_tplg_update_be_blob(w, ctx);
499
Jeeja KPf7590d42015-10-07 11:31:53 +0100500 /*
501 * apply fix/conversion to module params based on
502 * FE/BE params
503 */
504 skl_tplg_update_module_params(w, ctx);
Jeeja KPabb74002015-11-28 15:01:49 +0530505
506 skl_tplg_set_module_init_data(w);
Jeeja KP9939a9c2015-11-28 15:01:47 +0530507 ret = skl_init_module(ctx, mconfig);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100508 if (ret < 0)
509 return ret;
Jeeja KPabb74002015-11-28 15:01:49 +0530510
511 ret = skl_tplg_set_module_params(w, ctx);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100512 if (ret < 0)
513 return ret;
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530514 skl_tplg_alloc_pipe_mcps(skl, mconfig);
Jeeja KPe4e2d2f2015-10-07 11:31:52 +0100515 }
516
517 return 0;
518}
Vinod Kould93f8e52015-10-07 11:31:54 +0100519
Dharageswari R6c5768b2015-12-03 23:29:50 +0530520static int skl_tplg_unload_pipe_modules(struct skl_sst *ctx,
521 struct skl_pipe *pipe)
522{
523 struct skl_pipe_module *w_module = NULL;
524 struct skl_module_cfg *mconfig = NULL;
525
526 list_for_each_entry(w_module, &pipe->w_list, node) {
527 mconfig = w_module->w->priv;
528
Jeeja KPd6436782016-03-28 22:11:30 +0530529 if (mconfig->is_loadable && ctx->dsp->fw_ops.unload_mod &&
530 mconfig->m_state > SKL_MODULE_UNINIT)
Dharageswari R6c5768b2015-12-03 23:29:50 +0530531 return ctx->dsp->fw_ops.unload_mod(ctx->dsp,
532 mconfig->id.module_id);
533 }
534
535 /* no modules to unload in this path, so return */
536 return 0;
537}
538
Vinod Kould93f8e52015-10-07 11:31:54 +0100539/*
540 * Mixer module represents a pipeline. So in the Pre-PMU event of mixer we
541 * need create the pipeline. So we do following:
542 * - check the resources
543 * - Create the pipeline
544 * - Initialize the modules in pipeline
545 * - finally bind all modules together
546 */
547static int skl_tplg_mixer_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
548 struct skl *skl)
549{
550 int ret;
551 struct skl_module_cfg *mconfig = w->priv;
552 struct skl_pipe_module *w_module;
553 struct skl_pipe *s_pipe = mconfig->pipe;
554 struct skl_module_cfg *src_module = NULL, *dst_module;
555 struct skl_sst *ctx = skl->skl_sst;
556
557 /* check resource available */
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530558 if (!skl_is_pipe_mcps_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100559 return -EBUSY;
560
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530561 if (!skl_is_pipe_mem_avail(skl, mconfig))
Vinod Kould93f8e52015-10-07 11:31:54 +0100562 return -ENOMEM;
563
564 /*
565 * Create a list of modules for pipe.
566 * This list contains modules from source to sink
567 */
568 ret = skl_create_pipeline(ctx, mconfig->pipe);
569 if (ret < 0)
570 return ret;
571
572 /*
573 * we create a w_list of all widgets in that pipe. This list is not
574 * freed on PMD event as widgets within a pipe are static. This
575 * saves us cycles to get widgets in pipe every time.
576 *
577 * So if we have already initialized all the widgets of a pipeline
578 * we skip, so check for list_empty and create the list if empty
579 */
580 if (list_empty(&s_pipe->w_list)) {
581 ret = skl_tplg_alloc_pipe_widget(ctx->dev, w, s_pipe);
582 if (ret < 0)
583 return ret;
584 }
585
586 /* Init all pipe modules from source to sink */
587 ret = skl_tplg_init_pipe_modules(skl, s_pipe);
588 if (ret < 0)
589 return ret;
590
591 /* Bind modules from source to sink */
592 list_for_each_entry(w_module, &s_pipe->w_list, node) {
593 dst_module = w_module->w->priv;
594
595 if (src_module == NULL) {
596 src_module = dst_module;
597 continue;
598 }
599
600 ret = skl_bind_modules(ctx, src_module, dst_module);
601 if (ret < 0)
602 return ret;
603
604 src_module = dst_module;
605 }
606
Dharageswari.R9ba8ffe2016-02-03 17:59:47 +0530607 skl_tplg_alloc_pipe_mem(skl, mconfig);
608 skl_tplg_alloc_pipe_mcps(skl, mconfig);
609
Vinod Kould93f8e52015-10-07 11:31:54 +0100610 return 0;
611}
612
Jeeja KPcc6a4042016-02-05 12:19:08 +0530613/*
614 * Some modules require params to be set after the module is bound to
615 * all pins connected.
616 *
617 * The module provider initializes set_param flag for such modules and we
618 * send params after binding
619 */
620static int skl_tplg_set_module_bind_params(struct snd_soc_dapm_widget *w,
621 struct skl_module_cfg *mcfg, struct skl_sst *ctx)
622{
623 int i, ret;
624 struct skl_module_cfg *mconfig = w->priv;
625 const struct snd_kcontrol_new *k;
626 struct soc_bytes_ext *sb;
627 struct skl_algo_data *bc;
628 struct skl_specific_cfg *sp_cfg;
629
630 /*
631 * check all out/in pins are in bind state.
632 * if so set the module param
633 */
634 for (i = 0; i < mcfg->max_out_queue; i++) {
635 if (mcfg->m_out_pin[i].pin_state != SKL_PIN_BIND_DONE)
636 return 0;
637 }
638
639 for (i = 0; i < mcfg->max_in_queue; i++) {
640 if (mcfg->m_in_pin[i].pin_state != SKL_PIN_BIND_DONE)
641 return 0;
642 }
643
644 if (mconfig->formats_config.caps_size > 0 &&
645 mconfig->formats_config.set_params == SKL_PARAM_BIND) {
646 sp_cfg = &mconfig->formats_config;
647 ret = skl_set_module_params(ctx, sp_cfg->caps,
648 sp_cfg->caps_size,
649 sp_cfg->param_id, mconfig);
650 if (ret < 0)
651 return ret;
652 }
653
654 for (i = 0; i < w->num_kcontrols; i++) {
655 k = &w->kcontrol_news[i];
656 if (k->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
657 sb = (void *) k->private_value;
658 bc = (struct skl_algo_data *)sb->dobj.private;
659
660 if (bc->set_params == SKL_PARAM_BIND) {
661 ret = skl_set_module_params(ctx,
662 (u32 *)bc->params, bc->max,
663 bc->param_id, mconfig);
664 if (ret < 0)
665 return ret;
666 }
667 }
668 }
669
670 return 0;
671}
672
Jeeja KP8724ff12015-10-27 09:22:52 +0900673static int skl_tplg_bind_sinks(struct snd_soc_dapm_widget *w,
674 struct skl *skl,
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530675 struct snd_soc_dapm_widget *src_w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900676 struct skl_module_cfg *src_mconfig)
Vinod Kould93f8e52015-10-07 11:31:54 +0100677{
678 struct snd_soc_dapm_path *p;
Jeeja KP0ed95d72015-11-13 19:22:11 +0530679 struct snd_soc_dapm_widget *sink = NULL, *next_sink = NULL;
Jeeja KP8724ff12015-10-27 09:22:52 +0900680 struct skl_module_cfg *sink_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100681 struct skl_sst *ctx = skl->skl_sst;
Jeeja KP8724ff12015-10-27 09:22:52 +0900682 int ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100683
Jeeja KP8724ff12015-10-27 09:22:52 +0900684 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Kould93f8e52015-10-07 11:31:54 +0100685 if (!p->connect)
686 continue;
687
688 dev_dbg(ctx->dev, "%s: src widget=%s\n", __func__, w->name);
689 dev_dbg(ctx->dev, "%s: sink widget=%s\n", __func__, p->sink->name);
690
Jeeja KP0ed95d72015-11-13 19:22:11 +0530691 next_sink = p->sink;
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530692
693 if (!is_skl_dsp_widget_type(p->sink))
694 return skl_tplg_bind_sinks(p->sink, skl, src_w, src_mconfig);
695
Vinod Kould93f8e52015-10-07 11:31:54 +0100696 /*
697 * here we will check widgets in sink pipelines, so that
698 * can be any widgets type and we are only interested if
699 * they are ones used for SKL so check that first
700 */
701 if ((p->sink->priv != NULL) &&
702 is_skl_dsp_widget_type(p->sink)) {
703
704 sink = p->sink;
Vinod Kould93f8e52015-10-07 11:31:54 +0100705 sink_mconfig = sink->priv;
706
Jeeja KPcc6a4042016-02-05 12:19:08 +0530707 if (src_mconfig->m_state == SKL_MODULE_UNINIT ||
708 sink_mconfig->m_state == SKL_MODULE_UNINIT)
709 continue;
710
Vinod Kould93f8e52015-10-07 11:31:54 +0100711 /* Bind source to sink, mixin is always source */
712 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
713 if (ret)
714 return ret;
715
Jeeja KPcc6a4042016-02-05 12:19:08 +0530716 /* set module params after bind */
717 skl_tplg_set_module_bind_params(src_w, src_mconfig, ctx);
718 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
719
Vinod Kould93f8e52015-10-07 11:31:54 +0100720 /* Start sinks pipe first */
721 if (sink_mconfig->pipe->state != SKL_PIPE_STARTED) {
Jeeja KPd1730c32015-10-27 09:22:53 +0900722 if (sink_mconfig->pipe->conn_type !=
723 SKL_PIPE_CONN_TYPE_FE)
724 ret = skl_run_pipe(ctx,
725 sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100726 if (ret)
727 return ret;
728 }
Vinod Kould93f8e52015-10-07 11:31:54 +0100729 }
730 }
731
Jeeja KP8724ff12015-10-27 09:22:52 +0900732 if (!sink)
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530733 return skl_tplg_bind_sinks(next_sink, skl, src_w, src_mconfig);
Jeeja KP8724ff12015-10-27 09:22:52 +0900734
735 return 0;
736}
737
Vinod Kould93f8e52015-10-07 11:31:54 +0100738/*
739 * A PGA represents a module in a pipeline. So in the Pre-PMU event of PGA
740 * we need to do following:
741 * - Bind to sink pipeline
742 * Since the sink pipes can be running and we don't get mixer event on
743 * connect for already running mixer, we need to find the sink pipes
744 * here and bind to them. This way dynamic connect works.
745 * - Start sink pipeline, if not running
746 * - Then run current pipe
747 */
748static int skl_tplg_pga_dapm_pre_pmu_event(struct snd_soc_dapm_widget *w,
Jeeja KP8724ff12015-10-27 09:22:52 +0900749 struct skl *skl)
Vinod Kould93f8e52015-10-07 11:31:54 +0100750{
Jeeja KP8724ff12015-10-27 09:22:52 +0900751 struct skl_module_cfg *src_mconfig;
Vinod Kould93f8e52015-10-07 11:31:54 +0100752 struct skl_sst *ctx = skl->skl_sst;
753 int ret = 0;
754
Jeeja KP8724ff12015-10-27 09:22:52 +0900755 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100756
757 /*
758 * find which sink it is connected to, bind with the sink,
759 * if sink is not started, start sink pipe first, then start
760 * this pipe
761 */
Jeeja KP6bd4cf82016-02-03 17:59:51 +0530762 ret = skl_tplg_bind_sinks(w, skl, w, src_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100763 if (ret)
764 return ret;
765
Vinod Kould93f8e52015-10-07 11:31:54 +0100766 /* Start source pipe last after starting all sinks */
Jeeja KPd1730c32015-10-27 09:22:53 +0900767 if (src_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
768 return skl_run_pipe(ctx, src_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100769
770 return 0;
771}
772
Jeeja KP8724ff12015-10-27 09:22:52 +0900773static struct snd_soc_dapm_widget *skl_get_src_dsp_widget(
774 struct snd_soc_dapm_widget *w, struct skl *skl)
775{
776 struct snd_soc_dapm_path *p;
777 struct snd_soc_dapm_widget *src_w = NULL;
778 struct skl_sst *ctx = skl->skl_sst;
779
780 snd_soc_dapm_widget_for_each_source_path(w, p) {
781 src_w = p->source;
782 if (!p->connect)
783 continue;
784
785 dev_dbg(ctx->dev, "sink widget=%s\n", w->name);
786 dev_dbg(ctx->dev, "src widget=%s\n", p->source->name);
787
788 /*
789 * here we will check widgets in sink pipelines, so that can
790 * be any widgets type and we are only interested if they are
791 * ones used for SKL so check that first
792 */
793 if ((p->source->priv != NULL) &&
794 is_skl_dsp_widget_type(p->source)) {
795 return p->source;
796 }
797 }
798
799 if (src_w != NULL)
800 return skl_get_src_dsp_widget(src_w, skl);
801
802 return NULL;
803}
804
Vinod Kould93f8e52015-10-07 11:31:54 +0100805/*
806 * in the Post-PMU event of mixer we need to do following:
807 * - Check if this pipe is running
808 * - if not, then
809 * - bind this pipeline to its source pipeline
810 * if source pipe is already running, this means it is a dynamic
811 * connection and we need to bind only to that pipe
812 * - start this pipeline
813 */
814static int skl_tplg_mixer_dapm_post_pmu_event(struct snd_soc_dapm_widget *w,
815 struct skl *skl)
816{
817 int ret = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100818 struct snd_soc_dapm_widget *source, *sink;
819 struct skl_module_cfg *src_mconfig, *sink_mconfig;
820 struct skl_sst *ctx = skl->skl_sst;
821 int src_pipe_started = 0;
822
823 sink = w;
824 sink_mconfig = sink->priv;
825
826 /*
827 * If source pipe is already started, that means source is driving
828 * one more sink before this sink got connected, Since source is
829 * started, bind this sink to source and start this pipe.
830 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900831 source = skl_get_src_dsp_widget(w, skl);
832 if (source != NULL) {
833 src_mconfig = source->priv;
834 sink_mconfig = sink->priv;
835 src_pipe_started = 1;
Vinod Kould93f8e52015-10-07 11:31:54 +0100836
837 /*
Jeeja KP8724ff12015-10-27 09:22:52 +0900838 * check pipe state, then no need to bind or start the
839 * pipe
Vinod Kould93f8e52015-10-07 11:31:54 +0100840 */
Jeeja KP8724ff12015-10-27 09:22:52 +0900841 if (src_mconfig->pipe->state != SKL_PIPE_STARTED)
842 src_pipe_started = 0;
Vinod Kould93f8e52015-10-07 11:31:54 +0100843 }
844
845 if (src_pipe_started) {
846 ret = skl_bind_modules(ctx, src_mconfig, sink_mconfig);
847 if (ret)
848 return ret;
849
Jeeja KPcc6a4042016-02-05 12:19:08 +0530850 /* set module params after bind */
851 skl_tplg_set_module_bind_params(source, src_mconfig, ctx);
852 skl_tplg_set_module_bind_params(sink, sink_mconfig, ctx);
853
Jeeja KPd1730c32015-10-27 09:22:53 +0900854 if (sink_mconfig->pipe->conn_type != SKL_PIPE_CONN_TYPE_FE)
855 ret = skl_run_pipe(ctx, sink_mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100856 }
857
858 return ret;
859}
860
861/*
862 * in the Pre-PMD event of mixer we need to do following:
863 * - Stop the pipe
864 * - find the source connections and remove that from dapm_path_list
865 * - unbind with source pipelines if still connected
866 */
867static int skl_tplg_mixer_dapm_pre_pmd_event(struct snd_soc_dapm_widget *w,
868 struct skl *skl)
869{
Vinod Kould93f8e52015-10-07 11:31:54 +0100870 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900871 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100872 struct skl_sst *ctx = skl->skl_sst;
873
Jeeja KPce1b5552015-10-27 09:22:51 +0900874 sink_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100875
876 /* Stop the pipe */
877 ret = skl_stop_pipe(ctx, sink_mconfig->pipe);
878 if (ret)
879 return ret;
880
Jeeja KPce1b5552015-10-27 09:22:51 +0900881 for (i = 0; i < sink_mconfig->max_in_queue; i++) {
882 if (sink_mconfig->m_in_pin[i].pin_state == SKL_PIN_BIND_DONE) {
883 src_mconfig = sink_mconfig->m_in_pin[i].tgt_mcfg;
884 if (!src_mconfig)
885 continue;
886 /*
887 * If path_found == 1, that means pmd for source
888 * pipe has not occurred, source is connected to
889 * some other sink. so its responsibility of sink
890 * to unbind itself from source.
891 */
892 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
893 if (ret < 0)
894 return ret;
Vinod Kould93f8e52015-10-07 11:31:54 +0100895
Jeeja KPce1b5552015-10-27 09:22:51 +0900896 ret = skl_unbind_modules(ctx,
897 src_mconfig, sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100898 }
899 }
900
Vinod Kould93f8e52015-10-07 11:31:54 +0100901 return ret;
902}
903
904/*
905 * in the Post-PMD event of mixer we need to do following:
906 * - Free the mcps used
907 * - Free the mem used
908 * - Unbind the modules within the pipeline
909 * - Delete the pipeline (modules are not required to be explicitly
910 * deleted, pipeline delete is enough here
911 */
912static int skl_tplg_mixer_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
913 struct skl *skl)
914{
915 struct skl_module_cfg *mconfig = w->priv;
916 struct skl_pipe_module *w_module;
917 struct skl_module_cfg *src_module = NULL, *dst_module;
918 struct skl_sst *ctx = skl->skl_sst;
919 struct skl_pipe *s_pipe = mconfig->pipe;
920 int ret = 0;
921
922 skl_tplg_free_pipe_mcps(skl, mconfig);
Vinod Koul65976872015-11-23 22:26:29 +0530923 skl_tplg_free_pipe_mem(skl, mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100924
925 list_for_each_entry(w_module, &s_pipe->w_list, node) {
926 dst_module = w_module->w->priv;
927
Vinod Koul7ae3cb12015-11-05 21:34:10 +0530928 skl_tplg_free_pipe_mcps(skl, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +0100929 if (src_module == NULL) {
930 src_module = dst_module;
931 continue;
932 }
933
Guneshwor Singh7ca42f52016-02-03 17:59:46 +0530934 skl_unbind_modules(ctx, src_module, dst_module);
Vinod Kould93f8e52015-10-07 11:31:54 +0100935 src_module = dst_module;
936 }
937
938 ret = skl_delete_pipe(ctx, mconfig->pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100939
Dharageswari R6c5768b2015-12-03 23:29:50 +0530940 return skl_tplg_unload_pipe_modules(ctx, s_pipe);
Vinod Kould93f8e52015-10-07 11:31:54 +0100941}
942
943/*
944 * in the Post-PMD event of PGA we need to do following:
945 * - Free the mcps used
946 * - Stop the pipeline
947 * - In source pipe is connected, unbind with source pipelines
948 */
949static int skl_tplg_pga_dapm_post_pmd_event(struct snd_soc_dapm_widget *w,
950 struct skl *skl)
951{
Vinod Kould93f8e52015-10-07 11:31:54 +0100952 struct skl_module_cfg *src_mconfig, *sink_mconfig;
Jeeja KPce1b5552015-10-27 09:22:51 +0900953 int ret = 0, i;
Vinod Kould93f8e52015-10-07 11:31:54 +0100954 struct skl_sst *ctx = skl->skl_sst;
955
Jeeja KPce1b5552015-10-27 09:22:51 +0900956 src_mconfig = w->priv;
Vinod Kould93f8e52015-10-07 11:31:54 +0100957
Vinod Kould93f8e52015-10-07 11:31:54 +0100958 /* Stop the pipe since this is a mixin module */
959 ret = skl_stop_pipe(ctx, src_mconfig->pipe);
960 if (ret)
961 return ret;
962
Jeeja KPce1b5552015-10-27 09:22:51 +0900963 for (i = 0; i < src_mconfig->max_out_queue; i++) {
964 if (src_mconfig->m_out_pin[i].pin_state == SKL_PIN_BIND_DONE) {
965 sink_mconfig = src_mconfig->m_out_pin[i].tgt_mcfg;
966 if (!sink_mconfig)
967 continue;
968 /*
969 * This is a connecter and if path is found that means
970 * unbind between source and sink has not happened yet
971 */
Jeeja KPce1b5552015-10-27 09:22:51 +0900972 ret = skl_unbind_modules(ctx, src_mconfig,
973 sink_mconfig);
Vinod Kould93f8e52015-10-07 11:31:54 +0100974 }
975 }
976
Vinod Kould93f8e52015-10-07 11:31:54 +0100977 return ret;
978}
979
980/*
981 * In modelling, we assume there will be ONLY one mixer in a pipeline. If
982 * mixer is not required then it is treated as static mixer aka vmixer with
983 * a hard path to source module
984 * So we don't need to check if source is started or not as hard path puts
985 * dependency on each other
986 */
987static int skl_tplg_vmixer_event(struct snd_soc_dapm_widget *w,
988 struct snd_kcontrol *k, int event)
989{
990 struct snd_soc_dapm_context *dapm = w->dapm;
991 struct skl *skl = get_skl_ctx(dapm->dev);
992
993 switch (event) {
994 case SND_SOC_DAPM_PRE_PMU:
995 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
996
Jeeja KPde1fedf2016-02-03 17:59:52 +0530997 case SND_SOC_DAPM_POST_PMU:
998 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
999
1000 case SND_SOC_DAPM_PRE_PMD:
1001 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1002
Vinod Kould93f8e52015-10-07 11:31:54 +01001003 case SND_SOC_DAPM_POST_PMD:
1004 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1005 }
1006
1007 return 0;
1008}
1009
1010/*
1011 * In modelling, we assume there will be ONLY one mixer in a pipeline. If a
1012 * second one is required that is created as another pipe entity.
1013 * The mixer is responsible for pipe management and represent a pipeline
1014 * instance
1015 */
1016static int skl_tplg_mixer_event(struct snd_soc_dapm_widget *w,
1017 struct snd_kcontrol *k, int event)
1018{
1019 struct snd_soc_dapm_context *dapm = w->dapm;
1020 struct skl *skl = get_skl_ctx(dapm->dev);
1021
1022 switch (event) {
1023 case SND_SOC_DAPM_PRE_PMU:
1024 return skl_tplg_mixer_dapm_pre_pmu_event(w, skl);
1025
1026 case SND_SOC_DAPM_POST_PMU:
1027 return skl_tplg_mixer_dapm_post_pmu_event(w, skl);
1028
1029 case SND_SOC_DAPM_PRE_PMD:
1030 return skl_tplg_mixer_dapm_pre_pmd_event(w, skl);
1031
1032 case SND_SOC_DAPM_POST_PMD:
1033 return skl_tplg_mixer_dapm_post_pmd_event(w, skl);
1034 }
1035
1036 return 0;
1037}
1038
1039/*
1040 * In modelling, we assumed rest of the modules in pipeline are PGA. But we
1041 * are interested in last PGA (leaf PGA) in a pipeline to disconnect with
1042 * the sink when it is running (two FE to one BE or one FE to two BE)
1043 * scenarios
1044 */
1045static int skl_tplg_pga_event(struct snd_soc_dapm_widget *w,
1046 struct snd_kcontrol *k, int event)
1047
1048{
1049 struct snd_soc_dapm_context *dapm = w->dapm;
1050 struct skl *skl = get_skl_ctx(dapm->dev);
1051
1052 switch (event) {
1053 case SND_SOC_DAPM_PRE_PMU:
1054 return skl_tplg_pga_dapm_pre_pmu_event(w, skl);
1055
1056 case SND_SOC_DAPM_POST_PMD:
1057 return skl_tplg_pga_dapm_post_pmd_event(w, skl);
1058 }
1059
1060 return 0;
1061}
Vinod Koulcfb0a872015-10-07 11:31:55 +01001062
Jeeja KP140adfb2015-11-28 15:01:50 +05301063static int skl_tplg_tlv_control_get(struct snd_kcontrol *kcontrol,
1064 unsigned int __user *data, unsigned int size)
1065{
1066 struct soc_bytes_ext *sb =
1067 (struct soc_bytes_ext *)kcontrol->private_value;
1068 struct skl_algo_data *bc = (struct skl_algo_data *)sb->dobj.private;
Omair M Abdullah7d9f2912015-12-03 23:29:56 +05301069 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1070 struct skl_module_cfg *mconfig = w->priv;
1071 struct skl *skl = get_skl_ctx(w->dapm->dev);
1072
1073 if (w->power)
1074 skl_get_module_params(skl->skl_sst, (u32 *)bc->params,
1075 bc->max, bc->param_id, mconfig);
Jeeja KP140adfb2015-11-28 15:01:50 +05301076
Vinod Koul41556f62016-02-03 17:59:44 +05301077 /* decrement size for TLV header */
1078 size -= 2 * sizeof(u32);
1079
1080 /* check size as we don't want to send kernel data */
1081 if (size > bc->max)
1082 size = bc->max;
1083
Jeeja KP140adfb2015-11-28 15:01:50 +05301084 if (bc->params) {
1085 if (copy_to_user(data, &bc->param_id, sizeof(u32)))
1086 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001087 if (copy_to_user(data + 1, &size, sizeof(u32)))
Jeeja KP140adfb2015-11-28 15:01:50 +05301088 return -EFAULT;
Dan Carpentere8bc3c92015-12-08 08:53:22 +03001089 if (copy_to_user(data + 2, bc->params, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301090 return -EFAULT;
1091 }
1092
1093 return 0;
1094}
1095
1096#define SKL_PARAM_VENDOR_ID 0xff
1097
1098static int skl_tplg_tlv_control_set(struct snd_kcontrol *kcontrol,
1099 const unsigned int __user *data, unsigned int size)
1100{
1101 struct snd_soc_dapm_widget *w = snd_soc_dapm_kcontrol_widget(kcontrol);
1102 struct skl_module_cfg *mconfig = w->priv;
1103 struct soc_bytes_ext *sb =
1104 (struct soc_bytes_ext *)kcontrol->private_value;
1105 struct skl_algo_data *ac = (struct skl_algo_data *)sb->dobj.private;
1106 struct skl *skl = get_skl_ctx(w->dapm->dev);
1107
1108 if (ac->params) {
1109 /*
1110 * if the param_is is of type Vendor, firmware expects actual
1111 * parameter id and size from the control.
1112 */
1113 if (ac->param_id == SKL_PARAM_VENDOR_ID) {
1114 if (copy_from_user(ac->params, data, size))
1115 return -EFAULT;
1116 } else {
1117 if (copy_from_user(ac->params,
Alan65b4bcb2016-02-19 11:42:32 +05301118 data + 2, size))
Jeeja KP140adfb2015-11-28 15:01:50 +05301119 return -EFAULT;
1120 }
1121
1122 if (w->power)
1123 return skl_set_module_params(skl->skl_sst,
1124 (u32 *)ac->params, ac->max,
1125 ac->param_id, mconfig);
1126 }
1127
1128 return 0;
1129}
1130
Vinod Koulcfb0a872015-10-07 11:31:55 +01001131/*
1132 * The FE params are passed by hw_params of the DAI.
1133 * On hw_params, the params are stored in Gateway module of the FE and we
1134 * need to calculate the format in DSP module configuration, that
1135 * conversion is done here
1136 */
1137int skl_tplg_update_pipe_params(struct device *dev,
1138 struct skl_module_cfg *mconfig,
1139 struct skl_pipe_params *params)
1140{
1141 struct skl_pipe *pipe = mconfig->pipe;
1142 struct skl_module_fmt *format = NULL;
1143
1144 memcpy(pipe->p_params, params, sizeof(*params));
1145
1146 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK)
Hardik T Shah4cd98992015-10-27 09:22:55 +09001147 format = &mconfig->in_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001148 else
Hardik T Shah4cd98992015-10-27 09:22:55 +09001149 format = &mconfig->out_fmt[0];
Vinod Koulcfb0a872015-10-07 11:31:55 +01001150
1151 /* set the hw_params */
1152 format->s_freq = params->s_freq;
1153 format->channels = params->ch;
1154 format->valid_bit_depth = skl_get_bit_depth(params->s_fmt);
1155
1156 /*
1157 * 16 bit is 16 bit container whereas 24 bit is in 32 bit
1158 * container so update bit depth accordingly
1159 */
1160 switch (format->valid_bit_depth) {
1161 case SKL_DEPTH_16BIT:
1162 format->bit_depth = format->valid_bit_depth;
1163 break;
1164
1165 case SKL_DEPTH_24BIT:
Jeeja KP6654f392015-10-27 09:22:46 +09001166 case SKL_DEPTH_32BIT:
Vinod Koulcfb0a872015-10-07 11:31:55 +01001167 format->bit_depth = SKL_DEPTH_32BIT;
1168 break;
1169
1170 default:
1171 dev_err(dev, "Invalid bit depth %x for pipe\n",
1172 format->valid_bit_depth);
1173 return -EINVAL;
1174 }
1175
1176 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1177 mconfig->ibs = (format->s_freq / 1000) *
1178 (format->channels) *
1179 (format->bit_depth >> 3);
1180 } else {
1181 mconfig->obs = (format->s_freq / 1000) *
1182 (format->channels) *
1183 (format->bit_depth >> 3);
1184 }
1185
1186 return 0;
1187}
1188
1189/*
1190 * Query the module config for the FE DAI
1191 * This is used to find the hw_params set for that DAI and apply to FE
1192 * pipeline
1193 */
1194struct skl_module_cfg *
1195skl_tplg_fe_get_cpr_module(struct snd_soc_dai *dai, int stream)
1196{
1197 struct snd_soc_dapm_widget *w;
1198 struct snd_soc_dapm_path *p = NULL;
1199
1200 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1201 w = dai->playback_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301202 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001203 if (p->connect && p->sink->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001204 !is_skl_dsp_widget_type(p->sink))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001205 continue;
1206
1207 if (p->sink->priv) {
1208 dev_dbg(dai->dev, "set params for %s\n",
1209 p->sink->name);
1210 return p->sink->priv;
1211 }
1212 }
1213 } else {
1214 w = dai->capture_widget;
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301215 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001216 if (p->connect && p->source->power &&
Jeeja KPa28f51d2015-10-27 09:22:44 +09001217 !is_skl_dsp_widget_type(p->source))
Vinod Koulcfb0a872015-10-07 11:31:55 +01001218 continue;
1219
1220 if (p->source->priv) {
1221 dev_dbg(dai->dev, "set params for %s\n",
1222 p->source->name);
1223 return p->source->priv;
1224 }
1225 }
1226 }
1227
1228 return NULL;
1229}
1230
Dharageswari.R718a42b2016-02-05 12:19:06 +05301231static struct skl_module_cfg *skl_get_mconfig_pb_cpr(
1232 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1233{
1234 struct snd_soc_dapm_path *p;
1235 struct skl_module_cfg *mconfig = NULL;
1236
1237 snd_soc_dapm_widget_for_each_source_path(w, p) {
1238 if (w->endpoints[SND_SOC_DAPM_DIR_OUT] > 0) {
1239 if (p->connect &&
1240 (p->sink->id == snd_soc_dapm_aif_out) &&
1241 p->source->priv) {
1242 mconfig = p->source->priv;
1243 return mconfig;
1244 }
1245 mconfig = skl_get_mconfig_pb_cpr(dai, p->source);
1246 if (mconfig)
1247 return mconfig;
1248 }
1249 }
1250 return mconfig;
1251}
1252
1253static struct skl_module_cfg *skl_get_mconfig_cap_cpr(
1254 struct snd_soc_dai *dai, struct snd_soc_dapm_widget *w)
1255{
1256 struct snd_soc_dapm_path *p;
1257 struct skl_module_cfg *mconfig = NULL;
1258
1259 snd_soc_dapm_widget_for_each_sink_path(w, p) {
1260 if (w->endpoints[SND_SOC_DAPM_DIR_IN] > 0) {
1261 if (p->connect &&
1262 (p->source->id == snd_soc_dapm_aif_in) &&
1263 p->sink->priv) {
1264 mconfig = p->sink->priv;
1265 return mconfig;
1266 }
1267 mconfig = skl_get_mconfig_cap_cpr(dai, p->sink);
1268 if (mconfig)
1269 return mconfig;
1270 }
1271 }
1272 return mconfig;
1273}
1274
1275struct skl_module_cfg *
1276skl_tplg_be_get_cpr_module(struct snd_soc_dai *dai, int stream)
1277{
1278 struct snd_soc_dapm_widget *w;
1279 struct skl_module_cfg *mconfig;
1280
1281 if (stream == SNDRV_PCM_STREAM_PLAYBACK) {
1282 w = dai->playback_widget;
1283 mconfig = skl_get_mconfig_pb_cpr(dai, w);
1284 } else {
1285 w = dai->capture_widget;
1286 mconfig = skl_get_mconfig_cap_cpr(dai, w);
1287 }
1288 return mconfig;
1289}
1290
Vinod Koulcfb0a872015-10-07 11:31:55 +01001291static u8 skl_tplg_be_link_type(int dev_type)
1292{
1293 int ret;
1294
1295 switch (dev_type) {
1296 case SKL_DEVICE_BT:
1297 ret = NHLT_LINK_SSP;
1298 break;
1299
1300 case SKL_DEVICE_DMIC:
1301 ret = NHLT_LINK_DMIC;
1302 break;
1303
1304 case SKL_DEVICE_I2S:
1305 ret = NHLT_LINK_SSP;
1306 break;
1307
1308 case SKL_DEVICE_HDALINK:
1309 ret = NHLT_LINK_HDA;
1310 break;
1311
1312 default:
1313 ret = NHLT_LINK_INVALID;
1314 break;
1315 }
1316
1317 return ret;
1318}
1319
1320/*
1321 * Fill the BE gateway parameters
1322 * The BE gateway expects a blob of parameters which are kept in the ACPI
1323 * NHLT blob, so query the blob for interface type (i2s/pdm) and instance.
1324 * The port can have multiple settings so pick based on the PCM
1325 * parameters
1326 */
1327static int skl_tplg_be_fill_pipe_params(struct snd_soc_dai *dai,
1328 struct skl_module_cfg *mconfig,
1329 struct skl_pipe_params *params)
1330{
1331 struct skl_pipe *pipe = mconfig->pipe;
1332 struct nhlt_specific_cfg *cfg;
1333 struct skl *skl = get_skl_ctx(dai->dev);
1334 int link_type = skl_tplg_be_link_type(mconfig->dev_type);
1335
1336 memcpy(pipe->p_params, params, sizeof(*params));
1337
Jeeja KPb30c2752015-10-27 09:22:48 +09001338 if (link_type == NHLT_LINK_HDA)
1339 return 0;
1340
Vinod Koulcfb0a872015-10-07 11:31:55 +01001341 /* update the blob based on virtual bus_id*/
1342 cfg = skl_get_ep_blob(skl, mconfig->vbus_id, link_type,
1343 params->s_fmt, params->ch,
1344 params->s_freq, params->stream);
1345 if (cfg) {
1346 mconfig->formats_config.caps_size = cfg->size;
Jeeja KPbc032812015-10-22 23:22:35 +05301347 mconfig->formats_config.caps = (u32 *) &cfg->caps;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001348 } else {
1349 dev_err(dai->dev, "Blob NULL for id %x type %d dirn %d\n",
1350 mconfig->vbus_id, link_type,
1351 params->stream);
1352 dev_err(dai->dev, "PCM: ch %d, freq %d, fmt %d\n",
1353 params->ch, params->s_freq, params->s_fmt);
1354 return -EINVAL;
1355 }
1356
1357 return 0;
1358}
1359
1360static int skl_tplg_be_set_src_pipe_params(struct snd_soc_dai *dai,
1361 struct snd_soc_dapm_widget *w,
1362 struct skl_pipe_params *params)
1363{
1364 struct snd_soc_dapm_path *p;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301365 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001366
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301367 snd_soc_dapm_widget_for_each_source_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001368 if (p->connect && is_skl_dsp_widget_type(p->source) &&
1369 p->source->priv) {
1370
Jeeja KP9a03cb42015-10-27 09:22:54 +09001371 ret = skl_tplg_be_fill_pipe_params(dai,
1372 p->source->priv, params);
1373 if (ret < 0)
1374 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001375 } else {
Jeeja KP9a03cb42015-10-27 09:22:54 +09001376 ret = skl_tplg_be_set_src_pipe_params(dai,
1377 p->source, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301378 if (ret < 0)
1379 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001380 }
1381 }
1382
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301383 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001384}
1385
1386static int skl_tplg_be_set_sink_pipe_params(struct snd_soc_dai *dai,
1387 struct snd_soc_dapm_widget *w, struct skl_pipe_params *params)
1388{
1389 struct snd_soc_dapm_path *p = NULL;
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301390 int ret = -EIO;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001391
Subhransu S. Prustyf0900eb2015-10-22 23:22:36 +05301392 snd_soc_dapm_widget_for_each_sink_path(w, p) {
Vinod Koulcfb0a872015-10-07 11:31:55 +01001393 if (p->connect && is_skl_dsp_widget_type(p->sink) &&
1394 p->sink->priv) {
1395
Jeeja KP9a03cb42015-10-27 09:22:54 +09001396 ret = skl_tplg_be_fill_pipe_params(dai,
1397 p->sink->priv, params);
1398 if (ret < 0)
1399 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001400 } else {
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301401 ret = skl_tplg_be_set_sink_pipe_params(
Vinod Koulcfb0a872015-10-07 11:31:55 +01001402 dai, p->sink, params);
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301403 if (ret < 0)
1404 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001405 }
1406 }
1407
Subhransu S. Prusty4d8adccb2015-10-22 23:22:37 +05301408 return ret;
Vinod Koulcfb0a872015-10-07 11:31:55 +01001409}
1410
1411/*
1412 * BE hw_params can be a source parameters (capture) or sink parameters
1413 * (playback). Based on sink and source we need to either find the source
1414 * list or the sink list and set the pipeline parameters
1415 */
1416int skl_tplg_be_update_params(struct snd_soc_dai *dai,
1417 struct skl_pipe_params *params)
1418{
1419 struct snd_soc_dapm_widget *w;
1420
1421 if (params->stream == SNDRV_PCM_STREAM_PLAYBACK) {
1422 w = dai->playback_widget;
1423
1424 return skl_tplg_be_set_src_pipe_params(dai, w, params);
1425
1426 } else {
1427 w = dai->capture_widget;
1428
1429 return skl_tplg_be_set_sink_pipe_params(dai, w, params);
1430 }
1431
1432 return 0;
1433}
Vinod Koul3af36702015-10-07 11:31:56 +01001434
1435static const struct snd_soc_tplg_widget_events skl_tplg_widget_ops[] = {
1436 {SKL_MIXER_EVENT, skl_tplg_mixer_event},
1437 {SKL_VMIXER_EVENT, skl_tplg_vmixer_event},
1438 {SKL_PGA_EVENT, skl_tplg_pga_event},
1439};
1440
Jeeja KP140adfb2015-11-28 15:01:50 +05301441static const struct snd_soc_tplg_bytes_ext_ops skl_tlv_ops[] = {
1442 {SKL_CONTROL_TYPE_BYTE_TLV, skl_tplg_tlv_control_get,
1443 skl_tplg_tlv_control_set},
1444};
1445
Vinod Koul3af36702015-10-07 11:31:56 +01001446/*
1447 * The topology binary passes the pin info for a module so initialize the pin
1448 * info passed into module instance
1449 */
Jeeja KP6abca1d2015-10-22 23:22:42 +05301450static void skl_fill_module_pin_info(struct skl_dfw_module_pin *dfw_pin,
1451 struct skl_module_pin *m_pin,
1452 bool is_dynamic, int max_pin)
Vinod Koul3af36702015-10-07 11:31:56 +01001453{
1454 int i;
1455
1456 for (i = 0; i < max_pin; i++) {
Jeeja KP6abca1d2015-10-22 23:22:42 +05301457 m_pin[i].id.module_id = dfw_pin[i].module_id;
1458 m_pin[i].id.instance_id = dfw_pin[i].instance_id;
Vinod Koul3af36702015-10-07 11:31:56 +01001459 m_pin[i].in_use = false;
Jeeja KP6abca1d2015-10-22 23:22:42 +05301460 m_pin[i].is_dynamic = is_dynamic;
Jeeja KP4f745702015-10-27 09:22:49 +09001461 m_pin[i].pin_state = SKL_PIN_UNBIND;
Vinod Koul3af36702015-10-07 11:31:56 +01001462 }
1463}
1464
1465/*
1466 * Add pipeline from topology binary into driver pipeline list
1467 *
1468 * If already added we return that instance
1469 * Otherwise we create a new instance and add into driver list
1470 */
1471static struct skl_pipe *skl_tplg_add_pipe(struct device *dev,
1472 struct skl *skl, struct skl_dfw_pipe *dfw_pipe)
1473{
1474 struct skl_pipeline *ppl;
1475 struct skl_pipe *pipe;
1476 struct skl_pipe_params *params;
1477
1478 list_for_each_entry(ppl, &skl->ppl_list, node) {
1479 if (ppl->pipe->ppl_id == dfw_pipe->pipe_id)
1480 return ppl->pipe;
1481 }
1482
1483 ppl = devm_kzalloc(dev, sizeof(*ppl), GFP_KERNEL);
1484 if (!ppl)
1485 return NULL;
1486
1487 pipe = devm_kzalloc(dev, sizeof(*pipe), GFP_KERNEL);
1488 if (!pipe)
1489 return NULL;
1490
1491 params = devm_kzalloc(dev, sizeof(*params), GFP_KERNEL);
1492 if (!params)
1493 return NULL;
1494
1495 pipe->ppl_id = dfw_pipe->pipe_id;
1496 pipe->memory_pages = dfw_pipe->memory_pages;
1497 pipe->pipe_priority = dfw_pipe->pipe_priority;
1498 pipe->conn_type = dfw_pipe->conn_type;
1499 pipe->state = SKL_PIPE_INVALID;
1500 pipe->p_params = params;
1501 INIT_LIST_HEAD(&pipe->w_list);
1502
1503 ppl->pipe = pipe;
1504 list_add(&ppl->node, &skl->ppl_list);
1505
1506 return ppl->pipe;
1507}
1508
Hardik T Shah4cd98992015-10-27 09:22:55 +09001509static void skl_tplg_fill_fmt(struct skl_module_fmt *dst_fmt,
1510 struct skl_dfw_module_fmt *src_fmt,
1511 int pins)
1512{
1513 int i;
1514
1515 for (i = 0; i < pins; i++) {
1516 dst_fmt[i].channels = src_fmt[i].channels;
1517 dst_fmt[i].s_freq = src_fmt[i].freq;
1518 dst_fmt[i].bit_depth = src_fmt[i].bit_depth;
1519 dst_fmt[i].valid_bit_depth = src_fmt[i].valid_bit_depth;
1520 dst_fmt[i].ch_cfg = src_fmt[i].ch_cfg;
1521 dst_fmt[i].ch_map = src_fmt[i].ch_map;
1522 dst_fmt[i].interleaving_style = src_fmt[i].interleaving_style;
1523 dst_fmt[i].sample_type = src_fmt[i].sample_type;
1524 }
1525}
1526
Vinod Koul3af36702015-10-07 11:31:56 +01001527/*
1528 * Topology core widget load callback
1529 *
1530 * This is used to save the private data for each widget which gives
1531 * information to the driver about module and pipeline parameters which DSP
1532 * FW expects like ids, resource values, formats etc
1533 */
1534static int skl_tplg_widget_load(struct snd_soc_component *cmpnt,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001535 struct snd_soc_dapm_widget *w,
1536 struct snd_soc_tplg_dapm_widget *tplg_w)
Vinod Koul3af36702015-10-07 11:31:56 +01001537{
1538 int ret;
1539 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
1540 struct skl *skl = ebus_to_skl(ebus);
1541 struct hdac_bus *bus = ebus_to_hbus(ebus);
1542 struct skl_module_cfg *mconfig;
1543 struct skl_pipe *pipe;
Jeeja KPb663a8c2015-10-07 11:31:57 +01001544 struct skl_dfw_module *dfw_config =
1545 (struct skl_dfw_module *)tplg_w->priv.data;
Vinod Koul3af36702015-10-07 11:31:56 +01001546
1547 if (!tplg_w->priv.size)
1548 goto bind_event;
1549
1550 mconfig = devm_kzalloc(bus->dev, sizeof(*mconfig), GFP_KERNEL);
1551
1552 if (!mconfig)
1553 return -ENOMEM;
1554
1555 w->priv = mconfig;
1556 mconfig->id.module_id = dfw_config->module_id;
1557 mconfig->id.instance_id = dfw_config->instance_id;
1558 mconfig->mcps = dfw_config->max_mcps;
1559 mconfig->ibs = dfw_config->ibs;
1560 mconfig->obs = dfw_config->obs;
1561 mconfig->core_id = dfw_config->core_id;
1562 mconfig->max_in_queue = dfw_config->max_in_queue;
1563 mconfig->max_out_queue = dfw_config->max_out_queue;
1564 mconfig->is_loadable = dfw_config->is_loadable;
Hardik T Shah4cd98992015-10-27 09:22:55 +09001565 skl_tplg_fill_fmt(mconfig->in_fmt, dfw_config->in_fmt,
1566 MODULE_MAX_IN_PINS);
1567 skl_tplg_fill_fmt(mconfig->out_fmt, dfw_config->out_fmt,
1568 MODULE_MAX_OUT_PINS);
1569
Vinod Koul3af36702015-10-07 11:31:56 +01001570 mconfig->params_fixup = dfw_config->params_fixup;
1571 mconfig->converter = dfw_config->converter;
1572 mconfig->m_type = dfw_config->module_type;
1573 mconfig->vbus_id = dfw_config->vbus_id;
Jeeja KPb18c4582015-12-03 23:29:51 +05301574 mconfig->mem_pages = dfw_config->mem_pages;
Vinod Koul3af36702015-10-07 11:31:56 +01001575
1576 pipe = skl_tplg_add_pipe(bus->dev, skl, &dfw_config->pipe);
1577 if (pipe)
1578 mconfig->pipe = pipe;
1579
1580 mconfig->dev_type = dfw_config->dev_type;
1581 mconfig->hw_conn_type = dfw_config->hw_conn_type;
1582 mconfig->time_slot = dfw_config->time_slot;
1583 mconfig->formats_config.caps_size = dfw_config->caps.caps_size;
1584
Hardik T Shah65aecfa2015-10-27 09:22:57 +09001585 if (dfw_config->is_loadable)
1586 memcpy(mconfig->guid, dfw_config->uuid,
1587 ARRAY_SIZE(dfw_config->uuid));
1588
Hardik T Shah4cd98992015-10-27 09:22:55 +09001589 mconfig->m_in_pin = devm_kzalloc(bus->dev, (mconfig->max_in_queue) *
1590 sizeof(*mconfig->m_in_pin),
1591 GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001592 if (!mconfig->m_in_pin)
1593 return -ENOMEM;
1594
Jeeja KP6abca1d2015-10-22 23:22:42 +05301595 mconfig->m_out_pin = devm_kzalloc(bus->dev, (mconfig->max_out_queue) *
1596 sizeof(*mconfig->m_out_pin),
1597 GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001598 if (!mconfig->m_out_pin)
1599 return -ENOMEM;
1600
Jeeja KP6abca1d2015-10-22 23:22:42 +05301601 skl_fill_module_pin_info(dfw_config->in_pin, mconfig->m_in_pin,
1602 dfw_config->is_dynamic_in_pin,
1603 mconfig->max_in_queue);
1604
1605 skl_fill_module_pin_info(dfw_config->out_pin, mconfig->m_out_pin,
1606 dfw_config->is_dynamic_out_pin,
1607 mconfig->max_out_queue);
1608
Vinod Koul3af36702015-10-07 11:31:56 +01001609
1610 if (mconfig->formats_config.caps_size == 0)
1611 goto bind_event;
1612
1613 mconfig->formats_config.caps = (u32 *)devm_kzalloc(bus->dev,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001614 mconfig->formats_config.caps_size, GFP_KERNEL);
Vinod Koul3af36702015-10-07 11:31:56 +01001615
1616 if (mconfig->formats_config.caps == NULL)
1617 return -ENOMEM;
1618
1619 memcpy(mconfig->formats_config.caps, dfw_config->caps.caps,
Jeeja KPabb74002015-11-28 15:01:49 +05301620 dfw_config->caps.caps_size);
1621 mconfig->formats_config.param_id = dfw_config->caps.param_id;
1622 mconfig->formats_config.set_params = dfw_config->caps.set_params;
Vinod Koul3af36702015-10-07 11:31:56 +01001623
1624bind_event:
1625 if (tplg_w->event_type == 0) {
Vinod Koul3373f712015-10-07 16:39:38 +01001626 dev_dbg(bus->dev, "ASoC: No event handler required\n");
Vinod Koul3af36702015-10-07 11:31:56 +01001627 return 0;
1628 }
1629
1630 ret = snd_soc_tplg_widget_bind_event(w, skl_tplg_widget_ops,
Jeeja KPb663a8c2015-10-07 11:31:57 +01001631 ARRAY_SIZE(skl_tplg_widget_ops),
1632 tplg_w->event_type);
Vinod Koul3af36702015-10-07 11:31:56 +01001633
1634 if (ret) {
1635 dev_err(bus->dev, "%s: No matching event handlers found for %d\n",
1636 __func__, tplg_w->event_type);
1637 return -EINVAL;
1638 }
1639
1640 return 0;
1641}
1642
Jeeja KP140adfb2015-11-28 15:01:50 +05301643static int skl_init_algo_data(struct device *dev, struct soc_bytes_ext *be,
1644 struct snd_soc_tplg_bytes_control *bc)
1645{
1646 struct skl_algo_data *ac;
1647 struct skl_dfw_algo_data *dfw_ac =
1648 (struct skl_dfw_algo_data *)bc->priv.data;
1649
1650 ac = devm_kzalloc(dev, sizeof(*ac), GFP_KERNEL);
1651 if (!ac)
1652 return -ENOMEM;
1653
1654 /* Fill private data */
1655 ac->max = dfw_ac->max;
1656 ac->param_id = dfw_ac->param_id;
1657 ac->set_params = dfw_ac->set_params;
1658
1659 if (ac->max) {
1660 ac->params = (char *) devm_kzalloc(dev, ac->max, GFP_KERNEL);
1661 if (!ac->params)
1662 return -ENOMEM;
1663
Alan Coxedd7ea22016-02-22 09:37:27 +05301664 memcpy(ac->params, dfw_ac->params, ac->max);
Jeeja KP140adfb2015-11-28 15:01:50 +05301665 }
1666
1667 be->dobj.private = ac;
1668 return 0;
1669}
1670
1671static int skl_tplg_control_load(struct snd_soc_component *cmpnt,
1672 struct snd_kcontrol_new *kctl,
1673 struct snd_soc_tplg_ctl_hdr *hdr)
1674{
1675 struct soc_bytes_ext *sb;
1676 struct snd_soc_tplg_bytes_control *tplg_bc;
1677 struct hdac_ext_bus *ebus = snd_soc_component_get_drvdata(cmpnt);
1678 struct hdac_bus *bus = ebus_to_hbus(ebus);
1679
1680 switch (hdr->ops.info) {
1681 case SND_SOC_TPLG_CTL_BYTES:
1682 tplg_bc = container_of(hdr,
1683 struct snd_soc_tplg_bytes_control, hdr);
1684 if (kctl->access & SNDRV_CTL_ELEM_ACCESS_TLV_CALLBACK) {
1685 sb = (struct soc_bytes_ext *)kctl->private_value;
1686 if (tplg_bc->priv.size)
1687 return skl_init_algo_data(
1688 bus->dev, sb, tplg_bc);
1689 }
1690 break;
1691
1692 default:
1693 dev_warn(bus->dev, "Control load not supported %d:%d:%d\n",
1694 hdr->ops.get, hdr->ops.put, hdr->ops.info);
1695 break;
1696 }
1697
1698 return 0;
1699}
1700
Vinod Koul3af36702015-10-07 11:31:56 +01001701static struct snd_soc_tplg_ops skl_tplg_ops = {
1702 .widget_load = skl_tplg_widget_load,
Jeeja KP140adfb2015-11-28 15:01:50 +05301703 .control_load = skl_tplg_control_load,
1704 .bytes_ext_ops = skl_tlv_ops,
1705 .bytes_ext_ops_count = ARRAY_SIZE(skl_tlv_ops),
Vinod Koul3af36702015-10-07 11:31:56 +01001706};
1707
1708/* This will be read from topology manifest, currently defined here */
1709#define SKL_MAX_MCPS 30000000
1710#define SKL_FW_MAX_MEM 1000000
1711
1712/*
1713 * SKL topology init routine
1714 */
1715int skl_tplg_init(struct snd_soc_platform *platform, struct hdac_ext_bus *ebus)
1716{
1717 int ret;
1718 const struct firmware *fw;
1719 struct hdac_bus *bus = ebus_to_hbus(ebus);
1720 struct skl *skl = ebus_to_skl(ebus);
1721
Vinod Koul4b235c42016-02-19 11:42:34 +05301722 ret = request_firmware(&fw, skl->tplg_name, bus->dev);
Vinod Koul3af36702015-10-07 11:31:56 +01001723 if (ret < 0) {
Jeeja KPb663a8c2015-10-07 11:31:57 +01001724 dev_err(bus->dev, "tplg fw %s load failed with %d\n",
Vinod Koul4b235c42016-02-19 11:42:34 +05301725 skl->tplg_name, ret);
1726 ret = request_firmware(&fw, "dfw_sst.bin", bus->dev);
1727 if (ret < 0) {
1728 dev_err(bus->dev, "Fallback tplg fw %s load failed with %d\n",
1729 "dfw_sst.bin", ret);
1730 return ret;
1731 }
Vinod Koul3af36702015-10-07 11:31:56 +01001732 }
1733
1734 /*
1735 * The complete tplg for SKL is loaded as index 0, we don't use
1736 * any other index
1737 */
Jeeja KPb663a8c2015-10-07 11:31:57 +01001738 ret = snd_soc_tplg_component_load(&platform->component,
1739 &skl_tplg_ops, fw, 0);
Vinod Koul3af36702015-10-07 11:31:56 +01001740 if (ret < 0) {
1741 dev_err(bus->dev, "tplg component load failed%d\n", ret);
Sudip Mukherjeec14a82c2016-01-21 17:27:59 +05301742 release_firmware(fw);
Vinod Koul3af36702015-10-07 11:31:56 +01001743 return -EINVAL;
1744 }
1745
1746 skl->resource.max_mcps = SKL_MAX_MCPS;
1747 skl->resource.max_mem = SKL_FW_MAX_MEM;
1748
Vinod Kould8018362016-01-05 17:16:04 +05301749 skl->tplg = fw;
1750
Vinod Koul3af36702015-10-07 11:31:56 +01001751 return 0;
1752}