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Chunfeng Yundf2069a2016-10-19 10:28:23 +08001/*
2 * Copyright (C) 2016 MediaTek Inc.
3 *
4 * Author: Chunfeng Yun <chunfeng.yun@mediatek.com>
5 *
6 * This software is licensed under the terms of the GNU General Public
7 * License version 2, as published by the Free Software Foundation, and
8 * may be copied, distributed, and modified under those terms.
9 *
10 * This program is distributed in the hope that it will be useful,
11 * but WITHOUT ANY WARRANTY; without even the implied warranty of
12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 * GNU General Public License for more details.
14 *
15 */
16
17#include <linux/clk.h>
18#include <linux/dma-mapping.h>
19#include <linux/iopoll.h>
20#include <linux/kernel.h>
21#include <linux/module.h>
22#include <linux/of_address.h>
23#include <linux/of_irq.h>
24#include <linux/platform_device.h>
25
26#include "mtu3.h"
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080027#include "mtu3_dr.h"
Chunfeng Yundf2069a2016-10-19 10:28:23 +080028
29/* u2-port0 should be powered on and enabled; */
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080030int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks)
Chunfeng Yundf2069a2016-10-19 10:28:23 +080031{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080032 void __iomem *ibase = ssusb->ippc_base;
Chunfeng Yundf2069a2016-10-19 10:28:23 +080033 u32 value, check_val;
34 int ret;
35
36 check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE |
37 SSUSB_REF_RST_B_STS;
38
39 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value,
40 (check_val == (value & check_val)), 100, 20000);
41 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080042 dev_err(ssusb->dev, "clks of sts1 are not stable!\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +080043 return ret;
44 }
45
46 ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value,
47 (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000);
48 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080049 dev_err(ssusb->dev, "mac2 clock is not stable\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +080050 return ret;
51 }
52
53 return 0;
54}
55
Chunfeng Yunb3f4e722016-10-19 10:28:25 +080056static int ssusb_phy_init(struct ssusb_mtk *ssusb)
57{
58 int i;
59 int ret;
60
61 for (i = 0; i < ssusb->num_phys; i++) {
62 ret = phy_init(ssusb->phys[i]);
63 if (ret)
64 goto exit_phy;
65 }
66 return 0;
67
68exit_phy:
69 for (; i > 0; i--)
70 phy_exit(ssusb->phys[i - 1]);
71
72 return ret;
73}
74
75static int ssusb_phy_exit(struct ssusb_mtk *ssusb)
76{
77 int i;
78
79 for (i = 0; i < ssusb->num_phys; i++)
80 phy_exit(ssusb->phys[i]);
81
82 return 0;
83}
84
85static int ssusb_phy_power_on(struct ssusb_mtk *ssusb)
86{
87 int i;
88 int ret;
89
90 for (i = 0; i < ssusb->num_phys; i++) {
91 ret = phy_power_on(ssusb->phys[i]);
92 if (ret)
93 goto power_off_phy;
94 }
95 return 0;
96
97power_off_phy:
98 for (; i > 0; i--)
99 phy_power_off(ssusb->phys[i - 1]);
100
101 return ret;
102}
103
104static void ssusb_phy_power_off(struct ssusb_mtk *ssusb)
105{
106 unsigned int i;
107
108 for (i = 0; i < ssusb->num_phys; i++)
109 phy_power_off(ssusb->phys[i]);
110}
111
Chunfeng Yuna316da82017-10-13 17:10:40 +0800112static int ssusb_clks_enable(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800113{
Chunfeng Yuna316da82017-10-13 17:10:40 +0800114 int ret;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800115
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800116 ret = clk_prepare_enable(ssusb->sys_clk);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800117 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800118 dev_err(ssusb->dev, "failed to enable sys_clk\n");
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800119 goto sys_clk_err;
120 }
121
122 ret = clk_prepare_enable(ssusb->ref_clk);
123 if (ret) {
124 dev_err(ssusb->dev, "failed to enable ref_clk\n");
125 goto ref_clk_err;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800126 }
127
Chunfeng Yuna316da82017-10-13 17:10:40 +0800128 ret = clk_prepare_enable(ssusb->mcu_clk);
129 if (ret) {
130 dev_err(ssusb->dev, "failed to enable mcu_clk\n");
131 goto mcu_clk_err;
132 }
133
134 ret = clk_prepare_enable(ssusb->dma_clk);
135 if (ret) {
136 dev_err(ssusb->dev, "failed to enable dma_clk\n");
137 goto dma_clk_err;
138 }
139
140 return 0;
141
142dma_clk_err:
143 clk_disable_unprepare(ssusb->mcu_clk);
144mcu_clk_err:
145 clk_disable_unprepare(ssusb->ref_clk);
146ref_clk_err:
147 clk_disable_unprepare(ssusb->sys_clk);
148sys_clk_err:
149 return ret;
150}
151
152static void ssusb_clks_disable(struct ssusb_mtk *ssusb)
153{
154 clk_disable_unprepare(ssusb->dma_clk);
155 clk_disable_unprepare(ssusb->mcu_clk);
156 clk_disable_unprepare(ssusb->ref_clk);
157 clk_disable_unprepare(ssusb->sys_clk);
158}
159
160static int ssusb_rscs_init(struct ssusb_mtk *ssusb)
161{
162 int ret = 0;
163
164 ret = regulator_enable(ssusb->vusb33);
165 if (ret) {
166 dev_err(ssusb->dev, "failed to enable vusb33\n");
167 goto vusb33_err;
168 }
169
170 ret = ssusb_clks_enable(ssusb);
171 if (ret)
172 goto clks_err;
173
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800174 ret = ssusb_phy_init(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800175 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800176 dev_err(ssusb->dev, "failed to init phy\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800177 goto phy_init_err;
178 }
179
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800180 ret = ssusb_phy_power_on(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800181 if (ret) {
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800182 dev_err(ssusb->dev, "failed to power on phy\n");
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800183 goto phy_err;
184 }
185
186 return 0;
187
188phy_err:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800189 ssusb_phy_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800190phy_init_err:
Chunfeng Yuna316da82017-10-13 17:10:40 +0800191 ssusb_clks_disable(ssusb);
192clks_err:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800193 regulator_disable(ssusb->vusb33);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800194vusb33_err:
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800195 return ret;
196}
197
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800198static void ssusb_rscs_exit(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800199{
Chunfeng Yuna316da82017-10-13 17:10:40 +0800200 ssusb_clks_disable(ssusb);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800201 regulator_disable(ssusb->vusb33);
202 ssusb_phy_power_off(ssusb);
203 ssusb_phy_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800204}
205
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800206static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800207{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800208 /* reset whole ip (xhci & u3d) */
209 mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800210 udelay(1);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800211 mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800212}
213
Chunfeng Yuna316da82017-10-13 17:10:40 +0800214/* ignore the error if the clock does not exist */
215static struct clk *get_optional_clk(struct device *dev, const char *id)
216{
217 struct clk *opt_clk;
218
219 opt_clk = devm_clk_get(dev, id);
220 /* ignore error number except EPROBE_DEFER */
221 if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER))
222 opt_clk = NULL;
223
224 return opt_clk;
225}
226
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800227static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800228{
229 struct device_node *node = pdev->dev.of_node;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800230 struct otg_switch_mtk *otg_sx = &ssusb->otg_switch;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800231 struct device *dev = &pdev->dev;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800232 struct regulator *vbus;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800233 struct resource *res;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800234 int i;
235 int ret;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800236
Chunfeng Yun5cbf2d62017-01-18 14:08:22 +0800237 ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33");
238 if (IS_ERR(ssusb->vusb33)) {
239 dev_err(dev, "failed to get vusb33\n");
240 return PTR_ERR(ssusb->vusb33);
241 }
242
243 ssusb->sys_clk = devm_clk_get(dev, "sys_ck");
244 if (IS_ERR(ssusb->sys_clk)) {
245 dev_err(dev, "failed to get sys clock\n");
246 return PTR_ERR(ssusb->sys_clk);
247 }
248
Chunfeng Yuna316da82017-10-13 17:10:40 +0800249 ssusb->ref_clk = get_optional_clk(dev, "ref_ck");
250 if (IS_ERR(ssusb->ref_clk))
251 return PTR_ERR(ssusb->ref_clk);
Chunfeng Yunca12cb72017-02-07 14:13:32 +0800252
Chunfeng Yuna316da82017-10-13 17:10:40 +0800253 ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck");
254 if (IS_ERR(ssusb->mcu_clk))
255 return PTR_ERR(ssusb->mcu_clk);
256
257 ssusb->dma_clk = get_optional_clk(dev, "dma_ck");
258 if (IS_ERR(ssusb->dma_clk))
259 return PTR_ERR(ssusb->dma_clk);
Chunfeng Yun4d70d0c2017-01-18 14:08:23 +0800260
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800261 ssusb->num_phys = of_count_phandle_with_args(node,
262 "phys", "#phy-cells");
263 if (ssusb->num_phys > 0) {
264 ssusb->phys = devm_kcalloc(dev, ssusb->num_phys,
265 sizeof(*ssusb->phys), GFP_KERNEL);
266 if (!ssusb->phys)
267 return -ENOMEM;
268 } else {
269 ssusb->num_phys = 0;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800270 }
271
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800272 for (i = 0; i < ssusb->num_phys; i++) {
273 ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i);
274 if (IS_ERR(ssusb->phys[i])) {
275 dev_err(dev, "failed to get phy-%d\n", i);
276 return PTR_ERR(ssusb->phys[i]);
277 }
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800278 }
279
280 res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc");
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800281 ssusb->ippc_base = devm_ioremap_resource(dev, res);
Wei Yongjunb7ecfe72017-02-05 16:25:38 +0000282 if (IS_ERR(ssusb->ippc_base))
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800283 return PTR_ERR(ssusb->ippc_base);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800284
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800285 ssusb->dr_mode = usb_get_dr_mode(dev);
286 if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) {
287 dev_err(dev, "dr_mode is error\n");
288 return -EINVAL;
289 }
290
291 if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL)
292 return 0;
293
294 /* if host role is supported */
295 ret = ssusb_wakeup_of_property_parse(ssusb, node);
296 if (ret)
297 return ret;
298
Chunfeng Yun076f1a82017-10-13 17:10:38 +0800299 /* optional property, ignore the error if it does not exist */
300 of_property_read_u32(node, "mediatek,u3p-dis-msk",
301 &ssusb->u3p_dis_msk);
302
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800303 vbus = devm_regulator_get(&pdev->dev, "vbus");
304 if (IS_ERR(vbus)) {
305 dev_err(dev, "failed to get vbus\n");
306 return PTR_ERR(vbus);
307 }
308 otg_sx->vbus = vbus;
309
Chunfeng Yun6638ec52017-10-13 17:10:44 +0800310 if (ssusb->dr_mode == USB_DR_MODE_HOST)
311 return 0;
312
313 /* if dual-role mode is supported */
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800314 otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd");
315 otg_sx->manual_drd_enabled =
316 of_property_read_bool(node, "enable-manual-drd");
317
318 if (of_property_read_bool(node, "extcon")) {
319 otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0);
320 if (IS_ERR(otg_sx->edev)) {
321 dev_err(ssusb->dev, "couldn't get extcon device\n");
322 return -EPROBE_DEFER;
323 }
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800324 }
325
Chunfeng Yunc776f2c2017-10-13 17:10:42 +0800326 dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n",
327 ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk,
328 otg_sx->manual_drd_enabled ? "manual" : "auto");
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800329
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800330 return 0;
331}
332
333static int mtu3_probe(struct platform_device *pdev)
334{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800335 struct device_node *node = pdev->dev.of_node;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800336 struct device *dev = &pdev->dev;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800337 struct ssusb_mtk *ssusb;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800338 int ret = -ENOMEM;
339
340 /* all elements are set to ZERO as default value */
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800341 ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL);
342 if (!ssusb)
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800343 return -ENOMEM;
344
345 ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32));
346 if (ret) {
347 dev_err(dev, "No suitable DMA config available\n");
348 return -ENOTSUPP;
349 }
350
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800351 platform_set_drvdata(pdev, ssusb);
352 ssusb->dev = dev;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800353
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800354 ret = get_ssusb_rscs(pdev, ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800355 if (ret)
356 return ret;
357
358 /* enable power domain */
359 pm_runtime_enable(dev);
360 pm_runtime_get_sync(dev);
361 device_enable_async_suspend(dev);
362
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800363 ret = ssusb_rscs_init(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800364 if (ret)
365 goto comm_init_err;
366
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800367 ssusb_ip_sw_reset(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800368
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800369 if (IS_ENABLED(CONFIG_USB_MTU3_HOST))
370 ssusb->dr_mode = USB_DR_MODE_HOST;
371 else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET))
372 ssusb->dr_mode = USB_DR_MODE_PERIPHERAL;
373
374 /* default as host */
375 ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL);
376
377 switch (ssusb->dr_mode) {
378 case USB_DR_MODE_PERIPHERAL:
379 ret = ssusb_gadget_init(ssusb);
380 if (ret) {
381 dev_err(dev, "failed to initialize gadget\n");
382 goto comm_exit;
383 }
384 break;
385 case USB_DR_MODE_HOST:
386 ret = ssusb_host_init(ssusb, node);
387 if (ret) {
388 dev_err(dev, "failed to initialize host\n");
389 goto comm_exit;
390 }
391 break;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800392 case USB_DR_MODE_OTG:
393 ret = ssusb_gadget_init(ssusb);
394 if (ret) {
395 dev_err(dev, "failed to initialize gadget\n");
396 goto comm_exit;
397 }
398
399 ret = ssusb_host_init(ssusb, node);
400 if (ret) {
401 dev_err(dev, "failed to initialize host\n");
402 goto gadget_exit;
403 }
404
405 ssusb_otg_switch_init(ssusb);
406 break;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800407 default:
408 dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode);
409 ret = -EINVAL;
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800410 goto comm_exit;
411 }
412
413 return 0;
414
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800415gadget_exit:
416 ssusb_gadget_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800417comm_exit:
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800418 ssusb_rscs_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800419comm_init_err:
420 pm_runtime_put_sync(dev);
421 pm_runtime_disable(dev);
422
423 return ret;
424}
425
426static int mtu3_remove(struct platform_device *pdev)
427{
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800428 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800429
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800430 switch (ssusb->dr_mode) {
431 case USB_DR_MODE_PERIPHERAL:
432 ssusb_gadget_exit(ssusb);
433 break;
434 case USB_DR_MODE_HOST:
435 ssusb_host_exit(ssusb);
436 break;
Chunfeng Yund0ed0622016-10-19 10:28:26 +0800437 case USB_DR_MODE_OTG:
438 ssusb_otg_switch_exit(ssusb);
439 ssusb_gadget_exit(ssusb);
440 ssusb_host_exit(ssusb);
441 break;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800442 default:
443 return -EINVAL;
444 }
445
446 ssusb_rscs_exit(ssusb);
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800447 pm_runtime_put_sync(&pdev->dev);
448 pm_runtime_disable(&pdev->dev);
449
450 return 0;
451}
452
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800453/*
454 * when support dual-role mode, we reject suspend when
455 * it works as device mode;
456 */
457static int __maybe_unused mtu3_suspend(struct device *dev)
458{
459 struct platform_device *pdev = to_platform_device(dev);
460 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
461
462 dev_dbg(dev, "%s\n", __func__);
463
464 /* REVISIT: disconnect it for only device mode? */
465 if (!ssusb->is_host)
466 return 0;
467
468 ssusb_host_disable(ssusb, true);
469 ssusb_phy_power_off(ssusb);
Chunfeng Yuna316da82017-10-13 17:10:40 +0800470 ssusb_clks_disable(ssusb);
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800471 ssusb_wakeup_enable(ssusb);
472
473 return 0;
474}
475
476static int __maybe_unused mtu3_resume(struct device *dev)
477{
478 struct platform_device *pdev = to_platform_device(dev);
479 struct ssusb_mtk *ssusb = platform_get_drvdata(pdev);
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530480 int ret;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800481
482 dev_dbg(dev, "%s\n", __func__);
483
484 if (!ssusb->is_host)
485 return 0;
486
487 ssusb_wakeup_disable(ssusb);
Chunfeng Yuna316da82017-10-13 17:10:40 +0800488 ret = ssusb_clks_enable(ssusb);
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530489 if (ret)
Chunfeng Yuna316da82017-10-13 17:10:40 +0800490 goto clks_err;
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530491
492 ret = ssusb_phy_power_on(ssusb);
493 if (ret)
Chunfeng Yuna316da82017-10-13 17:10:40 +0800494 goto phy_err;
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530495
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800496 ssusb_host_enable(ssusb);
497
498 return 0;
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530499
Chunfeng Yuna316da82017-10-13 17:10:40 +0800500phy_err:
501 ssusb_clks_disable(ssusb);
502clks_err:
Arvind Yadav0f4c3f92017-06-09 17:33:31 +0530503 return ret;
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800504}
505
506static const struct dev_pm_ops mtu3_pm_ops = {
507 SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume)
508};
509
510#define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL)
511
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800512#ifdef CONFIG_OF
513
514static const struct of_device_id mtu3_of_match[] = {
515 {.compatible = "mediatek,mt8173-mtu3",},
Chunfeng Yundfcdcba2017-08-08 13:42:49 +0800516 {.compatible = "mediatek,mtu3",},
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800517 {},
518};
519
520MODULE_DEVICE_TABLE(of, mtu3_of_match);
521
522#endif
523
524static struct platform_driver mtu3_driver = {
525 .probe = mtu3_probe,
526 .remove = mtu3_remove,
527 .driver = {
528 .name = MTU3_DRIVER_NAME,
Chunfeng Yunb3f4e722016-10-19 10:28:25 +0800529 .pm = DEV_PM_OPS,
Chunfeng Yundf2069a2016-10-19 10:28:23 +0800530 .of_match_table = of_match_ptr(mtu3_of_match),
531 },
532};
533module_platform_driver(mtu3_driver);
534
535MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>");
536MODULE_LICENSE("GPL v2");
537MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver");