Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 1 | /* |
| 2 | * Copyright (C) 2016 MediaTek Inc. |
| 3 | * |
| 4 | * Author: Chunfeng Yun <chunfeng.yun@mediatek.com> |
| 5 | * |
| 6 | * This software is licensed under the terms of the GNU General Public |
| 7 | * License version 2, as published by the Free Software Foundation, and |
| 8 | * may be copied, distributed, and modified under those terms. |
| 9 | * |
| 10 | * This program is distributed in the hope that it will be useful, |
| 11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of |
| 12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
| 13 | * GNU General Public License for more details. |
| 14 | * |
| 15 | */ |
| 16 | |
| 17 | #include <linux/clk.h> |
| 18 | #include <linux/dma-mapping.h> |
| 19 | #include <linux/iopoll.h> |
| 20 | #include <linux/kernel.h> |
| 21 | #include <linux/module.h> |
| 22 | #include <linux/of_address.h> |
| 23 | #include <linux/of_irq.h> |
| 24 | #include <linux/platform_device.h> |
| 25 | |
| 26 | #include "mtu3.h" |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 27 | #include "mtu3_dr.h" |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 28 | |
| 29 | /* u2-port0 should be powered on and enabled; */ |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 30 | int ssusb_check_clocks(struct ssusb_mtk *ssusb, u32 ex_clks) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 31 | { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 32 | void __iomem *ibase = ssusb->ippc_base; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 33 | u32 value, check_val; |
| 34 | int ret; |
| 35 | |
| 36 | check_val = ex_clks | SSUSB_SYS125_RST_B_STS | SSUSB_SYSPLL_STABLE | |
| 37 | SSUSB_REF_RST_B_STS; |
| 38 | |
| 39 | ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS1, value, |
| 40 | (check_val == (value & check_val)), 100, 20000); |
| 41 | if (ret) { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 42 | dev_err(ssusb->dev, "clks of sts1 are not stable!\n"); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 43 | return ret; |
| 44 | } |
| 45 | |
| 46 | ret = readl_poll_timeout(ibase + U3D_SSUSB_IP_PW_STS2, value, |
| 47 | (value & SSUSB_U2_MAC_SYS_RST_B_STS), 100, 10000); |
| 48 | if (ret) { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 49 | dev_err(ssusb->dev, "mac2 clock is not stable\n"); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 50 | return ret; |
| 51 | } |
| 52 | |
| 53 | return 0; |
| 54 | } |
| 55 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 56 | static int ssusb_phy_init(struct ssusb_mtk *ssusb) |
| 57 | { |
| 58 | int i; |
| 59 | int ret; |
| 60 | |
| 61 | for (i = 0; i < ssusb->num_phys; i++) { |
| 62 | ret = phy_init(ssusb->phys[i]); |
| 63 | if (ret) |
| 64 | goto exit_phy; |
| 65 | } |
| 66 | return 0; |
| 67 | |
| 68 | exit_phy: |
| 69 | for (; i > 0; i--) |
| 70 | phy_exit(ssusb->phys[i - 1]); |
| 71 | |
| 72 | return ret; |
| 73 | } |
| 74 | |
| 75 | static int ssusb_phy_exit(struct ssusb_mtk *ssusb) |
| 76 | { |
| 77 | int i; |
| 78 | |
| 79 | for (i = 0; i < ssusb->num_phys; i++) |
| 80 | phy_exit(ssusb->phys[i]); |
| 81 | |
| 82 | return 0; |
| 83 | } |
| 84 | |
| 85 | static int ssusb_phy_power_on(struct ssusb_mtk *ssusb) |
| 86 | { |
| 87 | int i; |
| 88 | int ret; |
| 89 | |
| 90 | for (i = 0; i < ssusb->num_phys; i++) { |
| 91 | ret = phy_power_on(ssusb->phys[i]); |
| 92 | if (ret) |
| 93 | goto power_off_phy; |
| 94 | } |
| 95 | return 0; |
| 96 | |
| 97 | power_off_phy: |
| 98 | for (; i > 0; i--) |
| 99 | phy_power_off(ssusb->phys[i - 1]); |
| 100 | |
| 101 | return ret; |
| 102 | } |
| 103 | |
| 104 | static void ssusb_phy_power_off(struct ssusb_mtk *ssusb) |
| 105 | { |
| 106 | unsigned int i; |
| 107 | |
| 108 | for (i = 0; i < ssusb->num_phys; i++) |
| 109 | phy_power_off(ssusb->phys[i]); |
| 110 | } |
| 111 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 112 | static int ssusb_clks_enable(struct ssusb_mtk *ssusb) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 113 | { |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 114 | int ret; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 115 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 116 | ret = clk_prepare_enable(ssusb->sys_clk); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 117 | if (ret) { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 118 | dev_err(ssusb->dev, "failed to enable sys_clk\n"); |
Chunfeng Yun | 4d70d0c | 2017-01-18 14:08:23 +0800 | [diff] [blame] | 119 | goto sys_clk_err; |
| 120 | } |
| 121 | |
| 122 | ret = clk_prepare_enable(ssusb->ref_clk); |
| 123 | if (ret) { |
| 124 | dev_err(ssusb->dev, "failed to enable ref_clk\n"); |
| 125 | goto ref_clk_err; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 126 | } |
| 127 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 128 | ret = clk_prepare_enable(ssusb->mcu_clk); |
| 129 | if (ret) { |
| 130 | dev_err(ssusb->dev, "failed to enable mcu_clk\n"); |
| 131 | goto mcu_clk_err; |
| 132 | } |
| 133 | |
| 134 | ret = clk_prepare_enable(ssusb->dma_clk); |
| 135 | if (ret) { |
| 136 | dev_err(ssusb->dev, "failed to enable dma_clk\n"); |
| 137 | goto dma_clk_err; |
| 138 | } |
| 139 | |
| 140 | return 0; |
| 141 | |
| 142 | dma_clk_err: |
| 143 | clk_disable_unprepare(ssusb->mcu_clk); |
| 144 | mcu_clk_err: |
| 145 | clk_disable_unprepare(ssusb->ref_clk); |
| 146 | ref_clk_err: |
| 147 | clk_disable_unprepare(ssusb->sys_clk); |
| 148 | sys_clk_err: |
| 149 | return ret; |
| 150 | } |
| 151 | |
| 152 | static void ssusb_clks_disable(struct ssusb_mtk *ssusb) |
| 153 | { |
| 154 | clk_disable_unprepare(ssusb->dma_clk); |
| 155 | clk_disable_unprepare(ssusb->mcu_clk); |
| 156 | clk_disable_unprepare(ssusb->ref_clk); |
| 157 | clk_disable_unprepare(ssusb->sys_clk); |
| 158 | } |
| 159 | |
| 160 | static int ssusb_rscs_init(struct ssusb_mtk *ssusb) |
| 161 | { |
| 162 | int ret = 0; |
| 163 | |
| 164 | ret = regulator_enable(ssusb->vusb33); |
| 165 | if (ret) { |
| 166 | dev_err(ssusb->dev, "failed to enable vusb33\n"); |
| 167 | goto vusb33_err; |
| 168 | } |
| 169 | |
| 170 | ret = ssusb_clks_enable(ssusb); |
| 171 | if (ret) |
| 172 | goto clks_err; |
| 173 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 174 | ret = ssusb_phy_init(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 175 | if (ret) { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 176 | dev_err(ssusb->dev, "failed to init phy\n"); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 177 | goto phy_init_err; |
| 178 | } |
| 179 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 180 | ret = ssusb_phy_power_on(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 181 | if (ret) { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 182 | dev_err(ssusb->dev, "failed to power on phy\n"); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 183 | goto phy_err; |
| 184 | } |
| 185 | |
| 186 | return 0; |
| 187 | |
| 188 | phy_err: |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 189 | ssusb_phy_exit(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 190 | phy_init_err: |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 191 | ssusb_clks_disable(ssusb); |
| 192 | clks_err: |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 193 | regulator_disable(ssusb->vusb33); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 194 | vusb33_err: |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 195 | return ret; |
| 196 | } |
| 197 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 198 | static void ssusb_rscs_exit(struct ssusb_mtk *ssusb) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 199 | { |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 200 | ssusb_clks_disable(ssusb); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 201 | regulator_disable(ssusb->vusb33); |
| 202 | ssusb_phy_power_off(ssusb); |
| 203 | ssusb_phy_exit(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 204 | } |
| 205 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 206 | static void ssusb_ip_sw_reset(struct ssusb_mtk *ssusb) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 207 | { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 208 | /* reset whole ip (xhci & u3d) */ |
| 209 | mtu3_setbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 210 | udelay(1); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 211 | mtu3_clrbits(ssusb->ippc_base, U3D_SSUSB_IP_PW_CTRL0, SSUSB_IP_SW_RST); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 212 | } |
| 213 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 214 | /* ignore the error if the clock does not exist */ |
| 215 | static struct clk *get_optional_clk(struct device *dev, const char *id) |
| 216 | { |
| 217 | struct clk *opt_clk; |
| 218 | |
| 219 | opt_clk = devm_clk_get(dev, id); |
| 220 | /* ignore error number except EPROBE_DEFER */ |
| 221 | if (IS_ERR(opt_clk) && (PTR_ERR(opt_clk) != -EPROBE_DEFER)) |
| 222 | opt_clk = NULL; |
| 223 | |
| 224 | return opt_clk; |
| 225 | } |
| 226 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 227 | static int get_ssusb_rscs(struct platform_device *pdev, struct ssusb_mtk *ssusb) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 228 | { |
| 229 | struct device_node *node = pdev->dev.of_node; |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 230 | struct otg_switch_mtk *otg_sx = &ssusb->otg_switch; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 231 | struct device *dev = &pdev->dev; |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 232 | struct regulator *vbus; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 233 | struct resource *res; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 234 | int i; |
| 235 | int ret; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 236 | |
Chunfeng Yun | 5cbf2d6 | 2017-01-18 14:08:22 +0800 | [diff] [blame] | 237 | ssusb->vusb33 = devm_regulator_get(&pdev->dev, "vusb33"); |
| 238 | if (IS_ERR(ssusb->vusb33)) { |
| 239 | dev_err(dev, "failed to get vusb33\n"); |
| 240 | return PTR_ERR(ssusb->vusb33); |
| 241 | } |
| 242 | |
| 243 | ssusb->sys_clk = devm_clk_get(dev, "sys_ck"); |
| 244 | if (IS_ERR(ssusb->sys_clk)) { |
| 245 | dev_err(dev, "failed to get sys clock\n"); |
| 246 | return PTR_ERR(ssusb->sys_clk); |
| 247 | } |
| 248 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 249 | ssusb->ref_clk = get_optional_clk(dev, "ref_ck"); |
| 250 | if (IS_ERR(ssusb->ref_clk)) |
| 251 | return PTR_ERR(ssusb->ref_clk); |
Chunfeng Yun | ca12cb7 | 2017-02-07 14:13:32 +0800 | [diff] [blame] | 252 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 253 | ssusb->mcu_clk = get_optional_clk(dev, "mcu_ck"); |
| 254 | if (IS_ERR(ssusb->mcu_clk)) |
| 255 | return PTR_ERR(ssusb->mcu_clk); |
| 256 | |
| 257 | ssusb->dma_clk = get_optional_clk(dev, "dma_ck"); |
| 258 | if (IS_ERR(ssusb->dma_clk)) |
| 259 | return PTR_ERR(ssusb->dma_clk); |
Chunfeng Yun | 4d70d0c | 2017-01-18 14:08:23 +0800 | [diff] [blame] | 260 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 261 | ssusb->num_phys = of_count_phandle_with_args(node, |
| 262 | "phys", "#phy-cells"); |
| 263 | if (ssusb->num_phys > 0) { |
| 264 | ssusb->phys = devm_kcalloc(dev, ssusb->num_phys, |
| 265 | sizeof(*ssusb->phys), GFP_KERNEL); |
| 266 | if (!ssusb->phys) |
| 267 | return -ENOMEM; |
| 268 | } else { |
| 269 | ssusb->num_phys = 0; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 270 | } |
| 271 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 272 | for (i = 0; i < ssusb->num_phys; i++) { |
| 273 | ssusb->phys[i] = devm_of_phy_get_by_index(dev, node, i); |
| 274 | if (IS_ERR(ssusb->phys[i])) { |
| 275 | dev_err(dev, "failed to get phy-%d\n", i); |
| 276 | return PTR_ERR(ssusb->phys[i]); |
| 277 | } |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 278 | } |
| 279 | |
| 280 | res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "ippc"); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 281 | ssusb->ippc_base = devm_ioremap_resource(dev, res); |
Wei Yongjun | b7ecfe7 | 2017-02-05 16:25:38 +0000 | [diff] [blame] | 282 | if (IS_ERR(ssusb->ippc_base)) |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 283 | return PTR_ERR(ssusb->ippc_base); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 284 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 285 | ssusb->dr_mode = usb_get_dr_mode(dev); |
| 286 | if (ssusb->dr_mode == USB_DR_MODE_UNKNOWN) { |
| 287 | dev_err(dev, "dr_mode is error\n"); |
| 288 | return -EINVAL; |
| 289 | } |
| 290 | |
| 291 | if (ssusb->dr_mode == USB_DR_MODE_PERIPHERAL) |
| 292 | return 0; |
| 293 | |
| 294 | /* if host role is supported */ |
| 295 | ret = ssusb_wakeup_of_property_parse(ssusb, node); |
| 296 | if (ret) |
| 297 | return ret; |
| 298 | |
Chunfeng Yun | 076f1a8 | 2017-10-13 17:10:38 +0800 | [diff] [blame] | 299 | /* optional property, ignore the error if it does not exist */ |
| 300 | of_property_read_u32(node, "mediatek,u3p-dis-msk", |
| 301 | &ssusb->u3p_dis_msk); |
| 302 | |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 303 | vbus = devm_regulator_get(&pdev->dev, "vbus"); |
| 304 | if (IS_ERR(vbus)) { |
| 305 | dev_err(dev, "failed to get vbus\n"); |
| 306 | return PTR_ERR(vbus); |
| 307 | } |
| 308 | otg_sx->vbus = vbus; |
| 309 | |
Chunfeng Yun | 6638ec5 | 2017-10-13 17:10:44 +0800 | [diff] [blame^] | 310 | if (ssusb->dr_mode == USB_DR_MODE_HOST) |
| 311 | return 0; |
| 312 | |
| 313 | /* if dual-role mode is supported */ |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 314 | otg_sx->is_u3_drd = of_property_read_bool(node, "mediatek,usb3-drd"); |
| 315 | otg_sx->manual_drd_enabled = |
| 316 | of_property_read_bool(node, "enable-manual-drd"); |
| 317 | |
| 318 | if (of_property_read_bool(node, "extcon")) { |
| 319 | otg_sx->edev = extcon_get_edev_by_phandle(ssusb->dev, 0); |
| 320 | if (IS_ERR(otg_sx->edev)) { |
| 321 | dev_err(ssusb->dev, "couldn't get extcon device\n"); |
| 322 | return -EPROBE_DEFER; |
| 323 | } |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 324 | } |
| 325 | |
Chunfeng Yun | c776f2c | 2017-10-13 17:10:42 +0800 | [diff] [blame] | 326 | dev_info(dev, "dr_mode: %d, is_u3_dr: %d, u3p_dis_msk: %x, drd: %s\n", |
| 327 | ssusb->dr_mode, otg_sx->is_u3_drd, ssusb->u3p_dis_msk, |
| 328 | otg_sx->manual_drd_enabled ? "manual" : "auto"); |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 329 | |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 330 | return 0; |
| 331 | } |
| 332 | |
| 333 | static int mtu3_probe(struct platform_device *pdev) |
| 334 | { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 335 | struct device_node *node = pdev->dev.of_node; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 336 | struct device *dev = &pdev->dev; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 337 | struct ssusb_mtk *ssusb; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 338 | int ret = -ENOMEM; |
| 339 | |
| 340 | /* all elements are set to ZERO as default value */ |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 341 | ssusb = devm_kzalloc(dev, sizeof(*ssusb), GFP_KERNEL); |
| 342 | if (!ssusb) |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 343 | return -ENOMEM; |
| 344 | |
| 345 | ret = dma_set_mask_and_coherent(dev, DMA_BIT_MASK(32)); |
| 346 | if (ret) { |
| 347 | dev_err(dev, "No suitable DMA config available\n"); |
| 348 | return -ENOTSUPP; |
| 349 | } |
| 350 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 351 | platform_set_drvdata(pdev, ssusb); |
| 352 | ssusb->dev = dev; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 353 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 354 | ret = get_ssusb_rscs(pdev, ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 355 | if (ret) |
| 356 | return ret; |
| 357 | |
| 358 | /* enable power domain */ |
| 359 | pm_runtime_enable(dev); |
| 360 | pm_runtime_get_sync(dev); |
| 361 | device_enable_async_suspend(dev); |
| 362 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 363 | ret = ssusb_rscs_init(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 364 | if (ret) |
| 365 | goto comm_init_err; |
| 366 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 367 | ssusb_ip_sw_reset(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 368 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 369 | if (IS_ENABLED(CONFIG_USB_MTU3_HOST)) |
| 370 | ssusb->dr_mode = USB_DR_MODE_HOST; |
| 371 | else if (IS_ENABLED(CONFIG_USB_MTU3_GADGET)) |
| 372 | ssusb->dr_mode = USB_DR_MODE_PERIPHERAL; |
| 373 | |
| 374 | /* default as host */ |
| 375 | ssusb->is_host = !(ssusb->dr_mode == USB_DR_MODE_PERIPHERAL); |
| 376 | |
| 377 | switch (ssusb->dr_mode) { |
| 378 | case USB_DR_MODE_PERIPHERAL: |
| 379 | ret = ssusb_gadget_init(ssusb); |
| 380 | if (ret) { |
| 381 | dev_err(dev, "failed to initialize gadget\n"); |
| 382 | goto comm_exit; |
| 383 | } |
| 384 | break; |
| 385 | case USB_DR_MODE_HOST: |
| 386 | ret = ssusb_host_init(ssusb, node); |
| 387 | if (ret) { |
| 388 | dev_err(dev, "failed to initialize host\n"); |
| 389 | goto comm_exit; |
| 390 | } |
| 391 | break; |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 392 | case USB_DR_MODE_OTG: |
| 393 | ret = ssusb_gadget_init(ssusb); |
| 394 | if (ret) { |
| 395 | dev_err(dev, "failed to initialize gadget\n"); |
| 396 | goto comm_exit; |
| 397 | } |
| 398 | |
| 399 | ret = ssusb_host_init(ssusb, node); |
| 400 | if (ret) { |
| 401 | dev_err(dev, "failed to initialize host\n"); |
| 402 | goto gadget_exit; |
| 403 | } |
| 404 | |
| 405 | ssusb_otg_switch_init(ssusb); |
| 406 | break; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 407 | default: |
| 408 | dev_err(dev, "unsupported mode: %d\n", ssusb->dr_mode); |
| 409 | ret = -EINVAL; |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 410 | goto comm_exit; |
| 411 | } |
| 412 | |
| 413 | return 0; |
| 414 | |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 415 | gadget_exit: |
| 416 | ssusb_gadget_exit(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 417 | comm_exit: |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 418 | ssusb_rscs_exit(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 419 | comm_init_err: |
| 420 | pm_runtime_put_sync(dev); |
| 421 | pm_runtime_disable(dev); |
| 422 | |
| 423 | return ret; |
| 424 | } |
| 425 | |
| 426 | static int mtu3_remove(struct platform_device *pdev) |
| 427 | { |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 428 | struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 429 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 430 | switch (ssusb->dr_mode) { |
| 431 | case USB_DR_MODE_PERIPHERAL: |
| 432 | ssusb_gadget_exit(ssusb); |
| 433 | break; |
| 434 | case USB_DR_MODE_HOST: |
| 435 | ssusb_host_exit(ssusb); |
| 436 | break; |
Chunfeng Yun | d0ed062 | 2016-10-19 10:28:26 +0800 | [diff] [blame] | 437 | case USB_DR_MODE_OTG: |
| 438 | ssusb_otg_switch_exit(ssusb); |
| 439 | ssusb_gadget_exit(ssusb); |
| 440 | ssusb_host_exit(ssusb); |
| 441 | break; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 442 | default: |
| 443 | return -EINVAL; |
| 444 | } |
| 445 | |
| 446 | ssusb_rscs_exit(ssusb); |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 447 | pm_runtime_put_sync(&pdev->dev); |
| 448 | pm_runtime_disable(&pdev->dev); |
| 449 | |
| 450 | return 0; |
| 451 | } |
| 452 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 453 | /* |
| 454 | * when support dual-role mode, we reject suspend when |
| 455 | * it works as device mode; |
| 456 | */ |
| 457 | static int __maybe_unused mtu3_suspend(struct device *dev) |
| 458 | { |
| 459 | struct platform_device *pdev = to_platform_device(dev); |
| 460 | struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); |
| 461 | |
| 462 | dev_dbg(dev, "%s\n", __func__); |
| 463 | |
| 464 | /* REVISIT: disconnect it for only device mode? */ |
| 465 | if (!ssusb->is_host) |
| 466 | return 0; |
| 467 | |
| 468 | ssusb_host_disable(ssusb, true); |
| 469 | ssusb_phy_power_off(ssusb); |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 470 | ssusb_clks_disable(ssusb); |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 471 | ssusb_wakeup_enable(ssusb); |
| 472 | |
| 473 | return 0; |
| 474 | } |
| 475 | |
| 476 | static int __maybe_unused mtu3_resume(struct device *dev) |
| 477 | { |
| 478 | struct platform_device *pdev = to_platform_device(dev); |
| 479 | struct ssusb_mtk *ssusb = platform_get_drvdata(pdev); |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 480 | int ret; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 481 | |
| 482 | dev_dbg(dev, "%s\n", __func__); |
| 483 | |
| 484 | if (!ssusb->is_host) |
| 485 | return 0; |
| 486 | |
| 487 | ssusb_wakeup_disable(ssusb); |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 488 | ret = ssusb_clks_enable(ssusb); |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 489 | if (ret) |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 490 | goto clks_err; |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 491 | |
| 492 | ret = ssusb_phy_power_on(ssusb); |
| 493 | if (ret) |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 494 | goto phy_err; |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 495 | |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 496 | ssusb_host_enable(ssusb); |
| 497 | |
| 498 | return 0; |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 499 | |
Chunfeng Yun | a316da8 | 2017-10-13 17:10:40 +0800 | [diff] [blame] | 500 | phy_err: |
| 501 | ssusb_clks_disable(ssusb); |
| 502 | clks_err: |
Arvind Yadav | 0f4c3f9 | 2017-06-09 17:33:31 +0530 | [diff] [blame] | 503 | return ret; |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 504 | } |
| 505 | |
| 506 | static const struct dev_pm_ops mtu3_pm_ops = { |
| 507 | SET_SYSTEM_SLEEP_PM_OPS(mtu3_suspend, mtu3_resume) |
| 508 | }; |
| 509 | |
| 510 | #define DEV_PM_OPS (IS_ENABLED(CONFIG_PM) ? &mtu3_pm_ops : NULL) |
| 511 | |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 512 | #ifdef CONFIG_OF |
| 513 | |
| 514 | static const struct of_device_id mtu3_of_match[] = { |
| 515 | {.compatible = "mediatek,mt8173-mtu3",}, |
Chunfeng Yun | dfcdcba | 2017-08-08 13:42:49 +0800 | [diff] [blame] | 516 | {.compatible = "mediatek,mtu3",}, |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 517 | {}, |
| 518 | }; |
| 519 | |
| 520 | MODULE_DEVICE_TABLE(of, mtu3_of_match); |
| 521 | |
| 522 | #endif |
| 523 | |
| 524 | static struct platform_driver mtu3_driver = { |
| 525 | .probe = mtu3_probe, |
| 526 | .remove = mtu3_remove, |
| 527 | .driver = { |
| 528 | .name = MTU3_DRIVER_NAME, |
Chunfeng Yun | b3f4e72 | 2016-10-19 10:28:25 +0800 | [diff] [blame] | 529 | .pm = DEV_PM_OPS, |
Chunfeng Yun | df2069a | 2016-10-19 10:28:23 +0800 | [diff] [blame] | 530 | .of_match_table = of_match_ptr(mtu3_of_match), |
| 531 | }, |
| 532 | }; |
| 533 | module_platform_driver(mtu3_driver); |
| 534 | |
| 535 | MODULE_AUTHOR("Chunfeng Yun <chunfeng.yun@mediatek.com>"); |
| 536 | MODULE_LICENSE("GPL v2"); |
| 537 | MODULE_DESCRIPTION("MediaTek USB3 DRD Controller Driver"); |