blob: f29369622d2ca0a5223ed2de9861b16c16b6a659 [file] [log] [blame]
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001/*
2 * Copyright © 2011 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Jesse Barnes <jbarnes@virtuousgeek.org>
25 *
26 * New plane/sprite handling.
27 *
28 * The older chips had a separate interface for programming plane related
29 * registers; newer ones are much simpler and we can use the new DRM plane
30 * support.
31 */
David Howells760285e2012-10-02 18:01:07 +010032#include <drm/drmP.h>
Ben Widawsky714244e2017-08-01 09:58:16 -070033#include <drm/drm_atomic_helper.h>
David Howells760285e2012-10-02 18:01:07 +010034#include <drm/drm_crtc.h>
35#include <drm/drm_fourcc.h>
Ville Syrjälä17316932013-04-24 18:52:38 +030036#include <drm/drm_rect.h>
Chandra Konduruc3318792015-04-15 15:15:02 -070037#include <drm/drm_atomic.h>
Matt Roperea2c67b2014-12-23 10:41:52 -080038#include <drm/drm_plane_helper.h>
Jesse Barnesb840d907f2011-12-13 13:19:38 -080039#include "intel_drv.h"
Chris Wilson5d723d72016-08-04 16:32:35 +010040#include "intel_frontbuffer.h"
David Howells760285e2012-10-02 18:01:07 +010041#include <drm/i915_drm.h>
Jesse Barnesb840d907f2011-12-13 13:19:38 -080042#include "i915_drv.h"
43
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +030044static bool
45format_is_yuv(uint32_t format)
46{
47 switch (format) {
48 case DRM_FORMAT_YUYV:
49 case DRM_FORMAT_UYVY:
50 case DRM_FORMAT_VYUY:
51 case DRM_FORMAT_YVYU:
52 return true;
53 default:
54 return false;
55 }
56}
57
Ville Syrjälädfd2e9a2016-05-18 11:34:38 +030058int intel_usecs_to_scanlines(const struct drm_display_mode *adjusted_mode,
59 int usecs)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030060{
61 /* paranoia */
Ville Syrjälä5e7234c2015-09-25 16:37:43 +030062 if (!adjusted_mode->crtc_htotal)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030063 return 1;
64
Ville Syrjälä5e7234c2015-09-25 16:37:43 +030065 return DIV_ROUND_UP(usecs * adjusted_mode->crtc_clock,
66 1000 * adjusted_mode->crtc_htotal);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030067}
68
Daniel Vetter69208c92017-10-10 11:18:16 +020069/* FIXME: We should instead only take spinlocks once for the entire update
70 * instead of once per mmio. */
71#if IS_ENABLED(CONFIG_PROVE_LOCKING)
72#define VBLANK_EVASION_TIME_US 250
73#else
Maarten Lankhorste1edbd42017-02-28 15:28:48 +010074#define VBLANK_EVASION_TIME_US 100
Daniel Vetter69208c92017-10-10 11:18:16 +020075#endif
Maarten Lankhorste1edbd42017-02-28 15:28:48 +010076
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +020077/**
78 * intel_pipe_update_start() - start update of a set of display registers
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030079 * @new_crtc_state: the new crtc state
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +020080 *
81 * Mark the start of an update to pipe registers that should be updated
82 * atomically regarding vblank. If the next vblank will happens within
83 * the next 100 us, this function waits until the vblank passes.
84 *
85 * After a successful call to this function, interrupts will be disabled
86 * until a subsequent call to intel_pipe_update_end(). That is done to
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030087 * avoid random delays.
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +020088 */
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030089void intel_pipe_update_start(const struct intel_crtc_state *new_crtc_state)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030090{
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030091 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
Ville Syrjäläec1b4ee2016-12-15 19:47:34 +020092 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030093 const struct drm_display_mode *adjusted_mode = &new_crtc_state->base.adjusted_mode;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030094 long timeout = msecs_to_jiffies_timeout(1);
95 int scanline, min, max, vblank_start;
Ville Syrjälä210871b2014-05-22 19:00:50 +030096 wait_queue_head_t *wq = drm_crtc_vblank_waitqueue(&crtc->base);
Ville Syrjäläec1b4ee2016-12-15 19:47:34 +020097 bool need_vlv_dsi_wa = (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +030098 intel_crtc_has_type(new_crtc_state, INTEL_OUTPUT_DSI);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +030099 DEFINE_WAIT(wait);
100
Ville Syrjälä124abe02015-09-08 13:40:45 +0300101 vblank_start = adjusted_mode->crtc_vblank_start;
102 if (adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300103 vblank_start = DIV_ROUND_UP(vblank_start, 2);
104
105 /* FIXME needs to be calibrated sensibly */
Maarten Lankhorste1edbd42017-02-28 15:28:48 +0100106 min = vblank_start - intel_usecs_to_scanlines(adjusted_mode,
107 VBLANK_EVASION_TIME_US);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300108 max = vblank_start - 1;
109
Maarten Lankhorst8f539a82015-07-13 16:30:32 +0200110 local_irq_disable();
Maarten Lankhorst8f539a82015-07-13 16:30:32 +0200111
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300112 if (min <= 0 || max <= 0)
Maarten Lankhorst8f539a82015-07-13 16:30:32 +0200113 return;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300114
Daniel Vetter1e3feef2015-02-13 21:03:45 +0100115 if (WARN_ON(drm_crtc_vblank_get(&crtc->base)))
Maarten Lankhorst8f539a82015-07-13 16:30:32 +0200116 return;
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300117
Jesse Barnesd637ce32015-09-17 08:08:32 -0700118 crtc->debug.min_vbl = min;
119 crtc->debug.max_vbl = max;
120 trace_i915_pipe_update_start(crtc);
Ville Syrjälä25ef2842014-04-29 13:35:48 +0300121
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300122 for (;;) {
123 /*
124 * prepare_to_wait() has a memory barrier, which guarantees
125 * other CPUs can see the task state update by the time we
126 * read the scanline.
127 */
Ville Syrjälä210871b2014-05-22 19:00:50 +0300128 prepare_to_wait(wq, &wait, TASK_UNINTERRUPTIBLE);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300129
130 scanline = intel_get_crtc_scanline(crtc);
131 if (scanline < min || scanline > max)
132 break;
133
134 if (timeout <= 0) {
135 DRM_ERROR("Potential atomic update failure on pipe %c\n",
136 pipe_name(crtc->pipe));
137 break;
138 }
139
140 local_irq_enable();
141
142 timeout = schedule_timeout(timeout);
143
144 local_irq_disable();
145 }
146
Ville Syrjälä210871b2014-05-22 19:00:50 +0300147 finish_wait(wq, &wait);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300148
Daniel Vetter1e3feef2015-02-13 21:03:45 +0100149 drm_crtc_vblank_put(&crtc->base);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300150
Ville Syrjäläec1b4ee2016-12-15 19:47:34 +0200151 /*
152 * On VLV/CHV DSI the scanline counter would appear to
153 * increment approx. 1/3 of a scanline before start of vblank.
154 * The registers still get latched at start of vblank however.
155 * This means we must not write any registers on the first
156 * line of vblank (since not the whole line is actually in
157 * vblank). And unfortunately we can't use the interrupt to
158 * wait here since it will fire too soon. We could use the
159 * frame start interrupt instead since it will fire after the
160 * critical scanline, but that would require more changes
161 * in the interrupt code. So for now we'll just do the nasty
162 * thing and poll for the bad scanline to pass us by.
163 *
164 * FIXME figure out if BXT+ DSI suffers from this as well
165 */
166 while (need_vlv_dsi_wa && scanline == vblank_start)
167 scanline = intel_get_crtc_scanline(crtc);
168
Jesse Barneseb120ef2015-09-15 14:19:32 -0700169 crtc->debug.scanline_start = scanline;
170 crtc->debug.start_vbl_time = ktime_get();
Maarten Lankhorsta2991412016-05-17 15:07:48 +0200171 crtc->debug.start_vbl_count = intel_crtc_get_vblank_counter(crtc);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300172
Jesse Barnesd637ce32015-09-17 08:08:32 -0700173 trace_i915_pipe_update_vblank_evaded(crtc);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300174}
175
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +0200176/**
177 * intel_pipe_update_end() - end update of a set of display registers
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300178 * @new_crtc_state: the new crtc state
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +0200179 *
180 * Mark the end of an update started with intel_pipe_update_start(). This
181 * re-enables interrupts and verifies the update was actually completed
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300182 * before a vblank.
Ander Conselvan de Oliveira26ff2762014-10-28 15:10:12 +0200183 */
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300184void intel_pipe_update_end(struct intel_crtc_state *new_crtc_state)
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300185{
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300186 struct intel_crtc *crtc = to_intel_crtc(new_crtc_state->base.crtc);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300187 enum pipe pipe = crtc->pipe;
Jesse Barneseb120ef2015-09-15 14:19:32 -0700188 int scanline_end = intel_get_crtc_scanline(crtc);
Maarten Lankhorsta2991412016-05-17 15:07:48 +0200189 u32 end_vbl_count = intel_crtc_get_vblank_counter(crtc);
Maarten Lankhorst85a62bf2015-09-01 12:15:33 +0200190 ktime_t end_vbl_time = ktime_get();
Bing Niua94f2b92017-03-08 15:14:03 -0500191 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300192
Jesse Barnesd637ce32015-09-17 08:08:32 -0700193 trace_i915_pipe_update_end(crtc, end_vbl_count, scanline_end);
Ville Syrjälä25ef2842014-04-29 13:35:48 +0300194
Daniel Vetter1f7528c2016-06-13 16:13:45 +0200195 /* We're still in the vblank-evade critical section, this can't race.
196 * Would be slightly nice to just grab the vblank count and arm the
197 * event outside of the critical section - the spinlock might spin for a
198 * while ... */
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300199 if (new_crtc_state->base.event) {
Daniel Vetter1f7528c2016-06-13 16:13:45 +0200200 WARN_ON(drm_crtc_vblank_get(&crtc->base) != 0);
201
202 spin_lock(&crtc->base.dev->event_lock);
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300203 drm_crtc_arm_vblank_event(&crtc->base, new_crtc_state->base.event);
Daniel Vetter1f7528c2016-06-13 16:13:45 +0200204 spin_unlock(&crtc->base.dev->event_lock);
205
Ville Syrjäläd3a8fb32017-08-23 18:22:21 +0300206 new_crtc_state->base.event = NULL;
Daniel Vetter1f7528c2016-06-13 16:13:45 +0200207 }
208
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300209 local_irq_enable();
210
Bing Niua94f2b92017-03-08 15:14:03 -0500211 if (intel_vgpu_active(dev_priv))
212 return;
213
Jesse Barneseb120ef2015-09-15 14:19:32 -0700214 if (crtc->debug.start_vbl_count &&
215 crtc->debug.start_vbl_count != end_vbl_count) {
216 DRM_ERROR("Atomic update failure on pipe %c (start=%u end=%u) time %lld us, min %d, max %d, scanline start %d, end %d\n",
217 pipe_name(pipe), crtc->debug.start_vbl_count,
218 end_vbl_count,
219 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
220 crtc->debug.min_vbl, crtc->debug.max_vbl,
221 crtc->debug.scanline_start, scanline_end);
Ville Syrjälä7b8cd332017-05-07 20:12:52 +0300222 }
223#ifdef CONFIG_DRM_I915_DEBUG_VBLANK_EVADE
224 else if (ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time) >
225 VBLANK_EVASION_TIME_US)
Maarten Lankhorste1edbd42017-02-28 15:28:48 +0100226 DRM_WARN("Atomic update on pipe (%c) took %lld us, max time under evasion is %u us\n",
227 pipe_name(pipe),
228 ktime_us_delta(end_vbl_time, crtc->debug.start_vbl_time),
229 VBLANK_EVASION_TIME_US);
Ville Syrjälä7b8cd332017-05-07 20:12:52 +0300230#endif
Ville Syrjälä8d7849d2014-04-29 13:35:46 +0300231}
232
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800233static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300234skl_update_plane(struct intel_plane *plane,
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100235 const struct intel_crtc_state *crtc_state,
236 const struct intel_plane_state *plane_state)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000237{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300238 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
239 const struct drm_framebuffer *fb = plane_state->base.fb;
240 enum plane_id plane_id = plane->id;
241 enum pipe pipe = plane->pipe;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200242 u32 plane_ctl = plane_state->ctl;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100243 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200244 u32 surf_addr = plane_state->main.offset;
Ville Syrjälä8d0deca2016-02-15 22:54:41 +0200245 unsigned int rotation = plane_state->base.rotation;
Ville Syrjäläd2196772016-01-28 18:33:11 +0200246 u32 stride = skl_plane_stride(fb, 0, rotation);
Ville Syrjälä2e2adb02017-08-01 09:58:13 -0700247 u32 aux_stride = skl_plane_stride(fb, 1, rotation);
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300248 int crtc_x = plane_state->base.dst.x1;
249 int crtc_y = plane_state->base.dst.y1;
250 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
251 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200252 uint32_t x = plane_state->main.x;
253 uint32_t y = plane_state->main.y;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300254 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
255 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200256 unsigned long irqflags;
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000257
Ville Syrjälä6687c902015-09-15 13:16:41 +0300258 /* Sizes are 0 based */
259 src_w--;
260 src_h--;
261 crtc_w--;
262 crtc_h--;
263
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200264 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
265
Rodrigo Vivi6602be02017-07-06 14:01:13 -0700266 if (IS_GEMINILAKE(dev_priv) || IS_CANNONLAKE(dev_priv)) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200267 I915_WRITE_FW(PLANE_COLOR_CTL(pipe, plane_id),
268 PLANE_COLOR_PIPE_GAMMA_ENABLE |
269 PLANE_COLOR_PIPE_CSC_ENABLE |
270 PLANE_COLOR_PLANE_GAMMA_DISABLE);
Ville Syrjälä78587de2017-03-09 17:44:32 +0200271 }
272
273 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200274 I915_WRITE_FW(PLANE_KEYVAL(pipe, plane_id), key->min_value);
275 I915_WRITE_FW(PLANE_KEYMAX(pipe, plane_id), key->max_value);
276 I915_WRITE_FW(PLANE_KEYMSK(pipe, plane_id), key->channel_mask);
Ville Syrjälä78587de2017-03-09 17:44:32 +0200277 }
278
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200279 I915_WRITE_FW(PLANE_OFFSET(pipe, plane_id), (y << 16) | x);
280 I915_WRITE_FW(PLANE_STRIDE(pipe, plane_id), stride);
281 I915_WRITE_FW(PLANE_SIZE(pipe, plane_id), (src_h << 16) | src_w);
Ville Syrjälä2e2adb02017-08-01 09:58:13 -0700282 I915_WRITE_FW(PLANE_AUX_DIST(pipe, plane_id),
283 (plane_state->aux.offset - surf_addr) | aux_stride);
284 I915_WRITE_FW(PLANE_AUX_OFFSET(pipe, plane_id),
285 (plane_state->aux.y << 16) | plane_state->aux.x);
Chandra Konduruc3318792015-04-15 15:15:02 -0700286
287 /* program plane scaler */
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100288 if (plane_state->scaler_id >= 0) {
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100289 int scaler_id = plane_state->scaler_id;
Imre Deak7494bcd2016-05-12 16:18:49 +0300290 const struct intel_scaler *scaler;
Chandra Konduruc3318792015-04-15 15:15:02 -0700291
Imre Deak7494bcd2016-05-12 16:18:49 +0300292 scaler = &crtc_state->scaler_state.scalers[scaler_id];
293
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200294 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id),
295 PS_SCALER_EN | PS_PLANE_SEL(plane_id) | scaler->mode);
296 I915_WRITE_FW(SKL_PS_PWR_GATE(pipe, scaler_id), 0);
297 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y);
298 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id),
299 ((crtc_w + 1) << 16)|(crtc_h + 1));
Chandra Konduruc3318792015-04-15 15:15:02 -0700300
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200301 I915_WRITE_FW(PLANE_POS(pipe, plane_id), 0);
Chandra Konduruc3318792015-04-15 15:15:02 -0700302 } else {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200303 I915_WRITE_FW(PLANE_POS(pipe, plane_id), (crtc_y << 16) | crtc_x);
Chandra Konduruc3318792015-04-15 15:15:02 -0700304 }
305
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200306 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), plane_ctl);
307 I915_WRITE_FW(PLANE_SURF(pipe, plane_id),
308 intel_plane_ggtt_offset(plane_state) + surf_addr);
309 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
310
311 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000312}
313
314static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300315skl_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000316{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300317 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
318 enum plane_id plane_id = plane->id;
319 enum pipe pipe = plane->pipe;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200320 unsigned long irqflags;
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000321
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200322 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000323
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200324 I915_WRITE_FW(PLANE_CTL(pipe, plane_id), 0);
325
326 I915_WRITE_FW(PLANE_SURF(pipe, plane_id), 0);
327 POSTING_READ_FW(PLANE_SURF(pipe, plane_id));
328
329 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000330}
331
Damien Lespiaudc2a41b2013-12-04 00:49:41 +0000332static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300333chv_update_csc(struct intel_plane *plane, uint32_t format)
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300334{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300335 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
336 enum plane_id plane_id = plane->id;
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300337
338 /* Seems RGB data bypasses the CSC always */
339 if (!format_is_yuv(format))
340 return;
341
342 /*
343 * BT.601 limited range YCbCr -> full range RGB
344 *
345 * |r| | 6537 4769 0| |cr |
346 * |g| = |-3330 4769 -1605| x |y-64|
347 * |b| | 0 4769 8263| |cb |
348 *
349 * Cb and Cr apparently come in as signed already, so no
350 * need for any offset. For Y we need to remove the offset.
351 */
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200352 I915_WRITE_FW(SPCSCYGOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(-64));
353 I915_WRITE_FW(SPCSCCBOFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
354 I915_WRITE_FW(SPCSCCROFF(plane_id), SPCSC_OOFF(0) | SPCSC_IOFF(0));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300355
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200356 I915_WRITE_FW(SPCSCC01(plane_id), SPCSC_C1(4769) | SPCSC_C0(6537));
357 I915_WRITE_FW(SPCSCC23(plane_id), SPCSC_C1(-3330) | SPCSC_C0(0));
358 I915_WRITE_FW(SPCSCC45(plane_id), SPCSC_C1(-1605) | SPCSC_C0(4769));
359 I915_WRITE_FW(SPCSCC67(plane_id), SPCSC_C1(4769) | SPCSC_C0(0));
360 I915_WRITE_FW(SPCSCC8(plane_id), SPCSC_C0(8263));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300361
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200362 I915_WRITE_FW(SPCSCYGICLAMP(plane_id), SPCSC_IMAX(940) | SPCSC_IMIN(64));
363 I915_WRITE_FW(SPCSCCBICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
364 I915_WRITE_FW(SPCSCCRICLAMP(plane_id), SPCSC_IMAX(448) | SPCSC_IMIN(-448));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300365
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200366 I915_WRITE_FW(SPCSCYGOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
367 I915_WRITE_FW(SPCSCCBOCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
368 I915_WRITE_FW(SPCSCCROCLAMP(plane_id), SPCSC_OMAX(1023) | SPCSC_OMIN(0));
Ville Syrjälä6ca2aeb2014-10-20 19:47:53 +0300369}
370
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200371static u32 vlv_sprite_ctl(const struct intel_crtc_state *crtc_state,
372 const struct intel_plane_state *plane_state)
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700373{
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200374 const struct drm_framebuffer *fb = plane_state->base.fb;
Ville Syrjälä11df4d92016-11-07 22:20:55 +0200375 unsigned int rotation = plane_state->base.rotation;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100376 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200377 u32 sprctl;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700378
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200379 sprctl = SP_ENABLE | SP_GAMMA_ENABLE;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700380
Ville Syrjälä438b74a2016-12-14 23:32:55 +0200381 switch (fb->format->format) {
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700382 case DRM_FORMAT_YUYV:
383 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YUYV;
384 break;
385 case DRM_FORMAT_YVYU:
386 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_YVYU;
387 break;
388 case DRM_FORMAT_UYVY:
389 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_UYVY;
390 break;
391 case DRM_FORMAT_VYUY:
392 sprctl |= SP_FORMAT_YUV422 | SP_YUV_ORDER_VYUY;
393 break;
394 case DRM_FORMAT_RGB565:
395 sprctl |= SP_FORMAT_BGR565;
396 break;
397 case DRM_FORMAT_XRGB8888:
398 sprctl |= SP_FORMAT_BGRX8888;
399 break;
400 case DRM_FORMAT_ARGB8888:
401 sprctl |= SP_FORMAT_BGRA8888;
402 break;
403 case DRM_FORMAT_XBGR2101010:
404 sprctl |= SP_FORMAT_RGBX1010102;
405 break;
406 case DRM_FORMAT_ABGR2101010:
407 sprctl |= SP_FORMAT_RGBA1010102;
408 break;
409 case DRM_FORMAT_XBGR8888:
410 sprctl |= SP_FORMAT_RGBX8888;
411 break;
412 case DRM_FORMAT_ABGR8888:
413 sprctl |= SP_FORMAT_RGBA8888;
414 break;
415 default:
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200416 MISSING_CASE(fb->format->format);
417 return 0;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700418 }
419
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200420 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700421 sprctl |= SP_TILED;
422
Robert Fossc2c446a2017-05-19 16:50:17 -0400423 if (rotation & DRM_MODE_ROTATE_180)
Ville Syrjälädf0cd452016-11-14 18:53:59 +0200424 sprctl |= SP_ROTATE_180;
425
Robert Fossc2c446a2017-05-19 16:50:17 -0400426 if (rotation & DRM_MODE_REFLECT_X)
Ville Syrjälä4ea7be22016-11-14 18:54:00 +0200427 sprctl |= SP_MIRROR;
428
Ville Syrjälä78587de2017-03-09 17:44:32 +0200429 if (key->flags & I915_SET_COLORKEY_SOURCE)
430 sprctl |= SP_SOURCE_KEY;
431
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200432 return sprctl;
433}
434
435static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300436vlv_update_plane(struct intel_plane *plane,
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200437 const struct intel_crtc_state *crtc_state,
438 const struct intel_plane_state *plane_state)
439{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300440 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
441 const struct drm_framebuffer *fb = plane_state->base.fb;
442 enum pipe pipe = plane->pipe;
443 enum plane_id plane_id = plane->id;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200444 u32 sprctl = plane_state->ctl;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200445 u32 sprsurf_offset = plane_state->main.offset;
446 u32 linear_offset;
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200447 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
448 int crtc_x = plane_state->base.dst.x1;
449 int crtc_y = plane_state->base.dst.y1;
450 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
451 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200452 uint32_t x = plane_state->main.x;
453 uint32_t y = plane_state->main.y;
Ville Syrjälä96ef6852017-03-17 23:17:58 +0200454 unsigned long irqflags;
455
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700456 /* Sizes are 0 based */
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700457 crtc_w--;
458 crtc_h--;
459
Ville Syrjälä29490562016-01-20 18:02:50 +0200460 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +0300461
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200462 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
463
Ville Syrjälä78587de2017-03-09 17:44:32 +0200464 if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B)
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300465 chv_update_csc(plane, fb->format->format);
Ville Syrjälä78587de2017-03-09 17:44:32 +0200466
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200467 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200468 I915_WRITE_FW(SPKEYMINVAL(pipe, plane_id), key->min_value);
469 I915_WRITE_FW(SPKEYMAXVAL(pipe, plane_id), key->max_value);
470 I915_WRITE_FW(SPKEYMSK(pipe, plane_id), key->channel_mask);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200471 }
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200472 I915_WRITE_FW(SPSTRIDE(pipe, plane_id), fb->pitches[0]);
473 I915_WRITE_FW(SPPOS(pipe, plane_id), (crtc_y << 16) | crtc_x);
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200474
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200475 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200476 I915_WRITE_FW(SPTILEOFF(pipe, plane_id), (y << 16) | x);
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700477 else
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200478 I915_WRITE_FW(SPLINOFF(pipe, plane_id), linear_offset);
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700479
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200480 I915_WRITE_FW(SPCONSTALPHA(pipe, plane_id), 0);
Ville Syrjäläc14b0482014-10-16 20:52:34 +0300481
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200482 I915_WRITE_FW(SPSIZE(pipe, plane_id), (crtc_h << 16) | crtc_w);
483 I915_WRITE_FW(SPCNTR(pipe, plane_id), sprctl);
484 I915_WRITE_FW(SPSURF(pipe, plane_id),
485 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
486 POSTING_READ_FW(SPSURF(pipe, plane_id));
487
488 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700489}
490
491static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300492vlv_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700493{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300494 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
495 enum pipe pipe = plane->pipe;
496 enum plane_id plane_id = plane->id;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200497 unsigned long irqflags;
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700498
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200499 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200500
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200501 I915_WRITE_FW(SPCNTR(pipe, plane_id), 0);
502
503 I915_WRITE_FW(SPSURF(pipe, plane_id), 0);
504 POSTING_READ_FW(SPSURF(pipe, plane_id));
505
506 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700507}
508
Ville Syrjälä45dea7b2017-03-17 23:17:59 +0200509static u32 ivb_sprite_ctl(const struct intel_crtc_state *crtc_state,
510 const struct intel_plane_state *plane_state)
511{
512 struct drm_i915_private *dev_priv =
513 to_i915(plane_state->base.plane->dev);
514 const struct drm_framebuffer *fb = plane_state->base.fb;
515 unsigned int rotation = plane_state->base.rotation;
516 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
517 u32 sprctl;
518
519 sprctl = SPRITE_ENABLE | SPRITE_GAMMA_ENABLE;
520
521 if (IS_IVYBRIDGE(dev_priv))
522 sprctl |= SPRITE_TRICKLE_FEED_DISABLE;
523
524 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
525 sprctl |= SPRITE_PIPE_CSC_ENABLE;
526
527 switch (fb->format->format) {
528 case DRM_FORMAT_XBGR8888:
529 sprctl |= SPRITE_FORMAT_RGBX888 | SPRITE_RGB_ORDER_RGBX;
530 break;
531 case DRM_FORMAT_XRGB8888:
532 sprctl |= SPRITE_FORMAT_RGBX888;
533 break;
534 case DRM_FORMAT_YUYV:
535 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YUYV;
536 break;
537 case DRM_FORMAT_YVYU:
538 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_YVYU;
539 break;
540 case DRM_FORMAT_UYVY:
541 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_UYVY;
542 break;
543 case DRM_FORMAT_VYUY:
544 sprctl |= SPRITE_FORMAT_YUV422 | SPRITE_YUV_ORDER_VYUY;
545 break;
546 default:
547 MISSING_CASE(fb->format->format);
548 return 0;
549 }
550
551 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
552 sprctl |= SPRITE_TILED;
553
Robert Fossc2c446a2017-05-19 16:50:17 -0400554 if (rotation & DRM_MODE_ROTATE_180)
Ville Syrjälä45dea7b2017-03-17 23:17:59 +0200555 sprctl |= SPRITE_ROTATE_180;
556
557 if (key->flags & I915_SET_COLORKEY_DESTINATION)
558 sprctl |= SPRITE_DEST_KEY;
559 else if (key->flags & I915_SET_COLORKEY_SOURCE)
560 sprctl |= SPRITE_SOURCE_KEY;
561
562 return sprctl;
563}
564
Jesse Barnes7f1f3852013-04-02 11:22:20 -0700565static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300566ivb_update_plane(struct intel_plane *plane,
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100567 const struct intel_crtc_state *crtc_state,
568 const struct intel_plane_state *plane_state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800569{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300570 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
571 const struct drm_framebuffer *fb = plane_state->base.fb;
572 enum pipe pipe = plane->pipe;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200573 u32 sprctl = plane_state->ctl, sprscale = 0;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200574 u32 sprsurf_offset = plane_state->main.offset;
575 u32 linear_offset;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100576 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300577 int crtc_x = plane_state->base.dst.x1;
578 int crtc_y = plane_state->base.dst.y1;
579 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
580 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200581 uint32_t x = plane_state->main.x;
582 uint32_t y = plane_state->main.y;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300583 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
584 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200585 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800586
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800587 /* Sizes are 0 based */
588 src_w--;
589 src_h--;
590 crtc_w--;
591 crtc_h--;
592
Ville Syrjälä8553c182013-12-05 15:51:39 +0200593 if (crtc_w != src_w || crtc_h != src_h)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800594 sprscale = SPRITE_SCALE_ENABLE | (src_w << 16) | src_h;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800595
Ville Syrjälä29490562016-01-20 18:02:50 +0200596 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +0300597
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200598 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
599
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200600 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200601 I915_WRITE_FW(SPRKEYVAL(pipe), key->min_value);
602 I915_WRITE_FW(SPRKEYMAX(pipe), key->max_value);
603 I915_WRITE_FW(SPRKEYMSK(pipe), key->channel_mask);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200604 }
605
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200606 I915_WRITE_FW(SPRSTRIDE(pipe), fb->pitches[0]);
607 I915_WRITE_FW(SPRPOS(pipe), (crtc_y << 16) | crtc_x);
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200608
Damien Lespiau5a35e992012-10-26 18:20:12 +0100609 /* HSW consolidates SPRTILEOFF and SPRLINOFF into a single SPROFFSET
610 * register */
Tvrtko Ursulin86527442016-10-13 11:03:00 +0100611 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200612 I915_WRITE_FW(SPROFFSET(pipe), (y << 16) | x);
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200613 else if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200614 I915_WRITE_FW(SPRTILEOFF(pipe), (y << 16) | x);
Damien Lespiau5a35e992012-10-26 18:20:12 +0100615 else
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200616 I915_WRITE_FW(SPRLINOFF(pipe), linear_offset);
Damien Lespiauc54173a2012-10-26 18:20:11 +0100617
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200618 I915_WRITE_FW(SPRSIZE(pipe), (crtc_h << 16) | crtc_w);
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300619 if (plane->can_scale)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200620 I915_WRITE_FW(SPRSCALE(pipe), sprscale);
621 I915_WRITE_FW(SPRCTL(pipe), sprctl);
622 I915_WRITE_FW(SPRSURF(pipe),
623 intel_plane_ggtt_offset(plane_state) + sprsurf_offset);
624 POSTING_READ_FW(SPRSURF(pipe));
625
626 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800627}
628
629static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300630ivb_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800631{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300632 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
633 enum pipe pipe = plane->pipe;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200634 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800635
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200636 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
637
638 I915_WRITE_FW(SPRCTL(pipe), 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800639 /* Can't leave the scaler enabled... */
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300640 if (plane->can_scale)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200641 I915_WRITE_FW(SPRSCALE(pipe), 0);
Ville Syrjälä5b633d62014-04-29 13:35:47 +0300642
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200643 I915_WRITE_FW(SPRSURF(pipe), 0);
644 POSTING_READ_FW(SPRSURF(pipe));
645
646 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800647}
648
Ville Syrjäläab330812017-04-21 21:14:32 +0300649static u32 g4x_sprite_ctl(const struct intel_crtc_state *crtc_state,
Ville Syrjälä0a375142017-03-17 23:18:00 +0200650 const struct intel_plane_state *plane_state)
651{
652 struct drm_i915_private *dev_priv =
653 to_i915(plane_state->base.plane->dev);
654 const struct drm_framebuffer *fb = plane_state->base.fb;
655 unsigned int rotation = plane_state->base.rotation;
656 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
657 u32 dvscntr;
658
659 dvscntr = DVS_ENABLE | DVS_GAMMA_ENABLE;
660
661 if (IS_GEN6(dev_priv))
662 dvscntr |= DVS_TRICKLE_FEED_DISABLE;
663
664 switch (fb->format->format) {
665 case DRM_FORMAT_XBGR8888:
666 dvscntr |= DVS_FORMAT_RGBX888 | DVS_RGB_ORDER_XBGR;
667 break;
668 case DRM_FORMAT_XRGB8888:
669 dvscntr |= DVS_FORMAT_RGBX888;
670 break;
671 case DRM_FORMAT_YUYV:
672 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YUYV;
673 break;
674 case DRM_FORMAT_YVYU:
675 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_YVYU;
676 break;
677 case DRM_FORMAT_UYVY:
678 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_UYVY;
679 break;
680 case DRM_FORMAT_VYUY:
681 dvscntr |= DVS_FORMAT_YUV422 | DVS_YUV_ORDER_VYUY;
682 break;
683 default:
684 MISSING_CASE(fb->format->format);
685 return 0;
686 }
687
688 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
689 dvscntr |= DVS_TILED;
690
Robert Fossc2c446a2017-05-19 16:50:17 -0400691 if (rotation & DRM_MODE_ROTATE_180)
Ville Syrjälä0a375142017-03-17 23:18:00 +0200692 dvscntr |= DVS_ROTATE_180;
693
694 if (key->flags & I915_SET_COLORKEY_DESTINATION)
695 dvscntr |= DVS_DEST_KEY;
696 else if (key->flags & I915_SET_COLORKEY_SOURCE)
697 dvscntr |= DVS_SOURCE_KEY;
698
699 return dvscntr;
700}
701
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800702static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300703g4x_update_plane(struct intel_plane *plane,
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100704 const struct intel_crtc_state *crtc_state,
705 const struct intel_plane_state *plane_state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800706{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300707 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
708 const struct drm_framebuffer *fb = plane_state->base.fb;
709 enum pipe pipe = plane->pipe;
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200710 u32 dvscntr = plane_state->ctl, dvsscale = 0;
711 u32 dvssurf_offset = plane_state->main.offset;
712 u32 linear_offset;
Maarten Lankhorst2fde1392016-01-07 11:54:06 +0100713 const struct drm_intel_sprite_colorkey *key = &plane_state->ckey;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300714 int crtc_x = plane_state->base.dst.x1;
715 int crtc_y = plane_state->base.dst.y1;
716 uint32_t crtc_w = drm_rect_width(&plane_state->base.dst);
717 uint32_t crtc_h = drm_rect_height(&plane_state->base.dst);
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200718 uint32_t x = plane_state->main.x;
719 uint32_t y = plane_state->main.y;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300720 uint32_t src_w = drm_rect_width(&plane_state->base.src) >> 16;
721 uint32_t src_h = drm_rect_height(&plane_state->base.src) >> 16;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200722 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800723
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800724 /* Sizes are 0 based */
725 src_w--;
726 src_h--;
727 crtc_w--;
728 crtc_h--;
729
Ville Syrjälä8368f012013-12-05 15:51:31 +0200730 if (crtc_w != src_w || crtc_h != src_h)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800731 dvsscale = DVS_SCALE_ENABLE | (src_w << 16) | src_h;
732
Ville Syrjälä29490562016-01-20 18:02:50 +0200733 linear_offset = intel_fb_xy_to_linear(x, y, plane_state, 0);
Ville Syrjälä6687c902015-09-15 13:16:41 +0300734
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200735 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
736
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200737 if (key->flags) {
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200738 I915_WRITE_FW(DVSKEYVAL(pipe), key->min_value);
739 I915_WRITE_FW(DVSKEYMAX(pipe), key->max_value);
740 I915_WRITE_FW(DVSKEYMSK(pipe), key->channel_mask);
Ville Syrjälä47ecbb22015-03-19 21:18:57 +0200741 }
742
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200743 I915_WRITE_FW(DVSSTRIDE(pipe), fb->pitches[0]);
744 I915_WRITE_FW(DVSPOS(pipe), (crtc_y << 16) | crtc_x);
Ville Syrjäläca6ad022014-01-17 20:09:03 +0200745
Ville Syrjäläbae781b2016-11-16 13:33:16 +0200746 if (fb->modifier == I915_FORMAT_MOD_X_TILED)
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200747 I915_WRITE_FW(DVSTILEOFF(pipe), (y << 16) | x);
Damien Lespiau5a35e992012-10-26 18:20:12 +0100748 else
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200749 I915_WRITE_FW(DVSLINOFF(pipe), linear_offset);
Damien Lespiau5a35e992012-10-26 18:20:12 +0100750
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200751 I915_WRITE_FW(DVSSIZE(pipe), (crtc_h << 16) | crtc_w);
752 I915_WRITE_FW(DVSSCALE(pipe), dvsscale);
753 I915_WRITE_FW(DVSCNTR(pipe), dvscntr);
754 I915_WRITE_FW(DVSSURF(pipe),
755 intel_plane_ggtt_offset(plane_state) + dvssurf_offset);
756 POSTING_READ_FW(DVSSURF(pipe));
757
758 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800759}
760
761static void
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300762g4x_disable_plane(struct intel_plane *plane, struct intel_crtc *crtc)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800763{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300764 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
765 enum pipe pipe = plane->pipe;
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200766 unsigned long irqflags;
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800767
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200768 spin_lock_irqsave(&dev_priv->uncore.lock, irqflags);
769
770 I915_WRITE_FW(DVSCNTR(pipe), 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800771 /* Disable the scaler */
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200772 I915_WRITE_FW(DVSSCALE(pipe), 0);
Ville Syrjälä48fe4692015-03-19 17:57:13 +0200773
Ville Syrjälädd584fc2017-03-09 17:44:33 +0200774 I915_WRITE_FW(DVSSURF(pipe), 0);
775 POSTING_READ_FW(DVSSURF(pipe));
776
777 spin_unlock_irqrestore(&dev_priv->uncore.lock, irqflags);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800778}
779
Jesse Barnes8ea30862012-01-03 08:05:39 -0800780static int
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300781intel_check_sprite_plane(struct intel_plane *plane,
Maarten Lankhorst061e4b82015-06-15 12:33:46 +0200782 struct intel_crtc_state *crtc_state,
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300783 struct intel_plane_state *state)
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800784{
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300785 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
786 struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc);
Matt Roper2b875c22014-12-01 15:40:13 -0800787 struct drm_framebuffer *fb = state->base.fb;
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300788 int crtc_x, crtc_y;
789 unsigned int crtc_w, crtc_h;
790 uint32_t src_x, src_y, src_w, src_h;
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300791 struct drm_rect *src = &state->base.src;
792 struct drm_rect *dst = &state->base.dst;
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300793 const struct drm_rect *clip = &state->clip;
Ville Syrjälä17316932013-04-24 18:52:38 +0300794 int hscale, vscale;
795 int max_scale, min_scale;
Chandra Konduru225c2282015-05-18 16:18:44 -0700796 bool can_scale;
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200797 int ret;
Matt Ropercf4c7c12014-12-04 10:27:42 -0800798
Rob Clark1638d302016-11-05 11:08:08 -0400799 *src = drm_plane_state_src(&state->base);
800 *dst = drm_plane_state_dest(&state->base);
Ville Syrjäläf8856a42016-07-26 19:07:00 +0300801
Matt Ropercf4c7c12014-12-04 10:27:42 -0800802 if (!fb) {
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300803 state->base.visible = false;
Maarten Lankhorstda20eab2015-06-15 12:33:44 +0200804 return 0;
Matt Ropercf4c7c12014-12-04 10:27:42 -0800805 }
Jesse Barnes5e1bac22013-03-26 09:25:43 -0700806
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800807 /* Don't modify another pipe's plane */
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300808 if (plane->pipe != crtc->pipe) {
Ville Syrjälä17316932013-04-24 18:52:38 +0300809 DRM_DEBUG_KMS("Wrong plane <-> crtc mapping\n");
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800810 return -EINVAL;
Ville Syrjälä17316932013-04-24 18:52:38 +0300811 }
812
813 /* FIXME check all gen limits */
814 if (fb->width < 3 || fb->height < 3 || fb->pitches[0] > 16384) {
815 DRM_DEBUG_KMS("Unsuitable framebuffer for plane\n");
816 return -EINVAL;
817 }
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800818
Chandra Konduru225c2282015-05-18 16:18:44 -0700819 /* setup can_scale, min_scale, max_scale */
Tvrtko Ursulin55b8f2a2016-10-14 09:17:22 +0100820 if (INTEL_GEN(dev_priv) >= 9) {
Chandra Konduru225c2282015-05-18 16:18:44 -0700821 /* use scaler when colorkey is not required */
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200822 if (state->ckey.flags == I915_SET_COLORKEY_NONE) {
Chandra Konduru225c2282015-05-18 16:18:44 -0700823 can_scale = 1;
824 min_scale = 1;
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300825 max_scale = skl_max_scale(crtc, crtc_state);
Chandra Konduru225c2282015-05-18 16:18:44 -0700826 } else {
827 can_scale = 0;
828 min_scale = DRM_PLANE_HELPER_NO_SCALING;
829 max_scale = DRM_PLANE_HELPER_NO_SCALING;
830 }
831 } else {
Ville Syrjälä282dbf92017-03-27 21:55:33 +0300832 can_scale = plane->can_scale;
833 max_scale = plane->max_downscale << 16;
834 min_scale = plane->can_scale ? 1 : (1 << 16);
Chandra Konduru225c2282015-05-18 16:18:44 -0700835 }
836
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300837 /*
838 * FIXME the following code does a bunch of fuzzy adjustments to the
839 * coordinates and sizes. We probably need some way to decide whether
840 * more strict checking should be done instead.
841 */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300842 drm_rect_rotate(src, fb->width << 16, fb->height << 16,
Matt Roper8e7d6882015-01-21 16:35:41 -0800843 state->base.rotation);
Ville Syrjälä76eebda2014-08-05 11:26:52 +0530844
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300845 hscale = drm_rect_calc_hscale_relaxed(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300846 BUG_ON(hscale < 0);
Ville Syrjälä17316932013-04-24 18:52:38 +0300847
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300848 vscale = drm_rect_calc_vscale_relaxed(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300849 BUG_ON(vscale < 0);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800850
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300851 state->base.visible = drm_rect_clip_scaled(src, dst, clip, hscale, vscale);
Jesse Barnesb840d907f2011-12-13 13:19:38 -0800852
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300853 crtc_x = dst->x1;
854 crtc_y = dst->y1;
855 crtc_w = drm_rect_width(dst);
856 crtc_h = drm_rect_height(dst);
Damien Lespiau2d354c32012-10-22 18:19:27 +0100857
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300858 if (state->base.visible) {
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300859 /* check again in case clipping clamped the results */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300860 hscale = drm_rect_calc_hscale(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300861 if (hscale < 0) {
862 DRM_DEBUG_KMS("Horizontal scaling factor out of limits\n");
Ville Syrjäläc70f5772015-11-16 17:02:36 +0200863 drm_rect_debug_print("src: ", src, true);
864 drm_rect_debug_print("dst: ", dst, false);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300865
866 return hscale;
867 }
868
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300869 vscale = drm_rect_calc_vscale(src, dst, min_scale, max_scale);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300870 if (vscale < 0) {
871 DRM_DEBUG_KMS("Vertical scaling factor out of limits\n");
Ville Syrjäläc70f5772015-11-16 17:02:36 +0200872 drm_rect_debug_print("src: ", src, true);
873 drm_rect_debug_print("dst: ", dst, false);
Ville Syrjälä3c3686c2013-04-24 18:52:39 +0300874
875 return vscale;
876 }
877
Ville Syrjälä17316932013-04-24 18:52:38 +0300878 /* Make the source viewport size an exact multiple of the scaling factors. */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300879 drm_rect_adjust_size(src,
880 drm_rect_width(dst) * hscale - drm_rect_width(src),
881 drm_rect_height(dst) * vscale - drm_rect_height(src));
Ville Syrjälä17316932013-04-24 18:52:38 +0300882
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300883 drm_rect_rotate_inv(src, fb->width << 16, fb->height << 16,
Matt Roper8e7d6882015-01-21 16:35:41 -0800884 state->base.rotation);
Ville Syrjälä76eebda2014-08-05 11:26:52 +0530885
Ville Syrjälä17316932013-04-24 18:52:38 +0300886 /* sanity check to make sure the src viewport wasn't enlarged */
Matt Roperea2c67b2014-12-23 10:41:52 -0800887 WARN_ON(src->x1 < (int) state->base.src_x ||
888 src->y1 < (int) state->base.src_y ||
889 src->x2 > (int) state->base.src_x + state->base.src_w ||
890 src->y2 > (int) state->base.src_y + state->base.src_h);
Ville Syrjälä17316932013-04-24 18:52:38 +0300891
892 /*
893 * Hardware doesn't handle subpixel coordinates.
894 * Adjust to (macro)pixel boundary, but be careful not to
895 * increase the source viewport size, because that could
896 * push the downscaling factor out of bounds.
Ville Syrjälä17316932013-04-24 18:52:38 +0300897 */
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300898 src_x = src->x1 >> 16;
899 src_w = drm_rect_width(src) >> 16;
900 src_y = src->y1 >> 16;
901 src_h = drm_rect_height(src) >> 16;
Ville Syrjälä17316932013-04-24 18:52:38 +0300902
Ville Syrjälä438b74a2016-12-14 23:32:55 +0200903 if (format_is_yuv(fb->format->format)) {
Ville Syrjälä17316932013-04-24 18:52:38 +0300904 src_x &= ~1;
905 src_w &= ~1;
906
907 /*
908 * Must keep src and dst the
909 * same if we can't scale.
910 */
Chandra Konduru225c2282015-05-18 16:18:44 -0700911 if (!can_scale)
Ville Syrjälä17316932013-04-24 18:52:38 +0300912 crtc_w &= ~1;
913
914 if (crtc_w == 0)
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300915 state->base.visible = false;
Ville Syrjälä17316932013-04-24 18:52:38 +0300916 }
917 }
918
919 /* Check size restrictions when scaling */
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300920 if (state->base.visible && (src_w != crtc_w || src_h != crtc_h)) {
Ville Syrjälä17316932013-04-24 18:52:38 +0300921 unsigned int width_bytes;
Ville Syrjälä353c8592016-12-14 23:30:57 +0200922 int cpp = fb->format->cpp[0];
Ville Syrjälä17316932013-04-24 18:52:38 +0300923
Chandra Konduru225c2282015-05-18 16:18:44 -0700924 WARN_ON(!can_scale);
Ville Syrjälä17316932013-04-24 18:52:38 +0300925
926 /* FIXME interlacing min height is 6 */
927
928 if (crtc_w < 3 || crtc_h < 3)
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300929 state->base.visible = false;
Ville Syrjälä17316932013-04-24 18:52:38 +0300930
931 if (src_w < 3 || src_h < 3)
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300932 state->base.visible = false;
Ville Syrjälä17316932013-04-24 18:52:38 +0300933
Ville Syrjäläac484962016-01-20 21:05:26 +0200934 width_bytes = ((src_x * cpp) & 63) + src_w * cpp;
Ville Syrjälä17316932013-04-24 18:52:38 +0300935
Tvrtko Ursulin55b8f2a2016-10-14 09:17:22 +0100936 if (INTEL_GEN(dev_priv) < 9 && (src_w > 2048 || src_h > 2048 ||
Chandra Konduruc3318792015-04-15 15:15:02 -0700937 width_bytes > 4096 || fb->pitches[0] > 4096)) {
Ville Syrjälä17316932013-04-24 18:52:38 +0300938 DRM_DEBUG_KMS("Source dimensions exceed hardware limits\n");
939 return -EINVAL;
940 }
941 }
942
Ville Syrjälä936e71e2016-07-26 19:06:59 +0300943 if (state->base.visible) {
Chandra Konduru0a5ae1b2015-04-09 16:41:54 -0700944 src->x1 = src_x << 16;
945 src->x2 = (src_x + src_w) << 16;
946 src->y1 = src_y << 16;
947 src->y2 = (src_y + src_h) << 16;
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300948 }
949
950 dst->x1 = crtc_x;
951 dst->x2 = crtc_x + crtc_w;
952 dst->y1 = crtc_y;
953 dst->y2 = crtc_y + crtc_h;
954
Tvrtko Ursulin55b8f2a2016-10-14 09:17:22 +0100955 if (INTEL_GEN(dev_priv) >= 9) {
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200956 ret = skl_check_plane_surface(state);
957 if (ret)
958 return ret;
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200959
960 state->ctl = skl_plane_ctl(crtc_state, state);
961 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200962 ret = i9xx_check_plane_surface(state);
963 if (ret)
964 return ret;
965
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200966 state->ctl = vlv_sprite_ctl(crtc_state, state);
967 } else if (INTEL_GEN(dev_priv) >= 7) {
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200968 ret = i9xx_check_plane_surface(state);
969 if (ret)
970 return ret;
971
Ville Syrjäläa0864d52017-03-23 21:27:09 +0200972 state->ctl = ivb_sprite_ctl(crtc_state, state);
973 } else {
Ville Syrjäläf9407ae2017-03-23 21:27:12 +0200974 ret = i9xx_check_plane_surface(state);
975 if (ret)
976 return ret;
977
Ville Syrjäläab330812017-04-21 21:14:32 +0300978 state->ctl = g4x_sprite_ctl(crtc_state, state);
Ville Syrjäläb63a16f2016-01-28 16:53:54 +0200979 }
980
Gustavo Padovan96d61a72014-09-05 17:04:47 -0300981 return 0;
982}
983
Jesse Barnes8ea30862012-01-03 08:05:39 -0800984int intel_sprite_set_colorkey(struct drm_device *dev, void *data,
985 struct drm_file *file_priv)
986{
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +0100987 struct drm_i915_private *dev_priv = to_i915(dev);
Jesse Barnes8ea30862012-01-03 08:05:39 -0800988 struct drm_intel_sprite_colorkey *set = data;
Jesse Barnes8ea30862012-01-03 08:05:39 -0800989 struct drm_plane *plane;
Maarten Lankhorst818ed962015-06-15 12:33:54 +0200990 struct drm_plane_state *plane_state;
991 struct drm_atomic_state *state;
992 struct drm_modeset_acquire_ctx ctx;
Jesse Barnes8ea30862012-01-03 08:05:39 -0800993 int ret = 0;
994
Jesse Barnes8ea30862012-01-03 08:05:39 -0800995 /* Make sure we don't try to enable both src & dest simultaneously */
996 if ((set->flags & (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE)) == (I915_SET_COLORKEY_DESTINATION | I915_SET_COLORKEY_SOURCE))
997 return -EINVAL;
998
Tvrtko Ursulin920a14b2016-10-14 10:13:44 +0100999 if ((IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) &&
Ville Syrjälä47ecbb22015-03-19 21:18:57 +02001000 set->flags & I915_SET_COLORKEY_DESTINATION)
1001 return -EINVAL;
1002
Rob Clark7707e652014-07-17 23:30:04 -04001003 plane = drm_plane_find(dev, set->plane_id);
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001004 if (!plane || plane->type != DRM_PLANE_TYPE_OVERLAY)
1005 return -ENOENT;
1006
1007 drm_modeset_acquire_init(&ctx, 0);
1008
1009 state = drm_atomic_state_alloc(plane->dev);
1010 if (!state) {
1011 ret = -ENOMEM;
1012 goto out;
Jesse Barnes8ea30862012-01-03 08:05:39 -08001013 }
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001014 state->acquire_ctx = &ctx;
Jesse Barnes8ea30862012-01-03 08:05:39 -08001015
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001016 while (1) {
1017 plane_state = drm_atomic_get_plane_state(state, plane);
1018 ret = PTR_ERR_OR_ZERO(plane_state);
1019 if (!ret) {
1020 to_intel_plane_state(plane_state)->ckey = *set;
1021 ret = drm_atomic_commit(state);
Chandra Konduru6156a452015-04-27 13:48:39 -07001022 }
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001023
1024 if (ret != -EDEADLK)
1025 break;
1026
1027 drm_atomic_state_clear(state);
1028 drm_modeset_backoff(&ctx);
Chandra Konduru6156a452015-04-27 13:48:39 -07001029 }
1030
Chris Wilson08536952016-10-14 13:18:18 +01001031 drm_atomic_state_put(state);
Maarten Lankhorst818ed962015-06-15 12:33:54 +02001032out:
1033 drm_modeset_drop_locks(&ctx);
1034 drm_modeset_acquire_fini(&ctx);
Jesse Barnes8ea30862012-01-03 08:05:39 -08001035 return ret;
1036}
1037
Ville Syrjäläab330812017-04-21 21:14:32 +03001038static const uint32_t g4x_plane_formats[] = {
Chris Wilsond1686ae2012-04-10 11:41:49 +01001039 DRM_FORMAT_XRGB8888,
1040 DRM_FORMAT_YUYV,
1041 DRM_FORMAT_YVYU,
1042 DRM_FORMAT_UYVY,
1043 DRM_FORMAT_VYUY,
1044};
1045
Ben Widawsky714244e2017-08-01 09:58:16 -07001046static const uint64_t i9xx_plane_format_modifiers[] = {
1047 I915_FORMAT_MOD_X_TILED,
1048 DRM_FORMAT_MOD_LINEAR,
1049 DRM_FORMAT_MOD_INVALID
1050};
1051
Damien Lespiaudada2d52015-05-12 16:13:22 +01001052static const uint32_t snb_plane_formats[] = {
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001053 DRM_FORMAT_XBGR8888,
1054 DRM_FORMAT_XRGB8888,
1055 DRM_FORMAT_YUYV,
1056 DRM_FORMAT_YVYU,
1057 DRM_FORMAT_UYVY,
1058 DRM_FORMAT_VYUY,
1059};
1060
Damien Lespiaudada2d52015-05-12 16:13:22 +01001061static const uint32_t vlv_plane_formats[] = {
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001062 DRM_FORMAT_RGB565,
1063 DRM_FORMAT_ABGR8888,
1064 DRM_FORMAT_ARGB8888,
1065 DRM_FORMAT_XBGR8888,
1066 DRM_FORMAT_XRGB8888,
1067 DRM_FORMAT_XBGR2101010,
1068 DRM_FORMAT_ABGR2101010,
1069 DRM_FORMAT_YUYV,
1070 DRM_FORMAT_YVYU,
1071 DRM_FORMAT_UYVY,
1072 DRM_FORMAT_VYUY,
1073};
1074
Damien Lespiaudc2a41b2013-12-04 00:49:41 +00001075static uint32_t skl_plane_formats[] = {
1076 DRM_FORMAT_RGB565,
1077 DRM_FORMAT_ABGR8888,
1078 DRM_FORMAT_ARGB8888,
1079 DRM_FORMAT_XBGR8888,
1080 DRM_FORMAT_XRGB8888,
1081 DRM_FORMAT_YUYV,
1082 DRM_FORMAT_YVYU,
1083 DRM_FORMAT_UYVY,
1084 DRM_FORMAT_VYUY,
1085};
1086
Ben Widawsky714244e2017-08-01 09:58:16 -07001087static const uint64_t skl_plane_format_modifiers[] = {
1088 I915_FORMAT_MOD_X_TILED,
1089 DRM_FORMAT_MOD_LINEAR,
1090 DRM_FORMAT_MOD_INVALID
1091};
1092
1093static bool g4x_sprite_plane_format_mod_supported(struct drm_plane *plane,
1094 uint32_t format,
1095 uint64_t modifier)
1096{
1097 switch (format) {
1098 case DRM_FORMAT_XBGR8888:
1099 case DRM_FORMAT_XRGB8888:
1100 case DRM_FORMAT_YUYV:
1101 case DRM_FORMAT_YVYU:
1102 case DRM_FORMAT_UYVY:
1103 case DRM_FORMAT_VYUY:
1104 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1105 modifier == I915_FORMAT_MOD_X_TILED)
1106 return true;
1107 /* fall through */
1108 default:
1109 return false;
1110 }
1111}
1112
1113static bool vlv_sprite_plane_format_mod_supported(struct drm_plane *plane,
1114 uint32_t format,
1115 uint64_t modifier)
1116{
1117 switch (format) {
1118 case DRM_FORMAT_YUYV:
1119 case DRM_FORMAT_YVYU:
1120 case DRM_FORMAT_UYVY:
1121 case DRM_FORMAT_VYUY:
1122 case DRM_FORMAT_RGB565:
1123 case DRM_FORMAT_XRGB8888:
1124 case DRM_FORMAT_ARGB8888:
1125 case DRM_FORMAT_XBGR2101010:
1126 case DRM_FORMAT_ABGR2101010:
1127 case DRM_FORMAT_XBGR8888:
1128 case DRM_FORMAT_ABGR8888:
1129 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1130 modifier == I915_FORMAT_MOD_X_TILED)
1131 return true;
1132 /* fall through */
1133 default:
1134 return false;
1135 }
1136}
1137
1138static bool skl_sprite_plane_format_mod_supported(struct drm_plane *plane,
1139 uint32_t format,
1140 uint64_t modifier)
1141{
1142 /* This is the same as primary plane since SKL has universal planes */
1143 switch (format) {
1144 case DRM_FORMAT_XRGB8888:
1145 case DRM_FORMAT_XBGR8888:
1146 case DRM_FORMAT_ARGB8888:
1147 case DRM_FORMAT_ABGR8888:
1148 case DRM_FORMAT_RGB565:
1149 case DRM_FORMAT_XRGB2101010:
1150 case DRM_FORMAT_XBGR2101010:
1151 case DRM_FORMAT_YUYV:
1152 case DRM_FORMAT_YVYU:
1153 case DRM_FORMAT_UYVY:
1154 case DRM_FORMAT_VYUY:
1155 if (modifier == I915_FORMAT_MOD_Yf_TILED)
1156 return true;
1157 /* fall through */
1158 case DRM_FORMAT_C8:
1159 if (modifier == DRM_FORMAT_MOD_LINEAR ||
1160 modifier == I915_FORMAT_MOD_X_TILED ||
1161 modifier == I915_FORMAT_MOD_Y_TILED)
1162 return true;
1163 /* fall through */
1164 default:
1165 return false;
1166 }
1167}
1168
1169static bool intel_sprite_plane_format_mod_supported(struct drm_plane *plane,
1170 uint32_t format,
1171 uint64_t modifier)
1172{
1173 struct drm_i915_private *dev_priv = to_i915(plane->dev);
1174
1175 if (WARN_ON(modifier == DRM_FORMAT_MOD_INVALID))
1176 return false;
1177
1178 if ((modifier >> 56) != DRM_FORMAT_MOD_VENDOR_INTEL &&
1179 modifier != DRM_FORMAT_MOD_LINEAR)
1180 return false;
1181
1182 if (INTEL_GEN(dev_priv) >= 9)
1183 return skl_sprite_plane_format_mod_supported(plane, format, modifier);
1184 else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
1185 return vlv_sprite_plane_format_mod_supported(plane, format, modifier);
1186 else
1187 return g4x_sprite_plane_format_mod_supported(plane, format, modifier);
1188
1189 unreachable();
1190}
1191
Colin Ian King2d567582017-08-11 14:49:38 +01001192static const struct drm_plane_funcs intel_sprite_plane_funcs = {
Ben Widawsky714244e2017-08-01 09:58:16 -07001193 .update_plane = drm_atomic_helper_update_plane,
1194 .disable_plane = drm_atomic_helper_disable_plane,
1195 .destroy = intel_plane_destroy,
1196 .atomic_get_property = intel_plane_atomic_get_property,
1197 .atomic_set_property = intel_plane_atomic_set_property,
1198 .atomic_duplicate_state = intel_plane_duplicate_state,
1199 .atomic_destroy_state = intel_plane_destroy_state,
1200 .format_mod_supported = intel_sprite_plane_format_mod_supported,
1201};
1202
Ville Syrjäläb079bd172016-10-25 18:58:02 +03001203struct intel_plane *
Ville Syrjälä580503c2016-10-31 22:37:00 +02001204intel_sprite_plane_create(struct drm_i915_private *dev_priv,
1205 enum pipe pipe, int plane)
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001206{
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001207 struct intel_plane *intel_plane = NULL;
1208 struct intel_plane_state *state = NULL;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001209 unsigned long possible_crtcs;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001210 const uint32_t *plane_formats;
Ben Widawsky714244e2017-08-01 09:58:16 -07001211 const uint64_t *modifiers;
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001212 unsigned int supported_rotations;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001213 int num_plane_formats;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001214 int ret;
1215
Daniel Vetterb14c5672013-09-19 12:18:32 +02001216 intel_plane = kzalloc(sizeof(*intel_plane), GFP_KERNEL);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001217 if (!intel_plane) {
1218 ret = -ENOMEM;
1219 goto fail;
1220 }
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001221
Matt Roper8e7d6882015-01-21 16:35:41 -08001222 state = intel_create_plane_state(&intel_plane->base);
1223 if (!state) {
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001224 ret = -ENOMEM;
1225 goto fail;
Matt Roperea2c67b2014-12-23 10:41:52 -08001226 }
Matt Roper8e7d6882015-01-21 16:35:41 -08001227 intel_plane->base.state = &state->base;
Matt Roperea2c67b2014-12-23 10:41:52 -08001228
Ben Widawsky714244e2017-08-01 09:58:16 -07001229 if (INTEL_GEN(dev_priv) >= 10) {
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001230 intel_plane->can_scale = true;
1231 state->scaler_id = -1;
1232
1233 intel_plane->update_plane = skl_update_plane;
1234 intel_plane->disable_plane = skl_disable_plane;
1235
1236 plane_formats = skl_plane_formats;
1237 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
Ben Widawsky714244e2017-08-01 09:58:16 -07001238 modifiers = skl_plane_format_modifiers;
1239 } else if (INTEL_GEN(dev_priv) >= 9) {
1240 intel_plane->can_scale = true;
1241 state->scaler_id = -1;
1242
1243 intel_plane->update_plane = skl_update_plane;
1244 intel_plane->disable_plane = skl_disable_plane;
1245
1246 plane_formats = skl_plane_formats;
1247 num_plane_formats = ARRAY_SIZE(skl_plane_formats);
1248 modifiers = skl_plane_format_modifiers;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001249 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
1250 intel_plane->can_scale = false;
1251 intel_plane->max_downscale = 1;
1252
1253 intel_plane->update_plane = vlv_update_plane;
1254 intel_plane->disable_plane = vlv_disable_plane;
1255
1256 plane_formats = vlv_plane_formats;
1257 num_plane_formats = ARRAY_SIZE(vlv_plane_formats);
Ben Widawsky714244e2017-08-01 09:58:16 -07001258 modifiers = i9xx_plane_format_modifiers;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001259 } else if (INTEL_GEN(dev_priv) >= 7) {
1260 if (IS_IVYBRIDGE(dev_priv)) {
1261 intel_plane->can_scale = true;
1262 intel_plane->max_downscale = 2;
1263 } else {
1264 intel_plane->can_scale = false;
1265 intel_plane->max_downscale = 1;
1266 }
1267
1268 intel_plane->update_plane = ivb_update_plane;
1269 intel_plane->disable_plane = ivb_disable_plane;
1270
1271 plane_formats = snb_plane_formats;
1272 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
Ben Widawsky714244e2017-08-01 09:58:16 -07001273 modifiers = i9xx_plane_format_modifiers;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001274 } else {
Damien Lespiau2d354c32012-10-22 18:19:27 +01001275 intel_plane->can_scale = true;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001276 intel_plane->max_downscale = 16;
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001277
Ville Syrjäläab330812017-04-21 21:14:32 +03001278 intel_plane->update_plane = g4x_update_plane;
1279 intel_plane->disable_plane = g4x_disable_plane;
Chris Wilsond1686ae2012-04-10 11:41:49 +01001280
Ben Widawsky714244e2017-08-01 09:58:16 -07001281 modifiers = i9xx_plane_format_modifiers;
Tvrtko Ursulin5db94012016-10-13 11:03:10 +01001282 if (IS_GEN6(dev_priv)) {
Chris Wilsond1686ae2012-04-10 11:41:49 +01001283 plane_formats = snb_plane_formats;
1284 num_plane_formats = ARRAY_SIZE(snb_plane_formats);
1285 } else {
Ville Syrjäläab330812017-04-21 21:14:32 +03001286 plane_formats = g4x_plane_formats;
1287 num_plane_formats = ARRAY_SIZE(g4x_plane_formats);
Chris Wilsond1686ae2012-04-10 11:41:49 +01001288 }
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001289 }
1290
Dave Airlie5481e272016-10-25 16:36:13 +10001291 if (INTEL_GEN(dev_priv) >= 9) {
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001292 supported_rotations =
Robert Fossc2c446a2017-05-19 16:50:17 -04001293 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_90 |
1294 DRM_MODE_ROTATE_180 | DRM_MODE_ROTATE_270;
Ville Syrjälä4ea7be22016-11-14 18:54:00 +02001295 } else if (IS_CHERRYVIEW(dev_priv) && pipe == PIPE_B) {
1296 supported_rotations =
Robert Fossc2c446a2017-05-19 16:50:17 -04001297 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180 |
1298 DRM_MODE_REFLECT_X;
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001299 } else {
1300 supported_rotations =
Robert Fossc2c446a2017-05-19 16:50:17 -04001301 DRM_MODE_ROTATE_0 | DRM_MODE_ROTATE_180;
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001302 }
1303
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001304 intel_plane->pipe = pipe;
Jesse Barnes7f1f3852013-04-02 11:22:20 -07001305 intel_plane->plane = plane;
Ville Syrjäläb14e5842016-11-22 18:01:56 +02001306 intel_plane->id = PLANE_SPRITE0 + plane;
Sagar Arun Kambled1b9d032015-09-14 21:35:42 +05301307 intel_plane->frontbuffer_bit = INTEL_FRONTBUFFER_SPRITE(pipe, plane);
Matt Roperc59cb172014-12-01 15:40:16 -08001308 intel_plane->check_plane = intel_check_sprite_plane;
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001309
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001310 possible_crtcs = (1 << pipe);
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001311
Ville Syrjälä1890ae62016-10-25 18:58:03 +03001312 if (INTEL_GEN(dev_priv) >= 9)
Ville Syrjälä580503c2016-10-31 22:37:00 +02001313 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
Ben Widawsky714244e2017-08-01 09:58:16 -07001314 possible_crtcs, &intel_sprite_plane_funcs,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001315 plane_formats, num_plane_formats,
Ben Widawsky714244e2017-08-01 09:58:16 -07001316 modifiers,
1317 DRM_PLANE_TYPE_OVERLAY,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001318 "plane %d%c", plane + 2, pipe_name(pipe));
1319 else
Ville Syrjälä580503c2016-10-31 22:37:00 +02001320 ret = drm_universal_plane_init(&dev_priv->drm, &intel_plane->base,
Ben Widawsky714244e2017-08-01 09:58:16 -07001321 possible_crtcs, &intel_sprite_plane_funcs,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001322 plane_formats, num_plane_formats,
Ben Widawsky714244e2017-08-01 09:58:16 -07001323 modifiers,
1324 DRM_PLANE_TYPE_OVERLAY,
Ville Syrjälä38573dc2016-05-27 20:59:23 +03001325 "sprite %c", sprite_name(pipe, plane));
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001326 if (ret)
1327 goto fail;
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001328
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001329 drm_plane_create_rotation_property(&intel_plane->base,
Robert Fossc2c446a2017-05-19 16:50:17 -04001330 DRM_MODE_ROTATE_0,
Ville Syrjälä93ca7e02016-09-26 19:30:56 +03001331 supported_rotations);
Ville Syrjälä7ed6eee2014-08-05 11:26:55 +05301332
Matt Roperea2c67b2014-12-23 10:41:52 -08001333 drm_plane_helper_add(&intel_plane->base, &intel_plane_helper_funcs);
1334
Ville Syrjäläb079bd172016-10-25 18:58:02 +03001335 return intel_plane;
Ville Syrjäläfca0ce22016-03-21 14:43:22 +00001336
1337fail:
1338 kfree(state);
1339 kfree(intel_plane);
1340
Ville Syrjäläb079bd172016-10-25 18:58:02 +03001341 return ERR_PTR(ret);
Jesse Barnesb840d907f2011-12-13 13:19:38 -08001342}