Gitiles
Code Review Sign In
gerrit-public.fairphone.software / kernel / msm-5.4 / 8edb254c8c08dc2e6cb60e30da00a49f8b102c43 / . / drivers / net / wireless / ath / ath9k / ar9003_eeprom.c
blob: 1188db205e32d0c7b1d7c102b8dce9339f0d62b0 [file] [log] [blame]
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]1/*
Sujith Manoharan5b681382011-05-17 13:36:18 +0530[diff] [blame]2 * Copyright (c) 2010-2011 Atheros Communications Inc.
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3 *
4 * Permission to use, copy, modify, and/or distribute this software for any
5 * purpose with or without fee is hereby granted, provided that the above
6 * copyright notice and this permission notice appear in all copies.
7 *
8 * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES
9 * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF
10 * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR
11 * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES
12 * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN
13 * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF
14 * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.
15 */
16
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]17#include <asm/unaligned.h>
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]18#include "hw.h"
19#include "ar9003_phy.h"
20#include "ar9003_eeprom.h"
21
22#define COMP_HDR_LEN 4
23#define COMP_CKSUM_LEN 2
24
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]25#define LE16(x) __constant_cpu_to_le16(x)
26#define LE32(x) __constant_cpu_to_le32(x)
27
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]28/* Local defines to distinguish between extension and control CTL's */
29#define EXT_ADDITIVE (0x8000)
30#define CTL_11A_EXT (CTL_11A | EXT_ADDITIVE)
31#define CTL_11G_EXT (CTL_11G | EXT_ADDITIVE)
32#define CTL_11B_EXT (CTL_11B | EXT_ADDITIVE)
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]33
34#define SUB_NUM_CTL_MODES_AT_5G_40 2 /* excluding HT40, EXT-OFDM */
35#define SUB_NUM_CTL_MODES_AT_2G_40 3 /* excluding HT40, EXT-OFDM, EXT-CCK */
36
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]37#define CTL(_tpower, _flag) ((_tpower) | ((_flag) << 6))
38
Vasanthakumar Thiagarajand0ce2d12010-12-21 01:42:43 -0800[diff] [blame]39#define EEPROM_DATA_LEN_9485 1088
40
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]41static int ar9003_hw_power_interpolate(int32_t x,
42 int32_t *px, int32_t *py, u_int16_t np);
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]43
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]44
45static const struct ar9300_eeprom ar9300_default = {
46 .eepromVersion = 2,
47 .templateVersion = 2,
Senthil Balasubramanianb503c7a2011-08-19 18:43:06 +0530[diff] [blame]48 .macAddr = {0, 2, 3, 4, 5, 6},
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]49 .custData = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0,
50 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
51 .baseEepHeader = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]52 .regDmn = { LE16(0), LE16(0x1f) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]53 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
54 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]55 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]56 .eepMisc = 0,
57 },
58 .rfSilent = 0,
59 .blueToothOptions = 0,
60 .deviceCap = 0,
61 .deviceType = 5, /* takes lower byte in eeprom location */
62 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
63 .params_for_tuning_caps = {0, 0},
64 .featureEnable = 0x0c,
65 /*
66 * bit0 - enable tx temp comp - disabled
67 * bit1 - enable tx volt comp - disabled
68 * bit2 - enable fastClock - enabled
69 * bit3 - enable doubling - enabled
70 * bit4 - enable internal regulator - disabled
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]71 * bit5 - enable pa predistortion - disabled
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]72 */
73 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
74 .eepromWriteEnableGpio = 3,
75 .wlanDisableGpio = 0,
76 .wlanLedGpio = 8,
77 .rxBandSelectGpio = 0xff,
78 .txrxgain = 0,
79 .swreg = 0,
80 },
81 .modalHeader2G = {
82 /* ar9300_modal_eep_header 2g */
83 /* 4 idle,t1,t2,b(4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]84 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]85 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]86 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]87
88 /*
89 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
90 * rx1, rx12, b (2 bits each)
91 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]92 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]93
94 /*
95 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
96 * for ar9280 (0xa20c/b20c 5:0)
97 */
98 .xatten1DB = {0, 0, 0},
99
100 /*
101 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
102 * for ar9280 (0xa20c/b20c 16:12
103 */
104 .xatten1Margin = {0, 0, 0},
105 .tempSlope = 36,
106 .voltSlope = 0,
107
108 /*
109 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
110 * channels in usual fbin coding format
111 */
112 .spurChans = {0, 0, 0, 0, 0},
113
114 /*
115 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
116 * if the register is per chain
117 */
118 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]119 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
120 .quick_drop = 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]121 .xpaBiasLvl = 0,
122 .txFrameToDataStart = 0x0e,
123 .txFrameToPaOn = 0x0e,
124 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
125 .antennaGain = 0,
126 .switchSettling = 0x2c,
127 .adcDesiredSize = -30,
128 .txEndToXpaOff = 0,
129 .txEndToRxOn = 0x2,
130 .txFrameToXpaOn = 0xe,
131 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]132 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
133 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]134 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]135 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]136 },
137 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]138 .base_ext1 = {
139 .ant_div_control = 0,
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]140 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]141 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]142 .calFreqPier2G = {
143 FREQ2FBIN(2412, 1),
144 FREQ2FBIN(2437, 1),
145 FREQ2FBIN(2472, 1),
146 },
147 /* ar9300_cal_data_per_freq_op_loop 2g */
148 .calPierData2G = {
149 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
150 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
151 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
152 },
153 .calTarget_freqbin_Cck = {
154 FREQ2FBIN(2412, 1),
155 FREQ2FBIN(2484, 1),
156 },
157 .calTarget_freqbin_2G = {
158 FREQ2FBIN(2412, 1),
159 FREQ2FBIN(2437, 1),
160 FREQ2FBIN(2472, 1)
161 },
162 .calTarget_freqbin_2GHT20 = {
163 FREQ2FBIN(2412, 1),
164 FREQ2FBIN(2437, 1),
165 FREQ2FBIN(2472, 1)
166 },
167 .calTarget_freqbin_2GHT40 = {
168 FREQ2FBIN(2412, 1),
169 FREQ2FBIN(2437, 1),
170 FREQ2FBIN(2472, 1)
171 },
172 .calTargetPowerCck = {
173 /* 1L-5L,5S,11L,11S */
174 { {36, 36, 36, 36} },
175 { {36, 36, 36, 36} },
176 },
177 .calTargetPower2G = {
178 /* 6-24,36,48,54 */
179 { {32, 32, 28, 24} },
180 { {32, 32, 28, 24} },
181 { {32, 32, 28, 24} },
182 },
183 .calTargetPower2GHT20 = {
184 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
185 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
186 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
187 },
188 .calTargetPower2GHT40 = {
189 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
190 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
191 { {32, 32, 32, 32, 28, 20, 32, 32, 28, 20, 32, 32, 28, 20} },
192 },
193 .ctlIndex_2G = {
194 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
195 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
196 },
197 .ctl_freqbin_2G = {
198 {
199 FREQ2FBIN(2412, 1),
200 FREQ2FBIN(2417, 1),
201 FREQ2FBIN(2457, 1),
202 FREQ2FBIN(2462, 1)
203 },
204 {
205 FREQ2FBIN(2412, 1),
206 FREQ2FBIN(2417, 1),
207 FREQ2FBIN(2462, 1),
208 0xFF,
209 },
210
211 {
212 FREQ2FBIN(2412, 1),
213 FREQ2FBIN(2417, 1),
214 FREQ2FBIN(2462, 1),
215 0xFF,
216 },
217 {
218 FREQ2FBIN(2422, 1),
219 FREQ2FBIN(2427, 1),
220 FREQ2FBIN(2447, 1),
221 FREQ2FBIN(2452, 1)
222 },
223
224 {
225 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
226 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
227 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
228 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
229 },
230
231 {
232 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
233 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
234 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
235 0,
236 },
237
238 {
239 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
240 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
241 FREQ2FBIN(2472, 1),
242 0,
243 },
244
245 {
246 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
247 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
248 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
249 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
250 },
251
252 {
253 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
254 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
255 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
256 },
257
258 {
259 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
260 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
261 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
262 0
263 },
264
265 {
266 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
267 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
268 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
269 0
270 },
271
272 {
273 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
274 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
275 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]276 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]277 }
278 },
279 .ctlPowerData_2G = {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]280 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
281 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
282 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]283
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]284 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]285 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
286 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]287
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]288 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
289 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
290 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]291
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]292 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
293 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
294 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]295 },
296 .modalHeader5G = {
297 /* 4 idle,t1,t2,b (4 bits per setting) */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]298 .antCtrlCommon = LE32(0x110),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]299 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]300 .antCtrlCommon2 = LE32(0x22222),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]301 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
302 .antCtrlChain = {
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]303 LE16(0x000), LE16(0x000), LE16(0x000),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]304 },
305 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
306 .xatten1DB = {0, 0, 0},
307
308 /*
309 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
310 * for merlin (0xa20c/b20c 16:12
311 */
312 .xatten1Margin = {0, 0, 0},
313 .tempSlope = 68,
314 .voltSlope = 0,
315 /* spurChans spur channels in usual fbin coding format */
316 .spurChans = {0, 0, 0, 0, 0},
317 /* noiseFloorThreshCh Check if the register is per chain */
318 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]319 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
320 .quick_drop = 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]321 .xpaBiasLvl = 0,
322 .txFrameToDataStart = 0x0e,
323 .txFrameToPaOn = 0x0e,
324 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
325 .antennaGain = 0,
326 .switchSettling = 0x2d,
327 .adcDesiredSize = -30,
328 .txEndToXpaOff = 0,
329 .txEndToRxOn = 0x2,
330 .txFrameToXpaOn = 0xe,
331 .thresh62 = 28,
Senthil Balasubramanian3ceb8012010-11-10 05:03:09 -0800[diff] [blame]332 .papdRateMaskHt20 = LE32(0x0c80c080),
333 .papdRateMaskHt40 = LE32(0x0080c080),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]334 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]335 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]336 },
337 },
Senthil Balasubramanianb3dd6bc2010-11-10 05:03:07 -0800[diff] [blame]338 .base_ext2 = {
339 .tempSlopeLow = 0,
340 .tempSlopeHigh = 0,
341 .xatten1DBLow = {0, 0, 0},
342 .xatten1MarginLow = {0, 0, 0},
343 .xatten1DBHigh = {0, 0, 0},
344 .xatten1MarginHigh = {0, 0, 0}
345 },
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]346 .calFreqPier5G = {
347 FREQ2FBIN(5180, 0),
348 FREQ2FBIN(5220, 0),
349 FREQ2FBIN(5320, 0),
350 FREQ2FBIN(5400, 0),
351 FREQ2FBIN(5500, 0),
352 FREQ2FBIN(5600, 0),
353 FREQ2FBIN(5725, 0),
354 FREQ2FBIN(5825, 0)
355 },
356 .calPierData5G = {
357 {
358 {0, 0, 0, 0, 0},
359 {0, 0, 0, 0, 0},
360 {0, 0, 0, 0, 0},
361 {0, 0, 0, 0, 0},
362 {0, 0, 0, 0, 0},
363 {0, 0, 0, 0, 0},
364 {0, 0, 0, 0, 0},
365 {0, 0, 0, 0, 0},
366 },
367 {
368 {0, 0, 0, 0, 0},
369 {0, 0, 0, 0, 0},
370 {0, 0, 0, 0, 0},
371 {0, 0, 0, 0, 0},
372 {0, 0, 0, 0, 0},
373 {0, 0, 0, 0, 0},
374 {0, 0, 0, 0, 0},
375 {0, 0, 0, 0, 0},
376 },
377 {
378 {0, 0, 0, 0, 0},
379 {0, 0, 0, 0, 0},
380 {0, 0, 0, 0, 0},
381 {0, 0, 0, 0, 0},
382 {0, 0, 0, 0, 0},
383 {0, 0, 0, 0, 0},
384 {0, 0, 0, 0, 0},
385 {0, 0, 0, 0, 0},
386 },
387
388 },
389 .calTarget_freqbin_5G = {
390 FREQ2FBIN(5180, 0),
391 FREQ2FBIN(5220, 0),
392 FREQ2FBIN(5320, 0),
393 FREQ2FBIN(5400, 0),
394 FREQ2FBIN(5500, 0),
395 FREQ2FBIN(5600, 0),
396 FREQ2FBIN(5725, 0),
397 FREQ2FBIN(5825, 0)
398 },
399 .calTarget_freqbin_5GHT20 = {
400 FREQ2FBIN(5180, 0),
401 FREQ2FBIN(5240, 0),
402 FREQ2FBIN(5320, 0),
403 FREQ2FBIN(5500, 0),
404 FREQ2FBIN(5700, 0),
405 FREQ2FBIN(5745, 0),
406 FREQ2FBIN(5725, 0),
407 FREQ2FBIN(5825, 0)
408 },
409 .calTarget_freqbin_5GHT40 = {
410 FREQ2FBIN(5180, 0),
411 FREQ2FBIN(5240, 0),
412 FREQ2FBIN(5320, 0),
413 FREQ2FBIN(5500, 0),
414 FREQ2FBIN(5700, 0),
415 FREQ2FBIN(5745, 0),
416 FREQ2FBIN(5725, 0),
417 FREQ2FBIN(5825, 0)
418 },
419 .calTargetPower5G = {
420 /* 6-24,36,48,54 */
421 { {20, 20, 20, 10} },
422 { {20, 20, 20, 10} },
423 { {20, 20, 20, 10} },
424 { {20, 20, 20, 10} },
425 { {20, 20, 20, 10} },
426 { {20, 20, 20, 10} },
427 { {20, 20, 20, 10} },
428 { {20, 20, 20, 10} },
429 },
430 .calTargetPower5GHT20 = {
431 /*
432 * 0_8_16,1-3_9-11_17-19,
433 * 4,5,6,7,12,13,14,15,20,21,22,23
434 */
435 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
436 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
437 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
438 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
439 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
440 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
441 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
442 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
443 },
444 .calTargetPower5GHT40 = {
445 /*
446 * 0_8_16,1-3_9-11_17-19,
447 * 4,5,6,7,12,13,14,15,20,21,22,23
448 */
449 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
450 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
451 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
452 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
453 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
454 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
455 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
456 { {20, 20, 10, 10, 0, 0, 10, 10, 0, 0, 10, 10, 0, 0} },
457 },
458 .ctlIndex_5G = {
459 0x10, 0x16, 0x18, 0x40, 0x46,
460 0x48, 0x30, 0x36, 0x38
461 },
462 .ctl_freqbin_5G = {
463 {
464 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
465 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
466 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
467 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
468 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
469 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
470 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
471 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
472 },
473 {
474 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
475 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
476 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
477 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
478 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
479 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
480 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
481 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
482 },
483
484 {
485 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
486 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
487 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
488 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
489 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
490 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
491 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
492 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
493 },
494
495 {
496 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
497 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
498 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
499 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
500 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
501 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
502 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
503 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
504 },
505
506 {
507 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
508 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
509 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
510 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
511 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
512 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
513 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
514 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
515 },
516
517 {
518 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
519 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
520 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
521 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
522 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
523 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
524 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
525 /* Data[5].ctlEdges[7].bChannel */ 0xFF
526 },
527
528 {
529 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
530 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
531 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
532 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
533 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
534 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
535 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
536 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
537 },
538
539 {
540 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
541 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
542 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
543 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
544 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
545 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
546 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
547 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
548 },
549
550 {
551 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
552 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
553 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
554 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
555 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
556 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
557 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
558 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
559 }
560 },
561 .ctlPowerData_5G = {
562 {
563 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]564 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
565 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]566 }
567 },
568 {
569 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]570 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
571 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]572 }
573 },
574 {
575 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]576 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
577 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]578 }
579 },
580 {
581 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]582 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
583 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]584 }
585 },
586 {
587 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]588 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
589 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]590 }
591 },
592 {
593 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]594 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
595 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]596 }
597 },
598 {
599 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]600 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
601 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]602 }
603 },
604 {
605 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]606 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
607 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]608 }
609 },
610 {
611 {
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]612 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
613 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]614 }
615 },
616 }
617};
618
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]619static const struct ar9300_eeprom ar9300_x113 = {
620 .eepromVersion = 2,
621 .templateVersion = 6,
622 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
623 .custData = {"x113-023-f0000"},
624 .baseEepHeader = {
625 .regDmn = { LE16(0), LE16(0x1f) },
626 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
627 .opCapFlags = {
Luis R. Rodriguez9ba7f4f2011-05-11 14:57:26 -0700[diff] [blame]628 .opFlags = AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]629 .eepMisc = 0,
630 },
631 .rfSilent = 0,
632 .blueToothOptions = 0,
633 .deviceCap = 0,
634 .deviceType = 5, /* takes lower byte in eeprom location */
635 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
636 .params_for_tuning_caps = {0, 0},
637 .featureEnable = 0x0d,
638 /*
639 * bit0 - enable tx temp comp - disabled
640 * bit1 - enable tx volt comp - disabled
641 * bit2 - enable fastClock - enabled
642 * bit3 - enable doubling - enabled
643 * bit4 - enable internal regulator - disabled
644 * bit5 - enable pa predistortion - disabled
645 */
646 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
647 .eepromWriteEnableGpio = 6,
648 .wlanDisableGpio = 0,
649 .wlanLedGpio = 8,
650 .rxBandSelectGpio = 0xff,
651 .txrxgain = 0x21,
652 .swreg = 0,
653 },
654 .modalHeader2G = {
655 /* ar9300_modal_eep_header 2g */
656 /* 4 idle,t1,t2,b(4 bits per setting) */
657 .antCtrlCommon = LE32(0x110),
658 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
659 .antCtrlCommon2 = LE32(0x44444),
660
661 /*
662 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
663 * rx1, rx12, b (2 bits each)
664 */
665 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
666
667 /*
668 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
669 * for ar9280 (0xa20c/b20c 5:0)
670 */
671 .xatten1DB = {0, 0, 0},
672
673 /*
674 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
675 * for ar9280 (0xa20c/b20c 16:12
676 */
677 .xatten1Margin = {0, 0, 0},
678 .tempSlope = 25,
679 .voltSlope = 0,
680
681 /*
682 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
683 * channels in usual fbin coding format
684 */
685 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
686
687 /*
688 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
689 * if the register is per chain
690 */
691 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]692 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
693 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]694 .xpaBiasLvl = 0,
695 .txFrameToDataStart = 0x0e,
696 .txFrameToPaOn = 0x0e,
697 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
698 .antennaGain = 0,
699 .switchSettling = 0x2c,
700 .adcDesiredSize = -30,
701 .txEndToXpaOff = 0,
702 .txEndToRxOn = 0x2,
703 .txFrameToXpaOn = 0xe,
704 .thresh62 = 28,
705 .papdRateMaskHt20 = LE32(0x0c80c080),
706 .papdRateMaskHt40 = LE32(0x0080c080),
707 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]708 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]709 },
710 },
711 .base_ext1 = {
712 .ant_div_control = 0,
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]713 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]714 },
715 .calFreqPier2G = {
716 FREQ2FBIN(2412, 1),
717 FREQ2FBIN(2437, 1),
718 FREQ2FBIN(2472, 1),
719 },
720 /* ar9300_cal_data_per_freq_op_loop 2g */
721 .calPierData2G = {
722 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
723 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
724 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
725 },
726 .calTarget_freqbin_Cck = {
727 FREQ2FBIN(2412, 1),
728 FREQ2FBIN(2472, 1),
729 },
730 .calTarget_freqbin_2G = {
731 FREQ2FBIN(2412, 1),
732 FREQ2FBIN(2437, 1),
733 FREQ2FBIN(2472, 1)
734 },
735 .calTarget_freqbin_2GHT20 = {
736 FREQ2FBIN(2412, 1),
737 FREQ2FBIN(2437, 1),
738 FREQ2FBIN(2472, 1)
739 },
740 .calTarget_freqbin_2GHT40 = {
741 FREQ2FBIN(2412, 1),
742 FREQ2FBIN(2437, 1),
743 FREQ2FBIN(2472, 1)
744 },
745 .calTargetPowerCck = {
746 /* 1L-5L,5S,11L,11S */
747 { {34, 34, 34, 34} },
748 { {34, 34, 34, 34} },
749 },
750 .calTargetPower2G = {
751 /* 6-24,36,48,54 */
752 { {34, 34, 32, 32} },
753 { {34, 34, 32, 32} },
754 { {34, 34, 32, 32} },
755 },
756 .calTargetPower2GHT20 = {
757 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
758 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
759 { {32, 32, 32, 32, 32, 28, 32, 32, 30, 28, 0, 0, 0, 0} },
760 },
761 .calTargetPower2GHT40 = {
762 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
763 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
764 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
765 },
766 .ctlIndex_2G = {
767 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
768 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
769 },
770 .ctl_freqbin_2G = {
771 {
772 FREQ2FBIN(2412, 1),
773 FREQ2FBIN(2417, 1),
774 FREQ2FBIN(2457, 1),
775 FREQ2FBIN(2462, 1)
776 },
777 {
778 FREQ2FBIN(2412, 1),
779 FREQ2FBIN(2417, 1),
780 FREQ2FBIN(2462, 1),
781 0xFF,
782 },
783
784 {
785 FREQ2FBIN(2412, 1),
786 FREQ2FBIN(2417, 1),
787 FREQ2FBIN(2462, 1),
788 0xFF,
789 },
790 {
791 FREQ2FBIN(2422, 1),
792 FREQ2FBIN(2427, 1),
793 FREQ2FBIN(2447, 1),
794 FREQ2FBIN(2452, 1)
795 },
796
797 {
798 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
799 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
800 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
801 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
802 },
803
804 {
805 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
806 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
807 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
808 0,
809 },
810
811 {
812 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
813 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
814 FREQ2FBIN(2472, 1),
815 0,
816 },
817
818 {
819 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
820 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
821 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
822 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
823 },
824
825 {
826 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
827 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
828 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
829 },
830
831 {
832 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
833 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
834 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
835 0
836 },
837
838 {
839 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
840 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
841 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
842 0
843 },
844
845 {
846 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
847 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
848 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
849 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
850 }
851 },
852 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]853 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
854 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
855 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]856
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]857 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]858 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
859 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]860
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]861 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
862 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
863 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]864
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]865 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
866 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
867 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]868 },
869 .modalHeader5G = {
870 /* 4 idle,t1,t2,b (4 bits per setting) */
871 .antCtrlCommon = LE32(0x220),
872 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
873 .antCtrlCommon2 = LE32(0x11111),
874 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
875 .antCtrlChain = {
876 LE16(0x150), LE16(0x150), LE16(0x150),
877 },
878 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
879 .xatten1DB = {0, 0, 0},
880
881 /*
882 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
883 * for merlin (0xa20c/b20c 16:12
884 */
885 .xatten1Margin = {0, 0, 0},
886 .tempSlope = 68,
887 .voltSlope = 0,
888 /* spurChans spur channels in usual fbin coding format */
889 .spurChans = {FREQ2FBIN(5500, 0), 0, 0, 0, 0},
890 /* noiseFloorThreshCh Check if the register is per chain */
891 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]892 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
893 .quick_drop = 0,
Senthil Balasubramanianbe0e6aa2011-05-12 16:24:28 +0530[diff] [blame]894 .xpaBiasLvl = 0xf,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]895 .txFrameToDataStart = 0x0e,
896 .txFrameToPaOn = 0x0e,
897 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
898 .antennaGain = 0,
899 .switchSettling = 0x2d,
900 .adcDesiredSize = -30,
901 .txEndToXpaOff = 0,
902 .txEndToRxOn = 0x2,
903 .txFrameToXpaOn = 0xe,
904 .thresh62 = 28,
905 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
906 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
907 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]908 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]909 },
910 },
911 .base_ext2 = {
912 .tempSlopeLow = 72,
913 .tempSlopeHigh = 105,
914 .xatten1DBLow = {0, 0, 0},
915 .xatten1MarginLow = {0, 0, 0},
916 .xatten1DBHigh = {0, 0, 0},
917 .xatten1MarginHigh = {0, 0, 0}
918 },
919 .calFreqPier5G = {
920 FREQ2FBIN(5180, 0),
921 FREQ2FBIN(5240, 0),
922 FREQ2FBIN(5320, 0),
923 FREQ2FBIN(5400, 0),
924 FREQ2FBIN(5500, 0),
925 FREQ2FBIN(5600, 0),
926 FREQ2FBIN(5745, 0),
927 FREQ2FBIN(5785, 0)
928 },
929 .calPierData5G = {
930 {
931 {0, 0, 0, 0, 0},
932 {0, 0, 0, 0, 0},
933 {0, 0, 0, 0, 0},
934 {0, 0, 0, 0, 0},
935 {0, 0, 0, 0, 0},
936 {0, 0, 0, 0, 0},
937 {0, 0, 0, 0, 0},
938 {0, 0, 0, 0, 0},
939 },
940 {
941 {0, 0, 0, 0, 0},
942 {0, 0, 0, 0, 0},
943 {0, 0, 0, 0, 0},
944 {0, 0, 0, 0, 0},
945 {0, 0, 0, 0, 0},
946 {0, 0, 0, 0, 0},
947 {0, 0, 0, 0, 0},
948 {0, 0, 0, 0, 0},
949 },
950 {
951 {0, 0, 0, 0, 0},
952 {0, 0, 0, 0, 0},
953 {0, 0, 0, 0, 0},
954 {0, 0, 0, 0, 0},
955 {0, 0, 0, 0, 0},
956 {0, 0, 0, 0, 0},
957 {0, 0, 0, 0, 0},
958 {0, 0, 0, 0, 0},
959 },
960
961 },
962 .calTarget_freqbin_5G = {
963 FREQ2FBIN(5180, 0),
964 FREQ2FBIN(5220, 0),
965 FREQ2FBIN(5320, 0),
966 FREQ2FBIN(5400, 0),
967 FREQ2FBIN(5500, 0),
968 FREQ2FBIN(5600, 0),
969 FREQ2FBIN(5745, 0),
970 FREQ2FBIN(5785, 0)
971 },
972 .calTarget_freqbin_5GHT20 = {
973 FREQ2FBIN(5180, 0),
974 FREQ2FBIN(5240, 0),
975 FREQ2FBIN(5320, 0),
976 FREQ2FBIN(5400, 0),
977 FREQ2FBIN(5500, 0),
978 FREQ2FBIN(5700, 0),
979 FREQ2FBIN(5745, 0),
980 FREQ2FBIN(5825, 0)
981 },
982 .calTarget_freqbin_5GHT40 = {
983 FREQ2FBIN(5190, 0),
984 FREQ2FBIN(5230, 0),
985 FREQ2FBIN(5320, 0),
986 FREQ2FBIN(5410, 0),
987 FREQ2FBIN(5510, 0),
988 FREQ2FBIN(5670, 0),
989 FREQ2FBIN(5755, 0),
990 FREQ2FBIN(5825, 0)
991 },
992 .calTargetPower5G = {
993 /* 6-24,36,48,54 */
994 { {42, 40, 40, 34} },
995 { {42, 40, 40, 34} },
996 { {42, 40, 40, 34} },
997 { {42, 40, 40, 34} },
998 { {42, 40, 40, 34} },
999 { {42, 40, 40, 34} },
1000 { {42, 40, 40, 34} },
1001 { {42, 40, 40, 34} },
1002 },
1003 .calTargetPower5GHT20 = {
1004 /*
1005 * 0_8_16,1-3_9-11_17-19,
1006 * 4,5,6,7,12,13,14,15,20,21,22,23
1007 */
1008 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1009 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1010 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1011 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1012 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1013 { {40, 40, 40, 40, 32, 28, 40, 40, 32, 28, 40, 40, 32, 20} },
1014 { {38, 38, 38, 38, 32, 28, 38, 38, 32, 28, 38, 38, 32, 26} },
1015 { {36, 36, 36, 36, 32, 28, 36, 36, 32, 28, 36, 36, 32, 26} },
1016 },
1017 .calTargetPower5GHT40 = {
1018 /*
1019 * 0_8_16,1-3_9-11_17-19,
1020 * 4,5,6,7,12,13,14,15,20,21,22,23
1021 */
1022 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1023 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1024 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1025 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1026 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1027 { {40, 40, 40, 38, 30, 26, 40, 40, 30, 26, 40, 40, 30, 24} },
1028 { {36, 36, 36, 36, 30, 26, 36, 36, 30, 26, 36, 36, 30, 24} },
1029 { {34, 34, 34, 34, 30, 26, 34, 34, 30, 26, 34, 34, 30, 24} },
1030 },
1031 .ctlIndex_5G = {
1032 0x10, 0x16, 0x18, 0x40, 0x46,
1033 0x48, 0x30, 0x36, 0x38
1034 },
1035 .ctl_freqbin_5G = {
1036 {
1037 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1038 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1039 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1040 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1041 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1042 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1043 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1044 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1045 },
1046 {
1047 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1048 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1049 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1050 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1051 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1052 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1053 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1054 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1055 },
1056
1057 {
1058 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1059 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1060 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1061 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1062 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1063 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1064 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1065 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1066 },
1067
1068 {
1069 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1070 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1071 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1072 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1073 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1074 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1075 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1076 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1077 },
1078
1079 {
1080 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1081 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1082 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1083 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1084 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1085 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1086 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1087 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1088 },
1089
1090 {
1091 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1092 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1093 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1094 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1095 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1096 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1097 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1098 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1099 },
1100
1101 {
1102 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1103 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1104 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1105 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1106 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1107 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1108 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1109 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1110 },
1111
1112 {
1113 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1114 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1115 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1116 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1117 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1118 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1119 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1120 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1121 },
1122
1123 {
1124 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1125 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1126 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1127 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1128 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1129 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1130 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1131 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1132 }
1133 },
1134 .ctlPowerData_5G = {
1135 {
1136 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1137 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1138 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1139 }
1140 },
1141 {
1142 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1143 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1144 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1145 }
1146 },
1147 {
1148 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1149 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1150 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1151 }
1152 },
1153 {
1154 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1155 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1156 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1157 }
1158 },
1159 {
1160 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1161 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1162 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1163 }
1164 },
1165 {
1166 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1167 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1168 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1169 }
1170 },
1171 {
1172 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1173 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1174 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1175 }
1176 },
1177 {
1178 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1179 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1180 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1181 }
1182 },
1183 {
1184 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1185 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1186 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1187 }
1188 },
1189 }
1190};
1191
1192
1193static const struct ar9300_eeprom ar9300_h112 = {
1194 .eepromVersion = 2,
1195 .templateVersion = 3,
1196 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1197 .custData = {"h112-241-f0000"},
1198 .baseEepHeader = {
1199 .regDmn = { LE16(0), LE16(0x1f) },
1200 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1201 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]1202 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1203 .eepMisc = 0,
1204 },
1205 .rfSilent = 0,
1206 .blueToothOptions = 0,
1207 .deviceCap = 0,
1208 .deviceType = 5, /* takes lower byte in eeprom location */
1209 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1210 .params_for_tuning_caps = {0, 0},
1211 .featureEnable = 0x0d,
1212 /*
1213 * bit0 - enable tx temp comp - disabled
1214 * bit1 - enable tx volt comp - disabled
1215 * bit2 - enable fastClock - enabled
1216 * bit3 - enable doubling - enabled
1217 * bit4 - enable internal regulator - disabled
1218 * bit5 - enable pa predistortion - disabled
1219 */
1220 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1221 .eepromWriteEnableGpio = 6,
1222 .wlanDisableGpio = 0,
1223 .wlanLedGpio = 8,
1224 .rxBandSelectGpio = 0xff,
1225 .txrxgain = 0x10,
1226 .swreg = 0,
1227 },
1228 .modalHeader2G = {
1229 /* ar9300_modal_eep_header 2g */
1230 /* 4 idle,t1,t2,b(4 bits per setting) */
1231 .antCtrlCommon = LE32(0x110),
1232 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1233 .antCtrlCommon2 = LE32(0x44444),
1234
1235 /*
1236 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
1237 * rx1, rx12, b (2 bits each)
1238 */
1239 .antCtrlChain = { LE16(0x150), LE16(0x150), LE16(0x150) },
1240
1241 /*
1242 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
1243 * for ar9280 (0xa20c/b20c 5:0)
1244 */
1245 .xatten1DB = {0, 0, 0},
1246
1247 /*
1248 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1249 * for ar9280 (0xa20c/b20c 16:12
1250 */
1251 .xatten1Margin = {0, 0, 0},
1252 .tempSlope = 25,
1253 .voltSlope = 0,
1254
1255 /*
1256 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
1257 * channels in usual fbin coding format
1258 */
1259 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1260
1261 /*
1262 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
1263 * if the register is per chain
1264 */
1265 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1266 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1267 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1268 .xpaBiasLvl = 0,
1269 .txFrameToDataStart = 0x0e,
1270 .txFrameToPaOn = 0x0e,
1271 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1272 .antennaGain = 0,
1273 .switchSettling = 0x2c,
1274 .adcDesiredSize = -30,
1275 .txEndToXpaOff = 0,
1276 .txEndToRxOn = 0x2,
1277 .txFrameToXpaOn = 0xe,
1278 .thresh62 = 28,
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1279 .papdRateMaskHt20 = LE32(0x0c80c080),
1280 .papdRateMaskHt40 = LE32(0x0080c080),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1281 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]1282 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1283 },
1284 },
1285 .base_ext1 = {
1286 .ant_div_control = 0,
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1287 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1288 },
1289 .calFreqPier2G = {
1290 FREQ2FBIN(2412, 1),
1291 FREQ2FBIN(2437, 1),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1292 FREQ2FBIN(2462, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1293 },
1294 /* ar9300_cal_data_per_freq_op_loop 2g */
1295 .calPierData2G = {
1296 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1297 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1298 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1299 },
1300 .calTarget_freqbin_Cck = {
1301 FREQ2FBIN(2412, 1),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1302 FREQ2FBIN(2472, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1303 },
1304 .calTarget_freqbin_2G = {
1305 FREQ2FBIN(2412, 1),
1306 FREQ2FBIN(2437, 1),
1307 FREQ2FBIN(2472, 1)
1308 },
1309 .calTarget_freqbin_2GHT20 = {
1310 FREQ2FBIN(2412, 1),
1311 FREQ2FBIN(2437, 1),
1312 FREQ2FBIN(2472, 1)
1313 },
1314 .calTarget_freqbin_2GHT40 = {
1315 FREQ2FBIN(2412, 1),
1316 FREQ2FBIN(2437, 1),
1317 FREQ2FBIN(2472, 1)
1318 },
1319 .calTargetPowerCck = {
1320 /* 1L-5L,5S,11L,11S */
1321 { {34, 34, 34, 34} },
1322 { {34, 34, 34, 34} },
1323 },
1324 .calTargetPower2G = {
1325 /* 6-24,36,48,54 */
1326 { {34, 34, 32, 32} },
1327 { {34, 34, 32, 32} },
1328 { {34, 34, 32, 32} },
1329 },
1330 .calTargetPower2GHT20 = {
1331 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1332 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1333 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 28, 28, 28, 24} },
1334 },
1335 .calTargetPower2GHT40 = {
1336 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1337 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1338 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 26, 26, 26, 22} },
1339 },
1340 .ctlIndex_2G = {
1341 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1342 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1343 },
1344 .ctl_freqbin_2G = {
1345 {
1346 FREQ2FBIN(2412, 1),
1347 FREQ2FBIN(2417, 1),
1348 FREQ2FBIN(2457, 1),
1349 FREQ2FBIN(2462, 1)
1350 },
1351 {
1352 FREQ2FBIN(2412, 1),
1353 FREQ2FBIN(2417, 1),
1354 FREQ2FBIN(2462, 1),
1355 0xFF,
1356 },
1357
1358 {
1359 FREQ2FBIN(2412, 1),
1360 FREQ2FBIN(2417, 1),
1361 FREQ2FBIN(2462, 1),
1362 0xFF,
1363 },
1364 {
1365 FREQ2FBIN(2422, 1),
1366 FREQ2FBIN(2427, 1),
1367 FREQ2FBIN(2447, 1),
1368 FREQ2FBIN(2452, 1)
1369 },
1370
1371 {
1372 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1373 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1374 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1375 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
1376 },
1377
1378 {
1379 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1380 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1381 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1382 0,
1383 },
1384
1385 {
1386 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1387 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1388 FREQ2FBIN(2472, 1),
1389 0,
1390 },
1391
1392 {
1393 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1394 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1395 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1396 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1397 },
1398
1399 {
1400 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1401 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1402 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1403 },
1404
1405 {
1406 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1407 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1408 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1409 0
1410 },
1411
1412 {
1413 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
1414 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
1415 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
1416 0
1417 },
1418
1419 {
1420 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
1421 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
1422 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
1423 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
1424 }
1425 },
1426 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1427 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1428 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1429 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1430
Mohammed Shafi Shajakhan81dc6762011-06-17 11:07:32 +0530[diff] [blame]1431 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1432 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1433 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1434
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1435 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
1436 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1437 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1438
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1439 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
1440 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
1441 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1442 },
1443 .modalHeader5G = {
1444 /* 4 idle,t1,t2,b (4 bits per setting) */
1445 .antCtrlCommon = LE32(0x220),
1446 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
1447 .antCtrlCommon2 = LE32(0x44444),
1448 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
1449 .antCtrlChain = {
1450 LE16(0x150), LE16(0x150), LE16(0x150),
1451 },
1452 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
1453 .xatten1DB = {0, 0, 0},
1454
1455 /*
1456 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
1457 * for merlin (0xa20c/b20c 16:12
1458 */
1459 .xatten1Margin = {0, 0, 0},
1460 .tempSlope = 45,
1461 .voltSlope = 0,
1462 /* spurChans spur channels in usual fbin coding format */
1463 .spurChans = {0, 0, 0, 0, 0},
1464 /* noiseFloorThreshCh Check if the register is per chain */
1465 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1466 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1467 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1468 .xpaBiasLvl = 0,
1469 .txFrameToDataStart = 0x0e,
1470 .txFrameToPaOn = 0x0e,
1471 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1472 .antennaGain = 0,
1473 .switchSettling = 0x2d,
1474 .adcDesiredSize = -30,
1475 .txEndToXpaOff = 0,
1476 .txEndToRxOn = 0x2,
1477 .txFrameToXpaOn = 0xe,
1478 .thresh62 = 28,
1479 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
1480 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
1481 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]1482 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1483 },
1484 },
1485 .base_ext2 = {
1486 .tempSlopeLow = 40,
1487 .tempSlopeHigh = 50,
1488 .xatten1DBLow = {0, 0, 0},
1489 .xatten1MarginLow = {0, 0, 0},
1490 .xatten1DBHigh = {0, 0, 0},
1491 .xatten1MarginHigh = {0, 0, 0}
1492 },
1493 .calFreqPier5G = {
1494 FREQ2FBIN(5180, 0),
1495 FREQ2FBIN(5220, 0),
1496 FREQ2FBIN(5320, 0),
1497 FREQ2FBIN(5400, 0),
1498 FREQ2FBIN(5500, 0),
1499 FREQ2FBIN(5600, 0),
1500 FREQ2FBIN(5700, 0),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]1501 FREQ2FBIN(5785, 0)
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1502 },
1503 .calPierData5G = {
1504 {
1505 {0, 0, 0, 0, 0},
1506 {0, 0, 0, 0, 0},
1507 {0, 0, 0, 0, 0},
1508 {0, 0, 0, 0, 0},
1509 {0, 0, 0, 0, 0},
1510 {0, 0, 0, 0, 0},
1511 {0, 0, 0, 0, 0},
1512 {0, 0, 0, 0, 0},
1513 },
1514 {
1515 {0, 0, 0, 0, 0},
1516 {0, 0, 0, 0, 0},
1517 {0, 0, 0, 0, 0},
1518 {0, 0, 0, 0, 0},
1519 {0, 0, 0, 0, 0},
1520 {0, 0, 0, 0, 0},
1521 {0, 0, 0, 0, 0},
1522 {0, 0, 0, 0, 0},
1523 },
1524 {
1525 {0, 0, 0, 0, 0},
1526 {0, 0, 0, 0, 0},
1527 {0, 0, 0, 0, 0},
1528 {0, 0, 0, 0, 0},
1529 {0, 0, 0, 0, 0},
1530 {0, 0, 0, 0, 0},
1531 {0, 0, 0, 0, 0},
1532 {0, 0, 0, 0, 0},
1533 },
1534
1535 },
1536 .calTarget_freqbin_5G = {
1537 FREQ2FBIN(5180, 0),
1538 FREQ2FBIN(5240, 0),
1539 FREQ2FBIN(5320, 0),
1540 FREQ2FBIN(5400, 0),
1541 FREQ2FBIN(5500, 0),
1542 FREQ2FBIN(5600, 0),
1543 FREQ2FBIN(5700, 0),
1544 FREQ2FBIN(5825, 0)
1545 },
1546 .calTarget_freqbin_5GHT20 = {
1547 FREQ2FBIN(5180, 0),
1548 FREQ2FBIN(5240, 0),
1549 FREQ2FBIN(5320, 0),
1550 FREQ2FBIN(5400, 0),
1551 FREQ2FBIN(5500, 0),
1552 FREQ2FBIN(5700, 0),
1553 FREQ2FBIN(5745, 0),
1554 FREQ2FBIN(5825, 0)
1555 },
1556 .calTarget_freqbin_5GHT40 = {
1557 FREQ2FBIN(5180, 0),
1558 FREQ2FBIN(5240, 0),
1559 FREQ2FBIN(5320, 0),
1560 FREQ2FBIN(5400, 0),
1561 FREQ2FBIN(5500, 0),
1562 FREQ2FBIN(5700, 0),
1563 FREQ2FBIN(5745, 0),
1564 FREQ2FBIN(5825, 0)
1565 },
1566 .calTargetPower5G = {
1567 /* 6-24,36,48,54 */
1568 { {30, 30, 28, 24} },
1569 { {30, 30, 28, 24} },
1570 { {30, 30, 28, 24} },
1571 { {30, 30, 28, 24} },
1572 { {30, 30, 28, 24} },
1573 { {30, 30, 28, 24} },
1574 { {30, 30, 28, 24} },
1575 { {30, 30, 28, 24} },
1576 },
1577 .calTargetPower5GHT20 = {
1578 /*
1579 * 0_8_16,1-3_9-11_17-19,
1580 * 4,5,6,7,12,13,14,15,20,21,22,23
1581 */
1582 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1583 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 20, 20, 20, 16} },
1584 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1585 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 18, 18, 18, 16} },
1586 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1587 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 16, 16, 16, 14} },
1588 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1589 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 14, 14, 14, 12} },
1590 },
1591 .calTargetPower5GHT40 = {
1592 /*
1593 * 0_8_16,1-3_9-11_17-19,
1594 * 4,5,6,7,12,13,14,15,20,21,22,23
1595 */
1596 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1597 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 18, 18, 18, 14} },
1598 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1599 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 16, 16, 16, 12} },
1600 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1601 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 14, 14, 14, 10} },
1602 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1603 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 12, 12, 12, 8} },
1604 },
1605 .ctlIndex_5G = {
1606 0x10, 0x16, 0x18, 0x40, 0x46,
1607 0x48, 0x30, 0x36, 0x38
1608 },
1609 .ctl_freqbin_5G = {
1610 {
1611 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1612 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1613 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1614 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1615 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
1616 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1617 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1618 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1619 },
1620 {
1621 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1622 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1623 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
1624 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1625 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
1626 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1627 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1628 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1629 },
1630
1631 {
1632 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1633 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1634 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1635 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
1636 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
1637 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
1638 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
1639 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
1640 },
1641
1642 {
1643 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1644 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1645 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
1646 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
1647 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1648 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1649 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
1650 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
1651 },
1652
1653 {
1654 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1655 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1656 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
1657 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
1658 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
1659 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
1660 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
1661 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
1662 },
1663
1664 {
1665 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1666 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
1667 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
1668 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1669 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
1670 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1671 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
1672 /* Data[5].ctlEdges[7].bChannel */ 0xFF
1673 },
1674
1675 {
1676 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1677 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
1678 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
1679 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
1680 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
1681 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
1682 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
1683 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
1684 },
1685
1686 {
1687 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
1688 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
1689 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
1690 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
1691 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
1692 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
1693 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
1694 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
1695 },
1696
1697 {
1698 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
1699 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
1700 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
1701 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
1702 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
1703 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
1704 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
1705 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
1706 }
1707 },
1708 .ctlPowerData_5G = {
1709 {
1710 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1711 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1712 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1713 }
1714 },
1715 {
1716 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1717 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1718 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1719 }
1720 },
1721 {
1722 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1723 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1724 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1725 }
1726 },
1727 {
1728 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1729 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1730 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1731 }
1732 },
1733 {
1734 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1735 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
1736 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1737 }
1738 },
1739 {
1740 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1741 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1742 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1743 }
1744 },
1745 {
1746 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1747 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
1748 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1749 }
1750 },
1751 {
1752 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1753 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
1754 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1755 }
1756 },
1757 {
1758 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]1759 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
1760 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1761 }
1762 },
1763 }
1764};
1765
1766
1767static const struct ar9300_eeprom ar9300_x112 = {
1768 .eepromVersion = 2,
1769 .templateVersion = 5,
1770 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
1771 .custData = {"x112-041-f0000"},
1772 .baseEepHeader = {
1773 .regDmn = { LE16(0), LE16(0x1f) },
1774 .txrxMask = 0x77, /* 4 bits tx and 4 bits rx */
1775 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]1776 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1777 .eepMisc = 0,
1778 },
1779 .rfSilent = 0,
1780 .blueToothOptions = 0,
1781 .deviceCap = 0,
1782 .deviceType = 5, /* takes lower byte in eeprom location */
1783 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
1784 .params_for_tuning_caps = {0, 0},
1785 .featureEnable = 0x0d,
1786 /*
1787 * bit0 - enable tx temp comp - disabled
1788 * bit1 - enable tx volt comp - disabled
1789 * bit2 - enable fastclock - enabled
1790 * bit3 - enable doubling - enabled
1791 * bit4 - enable internal regulator - disabled
1792 * bit5 - enable pa predistortion - disabled
1793 */
1794 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
1795 .eepromWriteEnableGpio = 6,
1796 .wlanDisableGpio = 0,
1797 .wlanLedGpio = 8,
1798 .rxBandSelectGpio = 0xff,
1799 .txrxgain = 0x0,
1800 .swreg = 0,
1801 },
1802 .modalHeader2G = {
1803 /* ar9300_modal_eep_header 2g */
1804 /* 4 idle,t1,t2,b(4 bits per setting) */
1805 .antCtrlCommon = LE32(0x110),
1806 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
1807 .antCtrlCommon2 = LE32(0x22222),
1808
1809 /*
1810 * antCtrlChain[ar9300_max_chains]; 6 idle, t, r,
1811 * rx1, rx12, b (2 bits each)
1812 */
1813 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
1814
1815 /*
1816 * xatten1DB[AR9300_max_chains]; 3 xatten1_db
1817 * for ar9280 (0xa20c/b20c 5:0)
1818 */
1819 .xatten1DB = {0x1b, 0x1b, 0x1b},
1820
1821 /*
1822 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
1823 * for ar9280 (0xa20c/b20c 16:12
1824 */
1825 .xatten1Margin = {0x15, 0x15, 0x15},
1826 .tempSlope = 50,
1827 .voltSlope = 0,
1828
1829 /*
1830 * spurChans[OSPrey_eeprom_modal_sPURS]; spur
1831 * channels in usual fbin coding format
1832 */
1833 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
1834
1835 /*
1836 * noiseFloorThreshch[ar9300_max_cHAINS]; 3 Check
1837 * if the register is per chain
1838 */
1839 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1840 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
1841 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1842 .xpaBiasLvl = 0,
1843 .txFrameToDataStart = 0x0e,
1844 .txFrameToPaOn = 0x0e,
1845 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
1846 .antennaGain = 0,
1847 .switchSettling = 0x2c,
1848 .adcDesiredSize = -30,
1849 .txEndToXpaOff = 0,
1850 .txEndToRxOn = 0x2,
1851 .txFrameToXpaOn = 0xe,
1852 .thresh62 = 28,
1853 .papdRateMaskHt20 = LE32(0x0c80c080),
1854 .papdRateMaskHt40 = LE32(0x0080c080),
1855 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]1856 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1857 },
1858 },
1859 .base_ext1 = {
1860 .ant_div_control = 0,
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]1861 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]1862 },
1863 .calFreqPier2G = {
1864 FREQ2FBIN(2412, 1),
1865 FREQ2FBIN(2437, 1),
1866 FREQ2FBIN(2472, 1),
1867 },
1868 /* ar9300_cal_data_per_freq_op_loop 2g */
1869 .calPierData2G = {
1870 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1871 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1872 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
1873 },
1874 .calTarget_freqbin_Cck = {
1875 FREQ2FBIN(2412, 1),
1876 FREQ2FBIN(2472, 1),
1877 },
1878 .calTarget_freqbin_2G = {
1879 FREQ2FBIN(2412, 1),
1880 FREQ2FBIN(2437, 1),
1881 FREQ2FBIN(2472, 1)
1882 },
1883 .calTarget_freqbin_2GHT20 = {
1884 FREQ2FBIN(2412, 1),
1885 FREQ2FBIN(2437, 1),
1886 FREQ2FBIN(2472, 1)
1887 },
1888 .calTarget_freqbin_2GHT40 = {
1889 FREQ2FBIN(2412, 1),
1890 FREQ2FBIN(2437, 1),
1891 FREQ2FBIN(2472, 1)
1892 },
1893 .calTargetPowerCck = {
1894 /* 1L-5L,5S,11L,11s */
1895 { {38, 38, 38, 38} },
1896 { {38, 38, 38, 38} },
1897 },
1898 .calTargetPower2G = {
1899 /* 6-24,36,48,54 */
1900 { {38, 38, 36, 34} },
1901 { {38, 38, 36, 34} },
1902 { {38, 38, 34, 32} },
1903 },
1904 .calTargetPower2GHT20 = {
1905 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1906 { {36, 36, 36, 36, 36, 34, 36, 34, 32, 30, 30, 30, 28, 26} },
1907 { {36, 36, 36, 36, 36, 34, 34, 32, 30, 28, 28, 28, 28, 26} },
1908 },
1909 .calTargetPower2GHT40 = {
1910 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1911 { {36, 36, 36, 36, 34, 32, 34, 32, 30, 28, 28, 28, 28, 24} },
1912 { {36, 36, 36, 36, 34, 32, 32, 30, 28, 26, 26, 26, 26, 24} },
1913 },
1914 .ctlIndex_2G = {
1915 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
1916 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
1917 },
1918 .ctl_freqbin_2G = {
1919 {
1920 FREQ2FBIN(2412, 1),
1921 FREQ2FBIN(2417, 1),
1922 FREQ2FBIN(2457, 1),
1923 FREQ2FBIN(2462, 1)
1924 },
1925 {
1926 FREQ2FBIN(2412, 1),
1927 FREQ2FBIN(2417, 1),
1928 FREQ2FBIN(2462, 1),
1929 0xFF,
1930 },
1931
1932 {
1933 FREQ2FBIN(2412, 1),
1934 FREQ2FBIN(2417, 1),
1935 FREQ2FBIN(2462, 1),
1936 0xFF,
1937 },
1938 {
1939 FREQ2FBIN(2422, 1),
1940 FREQ2FBIN(2427, 1),
1941 FREQ2FBIN(2447, 1),
1942 FREQ2FBIN(2452, 1)
1943 },
1944
1945 {
1946 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1947 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1948 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1949 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(2484, 1),
1950 },
1951
1952 {
1953 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1954 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1955 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1956 0,
1957 },
1958
1959 {
1960 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1961 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1962 FREQ2FBIN(2472, 1),
1963 0,
1964 },
1965
1966 {
1967 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1968 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1969 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1970 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1971 },
1972
1973 {
1974 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1975 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1976 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1977 },
1978
1979 {
1980 /* Data[9].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1981 /* Data[9].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1982 /* Data[9].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1983 0
1984 },
1985
1986 {
1987 /* Data[10].ctledges[0].bchannel */ FREQ2FBIN(2412, 1),
1988 /* Data[10].ctledges[1].bchannel */ FREQ2FBIN(2417, 1),
1989 /* Data[10].ctledges[2].bchannel */ FREQ2FBIN(2472, 1),
1990 0
1991 },
1992
1993 {
1994 /* Data[11].ctledges[0].bchannel */ FREQ2FBIN(2422, 1),
1995 /* Data[11].ctledges[1].bchannel */ FREQ2FBIN(2427, 1),
1996 /* Data[11].ctledges[2].bchannel */ FREQ2FBIN(2447, 1),
1997 /* Data[11].ctledges[3].bchannel */ FREQ2FBIN(2462, 1),
1998 }
1999 },
2000 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2001 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2002 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2003 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2004
Rajkumar Manoharan15052f812011-07-29 17:38:15 +0530[diff] [blame]2005 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2006 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2007 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2008
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2009 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2010 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2011 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2012
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2013 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2014 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2015 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2016 },
2017 .modalHeader5G = {
2018 /* 4 idle,t1,t2,b (4 bits per setting) */
2019 .antCtrlCommon = LE32(0x110),
2020 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2021 .antCtrlCommon2 = LE32(0x22222),
2022 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2023 .antCtrlChain = {
2024 LE16(0x0), LE16(0x0), LE16(0x0),
2025 },
2026 /* xatten1DB 3 xatten1_db for ar9280 (0xa20c/b20c 5:0) */
2027 .xatten1DB = {0x13, 0x19, 0x17},
2028
2029 /*
2030 * xatten1Margin[ar9300_max_chains]; 3 xatten1_margin
2031 * for merlin (0xa20c/b20c 16:12
2032 */
2033 .xatten1Margin = {0x19, 0x19, 0x19},
2034 .tempSlope = 70,
2035 .voltSlope = 15,
2036 /* spurChans spur channels in usual fbin coding format */
2037 .spurChans = {0, 0, 0, 0, 0},
2038 /* noiseFloorThreshch check if the register is per chain */
2039 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2040 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2041 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2042 .xpaBiasLvl = 0,
2043 .txFrameToDataStart = 0x0e,
2044 .txFrameToPaOn = 0x0e,
2045 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2046 .antennaGain = 0,
2047 .switchSettling = 0x2d,
2048 .adcDesiredSize = -30,
2049 .txEndToXpaOff = 0,
2050 .txEndToRxOn = 0x2,
2051 .txFrameToXpaOn = 0xe,
2052 .thresh62 = 28,
2053 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2054 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2055 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]2056 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2057 },
2058 },
2059 .base_ext2 = {
2060 .tempSlopeLow = 72,
2061 .tempSlopeHigh = 105,
2062 .xatten1DBLow = {0x10, 0x14, 0x10},
2063 .xatten1MarginLow = {0x19, 0x19 , 0x19},
2064 .xatten1DBHigh = {0x1d, 0x20, 0x24},
2065 .xatten1MarginHigh = {0x10, 0x10, 0x10}
2066 },
2067 .calFreqPier5G = {
2068 FREQ2FBIN(5180, 0),
2069 FREQ2FBIN(5220, 0),
2070 FREQ2FBIN(5320, 0),
2071 FREQ2FBIN(5400, 0),
2072 FREQ2FBIN(5500, 0),
2073 FREQ2FBIN(5600, 0),
2074 FREQ2FBIN(5700, 0),
2075 FREQ2FBIN(5785, 0)
2076 },
2077 .calPierData5G = {
2078 {
2079 {0, 0, 0, 0, 0},
2080 {0, 0, 0, 0, 0},
2081 {0, 0, 0, 0, 0},
2082 {0, 0, 0, 0, 0},
2083 {0, 0, 0, 0, 0},
2084 {0, 0, 0, 0, 0},
2085 {0, 0, 0, 0, 0},
2086 {0, 0, 0, 0, 0},
2087 },
2088 {
2089 {0, 0, 0, 0, 0},
2090 {0, 0, 0, 0, 0},
2091 {0, 0, 0, 0, 0},
2092 {0, 0, 0, 0, 0},
2093 {0, 0, 0, 0, 0},
2094 {0, 0, 0, 0, 0},
2095 {0, 0, 0, 0, 0},
2096 {0, 0, 0, 0, 0},
2097 },
2098 {
2099 {0, 0, 0, 0, 0},
2100 {0, 0, 0, 0, 0},
2101 {0, 0, 0, 0, 0},
2102 {0, 0, 0, 0, 0},
2103 {0, 0, 0, 0, 0},
2104 {0, 0, 0, 0, 0},
2105 {0, 0, 0, 0, 0},
2106 {0, 0, 0, 0, 0},
2107 },
2108
2109 },
2110 .calTarget_freqbin_5G = {
2111 FREQ2FBIN(5180, 0),
2112 FREQ2FBIN(5220, 0),
2113 FREQ2FBIN(5320, 0),
2114 FREQ2FBIN(5400, 0),
2115 FREQ2FBIN(5500, 0),
2116 FREQ2FBIN(5600, 0),
2117 FREQ2FBIN(5725, 0),
2118 FREQ2FBIN(5825, 0)
2119 },
2120 .calTarget_freqbin_5GHT20 = {
2121 FREQ2FBIN(5180, 0),
2122 FREQ2FBIN(5220, 0),
2123 FREQ2FBIN(5320, 0),
2124 FREQ2FBIN(5400, 0),
2125 FREQ2FBIN(5500, 0),
2126 FREQ2FBIN(5600, 0),
2127 FREQ2FBIN(5725, 0),
2128 FREQ2FBIN(5825, 0)
2129 },
2130 .calTarget_freqbin_5GHT40 = {
2131 FREQ2FBIN(5180, 0),
2132 FREQ2FBIN(5220, 0),
2133 FREQ2FBIN(5320, 0),
2134 FREQ2FBIN(5400, 0),
2135 FREQ2FBIN(5500, 0),
2136 FREQ2FBIN(5600, 0),
2137 FREQ2FBIN(5725, 0),
2138 FREQ2FBIN(5825, 0)
2139 },
2140 .calTargetPower5G = {
2141 /* 6-24,36,48,54 */
2142 { {32, 32, 28, 26} },
2143 { {32, 32, 28, 26} },
2144 { {32, 32, 28, 26} },
2145 { {32, 32, 26, 24} },
2146 { {32, 32, 26, 24} },
2147 { {32, 32, 24, 22} },
2148 { {30, 30, 24, 22} },
2149 { {30, 30, 24, 22} },
2150 },
2151 .calTargetPower5GHT20 = {
2152 /*
2153 * 0_8_16,1-3_9-11_17-19,
2154 * 4,5,6,7,12,13,14,15,20,21,22,23
2155 */
2156 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2157 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2158 { {32, 32, 32, 32, 28, 26, 32, 28, 26, 24, 24, 24, 22, 22} },
2159 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 22, 22, 20, 20} },
2160 { {32, 32, 32, 32, 28, 26, 32, 26, 24, 22, 20, 18, 16, 16} },
2161 { {32, 32, 32, 32, 28, 26, 32, 24, 20, 16, 18, 16, 14, 14} },
2162 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2163 { {30, 30, 30, 30, 28, 26, 30, 24, 20, 16, 18, 16, 14, 14} },
2164 },
2165 .calTargetPower5GHT40 = {
2166 /*
2167 * 0_8_16,1-3_9-11_17-19,
2168 * 4,5,6,7,12,13,14,15,20,21,22,23
2169 */
2170 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2171 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2172 { {32, 32, 32, 30, 28, 26, 30, 28, 26, 24, 24, 24, 22, 22} },
2173 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 22, 22, 20, 20} },
2174 { {32, 32, 32, 30, 28, 26, 30, 26, 24, 22, 20, 18, 16, 16} },
2175 { {32, 32, 32, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2176 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2177 { {30, 30, 30, 30, 28, 26, 30, 22, 20, 16, 18, 16, 14, 14} },
2178 },
2179 .ctlIndex_5G = {
2180 0x10, 0x16, 0x18, 0x40, 0x46,
2181 0x48, 0x30, 0x36, 0x38
2182 },
2183 .ctl_freqbin_5G = {
2184 {
2185 /* Data[0].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2186 /* Data[0].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2187 /* Data[0].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2188 /* Data[0].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2189 /* Data[0].ctledges[4].bchannel */ FREQ2FBIN(5600, 0),
2190 /* Data[0].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2191 /* Data[0].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2192 /* Data[0].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2193 },
2194 {
2195 /* Data[1].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2196 /* Data[1].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2197 /* Data[1].ctledges[2].bchannel */ FREQ2FBIN(5280, 0),
2198 /* Data[1].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2199 /* Data[1].ctledges[4].bchannel */ FREQ2FBIN(5520, 0),
2200 /* Data[1].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2201 /* Data[1].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2202 /* Data[1].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2203 },
2204
2205 {
2206 /* Data[2].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2207 /* Data[2].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2208 /* Data[2].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2209 /* Data[2].ctledges[3].bchannel */ FREQ2FBIN(5310, 0),
2210 /* Data[2].ctledges[4].bchannel */ FREQ2FBIN(5510, 0),
2211 /* Data[2].ctledges[5].bchannel */ FREQ2FBIN(5550, 0),
2212 /* Data[2].ctledges[6].bchannel */ FREQ2FBIN(5670, 0),
2213 /* Data[2].ctledges[7].bchannel */ FREQ2FBIN(5755, 0)
2214 },
2215
2216 {
2217 /* Data[3].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2218 /* Data[3].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2219 /* Data[3].ctledges[2].bchannel */ FREQ2FBIN(5260, 0),
2220 /* Data[3].ctledges[3].bchannel */ FREQ2FBIN(5320, 0),
2221 /* Data[3].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2222 /* Data[3].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2223 /* Data[3].ctledges[6].bchannel */ 0xFF,
2224 /* Data[3].ctledges[7].bchannel */ 0xFF,
2225 },
2226
2227 {
2228 /* Data[4].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2229 /* Data[4].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2230 /* Data[4].ctledges[2].bchannel */ FREQ2FBIN(5500, 0),
2231 /* Data[4].ctledges[3].bchannel */ FREQ2FBIN(5700, 0),
2232 /* Data[4].ctledges[4].bchannel */ 0xFF,
2233 /* Data[4].ctledges[5].bchannel */ 0xFF,
2234 /* Data[4].ctledges[6].bchannel */ 0xFF,
2235 /* Data[4].ctledges[7].bchannel */ 0xFF,
2236 },
2237
2238 {
2239 /* Data[5].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2240 /* Data[5].ctledges[1].bchannel */ FREQ2FBIN(5270, 0),
2241 /* Data[5].ctledges[2].bchannel */ FREQ2FBIN(5310, 0),
2242 /* Data[5].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2243 /* Data[5].ctledges[4].bchannel */ FREQ2FBIN(5590, 0),
2244 /* Data[5].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2245 /* Data[5].ctledges[6].bchannel */ 0xFF,
2246 /* Data[5].ctledges[7].bchannel */ 0xFF
2247 },
2248
2249 {
2250 /* Data[6].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2251 /* Data[6].ctledges[1].bchannel */ FREQ2FBIN(5200, 0),
2252 /* Data[6].ctledges[2].bchannel */ FREQ2FBIN(5220, 0),
2253 /* Data[6].ctledges[3].bchannel */ FREQ2FBIN(5260, 0),
2254 /* Data[6].ctledges[4].bchannel */ FREQ2FBIN(5500, 0),
2255 /* Data[6].ctledges[5].bchannel */ FREQ2FBIN(5600, 0),
2256 /* Data[6].ctledges[6].bchannel */ FREQ2FBIN(5700, 0),
2257 /* Data[6].ctledges[7].bchannel */ FREQ2FBIN(5745, 0)
2258 },
2259
2260 {
2261 /* Data[7].ctledges[0].bchannel */ FREQ2FBIN(5180, 0),
2262 /* Data[7].ctledges[1].bchannel */ FREQ2FBIN(5260, 0),
2263 /* Data[7].ctledges[2].bchannel */ FREQ2FBIN(5320, 0),
2264 /* Data[7].ctledges[3].bchannel */ FREQ2FBIN(5500, 0),
2265 /* Data[7].ctledges[4].bchannel */ FREQ2FBIN(5560, 0),
2266 /* Data[7].ctledges[5].bchannel */ FREQ2FBIN(5700, 0),
2267 /* Data[7].ctledges[6].bchannel */ FREQ2FBIN(5745, 0),
2268 /* Data[7].ctledges[7].bchannel */ FREQ2FBIN(5825, 0)
2269 },
2270
2271 {
2272 /* Data[8].ctledges[0].bchannel */ FREQ2FBIN(5190, 0),
2273 /* Data[8].ctledges[1].bchannel */ FREQ2FBIN(5230, 0),
2274 /* Data[8].ctledges[2].bchannel */ FREQ2FBIN(5270, 0),
2275 /* Data[8].ctledges[3].bchannel */ FREQ2FBIN(5510, 0),
2276 /* Data[8].ctledges[4].bchannel */ FREQ2FBIN(5550, 0),
2277 /* Data[8].ctledges[5].bchannel */ FREQ2FBIN(5670, 0),
2278 /* Data[8].ctledges[6].bchannel */ FREQ2FBIN(5755, 0),
2279 /* Data[8].ctledges[7].bchannel */ FREQ2FBIN(5795, 0)
2280 }
2281 },
2282 .ctlPowerData_5G = {
2283 {
2284 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2285 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2286 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2287 }
2288 },
2289 {
2290 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2291 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2292 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2293 }
2294 },
2295 {
2296 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2297 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2298 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2299 }
2300 },
2301 {
2302 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2303 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2304 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2305 }
2306 },
2307 {
2308 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2309 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2310 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2311 }
2312 },
2313 {
2314 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2315 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2316 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2317 }
2318 },
2319 {
2320 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2321 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2322 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2323 }
2324 },
2325 {
2326 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2327 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2328 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2329 }
2330 },
2331 {
2332 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2333 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2334 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2335 }
2336 },
2337 }
2338};
2339
2340static const struct ar9300_eeprom ar9300_h116 = {
2341 .eepromVersion = 2,
2342 .templateVersion = 4,
2343 .macAddr = {0x00, 0x03, 0x7f, 0x0, 0x0, 0x0},
2344 .custData = {"h116-041-f0000"},
2345 .baseEepHeader = {
2346 .regDmn = { LE16(0), LE16(0x1f) },
2347 .txrxMask = 0x33, /* 4 bits tx and 4 bits rx */
2348 .opCapFlags = {
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]2349 .opFlags = AR5416_OPFLAGS_11G | AR5416_OPFLAGS_11A,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2350 .eepMisc = 0,
2351 },
2352 .rfSilent = 0,
2353 .blueToothOptions = 0,
2354 .deviceCap = 0,
2355 .deviceType = 5, /* takes lower byte in eeprom location */
2356 .pwrTableOffset = AR9300_PWR_TABLE_OFFSET,
2357 .params_for_tuning_caps = {0, 0},
2358 .featureEnable = 0x0d,
2359 /*
2360 * bit0 - enable tx temp comp - disabled
2361 * bit1 - enable tx volt comp - disabled
2362 * bit2 - enable fastClock - enabled
2363 * bit3 - enable doubling - enabled
2364 * bit4 - enable internal regulator - disabled
2365 * bit5 - enable pa predistortion - disabled
2366 */
2367 .miscConfiguration = 0, /* bit0 - turn down drivestrength */
2368 .eepromWriteEnableGpio = 6,
2369 .wlanDisableGpio = 0,
2370 .wlanLedGpio = 8,
2371 .rxBandSelectGpio = 0xff,
2372 .txrxgain = 0x10,
2373 .swreg = 0,
2374 },
2375 .modalHeader2G = {
2376 /* ar9300_modal_eep_header 2g */
2377 /* 4 idle,t1,t2,b(4 bits per setting) */
2378 .antCtrlCommon = LE32(0x110),
2379 /* 4 ra1l1, ra2l1, ra1l2, ra2l2, ra12 */
2380 .antCtrlCommon2 = LE32(0x44444),
2381
2382 /*
2383 * antCtrlChain[AR9300_MAX_CHAINS]; 6 idle, t, r,
2384 * rx1, rx12, b (2 bits each)
2385 */
2386 .antCtrlChain = { LE16(0x10), LE16(0x10), LE16(0x10) },
2387
2388 /*
2389 * xatten1DB[AR9300_MAX_CHAINS]; 3 xatten1_db
2390 * for ar9280 (0xa20c/b20c 5:0)
2391 */
2392 .xatten1DB = {0x1f, 0x1f, 0x1f},
2393
2394 /*
2395 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2396 * for ar9280 (0xa20c/b20c 16:12
2397 */
2398 .xatten1Margin = {0x12, 0x12, 0x12},
2399 .tempSlope = 25,
2400 .voltSlope = 0,
2401
2402 /*
2403 * spurChans[OSPREY_EEPROM_MODAL_SPURS]; spur
2404 * channels in usual fbin coding format
2405 */
2406 .spurChans = {FREQ2FBIN(2464, 1), 0, 0, 0, 0},
2407
2408 /*
2409 * noiseFloorThreshCh[AR9300_MAX_CHAINS]; 3 Check
2410 * if the register is per chain
2411 */
2412 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2413 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2414 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2415 .xpaBiasLvl = 0,
2416 .txFrameToDataStart = 0x0e,
2417 .txFrameToPaOn = 0x0e,
2418 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2419 .antennaGain = 0,
2420 .switchSettling = 0x2c,
2421 .adcDesiredSize = -30,
2422 .txEndToXpaOff = 0,
2423 .txEndToRxOn = 0x2,
2424 .txFrameToXpaOn = 0xe,
2425 .thresh62 = 28,
2426 .papdRateMaskHt20 = LE32(0x0c80C080),
2427 .papdRateMaskHt40 = LE32(0x0080C080),
2428 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]2429 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2430 },
2431 },
2432 .base_ext1 = {
2433 .ant_div_control = 0,
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2434 .future = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0}
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2435 },
2436 .calFreqPier2G = {
2437 FREQ2FBIN(2412, 1),
2438 FREQ2FBIN(2437, 1),
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]2439 FREQ2FBIN(2462, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2440 },
2441 /* ar9300_cal_data_per_freq_op_loop 2g */
2442 .calPierData2G = {
2443 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2444 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2445 { {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0}, {0, 0, 0, 0, 0, 0} },
2446 },
2447 .calTarget_freqbin_Cck = {
2448 FREQ2FBIN(2412, 1),
2449 FREQ2FBIN(2472, 1),
2450 },
2451 .calTarget_freqbin_2G = {
2452 FREQ2FBIN(2412, 1),
2453 FREQ2FBIN(2437, 1),
2454 FREQ2FBIN(2472, 1)
2455 },
2456 .calTarget_freqbin_2GHT20 = {
2457 FREQ2FBIN(2412, 1),
2458 FREQ2FBIN(2437, 1),
2459 FREQ2FBIN(2472, 1)
2460 },
2461 .calTarget_freqbin_2GHT40 = {
2462 FREQ2FBIN(2412, 1),
2463 FREQ2FBIN(2437, 1),
2464 FREQ2FBIN(2472, 1)
2465 },
2466 .calTargetPowerCck = {
2467 /* 1L-5L,5S,11L,11S */
2468 { {34, 34, 34, 34} },
2469 { {34, 34, 34, 34} },
2470 },
2471 .calTargetPower2G = {
2472 /* 6-24,36,48,54 */
2473 { {34, 34, 32, 32} },
2474 { {34, 34, 32, 32} },
2475 { {34, 34, 32, 32} },
2476 },
2477 .calTargetPower2GHT20 = {
2478 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2479 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2480 { {32, 32, 32, 32, 32, 30, 32, 32, 30, 28, 0, 0, 0, 0} },
2481 },
2482 .calTargetPower2GHT40 = {
2483 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2484 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2485 { {30, 30, 30, 30, 30, 28, 30, 30, 28, 26, 0, 0, 0, 0} },
2486 },
2487 .ctlIndex_2G = {
2488 0x11, 0x12, 0x15, 0x17, 0x41, 0x42,
2489 0x45, 0x47, 0x31, 0x32, 0x35, 0x37,
2490 },
2491 .ctl_freqbin_2G = {
2492 {
2493 FREQ2FBIN(2412, 1),
2494 FREQ2FBIN(2417, 1),
2495 FREQ2FBIN(2457, 1),
2496 FREQ2FBIN(2462, 1)
2497 },
2498 {
2499 FREQ2FBIN(2412, 1),
2500 FREQ2FBIN(2417, 1),
2501 FREQ2FBIN(2462, 1),
2502 0xFF,
2503 },
2504
2505 {
2506 FREQ2FBIN(2412, 1),
2507 FREQ2FBIN(2417, 1),
2508 FREQ2FBIN(2462, 1),
2509 0xFF,
2510 },
2511 {
2512 FREQ2FBIN(2422, 1),
2513 FREQ2FBIN(2427, 1),
2514 FREQ2FBIN(2447, 1),
2515 FREQ2FBIN(2452, 1)
2516 },
2517
2518 {
2519 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2520 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2521 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2522 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(2484, 1),
2523 },
2524
2525 {
2526 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2527 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2528 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2529 0,
2530 },
2531
2532 {
2533 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2534 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2535 FREQ2FBIN(2472, 1),
2536 0,
2537 },
2538
2539 {
2540 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2541 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2542 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2543 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2544 },
2545
2546 {
2547 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2548 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2549 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2550 },
2551
2552 {
2553 /* Data[9].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2554 /* Data[9].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2555 /* Data[9].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2556 0
2557 },
2558
2559 {
2560 /* Data[10].ctlEdges[0].bChannel */ FREQ2FBIN(2412, 1),
2561 /* Data[10].ctlEdges[1].bChannel */ FREQ2FBIN(2417, 1),
2562 /* Data[10].ctlEdges[2].bChannel */ FREQ2FBIN(2472, 1),
2563 0
2564 },
2565
2566 {
2567 /* Data[11].ctlEdges[0].bChannel */ FREQ2FBIN(2422, 1),
2568 /* Data[11].ctlEdges[1].bChannel */ FREQ2FBIN(2427, 1),
2569 /* Data[11].ctlEdges[2].bChannel */ FREQ2FBIN(2447, 1),
2570 /* Data[11].ctlEdges[3].bChannel */ FREQ2FBIN(2462, 1),
2571 }
2572 },
2573 .ctlPowerData_2G = {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2574 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2575 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2576 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2577
Mohammed Shafi Shajakhan81dc6762011-06-17 11:07:32 +0530[diff] [blame]2578 { { CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0) } },
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2579 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2580 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2581
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2582 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0) } },
2583 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2584 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2585
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2586 { { CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 0) } },
2587 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
2588 { { CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 1) } },
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2589 },
2590 .modalHeader5G = {
2591 /* 4 idle,t1,t2,b (4 bits per setting) */
2592 .antCtrlCommon = LE32(0x220),
2593 /* 4 ra1l1, ra2l1, ra1l2,ra2l2,ra12 */
2594 .antCtrlCommon2 = LE32(0x44444),
2595 /* antCtrlChain 6 idle, t,r,rx1,rx12,b (2 bits each) */
2596 .antCtrlChain = {
2597 LE16(0x150), LE16(0x150), LE16(0x150),
2598 },
2599 /* xatten1DB 3 xatten1_db for AR9280 (0xa20c/b20c 5:0) */
2600 .xatten1DB = {0x19, 0x19, 0x19},
2601
2602 /*
2603 * xatten1Margin[AR9300_MAX_CHAINS]; 3 xatten1_margin
2604 * for merlin (0xa20c/b20c 16:12
2605 */
2606 .xatten1Margin = {0x14, 0x14, 0x14},
2607 .tempSlope = 70,
2608 .voltSlope = 0,
2609 /* spurChans spur channels in usual fbin coding format */
2610 .spurChans = {0, 0, 0, 0, 0},
2611 /* noiseFloorThreshCh Check if the register is per chain */
2612 .noiseFloorThreshCh = {-1, 0, 0},
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2613 .reserved = {0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
2614 .quick_drop = 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2615 .xpaBiasLvl = 0,
2616 .txFrameToDataStart = 0x0e,
2617 .txFrameToPaOn = 0x0e,
2618 .txClip = 3, /* 4 bits tx_clip, 4 bits dac_scale_cck */
2619 .antennaGain = 0,
2620 .switchSettling = 0x2d,
2621 .adcDesiredSize = -30,
2622 .txEndToXpaOff = 0,
2623 .txEndToRxOn = 0x2,
2624 .txFrameToXpaOn = 0xe,
2625 .thresh62 = 28,
2626 .papdRateMaskHt20 = LE32(0x0cf0e0e0),
2627 .papdRateMaskHt40 = LE32(0x6cf0e0e0),
2628 .futureModal = {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]2629 0, 0, 0, 0, 0, 0, 0, 0,
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2630 },
2631 },
2632 .base_ext2 = {
2633 .tempSlopeLow = 35,
2634 .tempSlopeHigh = 50,
2635 .xatten1DBLow = {0, 0, 0},
2636 .xatten1MarginLow = {0, 0, 0},
2637 .xatten1DBHigh = {0, 0, 0},
2638 .xatten1MarginHigh = {0, 0, 0}
2639 },
2640 .calFreqPier5G = {
Rajkumar Manoharan94e2ad92011-11-08 14:19:34 +0530[diff] [blame]2641 FREQ2FBIN(5160, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2642 FREQ2FBIN(5220, 0),
2643 FREQ2FBIN(5320, 0),
2644 FREQ2FBIN(5400, 0),
2645 FREQ2FBIN(5500, 0),
2646 FREQ2FBIN(5600, 0),
2647 FREQ2FBIN(5700, 0),
2648 FREQ2FBIN(5785, 0)
2649 },
2650 .calPierData5G = {
2651 {
2652 {0, 0, 0, 0, 0},
2653 {0, 0, 0, 0, 0},
2654 {0, 0, 0, 0, 0},
2655 {0, 0, 0, 0, 0},
2656 {0, 0, 0, 0, 0},
2657 {0, 0, 0, 0, 0},
2658 {0, 0, 0, 0, 0},
2659 {0, 0, 0, 0, 0},
2660 },
2661 {
2662 {0, 0, 0, 0, 0},
2663 {0, 0, 0, 0, 0},
2664 {0, 0, 0, 0, 0},
2665 {0, 0, 0, 0, 0},
2666 {0, 0, 0, 0, 0},
2667 {0, 0, 0, 0, 0},
2668 {0, 0, 0, 0, 0},
2669 {0, 0, 0, 0, 0},
2670 },
2671 {
2672 {0, 0, 0, 0, 0},
2673 {0, 0, 0, 0, 0},
2674 {0, 0, 0, 0, 0},
2675 {0, 0, 0, 0, 0},
2676 {0, 0, 0, 0, 0},
2677 {0, 0, 0, 0, 0},
2678 {0, 0, 0, 0, 0},
2679 {0, 0, 0, 0, 0},
2680 },
2681
2682 },
2683 .calTarget_freqbin_5G = {
2684 FREQ2FBIN(5180, 0),
2685 FREQ2FBIN(5240, 0),
2686 FREQ2FBIN(5320, 0),
2687 FREQ2FBIN(5400, 0),
2688 FREQ2FBIN(5500, 0),
2689 FREQ2FBIN(5600, 0),
2690 FREQ2FBIN(5700, 0),
2691 FREQ2FBIN(5825, 0)
2692 },
2693 .calTarget_freqbin_5GHT20 = {
2694 FREQ2FBIN(5180, 0),
2695 FREQ2FBIN(5240, 0),
2696 FREQ2FBIN(5320, 0),
2697 FREQ2FBIN(5400, 0),
2698 FREQ2FBIN(5500, 0),
2699 FREQ2FBIN(5700, 0),
2700 FREQ2FBIN(5745, 0),
2701 FREQ2FBIN(5825, 0)
2702 },
2703 .calTarget_freqbin_5GHT40 = {
2704 FREQ2FBIN(5180, 0),
2705 FREQ2FBIN(5240, 0),
2706 FREQ2FBIN(5320, 0),
2707 FREQ2FBIN(5400, 0),
2708 FREQ2FBIN(5500, 0),
2709 FREQ2FBIN(5700, 0),
2710 FREQ2FBIN(5745, 0),
2711 FREQ2FBIN(5825, 0)
2712 },
2713 .calTargetPower5G = {
2714 /* 6-24,36,48,54 */
2715 { {30, 30, 28, 24} },
2716 { {30, 30, 28, 24} },
2717 { {30, 30, 28, 24} },
2718 { {30, 30, 28, 24} },
2719 { {30, 30, 28, 24} },
2720 { {30, 30, 28, 24} },
2721 { {30, 30, 28, 24} },
2722 { {30, 30, 28, 24} },
2723 },
2724 .calTargetPower5GHT20 = {
2725 /*
2726 * 0_8_16,1-3_9-11_17-19,
2727 * 4,5,6,7,12,13,14,15,20,21,22,23
2728 */
2729 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2730 { {30, 30, 30, 28, 24, 20, 30, 28, 24, 20, 0, 0, 0, 0} },
2731 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2732 { {30, 30, 30, 26, 22, 18, 30, 26, 22, 18, 0, 0, 0, 0} },
2733 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2734 { {30, 30, 30, 24, 20, 16, 30, 24, 20, 16, 0, 0, 0, 0} },
2735 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2736 { {30, 30, 30, 22, 18, 14, 30, 22, 18, 14, 0, 0, 0, 0} },
2737 },
2738 .calTargetPower5GHT40 = {
2739 /*
2740 * 0_8_16,1-3_9-11_17-19,
2741 * 4,5,6,7,12,13,14,15,20,21,22,23
2742 */
2743 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2744 { {28, 28, 28, 26, 22, 18, 28, 26, 22, 18, 0, 0, 0, 0} },
2745 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2746 { {28, 28, 28, 24, 20, 16, 28, 24, 20, 16, 0, 0, 0, 0} },
2747 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2748 { {28, 28, 28, 22, 18, 14, 28, 22, 18, 14, 0, 0, 0, 0} },
2749 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2750 { {28, 28, 28, 20, 16, 12, 28, 20, 16, 12, 0, 0, 0, 0} },
2751 },
2752 .ctlIndex_5G = {
2753 0x10, 0x16, 0x18, 0x40, 0x46,
2754 0x48, 0x30, 0x36, 0x38
2755 },
2756 .ctl_freqbin_5G = {
2757 {
2758 /* Data[0].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2759 /* Data[0].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2760 /* Data[0].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2761 /* Data[0].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2762 /* Data[0].ctlEdges[4].bChannel */ FREQ2FBIN(5600, 0),
2763 /* Data[0].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2764 /* Data[0].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2765 /* Data[0].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2766 },
2767 {
2768 /* Data[1].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2769 /* Data[1].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2770 /* Data[1].ctlEdges[2].bChannel */ FREQ2FBIN(5280, 0),
2771 /* Data[1].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2772 /* Data[1].ctlEdges[4].bChannel */ FREQ2FBIN(5520, 0),
2773 /* Data[1].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2774 /* Data[1].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2775 /* Data[1].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2776 },
2777
2778 {
2779 /* Data[2].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2780 /* Data[2].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2781 /* Data[2].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2782 /* Data[2].ctlEdges[3].bChannel */ FREQ2FBIN(5310, 0),
2783 /* Data[2].ctlEdges[4].bChannel */ FREQ2FBIN(5510, 0),
2784 /* Data[2].ctlEdges[5].bChannel */ FREQ2FBIN(5550, 0),
2785 /* Data[2].ctlEdges[6].bChannel */ FREQ2FBIN(5670, 0),
2786 /* Data[2].ctlEdges[7].bChannel */ FREQ2FBIN(5755, 0)
2787 },
2788
2789 {
2790 /* Data[3].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2791 /* Data[3].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2792 /* Data[3].ctlEdges[2].bChannel */ FREQ2FBIN(5260, 0),
2793 /* Data[3].ctlEdges[3].bChannel */ FREQ2FBIN(5320, 0),
2794 /* Data[3].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2795 /* Data[3].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2796 /* Data[3].ctlEdges[6].bChannel */ 0xFF,
2797 /* Data[3].ctlEdges[7].bChannel */ 0xFF,
2798 },
2799
2800 {
2801 /* Data[4].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2802 /* Data[4].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2803 /* Data[4].ctlEdges[2].bChannel */ FREQ2FBIN(5500, 0),
2804 /* Data[4].ctlEdges[3].bChannel */ FREQ2FBIN(5700, 0),
2805 /* Data[4].ctlEdges[4].bChannel */ 0xFF,
2806 /* Data[4].ctlEdges[5].bChannel */ 0xFF,
2807 /* Data[4].ctlEdges[6].bChannel */ 0xFF,
2808 /* Data[4].ctlEdges[7].bChannel */ 0xFF,
2809 },
2810
2811 {
2812 /* Data[5].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2813 /* Data[5].ctlEdges[1].bChannel */ FREQ2FBIN(5270, 0),
2814 /* Data[5].ctlEdges[2].bChannel */ FREQ2FBIN(5310, 0),
2815 /* Data[5].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2816 /* Data[5].ctlEdges[4].bChannel */ FREQ2FBIN(5590, 0),
2817 /* Data[5].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2818 /* Data[5].ctlEdges[6].bChannel */ 0xFF,
2819 /* Data[5].ctlEdges[7].bChannel */ 0xFF
2820 },
2821
2822 {
2823 /* Data[6].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2824 /* Data[6].ctlEdges[1].bChannel */ FREQ2FBIN(5200, 0),
2825 /* Data[6].ctlEdges[2].bChannel */ FREQ2FBIN(5220, 0),
2826 /* Data[6].ctlEdges[3].bChannel */ FREQ2FBIN(5260, 0),
2827 /* Data[6].ctlEdges[4].bChannel */ FREQ2FBIN(5500, 0),
2828 /* Data[6].ctlEdges[5].bChannel */ FREQ2FBIN(5600, 0),
2829 /* Data[6].ctlEdges[6].bChannel */ FREQ2FBIN(5700, 0),
2830 /* Data[6].ctlEdges[7].bChannel */ FREQ2FBIN(5745, 0)
2831 },
2832
2833 {
2834 /* Data[7].ctlEdges[0].bChannel */ FREQ2FBIN(5180, 0),
2835 /* Data[7].ctlEdges[1].bChannel */ FREQ2FBIN(5260, 0),
2836 /* Data[7].ctlEdges[2].bChannel */ FREQ2FBIN(5320, 0),
2837 /* Data[7].ctlEdges[3].bChannel */ FREQ2FBIN(5500, 0),
2838 /* Data[7].ctlEdges[4].bChannel */ FREQ2FBIN(5560, 0),
2839 /* Data[7].ctlEdges[5].bChannel */ FREQ2FBIN(5700, 0),
2840 /* Data[7].ctlEdges[6].bChannel */ FREQ2FBIN(5745, 0),
2841 /* Data[7].ctlEdges[7].bChannel */ FREQ2FBIN(5825, 0)
2842 },
2843
2844 {
2845 /* Data[8].ctlEdges[0].bChannel */ FREQ2FBIN(5190, 0),
2846 /* Data[8].ctlEdges[1].bChannel */ FREQ2FBIN(5230, 0),
2847 /* Data[8].ctlEdges[2].bChannel */ FREQ2FBIN(5270, 0),
2848 /* Data[8].ctlEdges[3].bChannel */ FREQ2FBIN(5510, 0),
2849 /* Data[8].ctlEdges[4].bChannel */ FREQ2FBIN(5550, 0),
2850 /* Data[8].ctlEdges[5].bChannel */ FREQ2FBIN(5670, 0),
2851 /* Data[8].ctlEdges[6].bChannel */ FREQ2FBIN(5755, 0),
2852 /* Data[8].ctlEdges[7].bChannel */ FREQ2FBIN(5795, 0)
2853 }
2854 },
2855 .ctlPowerData_5G = {
2856 {
2857 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2858 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2859 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2860 }
2861 },
2862 {
2863 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2864 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2865 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2866 }
2867 },
2868 {
2869 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2870 CTL(60, 0), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2871 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2872 }
2873 },
2874 {
2875 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2876 CTL(60, 0), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2877 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2878 }
2879 },
2880 {
2881 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2882 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
2883 CTL(60, 0), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2884 }
2885 },
2886 {
2887 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2888 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2889 CTL(60, 1), CTL(60, 0), CTL(60, 0), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2890 }
2891 },
2892 {
2893 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2894 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
2895 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2896 }
2897 },
2898 {
2899 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2900 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
2901 CTL(60, 1), CTL(60, 1), CTL(60, 1), CTL(60, 0),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2902 }
2903 },
2904 {
2905 {
David S. Millerfe6c7912010-12-08 13:15:38 -0800[diff] [blame]2906 CTL(60, 1), CTL(60, 0), CTL(60, 1), CTL(60, 1),
2907 CTL(60, 1), CTL(60, 1), CTL(60, 0), CTL(60, 1),
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]2908 }
2909 },
2910 }
2911};
2912
2913
2914static const struct ar9300_eeprom *ar9300_eep_templates[] = {
2915 &ar9300_default,
2916 &ar9300_x112,
2917 &ar9300_h116,
2918 &ar9300_h112,
2919 &ar9300_x113,
2920};
2921
2922static const struct ar9300_eeprom *ar9003_eeprom_struct_find_by_id(int id)
2923{
2924#define N_LOOP (sizeof(ar9300_eep_templates) / sizeof(ar9300_eep_templates[0]))
2925 int it;
2926
2927 for (it = 0; it < N_LOOP; it++)
2928 if (ar9300_eep_templates[it]->templateVersion == id)
2929 return ar9300_eep_templates[it];
2930 return NULL;
2931#undef N_LOOP
2932}
2933
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2934static int ath9k_hw_ar9300_check_eeprom(struct ath_hw *ah)
2935{
2936 return 0;
2937}
2938
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]2939static int interpolate(int x, int xa, int xb, int ya, int yb)
2940{
2941 int bf, factor, plus;
2942
2943 bf = 2 * (yb - ya) * (x - xa) / (xb - xa);
2944 factor = bf / 2;
2945 plus = bf % 2;
2946 return ya + factor + plus;
2947}
2948
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2949static u32 ath9k_hw_ar9300_get_eeprom(struct ath_hw *ah,
2950 enum eeprom_param param)
2951{
2952 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
2953 struct ar9300_base_eep_hdr *pBase = &eep->baseEepHeader;
2954
2955 switch (param) {
2956 case EEP_MAC_LSW:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2957 return get_unaligned_be16(eep->macAddr);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2958 case EEP_MAC_MID:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2959 return get_unaligned_be16(eep->macAddr + 2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2960 case EEP_MAC_MSW:
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]2961 return get_unaligned_be16(eep->macAddr + 4);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2962 case EEP_REG_0:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]2963 return le16_to_cpu(pBase->regDmn[0]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2964 case EEP_OP_CAP:
2965 return pBase->deviceCap;
2966 case EEP_OP_MODE:
2967 return pBase->opCapFlags.opFlags;
2968 case EEP_RF_SILENT:
2969 return pBase->rfSilent;
2970 case EEP_TX_MASK:
2971 return (pBase->txrxMask >> 4) & 0xf;
2972 case EEP_RX_MASK:
2973 return pBase->txrxMask & 0xf;
2974 case EEP_DRIVE_STRENGTH:
2975#define AR9300_EEP_BASE_DRIV_STRENGTH 0x1
2976 return pBase->miscConfiguration & AR9300_EEP_BASE_DRIV_STRENGTH;
2977 case EEP_INTERNAL_REGULATOR:
2978 /* Bit 4 is internal regulator flag */
2979 return (pBase->featureEnable & 0x10) >> 4;
2980 case EEP_SWREG:
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]2981 return le32_to_cpu(pBase->swreg);
Felix Fietkau49352502010-06-12 00:33:59 -0400[diff] [blame]2982 case EEP_PAPRD:
2983 return !!(pBase->featureEnable & BIT(5));
Mohammed Shafi Shajakhanea066d52010-11-23 20:42:27 +0530[diff] [blame]2984 case EEP_CHAIN_MASK_REDUCE:
2985 return (pBase->miscConfiguration >> 0x3) & 0x1;
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]2986 case EEP_ANT_DIV_CTL1:
Rajkumar Manoharan5479de62011-07-17 11:43:02 +0530[diff] [blame]2987 return eep->base_ext1.ant_div_control;
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame]2988 case EEP_ANTENNA_GAIN_5G:
2989 return eep->modalHeader5G.antennaGain;
2990 case EEP_ANTENNA_GAIN_2G:
2991 return eep->modalHeader2G.antennaGain;
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]2992 case EEP_QUICK_DROP:
2993 return pBase->miscConfiguration & BIT(1);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]2994 default:
2995 return 0;
2996 }
2997}
2998
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]2999static bool ar9300_eeprom_read_byte(struct ath_common *common, int address,
3000 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3001{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3002 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3003
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3004 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3005 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3006
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3007 *buffer = (val >> (8 * (address % 2))) & 0xff;
3008 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3009}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3010
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3011static bool ar9300_eeprom_read_word(struct ath_common *common, int address,
3012 u8 *buffer)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3013{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3014 u16 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3015
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3016 if (unlikely(!ath9k_hw_nvram_read(common, address / 2, &val)))
3017 return false;
3018
3019 buffer[0] = val >> 8;
3020 buffer[1] = val & 0xff;
3021
3022 return true;
3023}
3024
3025static bool ar9300_read_eeprom(struct ath_hw *ah, int address, u8 *buffer,
3026 int count)
3027{
3028 struct ath_common *common = ath9k_hw_common(ah);
3029 int i;
3030
3031 if ((address < 0) || ((address + count) / 2 > AR9300_EEPROM_SIZE - 1)) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3032 ath_dbg(common, EEPROM, "eeprom address not in range\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3033 return false;
3034 }
3035
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3036 /*
3037 * Since we're reading the bytes in reverse order from a little-endian
3038 * word stream, an even address means we only use the lower half of
3039 * the 16-bit word at that address
3040 */
3041 if (address % 2 == 0) {
3042 if (!ar9300_eeprom_read_byte(common, address--, buffer++))
3043 goto error;
3044
3045 count--;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3046 }
3047
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3048 for (i = 0; i < count / 2; i++) {
3049 if (!ar9300_eeprom_read_word(common, address, buffer))
3050 goto error;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3051
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3052 address -= 2;
3053 buffer += 2;
3054 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3055
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3056 if (count % 2)
3057 if (!ar9300_eeprom_read_byte(common, address, buffer))
3058 goto error;
3059
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3060 return true;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3061
3062error:
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3063 ath_dbg(common, EEPROM, "unable to read eeprom region at offset %d\n",
3064 address);
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3065 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3066}
3067
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3068static bool ar9300_otp_read_word(struct ath_hw *ah, int addr, u32 *data)
3069{
3070 REG_READ(ah, AR9300_OTP_BASE + (4 * addr));
3071
3072 if (!ath9k_hw_wait(ah, AR9300_OTP_STATUS, AR9300_OTP_STATUS_TYPE,
3073 AR9300_OTP_STATUS_VALID, 1000))
3074 return false;
3075
3076 *data = REG_READ(ah, AR9300_OTP_READ_DATA);
3077 return true;
3078}
3079
3080static bool ar9300_read_otp(struct ath_hw *ah, int address, u8 *buffer,
3081 int count)
3082{
3083 u32 data;
3084 int i;
3085
3086 for (i = 0; i < count; i++) {
3087 int offset = 8 * ((address - i) % 4);
3088 if (!ar9300_otp_read_word(ah, (address - i) / 4, &data))
3089 return false;
3090
3091 buffer[i] = (data >> offset) & 0xff;
3092 }
3093
3094 return true;
3095}
3096
3097
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3098static void ar9300_comp_hdr_unpack(u8 *best, int *code, int *reference,
3099 int *length, int *major, int *minor)
3100{
3101 unsigned long value[4];
3102
3103 value[0] = best[0];
3104 value[1] = best[1];
3105 value[2] = best[2];
3106 value[3] = best[3];
3107 *code = ((value[0] >> 5) & 0x0007);
3108 *reference = (value[0] & 0x001f) | ((value[1] >> 2) & 0x0020);
3109 *length = ((value[1] << 4) & 0x07f0) | ((value[2] >> 4) & 0x000f);
3110 *major = (value[2] & 0x000f);
3111 *minor = (value[3] & 0x00ff);
3112}
3113
3114static u16 ar9300_comp_cksum(u8 *data, int dsize)
3115{
3116 int it, checksum = 0;
3117
3118 for (it = 0; it < dsize; it++) {
3119 checksum += data[it];
3120 checksum &= 0xffff;
3121 }
3122
3123 return checksum;
3124}
3125
3126static bool ar9300_uncompress_block(struct ath_hw *ah,
3127 u8 *mptr,
3128 int mdataSize,
3129 u8 *block,
3130 int size)
3131{
3132 int it;
3133 int spot;
3134 int offset;
3135 int length;
3136 struct ath_common *common = ath9k_hw_common(ah);
3137
3138 spot = 0;
3139
3140 for (it = 0; it < size; it += (length+2)) {
3141 offset = block[it];
3142 offset &= 0xff;
3143 spot += offset;
3144 length = block[it+1];
3145 length &= 0xff;
3146
Luis R. Rodriguez803288e2010-08-30 19:26:32 -0400[diff] [blame]3147 if (length > 0 && spot >= 0 && spot+length <= mdataSize) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3148 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3149 "Restore at %d: spot=%d offset=%d length=%d\n",
3150 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3151 memcpy(&mptr[spot], &block[it+2], length);
3152 spot += length;
3153 } else if (length > 0) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3154 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3155 "Bad restore at %d: spot=%d offset=%d length=%d\n",
3156 it, spot, offset, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3157 return false;
3158 }
3159 }
3160 return true;
3161}
3162
3163static int ar9300_compress_decision(struct ath_hw *ah,
3164 int it,
3165 int code,
3166 int reference,
3167 u8 *mptr,
3168 u8 *word, int length, int mdata_size)
3169{
3170 struct ath_common *common = ath9k_hw_common(ah);
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3171 const struct ar9300_eeprom *eep = NULL;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3172
3173 switch (code) {
3174 case _CompressNone:
3175 if (length != mdata_size) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3176 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3177 "EEPROM structure size mismatch memory=%d eeprom=%d\n",
3178 mdata_size, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3179 return -1;
3180 }
3181 memcpy(mptr, (u8 *) (word + COMP_HDR_LEN), length);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3182 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3183 "restored eeprom %d: uncompressed, length %d\n",
3184 it, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3185 break;
3186 case _CompressBlock:
3187 if (reference == 0) {
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3188 } else {
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3189 eep = ar9003_eeprom_struct_find_by_id(reference);
3190 if (eep == NULL) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3191 ath_dbg(common, EEPROM,
Lucas De Marchi25985ed2011-03-30 22:57:33 -0300[diff] [blame]3192 "can't find reference eeprom struct %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3193 reference);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3194 return -1;
3195 }
Senthil Balasubramanian30923542010-11-10 05:03:10 -0800[diff] [blame]3196 memcpy(mptr, eep, mdata_size);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3197 }
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3198 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3199 "restore eeprom %d: block, reference %d, length %d\n",
3200 it, reference, length);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3201 ar9300_uncompress_block(ah, mptr, mdata_size,
3202 (u8 *) (word + COMP_HDR_LEN), length);
3203 break;
3204 default:
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3205 ath_dbg(common, EEPROM, "unknown compression code %d\n", code);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3206 return -1;
3207 }
3208 return 0;
3209}
3210
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3211typedef bool (*eeprom_read_op)(struct ath_hw *ah, int address, u8 *buffer,
3212 int count);
3213
3214static bool ar9300_check_header(void *data)
3215{
3216 u32 *word = data;
3217 return !(*word == 0 || *word == ~0);
3218}
3219
3220static bool ar9300_check_eeprom_header(struct ath_hw *ah, eeprom_read_op read,
3221 int base_addr)
3222{
3223 u8 header[4];
3224
3225 if (!read(ah, base_addr, header, 4))
3226 return false;
3227
3228 return ar9300_check_header(header);
3229}
3230
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3231static int ar9300_eeprom_restore_flash(struct ath_hw *ah, u8 *mptr,
3232 int mdata_size)
3233{
3234 struct ath_common *common = ath9k_hw_common(ah);
3235 u16 *data = (u16 *) mptr;
3236 int i;
3237
3238 for (i = 0; i < mdata_size / 2; i++, data++)
3239 ath9k_hw_nvram_read(common, i, data);
3240
3241 return 0;
3242}
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3243/*
3244 * Read the configuration data from the eeprom.
3245 * The data can be put in any specified memory buffer.
3246 *
3247 * Returns -1 on error.
3248 * Returns address of next memory location on success.
3249 */
3250static int ar9300_eeprom_restore_internal(struct ath_hw *ah,
3251 u8 *mptr, int mdata_size)
3252{
3253#define MDEFAULT 15
3254#define MSTATE 100
3255 int cptr;
3256 u8 *word;
3257 int code;
3258 int reference, length, major, minor;
3259 int osize;
3260 int it;
3261 u16 checksum, mchecksum;
3262 struct ath_common *common = ath9k_hw_common(ah);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3263 eeprom_read_op read;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3264
Felix Fietkauaaa13ca2010-11-17 04:19:47 +0100[diff] [blame]3265 if (ath9k_hw_use_flash(ah))
3266 return ar9300_eeprom_restore_flash(ah, mptr, mdata_size);
3267
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3268 word = kzalloc(2048, GFP_KERNEL);
3269 if (!word)
Larry Finger1ba45b92011-08-27 13:56:00 -0500[diff] [blame]3270 return -ENOMEM;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3271
3272 memcpy(mptr, &ar9300_default, mdata_size);
3273
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3274 read = ar9300_read_eeprom;
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3275 if (AR_SREV_9485(ah))
3276 cptr = AR9300_BASE_ADDR_4K;
Gabor Juhos5b5c0332011-06-21 11:23:38 +0200[diff] [blame]3277 else if (AR_SREV_9330(ah))
3278 cptr = AR9300_BASE_ADDR_512;
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3279 else
3280 cptr = AR9300_BASE_ADDR;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3281 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3282 cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3283 if (ar9300_check_eeprom_header(ah, read, cptr))
3284 goto found;
3285
3286 cptr = AR9300_BASE_ADDR_512;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3287 ath_dbg(common, EEPROM, "Trying EEPROM access at Address 0x%04x\n",
3288 cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3289 if (ar9300_check_eeprom_header(ah, read, cptr))
3290 goto found;
3291
3292 read = ar9300_read_otp;
3293 cptr = AR9300_BASE_ADDR;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3294 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3295 if (ar9300_check_eeprom_header(ah, read, cptr))
3296 goto found;
3297
3298 cptr = AR9300_BASE_ADDR_512;
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3299 ath_dbg(common, EEPROM, "Trying OTP access at Address 0x%04x\n", cptr);
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3300 if (ar9300_check_eeprom_header(ah, read, cptr))
3301 goto found;
3302
3303 goto fail;
3304
3305found:
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3306 ath_dbg(common, EEPROM, "Found valid EEPROM data\n");
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3307
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3308 for (it = 0; it < MSTATE; it++) {
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3309 if (!read(ah, cptr, word, COMP_HDR_LEN))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3310 goto fail;
3311
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3312 if (!ar9300_check_header(word))
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3313 break;
3314
3315 ar9300_comp_hdr_unpack(word, &code, &reference,
3316 &length, &major, &minor);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3317 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3318 "Found block at %x: code=%d ref=%d length=%d major=%d minor=%d\n",
3319 cptr, code, reference, length, major, minor);
Vasanthakumar Thiagarajan60e0c3a2010-12-06 04:27:39 -0800[diff] [blame]3320 if ((!AR_SREV_9485(ah) && length >= 1024) ||
Vasanthakumar Thiagarajand0ce2d12010-12-21 01:42:43 -0800[diff] [blame]3321 (AR_SREV_9485(ah) && length > EEPROM_DATA_LEN_9485)) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3322 ath_dbg(common, EEPROM, "Skipping bad header\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3323 cptr -= COMP_HDR_LEN;
3324 continue;
3325 }
3326
3327 osize = length;
Felix Fietkau488f6ba2010-11-16 19:20:28 +0100[diff] [blame]3328 read(ah, cptr, word, COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3329 checksum = ar9300_comp_cksum(&word[COMP_HDR_LEN], length);
Pavel Roskin78fa99a2011-07-15 19:06:33 -0400[diff] [blame]3330 mchecksum = get_unaligned_le16(&word[COMP_HDR_LEN + osize]);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3331 ath_dbg(common, EEPROM, "checksum %x %x\n",
3332 checksum, mchecksum);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3333 if (checksum == mchecksum) {
3334 ar9300_compress_decision(ah, it, code, reference, mptr,
3335 word, length, mdata_size);
3336 } else {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]3337 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]3338 "skipping block with bad checksum\n");
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3339 }
3340 cptr -= (COMP_HDR_LEN + osize + COMP_CKSUM_LEN);
3341 }
3342
3343 kfree(word);
3344 return cptr;
3345
3346fail:
3347 kfree(word);
3348 return -1;
3349}
3350
3351/*
3352 * Restore the configuration structure by reading the eeprom.
3353 * This function destroys any existing in-memory structure
3354 * content.
3355 */
3356static bool ath9k_hw_ar9300_fill_eeprom(struct ath_hw *ah)
3357{
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3358 u8 *mptr = (u8 *) &ah->eeprom.ar9300_eep;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3359
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3360 if (ar9300_eeprom_restore_internal(ah, mptr,
3361 sizeof(struct ar9300_eeprom)) < 0)
3362 return false;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3363
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3364 return true;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3365}
3366
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3367#if defined(CONFIG_ATH9K_DEBUGFS) || defined(CONFIG_ATH9K_HTC_DEBUGFS)
3368static u32 ar9003_dump_modal_eeprom(char *buf, u32 len, u32 size,
3369 struct ar9300_modal_eep_header *modal_hdr)
3370{
3371 PR_EEP("Chain0 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[0]));
3372 PR_EEP("Chain1 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[1]));
3373 PR_EEP("Chain2 Ant. Control", le16_to_cpu(modal_hdr->antCtrlChain[2]));
3374 PR_EEP("Ant. Common Control", le32_to_cpu(modal_hdr->antCtrlCommon));
3375 PR_EEP("Ant. Common Control2", le32_to_cpu(modal_hdr->antCtrlCommon2));
3376 PR_EEP("Ant. Gain", modal_hdr->antennaGain);
3377 PR_EEP("Switch Settle", modal_hdr->switchSettling);
3378 PR_EEP("Chain0 xatten1DB", modal_hdr->xatten1DB[0]);
3379 PR_EEP("Chain1 xatten1DB", modal_hdr->xatten1DB[1]);
3380 PR_EEP("Chain2 xatten1DB", modal_hdr->xatten1DB[2]);
3381 PR_EEP("Chain0 xatten1Margin", modal_hdr->xatten1Margin[0]);
3382 PR_EEP("Chain1 xatten1Margin", modal_hdr->xatten1Margin[1]);
3383 PR_EEP("Chain2 xatten1Margin", modal_hdr->xatten1Margin[2]);
3384 PR_EEP("Temp Slope", modal_hdr->tempSlope);
3385 PR_EEP("Volt Slope", modal_hdr->voltSlope);
3386 PR_EEP("spur Channels0", modal_hdr->spurChans[0]);
3387 PR_EEP("spur Channels1", modal_hdr->spurChans[1]);
3388 PR_EEP("spur Channels2", modal_hdr->spurChans[2]);
3389 PR_EEP("spur Channels3", modal_hdr->spurChans[3]);
3390 PR_EEP("spur Channels4", modal_hdr->spurChans[4]);
3391 PR_EEP("Chain0 NF Threshold", modal_hdr->noiseFloorThreshCh[0]);
3392 PR_EEP("Chain1 NF Threshold", modal_hdr->noiseFloorThreshCh[1]);
3393 PR_EEP("Chain2 NF Threshold", modal_hdr->noiseFloorThreshCh[2]);
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3394 PR_EEP("Quick Drop", modal_hdr->quick_drop);
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]3395 PR_EEP("txEndToXpaOff", modal_hdr->txEndToXpaOff);
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3396 PR_EEP("xPA Bias Level", modal_hdr->xpaBiasLvl);
3397 PR_EEP("txFrameToDataStart", modal_hdr->txFrameToDataStart);
3398 PR_EEP("txFrameToPaOn", modal_hdr->txFrameToPaOn);
3399 PR_EEP("txFrameToXpaOn", modal_hdr->txFrameToXpaOn);
3400 PR_EEP("txClip", modal_hdr->txClip);
3401 PR_EEP("ADC Desired size", modal_hdr->adcDesiredSize);
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3402
3403 return len;
3404}
3405
3406static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3407 u8 *buf, u32 len, u32 size)
3408{
3409 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3410 struct ar9300_base_eep_hdr *pBase;
3411
3412 if (!dump_base_hdr) {
3413 len += snprintf(buf + len, size - len,
3414 "%20s :\n", "2GHz modal Header");
3415 len += ar9003_dump_modal_eeprom(buf, len, size,
3416 &eep->modalHeader2G);
3417 len += snprintf(buf + len, size - len,
3418 "%20s :\n", "5GHz modal Header");
3419 len += ar9003_dump_modal_eeprom(buf, len, size,
3420 &eep->modalHeader5G);
3421 goto out;
3422 }
3423
3424 pBase = &eep->baseEepHeader;
3425
3426 PR_EEP("EEPROM Version", ah->eeprom.ar9300_eep.eepromVersion);
3427 PR_EEP("RegDomain1", le16_to_cpu(pBase->regDmn[0]));
3428 PR_EEP("RegDomain2", le16_to_cpu(pBase->regDmn[1]));
3429 PR_EEP("TX Mask", (pBase->txrxMask >> 4));
3430 PR_EEP("RX Mask", (pBase->txrxMask & 0x0f));
3431 PR_EEP("Allow 5GHz", !!(pBase->opCapFlags.opFlags &
3432 AR5416_OPFLAGS_11A));
3433 PR_EEP("Allow 2GHz", !!(pBase->opCapFlags.opFlags &
3434 AR5416_OPFLAGS_11G));
3435 PR_EEP("Disable 2GHz HT20", !!(pBase->opCapFlags.opFlags &
3436 AR5416_OPFLAGS_N_2G_HT20));
3437 PR_EEP("Disable 2GHz HT40", !!(pBase->opCapFlags.opFlags &
3438 AR5416_OPFLAGS_N_2G_HT40));
3439 PR_EEP("Disable 5Ghz HT20", !!(pBase->opCapFlags.opFlags &
3440 AR5416_OPFLAGS_N_5G_HT20));
3441 PR_EEP("Disable 5Ghz HT40", !!(pBase->opCapFlags.opFlags &
3442 AR5416_OPFLAGS_N_5G_HT40));
3443 PR_EEP("Big Endian", !!(pBase->opCapFlags.eepMisc & 0x01));
3444 PR_EEP("RF Silent", pBase->rfSilent);
3445 PR_EEP("BT option", pBase->blueToothOptions);
3446 PR_EEP("Device Cap", pBase->deviceCap);
3447 PR_EEP("Device Type", pBase->deviceType);
3448 PR_EEP("Power Table Offset", pBase->pwrTableOffset);
3449 PR_EEP("Tuning Caps1", pBase->params_for_tuning_caps[0]);
3450 PR_EEP("Tuning Caps2", pBase->params_for_tuning_caps[1]);
3451 PR_EEP("Enable Tx Temp Comp", !!(pBase->featureEnable & BIT(0)));
3452 PR_EEP("Enable Tx Volt Comp", !!(pBase->featureEnable & BIT(1)));
3453 PR_EEP("Enable fast clock", !!(pBase->featureEnable & BIT(2)));
3454 PR_EEP("Enable doubling", !!(pBase->featureEnable & BIT(3)));
3455 PR_EEP("Internal regulator", !!(pBase->featureEnable & BIT(4)));
3456 PR_EEP("Enable Paprd", !!(pBase->featureEnable & BIT(5)));
3457 PR_EEP("Driver Strength", !!(pBase->miscConfiguration & BIT(0)));
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3458 PR_EEP("Quick Drop", !!(pBase->miscConfiguration & BIT(1)));
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]3459 PR_EEP("Chain mask Reduce", (pBase->miscConfiguration >> 0x3) & 0x1);
3460 PR_EEP("Write enable Gpio", pBase->eepromWriteEnableGpio);
3461 PR_EEP("WLAN Disable Gpio", pBase->wlanDisableGpio);
3462 PR_EEP("WLAN LED Gpio", pBase->wlanLedGpio);
3463 PR_EEP("Rx Band Select Gpio", pBase->rxBandSelectGpio);
3464 PR_EEP("Tx Gain", pBase->txrxgain >> 4);
3465 PR_EEP("Rx Gain", pBase->txrxgain & 0xf);
3466 PR_EEP("SW Reg", le32_to_cpu(pBase->swreg));
3467
3468 len += snprintf(buf + len, size - len, "%20s : %pM\n", "MacAddress",
3469 ah->eeprom.ar9300_eep.macAddr);
3470out:
3471 if (len > size)
3472 len = size;
3473
3474 return len;
3475}
3476#else
3477static u32 ath9k_hw_ar9003_dump_eeprom(struct ath_hw *ah, bool dump_base_hdr,
3478 u8 *buf, u32 len, u32 size)
3479{
3480 return 0;
3481}
3482#endif
3483
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3484/* XXX: review hardware docs */
3485static int ath9k_hw_ar9300_get_eeprom_ver(struct ath_hw *ah)
3486{
3487 return ah->eeprom.ar9300_eep.eepromVersion;
3488}
3489
3490/* XXX: could be read from the eepromVersion, not sure yet */
3491static int ath9k_hw_ar9300_get_eeprom_rev(struct ath_hw *ah)
3492{
3493 return 0;
3494}
3495
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3496static s32 ar9003_hw_xpa_bias_level_get(struct ath_hw *ah, bool is2ghz)
3497{
3498 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3499
3500 if (is2ghz)
3501 return eep->modalHeader2G.xpaBiasLvl;
3502 else
3503 return eep->modalHeader5G.xpaBiasLvl;
3504}
3505
3506static void ar9003_hw_xpa_bias_level_apply(struct ath_hw *ah, bool is2ghz)
3507{
3508 int bias = ar9003_hw_xpa_bias_level_get(ah, is2ghz);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3509
Gabor Juhosdc9aa5f2011-06-21 11:23:39 +0200[diff] [blame]3510 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3511 REG_RMW_FIELD(ah, AR_CH0_TOP2, AR_CH0_TOP2_XPABIASLVL, bias);
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3512 else if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3513 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3514 else {
3515 REG_RMW_FIELD(ah, AR_CH0_TOP, AR_CH0_TOP_XPABIASLVL, bias);
Rajkumar Manoharan165af962011-05-09 19:11:26 +0530[diff] [blame]3516 REG_RMW_FIELD(ah, AR_CH0_THERM,
3517 AR_CH0_THERM_XPABIASLVL_MSB,
3518 bias >> 2);
3519 REG_RMW_FIELD(ah, AR_CH0_THERM,
3520 AR_CH0_THERM_XPASHORT2GND, 1);
Vasanthakumar Thiagarajan9936e652010-12-06 04:27:48 -0800[diff] [blame]3521 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3522}
3523
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3524static u16 ar9003_switch_com_spdt_get(struct ath_hw *ah, bool is_2ghz)
3525{
3526 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Luis R. Rodrigueza98aa7a2011-12-20 10:46:11 -0800[diff] [blame]3527 __le16 val;
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3528
3529 if (is_2ghz)
3530 val = eep->modalHeader2G.switchcomspdt;
3531 else
3532 val = eep->modalHeader5G.switchcomspdt;
Luis R. Rodrigueza98aa7a2011-12-20 10:46:11 -0800[diff] [blame]3533 return le16_to_cpu(val);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3534}
3535
3536
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3537static u32 ar9003_hw_ant_ctrl_common_get(struct ath_hw *ah, bool is2ghz)
3538{
3539 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3540 __le32 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3541
3542 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3543 val = eep->modalHeader2G.antCtrlCommon;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3544 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3545 val = eep->modalHeader5G.antCtrlCommon;
3546 return le32_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3547}
3548
3549static u32 ar9003_hw_ant_ctrl_common_2_get(struct ath_hw *ah, bool is2ghz)
3550{
3551 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3552 __le32 val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3553
3554 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3555 val = eep->modalHeader2G.antCtrlCommon2;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3556 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3557 val = eep->modalHeader5G.antCtrlCommon2;
3558 return le32_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3559}
3560
3561static u16 ar9003_hw_ant_ctrl_chain_get(struct ath_hw *ah,
3562 int chain,
3563 bool is2ghz)
3564{
3565 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3566 __le16 val = 0;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3567
3568 if (chain >= 0 && chain < AR9300_MAX_CHAINS) {
3569 if (is2ghz)
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3570 val = eep->modalHeader2G.antCtrlChain[chain];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3571 else
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3572 val = eep->modalHeader5G.antCtrlChain[chain];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3573 }
3574
Felix Fietkauffdc4cb2010-05-11 17:23:03 +0200[diff] [blame]3575 return le16_to_cpu(val);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3576}
3577
3578static void ar9003_hw_ant_ctrl_apply(struct ath_hw *ah, bool is2ghz)
3579{
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3580 int chain;
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3581 u32 regval;
3582 u32 ant_div_ctl1;
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3583 static const u32 switch_chain_reg[AR9300_MAX_CHAINS] = {
3584 AR_PHY_SWITCH_CHAIN_0,
3585 AR_PHY_SWITCH_CHAIN_1,
3586 AR_PHY_SWITCH_CHAIN_2,
3587 };
3588
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3589 u32 value = ar9003_hw_ant_ctrl_common_get(ah, is2ghz);
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3590
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3591 if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3592 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3593 AR_SWITCH_TABLE_COM_AR9462_ALL, value);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3594 } else
3595 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM,
3596 AR_SWITCH_TABLE_COM_ALL, value);
3597
3598
3599 /*
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3600 * AR9462 defines new switch table for BT/WLAN,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3601 * here's new field name in XXX.ref for both 2G and 5G.
3602 * Register: [GLB_CONTROL] GLB_CONTROL (@0x20044)
3603 * 15:12 R/W SWITCH_TABLE_COM_SPDT_WLAN_RX
3604 * SWITCH_TABLE_COM_SPDT_WLAN_RX
3605 *
3606 * 11:8 R/W SWITCH_TABLE_COM_SPDT_WLAN_TX
3607 * SWITCH_TABLE_COM_SPDT_WLAN_TX
3608 *
3609 * 7:4 R/W SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3610 * SWITCH_TABLE_COM_SPDT_WLAN_IDLE
3611 */
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3612 if (AR_SREV_9462_20_OR_LATER(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3613 value = ar9003_switch_com_spdt_get(ah, is2ghz);
3614 REG_RMW_FIELD(ah, AR_PHY_GLB_CONTROL,
3615 AR_SWITCH_TABLE_COM_SPDT_ALL, value);
3616 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3617
3618 value = ar9003_hw_ant_ctrl_common_2_get(ah, is2ghz);
3619 REG_RMW_FIELD(ah, AR_PHY_SWITCH_COM_2, AR_SWITCH_TABLE_COM2_ALL, value);
3620
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3621 for (chain = 0; chain < AR9300_MAX_CHAINS; chain++) {
3622 if ((ah->rxchainmask & BIT(chain)) ||
3623 (ah->txchainmask & BIT(chain))) {
3624 value = ar9003_hw_ant_ctrl_chain_get(ah, chain,
3625 is2ghz);
3626 REG_RMW_FIELD(ah, switch_chain_reg[chain],
3627 AR_SWITCH_TABLE_ALL, value);
3628 }
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3629 }
3630
Gabor Juhos7b09e492011-06-21 11:23:49 +0200[diff] [blame]3631 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3632 value = ath9k_hw_ar9300_get_eeprom(ah, EEP_ANT_DIV_CTL1);
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3633 /*
3634 * main_lnaconf, alt_lnaconf, main_tb, alt_tb
3635 * are the fields present
3636 */
3637 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3638 regval &= (~AR_ANT_DIV_CTRL_ALL);
3639 regval |= (value & 0x3f) << AR_ANT_DIV_CTRL_ALL_S;
3640 /* enable_lnadiv */
3641 regval &= (~AR_PHY_9485_ANT_DIV_LNADIV);
3642 regval |= ((value >> 6) & 0x1) <<
3643 AR_PHY_9485_ANT_DIV_LNADIV_S;
3644 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3645
3646 /*enable fast_div */
3647 regval = REG_READ(ah, AR_PHY_CCK_DETECT);
3648 regval &= (~AR_FAST_DIV_ENABLE);
3649 regval |= ((value >> 7) & 0x1) <<
3650 AR_FAST_DIV_ENABLE_S;
3651 REG_WRITE(ah, AR_PHY_CCK_DETECT, regval);
3652 ant_div_ctl1 =
3653 ah->eep_ops->get_eeprom(ah, EEP_ANT_DIV_CTL1);
3654 /* check whether antenna diversity is enabled */
3655 if ((ant_div_ctl1 >> 0x6) == 0x3) {
3656 regval = REG_READ(ah, AR_PHY_MC_GAIN_CTRL);
3657 /*
3658 * clear bits 25-30 main_lnaconf, alt_lnaconf,
3659 * main_tb, alt_tb
3660 */
3661 regval &= (~(AR_PHY_9485_ANT_DIV_MAIN_LNACONF |
3662 AR_PHY_9485_ANT_DIV_ALT_LNACONF |
3663 AR_PHY_9485_ANT_DIV_ALT_GAINTB |
3664 AR_PHY_9485_ANT_DIV_MAIN_GAINTB));
3665 /* by default use LNA1 for the main antenna */
3666 regval |= (AR_PHY_9485_ANT_DIV_LNA1 <<
3667 AR_PHY_9485_ANT_DIV_MAIN_LNACONF_S);
3668 regval |= (AR_PHY_9485_ANT_DIV_LNA2 <<
3669 AR_PHY_9485_ANT_DIV_ALT_LNACONF_S);
3670 REG_WRITE(ah, AR_PHY_MC_GAIN_CTRL, regval);
3671 }
3672
3673
Vasanthakumar Thiagarajan47e84df2010-12-06 04:27:49 -0800[diff] [blame]3674 }
Mohammed Shafi Shajakhan842ca782011-05-13 20:30:27 +0530[diff] [blame]3675
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3676}
3677
3678static void ar9003_hw_drive_strength_apply(struct ath_hw *ah)
3679{
3680 int drive_strength;
3681 unsigned long reg;
3682
3683 drive_strength = ath9k_hw_ar9300_get_eeprom(ah, EEP_DRIVE_STRENGTH);
3684
3685 if (!drive_strength)
3686 return;
3687
3688 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS1);
3689 reg &= ~0x00ffffc0;
3690 reg |= 0x5 << 21;
3691 reg |= 0x5 << 18;
3692 reg |= 0x5 << 15;
3693 reg |= 0x5 << 12;
3694 reg |= 0x5 << 9;
3695 reg |= 0x5 << 6;
3696 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS1, reg);
3697
3698 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS2);
3699 reg &= ~0xffffffe0;
3700 reg |= 0x5 << 29;
3701 reg |= 0x5 << 26;
3702 reg |= 0x5 << 23;
3703 reg |= 0x5 << 20;
3704 reg |= 0x5 << 17;
3705 reg |= 0x5 << 14;
3706 reg |= 0x5 << 11;
3707 reg |= 0x5 << 8;
3708 reg |= 0x5 << 5;
3709 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS2, reg);
3710
3711 reg = REG_READ(ah, AR_PHY_65NM_CH0_BIAS4);
3712 reg &= ~0xff800000;
3713 reg |= 0x5 << 29;
3714 reg |= 0x5 << 26;
3715 reg |= 0x5 << 23;
3716 REG_WRITE(ah, AR_PHY_65NM_CH0_BIAS4, reg);
3717}
3718
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3719static u16 ar9003_hw_atten_chain_get(struct ath_hw *ah, int chain,
3720 struct ath9k_channel *chan)
3721{
3722 int f[3], t[3];
3723 u16 value;
3724 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3725
3726 if (chain >= 0 && chain < 3) {
3727 if (IS_CHAN_2GHZ(chan))
3728 return eep->modalHeader2G.xatten1DB[chain];
3729 else if (eep->base_ext2.xatten1DBLow[chain] != 0) {
3730 t[0] = eep->base_ext2.xatten1DBLow[chain];
3731 f[0] = 5180;
3732 t[1] = eep->modalHeader5G.xatten1DB[chain];
3733 f[1] = 5500;
3734 t[2] = eep->base_ext2.xatten1DBHigh[chain];
3735 f[2] = 5785;
3736 value = ar9003_hw_power_interpolate((s32) chan->channel,
3737 f, t, 3);
3738 return value;
3739 } else
3740 return eep->modalHeader5G.xatten1DB[chain];
3741 }
3742
3743 return 0;
3744}
3745
3746
3747static u16 ar9003_hw_atten_chain_get_margin(struct ath_hw *ah, int chain,
3748 struct ath9k_channel *chan)
3749{
3750 int f[3], t[3];
3751 u16 value;
3752 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3753
3754 if (chain >= 0 && chain < 3) {
3755 if (IS_CHAN_2GHZ(chan))
3756 return eep->modalHeader2G.xatten1Margin[chain];
3757 else if (eep->base_ext2.xatten1MarginLow[chain] != 0) {
3758 t[0] = eep->base_ext2.xatten1MarginLow[chain];
3759 f[0] = 5180;
3760 t[1] = eep->modalHeader5G.xatten1Margin[chain];
3761 f[1] = 5500;
3762 t[2] = eep->base_ext2.xatten1MarginHigh[chain];
3763 f[2] = 5785;
3764 value = ar9003_hw_power_interpolate((s32) chan->channel,
3765 f, t, 3);
3766 return value;
3767 } else
3768 return eep->modalHeader5G.xatten1Margin[chain];
3769 }
3770
3771 return 0;
3772}
3773
3774static void ar9003_hw_atten_apply(struct ath_hw *ah, struct ath9k_channel *chan)
3775{
3776 int i;
3777 u16 value;
3778 unsigned long ext_atten_reg[3] = {AR_PHY_EXT_ATTEN_CTL_0,
3779 AR_PHY_EXT_ATTEN_CTL_1,
3780 AR_PHY_EXT_ATTEN_CTL_2,
3781 };
3782
3783 /* Test value. if 0 then attenuation is unused. Don't load anything. */
3784 for (i = 0; i < 3; i++) {
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3785 if (ah->txchainmask & BIT(i)) {
3786 value = ar9003_hw_atten_chain_get(ah, i, chan);
3787 REG_RMW_FIELD(ah, ext_atten_reg[i],
3788 AR_PHY_EXT_ATTEN_CTL_XATTEN1_DB, value);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3789
Vasanthakumar Thiagarajan2976bc52011-04-19 19:29:15 +0530[diff] [blame]3790 value = ar9003_hw_atten_chain_get_margin(ah, i, chan);
3791 REG_RMW_FIELD(ah, ext_atten_reg[i],
3792 AR_PHY_EXT_ATTEN_CTL_XATTEN1_MARGIN,
3793 value);
3794 }
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3795 }
3796}
3797
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3798static bool is_pmu_set(struct ath_hw *ah, u32 pmu_reg, int pmu_set)
3799{
3800 int timeout = 100;
3801
3802 while (pmu_set != REG_READ(ah, pmu_reg)) {
3803 if (timeout-- == 0)
3804 return false;
3805 REG_WRITE(ah, pmu_reg, pmu_set);
3806 udelay(10);
3807 }
3808
3809 return true;
3810}
3811
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3812static void ar9003_hw_internal_regulator_apply(struct ath_hw *ah)
3813{
3814 int internal_regulator =
3815 ath9k_hw_ar9300_get_eeprom(ah, EEP_INTERNAL_REGULATOR);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3816 u32 reg_val;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3817
3818 if (internal_regulator) {
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3819 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3820 int reg_pmu_set;
3821
3822 reg_pmu_set = REG_READ(ah, AR_PHY_PMU2) & ~AR_PHY_PMU2_PGM;
3823 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3824 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3825 return;
3826
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3827 if (AR_SREV_9330(ah)) {
3828 if (ah->is_clk_25mhz) {
3829 reg_pmu_set = (3 << 1) | (8 << 4) |
3830 (3 << 8) | (1 << 14) |
3831 (6 << 17) | (1 << 20) |
3832 (3 << 24);
3833 } else {
3834 reg_pmu_set = (4 << 1) | (7 << 4) |
3835 (3 << 8) | (1 << 14) |
3836 (6 << 17) | (1 << 20) |
3837 (3 << 24);
3838 }
3839 } else {
3840 reg_pmu_set = (5 << 1) | (7 << 4) |
Rajkumar Manoharan1fa707a2011-07-29 17:38:17 +0530[diff] [blame]3841 (2 << 8) | (2 << 14) |
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3842 (6 << 17) | (1 << 20) |
3843 (3 << 24) | (1 << 28);
3844 }
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3845
3846 REG_WRITE(ah, AR_PHY_PMU1, reg_pmu_set);
3847 if (!is_pmu_set(ah, AR_PHY_PMU1, reg_pmu_set))
3848 return;
3849
3850 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0xFFC00000)
3851 | (4 << 26);
3852 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3853 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3854 return;
3855
3856 reg_pmu_set = (REG_READ(ah, AR_PHY_PMU2) & ~0x00200000)
3857 | (1 << 21);
3858 REG_WRITE(ah, AR_PHY_PMU2, reg_pmu_set);
3859 if (!is_pmu_set(ah, AR_PHY_PMU2, reg_pmu_set))
3860 return;
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3861 } else if (AR_SREV_9462(ah)) {
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3862 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
3863 REG_WRITE(ah, AR_PHY_PMU1, reg_val);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3864 } else {
3865 /* Internal regulator is ON. Write swreg register. */
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3866 reg_val = ath9k_hw_ar9300_get_eeprom(ah, EEP_SWREG);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3867 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3868 REG_READ(ah, AR_RTC_REG_CONTROL1) &
3869 (~AR_RTC_REG_CONTROL1_SWREG_PROGRAM));
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3870 REG_WRITE(ah, AR_RTC_REG_CONTROL0, reg_val);
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3871 /* Set REG_CONTROL1.SWREG_PROGRAM */
3872 REG_WRITE(ah, AR_RTC_REG_CONTROL1,
3873 REG_READ(ah,
3874 AR_RTC_REG_CONTROL1) |
3875 AR_RTC_REG_CONTROL1_SWREG_PROGRAM);
3876 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3877 } else {
Gabor Juhos4187afa2011-06-21 11:23:50 +0200[diff] [blame]3878 if (AR_SREV_9330(ah) || AR_SREV_9485(ah)) {
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3879 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0);
3880 while (REG_READ_FIELD(ah, AR_PHY_PMU2,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3881 AR_PHY_PMU2_PGM))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3882 udelay(10);
3883
3884 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3885 while (!REG_READ_FIELD(ah, AR_PHY_PMU1,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3886 AR_PHY_PMU1_PWD))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3887 udelay(10);
3888 REG_RMW_FIELD(ah, AR_PHY_PMU2, AR_PHY_PMU2_PGM, 0x1);
3889 while (!REG_READ_FIELD(ah, AR_PHY_PMU2,
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3890 AR_PHY_PMU2_PGM))
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3891 udelay(10);
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]3892 } else if (AR_SREV_9462(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]3893 REG_RMW_FIELD(ah, AR_PHY_PMU1, AR_PHY_PMU1_PWD, 0x1);
3894 else {
3895 reg_val = REG_READ(ah, AR_RTC_SLEEP_CLK) |
3896 AR_RTC_FORCE_SWREG_PRD;
3897 REG_WRITE(ah, AR_RTC_SLEEP_CLK, reg_val);
3898 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3899 }
Vasanthakumar Thiagarajanab09b5b2010-12-07 02:20:39 -0800[diff] [blame]3900
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3901}
3902
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame]3903static void ar9003_hw_apply_tuning_caps(struct ath_hw *ah)
3904{
3905 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3906 u8 tuning_caps_param = eep->baseEepHeader.params_for_tuning_caps[0];
3907
3908 if (eep->baseEepHeader.featureEnable & 0x40) {
3909 tuning_caps_param &= 0x7f;
3910 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPINDAC,
3911 tuning_caps_param);
3912 REG_RMW_FIELD(ah, AR_CH0_XTAL, AR_CH0_XTAL_CAPOUTDAC,
3913 tuning_caps_param);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3914 }
3915}
3916
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3917static void ar9003_hw_quick_drop_apply(struct ath_hw *ah, u16 freq)
3918{
3919 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3920 int quick_drop = ath9k_hw_ar9300_get_eeprom(ah, EEP_QUICK_DROP);
3921 s32 t[3], f[3] = {5180, 5500, 5785};
3922
3923 if (!quick_drop)
3924 return;
3925
3926 if (freq < 4000)
3927 quick_drop = eep->modalHeader2G.quick_drop;
3928 else {
3929 t[0] = eep->base_ext1.quick_drop_low;
3930 t[1] = eep->modalHeader5G.quick_drop;
3931 t[2] = eep->base_ext1.quick_drop_high;
3932 quick_drop = ar9003_hw_power_interpolate(freq, f, t, 3);
3933 }
3934 REG_RMW_FIELD(ah, AR_PHY_AGC, AR_PHY_AGC_QUICK_DROP, quick_drop);
3935}
3936
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]3937static void ar9003_hw_txend_to_xpa_off_apply(struct ath_hw *ah, u16 freq)
3938{
3939 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
3940 u32 value;
3941
3942 value = (freq < 4000) ? eep->modalHeader2G.txEndToXpaOff :
3943 eep->modalHeader5G.txEndToXpaOff;
3944
3945 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3946 AR_PHY_XPA_TIMING_CTL_TX_END_XPAB_OFF, value);
3947 REG_RMW_FIELD(ah, AR_PHY_XPA_TIMING_CTL,
3948 AR_PHY_XPA_TIMING_CTL_TX_END_XPAA_OFF, value);
3949}
3950
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3951static void ath9k_hw_ar9300_set_board_values(struct ath_hw *ah,
3952 struct ath9k_channel *chan)
3953{
3954 ar9003_hw_xpa_bias_level_apply(ah, IS_CHAN_2GHZ(chan));
3955 ar9003_hw_ant_ctrl_apply(ah, IS_CHAN_2GHZ(chan));
3956 ar9003_hw_drive_strength_apply(ah);
Vasanthakumar Thiagarajanf4475a62010-11-10 05:03:12 -0800[diff] [blame]3957 ar9003_hw_atten_apply(ah, chan);
Rajkumar Manoharandf222ed2011-11-08 14:19:32 +0530[diff] [blame]3958 ar9003_hw_quick_drop_apply(ah, chan->channel);
Gabor Juhos7dc59662011-06-21 11:23:36 +0200[diff] [blame]3959 if (!AR_SREV_9330(ah) && !AR_SREV_9340(ah))
Vasanthakumar Thiagarajan3594bea2011-04-19 19:29:12 +0530[diff] [blame]3960 ar9003_hw_internal_regulator_apply(ah);
Gabor Juhos7d790a212011-06-21 11:23:37 +0200[diff] [blame]3961 if (AR_SREV_9485(ah) || AR_SREV_9330(ah) || AR_SREV_9340(ah))
Vasanthakumar Thiagarajandd040f72010-12-06 04:27:52 -0800[diff] [blame]3962 ar9003_hw_apply_tuning_caps(ah);
Rajkumar Manoharan202bff02011-11-08 14:19:33 +0530[diff] [blame]3963 ar9003_hw_txend_to_xpa_off_apply(ah, chan->channel);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]3964}
3965
3966static void ath9k_hw_ar9300_set_addac(struct ath_hw *ah,
3967 struct ath9k_channel *chan)
3968{
3969}
3970
3971/*
3972 * Returns the interpolated y value corresponding to the specified x value
3973 * from the np ordered pairs of data (px,py).
3974 * The pairs do not have to be in any order.
3975 * If the specified x value is less than any of the px,
3976 * the returned y value is equal to the py for the lowest px.
3977 * If the specified x value is greater than any of the px,
3978 * the returned y value is equal to the py for the highest px.
3979 */
3980static int ar9003_hw_power_interpolate(int32_t x,
3981 int32_t *px, int32_t *py, u_int16_t np)
3982{
3983 int ip = 0;
3984 int lx = 0, ly = 0, lhave = 0;
3985 int hx = 0, hy = 0, hhave = 0;
3986 int dx = 0;
3987 int y = 0;
3988
3989 lhave = 0;
3990 hhave = 0;
3991
3992 /* identify best lower and higher x calibration measurement */
3993 for (ip = 0; ip < np; ip++) {
3994 dx = x - px[ip];
3995
3996 /* this measurement is higher than our desired x */
3997 if (dx <= 0) {
3998 if (!hhave || dx > (x - hx)) {
3999 /* new best higher x measurement */
4000 hx = px[ip];
4001 hy = py[ip];
4002 hhave = 1;
4003 }
4004 }
4005 /* this measurement is lower than our desired x */
4006 if (dx >= 0) {
4007 if (!lhave || dx < (x - lx)) {
4008 /* new best lower x measurement */
4009 lx = px[ip];
4010 ly = py[ip];
4011 lhave = 1;
4012 }
4013 }
4014 }
4015
4016 /* the low x is good */
4017 if (lhave) {
4018 /* so is the high x */
4019 if (hhave) {
4020 /* they're the same, so just pick one */
4021 if (hx == lx)
4022 y = ly;
4023 else /* interpolate */
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4024 y = interpolate(x, lx, hx, ly, hy);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4025 } else /* only low is good, use it */
4026 y = ly;
4027 } else if (hhave) /* only high is good, use it */
4028 y = hy;
4029 else /* nothing is good,this should never happen unless np=0, ???? */
4030 y = -(1 << 30);
4031 return y;
4032}
4033
4034static u8 ar9003_hw_eeprom_get_tgt_pwr(struct ath_hw *ah,
4035 u16 rateIndex, u16 freq, bool is2GHz)
4036{
4037 u16 numPiers, i;
4038 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4039 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4040 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4041 struct cal_tgt_pow_legacy *pEepromTargetPwr;
4042 u8 *pFreqBin;
4043
4044 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]4045 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4046 pEepromTargetPwr = eep->calTargetPower2G;
4047 pFreqBin = eep->calTarget_freqbin_2G;
4048 } else {
4049 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4050 pEepromTargetPwr = eep->calTargetPower5G;
4051 pFreqBin = eep->calTarget_freqbin_5G;
4052 }
4053
4054 /*
4055 * create array of channels and targetpower from
4056 * targetpower piers stored on eeprom
4057 */
4058 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame^]4059 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4060 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4061 }
4062
4063 /* interpolate to get target power for given frequency */
4064 return (u8) ar9003_hw_power_interpolate((s32) freq,
4065 freqArray,
4066 targetPowerArray, numPiers);
4067}
4068
4069static u8 ar9003_hw_eeprom_get_ht20_tgt_pwr(struct ath_hw *ah,
4070 u16 rateIndex,
4071 u16 freq, bool is2GHz)
4072{
4073 u16 numPiers, i;
4074 s32 targetPowerArray[AR9300_NUM_5G_20_TARGET_POWERS];
4075 s32 freqArray[AR9300_NUM_5G_20_TARGET_POWERS];
4076 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4077 struct cal_tgt_pow_ht *pEepromTargetPwr;
4078 u8 *pFreqBin;
4079
4080 if (is2GHz) {
Felix Fietkaud10baf92010-04-26 15:04:38 -0400[diff] [blame]4081 numPiers = AR9300_NUM_2G_20_TARGET_POWERS;
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4082 pEepromTargetPwr = eep->calTargetPower2GHT20;
4083 pFreqBin = eep->calTarget_freqbin_2GHT20;
4084 } else {
4085 numPiers = AR9300_NUM_5G_20_TARGET_POWERS;
4086 pEepromTargetPwr = eep->calTargetPower5GHT20;
4087 pFreqBin = eep->calTarget_freqbin_5GHT20;
4088 }
4089
4090 /*
4091 * create array of channels and targetpower
4092 * from targetpower piers stored on eeprom
4093 */
4094 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame^]4095 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4096 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4097 }
4098
4099 /* interpolate to get target power for given frequency */
4100 return (u8) ar9003_hw_power_interpolate((s32) freq,
4101 freqArray,
4102 targetPowerArray, numPiers);
4103}
4104
4105static u8 ar9003_hw_eeprom_get_ht40_tgt_pwr(struct ath_hw *ah,
4106 u16 rateIndex,
4107 u16 freq, bool is2GHz)
4108{
4109 u16 numPiers, i;
4110 s32 targetPowerArray[AR9300_NUM_5G_40_TARGET_POWERS];
4111 s32 freqArray[AR9300_NUM_5G_40_TARGET_POWERS];
4112 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4113 struct cal_tgt_pow_ht *pEepromTargetPwr;
4114 u8 *pFreqBin;
4115
4116 if (is2GHz) {
4117 numPiers = AR9300_NUM_2G_40_TARGET_POWERS;
4118 pEepromTargetPwr = eep->calTargetPower2GHT40;
4119 pFreqBin = eep->calTarget_freqbin_2GHT40;
4120 } else {
4121 numPiers = AR9300_NUM_5G_40_TARGET_POWERS;
4122 pEepromTargetPwr = eep->calTargetPower5GHT40;
4123 pFreqBin = eep->calTarget_freqbin_5GHT40;
4124 }
4125
4126 /*
4127 * create array of channels and targetpower from
4128 * targetpower piers stored on eeprom
4129 */
4130 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame^]4131 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4132 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4133 }
4134
4135 /* interpolate to get target power for given frequency */
4136 return (u8) ar9003_hw_power_interpolate((s32) freq,
4137 freqArray,
4138 targetPowerArray, numPiers);
4139}
4140
4141static u8 ar9003_hw_eeprom_get_cck_tgt_pwr(struct ath_hw *ah,
4142 u16 rateIndex, u16 freq)
4143{
4144 u16 numPiers = AR9300_NUM_2G_CCK_TARGET_POWERS, i;
4145 s32 targetPowerArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4146 s32 freqArray[AR9300_NUM_2G_CCK_TARGET_POWERS];
4147 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4148 struct cal_tgt_pow_legacy *pEepromTargetPwr = eep->calTargetPowerCck;
4149 u8 *pFreqBin = eep->calTarget_freqbin_Cck;
4150
4151 /*
4152 * create array of channels and targetpower from
4153 * targetpower piers stored on eeprom
4154 */
4155 for (i = 0; i < numPiers; i++) {
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame^]4156 freqArray[i] = ath9k_hw_fbin2freq(pFreqBin[i], 1);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4157 targetPowerArray[i] = pEepromTargetPwr[i].tPow2x[rateIndex];
4158 }
4159
4160 /* interpolate to get target power for given frequency */
4161 return (u8) ar9003_hw_power_interpolate((s32) freq,
4162 freqArray,
4163 targetPowerArray, numPiers);
4164}
4165
4166/* Set tx power registers to array of values passed in */
4167static int ar9003_hw_tx_power_regwrite(struct ath_hw *ah, u8 * pPwrArray)
4168{
4169#define POW_SM(_r, _s) (((_r) & 0x3f) << (_s))
4170 /* make sure forced gain is not set */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4171 REG_WRITE(ah, AR_PHY_TX_FORCED_GAIN, 0);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4172
4173 /* Write the OFDM power per rate set */
4174
4175 /* 6 (LSB), 9, 12, 18 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4176 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(0),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4177 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4178 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 16) |
4179 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4180 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4181
4182 /* 24 (LSB), 36, 48, 54 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4183 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(1),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4184 POW_SM(pPwrArray[ALL_TARGET_LEGACY_54], 24) |
4185 POW_SM(pPwrArray[ALL_TARGET_LEGACY_48], 16) |
4186 POW_SM(pPwrArray[ALL_TARGET_LEGACY_36], 8) |
4187 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 0));
4188
4189 /* Write the CCK power per rate set */
4190
4191 /* 1L (LSB), reserved, 2L, 2S (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4192 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(2),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4193 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 24) |
4194 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4195 /* POW_SM(txPowerTimes2, 8) | this is reserved for AR9003 */
4196 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0));
4197
4198 /* 5.5L (LSB), 5.5S, 11L, 11S (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4199 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(3),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4200 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11S], 24) |
4201 POW_SM(pPwrArray[ALL_TARGET_LEGACY_11L], 16) |
4202 POW_SM(pPwrArray[ALL_TARGET_LEGACY_5S], 8) |
4203 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4204 );
4205
Luis R. Rodriguezcf3a03b2011-05-04 14:01:26 -0700[diff] [blame]4206 /* Write the power for duplicated frames - HT40 */
4207
4208 /* dup40_cck (LSB), dup40_ofdm, ext20_cck, ext20_ofdm (MSB) */
Alex Hacker8d7763b2011-08-03 17:41:54 +0600[diff] [blame]4209 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(8),
Luis R. Rodriguezcf3a03b2011-05-04 14:01:26 -0700[diff] [blame]4210 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 24) |
4211 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 16) |
4212 POW_SM(pPwrArray[ALL_TARGET_LEGACY_6_24], 8) |
4213 POW_SM(pPwrArray[ALL_TARGET_LEGACY_1L_5L], 0)
4214 );
4215
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4216 /* Write the HT20 power per rate set */
4217
4218 /* 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4219 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(4),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4220 POW_SM(pPwrArray[ALL_TARGET_HT20_5], 24) |
4221 POW_SM(pPwrArray[ALL_TARGET_HT20_4], 16) |
4222 POW_SM(pPwrArray[ALL_TARGET_HT20_1_3_9_11_17_19], 8) |
4223 POW_SM(pPwrArray[ALL_TARGET_HT20_0_8_16], 0)
4224 );
4225
4226 /* 6 (LSB), 7, 12, 13 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4227 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(5),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4228 POW_SM(pPwrArray[ALL_TARGET_HT20_13], 24) |
4229 POW_SM(pPwrArray[ALL_TARGET_HT20_12], 16) |
4230 POW_SM(pPwrArray[ALL_TARGET_HT20_7], 8) |
4231 POW_SM(pPwrArray[ALL_TARGET_HT20_6], 0)
4232 );
4233
4234 /* 14 (LSB), 15, 20, 21 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4235 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(9),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4236 POW_SM(pPwrArray[ALL_TARGET_HT20_21], 24) |
4237 POW_SM(pPwrArray[ALL_TARGET_HT20_20], 16) |
4238 POW_SM(pPwrArray[ALL_TARGET_HT20_15], 8) |
4239 POW_SM(pPwrArray[ALL_TARGET_HT20_14], 0)
4240 );
4241
4242 /* Mixed HT20 and HT40 rates */
4243
4244 /* HT20 22 (LSB), HT20 23, HT40 22, HT40 23 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4245 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(10),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4246 POW_SM(pPwrArray[ALL_TARGET_HT40_23], 24) |
4247 POW_SM(pPwrArray[ALL_TARGET_HT40_22], 16) |
4248 POW_SM(pPwrArray[ALL_TARGET_HT20_23], 8) |
4249 POW_SM(pPwrArray[ALL_TARGET_HT20_22], 0)
4250 );
4251
4252 /*
4253 * Write the HT40 power per rate set
4254 * correct PAR difference between HT40 and HT20/LEGACY
4255 * 0/8/16 (LSB), 1-3/9-11/17-19, 4, 5 (MSB)
4256 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4257 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(6),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4258 POW_SM(pPwrArray[ALL_TARGET_HT40_5], 24) |
4259 POW_SM(pPwrArray[ALL_TARGET_HT40_4], 16) |
4260 POW_SM(pPwrArray[ALL_TARGET_HT40_1_3_9_11_17_19], 8) |
4261 POW_SM(pPwrArray[ALL_TARGET_HT40_0_8_16], 0)
4262 );
4263
4264 /* 6 (LSB), 7, 12, 13 (MSB) */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4265 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(7),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4266 POW_SM(pPwrArray[ALL_TARGET_HT40_13], 24) |
4267 POW_SM(pPwrArray[ALL_TARGET_HT40_12], 16) |
4268 POW_SM(pPwrArray[ALL_TARGET_HT40_7], 8) |
4269 POW_SM(pPwrArray[ALL_TARGET_HT40_6], 0)
4270 );
4271
4272 /* 14 (LSB), 15, 20, 21 */
Felix Fietkau4a4fdf22011-01-21 18:46:35 +0100[diff] [blame]4273 REG_WRITE(ah, AR_PHY_POWER_TX_RATE(11),
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4274 POW_SM(pPwrArray[ALL_TARGET_HT40_21], 24) |
4275 POW_SM(pPwrArray[ALL_TARGET_HT40_20], 16) |
4276 POW_SM(pPwrArray[ALL_TARGET_HT40_15], 8) |
4277 POW_SM(pPwrArray[ALL_TARGET_HT40_14], 0)
4278 );
4279
4280 return 0;
4281#undef POW_SM
4282}
4283
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4284static void ar9003_hw_set_target_power_eeprom(struct ath_hw *ah, u16 freq,
4285 u8 *targetPowerValT2)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4286{
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4287 /* XXX: hard code for now, need to get from eeprom struct */
4288 u8 ht40PowerIncForPdadc = 0;
4289 bool is2GHz = false;
4290 unsigned int i = 0;
4291 struct ath_common *common = ath9k_hw_common(ah);
4292
4293 if (freq < 4000)
4294 is2GHz = true;
4295
4296 targetPowerValT2[ALL_TARGET_LEGACY_6_24] =
4297 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_6_24, freq,
4298 is2GHz);
4299 targetPowerValT2[ALL_TARGET_LEGACY_36] =
4300 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_36, freq,
4301 is2GHz);
4302 targetPowerValT2[ALL_TARGET_LEGACY_48] =
4303 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_48, freq,
4304 is2GHz);
4305 targetPowerValT2[ALL_TARGET_LEGACY_54] =
4306 ar9003_hw_eeprom_get_tgt_pwr(ah, LEGACY_TARGET_RATE_54, freq,
4307 is2GHz);
4308 targetPowerValT2[ALL_TARGET_LEGACY_1L_5L] =
4309 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_1L_5L,
4310 freq);
4311 targetPowerValT2[ALL_TARGET_LEGACY_5S] =
4312 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_5S, freq);
4313 targetPowerValT2[ALL_TARGET_LEGACY_11L] =
4314 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11L, freq);
4315 targetPowerValT2[ALL_TARGET_LEGACY_11S] =
4316 ar9003_hw_eeprom_get_cck_tgt_pwr(ah, LEGACY_TARGET_RATE_11S, freq);
4317 targetPowerValT2[ALL_TARGET_HT20_0_8_16] =
4318 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4319 is2GHz);
4320 targetPowerValT2[ALL_TARGET_HT20_1_3_9_11_17_19] =
4321 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4322 freq, is2GHz);
4323 targetPowerValT2[ALL_TARGET_HT20_4] =
4324 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4325 is2GHz);
4326 targetPowerValT2[ALL_TARGET_HT20_5] =
4327 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4328 is2GHz);
4329 targetPowerValT2[ALL_TARGET_HT20_6] =
4330 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4331 is2GHz);
4332 targetPowerValT2[ALL_TARGET_HT20_7] =
4333 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4334 is2GHz);
4335 targetPowerValT2[ALL_TARGET_HT20_12] =
4336 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4337 is2GHz);
4338 targetPowerValT2[ALL_TARGET_HT20_13] =
4339 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4340 is2GHz);
4341 targetPowerValT2[ALL_TARGET_HT20_14] =
4342 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4343 is2GHz);
4344 targetPowerValT2[ALL_TARGET_HT20_15] =
4345 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4346 is2GHz);
4347 targetPowerValT2[ALL_TARGET_HT20_20] =
4348 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4349 is2GHz);
4350 targetPowerValT2[ALL_TARGET_HT20_21] =
4351 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4352 is2GHz);
4353 targetPowerValT2[ALL_TARGET_HT20_22] =
4354 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4355 is2GHz);
4356 targetPowerValT2[ALL_TARGET_HT20_23] =
4357 ar9003_hw_eeprom_get_ht20_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4358 is2GHz);
4359 targetPowerValT2[ALL_TARGET_HT40_0_8_16] =
4360 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_0_8_16, freq,
4361 is2GHz) + ht40PowerIncForPdadc;
4362 targetPowerValT2[ALL_TARGET_HT40_1_3_9_11_17_19] =
4363 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_1_3_9_11_17_19,
4364 freq,
4365 is2GHz) + ht40PowerIncForPdadc;
4366 targetPowerValT2[ALL_TARGET_HT40_4] =
4367 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_4, freq,
4368 is2GHz) + ht40PowerIncForPdadc;
4369 targetPowerValT2[ALL_TARGET_HT40_5] =
4370 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_5, freq,
4371 is2GHz) + ht40PowerIncForPdadc;
4372 targetPowerValT2[ALL_TARGET_HT40_6] =
4373 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_6, freq,
4374 is2GHz) + ht40PowerIncForPdadc;
4375 targetPowerValT2[ALL_TARGET_HT40_7] =
4376 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_7, freq,
4377 is2GHz) + ht40PowerIncForPdadc;
4378 targetPowerValT2[ALL_TARGET_HT40_12] =
4379 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_12, freq,
4380 is2GHz) + ht40PowerIncForPdadc;
4381 targetPowerValT2[ALL_TARGET_HT40_13] =
4382 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_13, freq,
4383 is2GHz) + ht40PowerIncForPdadc;
4384 targetPowerValT2[ALL_TARGET_HT40_14] =
4385 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_14, freq,
4386 is2GHz) + ht40PowerIncForPdadc;
4387 targetPowerValT2[ALL_TARGET_HT40_15] =
4388 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_15, freq,
4389 is2GHz) + ht40PowerIncForPdadc;
4390 targetPowerValT2[ALL_TARGET_HT40_20] =
4391 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_20, freq,
4392 is2GHz) + ht40PowerIncForPdadc;
4393 targetPowerValT2[ALL_TARGET_HT40_21] =
4394 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_21, freq,
4395 is2GHz) + ht40PowerIncForPdadc;
4396 targetPowerValT2[ALL_TARGET_HT40_22] =
4397 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_22, freq,
4398 is2GHz) + ht40PowerIncForPdadc;
4399 targetPowerValT2[ALL_TARGET_HT40_23] =
4400 ar9003_hw_eeprom_get_ht40_tgt_pwr(ah, HT_TARGET_RATE_23, freq,
4401 is2GHz) + ht40PowerIncForPdadc;
4402
Joe Perchesa1cbc7a2010-12-02 19:12:38 -0800[diff] [blame]4403 for (i = 0; i < ar9300RateSize; i++) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4404 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
4405 i, targetPowerValT2[i]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4406 }
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4407}
4408
4409static int ar9003_hw_cal_pier_get(struct ath_hw *ah,
4410 int mode,
4411 int ipier,
4412 int ichain,
4413 int *pfrequency,
4414 int *pcorrection,
4415 int *ptemperature, int *pvoltage)
4416{
4417 u8 *pCalPier;
4418 struct ar9300_cal_data_per_freq_op_loop *pCalPierStruct;
4419 int is2GHz;
4420 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
4421 struct ath_common *common = ath9k_hw_common(ah);
4422
4423 if (ichain >= AR9300_MAX_CHAINS) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4424 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4425 "Invalid chain index, must be less than %d\n",
4426 AR9300_MAX_CHAINS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4427 return -1;
4428 }
4429
4430 if (mode) { /* 5GHz */
4431 if (ipier >= AR9300_NUM_5G_CAL_PIERS) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4432 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4433 "Invalid 5GHz cal pier index, must be less than %d\n",
4434 AR9300_NUM_5G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4435 return -1;
4436 }
4437 pCalPier = &(eep->calFreqPier5G[ipier]);
4438 pCalPierStruct = &(eep->calPierData5G[ichain][ipier]);
4439 is2GHz = 0;
4440 } else {
4441 if (ipier >= AR9300_NUM_2G_CAL_PIERS) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4442 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4443 "Invalid 2GHz cal pier index, must be less than %d\n",
4444 AR9300_NUM_2G_CAL_PIERS);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4445 return -1;
4446 }
4447
4448 pCalPier = &(eep->calFreqPier2G[ipier]);
4449 pCalPierStruct = &(eep->calPierData2G[ichain][ipier]);
4450 is2GHz = 1;
4451 }
4452
Gabor Juhos8edb2542012-04-16 22:46:32 +0200[diff] [blame^]4453 *pfrequency = ath9k_hw_fbin2freq(*pCalPier, is2GHz);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4454 *pcorrection = pCalPierStruct->refPower;
4455 *ptemperature = pCalPierStruct->tempMeas;
4456 *pvoltage = pCalPierStruct->voltMeas;
4457
4458 return 0;
4459}
4460
4461static int ar9003_hw_power_control_override(struct ath_hw *ah,
4462 int frequency,
4463 int *correction,
4464 int *voltage, int *temperature)
4465{
4466 int tempSlope = 0;
4467 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame]4468 int f[3], t[3];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4469
4470 REG_RMW(ah, AR_PHY_TPC_11_B0,
4471 (correction[0] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4472 AR_PHY_TPC_OLPC_GAIN_DELTA);
Vasanthakumar Thiagarajan5f139eb2010-12-06 04:27:53 -0800[diff] [blame]4473 if (ah->caps.tx_chainmask & BIT(1))
4474 REG_RMW(ah, AR_PHY_TPC_11_B1,
4475 (correction[1] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4476 AR_PHY_TPC_OLPC_GAIN_DELTA);
4477 if (ah->caps.tx_chainmask & BIT(2))
4478 REG_RMW(ah, AR_PHY_TPC_11_B2,
4479 (correction[2] << AR_PHY_TPC_OLPC_GAIN_DELTA_S),
4480 AR_PHY_TPC_OLPC_GAIN_DELTA);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4481
4482 /* enable open loop power control on chip */
4483 REG_RMW(ah, AR_PHY_TPC_6_B0,
4484 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4485 AR_PHY_TPC_6_ERROR_EST_MODE);
Vasanthakumar Thiagarajan5f139eb2010-12-06 04:27:53 -0800[diff] [blame]4486 if (ah->caps.tx_chainmask & BIT(1))
4487 REG_RMW(ah, AR_PHY_TPC_6_B1,
4488 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4489 AR_PHY_TPC_6_ERROR_EST_MODE);
4490 if (ah->caps.tx_chainmask & BIT(2))
4491 REG_RMW(ah, AR_PHY_TPC_6_B2,
4492 (3 << AR_PHY_TPC_6_ERROR_EST_MODE_S),
4493 AR_PHY_TPC_6_ERROR_EST_MODE);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4494
4495 /*
4496 * enable temperature compensation
4497 * Need to use register names
4498 */
4499 if (frequency < 4000)
4500 tempSlope = eep->modalHeader2G.tempSlope;
Vasanthakumar Thiagarajan15cbbc42010-11-10 05:03:13 -0800[diff] [blame]4501 else if (eep->base_ext2.tempSlopeLow != 0) {
4502 t[0] = eep->base_ext2.tempSlopeLow;
4503 f[0] = 5180;
4504 t[1] = eep->modalHeader5G.tempSlope;
4505 f[1] = 5500;
4506 t[2] = eep->base_ext2.tempSlopeHigh;
4507 f[2] = 5785;
4508 tempSlope = ar9003_hw_power_interpolate((s32) frequency,
4509 f, t, 3);
4510 } else
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4511 tempSlope = eep->modalHeader5G.tempSlope;
4512
4513 REG_RMW_FIELD(ah, AR_PHY_TPC_19, AR_PHY_TPC_19_ALPHA_THERM, tempSlope);
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]4514
Rajkumar Manoharan423e38e2011-10-13 11:00:44 +0530[diff] [blame]4515 if (AR_SREV_9462_20(ah))
Senthil Balasubramanian2577c6e2011-09-13 22:38:18 +0530[diff] [blame]4516 REG_RMW_FIELD(ah, AR_PHY_TPC_19_B1,
4517 AR_PHY_TPC_19_B1_ALPHA_THERM, tempSlope);
4518
4519
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4520 REG_RMW_FIELD(ah, AR_PHY_TPC_18, AR_PHY_TPC_18_THERM_CAL_VALUE,
4521 temperature[0]);
4522
4523 return 0;
4524}
4525
4526/* Apply the recorded correction values. */
4527static int ar9003_hw_calibration_apply(struct ath_hw *ah, int frequency)
4528{
4529 int ichain, ipier, npier;
4530 int mode;
4531 int lfrequency[AR9300_MAX_CHAINS],
4532 lcorrection[AR9300_MAX_CHAINS],
4533 ltemperature[AR9300_MAX_CHAINS], lvoltage[AR9300_MAX_CHAINS];
4534 int hfrequency[AR9300_MAX_CHAINS],
4535 hcorrection[AR9300_MAX_CHAINS],
4536 htemperature[AR9300_MAX_CHAINS], hvoltage[AR9300_MAX_CHAINS];
4537 int fdiff;
4538 int correction[AR9300_MAX_CHAINS],
4539 voltage[AR9300_MAX_CHAINS], temperature[AR9300_MAX_CHAINS];
4540 int pfrequency, pcorrection, ptemperature, pvoltage;
4541 struct ath_common *common = ath9k_hw_common(ah);
4542
4543 mode = (frequency >= 4000);
4544 if (mode)
4545 npier = AR9300_NUM_5G_CAL_PIERS;
4546 else
4547 npier = AR9300_NUM_2G_CAL_PIERS;
4548
4549 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4550 lfrequency[ichain] = 0;
4551 hfrequency[ichain] = 100000;
4552 }
4553 /* identify best lower and higher frequency calibration measurement */
4554 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
4555 for (ipier = 0; ipier < npier; ipier++) {
4556 if (!ar9003_hw_cal_pier_get(ah, mode, ipier, ichain,
4557 &pfrequency, &pcorrection,
4558 &ptemperature, &pvoltage)) {
4559 fdiff = frequency - pfrequency;
4560
4561 /*
4562 * this measurement is higher than
4563 * our desired frequency
4564 */
4565 if (fdiff <= 0) {
4566 if (hfrequency[ichain] <= 0 ||
4567 hfrequency[ichain] >= 100000 ||
4568 fdiff >
4569 (frequency - hfrequency[ichain])) {
4570 /*
4571 * new best higher
4572 * frequency measurement
4573 */
4574 hfrequency[ichain] = pfrequency;
4575 hcorrection[ichain] =
4576 pcorrection;
4577 htemperature[ichain] =
4578 ptemperature;
4579 hvoltage[ichain] = pvoltage;
4580 }
4581 }
4582 if (fdiff >= 0) {
4583 if (lfrequency[ichain] <= 0
4584 || fdiff <
4585 (frequency - lfrequency[ichain])) {
4586 /*
4587 * new best lower
4588 * frequency measurement
4589 */
4590 lfrequency[ichain] = pfrequency;
4591 lcorrection[ichain] =
4592 pcorrection;
4593 ltemperature[ichain] =
4594 ptemperature;
4595 lvoltage[ichain] = pvoltage;
4596 }
4597 }
4598 }
4599 }
4600 }
4601
4602 /* interpolate */
4603 for (ichain = 0; ichain < AR9300_MAX_CHAINS; ichain++) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4604 ath_dbg(common, EEPROM, "ch=%d f=%d low=%d %d h=%d %d\n",
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4605 ichain, frequency, lfrequency[ichain],
4606 lcorrection[ichain], hfrequency[ichain],
4607 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4608 /* they're the same, so just pick one */
4609 if (hfrequency[ichain] == lfrequency[ichain]) {
4610 correction[ichain] = lcorrection[ichain];
4611 voltage[ichain] = lvoltage[ichain];
4612 temperature[ichain] = ltemperature[ichain];
4613 }
4614 /* the low frequency is good */
4615 else if (frequency - lfrequency[ichain] < 1000) {
4616 /* so is the high frequency, interpolate */
4617 if (hfrequency[ichain] - frequency < 1000) {
4618
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4619 correction[ichain] = interpolate(frequency,
4620 lfrequency[ichain],
4621 hfrequency[ichain],
4622 lcorrection[ichain],
4623 hcorrection[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4624
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4625 temperature[ichain] = interpolate(frequency,
4626 lfrequency[ichain],
4627 hfrequency[ichain],
4628 ltemperature[ichain],
4629 htemperature[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4630
Vasanthakumar Thiagarajanbc206802010-11-10 05:03:14 -0800[diff] [blame]4631 voltage[ichain] = interpolate(frequency,
4632 lfrequency[ichain],
4633 hfrequency[ichain],
4634 lvoltage[ichain],
4635 hvoltage[ichain]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4636 }
4637 /* only low is good, use it */
4638 else {
4639 correction[ichain] = lcorrection[ichain];
4640 temperature[ichain] = ltemperature[ichain];
4641 voltage[ichain] = lvoltage[ichain];
4642 }
4643 }
4644 /* only high is good, use it */
4645 else if (hfrequency[ichain] - frequency < 1000) {
4646 correction[ichain] = hcorrection[ichain];
4647 temperature[ichain] = htemperature[ichain];
4648 voltage[ichain] = hvoltage[ichain];
4649 } else { /* nothing is good, presume 0???? */
4650 correction[ichain] = 0;
4651 temperature[ichain] = 0;
4652 voltage[ichain] = 0;
4653 }
4654 }
4655
4656 ar9003_hw_power_control_override(ah, frequency, correction, voltage,
4657 temperature);
4658
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4659 ath_dbg(common, EEPROM,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4660 "for frequency=%d, calibration correction = %d %d %d\n",
4661 frequency, correction[0], correction[1], correction[2]);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4662
4663 return 0;
4664}
4665
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4666static u16 ar9003_hw_get_direct_edge_power(struct ar9300_eeprom *eep,
4667 int idx,
4668 int edge,
4669 bool is2GHz)
4670{
4671 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4672 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4673
4674 if (is2GHz)
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4675 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4676 else
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4677 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4678}
4679
4680static u16 ar9003_hw_get_indirect_edge_power(struct ar9300_eeprom *eep,
4681 int idx,
4682 unsigned int edge,
4683 u16 freq,
4684 bool is2GHz)
4685{
4686 struct cal_ctl_data_2g *ctl_2g = eep->ctlPowerData_2G;
4687 struct cal_ctl_data_5g *ctl_5g = eep->ctlPowerData_5G;
4688
4689 u8 *ctl_freqbin = is2GHz ?
4690 &eep->ctl_freqbin_2G[idx][0] :
4691 &eep->ctl_freqbin_5G[idx][0];
4692
4693 if (is2GHz) {
4694 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 1) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4695 CTL_EDGE_FLAGS(ctl_2g[idx].ctlEdges[edge - 1]))
4696 return CTL_EDGE_TPOWER(ctl_2g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4697 } else {
4698 if (ath9k_hw_fbin2freq(ctl_freqbin[edge - 1], 0) < freq &&
Felix Fietkaue702ba12010-12-01 19:07:46 +0100[diff] [blame]4699 CTL_EDGE_FLAGS(ctl_5g[idx].ctlEdges[edge - 1]))
4700 return CTL_EDGE_TPOWER(ctl_5g[idx].ctlEdges[edge - 1]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4701 }
4702
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4703 return MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4704}
4705
4706/*
4707 * Find the maximum conformance test limit for the given channel and CTL info
4708 */
4709static u16 ar9003_hw_get_max_edge_power(struct ar9300_eeprom *eep,
4710 u16 freq, int idx, bool is2GHz)
4711{
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4712 u16 twiceMaxEdgePower = MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4713 u8 *ctl_freqbin = is2GHz ?
4714 &eep->ctl_freqbin_2G[idx][0] :
4715 &eep->ctl_freqbin_5G[idx][0];
4716 u16 num_edges = is2GHz ?
4717 AR9300_NUM_BAND_EDGES_2G : AR9300_NUM_BAND_EDGES_5G;
4718 unsigned int edge;
4719
4720 /* Get the edge power */
4721 for (edge = 0;
Felix Fietkau4ddfcd72010-12-12 00:51:08 +0100[diff] [blame]4722 (edge < num_edges) && (ctl_freqbin[edge] != AR5416_BCHAN_UNUSED);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4723 edge++) {
4724 /*
4725 * If there's an exact channel match or an inband flag set
4726 * on the lower channel use the given rdEdgePower
4727 */
4728 if (freq == ath9k_hw_fbin2freq(ctl_freqbin[edge], is2GHz)) {
4729 twiceMaxEdgePower =
4730 ar9003_hw_get_direct_edge_power(eep, idx,
4731 edge, is2GHz);
4732 break;
4733 } else if ((edge > 0) &&
4734 (freq < ath9k_hw_fbin2freq(ctl_freqbin[edge],
4735 is2GHz))) {
4736 twiceMaxEdgePower =
4737 ar9003_hw_get_indirect_edge_power(eep, idx,
4738 edge, freq,
4739 is2GHz);
4740 /*
4741 * Leave loop - no more affecting edges possible in
4742 * this monotonic increasing list
4743 */
4744 break;
4745 }
4746 }
4747 return twiceMaxEdgePower;
4748}
4749
4750static void ar9003_hw_set_power_per_rate_table(struct ath_hw *ah,
4751 struct ath9k_channel *chan,
4752 u8 *pPwrArray, u16 cfgCtl,
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame]4753 u8 antenna_reduction,
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4754 u16 powerLimit)
4755{
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4756 struct ath_common *common = ath9k_hw_common(ah);
4757 struct ar9300_eeprom *pEepData = &ah->eeprom.ar9300_eep;
Rajkumar Manoharana261f0e2011-11-22 18:52:00 +0530[diff] [blame]4758 u16 twiceMaxEdgePower;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4759 int i;
Felix Fietkauca2c68c2011-10-08 20:06:20 +0200[diff] [blame]4760 u16 scaledPower = 0, minCtlPower;
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4761 static const u16 ctlModesFor11a[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4762 CTL_11A, CTL_5GHT20, CTL_11A_EXT, CTL_5GHT40
4763 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4764 static const u16 ctlModesFor11g[] = {
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4765 CTL_11B, CTL_11G, CTL_2GHT20, CTL_11B_EXT,
4766 CTL_11G_EXT, CTL_2GHT40
4767 };
Joe Perches07b2fa52010-11-20 18:38:53 -0800[diff] [blame]4768 u16 numCtlModes;
4769 const u16 *pCtlMode;
4770 u16 ctlMode, freq;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4771 struct chan_centers centers;
4772 u8 *ctlIndex;
4773 u8 ctlNum;
4774 u16 twiceMinEdgePower;
4775 bool is2ghz = IS_CHAN_2GHZ(chan);
4776
4777 ath9k_hw_get_channel_centers(ah, chan, &centers);
Gabor Juhosea6f7922012-04-14 22:01:58 +0200[diff] [blame]4778 scaledPower = ath9k_hw_get_scaled_power(ah, powerLimit,
4779 antenna_reduction);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4780
4781 /*
4782 * Get target powers from EEPROM - our baseline for TX Power
4783 */
4784 if (is2ghz) {
4785 /* Setup for CTL modes */
4786 /* CTL_11B, CTL_11G, CTL_2GHT20 */
4787 numCtlModes =
4788 ARRAY_SIZE(ctlModesFor11g) -
4789 SUB_NUM_CTL_MODES_AT_2G_40;
4790 pCtlMode = ctlModesFor11g;
4791 if (IS_CHAN_HT40(chan))
4792 /* All 2G CTL's */
4793 numCtlModes = ARRAY_SIZE(ctlModesFor11g);
4794 } else {
4795 /* Setup for CTL modes */
4796 /* CTL_11A, CTL_5GHT20 */
4797 numCtlModes = ARRAY_SIZE(ctlModesFor11a) -
4798 SUB_NUM_CTL_MODES_AT_5G_40;
4799 pCtlMode = ctlModesFor11a;
4800 if (IS_CHAN_HT40(chan))
4801 /* All 5G CTL's */
4802 numCtlModes = ARRAY_SIZE(ctlModesFor11a);
4803 }
4804
4805 /*
4806 * For MIMO, need to apply regulatory caps individually across
4807 * dynamically running modes: CCK, OFDM, HT20, HT40
4808 *
4809 * The outer loop walks through each possible applicable runtime mode.
4810 * The inner loop walks through each ctlIndex entry in EEPROM.
4811 * The ctl value is encoded as [7:4] == test group, [3:0] == test mode.
4812 */
4813 for (ctlMode = 0; ctlMode < numCtlModes; ctlMode++) {
4814 bool isHt40CtlMode = (pCtlMode[ctlMode] == CTL_5GHT40) ||
4815 (pCtlMode[ctlMode] == CTL_2GHT40);
4816 if (isHt40CtlMode)
4817 freq = centers.synth_center;
4818 else if (pCtlMode[ctlMode] & EXT_ADDITIVE)
4819 freq = centers.ext_center;
4820 else
4821 freq = centers.ctl_center;
4822
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4823 ath_dbg(common, REGULATORY,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4824 "LOOP-Mode ctlMode %d < %d, isHt40CtlMode %d, EXT_ADDITIVE %d\n",
4825 ctlMode, numCtlModes, isHt40CtlMode,
4826 (pCtlMode[ctlMode] & EXT_ADDITIVE));
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4827
4828 /* walk through each CTL index stored in EEPROM */
4829 if (is2ghz) {
4830 ctlIndex = pEepData->ctlIndex_2G;
4831 ctlNum = AR9300_NUM_CTLS_2G;
4832 } else {
4833 ctlIndex = pEepData->ctlIndex_5G;
4834 ctlNum = AR9300_NUM_CTLS_5G;
4835 }
4836
Rajkumar Manoharana261f0e2011-11-22 18:52:00 +0530[diff] [blame]4837 twiceMaxEdgePower = MAX_RATE_POWER;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4838 for (i = 0; (i < ctlNum) && ctlIndex[i]; i++) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4839 ath_dbg(common, REGULATORY,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4840 "LOOP-Ctlidx %d: cfgCtl 0x%2.2x pCtlMode 0x%2.2x ctlIndex 0x%2.2x chan %d\n",
4841 i, cfgCtl, pCtlMode[ctlMode], ctlIndex[i],
4842 chan->channel);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4843
4844 /*
4845 * compare test group from regulatory
4846 * channel list with test mode from pCtlMode
4847 * list
4848 */
4849 if ((((cfgCtl & ~CTL_MODE_M) |
4850 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4851 ctlIndex[i]) ||
4852 (((cfgCtl & ~CTL_MODE_M) |
4853 (pCtlMode[ctlMode] & CTL_MODE_M)) ==
4854 ((ctlIndex[i] & CTL_MODE_M) |
4855 SD_NO_CTL))) {
4856 twiceMinEdgePower =
4857 ar9003_hw_get_max_edge_power(pEepData,
4858 freq, i,
4859 is2ghz);
4860
4861 if ((cfgCtl & ~CTL_MODE_M) == SD_NO_CTL)
4862 /*
4863 * Find the minimum of all CTL
4864 * edge powers that apply to
4865 * this channel
4866 */
4867 twiceMaxEdgePower =
4868 min(twiceMaxEdgePower,
4869 twiceMinEdgePower);
4870 else {
4871 /* specific */
4872 twiceMaxEdgePower =
4873 twiceMinEdgePower;
4874 break;
4875 }
4876 }
4877 }
4878
4879 minCtlPower = (u8)min(twiceMaxEdgePower, scaledPower);
4880
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]4881 ath_dbg(common, REGULATORY,
Joe Perches226afe62010-12-02 19:12:37 -0800[diff] [blame]4882 "SEL-Min ctlMode %d pCtlMode %d 2xMaxEdge %d sP %d minCtlPwr %d\n",
4883 ctlMode, pCtlMode[ctlMode], twiceMaxEdgePower,
4884 scaledPower, minCtlPower);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4885
4886 /* Apply ctl mode to correct target power set */
4887 switch (pCtlMode[ctlMode]) {
4888 case CTL_11B:
4889 for (i = ALL_TARGET_LEGACY_1L_5L;
4890 i <= ALL_TARGET_LEGACY_11S; i++)
4891 pPwrArray[i] =
4892 (u8)min((u16)pPwrArray[i],
4893 minCtlPower);
4894 break;
4895 case CTL_11A:
4896 case CTL_11G:
4897 for (i = ALL_TARGET_LEGACY_6_24;
4898 i <= ALL_TARGET_LEGACY_54; i++)
4899 pPwrArray[i] =
4900 (u8)min((u16)pPwrArray[i],
4901 minCtlPower);
4902 break;
4903 case CTL_5GHT20:
4904 case CTL_2GHT20:
4905 for (i = ALL_TARGET_HT20_0_8_16;
4906 i <= ALL_TARGET_HT20_21; i++)
4907 pPwrArray[i] =
4908 (u8)min((u16)pPwrArray[i],
4909 minCtlPower);
4910 pPwrArray[ALL_TARGET_HT20_22] =
4911 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_22],
4912 minCtlPower);
4913 pPwrArray[ALL_TARGET_HT20_23] =
4914 (u8)min((u16)pPwrArray[ALL_TARGET_HT20_23],
4915 minCtlPower);
4916 break;
4917 case CTL_5GHT40:
4918 case CTL_2GHT40:
4919 for (i = ALL_TARGET_HT40_0_8_16;
4920 i <= ALL_TARGET_HT40_23; i++)
4921 pPwrArray[i] =
4922 (u8)min((u16)pPwrArray[i],
4923 minCtlPower);
4924 break;
4925 default:
4926 break;
4927 }
4928 } /* end ctl mode checking */
4929}
4930
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]4931static inline u8 mcsidx_to_tgtpwridx(unsigned int mcs_idx, u8 base_pwridx)
4932{
4933 u8 mod_idx = mcs_idx % 8;
4934
4935 if (mod_idx <= 3)
4936 return mod_idx ? (base_pwridx + 1) : base_pwridx;
4937 else
4938 return base_pwridx + 4 * (mcs_idx / 8) + mod_idx - 2;
4939}
4940
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4941static void ath9k_hw_ar9300_set_txpower(struct ath_hw *ah,
4942 struct ath9k_channel *chan, u16 cfgCtl,
4943 u8 twiceAntennaReduction,
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]4944 u8 powerLimit, bool test)
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]4945{
Felix Fietkau6b7b6cf2010-10-20 02:09:44 +0200[diff] [blame]4946 struct ath_regulatory *regulatory = ath9k_hw_regulatory(ah);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4947 struct ath_common *common = ath9k_hw_common(ah);
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4948 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]4949 struct ar9300_modal_eep_header *modal_hdr;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4950 u8 targetPowerValT2[ar9300RateSize];
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4951 u8 target_power_val_t2_eep[ar9300RateSize];
4952 unsigned int i = 0, paprd_scale_factor = 0;
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]4953 u8 pwr_idx, min_pwridx = 0;
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4954
4955 ar9003_hw_set_target_power_eeprom(ah, chan->channel, targetPowerValT2);
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4956
4957 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
4958 if (IS_CHAN_2GHZ(chan))
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]4959 modal_hdr = &eep->modalHeader2G;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4960 else
Felix Fietkauf1a8abb2010-12-19 00:31:54 +0100[diff] [blame]4961 modal_hdr = &eep->modalHeader5G;
4962
4963 ah->paprd_ratemask =
4964 le32_to_cpu(modal_hdr->papdRateMaskHt20) &
4965 AR9300_PAPRD_RATE_MASK;
4966
4967 ah->paprd_ratemask_ht40 =
4968 le32_to_cpu(modal_hdr->papdRateMaskHt40) &
4969 AR9300_PAPRD_RATE_MASK;
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4970
Vasanthakumar Thiagarajan45ef6a02010-12-15 07:30:53 -0800[diff] [blame]4971 paprd_scale_factor = ar9003_get_paprd_scale_factor(ah, chan);
4972 min_pwridx = IS_CHAN_HT40(chan) ? ALL_TARGET_HT40_0_8_16 :
4973 ALL_TARGET_HT20_0_8_16;
4974
4975 if (!ah->paprd_table_write_done) {
4976 memcpy(target_power_val_t2_eep, targetPowerValT2,
4977 sizeof(targetPowerValT2));
4978 for (i = 0; i < 24; i++) {
4979 pwr_idx = mcsidx_to_tgtpwridx(i, min_pwridx);
4980 if (ah->paprd_ratemask & (1 << i)) {
4981 if (targetPowerValT2[pwr_idx] &&
4982 targetPowerValT2[pwr_idx] ==
4983 target_power_val_t2_eep[pwr_idx])
4984 targetPowerValT2[pwr_idx] -=
4985 paprd_scale_factor;
4986 }
4987 }
4988 }
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4989 memcpy(target_power_val_t2_eep, targetPowerValT2,
4990 sizeof(targetPowerValT2));
4991 }
4992
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4993 ar9003_hw_set_power_per_rate_table(ah, chan,
4994 targetPowerValT2, cfgCtl,
4995 twiceAntennaReduction,
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]4996 powerLimit);
4997
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4998 if (ah->eep_ops->get_eeprom(ah, EEP_PAPRD)) {
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]4999 for (i = 0; i < ar9300RateSize; i++) {
5000 if ((ah->paprd_ratemask & (1 << i)) &&
5001 (abs(targetPowerValT2[i] -
5002 target_power_val_t2_eep[i]) >
5003 paprd_scale_factor)) {
5004 ah->paprd_ratemask &= ~(1 << i);
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]5005 ath_dbg(common, EEPROM,
Vasanthakumar Thiagarajan7072bf62010-12-15 07:30:52 -0800[diff] [blame]5006 "paprd disabled for mcs %d\n", i);
5007 }
5008 }
5009 }
5010
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5011 regulatory->max_power_level = 0;
5012 for (i = 0; i < ar9300RateSize; i++) {
5013 if (targetPowerValT2[i] > regulatory->max_power_level)
5014 regulatory->max_power_level = targetPowerValT2[i];
5015 }
5016
Rajkumar Manoharan8915f982011-11-10 15:14:57 +0530[diff] [blame]5017 ath9k_hw_update_regulatory_maxpower(ah);
5018
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5019 if (test)
5020 return;
5021
5022 for (i = 0; i < ar9300RateSize; i++) {
Joe Perchesd2182b62011-12-15 14:55:53 -0800[diff] [blame]5023 ath_dbg(common, EEPROM, "TPC[%02d] 0x%08x\n",
5024 i, targetPowerValT2[i]);
Luis R. Rodriguez824b1852010-08-01 02:25:16 -0400[diff] [blame]5025 }
5026
Felix Fietkaude40f312010-10-20 03:08:53 +0200[diff] [blame]5027 /* Write target power array to registers */
5028 ar9003_hw_tx_power_regwrite(ah, targetPowerValT2);
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5029 ar9003_hw_calibration_apply(ah, chan->channel);
Felix Fietkau1bf38662010-12-13 08:40:54 +0100[diff] [blame]5030
5031 if (IS_CHAN_2GHZ(chan)) {
5032 if (IS_CHAN_HT40(chan))
5033 i = ALL_TARGET_HT40_0_8_16;
5034 else
5035 i = ALL_TARGET_HT20_0_8_16;
5036 } else {
5037 if (IS_CHAN_HT40(chan))
5038 i = ALL_TARGET_HT40_7;
5039 else
5040 i = ALL_TARGET_HT20_7;
5041 }
5042 ah->paprd_target_power = targetPowerValT2[i];
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5043}
5044
5045static u16 ath9k_hw_ar9300_get_spur_channel(struct ath_hw *ah,
5046 u16 i, bool is2GHz)
5047{
5048 return AR_NO_SPUR;
5049}
5050
Luis R. Rodriguezc14a85d2010-04-15 17:39:21 -0400[diff] [blame]5051s32 ar9003_hw_get_tx_gain_idx(struct ath_hw *ah)
5052{
5053 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5054
5055 return (eep->baseEepHeader.txrxgain >> 4) & 0xf; /* bits 7:4 */
5056}
5057
5058s32 ar9003_hw_get_rx_gain_idx(struct ath_hw *ah)
5059{
5060 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5061
5062 return (eep->baseEepHeader.txrxgain) & 0xf; /* bits 3:0 */
5063}
5064
Vasanthakumar Thiagarajan272ceba2010-12-06 04:27:46 -0800[diff] [blame]5065u8 *ar9003_get_spur_chan_ptr(struct ath_hw *ah, bool is_2ghz)
5066{
5067 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5068
5069 if (is_2ghz)
5070 return eep->modalHeader2G.spurChans;
5071 else
5072 return eep->modalHeader5G.spurChans;
5073}
5074
Vasanthakumar Thiagarajan8698bca2010-12-15 07:30:51 -0800[diff] [blame]5075unsigned int ar9003_get_paprd_scale_factor(struct ath_hw *ah,
5076 struct ath9k_channel *chan)
5077{
5078 struct ar9300_eeprom *eep = &ah->eeprom.ar9300_eep;
5079
5080 if (IS_CHAN_2GHZ(chan))
5081 return MS(le32_to_cpu(eep->modalHeader2G.papdRateMaskHt20),
5082 AR9300_PAPRD_SCALE_1);
5083 else {
5084 if (chan->channel >= 5700)
5085 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt20),
5086 AR9300_PAPRD_SCALE_1);
5087 else if (chan->channel >= 5400)
5088 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5089 AR9300_PAPRD_SCALE_2);
5090 else
5091 return MS(le32_to_cpu(eep->modalHeader5G.papdRateMaskHt40),
5092 AR9300_PAPRD_SCALE_1);
5093 }
5094}
5095
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5096const struct eeprom_ops eep_ar9300_ops = {
5097 .check_eeprom = ath9k_hw_ar9300_check_eeprom,
5098 .get_eeprom = ath9k_hw_ar9300_get_eeprom,
5099 .fill_eeprom = ath9k_hw_ar9300_fill_eeprom,
Rajkumar Manoharan26526202011-07-29 17:38:08 +0530[diff] [blame]5100 .dump_eeprom = ath9k_hw_ar9003_dump_eeprom,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5101 .get_eeprom_ver = ath9k_hw_ar9300_get_eeprom_ver,
5102 .get_eeprom_rev = ath9k_hw_ar9300_get_eeprom_rev,
Senthil Balasubramanian15c9ee72010-04-15 17:39:14 -0400[diff] [blame]5103 .set_board_values = ath9k_hw_ar9300_set_board_values,
5104 .set_addac = ath9k_hw_ar9300_set_addac,
5105 .set_txpower = ath9k_hw_ar9300_set_txpower,
5106 .get_spur_channel = ath9k_hw_ar9300_get_spur_channel
5107};